ALD User Manual: Modules

ALD User Manual Version 1.0
Cortex Microcontroller Software Interface Standard
Modules
Here is a list of all modules:
[detail level 1234]
▼ EASTSOFT ES32F3xx ALD | Shanghai Eastsoft Microelectronics Cortex-M Chip Abstraction Layer Driver(ALD)
► ACMP | ACMP module driver
► ACMP Public Functions |
Initialization functions | Initialization and Configuration functions
Interrupt operation functions | ACMP Interrupt operation functions
Output value functions | ACMP Output value functions
ACMP Public Types |
ACMP Public Macros |
ACMP Private Macros |
► ADC | ADC module driver
► ADC Public Functions |
Initialization functions | Initialization and Configuration functions
IO operation functions | Input and Output operation functions
Peripheral Control functions | Peripheral Control functions
Peripheral State functions | Peripheral State functions
ADC Private Functions |
ADC Pubulic Types |
ADC Public Macros |
ADC Private Macros |
► BKPC | BKPC module driver
► BKPC Public Functions |
Peripheral Control functions | Peripheral Control functions
IO operation functions | IO operation functions
BKPC Public Macros |
BKPC Public Types |
BKPC Private Macros |
► CALC | CALC module driver
CALC Public Functions | Accelerating calculate functions
► CAN | CAN module driver
► CAN Public Functions |
Initialization functions | Initialization and Configuration functions
IO operation functions | I/O operation functions
Peripheral Control functions | Peripheral Control functions
Peripheral State and Error functions | CAN Peripheral State functions
CAN Private Functions |
CAN Public Types |
CAN Public Macros |
CAN Private Macros |
► CMU | CMU module driver
CMU Private Variables |
CMU Private Functions |
► CMU Public Functions |
System clock configuration | System clock configuration functions
BUS division control | BUS division control functions
Clock safe configure | Clock safe configure functions
Clock output configure | Clock output configure functions
Peripheral Clock configure | Peripheral clock configure functions
CMU Public Macros |
CMU Public Types |
CMU Private Macros |
► CRC | CRC module driver
► CRC Public Functions |
Initialization functions | Initialization and Configuration functions
Calculate functions | Calculate functions
DMA operation functions | DMA operation functions
Peripheral State and Errors functions | CRC State and Errors functions
CRC Private Functions | CRC Private functions
CRC Public Types |
CRC Public Macros |
CRC Private Macros |
► CRYPT | CRYPT module driver
► CRYPT Public Functions |
Initialization functions | Initialization and Configuration functions
Encrypt or Decrypt functions | Encrypt or Decrypt functions
DMA operation functions | DMA operation functions
Peripheral Control functions | CRYPT control functions
Peripheral State and Errors functions | State and Errors functions
CRYPT Private Functions | CRYPT Private functions
CRYPT Public Types |
CRYPT Public Macros |
CRYPT Private Macros |
► DAC | DAC module driver
DAC Public Functions |
DAC Pubulic Types |
DAC Public Macros |
DAC Private Macros |
► DBGC | DBGC module driver
DBGC Public Types |
DBGC Public Functions |
► DMA | DMA module driver
DMA Private Variables |
DMA Private Functions |
► DMA Public Functions |
Initialization functions | Initialization functions
Configure DMA channel functions | Configure DMA channel functions
DMA Control functions | DMA control functions
DMA Public Macros |
DMA Public Types |
DMA Private Macros |
► EBI | EBI module driver
► EBI Public Functions |
NOR-FLASH SRAM initialize functions | NOR-FLASH SRAM initialize functions
NOR-FLASH SRAM control functions | NOR-FLASH SRAM control functions
NAND-FLASH initialize functions | NAND-FLASH initialize functions
NAND-FLASH control functions | NAND-FLASH control functions
LCD initialize functions | LCD initialize functions
EBI Public Macros |
EBI Public Types |
EBI Private Macros |
► FLASH | FLASH module driver
Flash Private Variables |
Flash Private Functions | Flash Private functions
FLASH Private Macros |
FLASH Private Types |
Flash Public Functions |
► GPIO | GPIO module driver
► GPIO Public Functions |
Initialization functions | Initialization and Configuration functions
IO operation functions | GPIO Read and Write
Control functions | EXTI Control functions
GPIO Public Macros |
GPIO Public Types |
GPIO Private Macros |
► I2C | I2C module driver
► I2C Public functions |
Initialization and de-initialization functions | Initialization and Configuration functions
Input and Output operation functions | Data transfers functions
Peripheral state and Errors functions | Peripheral state and Errors functions
IRQ Handler and Callbacks |
I2C Private Functions |
I2C Public Types |
I2C Public Macros |
I2C Private Macros |
I2C Private Constants |
I2C Private Functions |
► I2S | I2S module driver
► I2S Public Functions |
Initialization functions | Initialization and Configuration functions
IO operation functions | I2S Transmit and Receive functions
Control functions | I2S Control functions
Peripheral State and Errors functions | I2S State and Errors functions
I2S Private Functions | I2S Private functions
I2S Public Types |
I2S Public Macros |
I2S Private Macros |
► IAP | IAP module driver
IAP Public Functions |
IAP Private Macros |
IAP Private Types |
► NAND | NAND driver modules
► NAND Public Functions | NAND Public functions
Initialization functions | NAND Initialization functions
IO operation functions | IO operation functions
NAND Control functions | NAND Control functions
NAND Public Types |
Nand Private Constants |
Nand Private Macros |
► NOR_LCD | NOR_LCD driver modules
NOR_LCD Private Variables |
► NOR_LCD Public Functions | NOR_LCD public functions
Initialization functions | NOR_LCD Initialization functions
I/O operation functions | NOR_LCD I/O operation functions
Control functions | NOR_LCD Control functions
State functions | NOR_LCD State functions
NOR LCD Private Constants |
NOR_LCD Private Macros |
NOR_LCD Public Types |
► NOR_Public_Functions |
NOR_Public_Functions_Group1 |
I/O operation functions | NOR_LCD I/O operation functions
Control functions | NOR_LCD Control functions
State functions | NOR_LCD State functions
► PIS | PIS module driver
► PIS Public Functions |
Initialization functions | Initialization and Configuration functions
Operation functions | PIS output enable or disable functions
Peripheral State and Errors functions | PIS State and Errors functions
modulate output functions | PIS modulate output signal functions
PIS Public Types |
PIS Private Macros |
► PMU | PMU module driver
PMU Private Functions |
► PMU Public Functions |
Low Power Mode | Low power mode select functions
LVD Configure | LVD configure functions
PMU Public Macros |
PMU Public Types |
PMU Private Macros |
► QSPI | QSPI module driver
QSPI Private Functions | QSPI Private functions
► QSPI Public Functions | QSPI Public Functions
Basic execution functions | QSPI basic execution functions
Indirect and stig access execution functions | QSPI indirect and stig access execution functions
Status functions | QSPI status functions
QSPI Public Types |
QSPI Private Macros |
QSPI Public Macros |
► RMU | RMU module driver
RMU Public Functions |
RMU Public Types |
RMU Private Macros |
► RTC | RTC module driver
► RTC Public Functions |
Initialization functions | Initialization functions
Time and Date functions | RTC Time and Date functions
Alarm functions | RTC alarm functions
Time stamp functions | RTC time stamp functions
Tamper functions | RTC tamper functions
Wake-up functions | RTC wake-up functions
Clock output functions | RTC clock output functions
Control functions | RTC control functions
RTC Public Types |
RTC Public Macros |
CAN Private Macros |
RTC Private Functions |
► RTCHW | RTCHW module driver
RTCHW Public Functions |
RTCHW Public Types |
RTCHW Private Macros |
RTCHW Private Functions |
► SPI | SPI module driver
► SPI Public Functions |
Initialization functions | Initialization and Configuration functions
IO fast functions | SPI Transmit and Receive functions
IO operation functions | SPI Transmit and Receive functions
Control functions | SPI Control functions
Peripheral State and Errors functions | SPI State and Errors functions
SPI Private Functions | SPI Private functions
SPI Public Types |
SPI Public Macros |
SPI Private Macros |
► SRAM | SRAM module driver
► SRAM Public Functions |
Initialization functions | Initialization functions
I/O operation functions | I/O operation functions
Control functions | Control functions
State functions | State functions
SRAM Public Types |
► SYSCFG | SYSCFG module driver
SYSCFG Public Macros |
SYSCFG Public Functions |
► TIMER | TIMER module driver
TIMER Private Functions |
► TIMER Public Functions |
TIMER Base functions | Time Base functions
TIMER Output Compare functions | Time Output Compare functions
TIMER PWM functions | TIMER PWM functions
TIMER Input Capture functions | Time Input Capture functions
TIMER One Pulse functions | Time One Pulse functions
TIMER Encoder functions | TIMER Encoder functions
TIMER Hall Sensor functions | TIMER Hall Sensor functions
TIMER complementary output compare functions | TIMER complementary output compare functions
TIMER complementary PWM functions | TIMER complementary PWM functions
TIMER complementary one pulse functions | TIMER complementary one pulse functions
Peripheral Control functions | Peripheral Control functions
Peripheral State functions | Peripheral State functions
TIMER Public Types |
TIMER Public Macros |
TIMER Private Macros |
► TRNG | TRNG module driver
► TRNG Public Functions |
Initialization functions | Initialization functions
Peripheral Control functions | Peripheral Control functions
TRNG Public Types |
TRNG Public Macros |
TRNG Private Macros |
CRYPT Private Functions | CRYPT Private functions
► TSENSE | TSENSE module driver
TSENSE Private Variables |
► TSENSE Public Functions |
Initialization functions | Initialization functions
Peripheral Control functions | Peripheral Control functions
TSENSE Public Macros |
TSENSE Public Types |
TSENSE Private Macros |
► UART | UART module driver
UART Private Functions | UART Private functions
► UART Public Functions |
Initialization and Configuration functions | Initialization and Configuration functions
IO operation functions | UART Transmit and Receive functions
Peripheral Control functions | UART control functions
Peripheral State and Errors functions | UART State and Errors functions
UART Public Macros |
UART Public Types |
UART Private Macros |
► USB | USB module driver
► USB Public Function |
Base functions | Base functions
Device functions | Device functions
Host functions | Host functions
Endpoint functions | Endpoint functions
FIFO functions | FIFO functions
Interrupt functions | Interrupt functions
DMA functions | DMA functions
LPM functions | LPM functions
USB Public Macros |
► WDT | WDT module driver
WWDT Public Functions | Init and configure WWDT function
IWDT Public Functions | Init and configure IWDT function
WDT Public Types |
WDT Private Macros |
► Utils | Utils module driver
Private Constants | ALD Private Constants
Private Variables |
► Public Functions |
Initialization Function | Initialization functions
Control functions | Control functions
Public Types |
Public Macros |
Private Macros |


ALD User Manual: EASTSOFT ES32F3xx ALD

Modules
EASTSOFT ES32F3xx ALD

Shanghai Eastsoft Microelectronics Cortex-M Chip Abstraction Layer Driver(ALD) More...

Collaboration diagram for EASTSOFT ES32F3xx ALD:

Modules

ACMP
ACMP module driver.
ADC
ADC module driver.
BKPC
BKPC module driver.
CALC
CALC module driver.
CAN
CAN module driver.
CMU
CMU module driver.
CRC
CRC module driver.
CRYPT
CRYPT module driver.
DAC
DAC module driver.
DBGC
DBGC module driver.
DMA
DMA module driver.
EBI
EBI module driver.
FLASH
FLASH module driver.
GPIO
GPIO module driver.
I2C
I2C module driver.
I2S
I2S module driver.
IAP
IAP module driver.
NAND
NAND driver modules.
NOR_LCD
NOR_LCD driver modules.
PIS
PIS module driver.
PMU
PMU module driver.
QSPI
QSPI module driver.
RMU
RMU module driver.
RTC
RTC module driver.
RTCHW
RTCHW module driver.
SPI
SPI module driver.
SRAM
SRAM module driver.
SYSCFG
SYSCFG module driver.
TIMER
TIMER module driver.
TRNG
TRNG module driver.
TSENSE
TSENSE module driver.
UART
UART module driver.
USB
USB module driver.
WDT
WDT module driver.
Utils
Utils module driver.

Detailed Description

Shanghai Eastsoft Microelectronics Cortex-M Chip Abstraction Layer Driver(ALD)


ALD User Manual: ACMP

Modules
ACMP
EASTSOFT ES32F3xx ALD

ACMP module driver. More...

Collaboration diagram for ACMP:

Modules

ACMP Public Functions
ACMP Public Types
ACMP Public Macros
ACMP Private Macros

Detailed Description

ACMP module driver.


ALD User Manual: ACMP Public Functions

Modules
ACMP Public Functions
EASTSOFT ES32F3xx ALD » ACMP
Collaboration diagram for ACMP Public Functions:

Modules

Initialization functions
Initialization and Configuration functions.
Interrupt operation functions
ACMP Interrupt operation functions.
Output value functions
ACMP Output value functions.

Detailed Description


ALD User Manual: Initialization functions

Functions
Initialization functions
EASTSOFT ES32F3xx ALD » ACMP » ACMP Public Functions

Initialization and Configuration functions. More...

Collaboration diagram for Initialization functions:

Functions

ald_status_t ald_acmp_init (acmp_handle_t *hperh)
Initializes the ACMP mode according to the specified parameters in the acmp_init_t and create the associated handle. More...

Detailed Description

Initialization and Configuration functions.

Function Documentation

◆ ald_acmp_init()

ald_status_t ald_acmp_init ( acmp_handle_t * hperh )

Initializes the ACMP mode according to the specified parameters in the acmp_init_t and create the associated handle.

Parameters
hperh Pointer to a acmp_handle_t structure that contains the configuration information for the specified ACMP module.
Return values
Status,see ald_status_t.

Definition at line 45 of file ald_acmp.c.

46 {
47 uint32_t tmp = 0;
48
49 assert_param(IS_ACMP_TYPE(hperh->perh));
50 assert_param(IS_ACMP_MODE_TYPE(hperh->init.mode));
51 assert_param(IS_ACMP_WARM_UP_TIME_TYPE(hperh->init.warm_time));
52 assert_param(IS_ACMP_HYSTSEL_TYPE(hperh->init.hystsel));
53 assert_param(IS_ACMP_POS_INPUT_TYPE(hperh->init.p_port));
54 assert_param(IS_ACMP_NEG_INPUT_TYPE(hperh->init.n_port));
55 assert_param(IS_ACMP_INACTVAL_TYPE(hperh->init.inactval));
56 assert_param(IS_FUNC_STATE(hperh->init.out_inv));
57 assert_param(IS_ACMP_EDGE_TYPE(hperh->init.edge));
58 assert_param(hperh->init.vdd_level < 64);
59
60 __LOCK(hperh);
61 tmp = ((hperh->init.mode << ACMP_CON_MODSEL_POSS) | (hperh->init.warm_time << ACMP_CON_WARMUPT_POSS) |
62 (hperh->init.inactval << ACMP_CON_INACTV_POS) | (hperh->init.hystsel << ACMP_CON_HYSTSEL_POSS));
63
64 hperh->perh->CON = tmp;
65
66 tmp |= ((hperh->init.p_port << ACMP_INPUTSEL_PSEL_POSS) | (hperh->init.n_port << ACMP_INPUTSEL_NSEL_POSS) |
67 (hperh->init.vdd_level << ACMP_INPUTSEL_VDDLVL_POSS));
68 hperh->perh->INPUTSEL = tmp;
69
70 if (hperh->init.out_inv)
71 SET_BIT(hperh->perh->CON, ACMP_CON_OUTINV_MSK);
72 else
73 CLEAR_BIT(hperh->perh->CON, ACMP_CON_OUTINV_MSK);
74
75 switch (hperh->init.edge) {
76 case ACMP_EDGE_NONE:
77 CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
78 CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
79 break;
80
81 case ACMP_EDGE_FALL:
82 SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
83 CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
84 break;
85
86 case ACMP_EDGE_RISE:
87 CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
88 SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
89 break;
90
91 case ACMP_EDGE_ALL:
92 SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
93 SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
94 break;
95
96 default:
97 break;
98 }
99
100 SET_BIT(hperh->perh->CON, ACMP_CON_EN_MSK);
101
102 tmp = 0;
103 while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0) {
104 if (tmp++ >= 600000) {
105 __UNLOCK(hperh);
106 return ERROR;
107 }
108 }
109
110 __UNLOCK(hperh);
111 return OK;
112 }
ACMP_EDGE_NONE
Definition: ald_acmp.h:143
acmp_init_t::p_port
acmp_pos_input_t p_port
Definition: ald_acmp.h:164
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
ACMP_EDGE_RISE
Definition: ald_acmp.h:145
IS_ACMP_WARM_UP_TIME_TYPE
#define IS_ACMP_WARM_UP_TIME_TYPE(x)
Definition: ald_acmp.h:231
acmp_init_t::n_port
acmp_neg_input_t n_port
Definition: ald_acmp.h:165
acmp_handle_s::perh
ACMP_TypeDef * perh
Definition: ald_acmp.h:176
IS_ACMP_MODE_TYPE
#define IS_ACMP_MODE_TYPE(x)
Definition: ald_acmp.h:202
IS_ACMP_NEG_INPUT_TYPE
#define IS_ACMP_NEG_INPUT_TYPE(x)
Definition: ald_acmp.h:220
acmp_init_t::mode
acmp_mode_t mode
Definition: ald_acmp.h:161
acmp_init_t::out_inv
type_func_t out_inv
Definition: ald_acmp.h:167
acmp_init_t::hystsel
acmp_hystsel_t hystsel
Definition: ald_acmp.h:163
IS_ACMP_POS_INPUT_TYPE
#define IS_ACMP_POS_INPUT_TYPE(x)
Definition: ald_acmp.h:212
ACMP_EDGE_ALL
Definition: ald_acmp.h:146
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
acmp_handle_s::init
acmp_init_t init
Definition: ald_acmp.h:177
ACMP_EDGE_FALL
Definition: ald_acmp.h:144
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_ACMP_TYPE
#define IS_ACMP_TYPE(x)
Definition: ald_acmp.h:199
IS_ACMP_INACTVAL_TYPE
#define IS_ACMP_INACTVAL_TYPE(x)
Definition: ald_acmp.h:247
IS_ACMP_HYSTSEL_TYPE
#define IS_ACMP_HYSTSEL_TYPE(x)
Definition: ald_acmp.h:239
IS_ACMP_EDGE_TYPE
#define IS_ACMP_EDGE_TYPE(x)
Definition: ald_acmp.h:249
acmp_init_t::edge
acmp_edge_t edge
Definition: ald_acmp.h:168
acmp_init_t::warm_time
acmp_warm_time_t warm_time
Definition: ald_acmp.h:162
acmp_init_t::vdd_level
uint8_t vdd_level
Definition: ald_acmp.h:169
__LOCK
#define __LOCK(x)
Definition: utils.h:92
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
ERROR
Definition: utils.h:56
acmp_init_t::inactval
acmp_inactval_t inactval
Definition: ald_acmp.h:166


ALD User Manual: Interrupt operation functions

Functions
Interrupt operation functions
EASTSOFT ES32F3xx ALD » ACMP » ACMP Public Functions

ACMP Interrupt operation functions. More...

Collaboration diagram for Interrupt operation functions:

Functions

void | ald_acmp_interrupt_config (acmp_handle_t *hperh, acmp_it_t it, type_func_t state)
Enables or disables the specified ACMP interrupts. More...
it_status_t | ald_acmp_get_it_status (acmp_handle_t *hperh, acmp_it_t it)
Checks whether the specified ACMP interrupt has set or not. More...
flag_status_t | ald_acmp_get_flag_status (acmp_handle_t *hperh, acmp_flag_t flag)
Checks whether the specified ACMP interrupt has occurred or not. More...
flag_status_t | ald_acmp_get_mask_flag_status (acmp_handle_t *hperh, acmp_flag_t flag)
Get the status of interrupt flag and interupt source. More...
void | ald_acmp_clear_flag_status (acmp_handle_t *hperh, acmp_flag_t flag)
Clear the specified ACMP it flags. More...

Detailed Description

ACMP Interrupt operation functions.

Function Documentation

◆ ald_acmp_clear_flag_status()

void ald_acmp_clear_flag_status | ( | acmp_handle_t * | hperh,
 |  | acmp_flag_t | flag
 | ) |  |

Clear the specified ACMP it flags.

Parameters
hperh | Pointer to a acmp_handle_t structure that contains the configuration information for the specified ACMP module.
flag | specifies the it flag. This parameter can be one of the acmp_flag_t.
Return values
None

Definition at line 216 of file ald_acmp.c.

217 {
218 assert_param(IS_ACMP_TYPE(hperh->perh));
219 assert_param(IS_ACMP_FLAG_TYPE(flag));
220
221 hperh->perh->IFC = flag;
222 return;
223 }
assert_param
#define assert_param(x)
Definition: type.h:88
acmp_handle_s::perh
ACMP_TypeDef * perh
Definition: ald_acmp.h:176
IS_ACMP_FLAG_TYPE
#define IS_ACMP_FLAG_TYPE(x)
Definition: ald_acmp.h:208
IS_ACMP_TYPE
#define IS_ACMP_TYPE(x)
Definition: ald_acmp.h:199

◆ ald_acmp_get_flag_status()

flag_status_t ald_acmp_get_flag_status | ( | acmp_handle_t * | hperh,
 |  | acmp_flag_t | flag
 | ) |  |

Checks whether the specified ACMP interrupt has occurred or not.

Parameters
hperh | Pointer to a acmp_handle_t structure that contains the configuration information for the specified ACMP module.
flag | Specifies the ACMP interrupt source to check. This parameter can be one of the acmp_flag_t.
Return values
flag_status_t
  • SET
  • RESET

Definition at line 178 of file ald_acmp.c.

179 {
180 assert_param(IS_ACMP_TYPE(hperh->perh));
181 assert_param(IS_ACMP_FLAG_TYPE(flag));
182
183 if (hperh->perh->RIF & flag)
184 return SET;
185
186 return RESET;
187 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
acmp_handle_s::perh
ACMP_TypeDef * perh
Definition: ald_acmp.h:176
RESET
Definition: type.h:38
IS_ACMP_FLAG_TYPE
#define IS_ACMP_FLAG_TYPE(x)
Definition: ald_acmp.h:208
IS_ACMP_TYPE
#define IS_ACMP_TYPE(x)
Definition: ald_acmp.h:199

◆ ald_acmp_get_it_status()

it_status_t ald_acmp_get_it_status | ( | acmp_handle_t * | hperh,
 |  | acmp_it_t | it
 | ) |  |

Checks whether the specified ACMP interrupt has set or not.

Parameters
hperh | Pointer to a acmp_handle_t structure that contains the configuration information for the specified ACMP module.
it | Specifies the ACMP interrupt sources to be enabled or disabled. This parameter can be one of the acmp_it_t.
Return values
it_status_t
  • SET
  • RESET

Definition at line 157 of file ald_acmp.c.

158 {
159 assert_param(IS_ACMP_TYPE(hperh->perh));
160 assert_param(IS_ACMP_IT_TYPE(it));
161
162 if (hperh->perh->IEV & it)
163 return SET;
164
165 return RESET;
166 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_ACMP_IT_TYPE
#define IS_ACMP_IT_TYPE(x)
Definition: ald_acmp.h:206
SET
Definition: type.h:39
acmp_handle_s::perh
ACMP_TypeDef * perh
Definition: ald_acmp.h:176
RESET
Definition: type.h:38
IS_ACMP_TYPE
#define IS_ACMP_TYPE(x)
Definition: ald_acmp.h:199

◆ ald_acmp_get_mask_flag_status()

flag_status_t ald_acmp_get_mask_flag_status | ( | acmp_handle_t * | hperh,
 |  | acmp_flag_t | flag
 | ) |  |

Get the status of interrupt flag and interupt source.

Parameters
hperh | Pointer to a acmp_handle_t structure that contains the configuration information for the specified ACMP.
flag | Specifies the ACMP interrupt flag.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 198 of file ald_acmp.c.

199 {
200 assert_param(IS_ACMP_TYPE(hperh->perh));
201 assert_param(IS_ACMP_FLAG_TYPE(flag));
202
203 if (hperh->perh->IFM & flag)
204 return SET;
205
206 return RESET;
207 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
acmp_handle_s::perh
ACMP_TypeDef * perh
Definition: ald_acmp.h:176
RESET
Definition: type.h:38
IS_ACMP_FLAG_TYPE
#define IS_ACMP_FLAG_TYPE(x)
Definition: ald_acmp.h:208
IS_ACMP_TYPE
#define IS_ACMP_TYPE(x)
Definition: ald_acmp.h:199

◆ ald_acmp_interrupt_config()

void ald_acmp_interrupt_config | ( | acmp_handle_t * | hperh,
 |  | acmp_it_t | it,
 |  | type_func_t | state
 | ) |  |

Enables or disables the specified ACMP interrupts.

Parameters
hperh | Pointer to a acmp_handle_t structure that contains the configuration information for the specified ACMP module.
it | Specifies the ACMP interrupt sources to be enabled or disabled. This parameter can be one of the acmp_it_t.
state New status
  • ENABLE
  • DISABLE
Return values
None

Definition at line 133 of file ald_acmp.c.

134 {
135 assert_param(IS_ACMP_TYPE(hperh->perh));
136 assert_param(IS_ACMP_IT_TYPE(it));
137 assert_param(IS_FUNC_STATE(state));
138
139 if (state)
140 hperh->perh->IES = it;
141 else
142 hperh->perh->IEC = it;
143
144 return;
145 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_ACMP_IT_TYPE
#define IS_ACMP_IT_TYPE(x)
Definition: ald_acmp.h:206
acmp_handle_s::perh
ACMP_TypeDef * perh
Definition: ald_acmp.h:176
IS_ACMP_TYPE
#define IS_ACMP_TYPE(x)
Definition: ald_acmp.h:199
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73


ALD User Manual: Output value functions

Functions
Output value functions
EASTSOFT ES32F3xx ALD » ACMP » ACMP Public Functions

ACMP Output value functions. More...

Collaboration diagram for Output value functions:

Functions

void | ald_acmp_irq_handler (acmp_handle_t *hperh)
This function handles ACMP interrupt request. More...
void | ald_acmp_out_config (acmp_handle_t *hperh, type_func_t state)
This function config acmp output. More...
uint8_t | ald_acmp_out_result (acmp_handle_t *hperh)
This function output acmp result. More...
flag_status_t | ald_acmp_get_status (acmp_handle_t *hperh, acmp_status_t status)
Check whether the specified ACMP flag is set or not. More...

Detailed Description

ACMP Output value functions.

Function Documentation

◆ ald_acmp_get_status()

flag_status_t ald_acmp_get_status | ( | acmp_handle_t * | hperh,
 |  | acmp_status_t | status
 | ) |  |

Check whether the specified ACMP flag is set or not.

Parameters
hperh | Pointer to a acmp_handle_t structure that contains the configuration information for the specified ACMP module.
status | specifies the status to check. This parameter can be one of the acmp_status_t.
Return values
flag_status_t
  • SET
  • RESET

Definition at line 298 of file ald_acmp.c.

299 {
300 assert_param(IS_ACMP_TYPE(hperh->perh));
301 assert_param(IS_ACMP_STATUS_TYPE(status));
302
303 if (hperh->perh->STAT & status)
304 return SET;
305
306 return RESET;
307 }
IS_ACMP_STATUS_TYPE
#define IS_ACMP_STATUS_TYPE(x)
Definition: ald_acmp.h:210
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
acmp_handle_s::perh
ACMP_TypeDef * perh
Definition: ald_acmp.h:176
RESET
Definition: type.h:38
IS_ACMP_TYPE
#define IS_ACMP_TYPE(x)
Definition: ald_acmp.h:199

◆ ald_acmp_irq_handler()

void ald_acmp_irq_handler ( acmp_handle_t * hperh )

This function handles ACMP interrupt request.

Parameters
hperh Pointer to a acmp_handle_t structure that contains the configuration information for the specified ACMP module.
Return values
None

Definition at line 237 of file ald_acmp.c.

238 {
239 if ((ald_acmp_get_mask_flag_status(hperh, ACMP_FLAG_WARMUP)) == SET) {
240 ald_acmp_clear_flag_status(hperh, ACMP_FLAG_WARMUP);
241
242 if (hperh->acmp_warmup_cplt_cbk)
243 hperh->acmp_warmup_cplt_cbk(hperh);
244 }
245
246 if ((ald_acmp_get_mask_flag_status(hperh, ACMP_FLAG_EDGE)) == SET) {
247 ald_acmp_clear_flag_status(hperh, ACMP_FLAG_EDGE);
248
249 if (hperh->acmp_edge_cplt_cbk)
250 hperh->acmp_edge_cplt_cbk(hperh);
251 }
252
253 return;
254 }
SET
Definition: type.h:39
ald_acmp_clear_flag_status
void ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
Clear the specified ACMP it flags.
Definition: ald_acmp.c:216
ald_acmp_get_mask_flag_status
flag_status_t ald_acmp_get_mask_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
Get the status of interrupt flag and interupt source.
Definition: ald_acmp.c:198
ACMP_FLAG_WARMUP
Definition: ald_acmp.h:51
acmp_handle_s::acmp_warmup_cplt_cbk
void(* acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg)
Definition: ald_acmp.h:180
acmp_handle_s::acmp_edge_cplt_cbk
void(* acmp_edge_cplt_cbk)(struct acmp_handle_s *arg)
Definition: ald_acmp.h:181
ACMP_FLAG_EDGE
Definition: ald_acmp.h:50

◆ ald_acmp_out_config()

void ald_acmp_out_config | ( | acmp_handle_t * | hperh,
 |  | type_func_t | state
 | ) |  |

This function config acmp output.

Parameters
hperh | Pointer to a acmp_handle_t structure that contains the configuration information for the specified ACMP module.
state | ENABLE/DISABLE.
Return values
None

Definition at line 263 of file ald_acmp.c.

264 {
265 assert_param(IS_ACMP_TYPE(hperh->perh));
266 assert_param(IS_FUNC_STATE(state));
267
268 if (state)
269 SET_BIT(hperh->perh->PORT, ACMP_PORT_PEN_MSK);
270 else
271 CLEAR_BIT(hperh->perh->PORT, ACMP_PORT_PEN_MSK);
272
273 return;
274 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
acmp_handle_s::perh
ACMP_TypeDef * perh
Definition: ald_acmp.h:176
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_ACMP_TYPE
#define IS_ACMP_TYPE(x)
Definition: ald_acmp.h:199
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_acmp_out_result()

uint8_t ald_acmp_out_result ( acmp_handle_t * hperh )

This function output acmp result.

Parameters
hperh Pointer to a acmp_handle_t structure that contains the configuration information for the specified ACMP module.
Return values
output value.

Definition at line 282 of file ald_acmp.c.

283 {
284 assert_param(IS_ACMP_TYPE(hperh->perh));
285
286 return (READ_BIT(hperh->perh->STAT, ACMP_STAT_OUT_MSK) >> ACMP_STAT_OUT_POS);
287 }
assert_param
#define assert_param(x)
Definition: type.h:88
acmp_handle_s::perh
ACMP_TypeDef * perh
Definition: ald_acmp.h:176
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
IS_ACMP_TYPE
#define IS_ACMP_TYPE(x)
Definition: ald_acmp.h:199


ALD User Manual: ACMP Public Types

Data Structures | Typedefs | Enumerations
ACMP Public Types
EASTSOFT ES32F3xx ALD » ACMP
Collaboration diagram for ACMP Public Types:

Data Structures

struct | acmp_init_t
ACMP init structure definition. More...
struct | acmp_handle_s
ACMP Handle Structure definition. More...

Typedefs

typedef struct acmp_handle_s acmp_handle_t
ACMP Handle Structure definition. More...

Enumerations

enum | acmp_it_t { ACMP_IT_EDGE = (1U << 0), ACMP_IT_WARMUP = (1U << 1) }
ACMP interrupt. More...
enum | acmp_flag_t { ACMP_FLAG_EDGE = (1U << 0), ACMP_FLAG_WARMUP = (1U << 1) }
ACMP interrupt flag. More...
enum | acmp_status_t { ACMP_STATUS_ACT = (1U << 0), ACMP_STATUS_OUT = (1U << 1) }
ACMP status flag. More...
enum acmp_pos_input_t {
ACMP_POS_CH0 = 0x0U, ACMP_POS_CH1 = 0x1U, ACMP_POS_CH2 = 0x2U, ACMP_POS_CH3 = 0x3U,
ACMP_POS_CH4 = 0x4U, ACMP_POS_CH5 = 0x5U, ACMP_POS_CH6 = 0x6U, ACMP_POS_CH7 = 0x7U
}
ACMP positive input. More...
enum acmp_neg_input_t {
ACMP_NEG_CH0 = 0x0U, ACMP_NEG_CH1 = 0x1U, ACMP_NEG_CH2 = 0x2U, ACMP_NEG_CH3 = 0x3U,
ACMP_NEG_CH4 = 0x4U, ACMP_NEG_CH5 = 0x5U, ACMP_NEG_CH6 = 0x6U, ACMP_NEG_CH7 = 0x7U,
ACMP_NEG_1V25 = 0x8U, ACMP_NEG_2V5 = 0x9U, ACMP_NEG_VDD = 0xAU
}
ACMP negative input. More...
enum | acmp_mode_t { ACMP_ULTRA_LOW_POWER = 0x0U, ACMP_LOW_POWER = 0x1U, ACMP_MIDDLE_POWER = 0x2U, ACMP_HIGH_POWER = 0x3U }
ACMP mode. More...
enum acmp_warm_time_t {
ACMP_4_PCLK = 0x0U, ACMP_8_PCLK = 0x1U, ACMP_16_PCLK = 0x2U, ACMP_32_PCLK = 0x3U,
ACMP_64_PCLK = 0x4U, ACMP_128_PCLK = 0x5U, ACMP_256_PCLK = 0x6U, ACMP_512_PCLK = 0x7U
}
ACMP warm-up time. More...
enum acmp_hystsel_t {
ACMP_HYST_0 = 0x0U, ACMP_HYST_15 = 0x1U, ACMP_HYST_22 = 0x2U, ACMP_HYST_29 = 0x3U,
ACMP_HYST_36 = 0x4U, ACMP_HYST_43 = 0x5U, ACMP_HYST_50 = 0x6U, ACMP_HYST_57 = 0x7U
}
ACMP hysteresis level. More...
enum | acmp_inactval_t { ACMP_INACTVAL_LOW = 0x0U, ACMP_INACTVAL_HIGH = 0x1U }
ACMP inactive state. More...
enum | acmp_edge_t { ACMP_EDGE_NONE = 0x0U, ACMP_EDGE_FALL = 0x1U, ACMP_EDGE_RISE = 0x2U, ACMP_EDGE_ALL = 0x3U }
which edges set up interrupt More...
enum | acmp_out_func_t { ACMP_OUT_DISABLE = 0x0U, ACMP_OUT_ENABLE = 0x1U }
ACMP output function. More...

Detailed Description

Typedef Documentation

◆ acmp_handle_t

typedef struct acmp_handle_s acmp_handle_t

ACMP Handle Structure definition.

Enumeration Type Documentation

◆ acmp_edge_t

enum acmp_edge_t

which edges set up interrupt

Enumerator
ACMP_EDGE_NONE | Disable EDGE interrupt
ACMP_EDGE_FALL | Falling edges set EDGE interrupt
ACMP_EDGE_RISE | rise edges set EDGE interrupt
ACMP_EDGE_ALL | Falling edges and rise edges set EDGE interrupt

Definition at line 142 of file ald_acmp.h.

142 {
143 ACMP_EDGE_NONE = 0x0U,
144 ACMP_EDGE_FALL = 0x1U,
145 ACMP_EDGE_RISE = 0x2U,
146 ACMP_EDGE_ALL = 0x3U,
147 } acmp_edge_t;
ACMP_EDGE_NONE
Definition: ald_acmp.h:143
ACMP_EDGE_RISE
Definition: ald_acmp.h:145
ACMP_EDGE_ALL
Definition: ald_acmp.h:146
acmp_edge_t
acmp_edge_t
which edges set up interrupt
Definition: ald_acmp.h:142
ACMP_EDGE_FALL
Definition: ald_acmp.h:144

◆ acmp_flag_t

enum acmp_flag_t

ACMP interrupt flag.

Enumerator
ACMP_FLAG_EDGE | Edge interrupt flag
ACMP_FLAG_WARMUP | Warm up interrupt flag

Definition at line 49 of file ald_acmp.h.

49 {
50 ACMP_FLAG_EDGE = (1U << 0),
51 ACMP_FLAG_WARMUP = (1U << 1),
52 } acmp_flag_t;
acmp_flag_t
acmp_flag_t
ACMP interrupt flag.
Definition: ald_acmp.h:49
ACMP_FLAG_WARMUP
Definition: ald_acmp.h:51
ACMP_FLAG_EDGE
Definition: ald_acmp.h:50

◆ acmp_hystsel_t

enum acmp_hystsel_t

ACMP hysteresis level.

Enumerator
ACMP_HYST_0 | No hysteresis
ACMP_HYST_15 | 15mV hysteresis
ACMP_HYST_22 | 22mV hysteresis
ACMP_HYST_29 | 29mV hysteresis
ACMP_HYST_36 | 36mV hysteresis
ACMP_HYST_43 | 43mV hysteresis
ACMP_HYST_50 | 50mV hysteresis
ACMP_HYST_57 | 57mV hysteresis

Definition at line 120 of file ald_acmp.h.

120 {
121 ACMP_HYST_0 = 0x0U,
122 ACMP_HYST_15 = 0x1U,
123 ACMP_HYST_22 = 0x2U,
124 ACMP_HYST_29 = 0x3U,
125 ACMP_HYST_36 = 0x4U,
126 ACMP_HYST_43 = 0x5U,
127 ACMP_HYST_50 = 0x6U,
128 ACMP_HYST_57 = 0x7U,
129 } acmp_hystsel_t;
ACMP_HYST_0
Definition: ald_acmp.h:121
ACMP_HYST_15
Definition: ald_acmp.h:122
ACMP_HYST_50
Definition: ald_acmp.h:127
ACMP_HYST_22
Definition: ald_acmp.h:123
ACMP_HYST_29
Definition: ald_acmp.h:124
ACMP_HYST_36
Definition: ald_acmp.h:125
ACMP_HYST_43
Definition: ald_acmp.h:126
acmp_hystsel_t
acmp_hystsel_t
ACMP hysteresis level.
Definition: ald_acmp.h:120
ACMP_HYST_57
Definition: ald_acmp.h:128

◆ acmp_inactval_t

enum acmp_inactval_t

ACMP inactive state.

Enumerator
ACMP_INACTVAL_LOW | The inactive value is 0
ACMP_INACTVAL_HIGH | The inactive value is 1

Definition at line 134 of file ald_acmp.h.

134 {
135 ACMP_INACTVAL_LOW = 0x0U,
136 ACMP_INACTVAL_HIGH = 0x1U,
137 } acmp_inactval_t;
ACMP_INACTVAL_HIGH
Definition: ald_acmp.h:136
ACMP_INACTVAL_LOW
Definition: ald_acmp.h:135
acmp_inactval_t
acmp_inactval_t
ACMP inactive state.
Definition: ald_acmp.h:134

◆ acmp_it_t

enum acmp_it_t

ACMP interrupt.

Enumerator
ACMP_IT_EDGE | Edge interrupt bit
ACMP_IT_WARMUP | Warm up interrupt bit

Definition at line 41 of file ald_acmp.h.

41 {
42 ACMP_IT_EDGE = (1U << 0),
43 ACMP_IT_WARMUP = (1U << 1),
44 } acmp_it_t;
acmp_it_t
acmp_it_t
ACMP interrupt.
Definition: ald_acmp.h:41
ACMP_IT_EDGE
Definition: ald_acmp.h:42
ACMP_IT_WARMUP
Definition: ald_acmp.h:43

◆ acmp_mode_t

enum acmp_mode_t

ACMP mode.

Enumerator
ACMP_ULTRA_LOW_POWER | Ultra low power mode
ACMP_LOW_POWER | Low power mode
ACMP_MIDDLE_POWER | Middle power mode
ACMP_HIGH_POWER | High power mode

Definition at line 96 of file ald_acmp.h.

96 {
97 ACMP_ULTRA_LOW_POWER = 0x0U,
98 ACMP_LOW_POWER = 0x1U,
99 ACMP_MIDDLE_POWER = 0x2U,
100 ACMP_HIGH_POWER = 0x3U,
101 } acmp_mode_t;
ACMP_MIDDLE_POWER
Definition: ald_acmp.h:99
ACMP_LOW_POWER
Definition: ald_acmp.h:98
acmp_mode_t
acmp_mode_t
ACMP mode.
Definition: ald_acmp.h:96
ACMP_ULTRA_LOW_POWER
Definition: ald_acmp.h:97
ACMP_HIGH_POWER
Definition: ald_acmp.h:100

◆ acmp_neg_input_t

enum acmp_neg_input_t

ACMP negative input.

Enumerator
ACMP_NEG_CH0 | Channel 0 as negative input
ACMP_NEG_CH1 | Channel 1 as negative input
ACMP_NEG_CH2 | Channel 2 as negative input
ACMP_NEG_CH3 | Channel 3 as negative input
ACMP_NEG_CH4 | Channel 4 as negative input
ACMP_NEG_CH5 | Channel 5 as negative input
ACMP_NEG_CH6 | Channel 6 as negative input
ACMP_NEG_CH7 | Channel 7 as negative input
ACMP_NEG_1V25 | 1.25v as negative input
ACMP_NEG_2V5 | 2.5v as negative input
ACMP_NEG_VDD | VDD as negative input

Definition at line 79 of file ald_acmp.h.

79 {
80 ACMP_NEG_CH0 = 0x0U,
81 ACMP_NEG_CH1 = 0x1U,
82 ACMP_NEG_CH2 = 0x2U,
83 ACMP_NEG_CH3 = 0x3U,
84 ACMP_NEG_CH4 = 0x4U,
85 ACMP_NEG_CH5 = 0x5U,
86 ACMP_NEG_CH6 = 0x6U,
87 ACMP_NEG_CH7 = 0x7U,
88 ACMP_NEG_1V25 = 0x8U,
89 ACMP_NEG_2V5 = 0x9U,
90 ACMP_NEG_VDD = 0xAU,
91 } acmp_neg_input_t;
ACMP_NEG_1V25
Definition: ald_acmp.h:88
ACMP_NEG_CH0
Definition: ald_acmp.h:80
ACMP_NEG_CH2
Definition: ald_acmp.h:82
ACMP_NEG_CH4
Definition: ald_acmp.h:84
ACMP_NEG_2V5
Definition: ald_acmp.h:89
ACMP_NEG_CH7
Definition: ald_acmp.h:87
acmp_neg_input_t
acmp_neg_input_t
ACMP negative input.
Definition: ald_acmp.h:79
ACMP_NEG_CH5
Definition: ald_acmp.h:85
ACMP_NEG_VDD
Definition: ald_acmp.h:90
ACMP_NEG_CH3
Definition: ald_acmp.h:83
ACMP_NEG_CH6
Definition: ald_acmp.h:86
ACMP_NEG_CH1
Definition: ald_acmp.h:81

◆ acmp_out_func_t

enum acmp_out_func_t

ACMP output function.

Enumerator
ACMP_OUT_DISABLE | Disable acmp output
ACMP_OUT_ENABLE | Enable acmp output

Definition at line 152 of file ald_acmp.h.

152 {
153 ACMP_OUT_DISABLE = 0x0U,
154 ACMP_OUT_ENABLE = 0x1U,
155 } acmp_out_func_t;
ACMP_OUT_ENABLE
Definition: ald_acmp.h:154
acmp_out_func_t
acmp_out_func_t
ACMP output function.
Definition: ald_acmp.h:152
ACMP_OUT_DISABLE
Definition: ald_acmp.h:153

◆ acmp_pos_input_t

enum acmp_pos_input_t

ACMP positive input.

Enumerator
ACMP_POS_CH0 | Channel 0 as positive input
ACMP_POS_CH1 | Channel 1 as positive input
ACMP_POS_CH2 | Channel 2 as positive input
ACMP_POS_CH3 | Channel 3 as positive input
ACMP_POS_CH4 | Channel 4 as positive input
ACMP_POS_CH5 | Channel 5 as positive input
ACMP_POS_CH6 | Channel 6 as positive input
ACMP_POS_CH7 | Channel 7 as positive input

Definition at line 65 of file ald_acmp.h.

65 {
66 ACMP_POS_CH0 = 0x0U,
67 ACMP_POS_CH1 = 0x1U,
68 ACMP_POS_CH2 = 0x2U,
69 ACMP_POS_CH3 = 0x3U,
70 ACMP_POS_CH4 = 0x4U,
71 ACMP_POS_CH5 = 0x5U,
72 ACMP_POS_CH6 = 0x6U,
73 ACMP_POS_CH7 = 0x7U,
74 } acmp_pos_input_t;
ACMP_POS_CH3
Definition: ald_acmp.h:69
ACMP_POS_CH4
Definition: ald_acmp.h:70
ACMP_POS_CH2
Definition: ald_acmp.h:68
ACMP_POS_CH0
Definition: ald_acmp.h:66
ACMP_POS_CH1
Definition: ald_acmp.h:67
ACMP_POS_CH5
Definition: ald_acmp.h:71
ACMP_POS_CH6
Definition: ald_acmp.h:72
acmp_pos_input_t
acmp_pos_input_t
ACMP positive input.
Definition: ald_acmp.h:65
ACMP_POS_CH7
Definition: ald_acmp.h:73

◆ acmp_status_t

enum acmp_status_t

ACMP status flag.

Enumerator
ACMP_STATUS_ACT | Edge status flag
ACMP_STATUS_OUT | Warm up status flag

Definition at line 57 of file ald_acmp.h.

57 {
58 ACMP_STATUS_ACT = (1U << 0),
59 ACMP_STATUS_OUT = (1U << 1),
60 } acmp_status_t;
ACMP_STATUS_ACT
Definition: ald_acmp.h:58
ACMP_STATUS_OUT
Definition: ald_acmp.h:59
acmp_status_t
acmp_status_t
ACMP status flag.
Definition: ald_acmp.h:57

◆ acmp_warm_time_t

enum acmp_warm_time_t

ACMP warm-up time.

Enumerator
ACMP_4_PCLK | 4 hfperclk cycles
ACMP_8_PCLK | 4 hfperclk cycles
ACMP_16_PCLK | 4 hfperclk cycles
ACMP_32_PCLK | 4 hfperclk cycles
ACMP_64_PCLK | 4 hfperclk cycles
ACMP_128_PCLK | 4 hfperclk cycles
ACMP_256_PCLK | 4 hfperclk cycles
ACMP_512_PCLK | 4 hfperclk cycles

Definition at line 106 of file ald_acmp.h.

106 {
107 ACMP_4_PCLK = 0x0U,
108 ACMP_8_PCLK = 0x1U,
109 ACMP_16_PCLK = 0x2U,
110 ACMP_32_PCLK = 0x3U,
111 ACMP_64_PCLK = 0x4U,
112 ACMP_128_PCLK = 0x5U,
113 ACMP_256_PCLK = 0x6U,
114 ACMP_512_PCLK = 0x7U,
115 } acmp_warm_time_t;
ACMP_8_PCLK
Definition: ald_acmp.h:108
ACMP_256_PCLK
Definition: ald_acmp.h:113
ACMP_4_PCLK
Definition: ald_acmp.h:107
ACMP_512_PCLK
Definition: ald_acmp.h:114
acmp_warm_time_t
acmp_warm_time_t
ACMP warm-up time.
Definition: ald_acmp.h:106
ACMP_64_PCLK
Definition: ald_acmp.h:111
ACMP_128_PCLK
Definition: ald_acmp.h:112
ACMP_16_PCLK
Definition: ald_acmp.h:109
ACMP_32_PCLK
Definition: ald_acmp.h:110


ALD User Manual: acmp_init_t Struct Reference

Data Fields
acmp_init_t Struct Reference
EASTSOFT ES32F3xx ALD » ACMP » ACMP Public Types

ACMP init structure definition. More...

#include <ald_acmp.h>

Data Fields

acmp_mode_t mode
acmp_warm_time_t warm_time
acmp_hystsel_t hystsel
acmp_pos_input_t p_port
acmp_neg_input_t n_port
acmp_inactval_t inactval
type_func_t out_inv
acmp_edge_t edge
uint8_t vdd_level

Detailed Description

ACMP init structure definition.

Definition at line 160 of file ald_acmp.h.

Field Documentation

◆ edge

acmp_edge_t edge

Select edges to set interrupt flag

Definition at line 168 of file ald_acmp.h.

◆ hystsel

acmp_hystsel_t hystsel

ACMP hysteresis level

Definition at line 163 of file ald_acmp.h.

◆ inactval

acmp_inactval_t inactval

ACMP inavtive output value

Definition at line 166 of file ald_acmp.h.

◆ mode

acmp_mode_t mode

ACMP operation mode

Definition at line 161 of file ald_acmp.h.

◆ n_port

acmp_neg_input_t n_port

ACMP negative port select

Definition at line 165 of file ald_acmp.h.

◆ out_inv

type_func_t out_inv

ACMP output inverse

Definition at line 167 of file ald_acmp.h.

◆ p_port

acmp_pos_input_t p_port

ACMP positive port select

Definition at line 164 of file ald_acmp.h.

◆ vdd_level

uint8_t vdd_level

Select scaling factor for CDD reference level, MAX is 63

Definition at line 169 of file ald_acmp.h.

◆ warm_time

acmp_warm_time_t warm_time

ACMP warm up time

Definition at line 162 of file ald_acmp.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_acmp.h


ALD User Manual: acmp_handle_s Struct Reference

Data Fields
acmp_handle_s Struct Reference
EASTSOFT ES32F3xx ALD » ACMP » ACMP Public Types

ACMP Handle Structure definition. More...

#include <ald_acmp.h>

Collaboration diagram for acmp_handle_s:
[legend]

Data Fields

ACMP_TypeDef * | perh
acmp_init_t init
lock_state_t lock
void(* | acmp_warmup_cplt_cbk )(struct acmp_handle_s *arg)
void(* | acmp_edge_cplt_cbk )(struct acmp_handle_s *arg)

Detailed Description

ACMP Handle Structure definition.

Definition at line 175 of file ald_acmp.h.

Field Documentation

◆ acmp_edge_cplt_cbk

void(* acmp_edge_cplt_cbk) (struct acmp_handle_s *arg)

ACMP edge trigger callback

Definition at line 181 of file ald_acmp.h.

◆ acmp_warmup_cplt_cbk

void(* acmp_warmup_cplt_cbk) (struct acmp_handle_s *arg)

ACMP warm-up complete callback

Definition at line 180 of file ald_acmp.h.

◆ init

acmp_init_t init

ACMP required parameters

Definition at line 177 of file ald_acmp.h.

◆ lock

lock_state_t lock

Locking object

Definition at line 178 of file ald_acmp.h.

◆ perh

ACMP_TypeDef* perh

Register base address

Definition at line 176 of file ald_acmp.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_acmp.h


ALD User Manual: ACMP Public Macros

Macros
ACMP Public Macros
EASTSOFT ES32F3xx ALD » ACMP
Collaboration diagram for ACMP Public Macros:

Macros

#define | ACMP_ENABLE(handle) (SET_BIT((handle)->perh->CON, ACMP_CON_EN_MSK))
#define | ACMP_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, ACMP_CON_EN_MSK))

Detailed Description

Macro Definition Documentation

◆ ACMP_DISABLE

#define ACMP_DISABLE ( handle ) (CLEAR_BIT((handle)->perh->CON, ACMP_CON_EN_MSK))

Definition at line 191 of file ald_acmp.h.

◆ ACMP_ENABLE

#define ACMP_ENABLE ( handle ) (SET_BIT((handle)->perh->CON, ACMP_CON_EN_MSK))

Definition at line 190 of file ald_acmp.h.


ALD User Manual: ACMP Private Macros

Macros
ACMP Private Macros
EASTSOFT ES32F3xx ALD » ACMP
Collaboration diagram for ACMP Private Macros:

Macros

#define | IS_ACMP_TYPE(x)
#define | IS_ACMP_MODE_TYPE(x)
#define | IS_ACMP_IT_TYPE(x)
#define | IS_ACMP_FLAG_TYPE(x)
#define | IS_ACMP_STATUS_TYPE(x)
#define | IS_ACMP_POS_INPUT_TYPE(x)
#define | IS_ACMP_NEG_INPUT_TYPE(x)
#define | IS_ACMP_WARM_UP_TIME_TYPE(x)
#define | IS_ACMP_HYSTSEL_TYPE(x)
#define | IS_ACMP_INACTVAL_TYPE(x)
#define | IS_ACMP_EDGE_TYPE(x)

Detailed Description

Macro Definition Documentation

◆ IS_ACMP_EDGE_TYPE

#define IS_ACMP_EDGE_TYPE ( x )
Value:
(((x) == ACMP_EDGE_NONE) || \
((x) == ACMP_EDGE_FALL) || \
((x) == ACMP_EDGE_RISE) || \
((x) == ACMP_EDGE_ALL))
ACMP_EDGE_NONE
Definition: ald_acmp.h:143
ACMP_EDGE_RISE
Definition: ald_acmp.h:145
ACMP_EDGE_ALL
Definition: ald_acmp.h:146
ACMP_EDGE_FALL
Definition: ald_acmp.h:144

Definition at line 249 of file ald_acmp.h.

◆ IS_ACMP_FLAG_TYPE

#define IS_ACMP_FLAG_TYPE ( x )
Value:
(((x) == ACMP_FLAG_EDGE) || \
((x) == ACMP_FLAG_WARMUP))
ACMP_FLAG_WARMUP
Definition: ald_acmp.h:51
ACMP_FLAG_EDGE
Definition: ald_acmp.h:50

Definition at line 208 of file ald_acmp.h.

◆ IS_ACMP_HYSTSEL_TYPE

#define IS_ACMP_HYSTSEL_TYPE ( x )
Value:
(((x) == ACMP_HYST_0) || \
((x) == ACMP_HYST_15) || \
((x) == ACMP_HYST_22) || \
((x) == ACMP_HYST_29) || \
((x) == ACMP_HYST_36) || \
((x) == ACMP_HYST_43) || \
((x) == ACMP_HYST_50) || \
((x) == ACMP_HYST_57))
ACMP_HYST_0
Definition: ald_acmp.h:121
ACMP_HYST_15
Definition: ald_acmp.h:122
ACMP_HYST_50
Definition: ald_acmp.h:127
ACMP_HYST_22
Definition: ald_acmp.h:123
ACMP_HYST_29
Definition: ald_acmp.h:124
ACMP_HYST_36
Definition: ald_acmp.h:125
ACMP_HYST_43
Definition: ald_acmp.h:126
ACMP_HYST_57
Definition: ald_acmp.h:128

Definition at line 239 of file ald_acmp.h.

◆ IS_ACMP_INACTVAL_TYPE

#define IS_ACMP_INACTVAL_TYPE ( x )
Value:
(((x) == ACMP_INACTVAL_LOW) || \
((x) == ACMP_INACTVAL_HIGH))
ACMP_INACTVAL_HIGH
Definition: ald_acmp.h:136
ACMP_INACTVAL_LOW
Definition: ald_acmp.h:135

Definition at line 247 of file ald_acmp.h.

◆ IS_ACMP_IT_TYPE

#define IS_ACMP_IT_TYPE ( x )
Value:
(((x) == ACMP_IT_EDGE) || \
((x) == ACMP_IT_WARMUP))
ACMP_IT_EDGE
Definition: ald_acmp.h:42
ACMP_IT_WARMUP
Definition: ald_acmp.h:43

Definition at line 206 of file ald_acmp.h.

◆ IS_ACMP_MODE_TYPE

#define IS_ACMP_MODE_TYPE ( x )
Value:
(((x) == ACMP_ULTRA_LOW_POWER) || \
((x) == ACMP_LOW_POWER) || \
((x) == ACMP_MIDDLE_POWER) || \
((x) == ACMP_HIGH_POWER))
ACMP_MIDDLE_POWER
Definition: ald_acmp.h:99
ACMP_LOW_POWER
Definition: ald_acmp.h:98
ACMP_ULTRA_LOW_POWER
Definition: ald_acmp.h:97
ACMP_HIGH_POWER
Definition: ald_acmp.h:100

Definition at line 202 of file ald_acmp.h.

◆ IS_ACMP_NEG_INPUT_TYPE

#define IS_ACMP_NEG_INPUT_TYPE ( x )
Value:
(((x) == ACMP_NEG_CH0) || \
((x) == ACMP_NEG_CH1) || \
((x) == ACMP_NEG_CH2) || \
((x) == ACMP_NEG_CH3) || \
((x) == ACMP_NEG_CH4) || \
((x) == ACMP_NEG_CH5) || \
((x) == ACMP_NEG_CH6) || \
((x) == ACMP_NEG_CH7) || \
((x) == ACMP_NEG_1V25) || \
((x) == ACMP_NEG_2V5) || \
((x) == ACMP_NEG_VDD))
ACMP_NEG_1V25
Definition: ald_acmp.h:88
ACMP_NEG_CH0
Definition: ald_acmp.h:80
ACMP_NEG_CH2
Definition: ald_acmp.h:82
ACMP_NEG_CH4
Definition: ald_acmp.h:84
ACMP_NEG_2V5
Definition: ald_acmp.h:89
ACMP_NEG_CH7
Definition: ald_acmp.h:87
ACMP_NEG_CH5
Definition: ald_acmp.h:85
ACMP_NEG_VDD
Definition: ald_acmp.h:90
ACMP_NEG_CH3
Definition: ald_acmp.h:83
ACMP_NEG_CH6
Definition: ald_acmp.h:86
ACMP_NEG_CH1
Definition: ald_acmp.h:81

Definition at line 220 of file ald_acmp.h.

◆ IS_ACMP_POS_INPUT_TYPE

#define IS_ACMP_POS_INPUT_TYPE ( x )
Value:
(((x) == ACMP_POS_CH0) || \
((x) == ACMP_POS_CH1) || \
((x) == ACMP_POS_CH2) || \
((x) == ACMP_POS_CH3) || \
((x) == ACMP_POS_CH4) || \
((x) == ACMP_POS_CH5) || \
((x) == ACMP_POS_CH6) || \
((x) == ACMP_POS_CH7))
ACMP_POS_CH3
Definition: ald_acmp.h:69
ACMP_POS_CH4
Definition: ald_acmp.h:70
ACMP_POS_CH2
Definition: ald_acmp.h:68
ACMP_POS_CH0
Definition: ald_acmp.h:66
ACMP_POS_CH1
Definition: ald_acmp.h:67
ACMP_POS_CH5
Definition: ald_acmp.h:71
ACMP_POS_CH6
Definition: ald_acmp.h:72
ACMP_POS_CH7
Definition: ald_acmp.h:73

Definition at line 212 of file ald_acmp.h.

◆ IS_ACMP_STATUS_TYPE

#define IS_ACMP_STATUS_TYPE ( x )
Value:
(((x) == ACMP_STATUS_ACT) || \
((x) == ACMP_STATUS_OUT))
ACMP_STATUS_ACT
Definition: ald_acmp.h:58
ACMP_STATUS_OUT
Definition: ald_acmp.h:59

Definition at line 210 of file ald_acmp.h.

◆ IS_ACMP_TYPE

#define IS_ACMP_TYPE ( x )
Value:
(((x) == ACMP0) || \
((x) == ACMP1) || \
((x) == ACMP2))

Definition at line 199 of file ald_acmp.h.

◆ IS_ACMP_WARM_UP_TIME_TYPE

#define IS_ACMP_WARM_UP_TIME_TYPE ( x )
Value:
(((x) == ACMP_4_PCLK) || \
((x) == ACMP_8_PCLK) || \
((x) == ACMP_16_PCLK) || \
((x) == ACMP_32_PCLK) || \
((x) == ACMP_64_PCLK) || \
((x) == ACMP_128_PCLK) || \
((x) == ACMP_256_PCLK) || \
((x) == ACMP_512_PCLK))
ACMP_8_PCLK
Definition: ald_acmp.h:108
ACMP_256_PCLK
Definition: ald_acmp.h:113
ACMP_4_PCLK
Definition: ald_acmp.h:107
ACMP_512_PCLK
Definition: ald_acmp.h:114
ACMP_64_PCLK
Definition: ald_acmp.h:111
ACMP_128_PCLK
Definition: ald_acmp.h:112
ACMP_16_PCLK
Definition: ald_acmp.h:109
ACMP_32_PCLK
Definition: ald_acmp.h:110

Definition at line 231 of file ald_acmp.h.


ALD User Manual: ADC

Modules
ADC
EASTSOFT ES32F3xx ALD

ADC module driver. More...

Collaboration diagram for ADC:

Modules

ADC Public Functions
ADC Private Functions
ADC Pubulic Types
ADC Public Macros
ADC Private Macros

Detailed Description

ADC module driver.


ALD User Manual: ADC Public Functions

Modules
ADC Public Functions
EASTSOFT ES32F3xx ALD » ADC
Collaboration diagram for ADC Public Functions:

Modules

Initialization functions
Initialization and Configuration functions.
IO operation functions
Input and Output operation functions.
Peripheral Control functions
Peripheral Control functions.
Peripheral State functions
Peripheral State functions.

Detailed Description


ALD User Manual: Initialization functions

Functions
Initialization functions
EASTSOFT ES32F3xx ALD » ADC » ADC Public Functions

Initialization and Configuration functions. More...

Collaboration diagram for Initialization functions:

Functions

ald_status_t | ald_adc_init (adc_handle_t *hperh)
Initializes the ADC peripheral and normal group according to parameters specified in structure "adc_handle_t". More...
ald_status_t | ald_adc_reset (adc_handle_t *hperh)
Deinitialize the ADC peripheral registers to their default reset values. More...

Detailed Description

Initialization and Configuration functions.

Function Documentation

◆ ald_adc_init()

ald_status_t ald_adc_init ( adc_handle_t * hperh )

Initializes the ADC peripheral and normal group according to parameters specified in structure "adc_handle_t".

Parameters
hperh Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
Return values
Status,see ald_status_t.

Definition at line 74 of file ald_adc.c.

75 {
76 assert_param(IS_ADC_TYPE(hperh->perh));
77 assert_param(IS_ADC_DATA_ALIGN_TYPE(hperh->init.align));
78 assert_param(IS_FUNC_STATE(hperh->init.scan));
79 assert_param(IS_ADC_CLK_DIV_TYPE(hperh->init.div));
80 assert_param(IS_ADC_NEG_REF_VOLTAGE_TYPE(hperh->init.n_ref));
81 assert_param(IS_POS_REF_VOLTAGE_TYPE(hperh->init.p_ref));
82 assert_param(IS_ADC_CONV_BIT_TYPE(hperh->init.data_bit));
83 assert_param(IS_ADC_NCH_NR_TYPE(hperh->init.nch_nr));
84 assert_param(IS_ADC_DISC_NR_TYPE(hperh->init.disc_nr));
85 assert_param(IS_FUNC_STATE(hperh->init.cont));
86 assert_param(IS_ADC_NCHESEL_MODE_TYPE(hperh->init.nche_sel));
87
88 if (hperh->state == ADC_STATE_RESET ) {
89 hperh->error_code = ADC_ERROR_NONE;
90 hperh->lock = UNLOCK;
91 }
92
93 ADC_DISABLE(hperh);
94 ald_adc_reset(hperh);
95 hperh->state = ADC_STATE_BUSY;
96 MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, hperh->init.align << ADC_CON1_ALIGN_POS);
97 MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, hperh->init.data_bit << ADC_CON0_RSEL_POSS);
98
99 /* Enable discontinuous mode only if continuous mode is disable */
100 if (hperh->init.disc == ADC_NCH_DISC_EN) {
101 hperh->init.scan = ENABLE;
102 hperh->init.cont = DISABLE;
103 SET_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK);
104 MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nr << ADC_CON0_ETRGN_POSS);
105 }
106 else if (hperh->init.disc == ADC_ICH_DISC_EN) {
107 hperh->init.scan = ENABLE;
108 hperh->init.cont = DISABLE;
109 SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK);
110 MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nr << ADC_CON0_ETRGN_POSS);
111 }
112 else {
113 CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK);
114 CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK);
115 }
116
117 if ((hperh->init.scan == ENABLE) || (hperh->init.disc == ADC_NCH_DISC_EN))
118 MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.nch_nr << ADC_CHSL_NSL_POSS);
119
120 MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, hperh->init.cont << ADC_CON1_CM_POS);
121 MODIFY_REG(hperh->perh->CON0, ADC_CON0_SCANEN_MSK, hperh->init.scan << ADC_CON0_SCANEN_POS);
122 MODIFY_REG(hperh->perh->CCR, ADC_CCR_GAINCALEN_MSK, DISABLE << ADC_CCR_GAINCALEN_POS);
123 MODIFY_REG(hperh->perh->CCR, ADC_CCR_OFFCALEN_MSK, DISABLE << ADC_CCR_OFFCALEN_POS);
124 MODIFY_REG(hperh->perh->CCR, ADC_CCR_DIFFEN_MSK, DISABLE << ADC_CCR_DIFFEN_POS);
125 /* if the ADC clock less than 1MHz,PWRMOD should be disable*/
126 MODIFY_REG(hperh->perh->CCR, ADC_CCR_PWRMODSEL_MSK, DISABLE << ADC_CCR_PWRMODSEL_POS);
127 MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRBUFEN_MSK, ENABLE << ADC_CCR_VRBUFEN_POS);
128 MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, ENABLE << ADC_CCR_VCMBUFEN_POS);
129 MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS);
130 MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS);
131 MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, hperh->init.div << ADC_CCR_CKDIV_POSS);
132 MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS);
133 MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POSS);
134 MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_sel << ADC_CON1_NCHESEL_POS);
135 ald_adc_interrupt_config(hperh, ADC_IT_OVR, ENABLE);
136 ADC_ENABLE(hperh);
137
138 hperh->error_code = ADC_ERROR_NONE;
139 hperh->state = ADC_STATE_READY;
140 return OK;
141 }
ADC_ENABLE
#define ADC_ENABLE(handle)
Definition: ald_adc.h:401
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
adc_init_t::scan
type_func_t scan
Definition: ald_adc.h:306
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
adc_init_t::disc
adc_disc_mode_t disc
Definition: ald_adc.h:309
adc_init_t::nche_sel
adc_nchesel_t nche_sel
Definition: ald_adc.h:313
DISABLE
Definition: type.h:48
IS_ADC_CLK_DIV_TYPE
#define IS_ADC_CLK_DIV_TYPE(x)
Definition: ald_adc.h:449
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
adc_init_t::data_bit
adc_conv_bit_t data_bit
Definition: ald_adc.h:311
IS_ADC_DISC_NR_TYPE
#define IS_ADC_DISC_NR_TYPE(x)
Definition: ald_adc.h:465
adc_init_t::div
adc_clk_div_t div
Definition: ald_adc.h:312
ald_adc_reset
ald_status_t ald_adc_reset(adc_handle_t *hperh)
Deinitialize the ADC peripheral registers to their default reset values.
Definition: ald_adc.c:150
UNLOCK
Definition: type.h:59
adc_init_t::cont
type_func_t cont
Definition: ald_adc.h:307
IS_ADC_NCH_NR_TYPE
#define IS_ADC_NCH_NR_TYPE(x)
Definition: ald_adc.h:463
adc_handle_s::init
adc_init_t init
Definition: ald_adc.h:355
IS_ADC_NCHESEL_MODE_TYPE
#define IS_ADC_NCHESEL_MODE_TYPE(x)
Definition: ald_adc.h:472
IS_ADC_NEG_REF_VOLTAGE_TYPE
#define IS_ADC_NEG_REF_VOLTAGE_TYPE(x)
Definition: ald_adc.h:457
adc_init_t::align
adc_align_t align
Definition: ald_adc.h:305
IS_ADC_CONV_BIT_TYPE
#define IS_ADC_CONV_BIT_TYPE(x)
Definition: ald_adc.h:466
ADC_STATE_BUSY
Definition: ald_adc.h:46
adc_init_t::nch_nr
adc_nch_nr_t nch_nr
Definition: ald_adc.h:308
ADC_STATE_READY
Definition: ald_adc.h:45
ADC_ICH_DISC_EN
Definition: ald_adc.h:259
IS_ADC_DATA_ALIGN_TYPE
#define IS_ADC_DATA_ALIGN_TYPE(x)
Definition: ald_adc.h:430
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
ald_adc_interrupt_config
void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state)
Enables or disables the specified ADC interrupts.
Definition: ald_adc.c:913
adc_init_t::p_ref
adc_pos_ref_t p_ref
Definition: ald_adc.h:315
adc_init_t::n_ref
adc_neg_ref_t n_ref
Definition: ald_adc.h:314
IS_POS_REF_VOLTAGE_TYPE
#define IS_POS_REF_VOLTAGE_TYPE(x)
Definition: ald_adc.h:459
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470
adc_handle_s::lock
lock_state_t lock
Definition: ald_adc.h:360
ADC_DISABLE
#define ADC_DISABLE(handle)
Definition: ald_adc.h:402
ADC_IT_OVR
Definition: ald_adc.h:174
adc_init_t::disc_nr
adc_disc_nr_t disc_nr
Definition: ald_adc.h:310
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
ADC_NCH_DISC_EN
Definition: ald_adc.h:258
adc_handle_s::error_code
adc_error_t error_code
Definition: ald_adc.h:362
ADC_STATE_RESET
Definition: ald_adc.h:44
ADC_ERROR_NONE
Definition: ald_adc.h:58

◆ ald_adc_reset()

ald_status_t ald_adc_reset ( adc_handle_t * hperh )

Deinitialize the ADC peripheral registers to their default reset values.

Parameters
hperh Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
Return values
Status,see ald_status_t.

Definition at line 150 of file ald_adc.c.

151 {
152 assert_param(IS_ADC_TYPE(hperh->perh));
153
154 ADC_DISABLE(hperh);
155 WRITE_REG(hperh->perh->CLR, 0x30F);
156 WRITE_REG(hperh->perh->CON0, 0x0);
157 WRITE_REG(hperh->perh->CON1, 0x0);
158 WRITE_REG(hperh->perh->CCR, 0x0);
159 WRITE_REG(hperh->perh->WDTH, 0xFFF);
160 WRITE_REG(hperh->perh->WDTL, 0x0);
161 WRITE_REG(hperh->perh->ICHOFF1, 0x0);
162 WRITE_REG(hperh->perh->ICHOFF2, 0x0);
163 WRITE_REG(hperh->perh->ICHOFF3, 0x0);
164 WRITE_REG(hperh->perh->ICHOFF4, 0x0);
165 WRITE_REG(hperh->perh->ICHS, 0x0);
166 WRITE_REG(hperh->perh->NCHS1, 0x0);
167 WRITE_REG(hperh->perh->NCHS2, 0x0);
168 WRITE_REG(hperh->perh->NCHS3, 0x0);
169 WRITE_REG(hperh->perh->NCHS4, 0x0);
170 WRITE_REG(hperh->perh->SMPT1, 0x0);
171 WRITE_REG(hperh->perh->SMPT2, 0x0);
172 WRITE_REG(hperh->perh->CHSL, 0x0);
173
174 hperh->state = ADC_STATE_RESET;
175 hperh->error_code = ADC_ERROR_NONE;
176 return OK;
177 }
OK
Definition: utils.h:55
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
assert_param
#define assert_param(x)
Definition: type.h:88
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470
ADC_DISABLE
#define ADC_DISABLE(handle)
Definition: ald_adc.h:402
adc_handle_s::error_code
adc_error_t error_code
Definition: ald_adc.h:362
ADC_STATE_RESET
Definition: ald_adc.h:44
ADC_ERROR_NONE
Definition: ald_adc.h:58


ALD User Manual: IO operation functions

Functions
IO operation functions
EASTSOFT ES32F3xx ALD » ADC » ADC Public Functions

Input and Output operation functions. More...

Collaboration diagram for IO operation functions:

Functions

ald_status_t | ald_adc_normal_start (adc_handle_t *hperh)
Enables ADC, starts conversion of normal group. More...
ald_status_t | ald_adc_normal_stop (adc_handle_t *hperh)
Stop ADC conversion of normal group (and insert channels in case of auto_injection mode), disable ADC peripheral. More...
ald_status_t | ald_adc_normal_poll_for_conversion (adc_handle_t *hperh, uint32_t timeout)
Wait for normal group conversion to be completed. More...
ald_status_t | ald_adc_poll_for_event (adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout)
Poll for conversion event. More...
ald_status_t | ald_adc_normal_start_by_it (adc_handle_t *hperh)
Enables ADC, starts conversion of normal group with interruption. Interruptions enabled in this function: More...
ald_status_t | ald_adc_normal_stop_by_it (adc_handle_t *hperh)
Stop ADC conversion of normal group (and insert group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral. More...
ald_status_t | ald_adc_start_by_dma (adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel)
Enables ADC, starts conversion of normal group and transfers result through DMA. More...
ald_status_t | ald_adc_stop_by_dma (adc_handle_t *hperh, uint8_t channel)
Stop ADC conversion of normal group (and insert group in case of auto_insert mode), disable ADC DMA transfer, disable ADC peripheral. More...
static void | adc_dma_timer_trigger_cplt (void *arg)
DMA transfer complete callback. More...
ald_status_t | ald_adc_timer_trigger_adc_by_dma (adc_timer_config_t *config)
Config Timer trigger adc function. More...
uint32_t | ald_adc_normal_get_value (adc_handle_t *hperh)
Get ADC normal group conversion result. More...
ald_status_t | ald_adc_insert_start (adc_handle_t *hperh)
Enables ADC, starts conversion of insert group. Interruptions enabled in this function: None. More...
ald_status_t | ald_adc_insert_stop (adc_handle_t *hperh)
Stop conversion of insert channels. Disable ADC peripheral if no normal conversion is on going. More...
ald_status_t | ald_adc_insert_poll_for_conversion (adc_handle_t *hperh, uint32_t timeout)
Wait for insert group conversion to be completed. More...
ald_status_t | ald_adc_insert_start_by_it (adc_handle_t *hperh)
Enables ADC, starts conversion of insert group with interruption. More...
ald_status_t | ald_adc_insert_stop_by_it (adc_handle_t *hperh)
Stop conversion of insert channels, disable interruption of end-of-conversion. Disable ADC peripheral if no normal conversion is on going. More...
uint32_t | ald_adc_insert_get_value (adc_handle_t *hperh, adc_ich_idx_t idx)
Get ADC insert group conversion result. More...
void | ald_adc_irq_handler (adc_handle_t *hperh)
Handles ADC interrupt request. More...

Detailed Description

Input and Output operation functions.

Function Documentation

◆ adc_dma_timer_trigger_cplt()

static void adc_dma_timer_trigger_cplt ( void * arg )
static

DMA transfer complete callback.

Parameters
arg argument of the call back.
Return values
None

Definition at line 402 of file ald_adc.c.

403 {
404 adc_timer_config_t *hperh = (adc_timer_config_t *)arg;
405
406 ald_timer_base_stop(&hperh->h_timer);
407 CLEAR_BIT(hperh->h_adc.perh->CON1, ADC_CON1_DMA_MSK);
408 ADC_DISABLE(&hperh->h_adc);
409 ald_dma_channel_config(hperh->h_dma.perh, hperh->dma_ch, DISABLE);
410 CLEAR_BIT(hperh->h_adc.state, ADC_STATE_BUSY_N);
411
412 if (hperh->h_adc.normal_cplt_cbk)
413 hperh->h_adc.normal_cplt_cbk(&hperh->h_adc);
414
415 return;
416 }
adc_timer_config_t::h_dma
dma_handle_t h_dma
Definition: ald_adc.h:389
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
adc_timer_config_t
Timer trigger adc config structure definition.
Definition: ald_adc.h:374
DISABLE
Definition: type.h:48
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
ADC_STATE_BUSY_N
Definition: ald_adc.h:49
adc_timer_config_t::h_timer
timer_handle_t h_timer
Definition: ald_adc.h:390
ald_timer_base_stop
void ald_timer_base_stop(timer_handle_t *hperh)
Stops the TIMER Base generation.
Definition: ald_timer.c:154
adc_timer_config_t::h_adc
adc_handle_t h_adc
Definition: ald_adc.h:391
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
ADC_DISABLE
#define ADC_DISABLE(handle)
Definition: ald_adc.h:402
adc_timer_config_t::dma_ch
uint8_t dma_ch
Definition: ald_adc.h:381
adc_handle_s::normal_cplt_cbk
void(* normal_cplt_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:364
ald_dma_channel_config
void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state)
Configure channel enable or disable. It will unbind descriptor with channel, when channel has been di...
Definition: ald_dma.c:850

◆ ald_adc_insert_get_value()

uint32_t ald_adc_insert_get_value | ( | adc_handle_t * | hperh,
 |  | adc_ich_idx_t | idx
 | ) |  |

Get ADC insert group conversion result.

Parameters
hperh | Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
idx | Index of converted ADC insert channel.
Return values
ADC group insert conversion data

Definition at line 661 of file ald_adc.c.

662 {
663 uint32_t tmp;
664
665 assert_param(IS_ADC_TYPE(hperh->perh));
666 assert_param(IS_ADC_ICH_IDX_TYPE(idx));
667
668 switch (idx) {
669 case ADC_ICH_IDX_1:
670 tmp = hperh->perh->ICHDR1;
671 break;
672 case ADC_ICH_IDX_2:
673 tmp = hperh->perh->ICHDR2;
674 break;
675 case ADC_ICH_IDX_3:
676 tmp = hperh->perh->ICHDR3;
677 break;
678 case ADC_ICH_IDX_4:
679 tmp = hperh->perh->ICHDR4;
680 break;
681 default:
682 tmp = hperh->perh->ICHDR1;
683 break;
684 }
685
686 return tmp;
687 }
ADC_ICH_IDX_1
Definition: ald_adc.h:141
assert_param
#define assert_param(x)
Definition: type.h:88
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
ADC_ICH_IDX_3
Definition: ald_adc.h:143
ADC_ICH_IDX_4
Definition: ald_adc.h:144
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470
ADC_ICH_IDX_2
Definition: ald_adc.h:142
IS_ADC_ICH_IDX_TYPE
#define IS_ADC_ICH_IDX_TYPE(x)
Definition: ald_adc.h:423

◆ ald_adc_insert_poll_for_conversion()

ald_status_t ald_adc_insert_poll_for_conversion | ( | adc_handle_t * | hperh,
 |  | uint32_t | timeout
 | ) |  |

Wait for insert group conversion to be completed.

Parameters
hperh | Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
timeout | Timeout value in millisecond.
Return values
Status,see ald_status_t.

Definition at line 587 of file ald_adc.c.

588 {
589 uint32_t _tick;
590
591 assert_param(IS_ADC_TYPE(hperh->perh));
592
593 _tick = ald_get_tick();
594
595 while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_ICHE_MSK))) {
596 if (timeout != ALD_MAX_DELAY) {
597 if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) {
598 hperh->state |= ADC_STATE_TIMEOUT;
599 return TIMEOUT;
600 }
601 }
602 }
603
604 WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICHS | ADC_FLAG_ICH);
605 return OK;
606 }
ADC_STATE_TIMEOUT
Definition: ald_adc.h:47
OK
Definition: utils.h:55
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
assert_param
#define assert_param(x)
Definition: type.h:88
ALD_MAX_DELAY
#define ALD_MAX_DELAY
Definition: utils.h:88
ADC_FLAG_ICH
Definition: ald_adc.h:183
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
ADC_FLAG_ICHS
Definition: ald_adc.h:186
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470

◆ ald_adc_insert_start()

ald_status_t ald_adc_insert_start ( adc_handle_t * hperh )

Enables ADC, starts conversion of insert group. Interruptions enabled in this function: None.

Parameters
hperh Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
Return values
Status,see ald_status_t.

Definition at line 546 of file ald_adc.c.

547 {
548 assert_param(IS_ADC_TYPE(hperh->perh));
549
550 ADC_ENABLE(hperh);
551 WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICH);
552
553 if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)))
554 SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK);
555
556 return OK;
557 }
ADC_ENABLE
#define ADC_ENABLE(handle)
Definition: ald_adc.h:401
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
ADC_FLAG_ICH
Definition: ald_adc.h:183
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470

◆ ald_adc_insert_start_by_it()

ald_status_t ald_adc_insert_start_by_it ( adc_handle_t * hperh )

Enables ADC, starts conversion of insert group with interruption.

  • JEOC (end of conversion of insert group) Each of these interruptions has its dedicated callback function.
    Parameters
    hperh Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
    Return values
    Status,see ald_status_t..

Definition at line 616 of file ald_adc.c.

617 {
618 assert_param(IS_ADC_TYPE(hperh->perh));
619
620 SET_BIT(hperh->state, ADC_STATE_BUSY_I);
621 ADC_ENABLE(hperh);
622 WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICHS | ADC_FLAG_ICH);
623 ald_adc_interrupt_config(hperh, ADC_IT_ICH, ENABLE);
624
625 if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)))
626 SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK);
627
628 return OK;
629 }
ADC_ENABLE
#define ADC_ENABLE(handle)
Definition: ald_adc.h:401
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
assert_param
#define assert_param(x)
Definition: type.h:88
ADC_IT_ICH
Definition: ald_adc.h:173
ADC_FLAG_ICH
Definition: ald_adc.h:183
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
ADC_FLAG_ICHS
Definition: ald_adc.h:186
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
ald_adc_interrupt_config
void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state)
Enables or disables the specified ADC interrupts.
Definition: ald_adc.c:913
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470
ADC_STATE_BUSY_I
Definition: ald_adc.h:50

◆ ald_adc_insert_stop()

ald_status_t ald_adc_insert_stop ( adc_handle_t * hperh )

Stop conversion of insert channels. Disable ADC peripheral if no normal conversion is on going.

Note
If ADC must be disabled and if conversion is on going on normal group, function ald_adc_normal_stop must be used to stop both insert and normal groups, and disable the ADC.
If insert group mode auto-injection is enabled, function ald_adc_normal_stop must be used.
Parameters
hperh Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
Return values
Status,see ald_status_t.

Definition at line 571 of file ald_adc.c.

572 {
573 assert_param(IS_ADC_TYPE(hperh->perh));
574
575 ADC_DISABLE(hperh);
576 hperh->state = ADC_STATE_READY;
577 return OK;
578 }
OK
Definition: utils.h:55
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
assert_param
#define assert_param(x)
Definition: type.h:88
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
ADC_STATE_READY
Definition: ald_adc.h:45
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470
ADC_DISABLE
#define ADC_DISABLE(handle)
Definition: ald_adc.h:402

◆ ald_adc_insert_stop_by_it()

ald_status_t ald_adc_insert_stop_by_it ( adc_handle_t * hperh )

Stop conversion of insert channels, disable interruption of end-of-conversion. Disable ADC peripheral if no normal conversion is on going.

Note
If ADC must be disabled and if conversion is on going on normal group, function ald_adc_normal_stop must be used to stop both insert and normal groups, and disable the ADC.
If insert group mode auto-injection is enabled, function ald_adc_normal_stop must be used.
Parameters
hperh Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
Return values
None

Definition at line 644 of file ald_adc.c.

645 {
646 assert_param(IS_ADC_TYPE(hperh->perh));
647
648 CLEAR_BIT(hperh->state, ADC_STATE_BUSY_I);
649 ADC_DISABLE(hperh);
650 ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE);
651 return OK;
652 }
OK
Definition: utils.h:55
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
ADC_IT_ICH
Definition: ald_adc.h:173
DISABLE
Definition: type.h:48
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
ald_adc_interrupt_config
void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state)
Enables or disables the specified ADC interrupts.
Definition: ald_adc.c:913
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470
ADC_STATE_BUSY_I
Definition: ald_adc.h:50
ADC_DISABLE
#define ADC_DISABLE(handle)
Definition: ald_adc.h:402

◆ ald_adc_irq_handler()

void ald_adc_irq_handler ( adc_handle_t * hperh )

Handles ADC interrupt request.

Parameters
hperh Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
Return values
None

Definition at line 695 of file ald_adc.c.

696 {
697 assert_param(IS_ADC_TYPE(hperh->perh));
698
699 if (ald_adc_get_it_status(hperh, ADC_IT_NCH) && ald_adc_get_flag_status(hperh, ADC_FLAG_NCH)) {
700 WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH | ADC_FLAG_NCHS);
701 CLEAR_BIT(hperh->state, ADC_STATE_BUSY_N);
702
703 if (hperh->normal_cplt_cbk)
704 hperh->normal_cplt_cbk(hperh);
705 }
706
707 if (ald_adc_get_it_status(hperh, ADC_IT_ICH) && ald_adc_get_flag_status(hperh, ADC_FLAG_ICH)) {
708 WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICH | ADC_FLAG_ICHS);
709 CLEAR_BIT(hperh->state, ADC_STATE_BUSY_I);
710
711 if (hperh->insert_cplt_cbk)
712 hperh->insert_cplt_cbk(hperh);
713 }
714
715 if (ald_adc_get_it_status(hperh, ADC_IT_AWD) && ald_adc_get_flag_status(hperh, ADC_FLAG_AWD)) {
716 CLEAR_BIT(hperh->state, ADC_STATE_BUSY_WDG);
717 WRITE_REG(hperh->perh->CLR, ADC_FLAG_AWD);
718
719 if (hperh->wdg_cbk)
720 hperh->wdg_cbk(hperh);
721 }
722
723 if (ald_adc_get_it_status(hperh, ADC_IT_OVR) && ald_adc_get_flag_status(hperh, ADC_FLAG_OVR)) {
724 WRITE_REG(hperh->perh->CLR, ADC_FLAG_OVR);
725 hperh->error_code |= ADC_ERROR_OVR;
726 hperh->state |= ADC_STATE_ERROR;
727
728 if (hperh->ovr_cbk)
729 hperh->ovr_cbk(hperh);
730 }
731 }
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
ADC_IT_AWD
Definition: ald_adc.h:172
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
adc_handle_s::wdg_cbk
void(* wdg_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:366
ADC_STATE_ERROR
Definition: ald_adc.h:48
ADC_IT_ICH
Definition: ald_adc.h:173
ADC_FLAG_ICH
Definition: ald_adc.h:183
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
ADC_ERROR_OVR
Definition: ald_adc.h:60
ADC_STATE_BUSY_N
Definition: ald_adc.h:49
adc_handle_s::ovr_cbk
void(* ovr_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:368
ADC_FLAG_AWD
Definition: ald_adc.h:181
ADC_FLAG_ICHS
Definition: ald_adc.h:186
ald_adc_get_it_status
it_status_t ald_adc_get_it_status(adc_handle_t *hperh, adc_it_t it)
Checks whether the specified ADC interrupt has occurred or not.
Definition: ald_adc.c:936
adc_handle_s::insert_cplt_cbk
void(* insert_cplt_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:365
ADC_FLAG_OVR
Definition: ald_adc.h:184
ADC_IT_NCH
Definition: ald_adc.h:171
ADC_FLAG_NCHS
Definition: ald_adc.h:185
ADC_FLAG_NCH
Definition: ald_adc.h:182
ald_adc_get_flag_status
flag_status_t ald_adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag)
Check whether the specified ADC flag is set or not.
Definition: ald_adc.c:955
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470
ADC_STATE_BUSY_I
Definition: ald_adc.h:50
ADC_IT_OVR
Definition: ald_adc.h:174
adc_handle_s::error_code
adc_error_t error_code
Definition: ald_adc.h:362
adc_handle_s::normal_cplt_cbk
void(* normal_cplt_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:364
ADC_STATE_BUSY_WDG
Definition: ald_adc.h:51

◆ ald_adc_normal_get_value()

uint32_t ald_adc_normal_get_value ( adc_handle_t * hperh )

Get ADC normal group conversion result.

Parameters
hperh Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
Return values
ADC group normal conversion data

Definition at line 532 of file ald_adc.c.

533 {
534 assert_param(IS_ADC_TYPE(hperh->perh));
535
536 return hperh->perh->NCHDR;
537 }
assert_param
#define assert_param(x)
Definition: type.h:88
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470

◆ ald_adc_normal_poll_for_conversion()

ald_status_t ald_adc_normal_poll_for_conversion | ( | adc_handle_t * | hperh,
 |  | uint32_t | timeout
 | ) |  |

Wait for normal group conversion to be completed.

Note
This function cannot be used in a particular setup: ADC configured in DMA mode. In this case, DMA resets the flag EOC and polling cannot be performed on each conversion.
When use this function,you should be pay attention to the hperh->init.reocs_mode, if it is ADC_REOCS_MODE_ALL, it means the function will wait all normal rank conversion finished. if it is ADC_REOCS_MODE_ONE, it means the funcion will wait every normal rank conversion finished.
Parameters
hperh | Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
timeout | Timeout value in millisecond.
Return values
Status,see ald_status_t.

Definition at line 236 of file ald_adc.c.

237 {
238 uint32_t _tick;
239
240 assert_param(IS_ADC_TYPE(hperh->perh));
241
242 _tick = ald_get_tick();
243 while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK))) {
244 if (timeout != ALD_MAX_DELAY ) {
245 if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) {
246 hperh->state = ADC_STATE_TIMEOUT;
247 return TIMEOUT;
248 }
249 }
250 }
251
252 WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCHS | ADC_FLAG_NCH);
253 return OK;
254 }
ADC_STATE_TIMEOUT
Definition: ald_adc.h:47
OK
Definition: utils.h:55
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
assert_param
#define assert_param(x)
Definition: type.h:88
ALD_MAX_DELAY
#define ALD_MAX_DELAY
Definition: utils.h:88
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
ADC_FLAG_NCHS
Definition: ald_adc.h:185
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
ADC_FLAG_NCH
Definition: ald_adc.h:182
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470

◆ ald_adc_normal_start()

ald_status_t ald_adc_normal_start ( adc_handle_t * hperh )

Enables ADC, starts conversion of normal group.

Parameters
hperh Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
Return values
Status,see ald_status_t.

Definition at line 193 of file ald_adc.c.

194 {
195 assert_param(IS_ADC_TYPE(hperh->perh));
196
197 ADC_ENABLE(hperh);
198 WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH | ADC_FLAG_NCHS);
199 SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK);
200
201 return OK;
202 }
ADC_ENABLE
#define ADC_ENABLE(handle)
Definition: ald_adc.h:401
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
ADC_FLAG_NCHS
Definition: ald_adc.h:185
ADC_FLAG_NCH
Definition: ald_adc.h:182
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470

◆ ald_adc_normal_start_by_it()

ald_status_t ald_adc_normal_start_by_it ( adc_handle_t * hperh )

Enables ADC, starts conversion of normal group with interruption. Interruptions enabled in this function:

  • REOC (end of conversion of normal group) Each of these interruptions has its dedicated callback function.
    Parameters
    hperh Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
    Return values
    Status,see ald_status_t.

Definition at line 296 of file ald_adc.c.

297 {
298 assert_param(IS_ADC_TYPE(hperh->perh));
299
300 SET_BIT(hperh->state, ADC_STATE_BUSY_N);
301 ADC_ENABLE(hperh);
302 WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH);
303 ald_adc_interrupt_config(hperh, ADC_IT_NCH, ENABLE);
304 SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK);
305
306 return OK;
307 }
ADC_ENABLE
#define ADC_ENABLE(handle)
Definition: ald_adc.h:401
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
assert_param
#define assert_param(x)
Definition: type.h:88
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
ADC_STATE_BUSY_N
Definition: ald_adc.h:49
ADC_IT_NCH
Definition: ald_adc.h:171
ADC_FLAG_NCH
Definition: ald_adc.h:182
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
ald_adc_interrupt_config
void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state)
Enables or disables the specified ADC interrupts.
Definition: ald_adc.c:913
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470

◆ ald_adc_normal_stop()

ald_status_t ald_adc_normal_stop ( adc_handle_t * hperh )

Stop ADC conversion of normal group (and insert channels in case of auto_injection mode), disable ADC peripheral.

Note
: ADC peripheral disable is forcing stop of potential conversion on insert group. If insert group is under use, it should be preliminarily stopped using ald_adc_insert_stop function.
Parameters
hperh Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
Return values
Status,see ald_status_t.

Definition at line 214 of file ald_adc.c.

215 {
216 assert_param(IS_ADC_TYPE(hperh->perh));
217
218 ADC_DISABLE(hperh);
219 hperh->state = ADC_STATE_READY;
220
221 return OK;
222 }
OK
Definition: utils.h:55
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
assert_param
#define assert_param(x)
Definition: type.h:88
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
ADC_STATE_READY
Definition: ald_adc.h:45
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470
ADC_DISABLE
#define ADC_DISABLE(handle)
Definition: ald_adc.h:402

◆ ald_adc_normal_stop_by_it()

ald_status_t ald_adc_normal_stop_by_it ( adc_handle_t * hperh )

Stop ADC conversion of normal group (and insert group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.

Parameters
hperh Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
Return values
Status,see ald_status_t.

Definition at line 317 of file ald_adc.c.

318 {
319 assert_param(IS_ADC_TYPE(hperh->perh));
320
321 ADC_DISABLE(hperh);
322 ald_adc_interrupt_config(hperh, ADC_IT_NCH, DISABLE);
323 CLEAR_BIT(hperh->state, ADC_STATE_BUSY_N);
324
325 return OK;
326 }
OK
Definition: utils.h:55
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
DISABLE
Definition: type.h:48
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
ADC_STATE_BUSY_N
Definition: ald_adc.h:49
ADC_IT_NCH
Definition: ald_adc.h:171
ald_adc_interrupt_config
void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state)
Enables or disables the specified ADC interrupts.
Definition: ald_adc.c:913
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470
ADC_DISABLE
#define ADC_DISABLE(handle)
Definition: ald_adc.h:402

◆ ald_adc_poll_for_event()

ald_status_t ald_adc_poll_for_event | ( | adc_handle_t * | hperh,
 |  | adc_event_type_t | event_type,
 |  | uint32_t | timeout
 | ) |  |

Poll for conversion event.

Parameters
hperh | Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
event_type | the ADC event type. This parameter can be one of the following values: ADC_awd_event: ADC Analog watchdog event.
timeout | Timeout value in millisecond.
Return values
Status,see ald_status_t.

Definition at line 266 of file ald_adc.c.

267 {
268 uint32_t _tick;
269
270 assert_param(IS_ADC_TYPE(hperh->perh));
271 assert_param(IS_ADC_EVENT_TYPE(event_type));
272
273 _tick = ald_get_tick();
274 while (ald_adc_get_flag_status(hperh, (adc_flag_t)event_type) == RESET) {
275 if (timeout != ALD_MAX_DELAY ) {
276 if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) {
277 hperh->state = ADC_STATE_TIMEOUT;
278 return TIMEOUT;
279 }
280 }
281 }
282
283 CLEAR_BIT(hperh->state, ADC_STATE_BUSY_WDG);
284 return OK;
285 }
adc_flag_t
adc_flag_t
ADC flags definition.
Definition: ald_adc.h:180
ADC_STATE_TIMEOUT
Definition: ald_adc.h:47
OK
Definition: utils.h:55
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
ALD_MAX_DELAY
#define ALD_MAX_DELAY
Definition: utils.h:88
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
RESET
Definition: type.h:38
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
ald_adc_get_flag_status
flag_status_t ald_adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag)
Check whether the specified ADC flag is set or not.
Definition: ald_adc.c:955
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470
IS_ADC_EVENT_TYPE
#define IS_ADC_EVENT_TYPE(x)
Definition: ald_adc.h:474
ADC_STATE_BUSY_WDG
Definition: ald_adc.h:51

◆ ald_adc_start_by_dma()

ald_status_t ald_adc_start_by_dma | ( | adc_handle_t * | hperh,
 |  | uint16_t * | buf,
 |  | uint16_t | size,
 |  | uint8_t | channel
 | ) |  |

Enables ADC, starts conversion of normal group and transfers result through DMA.

Parameters
hperh | Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
buf | The destination Buffer address.
size | The length of data to be transferred from ADC peripheral to memory.
channel | The DMA channel
Return values
Status,see ald_status_t.

Definition at line 339 of file ald_adc.c.

340 {
341 if ((buf == NULL) || (size == 0))
342 return ERROR;
343
344 assert_param(IS_ADC_TYPE(hperh->perh));
345
346 SET_BIT(hperh->state, ADC_STATE_BUSY_N);
347
348 if (hperh->hdma.perh == NULL)
349 hperh->hdma.perh = DMA0;
350
351 hperh->hdma.cplt_cbk = adc_dma_normal_conv_cplt;
352 hperh->hdma.cplt_arg = hperh;
353 hperh->hdma.err_cbk = adc_dma_error;
354 hperh->hdma.err_arg = hperh;
355
356 ald_dma_config_struct(&hperh->hdma.config);
357 hperh->hdma.config.src = (void *)&hperh->perh->NCHDR;
358 hperh->hdma.config.dst = (void *)buf;
359 hperh->hdma.config.size = size;
360 hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD;
361 hperh->hdma.config.src_inc = DMA_DATA_INC_NONE;
362 hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD;
363 hperh->hdma.config.msel = hperh->perh == ADC0 ? DMA_MSEL_ADC0 : DMA_MSEL_ADC1;
364 hperh->hdma.config.msigsel = DMA_MSIGSEL_ADC;
365 hperh->hdma.config.burst = ENABLE;
366 hperh->hdma.config.channel = channel;
367 ald_dma_config_basic(&hperh->hdma);
368
369 ADC_ENABLE(hperh);
370 SET_BIT(hperh->perh->CON1, ADC_CON1_DMA_MSK);
371 SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK);
372
373 return OK;
374 }
ADC_ENABLE
#define ADC_ENABLE(handle)
Definition: ald_adc.h:401
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
assert_param
#define assert_param(x)
Definition: type.h:88
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
adc_handle_s::hdma
dma_handle_t hdma
Definition: ald_adc.h:357
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
adc_dma_normal_conv_cplt
static void adc_dma_normal_conv_cplt(void *arg)
DMA transfer complete callback.
Definition: ald_adc.c:1029
ADC_STATE_BUSY_N
Definition: ald_adc.h:49
dma_config_t::src
void * src
Definition: ald_dma.h:278
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
DMA_MSEL_ADC1
Definition: ald_dma.h:104
adc_dma_error
static void adc_dma_error(void *arg)
DMA error callback.
Definition: ald_adc.c:1045
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
DMA_MSIGSEL_ADC
Definition: ald_dma.h:136
DMA_MSEL_ADC0
Definition: ald_dma.h:82
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294

◆ ald_adc_stop_by_dma()

ald_status_t ald_adc_stop_by_dma | ( | adc_handle_t * | hperh,
 |  | uint8_t | channel
 | ) |  |

Stop ADC conversion of normal group (and insert group in case of auto_insert mode), disable ADC DMA transfer, disable ADC peripheral.

Parameters
hperh | Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
channel | The DMA channel
Return values
Status,see ald_status_t.

Definition at line 385 of file ald_adc.c.

386 {
387 assert_param(IS_ADC_TYPE(hperh->perh));
388
389 ADC_DISABLE(hperh);
390 CLEAR_BIT(hperh->perh->CON1, ADC_CON1_DMA_MSK);
391 ald_dma_channel_config(hperh->hdma.perh, channel, DISABLE);
392 CLEAR_BIT(hperh->state, ADC_STATE_BUSY_N);
393
394 return OK;
395 }
OK
Definition: utils.h:55
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
adc_handle_s::hdma
dma_handle_t hdma
Definition: ald_adc.h:357
DISABLE
Definition: type.h:48
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
ADC_STATE_BUSY_N
Definition: ald_adc.h:49
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470
ADC_DISABLE
#define ADC_DISABLE(handle)
Definition: ald_adc.h:402
ald_dma_channel_config
void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state)
Configure channel enable or disable. It will unbind descriptor with channel, when channel has been di...
Definition: ald_dma.c:850

◆ ald_adc_timer_trigger_adc_by_dma()

ald_status_t ald_adc_timer_trigger_adc_by_dma ( adc_timer_config_t * config )

Config Timer trigger adc function.

Parameters
config Pointer to a adc_timer_config_t structure that contains the configuration information for the specified function.
Return values
Status,see ald_status_t.

Definition at line 425 of file ald_adc.c.

426 {
427 config->h_pis.perh = PIS;
428 config->h_pis.init.producer_clk = PIS_CLK_PCLK1;
429 config->h_pis.init.producer_edge = PIS_EDGE_NONE;
430 config->h_pis.init.consumer_clk = PIS_CLK_PCLK2;
431
432 #if defined(ES32F36xx)
433 if (config->p_timer == AD16C4T0)
434 config->h_pis.init.producer_src = PIS_TIMER0_UPDATA;
435 else if (config->p_timer == AD16C4T1)
436 config->h_pis.init.producer_src = PIS_TIMER1_UPDATA;
437 else if (config->p_timer == GP32C4T0)
438 config->h_pis.init.producer_src = PIS_TIMER2_UPDATA;
439 else if (config->p_timer == GP32C4T1)
440 config->h_pis.init.producer_src = PIS_TIMER3_UPDATA;
441 else
442 return ERROR;
443 #elif defined(ES32F39xx) || defined(ES32F336x)
444 if (config->p_timer == GP16C4T0)
445 config->h_pis.init.producer_src = PIS_TIMER0_UPDATA;
446 else if (config->p_timer == GP16C4T1)
447 config->h_pis.init.producer_src = PIS_TIMER1_UPDATA;
448 else if (config->p_timer == GP32C4T0)
449 config->h_pis.init.producer_src = PIS_TIMER2_UPDATA;
450 else if (config->p_timer == GP32C4T1)
451 config->h_pis.init.producer_src = PIS_TIMER3_UPDATA;
452 else
453 return ERROR;
454 #endif
455
456 if (config->p_adc == ADC0)
457 config->h_pis.init.consumer_trig = PIS_CH6_ADC0_NORMAL;
458 else
459 return ERROR;
460
461 ald_pis_create(&config->h_pis);
462
463 /* Initialize TIMER0 */
464 config->h_timer.perh = config->p_timer;
465 config->h_timer.init.prescaler = 0;
466 config->h_timer.init.mode = TIMER_CNT_MODE_UP;
467 config->h_timer.init.period = ((ald_cmu_get_pclk1_clock() / 1000000) * config->time);
468 config->h_timer.init.clk_div = TIMER_CLOCK_DIV1;
469 config->h_timer.init.re_cnt = 0;
470 ald_timer_base_init(&config->h_timer);
471
472 config->h_adc.perh = config->p_adc;
473 config->h_adc.init.align = ADC_DATAALIGN_RIGHT;
474 config->h_adc.init.scan = DISABLE;
475 config->h_adc.init.cont = DISABLE;
476 config->h_adc.init.nch_nr = ADC_NCH_NR_1;
477 config->h_adc.init.disc = ADC_ALL_DISABLE;
478 config->h_adc.init.disc_nr = ADC_DISC_NR_1;
479 config->h_adc.init.data_bit = ADC_CONV_BIT_12;
480 config->h_adc.init.div = ADC_CKDIV_128;
481 config->h_adc.init.nche_sel = ADC_NCHESEL_MODE_ONE;
482 config->h_adc.init.n_ref = config->n_ref;
483 config->h_adc.init.p_ref = config->p_ref;
484 config->h_adc.normal_cplt_cbk = config->cplt_cbk;
485 config->h_adc.insert_cplt_cbk = NULL;
486 config->h_adc.wdg_cbk = NULL;
487 config->h_adc.error_cbk = NULL;
488 config->h_adc.ovr_cbk = NULL;
489 ald_adc_init(&config->h_adc);
490
491
492
493 config->h_adc.perh->CON1 |= 0x10000000;
494 config->config.ch = config->adc_ch;
495 config->config.idx = ADC_NCH_IDX_1;
496 config->config.samp = ADC_SAMPLETIME_4;
497 ald_adc_normal_channel_config(&config->h_adc, &config->config);
498
499 config->h_dma.cplt_cbk = adc_dma_timer_trigger_cplt;
500 config->h_dma.cplt_arg = config;
501 config->h_dma.err_cbk = adc_dma_error;
502 config->h_dma.err_arg = &config->h_adc;
503
504 ald_dma_config_struct(&config->h_dma.config);
505 config->h_dma.perh = DMA0;
506 config->h_dma.config.src = (void *)&config->h_adc.perh->NCHDR;
507 config->h_dma.config.dst = (void *)config->buf;
508 config->h_dma.config.size = config->size;
509 config->h_dma.config.data_width = DMA_DATA_SIZE_HALFWORD;
510 config->h_dma.config.src_inc = DMA_DATA_INC_NONE;
511 config->h_dma.config.dst_inc = DMA_DATA_INC_HALFWORD;
512 config->h_dma.config.msel = config->p_adc == ADC0 ? DMA_MSEL_ADC0 : DMA_MSEL_ADC1;
513 config->h_dma.config.msigsel = DMA_MSIGSEL_ADC;
514 config->h_dma.config.burst = ENABLE;
515 config->h_dma.config.channel = config->dma_ch;
516 ald_dma_config_basic(&config->h_dma);
517
518 SET_BIT(config->h_adc.perh->CON1, ADC_CON1_DMA_MSK);
519 ADC_ENABLE(&config->h_adc);
520 ald_timer_base_start(&config->h_timer);
521
522 return OK;
523 }
adc_timer_config_t::adc_ch
adc_channel_t adc_ch
Definition: ald_adc.h:380
ADC_ENABLE
#define ADC_ENABLE(handle)
Definition: ald_adc.h:401
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
adc_timer_config_t::h_dma
dma_handle_t h_dma
Definition: ald_adc.h:389
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
PIS_TIMER0_UPDATA
Definition: ald_pis.h:128
PIS_TIMER1_UPDATA
Definition: ald_pis.h:138
PIS_TIMER2_UPDATA
Definition: ald_pis.h:148
ADC_CONV_BIT_12
Definition: ald_adc.h:283
timer_base_init_t::re_cnt
uint32_t re_cnt
Definition: ald_timer.h:141
adc_init_t::scan
type_func_t scan
Definition: ald_adc.h:306
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
adc_timer_config_t::size
uint16_t size
Definition: ald_adc.h:376
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
adc_init_t::disc
adc_disc_mode_t disc
Definition: ald_adc.h:309
ald_adc_init
ald_status_t ald_adc_init(adc_handle_t *hperh)
Initializes the ADC peripheral and normal group according to parameters specified in structure "adc_h...
Definition: ald_adc.c:74
adc_init_t::nche_sel
adc_nchesel_t nche_sel
Definition: ald_adc.h:313
timer_base_init_t::clk_div
timer_clock_division_t clk_div
Definition: ald_timer.h:140
adc_handle_s::wdg_cbk
void(* wdg_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:366
DISABLE
Definition: type.h:48
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
PIS_CLK_PCLK1
Definition: ald_pis.h:251
ald_timer_base_init
ald_status_t ald_timer_base_init(timer_handle_t *hperh)
Initializes the TIMER Time base Unit according to the specified parameters in the timer_handle_t and ...
Definition: ald_timer.c:97
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
adc_nch_conf_t::ch
adc_channel_t ch
Definition: ald_adc.h:322
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
adc_init_t::data_bit
adc_conv_bit_t data_bit
Definition: ald_adc.h:311
adc_timer_config_t::n_ref
adc_neg_ref_t n_ref
Definition: ald_adc.h:378
dma_config_t::src
void * src
Definition: ald_dma.h:278
adc_handle_s::ovr_cbk
void(* ovr_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:368
adc_timer_config_t::buf
uint16_t * buf
Definition: ald_adc.h:377
pis_init_t::producer_src
pis_src_t producer_src
Definition: ald_pis.h:396
adc_nch_conf_t::samp
adc_samp_t samp
Definition: ald_adc.h:324
adc_init_t::div
adc_clk_div_t div
Definition: ald_adc.h:312
adc_timer_config_t::time
uint32_t time
Definition: ald_adc.h:375
timer_base_init_t::period
uint32_t period
Definition: ald_timer.h:139
timer_handle_s::init
timer_base_init_t init
Definition: ald_timer.h:184
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
ald_timer_base_start
void ald_timer_base_start(timer_handle_t *hperh)
Starts the TIMER Base generation.
Definition: ald_timer.c:138
TIMER_CLOCK_DIV1
Definition: ald_timer.h:55
adc_init_t::cont
type_func_t cont
Definition: ald_adc.h:307
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
adc_nch_conf_t::idx
adc_nch_idx_t idx
Definition: ald_adc.h:323
adc_dma_timer_trigger_cplt
static void adc_dma_timer_trigger_cplt(void *arg)
DMA transfer complete callback.
Definition: ald_adc.c:402
adc_handle_s::insert_cplt_cbk
void(* insert_cplt_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:365
adc_handle_s::init
adc_init_t init
Definition: ald_adc.h:355
adc_timer_config_t::p_timer
TIMER_TypeDef * p_timer
Definition: ald_adc.h:382
timer_base_init_t::prescaler
uint32_t prescaler
Definition: ald_timer.h:137
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
adc_init_t::align
adc_align_t align
Definition: ald_adc.h:305
adc_timer_config_t::p_adc
ADC_TypeDef * p_adc
Definition: ald_adc.h:383
DMA_MSEL_ADC1
Definition: ald_dma.h:104
TIMER_CNT_MODE_UP
Definition: ald_timer.h:44
adc_init_t::nch_nr
adc_nch_nr_t nch_nr
Definition: ald_adc.h:308
adc_dma_error
static void adc_dma_error(void *arg)
DMA error callback.
Definition: ald_adc.c:1045
PIS_EDGE_NONE
Definition: ald_pis.h:261
PIS_CH6_ADC0_NORMAL
Definition: ald_pis.h:202
pis_init_t::producer_edge
pis_edge_t producer_edge
Definition: ald_pis.h:399
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
adc_timer_config_t::h_timer
timer_handle_t h_timer
Definition: ald_adc.h:390
ald_adc_normal_channel_config
ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t *config)
Configures the the selected channel to be linked to the normal group.
Definition: ald_adc.c:750
ald_cmu_get_pclk1_clock
uint32_t ald_cmu_get_pclk1_clock(void)
Get APB1 clock.
Definition: ald_cmu.c:627
ADC_DISC_NR_1
Definition: ald_adc.h:266
adc_timer_config_t::h_pis
pis_handle_t h_pis
Definition: ald_adc.h:388
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
ald_pis_create
ald_status_t ald_pis_create(pis_handle_t *hperh)
Create the PIS mode according to the specified parameters in the pis_handle_t and create the associat...
Definition: ald_pis.c:45
adc_timer_config_t::cplt_cbk
void(* cplt_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:384
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
adc_init_t::p_ref
adc_pos_ref_t p_ref
Definition: ald_adc.h:315
adc_init_t::n_ref
adc_neg_ref_t n_ref
Definition: ald_adc.h:314
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
PIS_CLK_PCLK2
Definition: ald_pis.h:252
ADC_ALL_DISABLE
Definition: ald_adc.h:257
ADC_NCHESEL_MODE_ONE
Definition: ald_adc.h:77
ADC_SAMPLETIME_4
Definition: ald_adc.h:111
adc_timer_config_t::h_adc
adc_handle_t h_adc
Definition: ald_adc.h:391
adc_timer_config_t::p_ref
adc_pos_ref_t p_ref
Definition: ald_adc.h:379
pis_handle_s::perh
PIS_TypeDef * perh
Definition: ald_pis.h:419
DMA_MSIGSEL_ADC
Definition: ald_dma.h:136
DMA_MSEL_ADC0
Definition: ald_dma.h:82
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
ADC_CKDIV_128
Definition: ald_adc.h:200
timer_base_init_t::mode
timer_cnt_mode_t mode
Definition: ald_timer.h:138
pis_init_t::producer_clk
pis_clock_t producer_clk
Definition: ald_pis.h:398
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
pis_handle_s::init
pis_init_t init
Definition: ald_pis.h:420
adc_timer_config_t::config
adc_nch_conf_t config
Definition: ald_adc.h:392
ADC_NCH_IDX_1
Definition: ald_adc.h:119
pis_init_t::consumer_trig
pis_trig_t consumer_trig
Definition: ald_pis.h:400
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
adc_handle_s::error_cbk
void(* error_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:367
adc_timer_config_t::dma_ch
uint8_t dma_ch
Definition: ald_adc.h:381
adc_init_t::disc_nr
adc_disc_nr_t disc_nr
Definition: ald_adc.h:310
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
PIS_TIMER3_UPDATA
Definition: ald_pis.h:158
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
adc_handle_s::normal_cplt_cbk
void(* normal_cplt_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:364
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
pis_init_t::consumer_clk
pis_clock_t consumer_clk
Definition: ald_pis.h:401
ADC_DATAALIGN_RIGHT
Definition: ald_adc.h:68
ADC_NCH_NR_1
Definition: ald_adc.h:225


ALD User Manual: Peripheral Control functions

Functions
Peripheral Control functions
EASTSOFT ES32F3xx ALD » ADC » ADC Public Functions

Peripheral Control functions. More...

Collaboration diagram for Peripheral Control functions:

Functions

ald_status_t | ald_adc_normal_channel_config (adc_handle_t *hperh, adc_nch_conf_t *config)
Configures the the selected channel to be linked to the normal group. More...
ald_status_t | ald_adc_insert_channel_config (adc_handle_t *hperh, adc_ich_conf_t *config)
Configures the the selected channel to be linked to the insert group. More...
ald_status_t | ald_adc_analog_wdg_config (adc_handle_t *hperh, adc_analog_wdg_conf_t *config)
Configures the analog watchdog. More...
void | ald_adc_interrupt_config (adc_handle_t *hperh, adc_it_t it, type_func_t state)
Enables or disables the specified ADC interrupts. More...
it_status_t | ald_adc_get_it_status (adc_handle_t *hperh, adc_it_t it)
Checks whether the specified ADC interrupt has occurred or not. More...
flag_status_t | ald_adc_get_flag_status (adc_handle_t *hperh, adc_flag_t flag)
Check whether the specified ADC flag is set or not. More...
void | ald_adc_clear_flag_status (adc_handle_t *hperh, adc_flag_t flag)
Clear the specified ADC pending flags. More...

Detailed Description

Peripheral Control functions.

Function Documentation

◆ ald_adc_analog_wdg_config()

ald_status_t ald_adc_analog_wdg_config | ( | adc_handle_t * | hperh,
 |  | adc_analog_wdg_conf_t * | config
 | ) |  |

Configures the analog watchdog.

Parameters
hperh | Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
config | Structure of ADC analog watchdog configuration
Return values
ALD status

Definition at line 870 of file ald_adc.c.

871 {
872 assert_param(IS_ADC_TYPE(hperh->perh));
873 assert_param(IS_ADC_ANALOG_WTD_MODE_TYPE(config->mode));
874 assert_param(IS_FUNC_STATE(config->interrupt));
875 assert_param(IS_HTR_TYPE(config->high_thrd));
876 assert_param(IS_LTR_TYPE(config->low_thrd));
877
878 if ((config->mode == ADC_ANAWTD_SING_NM)
879 || (config->mode == ADC_ANAWTD_SING_IST)
880 || (config->mode == ADC_ANAWTD_SING_NMIST))
881 assert_param(IS_ADC_CHANNELS_TYPE(config->ch));
882
883 if (config->interrupt == DISABLE)
884 ald_adc_interrupt_config(hperh, ADC_IT_AWD, DISABLE);
885 else
886 ald_adc_interrupt_config(hperh, ADC_IT_AWD, ENABLE);
887
888 CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHWDTEN_MSK);
889 CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHWDEN_MSK);
890 CLEAR_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK);
891 hperh->perh->CON0 |= config->mode;
892
893 if (READ_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK))
894 MODIFY_REG(hperh->perh->CON0, ADC_CON0_AWDCH_MSK, config->ch << ADC_CON0_AWDCH_POSS);
895
896 WRITE_REG(hperh->perh->WDTL, config->low_thrd);
897 WRITE_REG(hperh->perh->WDTH, config->high_thrd);
898 SET_BIT(hperh->state, ADC_STATE_BUSY_WDG);
899
900 return OK;
901 }
ADC_ANAWTD_SING_IST
Definition: ald_adc.h:153
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
ADC_ANAWTD_SING_NM
Definition: ald_adc.h:152
ADC_IT_AWD
Definition: ald_adc.h:172
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
DISABLE
Definition: type.h:48
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
adc_analog_wdg_conf_t::interrupt
type_func_t interrupt
Definition: ald_adc.h:333
adc_analog_wdg_conf_t::high_thrd
uint32_t high_thrd
Definition: ald_adc.h:334
adc_analog_wdg_conf_t::mode
adc_ana_wdg_t mode
Definition: ald_adc.h:331
IS_ADC_CHANNELS_TYPE
#define IS_ADC_CHANNELS_TYPE(x)
Definition: ald_adc.h:429
ADC_ANAWTD_SING_NMIST
Definition: ald_adc.h:154
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
ald_adc_interrupt_config
void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state)
Enables or disables the specified ADC interrupts.
Definition: ald_adc.c:913
IS_HTR_TYPE
#define IS_HTR_TYPE(x)
Definition: ald_adc.h:476
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470
adc_analog_wdg_conf_t::ch
adc_channel_t ch
Definition: ald_adc.h:332
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
IS_ADC_ANALOG_WTD_MODE_TYPE
#define IS_ADC_ANALOG_WTD_MODE_TYPE(x)
Definition: ald_adc.h:432
IS_LTR_TYPE
#define IS_LTR_TYPE(x)
Definition: ald_adc.h:477
ADC_STATE_BUSY_WDG
Definition: ald_adc.h:51
adc_analog_wdg_conf_t::low_thrd
uint32_t low_thrd
Definition: ald_adc.h:335

◆ ald_adc_clear_flag_status()

void ald_adc_clear_flag_status | ( | adc_handle_t * | hperh,
 |  | adc_flag_t | flag
 | ) |  |

Clear the specified ADC pending flags.

Parameters
hperh | Pointer to a adc_handle_t structure.
flag | specifies the flag to check. This parameter can be one of the adc_flag_t.
Return values
None

Definition at line 972 of file ald_adc.c.

973 {
974 assert_param(IS_ADC_TYPE(hperh->perh));
975 assert_param(IS_ADC_FLAGS_TYPE(flag));
976
977 WRITE_REG(hperh->perh->CLR, flag);
978 return;
979 }
assert_param
#define assert_param(x)
Definition: type.h:88
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470
IS_ADC_FLAGS_TYPE
#define IS_ADC_FLAGS_TYPE(x)
Definition: ald_adc.h:443

◆ ald_adc_get_flag_status()

flag_status_t ald_adc_get_flag_status | ( | adc_handle_t * | hperh,
 |  | adc_flag_t | flag
 | ) |  |

Check whether the specified ADC flag is set or not.

Parameters
hperh | Pointer to a adc_handle_t structure.
flag | specifies the flag to check. This parameter can be one of the adc_flag_t.
Return values
Status
  • SET
  • RESET

Definition at line 955 of file ald_adc.c.

956 {
957 assert_param(IS_ADC_TYPE(hperh->perh));
958 assert_param(IS_ADC_FLAGS_TYPE(flag));
959
960 if (READ_BIT(hperh->perh->STAT, flag))
961 return SET;
962
963 return RESET;
964 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
RESET
Definition: type.h:38
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470
IS_ADC_FLAGS_TYPE
#define IS_ADC_FLAGS_TYPE(x)
Definition: ald_adc.h:443

◆ ald_adc_get_it_status()

it_status_t ald_adc_get_it_status | ( | adc_handle_t * | hperh,
 |  | adc_it_t | it
 | ) |  |

Checks whether the specified ADC interrupt has occurred or not.

Parameters
hperh | Pointer to a adc_handle_t structure.
it | Specifies the ADC interrupt source to check. This parameter can be one of the adc_it_t.
Return values
Status
  • SET
  • RESET

Definition at line 936 of file ald_adc.c.

937 {
938 assert_param(IS_ADC_TYPE(hperh->perh));
939 assert_param(IS_ADC_IT_TYPE(it));
940
941 if (READ_BIT(hperh->perh->CON0, it))
942 return SET;
943
944 return RESET;
945 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
IS_ADC_IT_TYPE
#define IS_ADC_IT_TYPE(x)
Definition: ald_adc.h:439
RESET
Definition: type.h:38
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470

◆ ald_adc_insert_channel_config()

ald_status_t ald_adc_insert_channel_config | ( | adc_handle_t * | hperh,
 |  | adc_ich_conf_t * | config
 | ) |  |

Configures the the selected channel to be linked to the insert group.

Parameters
hperh | Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
config | Structure of ADC channel for insert group.
Return values
Status,see ald_status_t.

Definition at line 798 of file ald_adc.c.

799 {
800 ald_status_t tmp_status = OK;
801
802 assert_param(IS_ADC_TYPE(hperh->perh));
803 assert_param(IS_ADC_CHANNELS_TYPE(config->ch));
804 assert_param(IS_ADC_ICH_IDX_TYPE(config->idx));
805 assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp));
806 assert_param(IS_ADC_IST_OFFSET_TYPE(config->offset));
807 assert_param(IS_ADC_ICH_NR_TYPE(config->nr));
808 assert_param(IS_FUNC_STATE(config->auto_m));
809
810 MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->nr << ADC_CHSL_ISL_POSS);
811 hperh->perh->ICHS &= ~(0x1f << (uint32_t)((config->idx - 1) << 3));
812 hperh->perh->ICHS |= config->ch << (uint32_t)((config->idx - 1) << 3);
813
814 if (config->auto_m == ENABLE)
815 SET_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK);
816 else
817 CLEAR_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK);
818
819 if (hperh->init.disc == ADC_ICH_DISC_EN) {
820 if (config->auto_m == DISABLE) {
821 SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK);
822 }
823 else {
824 hperh->state |= ADC_STATE_ERROR;
825 hperh->error_code |= ADC_ERROR_INTERNAL;
826 tmp_status = ERROR;
827 }
828 }
829
830 if (config->ch < 8) {
831 hperh->perh->SMPT1 &= ~(0x0f << (uint32_t)(config->ch << 2));
832 hperh->perh->SMPT1 |= config->samp << (uint32_t)(config->ch << 2);
833 }
834 else if (config->ch < 16) {
835 hperh->perh->SMPT2 &= ~(0x0f << (uint32_t)((config->ch - 8) << 2));
836 hperh->perh->SMPT2 |= config->samp << (uint32_t)((config->ch - 8) << 2);
837 }
838 else {
839 hperh->perh->SMPT3 &= ~(0x0f << (uint32_t)((config->ch - 16) << 2));
840 hperh->perh->SMPT3 |= config->samp << (uint32_t)((config->ch - 16) << 2);
841 }
842
843 switch (config->idx) {
844 case ADC_ICH_IDX_1:
845 hperh->perh->ICHOFF1 = config->offset;
846 break;
847 case ADC_ICH_IDX_2:
848 hperh->perh->ICHOFF2 = config->offset;
849 break;
850 case ADC_ICH_IDX_3:
851 hperh->perh->ICHOFF3 = config->offset;
852 break;
853 case ADC_ICH_IDX_4:
854 hperh->perh->ICHOFF4 = config->offset;
855 break;
856 default:
857 break;
858 }
859
860 return tmp_status;
861 }
IS_ADC_IST_OFFSET_TYPE
#define IS_ADC_IST_OFFSET_TYPE(x)
Definition: ald_adc.h:475
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
ADC_ICH_IDX_1
Definition: ald_adc.h:141
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
adc_init_t::disc
adc_disc_mode_t disc
Definition: ald_adc.h:309
adc_ich_conf_t::ch
adc_channel_t ch
Definition: ald_adc.h:342
ADC_STATE_ERROR
Definition: ald_adc.h:48
DISABLE
Definition: type.h:48
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
adc_ich_conf_t::samp
adc_samp_t samp
Definition: ald_adc.h:344
adc_ich_conf_t::auto_m
type_func_t auto_m
Definition: ald_adc.h:347
adc_handle_s::init
adc_init_t init
Definition: ald_adc.h:355
adc_ich_conf_t::nr
adc_ich_nr_t nr
Definition: ald_adc.h:346
adc_ich_conf_t::idx
adc_ich_idx_t idx
Definition: ald_adc.h:343
IS_ADC_CHANNELS_TYPE
#define IS_ADC_CHANNELS_TYPE(x)
Definition: ald_adc.h:429
IS_ADC_SAMPLING_TIMES_TYPE
#define IS_ADC_SAMPLING_TIMES_TYPE(x)
Definition: ald_adc.h:425
ADC_ICH_IDX_3
Definition: ald_adc.h:143
ADC_ICH_DISC_EN
Definition: ald_adc.h:259
ADC_ERROR_INTERNAL
Definition: ald_adc.h:59
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
ADC_ICH_IDX_4
Definition: ald_adc.h:144
adc_ich_conf_t::offset
uint32_t offset
Definition: ald_adc.h:345
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
IS_ADC_ICH_NR_TYPE
#define IS_ADC_ICH_NR_TYPE(x)
Definition: ald_adc.h:464
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
ERROR
Definition: utils.h:56
adc_handle_s::error_code
adc_error_t error_code
Definition: ald_adc.h:362
ADC_ICH_IDX_2
Definition: ald_adc.h:142
IS_ADC_ICH_IDX_TYPE
#define IS_ADC_ICH_IDX_TYPE(x)
Definition: ald_adc.h:423

◆ ald_adc_interrupt_config()

void ald_adc_interrupt_config | ( | adc_handle_t * | hperh,
 |  | adc_it_t | it,
 |  | type_func_t | state
 | ) |  |

Enables or disables the specified ADC interrupts.

Parameters
hperh | Pointer to a adc_handle_t structure.
it | Specifies the ADC interrupt sources to be enabled or disabled. This parameter can be one of the adc_it_t.
state New status
  • ENABLE
  • DISABLE
Return values
None

Definition at line 913 of file ald_adc.c.

914 {
915 assert_param(IS_ADC_TYPE(hperh->perh));
916 assert_param(IS_ADC_IT_TYPE(it));
917 assert_param(IS_FUNC_STATE(state));
918
919 if (state == ENABLE)
920 SET_BIT(hperh->perh->CON0, it);
921 else
922 CLEAR_BIT(hperh->perh->CON0, it);
923
924 return;
925 }
ENABLE
Definition: type.h:49
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
IS_ADC_IT_TYPE
#define IS_ADC_IT_TYPE(x)
Definition: ald_adc.h:439
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_adc_normal_channel_config()

ald_status_t ald_adc_normal_channel_config | ( | adc_handle_t * | hperh,
 |  | adc_nch_conf_t * | config
 | ) |  |

Configures the the selected channel to be linked to the normal group.

Parameters
hperh | Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
config | Structure of ADC channel for normal group.
Return values
Status,see ald_status_t.

Definition at line 750 of file ald_adc.c.

751 {
752 assert_param(IS_ADC_TYPE(hperh->perh));
753 assert_param(IS_ADC_CHANNELS_TYPE(config->ch));
754 assert_param(IS_ADC_NCH_IDX_TYPE(config->idx));
755 assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp));
756
757 if (config->idx <= ADC_NCH_IDX_4 ) {
758 hperh->perh->NCHS1 &= ~(0x1f << (uint32_t)((config->idx - 1) << 3));
759 hperh->perh->NCHS1 |= (config->ch << (uint32_t)((config->idx - 1) << 3));
760 }
761 else if (config->idx <= ADC_NCH_IDX_8) {
762 hperh->perh->NCHS2 &= ~(0x1f << (uint32_t)((config->idx - 5) << 3));
763 hperh->perh->NCHS2 |= (config->ch << (uint32_t)((config->idx - 5) << 3));
764 }
765 else if (config->idx <= ADC_NCH_IDX_12) {
766 hperh->perh->NCHS3 &= ~(0x1f << (uint32_t)((config->idx - 9) << 3));
767 hperh->perh->NCHS3 |= (config->ch << (uint32_t)((config->idx - 9) << 3));
768 }
769 else {
770 hperh->perh->NCHS4 &= ~(0x1f << (uint32_t)((config->idx - 13) << 3));
771 hperh->perh->NCHS4 |= (config->ch << (uint32_t)((config->idx - 13) << 3));
772 }
773
774 if (config->ch < 8) {
775 hperh->perh->SMPT1 &= ~(0x0f << (uint32_t)(config->ch << 2));
776 hperh->perh->SMPT1 |= config->samp << (uint32_t)(config->ch << 2);
777 }
778 else if (config->ch < 16) {
779 hperh->perh->SMPT2 &= ~(0x0f << (uint32_t)((config->ch - 8) << 2));
780 hperh->perh->SMPT2 |= config->samp << (uint32_t)((config->ch - 8) << 2);
781 }
782 else {
783 hperh->perh->SMPT3 &= ~(0x0f << (uint32_t)((config->ch - 16) << 2));
784 hperh->perh->SMPT3 |= config->samp << (uint32_t)((config->ch - 16) << 2);
785 }
786
787 return OK;
788 }
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
adc_nch_conf_t::ch
adc_channel_t ch
Definition: ald_adc.h:322
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
adc_nch_conf_t::samp
adc_samp_t samp
Definition: ald_adc.h:324
adc_nch_conf_t::idx
adc_nch_idx_t idx
Definition: ald_adc.h:323
IS_ADC_CHANNELS_TYPE
#define IS_ADC_CHANNELS_TYPE(x)
Definition: ald_adc.h:429
IS_ADC_SAMPLING_TIMES_TYPE
#define IS_ADC_SAMPLING_TIMES_TYPE(x)
Definition: ald_adc.h:425
ADC_NCH_IDX_8
Definition: ald_adc.h:126
ADC_NCH_IDX_12
Definition: ald_adc.h:130
IS_ADC_NCH_IDX_TYPE
#define IS_ADC_NCH_IDX_TYPE(x)
Definition: ald_adc.h:424
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470
ADC_NCH_IDX_4
Definition: ald_adc.h:122


ALD User Manual: Peripheral State functions

Functions
Peripheral State functions
EASTSOFT ES32F3xx ALD » ADC » ADC Public Functions

Peripheral State functions. More...

Collaboration diagram for Peripheral State functions:

Functions

uint32_t | ald_adc_get_state (adc_handle_t *hperh)
return the ADC state More...
uint32_t | ald_adc_get_error (adc_handle_t *hperh)
Return the ADC error code. More...

Detailed Description

Peripheral State functions.

Function Documentation

◆ ald_adc_get_error()

uint32_t ald_adc_get_error ( adc_handle_t * hperh )

Return the ADC error code.

Parameters
hperh Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
Return values
ADC Error Code

Definition at line 1006 of file ald_adc.c.

1007 {
1008 return hperh->error_code;
1009 }
adc_handle_s::error_code
adc_error_t error_code
Definition: ald_adc.h:362

◆ ald_adc_get_state()

uint32_t ald_adc_get_state ( adc_handle_t * hperh )

return the ADC state

Parameters
hperh Pointer to a adc_handle_t structure that contains the configuration information for the specified ADC module.
Return values
state

Definition at line 995 of file ald_adc.c.

996 {
997 return hperh->state;
998 }
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361


ALD User Manual: ADC Private Functions

Functions
ADC Private Functions
EASTSOFT ES32F3xx ALD » ADC
Collaboration diagram for ADC Private Functions:

Functions

static void | adc_dma_normal_conv_cplt (void *arg)
DMA transfer complete callback. More...
static void | adc_dma_error (void *arg)
DMA error callback. More...

Detailed Description

Function Documentation

◆ adc_dma_error()

static void adc_dma_error ( void * arg )
static

DMA error callback.

Parameters
arg argument of the call back.
Return values
None

Definition at line 1045 of file ald_adc.c.

1046 {
1047 adc_handle_t *hperh = (adc_handle_t *)arg;
1048 hperh->state |= ADC_STATE_ERROR;
1049 hperh->error_code |= ADC_ERROR_DMA;
1050
1051 if (hperh->error_cbk)
1052 hperh->error_cbk(hperh);
1053 }
adc_handle_s
ADC handle Structure definition.
Definition: ald_adc.h:353
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
ADC_ERROR_DMA
Definition: ald_adc.h:61
ADC_STATE_ERROR
Definition: ald_adc.h:48
adc_handle_s::error_cbk
void(* error_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:367
adc_handle_s::error_code
adc_error_t error_code
Definition: ald_adc.h:362

◆ adc_dma_normal_conv_cplt()

static void adc_dma_normal_conv_cplt ( void * arg )
static

DMA transfer complete callback.

Parameters
arg argument of the call back.
Return values
None

Definition at line 1029 of file ald_adc.c.

1030 {
1031 adc_handle_t *hperh = (adc_handle_t *)arg;
1032
1033 CLEAR_BIT(hperh->perh->CON1, ADC_CON1_DMA_MSK);
1034
1035 if (hperh->normal_cplt_cbk)
1036 hperh->normal_cplt_cbk(hperh);
1037
1038 }
adc_handle_s
ADC handle Structure definition.
Definition: ald_adc.h:353
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
adc_handle_s::normal_cplt_cbk
void(* normal_cplt_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:364


ALD User Manual: ADC Pubulic Types

Data Structures | Typedefs | Enumerations
ADC Pubulic Types
EASTSOFT ES32F3xx ALD » ADC
Collaboration diagram for ADC Pubulic Types:

Data Structures

struct | adc_init_t
ADC trigger conversion mode. More...
struct | adc_nch_conf_t
Structure definition of ADC channel for normal group. More...
struct | adc_analog_wdg_conf_t
ADC Configuration analog watchdog definition. More...
struct | adc_ich_conf_t
ADC Configuration insert Channel structure definition. More...
struct | adc_handle_s
ADC handle Structure definition. More...
struct | adc_timer_config_t
Timer trigger adc config structure definition. More...

Typedefs

typedef struct adc_handle_s adc_handle_t
ADC handle Structure definition. More...

Enumerations

enum adc_state_t {
ADC_STATE_RESET = 0x0U, ADC_STATE_READY = 0x1U, ADC_STATE_BUSY = 0x2U, ADC_STATE_TIMEOUT = 0x4U,
ADC_STATE_ERROR = 0x8U, ADC_STATE_BUSY_N = 0x10U, ADC_STATE_BUSY_I = 0x20U, ADC_STATE_BUSY_WDG = 0x40U
}
ADC State structures definition. More...
enum | adc_error_t { ADC_ERROR_NONE = 0x0U, ADC_ERROR_INTERNAL = 0x1U, ADC_ERROR_OVR = 0x2U, ADC_ERROR_DMA = 0x4U }
ADC Error Code. More...
enum | adc_align_t { ADC_DATAALIGN_RIGHT = 0x0U, ADC_DATAALIGN_LEFT = 0x1U }
ADC data alignment. More...
enum | adc_nchesel_t { ADC_NCHESEL_MODE_ALL = 0x0U, ADC_NCHESEL_MODE_ONE = 0x1U }
ADC config hannal trigger the EOC IT mode. More...
enum adc_channel_t {
ADC_CHANNEL_0 = 0x0U, ADC_CHANNEL_1 = 0x1U, ADC_CHANNEL_2 = 0x2U, ADC_CHANNEL_3 = 0x3U,
ADC_CHANNEL_4 = 0x4U, ADC_CHANNEL_5 = 0x5U, ADC_CHANNEL_6 = 0x6U, ADC_CHANNEL_7 = 0x7U,
ADC_CHANNEL_8 = 0x8U, ADC_CHANNEL_9 = 0x9U, ADC_CHANNEL_10 = 0xAU, ADC_CHANNEL_11 = 0xBU,
ADC_CHANNEL_12 = 0xCU, ADC_CHANNEL_13 = 0xDU, ADC_CHANNEL_14 = 0xEU, ADC_CHANNEL_15 = 0xFU,
ADC_CHANNEL_16 = 0x10U, ADC_CHANNEL_17 = 0x11U, ADC_CHANNEL_18 = 0x12U
}
ADC channels. More...
enum | adc_samp_t { ADC_SAMPLETIME_1 = 0x0U, ADC_SAMPLETIME_2 = 0x1U, ADC_SAMPLETIME_4 = 0x2U, ADC_SAMPLETIME_15 = 0x3U }
ADC sampling times. More...
enum adc_nch_idx_t {
ADC_NCH_IDX_1 = 0x1U, ADC_NCH_IDX_2 = 0x2U, ADC_NCH_IDX_3 = 0x3U, ADC_NCH_IDX_4 = 0x4U,
ADC_NCH_IDX_5 = 0x5U, ADC_NCH_IDX_6 = 0x6U, ADC_NCH_IDX_7 = 0x7U, ADC_NCH_IDX_8 = 0x8U,
ADC_NCH_IDX_9 = 0x9U, ADC_NCH_IDX_10 = 0xAU, ADC_NCH_IDX_11 = 0xBU, ADC_NCH_IDX_12 = 0xCU,
ADC_NCH_IDX_13 = 0xDU, ADC_NCH_IDX_14 = 0xEU, ADC_NCH_IDX_15 = 0xFU, ADC_NCH_IDX_16 = 0x10U
}
ADC index channel in normal group. More...
enum | adc_ich_idx_t { ADC_ICH_IDX_1 = 0x1U, ADC_ICH_IDX_2 = 0x2U, ADC_ICH_IDX_3 = 0x3U, ADC_ICH_IDX_4 = 0x4U }
ADC index channel in insert group. More...
enum adc_ana_wdg_t {
ADC_ANAWTD_NONE = 0x0U, ADC_ANAWTD_SING_NM = 0x800200U, ADC_ANAWTD_SING_IST = 0x400200U, ADC_ANAWTD_SING_NMIST = 0xC00200U,
ADC_ANAWTD_ALL_NM = 0x800000U, ADC_ANAWTD_ALL_IST = 0x400000U, ADC_ANAWTD_ALL_NMIST = 0xC00000U
}
ADC analog watchdog mode. More...
enum | adc_event_type_t { ADC_AWD_EVENT = (1U << 0) }
ADC Event type. More...
enum | adc_it_t { ADC_IT_NCH = (1U << 5), ADC_IT_AWD = (1U << 6), ADC_IT_ICH = (1U << 7), ADC_IT_OVR = (1U << 26) }
ADC interrupts definition. More...
enum adc_flag_t {
ADC_FLAG_AWD = (1U << 0), ADC_FLAG_NCH = (1U << 1), ADC_FLAG_ICH = (1U << 2), ADC_FLAG_OVR = (1U << 3),
ADC_FLAG_NCHS = (1U << 8), ADC_FLAG_ICHS = (1U << 9)
}
ADC flags definition. More...
enum adc_clk_div_t {
ADC_CKDIV_1 = 0x0U, ADC_CKDIV_2 = 0x1U, ADC_CKDIV_4 = 0x2U, ADC_CKDIV_8 = 0x3U,
ADC_CKDIV_16 = 0x4U, ADC_CKDIV_32 = 0x5U, ADC_CKDIV_64 = 0x6U, ADC_CKDIV_128 = 0x7U
}
ADC CLD DIV definition. More...
enum | adc_neg_ref_t { ADC_NEG_REF_VSS = 0x0U, ADC_NEG_REF_VREFN = 0x1U }
ADC negative reference voltage definition. More...
enum | adc_pos_ref_t { ADC_POS_REF_VDD = 0x0U, ADC_POS_REF_2V = 0x1U, ADC_POS_REF_VREEFP = 0x2U, ADC_POS_REF_VREEFP_BUF = 0x3U }
ADC positive reference voltage definition. More...
enum adc_nch_nr_t {
ADC_NCH_NR_1 = 0x0U, ADC_NCH_NR_2 = 0x1U, ADC_NCH_NR_3 = 0x2U, ADC_NCH_NR_4 = 0x3U,
ADC_NCH_NR_5 = 0x4U, ADC_NCH_NR_6 = 0x5U, ADC_NCH_NR_7 = 0x6U, ADC_NCH_NR_8 = 0x7U,
ADC_NCH_NR_9 = 0x8U, ADC_NCH_NR_10 = 0x9U, ADC_NCH_NR_11 = 0xAU, ADC_NCH_NR_12 = 0xBU,
ADC_NCH_NR_13 = 0xCU, ADC_NCH_NR_14 = 0xDU, ADC_NCH_NR_15 = 0xEU, ADC_NCH_NR_16 = 0xFU
}
ADC numbers of normal conversion channals. More...
enum | adc_ich_nr_t { ADC_ICH_NR_1 = 0x0U, ADC_ICH_NR_2 = 0x1U, ADC_ICH_NR_3 = 0x2U, ADC_ICH_NR_4 = 0x3U }
ADC numbers of insert conversion channals. More...
enum | adc_disc_mode_t { ADC_ALL_DISABLE = 0x0U, ADC_NCH_DISC_EN = 0x1U, ADC_ICH_DISC_EN = 0x2U }
ADC discontinuous mode choose. More...
enum adc_disc_nr_t {
ADC_DISC_NR_1 = 0x0U, ADC_DISC_NR_2 = 0x1U, ADC_DISC_NR_3 = 0x2U, ADC_DISC_NR_4 = 0x3U,
ADC_DISC_NR_5 = 0x4U, ADC_DISC_NR_6 = 0x5U, ADC_DISC_NR_7 = 0x6U, ADC_DISC_NR_8 = 0x7U
}
ADC numbers of channals in discontinuous conversion mode. More...
enum | adc_conv_bit_t { ADC_CONV_BIT_6 = 0x0U, ADC_CONV_BIT_8 = 0x1U, ADC_CONV_BIT_10 = 0x2U, ADC_CONV_BIT_12 = 0x3U }
ADC resolution of conversion. More...
enum | adc_ets_t { ADC_ETS_DISABLE = 0x0U, ADC_ETS_RISE = 0x1U, ADC_ETS_FALL = 0x2U, ADC_ETS_RISE_FALL = 0x3U }
ADC external trigger mode choose. More...

Detailed Description

Typedef Documentation

◆ adc_handle_t

typedef struct adc_handle_s adc_handle_t

ADC handle Structure definition.

Enumeration Type Documentation

◆ adc_align_t

enum adc_align_t

ADC data alignment.

Enumerator
ADC_DATAALIGN_RIGHT | ADC data alignment right
ADC_DATAALIGN_LEFT | ADC data alignment left

Definition at line 67 of file ald_adc.h.

67 {
68 ADC_DATAALIGN_RIGHT = 0x0U,
69 ADC_DATAALIGN_LEFT = 0x1U,
70 } adc_align_t;
ADC_DATAALIGN_LEFT
Definition: ald_adc.h:69
adc_align_t
adc_align_t
ADC data alignment.
Definition: ald_adc.h:67
ADC_DATAALIGN_RIGHT
Definition: ald_adc.h:68

◆ adc_ana_wdg_t

enum adc_ana_wdg_t

ADC analog watchdog mode.

Enumerator
ADC_ANAWTD_NONE | No watch dog
ADC_ANAWTD_SING_NM | One normal channel watch dog
ADC_ANAWTD_SING_IST | One insert channel Injec watch dog
ADC_ANAWTD_SING_NMIST | One normal and insert channel watch dog
ADC_ANAWTD_ALL_NM | All normal channel watch dog
ADC_ANAWTD_ALL_IST | All insert channel watch dog
ADC_ANAWTD_ALL_NMIST | All normal and insert channel watch dog

Definition at line 150 of file ald_adc.h.

150 {
151 ADC_ANAWTD_NONE = 0x0U,
152 ADC_ANAWTD_SING_NM = 0x800200U,
153 ADC_ANAWTD_SING_IST = 0x400200U,
154 ADC_ANAWTD_SING_NMIST = 0xC00200U,
155 ADC_ANAWTD_ALL_NM = 0x800000U,
156 ADC_ANAWTD_ALL_IST = 0x400000U,
157 ADC_ANAWTD_ALL_NMIST = 0xC00000U,
158 } adc_ana_wdg_t;
ADC_ANAWTD_SING_IST
Definition: ald_adc.h:153
ADC_ANAWTD_SING_NM
Definition: ald_adc.h:152
ADC_ANAWTD_ALL_IST
Definition: ald_adc.h:156
adc_ana_wdg_t
adc_ana_wdg_t
ADC analog watchdog mode.
Definition: ald_adc.h:150
ADC_ANAWTD_ALL_NM
Definition: ald_adc.h:155
ADC_ANAWTD_SING_NMIST
Definition: ald_adc.h:154
ADC_ANAWTD_ALL_NMIST
Definition: ald_adc.h:157
ADC_ANAWTD_NONE
Definition: ald_adc.h:151

◆ adc_channel_t

enum adc_channel_t

ADC channels.

Enumerator
ADC_CHANNEL_0 | ADC channel 0
ADC_CHANNEL_1 | ADC channel 1
ADC_CHANNEL_2 | ADC channel 2
ADC_CHANNEL_3 | ADC channel 3
ADC_CHANNEL_4 | ADC channel 4
ADC_CHANNEL_5 | ADC channel 5
ADC_CHANNEL_6 | ADC channel 6
ADC_CHANNEL_7 | ADC channel 7
ADC_CHANNEL_8 | ADC channel 8
ADC_CHANNEL_9 | ADC channel 9
ADC_CHANNEL_10 | ADC channel 10
ADC_CHANNEL_11 | ADC channel 11
ADC_CHANNEL_12 | ADC channel 12
ADC_CHANNEL_13 | ADC channel 13
ADC_CHANNEL_14 | ADC channel 14
ADC_CHANNEL_15 | ADC channel 15
ADC_CHANNEL_16 | ADC channel 16
ADC_CHANNEL_17 | ADC channel 17
ADC_CHANNEL_18 | ADC channel 18

Definition at line 83 of file ald_adc.h.

83 {
84 ADC_CHANNEL_0 = 0x0U,
85 ADC_CHANNEL_1 = 0x1U,
86 ADC_CHANNEL_2 = 0x2U,
87 ADC_CHANNEL_3 = 0x3U,
88 ADC_CHANNEL_4 = 0x4U,
89 ADC_CHANNEL_5 = 0x5U,
90 ADC_CHANNEL_6 = 0x6U,
91 ADC_CHANNEL_7 = 0x7U,
92 ADC_CHANNEL_8 = 0x8U,
93 ADC_CHANNEL_9 = 0x9U,
94 ADC_CHANNEL_10 = 0xAU,
95 ADC_CHANNEL_11 = 0xBU,
96 ADC_CHANNEL_12 = 0xCU,
97 ADC_CHANNEL_13 = 0xDU,
98 ADC_CHANNEL_14 = 0xEU,
99 ADC_CHANNEL_15 = 0xFU,
100 ADC_CHANNEL_16 = 0x10U,
101 ADC_CHANNEL_17 = 0x11U,
102 ADC_CHANNEL_18 = 0x12U,
103 } adc_channel_t;
adc_channel_t
adc_channel_t
ADC channels.
Definition: ald_adc.h:83
ADC_CHANNEL_15
Definition: ald_adc.h:99
ADC_CHANNEL_2
Definition: ald_adc.h:86
ADC_CHANNEL_16
Definition: ald_adc.h:100
ADC_CHANNEL_3
Definition: ald_adc.h:87
ADC_CHANNEL_8
Definition: ald_adc.h:92
ADC_CHANNEL_7
Definition: ald_adc.h:91
ADC_CHANNEL_10
Definition: ald_adc.h:94
ADC_CHANNEL_4
Definition: ald_adc.h:88
ADC_CHANNEL_14
Definition: ald_adc.h:98
ADC_CHANNEL_12
Definition: ald_adc.h:96
ADC_CHANNEL_0
Definition: ald_adc.h:84
ADC_CHANNEL_5
Definition: ald_adc.h:89
ADC_CHANNEL_6
Definition: ald_adc.h:90
ADC_CHANNEL_13
Definition: ald_adc.h:97
ADC_CHANNEL_18
Definition: ald_adc.h:102
ADC_CHANNEL_17
Definition: ald_adc.h:101
ADC_CHANNEL_1
Definition: ald_adc.h:85
ADC_CHANNEL_11
Definition: ald_adc.h:95
ADC_CHANNEL_9
Definition: ald_adc.h:93

◆ adc_clk_div_t

enum adc_clk_div_t

ADC CLD DIV definition.

Enumerator
ADC_CKDIV_1 | ADC CLK DIV 1
ADC_CKDIV_2 | ADC CLK DIV 2
ADC_CKDIV_4 | ADC CLK DIV 4
ADC_CKDIV_8 | ADC CLK DIV 8
ADC_CKDIV_16 | ADC CLK DIV 16
ADC_CKDIV_32 | ADC CLK DIV 32
ADC_CKDIV_64 | ADC CLK DIV 64
ADC_CKDIV_128 | ADC CLK DIV 128

Definition at line 192 of file ald_adc.h.

192 {
193 ADC_CKDIV_1 = 0x0U,
194 ADC_CKDIV_2 = 0x1U,
195 ADC_CKDIV_4 = 0x2U,
196 ADC_CKDIV_8 = 0x3U,
197 ADC_CKDIV_16 = 0x4U,
198 ADC_CKDIV_32 = 0x5U,
199 ADC_CKDIV_64 = 0x6U,
200 ADC_CKDIV_128 = 0x7U,
201 } adc_clk_div_t;
ADC_CKDIV_4
Definition: ald_adc.h:195
ADC_CKDIV_16
Definition: ald_adc.h:197
ADC_CKDIV_1
Definition: ald_adc.h:193
ADC_CKDIV_8
Definition: ald_adc.h:196
adc_clk_div_t
adc_clk_div_t
ADC CLD DIV definition.
Definition: ald_adc.h:192
ADC_CKDIV_32
Definition: ald_adc.h:198
ADC_CKDIV_2
Definition: ald_adc.h:194
ADC_CKDIV_64
Definition: ald_adc.h:199
ADC_CKDIV_128
Definition: ald_adc.h:200

◆ adc_conv_bit_t

enum adc_conv_bit_t

ADC resolution of conversion.

Enumerator
ADC_CONV_BIT_6 | ADC resolution of conversion 6
ADC_CONV_BIT_8 | ADC resolution of conversion 8
ADC_CONV_BIT_10 | ADC resolution of conversion 10
ADC_CONV_BIT_12 | ADC resolution of conversion 12

Definition at line 279 of file ald_adc.h.

279 {
280 ADC_CONV_BIT_6 = 0x0U,
281 ADC_CONV_BIT_8 = 0x1U,
282 ADC_CONV_BIT_10 = 0x2U,
283 ADC_CONV_BIT_12 = 0x3U,
284 } adc_conv_bit_t;
ADC_CONV_BIT_12
Definition: ald_adc.h:283
ADC_CONV_BIT_6
Definition: ald_adc.h:280
ADC_CONV_BIT_8
Definition: ald_adc.h:281
adc_conv_bit_t
adc_conv_bit_t
ADC resolution of conversion.
Definition: ald_adc.h:279
ADC_CONV_BIT_10
Definition: ald_adc.h:282

◆ adc_disc_mode_t

enum adc_disc_mode_t

ADC discontinuous mode choose.

Enumerator
ADC_ALL_DISABLE | ADC discontinuous mode all disable
ADC_NCH_DISC_EN | ADC normal channel discontinuous mode enable
ADC_ICH_DISC_EN | ADC insert channel discontinuous mode enable

Definition at line 256 of file ald_adc.h.

256 {
257 ADC_ALL_DISABLE = 0x0U,
258 ADC_NCH_DISC_EN = 0x1U,
259 ADC_ICH_DISC_EN = 0x2U,
260 } adc_disc_mode_t;
ADC_ICH_DISC_EN
Definition: ald_adc.h:259
adc_disc_mode_t
adc_disc_mode_t
ADC discontinuous mode choose.
Definition: ald_adc.h:256
ADC_ALL_DISABLE
Definition: ald_adc.h:257
ADC_NCH_DISC_EN
Definition: ald_adc.h:258

◆ adc_disc_nr_t

enum adc_disc_nr_t

ADC numbers of channals in discontinuous conversion mode.

Enumerator
ADC_DISC_NR_1 | ADC number of discontinuous conversion 1
ADC_DISC_NR_2 | ADC number of discontinuous conversion 2
ADC_DISC_NR_3 | ADC number of discontinuous conversion 3
ADC_DISC_NR_4 | ADC number of discontinuous conversion 4
ADC_DISC_NR_5 | ADC number of discontinuous conversion 5
ADC_DISC_NR_6 | ADC number of discontinuous conversion 6
ADC_DISC_NR_7 | ADC number of discontinuous conversion 7
ADC_DISC_NR_8 | ADC number of discontinuous conversion 8

Definition at line 265 of file ald_adc.h.

265 {
266 ADC_DISC_NR_1 = 0x0U,
267 ADC_DISC_NR_2 = 0x1U,
268 ADC_DISC_NR_3 = 0x2U,
269 ADC_DISC_NR_4 = 0x3U,
270 ADC_DISC_NR_5 = 0x4U,
271 ADC_DISC_NR_6 = 0x5U,
272 ADC_DISC_NR_7 = 0x6U,
273 ADC_DISC_NR_8 = 0x7U,
274 } adc_disc_nr_t;
ADC_DISC_NR_3
Definition: ald_adc.h:268
ADC_DISC_NR_2
Definition: ald_adc.h:267
ADC_DISC_NR_4
Definition: ald_adc.h:269
ADC_DISC_NR_7
Definition: ald_adc.h:272
ADC_DISC_NR_8
Definition: ald_adc.h:273
ADC_DISC_NR_1
Definition: ald_adc.h:266
ADC_DISC_NR_5
Definition: ald_adc.h:270
ADC_DISC_NR_6
Definition: ald_adc.h:271
adc_disc_nr_t
adc_disc_nr_t
ADC numbers of channals in discontinuous conversion mode.
Definition: ald_adc.h:265

◆ adc_error_t

enum adc_error_t

ADC Error Code.

Enumerator
ADC_ERROR_NONE | No error
ADC_ERROR_INTERNAL | ADC IP internal error
ADC_ERROR_OVR | Overrun error
ADC_ERROR_DMA | DMA transfer error

Definition at line 57 of file ald_adc.h.

57 {
58 ADC_ERROR_NONE = 0x0U,
59 ADC_ERROR_INTERNAL = 0x1U,
60 ADC_ERROR_OVR = 0x2U,
61 ADC_ERROR_DMA = 0x4U,
62 } adc_error_t;
ADC_ERROR_DMA
Definition: ald_adc.h:61
ADC_ERROR_OVR
Definition: ald_adc.h:60
adc_error_t
adc_error_t
ADC Error Code.
Definition: ald_adc.h:57
ADC_ERROR_INTERNAL
Definition: ald_adc.h:59
ADC_ERROR_NONE
Definition: ald_adc.h:58

◆ adc_ets_t

enum adc_ets_t

ADC external trigger mode choose.

Enumerator
ADC_ETS_DISABLE | ADC external trigger function disable
ADC_ETS_RISE | rise edge trigger ADC
ADC_ETS_FALL | fall edge trigger ADC
ADC_ETS_RISE_FALL | both rise and fall edge trigger ADC

Definition at line 289 of file ald_adc.h.

289 {
290 ADC_ETS_DISABLE = 0x0U,
291 ADC_ETS_RISE = 0x1U,
292 ADC_ETS_FALL = 0x2U,
293 ADC_ETS_RISE_FALL = 0x3U,
294 } adc_ets_t;
adc_ets_t
adc_ets_t
ADC external trigger mode choose.
Definition: ald_adc.h:289
ADC_ETS_RISE
Definition: ald_adc.h:291
ADC_ETS_DISABLE
Definition: ald_adc.h:290
ADC_ETS_FALL
Definition: ald_adc.h:292
ADC_ETS_RISE_FALL
Definition: ald_adc.h:293

◆ adc_event_type_t

enum adc_event_type_t

ADC Event type.

Enumerator
ADC_AWD_EVENT

ADC analog watch dog event

Definition at line 163 of file ald_adc.h.

163 {
164 ADC_AWD_EVENT = (1U << 0),
165 } adc_event_type_t;
adc_event_type_t
adc_event_type_t
ADC Event type.
Definition: ald_adc.h:163
ADC_AWD_EVENT
Definition: ald_adc.h:164

◆ adc_flag_t

enum adc_flag_t

ADC flags definition.

Enumerator
ADC_FLAG_AWD | ADC flag awd
ADC_FLAG_NCH | ADC flag normal mode complete
ADC_FLAG_ICH | ADC flag insert mode complete
ADC_FLAG_OVR | ADC flag ovr
ADC_FLAG_NCHS | ADC flag normal start
ADC_FLAG_ICHS | ADC flag insert start

Definition at line 180 of file ald_adc.h.

180 {
181 ADC_FLAG_AWD = (1U << 0),
182 ADC_FLAG_NCH = (1U << 1),
183 ADC_FLAG_ICH = (1U << 2),
184 ADC_FLAG_OVR = (1U << 3),
185 ADC_FLAG_NCHS = (1U << 8),
186 ADC_FLAG_ICHS = (1U << 9),
187 } adc_flag_t;
adc_flag_t
adc_flag_t
ADC flags definition.
Definition: ald_adc.h:180
ADC_FLAG_ICH
Definition: ald_adc.h:183
ADC_FLAG_AWD
Definition: ald_adc.h:181
ADC_FLAG_ICHS
Definition: ald_adc.h:186
ADC_FLAG_OVR
Definition: ald_adc.h:184
ADC_FLAG_NCHS
Definition: ald_adc.h:185
ADC_FLAG_NCH
Definition: ald_adc.h:182

◆ adc_ich_idx_t

enum adc_ich_idx_t

ADC index channel in insert group.

Enumerator
ADC_ICH_IDX_1 | ADC insert channel index 1
ADC_ICH_IDX_2 | ADC insert channel index 2
ADC_ICH_IDX_3 | ADC insert channel index 3
ADC_ICH_IDX_4 | ADC insert channel index 4

Definition at line 140 of file ald_adc.h.

140 {
141 ADC_ICH_IDX_1 = 0x1U,
142 ADC_ICH_IDX_2 = 0x2U,
143 ADC_ICH_IDX_3 = 0x3U,
144 ADC_ICH_IDX_4 = 0x4U,
145 } adc_ich_idx_t;
ADC_ICH_IDX_1
Definition: ald_adc.h:141
adc_ich_idx_t
adc_ich_idx_t
ADC index channel in insert group.
Definition: ald_adc.h:140
ADC_ICH_IDX_3
Definition: ald_adc.h:143
ADC_ICH_IDX_4
Definition: ald_adc.h:144
ADC_ICH_IDX_2
Definition: ald_adc.h:142

◆ adc_ich_nr_t

enum adc_ich_nr_t

ADC numbers of insert conversion channals.

Enumerator
ADC_ICH_NR_1 | ADC number of insert conversion 1
ADC_ICH_NR_2 | ADC number of insert conversion 2
ADC_ICH_NR_3 | ADC number of insert conversion 3
ADC_ICH_NR_4 | ADC number of insert conversion 4

Definition at line 246 of file ald_adc.h.

246 {
247 ADC_ICH_NR_1 = 0x0U,
248 ADC_ICH_NR_2 = 0x1U,
249 ADC_ICH_NR_3 = 0x2U,
250 ADC_ICH_NR_4 = 0x3U,
251 } adc_ich_nr_t;
adc_ich_nr_t
adc_ich_nr_t
ADC numbers of insert conversion channals.
Definition: ald_adc.h:246
ADC_ICH_NR_2
Definition: ald_adc.h:248
ADC_ICH_NR_4
Definition: ald_adc.h:250
ADC_ICH_NR_3
Definition: ald_adc.h:249
ADC_ICH_NR_1
Definition: ald_adc.h:247

◆ adc_it_t

enum adc_it_t

ADC interrupts definition.

Enumerator
ADC_IT_NCH | ADC it normal
ADC_IT_AWD | ADC it awd
ADC_IT_ICH | ADC it insert
ADC_IT_OVR | ADC it overring

Definition at line 170 of file ald_adc.h.

170 {
171 ADC_IT_NCH = (1U << 5),
172 ADC_IT_AWD = (1U << 6),
173 ADC_IT_ICH = (1U << 7),
174 ADC_IT_OVR = (1U << 26),
175 } adc_it_t;
ADC_IT_AWD
Definition: ald_adc.h:172
ADC_IT_ICH
Definition: ald_adc.h:173
adc_it_t
adc_it_t
ADC interrupts definition.
Definition: ald_adc.h:170
ADC_IT_NCH
Definition: ald_adc.h:171
ADC_IT_OVR
Definition: ald_adc.h:174

◆ adc_nch_idx_t

enum adc_nch_idx_t

ADC index channel in normal group.

Enumerator
ADC_NCH_IDX_1 | ADC normal channel index 1
ADC_NCH_IDX_2 | ADC normal channel index 2
ADC_NCH_IDX_3 | ADC normal channel index 3
ADC_NCH_IDX_4 | ADC normal channel index 4
ADC_NCH_IDX_5 | ADC normal channel index 5
ADC_NCH_IDX_6 | ADC normal channel index 6
ADC_NCH_IDX_7 | ADC normal channel index 7
ADC_NCH_IDX_8 | ADC normal channel index 8
ADC_NCH_IDX_9 | ADC normal channel index 9
ADC_NCH_IDX_10 | ADC normal channel index 10
ADC_NCH_IDX_11 | ADC normal channel index 11
ADC_NCH_IDX_12 | ADC normal channel index 12
ADC_NCH_IDX_13 | ADC normal channel index 13
ADC_NCH_IDX_14 | ADC normal channel index 14
ADC_NCH_IDX_15 | ADC normal channel index 15
ADC_NCH_IDX_16 | ADC normal channel index 16

Definition at line 118 of file ald_adc.h.

118 {
119 ADC_NCH_IDX_1 = 0x1U,
120 ADC_NCH_IDX_2 = 0x2U,
121 ADC_NCH_IDX_3 = 0x3U,
122 ADC_NCH_IDX_4 = 0x4U,
123 ADC_NCH_IDX_5 = 0x5U,
124 ADC_NCH_IDX_6 = 0x6U,
125 ADC_NCH_IDX_7 = 0x7U,
126 ADC_NCH_IDX_8 = 0x8U,
127 ADC_NCH_IDX_9 = 0x9U,
128 ADC_NCH_IDX_10 = 0xAU,
129 ADC_NCH_IDX_11 = 0xBU,
130 ADC_NCH_IDX_12 = 0xCU,
131 ADC_NCH_IDX_13 = 0xDU,
132 ADC_NCH_IDX_14 = 0xEU,
133 ADC_NCH_IDX_15 = 0xFU,
134 ADC_NCH_IDX_16 = 0x10U,
135 } adc_nch_idx_t;
ADC_NCH_IDX_11
Definition: ald_adc.h:129
ADC_NCH_IDX_10
Definition: ald_adc.h:128
adc_nch_idx_t
adc_nch_idx_t
ADC index channel in normal group.
Definition: ald_adc.h:118
ADC_NCH_IDX_5
Definition: ald_adc.h:123
ADC_NCH_IDX_15
Definition: ald_adc.h:133
ADC_NCH_IDX_2
Definition: ald_adc.h:120
ADC_NCH_IDX_14
Definition: ald_adc.h:132
ADC_NCH_IDX_7
Definition: ald_adc.h:125
ADC_NCH_IDX_13
Definition: ald_adc.h:131
ADC_NCH_IDX_16
Definition: ald_adc.h:134
ADC_NCH_IDX_9
Definition: ald_adc.h:127
ADC_NCH_IDX_8
Definition: ald_adc.h:126
ADC_NCH_IDX_12
Definition: ald_adc.h:130
ADC_NCH_IDX_6
Definition: ald_adc.h:124
ADC_NCH_IDX_1
Definition: ald_adc.h:119
ADC_NCH_IDX_4
Definition: ald_adc.h:122
ADC_NCH_IDX_3
Definition: ald_adc.h:121

◆ adc_nch_nr_t

enum adc_nch_nr_t

ADC numbers of normal conversion channals.

Enumerator
ADC_NCH_NR_1 | ADC number of normal conversion 1
ADC_NCH_NR_2 | ADC number of normal conversion 2
ADC_NCH_NR_3 | ADC number of normal conversion 3
ADC_NCH_NR_4 | ADC number of normal conversion 4
ADC_NCH_NR_5 | ADC number of normal conversion 5
ADC_NCH_NR_6 | ADC number of normal conversion 6
ADC_NCH_NR_7 | ADC number of normal conversion 7
ADC_NCH_NR_8 | ADC number of normal conversion 8
ADC_NCH_NR_9 | ADC number of normal conversion 9
ADC_NCH_NR_10 | ADC number of normal conversion 10
ADC_NCH_NR_11 | ADC number of normal conversion 11
ADC_NCH_NR_12 | ADC number of normal conversion 12
ADC_NCH_NR_13 | ADC number of normal conversion 13
ADC_NCH_NR_14 | ADC number of normal conversion 14
ADC_NCH_NR_15 | ADC number of normal conversion 15
ADC_NCH_NR_16 | ADC number of normal conversion 16

Definition at line 224 of file ald_adc.h.

224 {
225 ADC_NCH_NR_1 = 0x0U,
226 ADC_NCH_NR_2 = 0x1U,
227 ADC_NCH_NR_3 = 0x2U,
228 ADC_NCH_NR_4 = 0x3U,
229 ADC_NCH_NR_5 = 0x4U,
230 ADC_NCH_NR_6 = 0x5U,
231 ADC_NCH_NR_7 = 0x6U,
232 ADC_NCH_NR_8 = 0x7U,
233 ADC_NCH_NR_9 = 0x8U,
234 ADC_NCH_NR_10 = 0x9U,
235 ADC_NCH_NR_11 = 0xAU,
236 ADC_NCH_NR_12 = 0xBU,
237 ADC_NCH_NR_13 = 0xCU,
238 ADC_NCH_NR_14 = 0xDU,
239 ADC_NCH_NR_15 = 0xEU,
240 ADC_NCH_NR_16 = 0xFU,
241 } adc_nch_nr_t;
ADC_NCH_NR_8
Definition: ald_adc.h:232
ADC_NCH_NR_4
Definition: ald_adc.h:228
ADC_NCH_NR_16
Definition: ald_adc.h:240
ADC_NCH_NR_5
Definition: ald_adc.h:229
ADC_NCH_NR_12
Definition: ald_adc.h:236
ADC_NCH_NR_11
Definition: ald_adc.h:235
ADC_NCH_NR_6
Definition: ald_adc.h:230
ADC_NCH_NR_2
Definition: ald_adc.h:226
ADC_NCH_NR_15
Definition: ald_adc.h:239
ADC_NCH_NR_9
Definition: ald_adc.h:233
ADC_NCH_NR_10
Definition: ald_adc.h:234
ADC_NCH_NR_14
Definition: ald_adc.h:238
adc_nch_nr_t
adc_nch_nr_t
ADC numbers of normal conversion channals.
Definition: ald_adc.h:224
ADC_NCH_NR_3
Definition: ald_adc.h:227
ADC_NCH_NR_13
Definition: ald_adc.h:237
ADC_NCH_NR_7
Definition: ald_adc.h:231
ADC_NCH_NR_1
Definition: ald_adc.h:225

◆ adc_nchesel_t

enum adc_nchesel_t

ADC config hannal trigger the EOC IT mode.

Enumerator
ADC_NCHESEL_MODE_ALL | ADC set RCHE after convert sequence finish
ADC_NCHESEL_MODE_ONE | ADC set RCHE after one convert finish

Definition at line 75 of file ald_adc.h.

75 {
76 ADC_NCHESEL_MODE_ALL = 0x0U,
77 ADC_NCHESEL_MODE_ONE = 0x1U,
78 } adc_nchesel_t;
ADC_NCHESEL_MODE_ONE
Definition: ald_adc.h:77
adc_nchesel_t
adc_nchesel_t
ADC config hannal trigger the EOC IT mode.
Definition: ald_adc.h:75
ADC_NCHESEL_MODE_ALL
Definition: ald_adc.h:76

◆ adc_neg_ref_t

enum adc_neg_ref_t

ADC negative reference voltage definition.

Enumerator
ADC_NEG_REF_VSS | ADC negative regerence voltage vss
ADC_NEG_REF_VREFN | ADC negative regerence voltage vrefn

Definition at line 206 of file ald_adc.h.

206 {
207 ADC_NEG_REF_VSS = 0x0U,
208 ADC_NEG_REF_VREFN = 0x1U,
209 } adc_neg_ref_t;
ADC_NEG_REF_VSS
Definition: ald_adc.h:207
ADC_NEG_REF_VREFN
Definition: ald_adc.h:208
adc_neg_ref_t
adc_neg_ref_t
ADC negative reference voltage definition.
Definition: ald_adc.h:206

◆ adc_pos_ref_t

enum adc_pos_ref_t

ADC positive reference voltage definition.

Enumerator
ADC_POS_REF_VDD | ADC positive reference is VDD
ADC_POS_REF_2V | ADC positive reference is 2V internal voltage
ADC_POS_REF_VREEFP | ADC positive reference is VREEFP
ADC_POS_REF_VREEFP_BUF | ADC positive reference is VREEFP BUFFER

Definition at line 214 of file ald_adc.h.

214 {
215 ADC_POS_REF_VDD = 0x0U,
216 ADC_POS_REF_2V = 0x1U,
217 ADC_POS_REF_VREEFP = 0x2U,
218 ADC_POS_REF_VREEFP_BUF = 0x3U,
219 } adc_pos_ref_t;
adc_pos_ref_t
adc_pos_ref_t
ADC positive reference voltage definition.
Definition: ald_adc.h:214
ADC_POS_REF_VREEFP_BUF
Definition: ald_adc.h:218
ADC_POS_REF_VDD
Definition: ald_adc.h:215
ADC_POS_REF_2V
Definition: ald_adc.h:216
ADC_POS_REF_VREEFP
Definition: ald_adc.h:217

◆ adc_samp_t

enum adc_samp_t

ADC sampling times.

Enumerator
ADC_SAMPLETIME_1 | ADC sampling times 1 clk
ADC_SAMPLETIME_2 | ADC sampling times 2 clk
ADC_SAMPLETIME_4 | ADC sampling times 4 clk
ADC_SAMPLETIME_15 | ADC sampling times 15 clk

Definition at line 108 of file ald_adc.h.

108 {
109 ADC_SAMPLETIME_1 = 0x0U,
110 ADC_SAMPLETIME_2 = 0x1U,
111 ADC_SAMPLETIME_4 = 0x2U,
112 ADC_SAMPLETIME_15 = 0x3U,
113 } adc_samp_t;
ADC_SAMPLETIME_15
Definition: ald_adc.h:112
adc_samp_t
adc_samp_t
ADC sampling times.
Definition: ald_adc.h:108
ADC_SAMPLETIME_1
Definition: ald_adc.h:109
ADC_SAMPLETIME_4
Definition: ald_adc.h:111
ADC_SAMPLETIME_2
Definition: ald_adc.h:110

◆ adc_state_t

enum adc_state_t

ADC State structures definition.

Enumerator
ADC_STATE_RESET | ADC not yet initialized or disabled
ADC_STATE_READY | ADC peripheral ready for use
ADC_STATE_BUSY | ADC is busy to internal process
ADC_STATE_TIMEOUT | TimeOut occurrence
ADC_STATE_ERROR | Internal error occurrence
ADC_STATE_BUSY_N | Normal channel busy
ADC_STATE_BUSY_I | Insert channel busy
ADC_STATE_BUSY_WDG | Insert channel busy

Definition at line 43 of file ald_adc.h.

43 {
44 ADC_STATE_RESET = 0x0U,
45 ADC_STATE_READY = 0x1U,
46 ADC_STATE_BUSY = 0x2U,
47 ADC_STATE_TIMEOUT = 0x4U,
48 ADC_STATE_ERROR = 0x8U,
49 ADC_STATE_BUSY_N = 0x10U,
50 ADC_STATE_BUSY_I = 0x20U,
51 ADC_STATE_BUSY_WDG = 0x40U,
52 } adc_state_t;
ADC_STATE_TIMEOUT
Definition: ald_adc.h:47
ADC_STATE_ERROR
Definition: ald_adc.h:48
ADC_STATE_BUSY_N
Definition: ald_adc.h:49
adc_state_t
adc_state_t
ADC State structures definition.
Definition: ald_adc.h:43
ADC_STATE_BUSY
Definition: ald_adc.h:46
ADC_STATE_READY
Definition: ald_adc.h:45
ADC_STATE_BUSY_I
Definition: ald_adc.h:50
ADC_STATE_RESET
Definition: ald_adc.h:44
ADC_STATE_BUSY_WDG
Definition: ald_adc.h:51


ALD User Manual: adc_init_t Struct Reference

Data Fields
adc_init_t Struct Reference
EASTSOFT ES32F3xx ALD » ADC » ADC Pubulic Types

ADC trigger conversion mode. More...

#include <ald_adc.h>

Data Fields

adc_align_t align
type_func_t scan
type_func_t cont
adc_nch_nr_t nch_nr
adc_disc_mode_t disc
adc_disc_nr_t disc_nr
adc_conv_bit_t data_bit
adc_clk_div_t div
adc_nchesel_t nche_sel
adc_neg_ref_t n_ref
adc_pos_ref_t p_ref

Detailed Description

ADC trigger conversion mode.

Structure definition of ADC and normal group initialization

Definition at line 304 of file ald_adc.h.

Field Documentation

◆ align

adc_align_t align

Specifies ADC data alignment

Definition at line 305 of file ald_adc.h.

◆ cont

type_func_t cont

Choose continuous mode enable or not

Definition at line 307 of file ald_adc.h.

◆ data_bit

adc_conv_bit_t data_bit

The precision of conversion

Definition at line 311 of file ald_adc.h.

◆ disc

adc_disc_mode_t disc

Discontinuous mode enable or not

Definition at line 309 of file ald_adc.h.

◆ disc_nr

adc_disc_nr_t disc_nr

Number of discontinuous conversions channel

Definition at line 310 of file ald_adc.h.

◆ div

adc_clk_div_t div

ADCCLK divider

Definition at line 312 of file ald_adc.h.

◆ n_ref

adc_neg_ref_t n_ref

The negative reference voltage

Definition at line 314 of file ald_adc.h.

◆ nch_nr

adc_nch_nr_t nch_nr

Length of normal ranks will be converted

Definition at line 308 of file ald_adc.h.

◆ nche_sel

adc_nchesel_t nche_sel

Trigger the NCHE FALG mode

Definition at line 313 of file ald_adc.h.

◆ p_ref

adc_pos_ref_t p_ref

The positive reference voltage

Definition at line 315 of file ald_adc.h.

◆ scan

type_func_t scan

Choose scan mode enable or not

Definition at line 306 of file ald_adc.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_adc.h


ALD User Manual: adc_nch_conf_t Struct Reference

Data Fields
adc_nch_conf_t Struct Reference
EASTSOFT ES32F3xx ALD » ADC » ADC Pubulic Types

Structure definition of ADC channel for normal group. More...

#include <ald_adc.h>

Data Fields

adc_channel_t ch
adc_nch_idx_t idx
adc_samp_t samp

Detailed Description

Structure definition of ADC channel for normal group.

Definition at line 321 of file ald_adc.h.

Field Documentation

◆ ch

adc_channel_t ch

The channel to configure into ADC normal group

Definition at line 322 of file ald_adc.h.

◆ idx

adc_nch_idx_t idx

The rank in the normal group sequencer

Definition at line 323 of file ald_adc.h.

◆ samp

adc_samp_t samp

Sampling time value to be set

Definition at line 324 of file ald_adc.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_adc.h


ALD User Manual: adc_analog_wdg_conf_t Struct Reference

Data Fields
adc_analog_wdg_conf_t Struct Reference
EASTSOFT ES32F3xx ALD » ADC » ADC Pubulic Types

ADC Configuration analog watchdog definition. More...

#include <ald_adc.h>

Data Fields

adc_ana_wdg_t mode
adc_channel_t ch
type_func_t interrupt
uint32_t | high_thrd
uint32_t | low_thrd

Detailed Description

ADC Configuration analog watchdog definition.

Definition at line 330 of file ald_adc.h.

Field Documentation

◆ ch

adc_channel_t ch

Selects which ADC channel to monitor by analog watchdog

Definition at line 332 of file ald_adc.h.

◆ high_thrd

uint32_t high_thrd

The ADC analog watchdog High threshold value.

Definition at line 334 of file ald_adc.h.

◆ interrupt

type_func_t interrupt

Whether the analog watchdog is configured in interrupt

Definition at line 333 of file ald_adc.h.

◆ low_thrd

uint32_t low_thrd

The ADC analog watchdog Low threshold value.

Definition at line 335 of file ald_adc.h.

◆ mode

adc_ana_wdg_t mode

Configures the ADC analog watchdog mode

Definition at line 331 of file ald_adc.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_adc.h


ALD User Manual: adc_ich_conf_t Struct Reference

Data Fields
adc_ich_conf_t Struct Reference
EASTSOFT ES32F3xx ALD » ADC » ADC Pubulic Types

ADC Configuration insert Channel structure definition. More...

#include <ald_adc.h>

Data Fields

adc_channel_t ch
adc_ich_idx_t idx
adc_samp_t samp
uint32_t offset
adc_ich_nr_t nr
type_func_t auto_m

Detailed Description

ADC Configuration insert Channel structure definition.

Definition at line 341 of file ald_adc.h.

Field Documentation

◆ auto_m

type_func_t auto_m

insert sequence's auto function

Definition at line 347 of file ald_adc.h.

◆ ch

adc_channel_t ch

Selection of ADC channel to configure

Definition at line 342 of file ald_adc.h.

◆ idx

adc_ich_idx_t idx

Rank in the insert group sequencer

Definition at line 343 of file ald_adc.h.

◆ nr

adc_ich_nr_t nr

The number of insert ranks

Definition at line 346 of file ald_adc.h.

◆ offset

uint32_t offset

The offset about converted data

Definition at line 345 of file ald_adc.h.

◆ samp

adc_samp_t samp

Sampling time value for selected channel

Definition at line 344 of file ald_adc.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_adc.h


ALD User Manual: adc_handle_s Struct Reference

Data Fields
adc_handle_s Struct Reference
EASTSOFT ES32F3xx ALD » ADC » ADC Pubulic Types

ADC handle Structure definition. More...

#include <ald_adc.h>

Collaboration diagram for adc_handle_s:
[legend]

Data Fields

ADC_TypeDef * | perh
adc_init_t init
dma_handle_t hdma
pis_handle_t hpis
lock_state_t lock
adc_state_t state
adc_error_t error_code
void(* | normal_cplt_cbk )(struct adc_handle_s *arg)
void(* | insert_cplt_cbk )(struct adc_handle_s *arg)
void(* | wdg_cbk )(struct adc_handle_s *arg)
void(* | error_cbk )(struct adc_handle_s *arg)
void(* | ovr_cbk )(struct adc_handle_s *arg)

Detailed Description

ADC handle Structure definition.

Definition at line 353 of file ald_adc.h.

Field Documentation

◆ error_cbk

void(* error_cbk) (struct adc_handle_s *arg)

adc error callback

Definition at line 367 of file ald_adc.h.

◆ error_code

adc_error_t error_code

ADC Error code

Definition at line 362 of file ald_adc.h.

◆ hdma

dma_handle_t hdma

Pointer DMA Handler

Definition at line 357 of file ald_adc.h.

◆ hpis

pis_handle_t hpis

Pointer PIS Handler for connect adc and dma

Definition at line 358 of file ald_adc.h.

◆ init

adc_init_t init

ADC required parameters

Definition at line 355 of file ald_adc.h.

◆ insert_cplt_cbk

void(* insert_cplt_cbk) (struct adc_handle_s *arg)

insert Conversion complete callback

Definition at line 365 of file ald_adc.h.

◆ lock

lock_state_t lock

ADC locking object

Definition at line 360 of file ald_adc.h.

◆ normal_cplt_cbk

void(* normal_cplt_cbk) (struct adc_handle_s *arg)

Regluar Conversion complete callback

Definition at line 364 of file ald_adc.h.

◆ ovr_cbk

void(* ovr_cbk) (struct adc_handle_s *arg)

adc ovr callback

Definition at line 368 of file ald_adc.h.

◆ perh

ADC_TypeDef* perh

Register base address

Definition at line 354 of file ald_adc.h.

◆ state

adc_state_t state

ADC communication state

Definition at line 361 of file ald_adc.h.

◆ wdg_cbk

void(* wdg_cbk) (struct adc_handle_s *arg)

Level out of window callback

Definition at line 366 of file ald_adc.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_adc.h


ALD User Manual: adc_timer_config_t Struct Reference

Data Fields
adc_timer_config_t Struct Reference
EASTSOFT ES32F3xx ALD » ADC » ADC Pubulic Types

Timer trigger adc config structure definition. More...

#include <ald_adc.h>

Collaboration diagram for adc_timer_config_t:
[legend]

Data Fields

uint32_t | time
uint16_t | size
uint16_t * | buf
adc_neg_ref_t n_ref
adc_pos_ref_t p_ref
adc_channel_t adc_ch
uint8_t | dma_ch
TIMER_TypeDef * | p_timer
ADC_TypeDef * | p_adc
void(* | cplt_cbk )(struct adc_handle_s *arg)
lock_state_t lock
pis_handle_t h_pis
dma_handle_t h_dma
timer_handle_t h_timer
adc_handle_t h_adc
adc_nch_conf_t config

Detailed Description

Timer trigger adc config structure definition.

Definition at line 374 of file ald_adc.h.

Field Documentation

◆ adc_ch

adc_channel_t adc_ch

Adc channel

Definition at line 380 of file ald_adc.h.

◆ buf

uint16_t* buf

Convert data buffer

Definition at line 377 of file ald_adc.h.

◆ config

adc_nch_conf_t config

Struct for chanel configure

Definition at line 392 of file ald_adc.h.

◆ cplt_cbk

void(* cplt_cbk) (struct adc_handle_s *arg)

Conversion complete callback

Definition at line 384 of file ald_adc.h.

◆ dma_ch

uint8_t dma_ch

Dma channel

Definition at line 381 of file ald_adc.h.

◆ h_adc

adc_handle_t h_adc

Handle of ADC module

Definition at line 391 of file ald_adc.h.

◆ h_dma

dma_handle_t h_dma

Handle of DMA module

Definition at line 389 of file ald_adc.h.

◆ h_pis

pis_handle_t h_pis

Handle of PIS module

Definition at line 388 of file ald_adc.h.

◆ h_timer

timer_handle_t h_timer

Handle of TIMER module

Definition at line 390 of file ald_adc.h.

◆ lock

lock_state_t lock

Locking object

Definition at line 387 of file ald_adc.h.

◆ n_ref

adc_neg_ref_t n_ref

The negative reference voltage for adc

Definition at line 378 of file ald_adc.h.

◆ p_adc

ADC_TypeDef* p_adc

Adc peripheral

Definition at line 383 of file ald_adc.h.

◆ p_ref

adc_pos_ref_t p_ref

The positive reference voltage for adc

Definition at line 379 of file ald_adc.h.

◆ p_timer

TIMER_TypeDef* p_timer

Timer peripheral

Definition at line 382 of file ald_adc.h.

◆ size

uint16_t size

Adc convert times

Definition at line 376 of file ald_adc.h.

◆ time

uint32_t time

Timer period time uint: us

Definition at line 375 of file ald_adc.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_adc.h


ALD User Manual: ADC Public Macros

Macros
ADC Public Macros
EASTSOFT ES32F3xx ALD » ADC
Collaboration diagram for ADC Public Macros:

Macros

#define | ADC_ENABLE(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK))
#define | ADC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK))
#define | ADC_NH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK))
#define | ADC_IH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK))
#define | ADC_RESET_HANDLE_STATE(handle) ((handle)->state = ADC_STATE_RESET)
#define | ADC_VREF_OUT_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK))
#define | ADC_VREF_OUT_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK))
#define | ADC_NETS_ENABLE(handle, mode) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, (mode) << ADC_CON1_NETS_POSS))
#define | ADC_IETS_ENABLE(handle, mode) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, (mode) << ADC_CON1_IETS_POSS))
#define | ADC_NETS_DISABLE(handle) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, 0 << ADC_CON1_NETS_POSS))
#define | ADC_IETS_DISABLE(handle) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, 0 << ADC_CON1_IETS_POSS))
#define | ADC_SPEED_HIGH_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK))
#define | ADC_SPEED_HIGH_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK))
#define | ADC_CALIBRATE_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK))
#define | ADC_CALIBRATE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK))

Detailed Description

Macro Definition Documentation

◆ ADC_CALIBRATE_DISABLE

#define ADC_CALIBRATE_DISABLE ( handle ) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK))

Definition at line 415 of file ald_adc.h.

◆ ADC_CALIBRATE_ENABLE

#define ADC_CALIBRATE_ENABLE ( handle ) (SET_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK))

Definition at line 414 of file ald_adc.h.

◆ ADC_DISABLE

#define ADC_DISABLE ( handle ) (CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK))

Definition at line 402 of file ald_adc.h.

◆ ADC_ENABLE

#define ADC_ENABLE ( handle ) (SET_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK))

Definition at line 401 of file ald_adc.h.

◆ ADC_IETS_DISABLE

#define ADC_IETS_DISABLE ( handle ) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, 0 << ADC_CON1_IETS_POSS))

Definition at line 411 of file ald_adc.h.

◆ ADC_IETS_ENABLE

#define ADC_IETS_ENABLE | ( | handle,
 |  | mode
 | ) | (MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, (mode) << ADC_CON1_IETS_POSS))

Definition at line 409 of file ald_adc.h.

◆ ADC_IH_TRIG_BY_SOFT

#define ADC_IH_TRIG_BY_SOFT ( handle ) (SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK))

Definition at line 404 of file ald_adc.h.

◆ ADC_NETS_DISABLE

#define ADC_NETS_DISABLE ( handle ) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, 0 << ADC_CON1_NETS_POSS))

Definition at line 410 of file ald_adc.h.

◆ ADC_NETS_ENABLE

#define ADC_NETS_ENABLE | ( | handle,
 |  | mode
 | ) | (MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, (mode) << ADC_CON1_NETS_POSS))

Definition at line 408 of file ald_adc.h.

◆ ADC_NH_TRIG_BY_SOFT

#define ADC_NH_TRIG_BY_SOFT ( handle ) (SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK))

Definition at line 403 of file ald_adc.h.

◆ ADC_RESET_HANDLE_STATE

#define ADC_RESET_HANDLE_STATE ( handle ) ((handle)->state = ADC_STATE_RESET)

Definition at line 405 of file ald_adc.h.

◆ ADC_SPEED_HIGH_DISABLE

#define ADC_SPEED_HIGH_DISABLE ( handle ) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK))

Definition at line 413 of file ald_adc.h.

◆ ADC_SPEED_HIGH_ENABLE

#define ADC_SPEED_HIGH_ENABLE ( handle ) (SET_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK))

Definition at line 412 of file ald_adc.h.

◆ ADC_VREF_OUT_DISABLE

#define ADC_VREF_OUT_DISABLE ( handle ) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK))

Definition at line 407 of file ald_adc.h.

◆ ADC_VREF_OUT_ENABLE

#define ADC_VREF_OUT_ENABLE ( handle ) (SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK))

Definition at line 406 of file ald_adc.h.


ALD User Manual: ADC Private Macros

Macros
ADC Private Macros
EASTSOFT ES32F3xx ALD » ADC
Collaboration diagram for ADC Private Macros:

Macros

#define | IS_ADC_ICH_IDX_TYPE(x) ((x) <= ADC_ICH_IDX_4)
#define | IS_ADC_NCH_IDX_TYPE(x) ((x) <= ADC_NCH_IDX_16)
#define | IS_ADC_SAMPLING_TIMES_TYPE(x)
#define | IS_ADC_CHANNELS_TYPE(x) ((x) <= ADC_CHANNEL_18)
#define | IS_ADC_DATA_ALIGN_TYPE(x)
#define | IS_ADC_ANALOG_WTD_MODE_TYPE(x)
#define | IS_ADC_IT_TYPE(x)
#define | IS_ADC_FLAGS_TYPE(x)
#define | IS_ADC_CLK_DIV_TYPE(x)
#define | IS_ADC_NEG_REF_VOLTAGE_TYPE(x)
#define | IS_POS_REF_VOLTAGE_TYPE(x)
#define | IS_ADC_NCH_NR_TYPE(x) ((x) <= ADC_NCH_NR_16)
#define | IS_ADC_ICH_NR_TYPE(x) ((x) <= ADC_ICH_NR_4)
#define | IS_ADC_DISC_NR_TYPE(x) ((x) <= ADC_DISC_NR_8)
#define | IS_ADC_CONV_BIT_TYPE(x)
#define | IS_ADC_TYPE(x)
#define | IS_ADC_NCHESEL_MODE_TYPE(x)
#define | IS_ADC_EVENT_TYPE(x) ((x) == ADC_AWD_EVENT)
#define | IS_ADC_IST_OFFSET_TYPE(x) ((x) <= 0xfff)
#define | IS_HTR_TYPE(x) ((x) <= 0xfff)
#define | IS_LTR_TYPE(x) ((x) <= 0xfff)

Detailed Description

Macro Definition Documentation

◆ IS_ADC_ANALOG_WTD_MODE_TYPE

#define IS_ADC_ANALOG_WTD_MODE_TYPE ( x )
Value:
(((x) == ADC_ANAWTD_NONE) || \
((x) == ADC_ANAWTD_SING_NM) || \
((x) == ADC_ANAWTD_SING_IST) || \
((x) == ADC_ANAWTD_SING_NMIST) || \
((x) == ADC_ANAWTD_ALL_NM) || \
((x) == ADC_ANAWTD_ALL_IST) || \
((x) == ADC_ANAWTD_ALL_NMIST))
ADC_ANAWTD_SING_IST
Definition: ald_adc.h:153
ADC_ANAWTD_SING_NM
Definition: ald_adc.h:152
ADC_ANAWTD_ALL_IST
Definition: ald_adc.h:156
ADC_ANAWTD_ALL_NM
Definition: ald_adc.h:155
ADC_ANAWTD_SING_NMIST
Definition: ald_adc.h:154
ADC_ANAWTD_ALL_NMIST
Definition: ald_adc.h:157
ADC_ANAWTD_NONE
Definition: ald_adc.h:151

Definition at line 432 of file ald_adc.h.

◆ IS_ADC_CHANNELS_TYPE

#define IS_ADC_CHANNELS_TYPE ( x ) ((x) <= ADC_CHANNEL_18)

Definition at line 429 of file ald_adc.h.

◆ IS_ADC_CLK_DIV_TYPE

#define IS_ADC_CLK_DIV_TYPE ( x )
Value:
(((x) == ADC_CKDIV_1) || \
((x) == ADC_CKDIV_2) || \
((x) == ADC_CKDIV_4) || \
((x) == ADC_CKDIV_8) || \
((x) == ADC_CKDIV_16) || \
((x) == ADC_CKDIV_32) || \
((x) == ADC_CKDIV_64) || \
((x) == ADC_CKDIV_128))
ADC_CKDIV_4
Definition: ald_adc.h:195
ADC_CKDIV_16
Definition: ald_adc.h:197
ADC_CKDIV_1
Definition: ald_adc.h:193
ADC_CKDIV_8
Definition: ald_adc.h:196
ADC_CKDIV_32
Definition: ald_adc.h:198
ADC_CKDIV_2
Definition: ald_adc.h:194
ADC_CKDIV_64
Definition: ald_adc.h:199
ADC_CKDIV_128
Definition: ald_adc.h:200

Definition at line 449 of file ald_adc.h.

◆ IS_ADC_CONV_BIT_TYPE

#define IS_ADC_CONV_BIT_TYPE ( x )
Value:
(((x) == ADC_CONV_BIT_12) || \
((x) == ADC_CONV_BIT_6) || \
((x) == ADC_CONV_BIT_8) || \
((x) == ADC_CONV_BIT_10))
ADC_CONV_BIT_12
Definition: ald_adc.h:283
ADC_CONV_BIT_6
Definition: ald_adc.h:280
ADC_CONV_BIT_8
Definition: ald_adc.h:281
ADC_CONV_BIT_10
Definition: ald_adc.h:282

Definition at line 466 of file ald_adc.h.

◆ IS_ADC_DATA_ALIGN_TYPE

#define IS_ADC_DATA_ALIGN_TYPE ( x )
Value:
(((x) == ADC_DATAALIGN_RIGHT) || \
((x) == ADC_DATAALIGN_LEFT))
ADC_DATAALIGN_LEFT
Definition: ald_adc.h:69
ADC_DATAALIGN_RIGHT
Definition: ald_adc.h:68

Definition at line 430 of file ald_adc.h.

◆ IS_ADC_DISC_NR_TYPE

#define IS_ADC_DISC_NR_TYPE ( x ) ((x) <= ADC_DISC_NR_8)

Definition at line 465 of file ald_adc.h.

◆ IS_ADC_EVENT_TYPE

#define IS_ADC_EVENT_TYPE ( x ) ((x) == ADC_AWD_EVENT)

Definition at line 474 of file ald_adc.h.

◆ IS_ADC_FLAGS_TYPE

#define IS_ADC_FLAGS_TYPE ( x )
Value:
(((x) == ADC_FLAG_AWD) || \
((x) == ADC_FLAG_NCH) || \
((x) == ADC_FLAG_ICH) || \
((x) == ADC_FLAG_OVR) || \
((x) == ADC_FLAG_NCHS) || \
((x) == ADC_FLAG_ICHS))
ADC_FLAG_ICH
Definition: ald_adc.h:183
ADC_FLAG_AWD
Definition: ald_adc.h:181
ADC_FLAG_ICHS
Definition: ald_adc.h:186
ADC_FLAG_OVR
Definition: ald_adc.h:184
ADC_FLAG_NCHS
Definition: ald_adc.h:185
ADC_FLAG_NCH
Definition: ald_adc.h:182

Definition at line 443 of file ald_adc.h.

◆ IS_ADC_ICH_IDX_TYPE

#define IS_ADC_ICH_IDX_TYPE ( x ) ((x) <= ADC_ICH_IDX_4)

Definition at line 423 of file ald_adc.h.

◆ IS_ADC_ICH_NR_TYPE

#define IS_ADC_ICH_NR_TYPE ( x ) ((x) <= ADC_ICH_NR_4)

Definition at line 464 of file ald_adc.h.

◆ IS_ADC_IST_OFFSET_TYPE

#define IS_ADC_IST_OFFSET_TYPE ( x ) ((x) <= 0xfff)

Definition at line 475 of file ald_adc.h.

◆ IS_ADC_IT_TYPE

#define IS_ADC_IT_TYPE ( x )
Value:
(((x) == ADC_IT_NCH) || \
((x) == ADC_IT_AWD) || \
((x) == ADC_IT_ICH) || \
((x) == ADC_IT_OVR ))
ADC_IT_AWD
Definition: ald_adc.h:172
ADC_IT_ICH
Definition: ald_adc.h:173
ADC_IT_NCH
Definition: ald_adc.h:171
ADC_IT_OVR
Definition: ald_adc.h:174

Definition at line 439 of file ald_adc.h.

◆ IS_ADC_NCH_IDX_TYPE

#define IS_ADC_NCH_IDX_TYPE ( x ) ((x) <= ADC_NCH_IDX_16)

Definition at line 424 of file ald_adc.h.

◆ IS_ADC_NCH_NR_TYPE

#define IS_ADC_NCH_NR_TYPE ( x ) ((x) <= ADC_NCH_NR_16)

Definition at line 463 of file ald_adc.h.

◆ IS_ADC_NCHESEL_MODE_TYPE

#define IS_ADC_NCHESEL_MODE_TYPE ( x )
Value:
(((x) == ADC_NCHESEL_MODE_ALL) || \
((x) == ADC_NCHESEL_MODE_ONE))
ADC_NCHESEL_MODE_ONE
Definition: ald_adc.h:77
ADC_NCHESEL_MODE_ALL
Definition: ald_adc.h:76

Definition at line 472 of file ald_adc.h.

◆ IS_ADC_NEG_REF_VOLTAGE_TYPE

#define IS_ADC_NEG_REF_VOLTAGE_TYPE ( x )
Value:
(((x) == ADC_NEG_REF_VSS ) || \
((x) == ADC_NEG_REF_VREFN ))
ADC_NEG_REF_VSS
Definition: ald_adc.h:207
ADC_NEG_REF_VREFN
Definition: ald_adc.h:208

Definition at line 457 of file ald_adc.h.

◆ IS_ADC_SAMPLING_TIMES_TYPE

#define IS_ADC_SAMPLING_TIMES_TYPE ( x )
Value:
(((x) == ADC_SAMPLETIME_1) || \
((x) == ADC_SAMPLETIME_2) || \
((x) == ADC_SAMPLETIME_4) || \
((x) == ADC_SAMPLETIME_15))
ADC_SAMPLETIME_15
Definition: ald_adc.h:112
ADC_SAMPLETIME_1
Definition: ald_adc.h:109
ADC_SAMPLETIME_4
Definition: ald_adc.h:111
ADC_SAMPLETIME_2
Definition: ald_adc.h:110

Definition at line 425 of file ald_adc.h.

◆ IS_ADC_TYPE

#define IS_ADC_TYPE ( x )
Value:
(((x) == ADC0) || \
((x) == ADC1))

Definition at line 470 of file ald_adc.h.

◆ IS_HTR_TYPE

#define IS_HTR_TYPE ( x ) ((x) <= 0xfff)

Definition at line 476 of file ald_adc.h.

◆ IS_LTR_TYPE

#define IS_LTR_TYPE ( x ) ((x) <= 0xfff)

Definition at line 477 of file ald_adc.h.

◆ IS_POS_REF_VOLTAGE_TYPE

#define IS_POS_REF_VOLTAGE_TYPE ( x )
Value:
(((x) == ADC_POS_REF_VDD) || \
((x) == ADC_POS_REF_2V) || \
((x) == ADC_POS_REF_VREEFP) || \
((x) == ADC_POS_REF_VREEFP_BUF))
ADC_POS_REF_VREEFP_BUF
Definition: ald_adc.h:218
ADC_POS_REF_VDD
Definition: ald_adc.h:215
ADC_POS_REF_2V
Definition: ald_adc.h:216
ADC_POS_REF_VREEFP
Definition: ald_adc.h:217

Definition at line 459 of file ald_adc.h.


ALD User Manual: BKPC

Modules
BKPC
EASTSOFT ES32F3xx ALD

BKPC module driver. More...

Collaboration diagram for BKPC:

Modules

BKPC Public Functions
BKPC Public Macros
BKPC Public Types
BKPC Private Macros

Detailed Description

BKPC module driver.


ALD User Manual: BKPC Public Functions

Modules
BKPC Public Functions
EASTSOFT ES32F3xx ALD » BKPC
Collaboration diagram for BKPC Public Functions:

Modules

Peripheral Control functions
Peripheral Control functions.
IO operation functions
IO operation functions.

Detailed Description


ALD User Manual: Peripheral Control functions

Functions
Peripheral Control functions
EASTSOFT ES32F3xx ALD » BKPC » BKPC Public Functions

Peripheral Control functions. More...

Collaboration diagram for Peripheral Control functions:

Functions

void | ald_bkpc_standby_wakeup_config (bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
Configure standby wakeup in backup field. More...
void | ald_bkpc_rtc_clock_config (bkpc_preh_clk_t clock)
Configure rtc clock in backup field. More...
void | ald_bkpc_tsense_clock_config (bkpc_preh_clk_t clock)
Configure tsense clock in backup field. More...

Detailed Description

Peripheral Control functions.

==============================================================================
            ##### Peripheral Control functions #####
==============================================================================
[..]  This section provides functions allowing to:
  (+) ald_bkpc_standby_wakeup_config() API can configure STANDBY wakeup.
  (+) ald_bkpc_rtc_clock_config() API can configure RTC clock.
  (+) ald_bkpc_tsense_clock_config() API can configure Tsense clock.

Function Documentation

◆ ald_bkpc_rtc_clock_config()

void ald_bkpc_rtc_clock_config ( bkpc_preh_clk_t clock )

Configure rtc clock in backup field.

Parameters
clock Clock
Return values
None

Definition at line 84 of file ald_bkpc.c.

85 {
86 assert_param(IS_BKPC_PREH_CLOCK(clock));
87
88 BKPC_UNLOCK();
89 MODIFY_REG(BKPC->PCCR, BKPC_PCCR_RTCCS_MSK, clock << BKPC_PCCR_RTCCS_POSS);
90 BKPC_LOCK();
91
92 return;
93 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_BKPC_PREH_CLOCK
#define IS_BKPC_PREH_CLOCK(x)
Definition: ald_bkpc.h:150
BKPC_LOCK
#define BKPC_LOCK()
Definition: ald_bkpc.h:38
BKPC_UNLOCK
#define BKPC_UNLOCK()
Definition: ald_bkpc.h:39
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74

◆ ald_bkpc_standby_wakeup_config()

void ald_bkpc_standby_wakeup_config | ( | bkpc_wakeup_port_t | port,
 |  | bkpc_wakeup_level_t | level
 | ) |  |

Configure standby wakeup in backup field.

Parameters
port | Wakeup port
level | HIGH/LOW.
Return values
None

Definition at line 57 of file ald_bkpc.c.

58 {
59 assert_param(IS_BKPC_WAKEUP_PORT(port));
60 assert_param(IS_BKPC_WAKEUP_LEVEL(level));
61
62 if (port == PMU_STANDBY_PORT_SEL_NONE) {
63 BKPC_UNLOCK();
64 CLEAR_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK);
65 SET_BIT(BKPC->CR, BKPC_CR_MRST_WKPEN_MSK);
66 BKPC_LOCK();
67 return;
68 }
69
70 BKPC_UNLOCK();
71 SET_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK | BKPC_CR_MRST_WKPEN_MSK);
72 MODIFY_REG(BKPC->CR, BKPC_CR_WKPS_MSK, port << BKPC_CR_WKPS_POSS);
73 MODIFY_REG(BKPC->CR, BKPC_CR_WKPOL_MSK, level << BKPC_CR_WKPOL_POS);
74 BKPC_LOCK();
75
76 return;
77 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_BKPC_WAKEUP_PORT
#define IS_BKPC_WAKEUP_PORT(x)
Definition: ald_bkpc.h:139
IS_BKPC_WAKEUP_LEVEL
#define IS_BKPC_WAKEUP_LEVEL(x)
Definition: ald_bkpc.h:148
BKPC_LOCK
#define BKPC_LOCK()
Definition: ald_bkpc.h:38
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
BKPC_UNLOCK
#define BKPC_UNLOCK()
Definition: ald_bkpc.h:39
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
PMU_STANDBY_PORT_SEL_NONE
Definition: ald_bkpc.h:120

◆ ald_bkpc_tsense_clock_config()

void ald_bkpc_tsense_clock_config ( bkpc_preh_clk_t clock )

Configure tsense clock in backup field.

Parameters
clock Clock
Return values
None

Definition at line 100 of file ald_bkpc.c.

101 {
102 assert_param(IS_BKPC_PREH_CLOCK(clock));
103
104 BKPC_UNLOCK();
105 MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TSENSECS_MSK, clock << BKPC_PCCR_TSENSECS_POSS);
106 BKPC_LOCK();
107
108 return;
109 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_BKPC_PREH_CLOCK
#define IS_BKPC_PREH_CLOCK(x)
Definition: ald_bkpc.h:150
BKPC_LOCK
#define BKPC_LOCK()
Definition: ald_bkpc.h:38
BKPC_UNLOCK
#define BKPC_UNLOCK()
Definition: ald_bkpc.h:39
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74


ALD User Manual: IO operation functions

Functions
IO operation functions
EASTSOFT ES32F3xx ALD » BKPC » BKPC Public Functions

IO operation functions. More...

Collaboration diagram for IO operation functions:

Functions

void | ald_bkpc_write_ram (uint8_t idx, uint32_t value)
Write data into backup ram. More...
uint32_t | ald_bkpc_read_ram (uint8_t idx)
Read data from backup ram. More...

Detailed Description

IO operation functions.

==============================================================================
            ##### IO operation functions #####
==============================================================================
[..]  This section provides functions allowing to:
  (+) ald_bkpc_write_ram() API can write data in backup ram.
  (+) ald_bkpc_read_ram() API can read data from backup ram.

Function Documentation

◆ ald_bkpc_read_ram()

uint32_t ald_bkpc_read_ram ( uint8_t idx )

Read data from backup ram.

Parameters
idx Index of backup word.
Return values
The data.

Definition at line 151 of file ald_bkpc.c.

152 {
153 assert_param(IS_BKPC_RAM_IDX(idx));
154
155 return READ_REG(RTC->BKPR[idx]);
156 }
assert_param
#define assert_param(x)
Definition: type.h:88
READ_REG
#define READ_REG(reg)
Definition: type.h:73
IS_BKPC_RAM_IDX
#define IS_BKPC_RAM_IDX(x)
Definition: ald_bkpc.h:154

◆ ald_bkpc_write_ram()

void ald_bkpc_write_ram | ( | uint8_t | idx,
 |  | uint32_t | value
 | ) |  |

Write data into backup ram.

Parameters
idx | Index of backup word.
value | Value which will be written to backup ram.
Return values
None

Definition at line 135 of file ald_bkpc.c.

136 {
137 assert_param(IS_BKPC_RAM_IDX(idx));
138
139 RTC_UNLOCK();
140 WRITE_REG(RTC->BKPR[idx], value);
141 RTC_LOCK();
142
143 return;
144 }
assert_param
#define assert_param(x)
Definition: type.h:88
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
IS_BKPC_RAM_IDX
#define IS_BKPC_RAM_IDX(x)
Definition: ald_bkpc.h:154


ALD User Manual: BKPC Public Macros

Macros
BKPC Public Macros
EASTSOFT ES32F3xx ALD » BKPC
Collaboration diagram for BKPC Public Macros:

Macros

#define | BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0U))
#define | BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55U))
#define | BKPC_LRC_ENABLE()
#define | BKPC_LRC_DISABLE()
#define | BKPC_LOSM_ENABLE()
#define | BKPC_LOSM_DISABLE()
#define | BKPC_LOSC_ENABLE()
#define | BKPC_LOSC_DISABLE()
#define | BKPC_MRST_WAKEUP_ENABLE()
#define | BKPC_MRST_WAKEUP_DISABLE()

Detailed Description

Macro Definition Documentation

◆ BKPC_LOCK

#define BKPC_LOCK ( ) (WRITE_REG(BKPC->PROT, 0U))

Definition at line 38 of file ald_bkpc.h.

◆ BKPC_LOSC_DISABLE

#define BKPC_LOSC_DISABLE ( )
Value:
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\
BKPC_LOCK(); \
} while (0)

Definition at line 70 of file ald_bkpc.h.

◆ BKPC_LOSC_ENABLE

#define BKPC_LOSC_ENABLE ( )
Value:
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \
BKPC_LOCK(); \
} while (0)

Definition at line 64 of file ald_bkpc.h.

◆ BKPC_LOSM_DISABLE

#define BKPC_LOSM_DISABLE ( )
Value:
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\
BKPC_LOCK(); \
} while (0)

Definition at line 58 of file ald_bkpc.h.

◆ BKPC_LOSM_ENABLE

#define BKPC_LOSM_ENABLE ( )
Value:
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \
BKPC_LOCK(); \
} while (0)

Definition at line 52 of file ald_bkpc.h.

◆ BKPC_LRC_DISABLE

#define BKPC_LRC_DISABLE ( )
Value:
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \
BKPC_LOCK(); \
} while (0)

Definition at line 46 of file ald_bkpc.h.

◆ BKPC_LRC_ENABLE

#define BKPC_LRC_ENABLE ( )
Value:
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \
BKPC_LOCK(); \
} while (0)

Definition at line 40 of file ald_bkpc.h.

◆ BKPC_MRST_WAKEUP_DISABLE

#define BKPC_MRST_WAKEUP_DISABLE ( )
Value:
do { \
BKPC_UNLOCK(); \
CLEAR_BIT(BKPC->CR, BKPC_CR_MRST_WKPEN_MSK); \
BKPC_LOCK(); \
} while (0)

Definition at line 84 of file ald_bkpc.h.

◆ BKPC_MRST_WAKEUP_ENABLE

#define BKPC_MRST_WAKEUP_ENABLE ( )
Value:
do { \
BKPC_UNLOCK(); \
SET_BIT(BKPC->CR, BKPC_CR_MRST_WKPEN_MSK); \
BKPC_LOCK(); \
} while (0)

Definition at line 78 of file ald_bkpc.h.

◆ BKPC_UNLOCK

#define BKPC_UNLOCK ( ) (WRITE_REG(BKPC->PROT, 0x9669AA55U))

Definition at line 39 of file ald_bkpc.h.


ALD User Manual: BKPC Public Types

Enumerations
BKPC Public Types
EASTSOFT ES32F3xx ALD » BKPC
Collaboration diagram for BKPC Public Types:

Enumerations

enum | bkpc_preh_clk_t { BKPC_PREH_CLK_LOSM = 0x0U, BKPC_PREH_CLK_LRC = 0x1U, BKPC_PREH_CLK_HRC_1M = 0x2U, BKPC_PREH_CLK_HOSC_1M = 0x3U }
BKPC preipheral clock select. More...
enum bkpc_wakeup_port_t {
PMU_STANDBY_PORT_SEL_PA0 = 0x0U, PMU_STANDBY_PORT_SEL_PA1 = 0x1U, PMU_STANDBY_PORT_SEL_PA2 = 0x2U, PMU_STANDBY_PORT_SEL_PA3 = 0x3U,
PMU_STANDBY_PORT_SEL_PA4 = 0x4U, PMU_STANDBY_PORT_SEL_PA5 = 0x5U, PMU_STANDBY_PORT_SEL_PA6 = 0x6U, PMU_STANDBY_PORT_SEL_PA7 = 0x7U,
PMU_STANDBY_PORT_SEL_NONE = 0xFU
}
Standby wakeup port select. More...
enum | bkpc_wakeup_level_t { PMU_STANDBY_LEVEL_HIGH = 0x0U, PMU_STANDBY_LEVEL_LOW = 0x1U }
Standby wakeup level. More...

Detailed Description

Enumeration Type Documentation

◆ bkpc_preh_clk_t

enum bkpc_preh_clk_t

BKPC preipheral clock select.

Enumerator
BKPC_PREH_CLK_LOSM | LOSM
BKPC_PREH_CLK_LRC | LRC
BKPC_PREH_CLK_HRC_1M | HRC down to 1MHz
BKPC_PREH_CLK_HOSC_1M | HOSC down to 1MHz

Definition at line 101 of file ald_bkpc.h.

101 {
102 BKPC_PREH_CLK_LOSM = 0x0U,
103 BKPC_PREH_CLK_LRC = 0x1U,
104 BKPC_PREH_CLK_HRC_1M = 0x2U,
105 BKPC_PREH_CLK_HOSC_1M = 0x3U,
106 } bkpc_preh_clk_t;
BKPC_PREH_CLK_LRC
Definition: ald_bkpc.h:103
BKPC_PREH_CLK_HOSC_1M
Definition: ald_bkpc.h:105
BKPC_PREH_CLK_HRC_1M
Definition: ald_bkpc.h:104
BKPC_PREH_CLK_LOSM
Definition: ald_bkpc.h:102
bkpc_preh_clk_t
bkpc_preh_clk_t
BKPC preipheral clock select.
Definition: ald_bkpc.h:101

◆ bkpc_wakeup_level_t

enum bkpc_wakeup_level_t

Standby wakeup level.

Enumerator
PMU_STANDBY_LEVEL_HIGH | High level
PMU_STANDBY_LEVEL_LOW | Low level

Definition at line 126 of file ald_bkpc.h.

126 {
127 PMU_STANDBY_LEVEL_HIGH = 0x0U,
128 PMU_STANDBY_LEVEL_LOW = 0x1U,
129 } bkpc_wakeup_level_t;
PMU_STANDBY_LEVEL_LOW
Definition: ald_bkpc.h:128
PMU_STANDBY_LEVEL_HIGH
Definition: ald_bkpc.h:127
bkpc_wakeup_level_t
bkpc_wakeup_level_t
Standby wakeup level.
Definition: ald_bkpc.h:126

◆ bkpc_wakeup_port_t

enum bkpc_wakeup_port_t

Standby wakeup port select.

Enumerator
PMU_STANDBY_PORT_SEL_PA0 | Wakeup by PA0
PMU_STANDBY_PORT_SEL_PA1 | Wakeup by PA1
PMU_STANDBY_PORT_SEL_PA2 | Wakeup by PA2
PMU_STANDBY_PORT_SEL_PA3 | Wakeup by PA3
PMU_STANDBY_PORT_SEL_PA4 | Wakeup by PA4
PMU_STANDBY_PORT_SEL_PA5 | Wakeup by PA5
PMU_STANDBY_PORT_SEL_PA6 | Wakeup by PA6
PMU_STANDBY_PORT_SEL_PA7 | Wakeup by PA7
PMU_STANDBY_PORT_SEL_NONE | Wakeup by other source

Definition at line 111 of file ald_bkpc.h.

111 {
112 PMU_STANDBY_PORT_SEL_PA0 = 0x0U,
113 PMU_STANDBY_PORT_SEL_PA1 = 0x1U,
114 PMU_STANDBY_PORT_SEL_PA2 = 0x2U,
115 PMU_STANDBY_PORT_SEL_PA3 = 0x3U,
116 PMU_STANDBY_PORT_SEL_PA4 = 0x4U,
117 PMU_STANDBY_PORT_SEL_PA5 = 0x5U,
118 PMU_STANDBY_PORT_SEL_PA6 = 0x6U,
119 PMU_STANDBY_PORT_SEL_PA7 = 0x7U,
120 PMU_STANDBY_PORT_SEL_NONE = 0xFU,
121 } bkpc_wakeup_port_t;
bkpc_wakeup_port_t
bkpc_wakeup_port_t
Standby wakeup port select.
Definition: ald_bkpc.h:111
PMU_STANDBY_PORT_SEL_PA0
Definition: ald_bkpc.h:112
PMU_STANDBY_PORT_SEL_PA5
Definition: ald_bkpc.h:117
PMU_STANDBY_PORT_SEL_PA3
Definition: ald_bkpc.h:115
PMU_STANDBY_PORT_SEL_PA6
Definition: ald_bkpc.h:118
PMU_STANDBY_PORT_SEL_PA7
Definition: ald_bkpc.h:119
PMU_STANDBY_PORT_SEL_PA4
Definition: ald_bkpc.h:116
PMU_STANDBY_PORT_SEL_PA2
Definition: ald_bkpc.h:114
PMU_STANDBY_PORT_SEL_PA1
Definition: ald_bkpc.h:113
PMU_STANDBY_PORT_SEL_NONE
Definition: ald_bkpc.h:120


ALD User Manual: BKPC Private Macros

Macros
BKPC Private Macros
EASTSOFT ES32F3xx ALD » BKPC
Collaboration diagram for BKPC Private Macros:

Macros

#define | IS_BKPC_WAKEUP_PORT(x)
#define | IS_BKPC_WAKEUP_LEVEL(x)
#define | IS_BKPC_PREH_CLOCK(x)
#define | IS_BKPC_RAM_IDX(x) ((x) < 32)

Detailed Description

Macro Definition Documentation

◆ IS_BKPC_PREH_CLOCK

#define IS_BKPC_PREH_CLOCK ( x )
Value:
(((x) == BKPC_PREH_CLK_LOSM) || \
((x) == BKPC_PREH_CLK_LRC) || \
((x) == BKPC_PREH_CLK_HRC_1M) || \
((x) == BKPC_PREH_CLK_HOSC_1M))
BKPC_PREH_CLK_LRC
Definition: ald_bkpc.h:103
BKPC_PREH_CLK_HOSC_1M
Definition: ald_bkpc.h:105
BKPC_PREH_CLK_HRC_1M
Definition: ald_bkpc.h:104
BKPC_PREH_CLK_LOSM
Definition: ald_bkpc.h:102

Definition at line 150 of file ald_bkpc.h.

◆ IS_BKPC_RAM_IDX

#define IS_BKPC_RAM_IDX ( x ) ((x) < 32)

Definition at line 154 of file ald_bkpc.h.

◆ IS_BKPC_WAKEUP_LEVEL

#define IS_BKPC_WAKEUP_LEVEL ( x )
Value:
(((x) == PMU_STANDBY_LEVEL_HIGH) || \
((x) == PMU_STANDBY_LEVEL_LOW))
PMU_STANDBY_LEVEL_LOW
Definition: ald_bkpc.h:128
PMU_STANDBY_LEVEL_HIGH
Definition: ald_bkpc.h:127

Definition at line 148 of file ald_bkpc.h.

◆ IS_BKPC_WAKEUP_PORT

#define IS_BKPC_WAKEUP_PORT ( x )
Value:
(((x) == PMU_STANDBY_PORT_SEL_PA0) || \
((x) == PMU_STANDBY_PORT_SEL_PA1) || \
((x) == PMU_STANDBY_PORT_SEL_PA2) || \
((x) == PMU_STANDBY_PORT_SEL_PA3) || \
((x) == PMU_STANDBY_PORT_SEL_PA4) || \
((x) == PMU_STANDBY_PORT_SEL_PA5) || \
((x) == PMU_STANDBY_PORT_SEL_PA6) || \
((x) == PMU_STANDBY_PORT_SEL_PA7) || \
((x) == PMU_STANDBY_PORT_SEL_NONE))
PMU_STANDBY_PORT_SEL_PA0
Definition: ald_bkpc.h:112
PMU_STANDBY_PORT_SEL_PA5
Definition: ald_bkpc.h:117
PMU_STANDBY_PORT_SEL_PA3
Definition: ald_bkpc.h:115
PMU_STANDBY_PORT_SEL_PA6
Definition: ald_bkpc.h:118
PMU_STANDBY_PORT_SEL_PA7
Definition: ald_bkpc.h:119
PMU_STANDBY_PORT_SEL_PA4
Definition: ald_bkpc.h:116
PMU_STANDBY_PORT_SEL_PA2
Definition: ald_bkpc.h:114
PMU_STANDBY_PORT_SEL_PA1
Definition: ald_bkpc.h:113
PMU_STANDBY_PORT_SEL_NONE
Definition: ald_bkpc.h:120

Definition at line 139 of file ald_bkpc.h.


ALD User Manual: CALC

Modules
CALC
EASTSOFT ES32F3xx ALD

CALC module driver. More...

Collaboration diagram for CALC:

Modules

CALC Public Functions
Accelerating calculate functions.

Detailed Description

CALC module driver.


ALD User Manual: CALC Public Functions

Functions
CALC Public Functions
EASTSOFT ES32F3xx ALD » CALC

Accelerating calculate functions. More...

Collaboration diagram for CALC Public Functions:

Functions

uint32_t | ald_calc_sqrt (uint32_t data)
Square root operation. More...
uint32_t | ald_calc_div (uint32_t dividend, uint32_t divisor, uint32_t *remainder)
Calculating division. More...
int32_t | ald_calc_div_sign (int32_t dividend, int32_t divisor, int32_t *remainder)
Calculating division. More...
flag_status_t | ald_calc_get_dz_status (void)
Get the flag of divisor is zero. More...

Detailed Description

Accelerating calculate functions.

==============================================================================
            ##### Accelerating calculate functions #####
==============================================================================
  [..]  This section provides functions allowing to:
    (+) Square root operation.
    (+) Division.
    (+) Get DZ flag.

Function Documentation

◆ ald_calc_div()

uint32_t ald_calc_div | ( | uint32_t | dividend,
 |  | uint32_t | divisor,
 |  | uint32_t * | remainder
 | ) |  |

Calculating division.

Parameters
dividend | The value of the dividend.
divisor | The value of the divisor.
remainder | The value of the remainder.
Return values
The result of division.

Definition at line 66 of file ald_calc.c.

67 {
68 CLEAR_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK);
69 SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK);
70 WRITE_REG(CALC->DIVDR, dividend);
71 WRITE_REG(CALC->DIVSR, divisor);
72
73 while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK));
74
75 *remainder = READ_REG(CALC->DIVRR);
76 return READ_REG(CALC->DIVQR);
77 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
READ_REG
#define READ_REG(reg)
Definition: type.h:73
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72

◆ ald_calc_div_sign()

int32_t ald_calc_div_sign | ( | int32_t | dividend,
 |  | int32_t | divisor,
 |  | int32_t * | remainder
 | ) |  |

Calculating division.

Parameters
dividend | The value of the dividend.
divisor | The value of the divisor.
remainder | The value of the remainder.
Return values
The result of division.

Definition at line 86 of file ald_calc.c.

87 {
88 SET_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK);
89 SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK);
90 WRITE_REG(CALC->DIVDR, dividend);
91 WRITE_REG(CALC->DIVSR, divisor);
92
93 while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK));
94
95 *remainder = READ_REG(CALC->DIVRR);
96 return READ_REG(CALC->DIVQR);
97 }
READ_REG
#define READ_REG(reg)
Definition: type.h:73
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72

◆ ald_calc_get_dz_status()

flag_status_t ald_calc_get_dz_status ( void )

Get the flag of divisor is zero.

Return values
The status, SET/RESET.

Definition at line 103 of file ald_calc.c.

104 {
105 if (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_DZ_MSK))
106 return SET;
107
108 return RESET;
109 }
SET
Definition: type.h:39
RESET
Definition: type.h:38
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69

◆ ald_calc_sqrt()

uint32_t ald_calc_sqrt ( uint32_t data )

Square root operation.

Parameters
data The radicand.
Return values
The value of square root.

Definition at line 51 of file ald_calc.c.

52 {
53 WRITE_REG(CALC->RDCND, data);
54 while (READ_BIT(CALC->SQRTSR, CALC_SQRTSR_BUSY_MSK));
55
56 return READ_REG(CALC->SQRTRES);
57 }
READ_REG
#define READ_REG(reg)
Definition: type.h:73
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72


ALD User Manual: CAN

Modules
CAN
EASTSOFT ES32F3xx ALD

CAN module driver. More...

Collaboration diagram for CAN:

Modules

CAN Public Functions
CAN Private Functions
CAN Public Types
CAN Public Macros
CAN Private Macros

Detailed Description

CAN module driver.


ALD User Manual: CAN Public Functions

Modules
CAN Public Functions
EASTSOFT ES32F3xx ALD » CAN
Collaboration diagram for CAN Public Functions:

Modules

Initialization functions
Initialization and Configuration functions.
IO operation functions
I/O operation functions.
Peripheral Control functions
Peripheral Control functions.
Peripheral State and Error functions
CAN Peripheral State functions.

Detailed Description


ALD User Manual: Initialization functions

Functions
Initialization functions
EASTSOFT ES32F3xx ALD » CAN » CAN Public Functions

Initialization and Configuration functions. More...

Collaboration diagram for Initialization functions:

Functions

ald_status_t | ald_can_init (can_handle_t *hperh)
Initializes the CAN peripheral according to the specified parameters in the CAN_init_t. More...
ald_status_t | ald_can_filter_config (can_handle_t *hperh, can_filter_t *config)
Configures the CAN reception filter according to the specified parameters in the can_filter_t. More...
void | ald_can_reset (can_handle_t *hperh)
Reset the CAN peripheral. More...

Detailed Description

Initialization and Configuration functions.

==============================================================================
            ##### Initialization and Configuration functions #####
==============================================================================
  [..]  This section provides functions allowing to:
    (+) Initialize and configure the CAN.
    (+) Configures the CAN reception filter.
    (+) Reset the CAN.

Function Documentation

◆ ald_can_filter_config()

ald_status_t ald_can_filter_config | ( | can_handle_t * | hperh,
 |  | can_filter_t * | config
 | ) |  |

Configures the CAN reception filter according to the specified parameters in the can_filter_t.

Parameters
hperh | pointer to a can_handle_t structure.
config | pointer to a can_filter_t structure that contains the filter configuration information.
Return values
Status,see ald_status_t.

Definition at line 193 of file ald_can.c.

194 {
195 uint32_t pos;
196
197 assert_param(IS_CAN_ALL(hperh->perh));
198 assert_param(IS_CAN_FILTER_NUMBER(config->number));
199 assert_param(IS_CAN_FILTER_MODE(config->mode));
200 assert_param(IS_CAN_FILTER_SCALE(config->scale));
201 assert_param(IS_CAN_FILTER_FIFO(config->fifo));
202 assert_param(IS_FUNC_STATE(config->active));
203
204 pos = 1 << config->number;
205 SET_BIT(hperh->perh->FLTCON, CAN_FLTCON_FLTINI_MSK);
206 CLEAR_BIT(hperh->perh->FLTGO, pos);
207
208 if (config->scale == CAN_FILTER_SCALE_16) {
209 CLEAR_BIT(hperh->perh->FLTWS, pos);
210 hperh->perh->Filter[config->number].FLT1 =
211 ((0xFFFF & config->mask_id_low) << 16) |
212 (0xFFFF & config->id_low);
213
214 hperh->perh->Filter[config->number].FLT2 =
215 ((0xFFFF & config->mask_id_high) << 16) |
216 (0xFFFF & config->id_high);
217 }
218
219 if (config->scale == CAN_FILTER_SCALE_32) {
220 SET_BIT(hperh->perh->FLTWS, pos);
221 hperh->perh->Filter[config->number].FLT1 =
222 ((0xFFFF & config->id_high) << 16) |
223 (0xFFFF & config->id_low);
224 hperh->perh->Filter[config->number].FLT2 =
225 ((0xFFFF & config->mask_id_high) << 16) |
226 (0xFFFF & config->mask_id_low);
227 }
228
229 MODIFY_REG(hperh->perh->FLTM, pos, config->mode << config->number);
230 MODIFY_REG(hperh->perh->FLTAS, pos, config->fifo << config->number);
231 MODIFY_REG(hperh->perh->FLTGO, pos, config->active << config->number);
232 CLEAR_BIT(hperh->perh->FLTCON, CAN_FLTCON_FLTINI_MSK);
233
234 return OK;
235 }
IS_CAN_FILTER_MODE
#define IS_CAN_FILTER_MODE(x)
Definition: ald_can.h:338
OK
Definition: utils.h:55
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
CAN_FILTER_SCALE_16
Definition: ald_can.h:139
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
can_filter_t::fifo
can_filter_fifo_t fifo
Definition: ald_can.h:239
can_filter_t::mask_id_high
uint32_t mask_id_high
Definition: ald_can.h:237
IS_CAN_FILTER_NUMBER
#define IS_CAN_FILTER_NUMBER(x)
Definition: ald_can.h:327
can_filter_t::mode
can_filter_mode_t mode
Definition: ald_can.h:241
can_filter_t::id_low
uint32_t id_low
Definition: ald_can.h:236
IS_CAN_FILTER_FIFO
#define IS_CAN_FILTER_FIFO(x)
Definition: ald_can.h:342
can_filter_t::mask_id_low
uint32_t mask_id_low
Definition: ald_can.h:238
IS_CAN_FILTER_SCALE
#define IS_CAN_FILTER_SCALE(x)
Definition: ald_can.h:340
can_filter_t::scale
can_filter_scale_t scale
Definition: ald_can.h:242
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
can_filter_t::active
type_func_t active
Definition: ald_can.h:243
CAN_FILTER_SCALE_32
Definition: ald_can.h:140
IS_CAN_ALL
#define IS_CAN_ALL(x)
Definition: ald_can.h:326
can_filter_t::id_high
uint32_t id_high
Definition: ald_can.h:235
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
can_filter_t::number
uint32_t number
Definition: ald_can.h:240

◆ ald_can_init()

ald_status_t ald_can_init ( can_handle_t * hperh )

Initializes the CAN peripheral according to the specified parameters in the CAN_init_t.

Parameters
hperh pointer to a can_handle_t structure that contains the configuration information for the specified CAN.
Return values
Status,see ald_status_t.

Definition at line 119 of file ald_can.c.

120 {
121 uint32_t tickstart = 0;
122
123 assert_param(IS_CAN_ALL(hperh->perh));
124 assert_param(IS_FUNC_STATE(hperh->init.ttcm));
125 assert_param(IS_FUNC_STATE(hperh->init.abom));
126 assert_param(IS_FUNC_STATE(hperh->init.awk));
127 assert_param(IS_FUNC_STATE(hperh->init.abom));
128 assert_param(IS_FUNC_STATE(hperh->init.rfom));
129 assert_param(IS_FUNC_STATE(hperh->init.txmp));
130 assert_param(IS_CAN_MODE(hperh->init.mode));
131 assert_param(IS_CAN_SJW(hperh->init.sjw));
132 assert_param(IS_CAN_BS1(hperh->init.seg1));
133 assert_param(IS_CAN_BS2(hperh->init.seg2));
134 assert_param(IS_CAN_PRESCALER(hperh->init.psc));
135
136 if (hperh->state == CAN_STATE_RESET)
137 hperh->lock = UNLOCK;
138
139 hperh->state = CAN_STATE_BUSY;
140 tickstart = ald_get_tick();
141
142 CLEAR_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK);
143 SET_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK);
144
145 while (!READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) {
146 if ((ald_get_tick() - tickstart) > CAN_TIMEOUT_VALUE) {
147 hperh->state = CAN_STATE_TIMEOUT;
148 __UNLOCK(hperh);
149
150 return TIMEOUT;
151 }
152 }
153
154 MODIFY_REG(hperh->perh->CON, CAN_CON_TTCEN_MSK, hperh->init.ttcm << CAN_CON_TTCEN_POS);
155 MODIFY_REG(hperh->perh->CON, CAN_CON_ABOFFEN_MSK, hperh->init.abom << CAN_CON_ABOFFEN_POS);
156 MODIFY_REG(hperh->perh->CON, CAN_CON_AWKEN_MSK, hperh->init.awk << CAN_CON_AWKEN_POS);
157 MODIFY_REG(hperh->perh->CON, CAN_CON_ARTXDIS_MSK, hperh->init.artx << CAN_CON_ARTXDIS_POS);
158 MODIFY_REG(hperh->perh->CON, CAN_CON_RXFOPM_MSK, hperh->init.rfom << CAN_CON_RXFOPM_POS);
159 MODIFY_REG(hperh->perh->CON, CAN_CON_TXMP_MSK, hperh->init.txmp << CAN_CON_TXMP_POS);
160 MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_LOOP_MSK, (hperh->init.mode & 0x1) << CAN_BTIME_LOOP_POS);
161 MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_SILENT_MSK, ((hperh->init.mode >> 1) & 0x1) << CAN_BTIME_SILENT_POS);
162 MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_RESJW_MSK, hperh->init.sjw << CAN_BTIME_RESJW_POSS);
163 MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_SEG1_MSK, hperh->init.seg1 << CAN_BTIME_SEG1_POSS);
164 MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_SEG2_MSK, hperh->init.seg2 << CAN_BTIME_SEG2_POSS);
165 MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_BPSC_MSK, (hperh->init.psc - 1) << CAN_BTIME_BPSC_POSS);
166
167 CLEAR_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK);
168 tickstart = ald_get_tick();
169
170 while (READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) {
171 if ((ald_get_tick() - tickstart) > CAN_TIMEOUT_VALUE) {
172 hperh->state = CAN_STATE_TIMEOUT;
173 __UNLOCK(hperh);
174
175 return TIMEOUT;
176 }
177 }
178
179 hperh->err = CAN_ERROR_NONE;
180 hperh->state = CAN_STATE_READY;
181
182 return OK;
183 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
can_init_t::artx
type_func_t artx
Definition: ald_can.h:259
can_init_t::psc
uint32_t psc
Definition: ald_can.h:250
can_init_t::seg2
can_seg2_t seg2
Definition: ald_can.h:255
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
can_init_t::seg1
can_seg1_t seg1
Definition: ald_can.h:254
can_init_t::ttcm
type_func_t ttcm
Definition: ald_can.h:256
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
IS_CAN_BS2
#define IS_CAN_BS2(x)
Definition: ald_can.h:337
can_init_t::txmp
type_func_t txmp
Definition: ald_can.h:261
can_handle_s::lock
lock_state_t lock
Definition: ald_can.h:298
CAN_ERROR_NONE
Definition: ald_can.h:58
UNLOCK
Definition: type.h:59
can_handle_s::init
can_init_t init
Definition: ald_can.h:295
can_init_t::mode
can_operate_mode_t mode
Definition: ald_can.h:251
can_init_t::awk
type_func_t awk
Definition: ald_can.h:258
IS_CAN_SJW
#define IS_CAN_SJW(x)
Definition: ald_can.h:332
can_init_t::abom
type_func_t abom
Definition: ald_can.h:257
can_init_t::sjw
can_sjw_t sjw
Definition: ald_can.h:252
CAN_STATE_READY
Definition: ald_can.h:41
can_init_t::rfom
type_func_t rfom
Definition: ald_can.h:260
CAN_STATE_TIMEOUT
Definition: ald_can.h:50
IS_CAN_PRESCALER
#define IS_CAN_PRESCALER(x)
Definition: ald_can.h:352
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
can_handle_s::err
can_error_t err
Definition: ald_can.h:300
CAN_TIMEOUT_VALUE
#define CAN_TIMEOUT_VALUE
Definition: ald_can.h:397
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
can_handle_s::state
can_state_t state
Definition: ald_can.h:299
CAN_STATE_BUSY
Definition: ald_can.h:42
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_CAN_BS1
#define IS_CAN_BS1(x)
Definition: ald_can.h:336
IS_CAN_ALL
#define IS_CAN_ALL(x)
Definition: ald_can.h:326
CAN_STATE_RESET
Definition: ald_can.h:40
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
IS_CAN_MODE
#define IS_CAN_MODE(x)
Definition: ald_can.h:328

◆ ald_can_reset()

void ald_can_reset ( can_handle_t * hperh )

Reset the CAN peripheral.

Parameters
hperh pointer to a can_handle_t structure.
Return values
None

Definition at line 242 of file ald_can.c.

243 {
244 assert_param(IS_CAN_ALL(hperh->perh));
245
246 hperh->state = CAN_STATE_RESET;
247 __UNLOCK(hperh);
248
249 return;
250 }
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
can_handle_s::state
can_state_t state
Definition: ald_can.h:299
IS_CAN_ALL
#define IS_CAN_ALL(x)
Definition: ald_can.h:326
CAN_STATE_RESET
Definition: ald_can.h:40


ALD User Manual: IO operation functions

Functions
IO operation functions
EASTSOFT ES32F3xx ALD » CAN » CAN Public Functions

I/O operation functions. More...

Collaboration diagram for IO operation functions:

Functions

ald_status_t | ald_can_send (can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout)
Send a CAN frame message. More...
ald_status_t | ald_can_send_by_it (can_handle_t *hperh, can_tx_msg_t *msg)
Send a CAN frame message using interrupt. More...
ald_status_t | ald_can_recv (can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout)
Receives a correct CAN frame. More...
ald_status_t | ald_can_recv_by_it (can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg)
Receives a correct CAN frame using interrupt. More...

Detailed Description

I/O operation functions.

==============================================================================
                    ##### IO operation functions #####
==============================================================================
  [..]  This section provides functions allowing to:
    (+) Send a CAN frame message.
    (+) Send a CAN frame message using interrupt.
    (+) Receive a CAN frame message.
    (+) Receive a CAN frame message using interrupt.

*

Function Documentation

◆ ald_can_recv()

ald_status_t ald_can_recv | ( | can_handle_t * | hperh,
 |  | can_rx_fifo_t | num,
 |  | can_rx_msg_t * | msg,
 |  | uint32_t | timeout
 | ) |  |

Receives a correct CAN frame.

Parameters
hperh | pointer to a can_handle_t structure.
num | Receive fifo number, CAN_RX_FIFO0 or CAN_RX_FIFO1
msg | Storing message.
timeout | Specify timeout value
Return values
Status,see ald_status_t.

Definition at line 411 of file ald_can.c.

412 {
413 uint32_t tick, stid, exid;
414
415 assert_param(IS_CAN_ALL(hperh->perh));
416 assert_param(IS_CAN_FIFO(num));
417 assert_param(msg != NULL);
418
419 __LOCK(hperh);
420 SET_BIT(hperh->state, num == CAN_RX_FIFO0 ? CAN_STATE_RX0_MASK : CAN_STATE_RX1_MASK);
421 tick = ald_get_tick();
422
423 while (CAN_RX_MSG_PENDING(hperh, num) == 0) {
424 if ((timeout == 0) || ((ald_get_tick() - tick) > timeout)) {
425 hperh->state = CAN_STATE_TIMEOUT;
426 __UNLOCK(hperh);
427 return TIMEOUT;
428 }
429 }
430
431 stid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_STDID_MSK, CAN_RXF0ID_STDID_POSS);
432 exid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_EXID_MSK, CAN_RXF0ID_EXID_POSS);
433 msg->type = (can_id_type_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_IDE_MSK, CAN_RXF0ID_IDE_POS);
434
435 if (msg->type == CAN_ID_STD)
436 msg->std = stid;
437 else
438 msg->ext = (stid << 18) | exid;
439
440 msg->rtr = (can_remote_req_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_RTR_MSK, CAN_RXF0ID_RTR_POS);
441 msg->len = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_DLEN_MSK, CAN_RXF0INF_DLEN_POSS);
442 msg->fmi = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_FLTIDX_MSK, CAN_RXF0INF_FLTIDX_POSS);
443 msg->data[0] = hperh->perh->RxFIFO[num].RXFDL & 0xFF;
444 msg->data[1] = (hperh->perh->RxFIFO[num].RXFDL >> 8) & 0xFF;
445 msg->data[2] = (hperh->perh->RxFIFO[num].RXFDL >> 16) & 0xFF;
446 msg->data[3] = (hperh->perh->RxFIFO[num].RXFDL >> 24) & 0xFF;
447 msg->data[4] = hperh->perh->RxFIFO[num].RXFDH & 0xFF;
448 msg->data[5] = (hperh->perh->RxFIFO[num].RXFDH >> 8) & 0xFF;
449 msg->data[6] = (hperh->perh->RxFIFO[num].RXFDH >> 16) & 0xFF;
450 msg->data[7] = (hperh->perh->RxFIFO[num].RXFDH >> 24) & 0xFF;
451
452 can_rx_fifo_release(hperh, num);
453 CLEAR_BIT(hperh->state, num == CAN_RX_FIFO0 ? CAN_STATE_RX0_MASK : CAN_STATE_RX1_MASK);
454 __UNLOCK(hperh);
455
456 return OK;
457 }
can_rx_msg_t::ext
uint32_t ext
Definition: ald_can.h:281
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CAN_RX_MSG_PENDING
#define CAN_RX_MSG_PENDING(x, y)
Definition: ald_can.h:314
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
can_rx_msg_t::fmi
uint32_t fmi
Definition: ald_can.h:286
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
CAN_STATE_RX0_MASK
#define CAN_STATE_RX0_MASK
Definition: ald_can.h:399
CAN_STATE_TIMEOUT
Definition: ald_can.h:50
can_rx_msg_t::std
uint32_t std
Definition: ald_can.h:280
CAN_STATE_RX1_MASK
#define CAN_STATE_RX1_MASK
Definition: ald_can.h:400
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
can_rx_msg_t::len
uint32_t len
Definition: ald_can.h:284
IS_CAN_FIFO
#define IS_CAN_FIFO(x)
Definition: ald_can.h:347
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
can_handle_s::state
can_state_t state
Definition: ald_can.h:299
can_rx_fifo_release
static void can_rx_fifo_release(can_handle_t *hperh, can_rx_fifo_t num)
Release rx FIFO.
Definition: ald_can.c:950
can_rx_msg_t::data
uint8_t data[8]
Definition: ald_can.h:285
can_remote_req_t
can_remote_req_t
CAN Remote Transmission Request.
Definition: ald_can.h:162
can_rx_msg_t::rtr
can_remote_req_t rtr
Definition: ald_can.h:283
IS_CAN_ALL
#define IS_CAN_ALL(x)
Definition: ald_can.h:326
CAN_ID_STD
Definition: ald_can.h:155
__LOCK
#define __LOCK(x)
Definition: utils.h:92
CAN_RX_FIFO0
Definition: ald_can.h:181
can_rx_msg_t::type
can_id_type_t type
Definition: ald_can.h:282
can_id_type_t
can_id_type_t
CAN Identifier Type.
Definition: ald_can.h:154

◆ ald_can_recv_by_it()

ald_status_t ald_can_recv_by_it | ( | can_handle_t * | hperh,
 |  | can_rx_fifo_t | num,
 |  | can_rx_msg_t * | msg
 | ) |  |

Receives a correct CAN frame using interrupt.

Parameters
hperh | pointer to a can_handle_t structure.
num | Specify the FIFO number
msg | Storing message.
Return values
Status,see ald_status_t.

Definition at line 466 of file ald_can.c.

467 {
468 assert_param(IS_CAN_ALL(hperh->perh));
469 assert_param(IS_CAN_FIFO(num));
470 assert_param(msg != NULL);
471
472 if (num == CAN_RX_FIFO0) {
473 if ((hperh->state & CAN_STATE_RX0_MASK) || ((hperh->state & 0xF) != CAN_STATE_READY))
474 return BUSY;
475
476 SET_BIT(hperh->state, CAN_STATE_RX0_MASK);
477 hperh->rx0_msg = msg;
478 }
479 else {
480 if ((hperh->state & CAN_STATE_RX1_MASK) || ((hperh->state & 0xF) != CAN_STATE_READY))
481 return BUSY;
482
483 SET_BIT(hperh->state, CAN_STATE_RX1_MASK);
484 hperh->rx1_msg = msg;
485 }
486
487 ald_can_interrupt_config(hperh, CAN_IT_WARN, ENABLE);
488 ald_can_interrupt_config(hperh, CAN_IT_PERR, ENABLE);
489 ald_can_interrupt_config(hperh, CAN_IT_BOF, ENABLE);
490 ald_can_interrupt_config(hperh, CAN_IT_PRERR, ENABLE);
491 ald_can_interrupt_config(hperh, CAN_IT_ERR, ENABLE);
492
493 if (num == CAN_RX_FIFO0)
494 ald_can_interrupt_config(hperh, CAN_IT_FP0, ENABLE);
495 else
496 ald_can_interrupt_config(hperh, CAN_IT_FP1, ENABLE);
497
498 return OK;
499 }
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
CAN_IT_FP1
Definition: ald_can.h:219
can_handle_s::rx1_msg
can_rx_msg_t * rx1_msg
Definition: ald_can.h:297
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
can_handle_s::rx0_msg
can_rx_msg_t * rx0_msg
Definition: ald_can.h:296
CAN_IT_ERR
Definition: ald_can.h:226
CAN_STATE_READY
Definition: ald_can.h:41
CAN_STATE_RX0_MASK
#define CAN_STATE_RX0_MASK
Definition: ald_can.h:399
CAN_IT_WARN
Definition: ald_can.h:222
CAN_STATE_RX1_MASK
#define CAN_STATE_RX1_MASK
Definition: ald_can.h:400
CAN_IT_PRERR
Definition: ald_can.h:225
IS_CAN_FIFO
#define IS_CAN_FIFO(x)
Definition: ald_can.h:347
CAN_IT_PERR
Definition: ald_can.h:223
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
can_handle_s::state
can_state_t state
Definition: ald_can.h:299
IS_CAN_ALL
#define IS_CAN_ALL(x)
Definition: ald_can.h:326
ald_can_interrupt_config
void ald_can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state)
Enable/disable the specified CAN interrupts.
Definition: ald_can.c:779
CAN_RX_FIFO0
Definition: ald_can.h:181
CAN_IT_BOF
Definition: ald_can.h:224
CAN_IT_FP0
Definition: ald_can.h:216

◆ ald_can_send()

ald_status_t ald_can_send | ( | can_handle_t * | hperh,
 |  | can_tx_msg_t * | msg,
 |  | uint32_t | timeout
 | ) |  |

Send a CAN frame message.

Parameters
hperh | pointer to a can_handle_t structure.
msg | message which will be sent.
timeout | specify Timeout value
Return values
Status,see ald_status_t.

Definition at line 280 of file ald_can.c.

281 {
282 uint32_t tick;
283 can_tx_mailbox_t idx;
284
285 assert_param(IS_CAN_ALL(hperh->perh));
286 assert_param(IS_CAN_IDTYPE(msg->type));
287 assert_param(IS_CAN_RTR(msg->rtr));
288 assert_param(IS_CAN_DATA_LEN(msg->len));
289
290 __LOCK(hperh);
291 SET_BIT(hperh->state, CAN_STATE_TX_MASK);
292
293 if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK))
294 idx = CAN_TX_MAILBOX_0;
295 else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK))
296 idx = CAN_TX_MAILBOX_1;
297 else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK))
298 idx = CAN_TX_MAILBOX_2;
299 else
300 idx = CAN_TX_MAILBOX_NONE;
301
302 if (idx == CAN_TX_MAILBOX_NONE) {
303 hperh->state = CAN_STATE_ERROR;
304 __UNLOCK(hperh);
305 return ERROR;
306 }
307
308 CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK);
309 MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_IDE_MSK, msg->type << CAN_TXID0_IDE_POS);
310 MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_RTR_MSK, msg->rtr << CAN_TXID0_RTR_POS);
311
312 if (msg->type == CAN_ID_STD) {
313 assert_param(IS_CAN_STDID(msg->std));
314 MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, msg->std << CAN_TXID0_STDID_POSS);
315 CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK);
316 }
317 else {
318 assert_param(IS_CAN_EXTID(msg->ext));
319 MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, ((msg->ext >> 18) & 0x7FF) << CAN_TXID0_STDID_POSS);
320 MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK, (msg->ext & 0x3FFFF) << CAN_TXID0_EXID_POSS);
321 }
322 MODIFY_REG(hperh->perh->TxMailBox[idx].TXFCON, CAN_TXFCON0_DLEN_MSK, (msg->len & 0xF) << CAN_TXFCON0_DLEN_POSS);
323 WRITE_REG(hperh->perh->TxMailBox[idx].TXDL, msg->data[0] | (msg->data[1] << 8) | (msg->data[2] << 16) | (msg->data[3] << 24));
324 WRITE_REG(hperh->perh->TxMailBox[idx].TXDH, msg->data[4] | (msg->data[5] << 8) | (msg->data[6] << 16) | (msg->data[7] << 24));
325 SET_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK);
326 tick = ald_get_tick();
327
328 while (!(ald_can_get_tx_status(hperh, idx))) {
329 if ((timeout == 0) || ((ald_get_tick() - tick) > timeout)) {
330 hperh->state = CAN_STATE_TIMEOUT;
331 __UNLOCK(hperh);
332 return TIMEOUT;
333 }
334 }
335
336 CLEAR_BIT(hperh->state, CAN_STATE_TX_MASK);
337 __UNLOCK(hperh);
338 return OK;
339 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
can_tx_mailbox_t
can_tx_mailbox_t
CAN Transmit Constants.
Definition: ald_can.h:170
can_tx_msg_t::type
can_id_type_t type
Definition: ald_can.h:270
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_CAN_STDID
#define IS_CAN_STDID(x)
Definition: ald_can.h:349
can_tx_msg_t::ext
uint32_t ext
Definition: ald_can.h:269
CAN_TX_MAILBOX_NONE
Definition: ald_can.h:174
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
CAN_STATE_ERROR
Definition: ald_can.h:51
CAN_STATE_TIMEOUT
Definition: ald_can.h:50
CAN_TX_MAILBOX_2
Definition: ald_can.h:173
IS_CAN_EXTID
#define IS_CAN_EXTID(x)
Definition: ald_can.h:350
IS_CAN_RTR
#define IS_CAN_RTR(x)
Definition: ald_can.h:346
ald_can_get_tx_status
type_bool_t ald_can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box)
Check the transmission status of a CAN Frame.
Definition: ald_can.c:697
CAN_TX_MAILBOX_1
Definition: ald_can.h:172
can_tx_msg_t::std
uint32_t std
Definition: ald_can.h:268
can_tx_msg_t::rtr
can_remote_req_t rtr
Definition: ald_can.h:271
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
IS_CAN_DATA_LEN
#define IS_CAN_DATA_LEN(x)
Definition: ald_can.h:351
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
CAN_TX_MAILBOX_0
Definition: ald_can.h:171
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
can_handle_s::state
can_state_t state
Definition: ald_can.h:299
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
can_tx_msg_t::len
uint32_t len
Definition: ald_can.h:272
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
can_tx_msg_t::data
uint8_t data[8]
Definition: ald_can.h:273
IS_CAN_ALL
#define IS_CAN_ALL(x)
Definition: ald_can.h:326
CAN_ID_STD
Definition: ald_can.h:155
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
IS_CAN_IDTYPE
#define IS_CAN_IDTYPE(x)
Definition: ald_can.h:344
CAN_STATE_TX_MASK
#define CAN_STATE_TX_MASK
Definition: ald_can.h:398

◆ ald_can_send_by_it()

ald_status_t ald_can_send_by_it | ( | can_handle_t * | hperh,
 |  | can_tx_msg_t * | msg
 | ) |  |

Send a CAN frame message using interrupt.

Parameters
hperh | pointer to a can_handle_t structure.
msg | message which will be sent.
Return values
Status,see ald_status_t.

Definition at line 347 of file ald_can.c.

348 {
349 uint8_t idx = CAN_TX_MAILBOX_NONE;
350
351 assert_param(IS_CAN_ALL(hperh->perh));
352 assert_param(IS_CAN_IDTYPE(msg->type));
353 assert_param(IS_CAN_RTR(msg->rtr));
354 assert_param(IS_CAN_DATA_LEN(msg->len));
355
356 if ((hperh->state & CAN_STATE_TX_MASK) || ((hperh->state & 0xF) != CAN_STATE_READY))
357 return BUSY;
358
359 if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK))
360 idx = CAN_TX_MAILBOX_0;
361 else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK))
362 idx = CAN_TX_MAILBOX_1;
363 else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK))
364 idx = CAN_TX_MAILBOX_2;
365 else
366 idx = CAN_TX_MAILBOX_NONE;
367
368 if (idx == CAN_TX_MAILBOX_NONE)
369 return BUSY;
370
371 CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK);
372 MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_IDE_MSK, msg->type << CAN_TXID0_IDE_POS);
373 MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_RTR_MSK, msg->rtr << CAN_TXID0_RTR_POS);
374
375 if (msg->type == CAN_ID_STD) {
376 assert_param(IS_CAN_STDID(msg->std));
377 MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, msg->std << CAN_TXID0_STDID_POSS);
378 CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK);
379 }
380 else {
381 assert_param(IS_CAN_EXTID(msg->ext));
382 MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, ((msg->ext >> 18) & 0x7FF) << CAN_TXID0_STDID_POSS);
383 MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK, (msg->ext & 0x3FFFF) << CAN_TXID0_EXID_POSS);
384 }
385
386 MODIFY_REG(hperh->perh->TxMailBox[idx].TXFCON, CAN_TXFCON0_DLEN_MSK, (msg->len & 0xF) << CAN_TXFCON0_DLEN_POSS);
387 WRITE_REG(hperh->perh->TxMailBox[idx].TXDL, msg->data[0] | (msg->data[1] << 8) | (msg->data[2] << 16) | (msg->data[3] << 24));
388 WRITE_REG(hperh->perh->TxMailBox[idx].TXDH, msg->data[4] | (msg->data[5] << 8) | (msg->data[6] << 16) | (msg->data[7] << 24));
389
390 SET_BIT(hperh->state, CAN_STATE_TX_MASK);
391
392 ald_can_interrupt_config(hperh, CAN_IT_WARN, ENABLE);
393 ald_can_interrupt_config(hperh, CAN_IT_PERR, ENABLE);
394 ald_can_interrupt_config(hperh, CAN_IT_BOF, ENABLE);
395 ald_can_interrupt_config(hperh, CAN_IT_PRERR, ENABLE);
396 ald_can_interrupt_config(hperh, CAN_IT_ERR, ENABLE);
397 ald_can_interrupt_config(hperh, CAN_IT_TXM, ENABLE);
398
399 SET_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK);
400 return OK;
401 }
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
can_tx_msg_t::type
can_id_type_t type
Definition: ald_can.h:270
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_CAN_STDID
#define IS_CAN_STDID(x)
Definition: ald_can.h:349
BUSY
Definition: utils.h:57
can_tx_msg_t::ext
uint32_t ext
Definition: ald_can.h:269
CAN_TX_MAILBOX_NONE
Definition: ald_can.h:174
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
CAN_IT_ERR
Definition: ald_can.h:226
CAN_STATE_READY
Definition: ald_can.h:41
CAN_TX_MAILBOX_2
Definition: ald_can.h:173
IS_CAN_EXTID
#define IS_CAN_EXTID(x)
Definition: ald_can.h:350
CAN_IT_WARN
Definition: ald_can.h:222
IS_CAN_RTR
#define IS_CAN_RTR(x)
Definition: ald_can.h:346
CAN_TX_MAILBOX_1
Definition: ald_can.h:172
CAN_IT_TXM
Definition: ald_can.h:215
can_tx_msg_t::std
uint32_t std
Definition: ald_can.h:268
can_tx_msg_t::rtr
can_remote_req_t rtr
Definition: ald_can.h:271
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
IS_CAN_DATA_LEN
#define IS_CAN_DATA_LEN(x)
Definition: ald_can.h:351
CAN_IT_PRERR
Definition: ald_can.h:225
CAN_TX_MAILBOX_0
Definition: ald_can.h:171
CAN_IT_PERR
Definition: ald_can.h:223
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
can_handle_s::state
can_state_t state
Definition: ald_can.h:299
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
can_tx_msg_t::len
uint32_t len
Definition: ald_can.h:272
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
can_tx_msg_t::data
uint8_t data[8]
Definition: ald_can.h:273
IS_CAN_ALL
#define IS_CAN_ALL(x)
Definition: ald_can.h:326
ald_can_interrupt_config
void ald_can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state)
Enable/disable the specified CAN interrupts.
Definition: ald_can.c:779
CAN_ID_STD
Definition: ald_can.h:155
CAN_IT_BOF
Definition: ald_can.h:224
IS_CAN_IDTYPE
#define IS_CAN_IDTYPE(x)
Definition: ald_can.h:344
CAN_STATE_TX_MASK
#define CAN_STATE_TX_MASK
Definition: ald_can.h:398


ALD User Manual: Peripheral Control functions

Functions
Peripheral Control functions
EASTSOFT ES32F3xx ALD » CAN » CAN Public Functions

Peripheral Control functions. More...

Collaboration diagram for Peripheral Control functions:

Functions

ald_status_t | ald_can_sleep (can_handle_t *hperh)
Enters the Sleep(low power) mode. More...
ald_status_t | ald_can_wake_up (can_handle_t *hperh)
Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral is in the normal mode. More...
void | ald_can_irq_handler (can_handle_t *hperh)
Handles CAN interrupt request. More...
type_bool_t | ald_can_get_tx_status (can_handle_t *hperh, can_tx_mailbox_t box)
Check the transmission status of a CAN Frame. More...
void | ald_can_cancel_send (can_handle_t *hperh, can_tx_mailbox_t box)
Cancel transmission. More...
void | ald_can_interrupt_config (can_handle_t *hperh, can_it_t it, type_func_t state)
Enable/disable the specified CAN interrupts. More...
it_status_t | ald_can_get_it_status (can_handle_t *hperh, can_it_t it)
Get the status of CAN interrupt source. More...
flag_status_t | ald_can_get_flag_status (can_handle_t *hperh, can_flag_t flag)
Get the status of CAN interrupt flag. More...
void | can_clear_flag (can_handle_t *hperh, can_flag_t flag)
Clear the specified CAN pending flag. More...
void | ald_can_clear_flag_status (can_handle_t *hperh, can_flag_t flag)

Detailed Description

Peripheral Control functions.

==============================================================================
          ##### Peripheral Control functions #####
==============================================================================
  [..]
  This section provides functions allowing to:
    (+) Configure CAN sleep.
    (+) Configure CAN wakeup.
    (+) CAN cancel send message.
    (+) Handle CAN interrupt.
    (+) Get CAN transmit status.
    (+) Configure CAN interrupt ENABLE/DISABLE.
    (+) Get CAN interrupt source status.
    (+) Get CAN interrupt flag status.
    (+) Clear CAN interrupt flag.

*

Function Documentation

◆ ald_can_cancel_send()

void ald_can_cancel_send | ( | can_handle_t * | hperh,
 |  | can_tx_mailbox_t | box
 | ) |  |

Cancel transmission.

Parameters
hperh | pointer to a can_handle_t structure.
box | the index of the mailbox that is used for transmission.
Return values
None

Definition at line 746 of file ald_can.c.

747 {
748 assert_param(IS_CAN_ALL(hperh->perh));
749 assert_param(IS_CAN_TX_MAILBOX(box));
750
751 switch (box) {
752 case CAN_TX_MAILBOX_0:
753 SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0STPREQ_MSK);
754 break;
755 case CAN_TX_MAILBOX_1:
756 SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1STPREQ_MSK);
757 break;
758 case CAN_TX_MAILBOX_2:
759 SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2STPREQ_MSK);
760 break;
761 default:
762 break;
763 }
764
765 return;
766 }
assert_param
#define assert_param(x)
Definition: type.h:88
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
CAN_TX_MAILBOX_2
Definition: ald_can.h:173
CAN_TX_MAILBOX_1
Definition: ald_can.h:172
CAN_TX_MAILBOX_0
Definition: ald_can.h:171
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_CAN_ALL
#define IS_CAN_ALL(x)
Definition: ald_can.h:326
IS_CAN_TX_MAILBOX
#define IS_CAN_TX_MAILBOX(x)
Definition: ald_can.h:348

◆ ald_can_clear_flag_status()

void ald_can_clear_flag_status | ( | can_handle_t * | hperh,
 |  | can_flag_t | flag
 | ) |  |

◆ ald_can_get_flag_status()

flag_status_t ald_can_get_flag_status | ( | can_handle_t * | hperh,
 |  | can_flag_t | flag
 | ) |  |

Get the status of CAN interrupt flag.

Parameters
hperh | Pointer to a can_handle_t structure.
flag | Specifies the CAN interrupt flag. This parameter can be one of the can_flag_t.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 822 of file ald_can.c.

823 {
824 uint32_t idx = (flag >> 20) & 0x7;
825 uint32_t _flag = flag & 0xFF8FFFFF;
826
827 assert_param(IS_CAN_GET_FLAG(flag));
828
829 switch (idx) {
830 case 0:
831 if (READ_BIT(hperh->perh->STAT, _flag))
832 return SET;
833
834 break;
835 case 1:
836 if (READ_BIT(hperh->perh->TXSTAT, _flag))
837 return SET;
838
839 break;
840 case 2:
841 if (READ_BIT(hperh->perh->RXF0, _flag))
842 return SET;
843
844 break;
845 case 3:
846 if (READ_BIT(hperh->perh->RXF1, _flag))
847 return SET;
848
849 break;
850 case 4:
851 if (READ_BIT(hperh->perh->ERRSTAT, _flag))
852 return SET;
853
854 break;
855 default:
856 break;
857 }
858
859 return RESET;
860 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
RESET
Definition: type.h:38
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
IS_CAN_GET_FLAG
#define IS_CAN_GET_FLAG(x)
Definition: ald_can.h:353

◆ ald_can_get_it_status()

it_status_t ald_can_get_it_status | ( | can_handle_t * | hperh,
 |  | can_it_t | it
 | ) |  |

Get the status of CAN interrupt source.

Parameters
hperh | Pointer to a can_handle_t structure.
it | Specifies the CAN interrupt source. This parameter can be one of the can_it_t.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 802 of file ald_can.c.

803 {
804 assert_param(IS_CAN_ALL(hperh->perh));
805 assert_param(IS_CAN_IT(it));
806
807 if (READ_BIT(hperh->perh->IE, it))
808 return SET;
809
810 return RESET;
811 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
RESET
Definition: type.h:38
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
IS_CAN_IT
#define IS_CAN_IT(x)
Definition: ald_can.h:383
IS_CAN_ALL
#define IS_CAN_ALL(x)
Definition: ald_can.h:326

◆ ald_can_get_tx_status()

type_bool_t ald_can_get_tx_status | ( | can_handle_t * | hperh,
 |  | can_tx_mailbox_t | box
 | ) |  |

Check the transmission status of a CAN Frame.

Parameters
hperh | pointer to a can_handle_t structure.
box | the index of the mailbox that is used for transmission.
Return values
The new status of transmission(TRUE or FALSE).

Definition at line 697 of file ald_can.c.

698 {
699 assert_param(IS_CAN_ALL(hperh->perh));
700 assert_param(IS_CAN_TX_MAILBOX(box));
701
702 switch (box) {
703 case CAN_TX_MAILBOX_0:
704 if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0REQC_MSK))
705 return FALSE;
706 if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0TXC_MSK))
707 return FALSE;
708 if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK))
709 return FALSE;
710
711 return TRUE;
712
713 case CAN_TX_MAILBOX_1:
714 if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1REQC_MSK))
715 return FALSE;
716 if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1TXC_MSK))
717 return FALSE;
718 if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK))
719 return FALSE;
720
721 return TRUE;
722
723 case CAN_TX_MAILBOX_2:
724 if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2REQC_MSK))
725 return FALSE;
726 if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2TXC_MSK))
727 return FALSE;
728 if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK))
729 return FALSE;
730
731 return TRUE;
732
733 default:
734 break;
735 }
736
737 return FALSE;
738 }
assert_param
#define assert_param(x)
Definition: type.h:88
FALSE
Definition: type.h:54
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
TRUE
Definition: type.h:55
CAN_TX_MAILBOX_2
Definition: ald_can.h:173
CAN_TX_MAILBOX_1
Definition: ald_can.h:172
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
CAN_TX_MAILBOX_0
Definition: ald_can.h:171
IS_CAN_ALL
#define IS_CAN_ALL(x)
Definition: ald_can.h:326
IS_CAN_TX_MAILBOX
#define IS_CAN_TX_MAILBOX(x)
Definition: ald_can.h:348

◆ ald_can_interrupt_config()

void ald_can_interrupt_config | ( | can_handle_t * | hperh,
 |  | can_it_t | it,
 |  | type_func_t | state
 | ) |  |

Enable/disable the specified CAN interrupts.

Parameters
hperh | Pointer to a can_handle_t structure.
it | Specifies the CAN interrupt sources to be enabled or disabled. This parameter can be one of the can_it_t.
state New state of the specified CAN interrupts. This parameter can be:
  • ENABLE
  • DISABLE
Return values
None

Definition at line 779 of file ald_can.c.

780 {
781 assert_param(IS_CAN_ALL(hperh->perh));
782 assert_param(IS_CAN_IT(it));
783 assert_param(IS_FUNC_STATE(state));
784
785 if (state == ENABLE)
786 SET_BIT(hperh->perh->IE, it);
787 else
788 CLEAR_BIT(hperh->perh->IE, it);
789
790 return;
791 }
ENABLE
Definition: type.h:49
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
IS_CAN_IT
#define IS_CAN_IT(x)
Definition: ald_can.h:383
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_CAN_ALL
#define IS_CAN_ALL(x)
Definition: ald_can.h:326
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_can_irq_handler()

void ald_can_irq_handler ( can_handle_t * hperh )

Handles CAN interrupt request.

Parameters
hperh pointer to a can_handle_t structure.
Return values
None

Definition at line 596 of file ald_can.c.

597 {
598 if (ald_can_get_it_status(hperh, CAN_IT_TXM)) {
599 if ((ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_0))
600 || (ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_1))
601 || (ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_2)))
602 __can_send_by_it(hperh, 0);
603 if (hperh->perh->TXSTAT & CAN_TXSTAT_M0TXERR_MSK) {
604 SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M0REQC_MSK);
605 __can_send_by_it(hperh, 1);
606 }
607 if (hperh->perh->TXSTAT & CAN_TXSTAT_M1TXERR_MSK) {
608 SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M1REQC_MSK);
609 __can_send_by_it(hperh, 1);
610 }
611 if (hperh->perh->TXSTAT & CAN_TXSTAT_M2TXERR_MSK) {
612 SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M2REQC_MSK);
613 __can_send_by_it(hperh, 1);
614 }
615 }
616
617 if ((ald_can_get_it_status(hperh, CAN_IT_FP0))
618 && (CAN_RX_MSG_PENDING(hperh, CAN_RX_FIFO0) != 0))
619 __can_recv_by_it(hperh, CAN_RX_FIFO0);
620
621 if ((ald_can_get_it_status(hperh, CAN_IT_FP1))
622 && (CAN_RX_MSG_PENDING(hperh, CAN_RX_FIFO1) != 0))
623 __can_recv_by_it(hperh, CAN_RX_FIFO1);
624
625 if ((ald_can_get_flag_status(hperh, CAN_FLAG_WARN))
626 && (ald_can_get_it_status(hperh, CAN_IT_WARN))
627 && (ald_can_get_it_status(hperh, CAN_IT_ERR)))
628 hperh->err |= CAN_ERROR_EWG;
629
630 if ((ald_can_get_flag_status(hperh, CAN_FLAG_PERR))
631 && (ald_can_get_it_status(hperh, CAN_IT_PERR))
632 && (ald_can_get_it_status(hperh, CAN_IT_ERR)))
633 hperh->err |= CAN_ERROR_EPV;
634
635 if ((ald_can_get_flag_status(hperh, CAN_FLAG_BOF))
636 && (ald_can_get_it_status(hperh, CAN_IT_BOF))
637 && (ald_can_get_it_status(hperh, CAN_IT_ERR)))
638 hperh->err |= CAN_ERROR_BOF;
639
640 if (READ_BIT(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK)
641 && (ald_can_get_it_status(hperh, CAN_IT_PRERR))
642 && (ald_can_get_it_status(hperh, CAN_IT_ERR))) {
643
644 switch (READ_BITS(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK, CAN_ERRSTAT_PRERRF_POSS)) {
645 case(1):
646 hperh->err |= CAN_ERROR_STF;
647 break;
648 case(2):
649 hperh->err |= CAN_ERROR_FOR;
650 break;
651 case(3):
652 hperh->err |= CAN_ERROR_ACK;
653 break;
654 case(4):
655 hperh->err |= CAN_ERROR_BR;
656 break;
657 case(5):
658 hperh->err |= CAN_ERROR_BD;
659 break;
660 case(6):
661 hperh->err |= CAN_ERROR_CRC;
662 break;
663 default:
664 break;
665 }
666
667 CLEAR_BIT(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK);
668
669 if (READ_BIT(hperh->perh->IE, CAN_IE_TXMEIE_MSK))
670 ald_can_interrupt_config(hperh, CAN_IT_TXM, DISABLE);
671
672 if (READ_BIT(hperh->perh->IE, CAN_IE_F0PIE_MSK))
673 ald_can_interrupt_config(hperh, CAN_IT_FP0, DISABLE);
674
675 if (READ_BIT(hperh->perh->IE, CAN_IE_F1PIE_MSK))
676 ald_can_interrupt_config(hperh, CAN_IT_FP1, DISABLE);
677 }
678
679 if ((ald_can_get_flag_status(hperh, CAN_FLAG_ERR)) && (hperh->err == CAN_ERROR_NONE))
680 hperh->err = CAN_ERROR_UNK;
681
682 if (hperh->err != CAN_ERROR_NONE) {
683 SET_BIT(hperh->perh->IFC, CAN_IFC_ERRIFC_MSK);
684 hperh->state = CAN_STATE_READY;
685
686 if (hperh->error_cbk != NULL)
687 hperh->error_cbk(hperh);
688 }
689 }
CAN_ERROR_UNK
Definition: ald_can.h:68
CAN_ERROR_BR
Definition: ald_can.h:65
CAN_FLAG_ERR
Definition: ald_can.h:190
CAN_IT_FP1
Definition: ald_can.h:219
CAN_RX_MSG_PENDING
#define CAN_RX_MSG_PENDING(x, y)
Definition: ald_can.h:314
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
ald_can_get_flag_status
flag_status_t ald_can_get_flag_status(can_handle_t *hperh, can_flag_t flag)
Get the status of CAN interrupt flag.
Definition: ald_can.c:822
CAN_ERROR_BD
Definition: ald_can.h:66
DISABLE
Definition: type.h:48
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
CAN_ERROR_EWG
Definition: ald_can.h:59
CAN_ERROR_NONE
Definition: ald_can.h:58
CAN_ERROR_ACK
Definition: ald_can.h:64
CAN_ERROR_CRC
Definition: ald_can.h:67
CAN_IT_ERR
Definition: ald_can.h:226
CAN_STATE_READY
Definition: ald_can.h:41
CAN_TX_MAILBOX_2
Definition: ald_can.h:173
CAN_IT_WARN
Definition: ald_can.h:222
ald_can_get_tx_status
type_bool_t ald_can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box)
Check the transmission status of a CAN Frame.
Definition: ald_can.c:697
CAN_ERROR_BOF
Definition: ald_can.h:61
CAN_FLAG_BOF
Definition: ald_can.h:208
CAN_TX_MAILBOX_1
Definition: ald_can.h:172
CAN_IT_TXM
Definition: ald_can.h:215
CAN_ERROR_EPV
Definition: ald_can.h:60
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
CAN_RX_FIFO1
Definition: ald_can.h:182
ald_can_get_it_status
it_status_t ald_can_get_it_status(can_handle_t *hperh, can_it_t it)
Get the status of CAN interrupt source.
Definition: ald_can.c:802
CAN_IT_PRERR
Definition: ald_can.h:225
can_handle_s::err
can_error_t err
Definition: ald_can.h:300
CAN_TX_MAILBOX_0
Definition: ald_can.h:171
CAN_IT_PERR
Definition: ald_can.h:223
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
can_handle_s::state
can_state_t state
Definition: ald_can.h:299
__can_recv_by_it
static ald_status_t __can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num)
Receives a correct CAN frame using interrupt.
Definition: ald_can.c:1032
CAN_FLAG_PERR
Definition: ald_can.h:207
CAN_ERROR_FOR
Definition: ald_can.h:63
CAN_FLAG_WARN
Definition: ald_can.h:206
ald_can_interrupt_config
void ald_can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state)
Enable/disable the specified CAN interrupts.
Definition: ald_can.c:779
__can_send_by_it
static ald_status_t __can_send_by_it(can_handle_t *hperh, uint8_t err)
transmits a CAN frame message using interrupt.
Definition: ald_can.c:965
can_handle_s::error_cbk
void(* error_cbk)(struct can_handle_s *arg)
Definition: ald_can.h:304
CAN_RX_FIFO0
Definition: ald_can.h:181
CAN_ERROR_STF
Definition: ald_can.h:62
CAN_IT_BOF
Definition: ald_can.h:224
CAN_IT_FP0
Definition: ald_can.h:216

◆ ald_can_sleep()

ald_status_t ald_can_sleep ( can_handle_t * hperh )

Enters the Sleep(low power) mode.

Parameters
hperh pointer to a can_handle_t.
Return values
Status,see ald_status_t.

Definition at line 532 of file ald_can.c.

533 {
534 uint32_t tick;
535
536 assert_param(IS_CAN_ALL(hperh->perh));
537
538 __LOCK(hperh);
539 hperh->state = CAN_STATE_BUSY;
540
541 CLEAR_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK);
542 SET_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK);
543 tick = ald_get_tick();
544
545 while ((!(READ_BIT(hperh->perh->STAT, CAN_STAT_SLPSTAT_MSK))) || READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) {
546 if ((ald_get_tick() - tick) > CAN_TIMEOUT_VALUE) {
547 hperh->state = CAN_STATE_TIMEOUT;
548 __UNLOCK(hperh);
549 return TIMEOUT;
550 }
551 }
552
553 hperh->state = CAN_STATE_READY;
554 __UNLOCK(hperh);
555
556 return OK;
557 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
CAN_STATE_READY
Definition: ald_can.h:41
CAN_STATE_TIMEOUT
Definition: ald_can.h:50
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
CAN_TIMEOUT_VALUE
#define CAN_TIMEOUT_VALUE
Definition: ald_can.h:397
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
can_handle_s::state
can_state_t state
Definition: ald_can.h:299
CAN_STATE_BUSY
Definition: ald_can.h:42
IS_CAN_ALL
#define IS_CAN_ALL(x)
Definition: ald_can.h:326
__LOCK
#define __LOCK(x)
Definition: utils.h:92

◆ ald_can_wake_up()

ald_status_t ald_can_wake_up ( can_handle_t * hperh )

Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral is in the normal mode.

Parameters
hperh pointer to a can_handle_t structure.
Return values
Status,see ald_status_t.

Definition at line 565 of file ald_can.c.

566 {
567 uint32_t tick;
568
569 assert_param(IS_CAN_ALL(hperh->perh));
570
571 __LOCK(hperh);
572 hperh->state = CAN_STATE_BUSY;
573
574 CLEAR_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK);
575 tick = ald_get_tick();
576
577 while (READ_BIT(hperh->perh->STAT, CAN_STAT_SLPSTAT_MSK)) {
578 if ((ald_get_tick() - tick) > CAN_TIMEOUT_VALUE) {
579 hperh->state = CAN_STATE_TIMEOUT;
580 __UNLOCK(hperh);
581 return TIMEOUT;
582 }
583 }
584
585 hperh->state = CAN_STATE_READY;
586 __UNLOCK(hperh);
587
588 return OK;
589 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
CAN_STATE_READY
Definition: ald_can.h:41
CAN_STATE_TIMEOUT
Definition: ald_can.h:50
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
CAN_TIMEOUT_VALUE
#define CAN_TIMEOUT_VALUE
Definition: ald_can.h:397
can_handle_s::state
can_state_t state
Definition: ald_can.h:299
CAN_STATE_BUSY
Definition: ald_can.h:42
IS_CAN_ALL
#define IS_CAN_ALL(x)
Definition: ald_can.h:326
__LOCK
#define __LOCK(x)
Definition: utils.h:92

◆ can_clear_flag()

void can_clear_flag | ( | can_handle_t * | hperh,
 |  | can_flag_t | flag
 | ) |  |

Clear the specified CAN pending flag.

Parameters
hperh | pointer to a can_handle_t structure.
flag | specifies the flag to check.
Return values
None.

Definition at line 867 of file ald_can.c.

868 {
869 uint32_t idx = ((uint32_t)flag >> 20) & 0x7;
870 uint32_t _flag = flag & 0xFF8FFFFFU;
871
872 assert_param(IS_CAN_CLEAR_FLAG(flag));
873
874 switch (idx) {
875 case 0:
876 WRITE_REG(hperh->perh->IFC, _flag);
877 break;
878 case 1:
879 WRITE_REG(hperh->perh->TXSTATC, _flag);
880 break;
881 case 2:
882 WRITE_REG(hperh->perh->RXF0C, _flag);
883 break;
884 case 3:
885 WRITE_REG(hperh->perh->RXF1C, _flag);
886 break;
887 default:
888 break;
889 }
890
891 return;
892 }
assert_param
#define assert_param(x)
Definition: type.h:88
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
IS_CAN_CLEAR_FLAG
#define IS_CAN_CLEAR_FLAG(x)
Definition: ald_can.h:373
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72


ALD User Manual: Peripheral State and Error functions

Functions
Peripheral State and Error functions
EASTSOFT ES32F3xx ALD » CAN » CAN Public Functions

CAN Peripheral State functions. More...

Collaboration diagram for Peripheral State and Error functions:

Functions

can_state_t | ald_can_get_state (can_handle_t *hperh)
return the CAN state More...
can_error_t | ald_can_get_error (can_handle_t *hperh)
Return the CAN error code. More...

Detailed Description

CAN Peripheral State functions.

==============================================================================
          ##### Peripheral State and Error functions #####
==============================================================================
  [..]
  This subsection provides functions allowing to:
    (+) Check the CAN state.
    (+) Check CAN Errors detected during interrupt process

*

Function Documentation

◆ ald_can_get_error()

can_error_t ald_can_get_error ( can_handle_t * hperh )

Return the CAN error code.

Parameters
hperh pointer to a can_handle_t structure.
Return values
CAN Error Code

Definition at line 927 of file ald_can.c.

928 {
929 return hperh->err;
930 }
can_handle_s::err
can_error_t err
Definition: ald_can.h:300

◆ ald_can_get_state()

can_state_t ald_can_get_state ( can_handle_t * hperh )

return the CAN state

Parameters
hperh pointer to a can_handle_t structure.
Return values
Status,see can_state_t.

Definition at line 917 of file ald_can.c.

918 {
919 return hperh->state;
920 }
can_handle_s::state
can_state_t state
Definition: ald_can.h:299


ALD User Manual: CAN Private Functions

Functions
CAN Private Functions
EASTSOFT ES32F3xx ALD » CAN
Collaboration diagram for CAN Private Functions:

Functions

static void | can_rx_fifo_release (can_handle_t *hperh, can_rx_fifo_t num)
Release rx FIFO. More...
static ald_status_t | __can_send_by_it (can_handle_t *hperh, uint8_t err)
transmits a CAN frame message using interrupt. More...
static ald_status_t | __can_recv_by_it (can_handle_t *hperh, can_rx_fifo_t num)
Receives a correct CAN frame using interrupt. More...
static int | __can_rx_check (can_handle_t *hperh, can_rx_fifo_t num)
Check whether the data in the mailbox is contaminated. More...

Detailed Description

Function Documentation

◆ __can_recv_by_it()

static ald_status_t __can_recv_by_it | ( | can_handle_t * | hperh,
 |  | can_rx_fifo_t | num
 | ) |  |
static

Receives a correct CAN frame using interrupt.

Parameters
hperh | Pointer to a can_handle_t structure.
num | Specify the FIFO number
Return values
Status,see ald_status_t.

Definition at line 1032 of file ald_can.c.

1033 {
1034 uint32_t stid, exid;
1035 can_rx_msg_t *_msg;
1036
1037 if (__can_rx_check(hperh, num))
1038 return ERROR;
1039
1040 stid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_STDID_MSK, CAN_RXF0ID_STDID_POSS);
1041 exid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_EXID_MSK, CAN_RXF0ID_EXID_POSS);
1042
1043 _msg = num == CAN_RX_FIFO0 ? hperh->rx0_msg : hperh->rx1_msg;
1044 _msg->type = (can_id_type_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_IDE_MSK, CAN_RXF0ID_IDE_POS);
1045
1046 if (_msg->type == CAN_ID_STD)
1047 _msg->std = stid;
1048 else
1049 _msg->ext = (stid << 18) | exid;
1050
1051 _msg->rtr = (can_remote_req_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_RTR_MSK, CAN_RXF0ID_RTR_POS);
1052 _msg->len = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_DLEN_MSK, CAN_RXF0INF_DLEN_POSS);
1053 _msg->fmi = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_FLTIDX_MSK, CAN_RXF0INF_FLTIDX_POSS);
1054 _msg->data[0] = hperh->perh->RxFIFO[num].RXFDL & 0xFF;
1055 _msg->data[1] = (hperh->perh->RxFIFO[num].RXFDL >> 8) & 0xFF;
1056 _msg->data[2] = (hperh->perh->RxFIFO[num].RXFDL >> 16) & 0xFF;
1057 _msg->data[3] = (hperh->perh->RxFIFO[num].RXFDL >> 24) & 0xFF;
1058 _msg->data[4] = hperh->perh->RxFIFO[num].RXFDH & 0xFF;
1059 _msg->data[5] = (hperh->perh->RxFIFO[num].RXFDH >> 8) & 0xFF;
1060 _msg->data[6] = (hperh->perh->RxFIFO[num].RXFDH >> 16) & 0xFF;
1061 _msg->data[7] = (hperh->perh->RxFIFO[num].RXFDH >> 24) & 0xFF;
1062
1063 if (num == CAN_RX_FIFO0) {
1064 can_rx_fifo_release(hperh, CAN_RX_FIFO0);
1065 ald_can_interrupt_config(hperh, CAN_IT_FP0, DISABLE);
1066 CLEAR_BIT(hperh->state, CAN_STATE_RX0_MASK);
1067 }
1068 else {
1069 can_rx_fifo_release(hperh, CAN_RX_FIFO1);
1070 ald_can_interrupt_config(hperh, CAN_IT_FP1, DISABLE);
1071 CLEAR_BIT(hperh->state, CAN_STATE_RX1_MASK);
1072 }
1073
1074 if (hperh->state == CAN_STATE_READY) {
1075 ald_can_interrupt_config(hperh, CAN_IT_WARN, DISABLE);
1076 ald_can_interrupt_config(hperh, CAN_IT_PERR, DISABLE);
1077 ald_can_interrupt_config(hperh, CAN_IT_BOF, DISABLE);
1078 ald_can_interrupt_config(hperh, CAN_IT_PRERR, DISABLE);
1079 ald_can_interrupt_config(hperh, CAN_IT_ERR, DISABLE);
1080 }
1081
1082 if (hperh->rx_cplt_cbk)
1083 hperh->rx_cplt_cbk(hperh, num);
1084
1085 return OK;
1086 }
can_rx_msg_t::ext
uint32_t ext
Definition: ald_can.h:281
OK
Definition: utils.h:55
CAN_IT_FP1
Definition: ald_can.h:219
can_handle_s::rx1_msg
can_rx_msg_t * rx1_msg
Definition: ald_can.h:297
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
can_rx_msg_t::fmi
uint32_t fmi
Definition: ald_can.h:286
DISABLE
Definition: type.h:48
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
can_handle_s::rx0_msg
can_rx_msg_t * rx0_msg
Definition: ald_can.h:296
CAN_IT_ERR
Definition: ald_can.h:226
CAN_STATE_READY
Definition: ald_can.h:41
CAN_STATE_RX0_MASK
#define CAN_STATE_RX0_MASK
Definition: ald_can.h:399
CAN_IT_WARN
Definition: ald_can.h:222
can_rx_msg_t::std
uint32_t std
Definition: ald_can.h:280
can_rx_msg_t
CAN Rx message structure definition.
Definition: ald_can.h:279
can_handle_s::rx_cplt_cbk
void(* rx_cplt_cbk)(struct can_handle_s *arg, can_rx_fifo_t num)
Definition: ald_can.h:303
CAN_RX_FIFO1
Definition: ald_can.h:182
CAN_STATE_RX1_MASK
#define CAN_STATE_RX1_MASK
Definition: ald_can.h:400
CAN_IT_PRERR
Definition: ald_can.h:225
can_rx_msg_t::len
uint32_t len
Definition: ald_can.h:284
CAN_IT_PERR
Definition: ald_can.h:223
can_handle_s::state
can_state_t state
Definition: ald_can.h:299
can_rx_fifo_release
static void can_rx_fifo_release(can_handle_t *hperh, can_rx_fifo_t num)
Release rx FIFO.
Definition: ald_can.c:950
can_rx_msg_t::data
uint8_t data[8]
Definition: ald_can.h:285
can_remote_req_t
can_remote_req_t
CAN Remote Transmission Request.
Definition: ald_can.h:162
can_rx_msg_t::rtr
can_remote_req_t rtr
Definition: ald_can.h:283
ald_can_interrupt_config
void ald_can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state)
Enable/disable the specified CAN interrupts.
Definition: ald_can.c:779
CAN_ID_STD
Definition: ald_can.h:155
CAN_RX_FIFO0
Definition: ald_can.h:181
ERROR
Definition: utils.h:56
CAN_IT_BOF
Definition: ald_can.h:224
CAN_IT_FP0
Definition: ald_can.h:216
__can_rx_check
static int __can_rx_check(can_handle_t *hperh, can_rx_fifo_t num)
Check whether the data in the mailbox is contaminated.
Definition: ald_can.c:998
can_rx_msg_t::type
can_id_type_t type
Definition: ald_can.h:282
can_id_type_t
can_id_type_t
CAN Identifier Type.
Definition: ald_can.h:154

◆ __can_rx_check()

static int __can_rx_check | ( | can_handle_t * | hperh,
 |  | can_rx_fifo_t | num
 | ) |  |
static

Check whether the data in the mailbox is contaminated.

Parameters
hperh | Pointer to a can_handle_t structure.
num | Specify the FIFO number
Return values
status
  • 0: Data is valid
  • 1: Data is invalid

Definition at line 998 of file ald_can.c.

999 {
1000 int i;
1001
1002 if (!(hperh->perh->RESERVED0[0] & 0x200000U))
1003 return 0;
1004
1005 if (num == CAN_RX_FIFO0) {
1006 for (i = 0; i < 3; ++i) {
1007 if (hperh->perh->RXF0 & 0x3)
1008 SET_BIT(hperh->perh->RXF0, CAN_RXF0_FREE_MSK);
1009 else
1010 break;
1011 }
1012 }
1013 else {
1014 for (i = 0; i < 3; ++i) {
1015 if (hperh->perh->RXF1 & 0x3)
1016 SET_BIT(hperh->perh->RXF1, CAN_RXF1_FREE_MSK);
1017 else
1018 break;
1019 }
1020 }
1021
1022 hperh->perh->RESERVED0[0] |= 0x200000U;
1023 return 1;
1024 }
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
CAN_RX_FIFO0
Definition: ald_can.h:181

◆ __can_send_by_it()

static ald_status_t __can_send_by_it | ( | can_handle_t * | hperh,
 |  | uint8_t | err
 | ) |  |
static

transmits a CAN frame message using interrupt.

Parameters
hperh | pointer to a can_handle_t structure.
err | Error code, 0 - success, 1 - error.
Return values
Status,see ald_status_t.

Definition at line 965 of file ald_can.c.

966 {
967 ald_can_interrupt_config(hperh, CAN_IT_TXM, DISABLE);
968
969 if (hperh->state == CAN_STATE_BUSY_TX) {
970 ald_can_interrupt_config(hperh, CAN_IT_WARN, DISABLE);
971 ald_can_interrupt_config(hperh, CAN_IT_PERR, DISABLE);
972 ald_can_interrupt_config(hperh, CAN_IT_BOF, DISABLE);
973 ald_can_interrupt_config(hperh, CAN_IT_PRERR, DISABLE);
974 ald_can_interrupt_config(hperh, CAN_IT_ERR, DISABLE);
975 }
976
977 CLEAR_BIT(hperh->state, CAN_STATE_TX_MASK);
978
979 if ((err == 0) && (hperh->tx_cplt_cbk))
980 hperh->tx_cplt_cbk(hperh);
981
982 if ((err) && (hperh->error_cbk != NULL)) {
983 hperh->err = CAN_ERROR_UNK;
984 hperh->error_cbk(hperh);
985 }
986
987 return OK;
988 }
CAN_ERROR_UNK
Definition: ald_can.h:68
OK
Definition: utils.h:55
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
DISABLE
Definition: type.h:48
CAN_IT_ERR
Definition: ald_can.h:226
CAN_IT_WARN
Definition: ald_can.h:222
CAN_STATE_BUSY_TX
Definition: ald_can.h:43
CAN_IT_TXM
Definition: ald_can.h:215
CAN_IT_PRERR
Definition: ald_can.h:225
can_handle_s::err
can_error_t err
Definition: ald_can.h:300
CAN_IT_PERR
Definition: ald_can.h:223
can_handle_s::state
can_state_t state
Definition: ald_can.h:299
can_handle_s::tx_cplt_cbk
void(* tx_cplt_cbk)(struct can_handle_s *arg)
Definition: ald_can.h:302
ald_can_interrupt_config
void ald_can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state)
Enable/disable the specified CAN interrupts.
Definition: ald_can.c:779
can_handle_s::error_cbk
void(* error_cbk)(struct can_handle_s *arg)
Definition: ald_can.h:304
CAN_IT_BOF
Definition: ald_can.h:224
CAN_STATE_TX_MASK
#define CAN_STATE_TX_MASK
Definition: ald_can.h:398

◆ can_rx_fifo_release()

static void can_rx_fifo_release | ( | can_handle_t * | hperh,
 |  | can_rx_fifo_t | num
 | ) |  |
static

Release rx FIFO.

Parameters
hperh | pointer to a can_handle_t structure.
num | Receive fifo number, CAN_RX_FIFO0 or CAN_RX_FIFO1
Return values
None

Definition at line 950 of file ald_can.c.

951 {
952 if (num == CAN_RX_FIFO0)
953 SET_BIT(hperh->perh->RXF0, CAN_RXF0_FREE_MSK);
954 else
955 SET_BIT(hperh->perh->RXF1, CAN_RXF1_FREE_MSK);
956 }
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
CAN_RX_FIFO0
Definition: ald_can.h:181


ALD User Manual: CAN Public Types

Data Structures | Typedefs | Enumerations
CAN Public Types
EASTSOFT ES32F3xx ALD » CAN
Collaboration diagram for CAN Public Types:

Data Structures

struct | can_filter_t
CAN filter configuration structure definition. More...
struct | can_init_t
CAN init structure definition. More...
struct | can_tx_msg_t
CAN Tx message structure definition. More...
struct | can_rx_msg_t
CAN Rx message structure definition. More...
struct | can_handle_s
CAN handle Structure definition. More...

Typedefs

typedef struct can_handle_s can_handle_t
CAN handle Structure definition. More...

Enumerations

enum can_state_t {
CAN_STATE_RESET = 0x00U, CAN_STATE_READY = 0x01U, CAN_STATE_BUSY = 0x02U, CAN_STATE_BUSY_TX = 0x11U,
CAN_STATE_BUSY_RX0 = 0x21U, CAN_STATE_BUSY_RX1 = 0x41U, CAN_STATE_BUSY_TX_RX0 = 0x31U, CAN_STATE_BUSY_TX_RX1 = 0x51U,
CAN_STATE_BUSY_RX0_RX1 = 0x61U, CAN_STATE_BUSY_TX_RX0_RX1 = 0x71U, CAN_STATE_TIMEOUT = 0x04U, CAN_STATE_ERROR = 0x08U
}
ALD State structures definition. More...
enum can_error_t {
CAN_ERROR_NONE = 0x00U, CAN_ERROR_EWG = 0x01U, CAN_ERROR_EPV = 0x02U, CAN_ERROR_BOF = 0x04U,
CAN_ERROR_STF = 0x08U, CAN_ERROR_FOR = 0x10U, CAN_ERROR_ACK = 0x20U, CAN_ERROR_BR = 0x40U,
CAN_ERROR_BD = 0x80U, CAN_ERROR_CRC = 0x100U, CAN_ERROR_UNK = 0x200U
}
CAN Error Code. More...
enum | can_operate_mode_t { CAN_MODE_NORMAL = 0x00U, CAN_MODE_LOOPBACK = 0x01U, CAN_MODE_SILENT = 0x02U, CAN_MODE_SILENT_LOOPBACK = 0x03U }
CAN Operating Mode. More...
enum | can_sjw_t { CAN_SJW_1 = 0x0U, CAN_SJW_2 = 0x1U, CAN_SJW_3 = 0x2U, CAN_SJW_4 = 0x3U }
CAN Synchronization Jump Width. More...
enum can_seg1_t {
CAN_SEG1_1 = 0x0U, CAN_SEG1_2 = 0x1U, CAN_SEG1_3 = 0x2U, CAN_SEG1_4 = 0x3U,
CAN_SEG1_5 = 0x4U, CAN_SEG1_6 = 0x5U, CAN_SEG1_7 = 0x6U, CAN_SEG1_8 = 0x7U,
CAN_SEG1_9 = 0x8U, CAN_SEG1_10 = 0x9U, CAN_SEG1_11 = 0xAU, CAN_SEG1_12 = 0xBU,
CAN_SEG1_13 = 0xCU, CAN_SEG1_14 = 0xDU, CAN_SEG1_15 = 0xEU, CAN_SEG1_16 = 0xFU
}
CAN Time Quantum in Bit Segment 1. More...
enum can_seg2_t {
CAN_SEG2_1 = 0x0U, CAN_SEG2_2 = 0x1U, CAN_SEG2_3 = 0x2U, CAN_SEG2_4 = 0x3U,
CAN_SEG2_5 = 0x4U, CAN_SEG2_6 = 0x5U, CAN_SEG2_7 = 0x6U, CAN_SEG2_8 = 0x7U
}
CAN Time Quantum in Bit Segment 2. More...
enum | can_filter_mode_t { CAN_FILTER_MODE_MASK = 0x0U, CAN_FILTER_MODE_LIST = 0x1U }
CAN Filter Mode. More...
enum | can_filter_scale_t { CAN_FILTER_SCALE_16 = 0x0U, CAN_FILTER_SCALE_32 = 0x1U }
CAN Filter Scale. More...
enum | can_filter_fifo_t { CAN_FILTER_FIFO0 = 0x0U, CAN_FILTER_FIFO1 = 0x1U }
CAN Filter fifo. More...
enum | can_id_type_t { CAN_ID_STD = 0x0U, CAN_ID_EXT = 0x1U }
CAN Identifier Type. More...
enum | can_remote_req_t { CAN_RTR_DATA = 0x0U, CAN_RTR_REMOTE = 0x1U }
CAN Remote Transmission Request. More...
enum | can_tx_mailbox_t { CAN_TX_MAILBOX_0 = 0x0U, CAN_TX_MAILBOX_1 = 0x1U, CAN_TX_MAILBOX_2 = 0x2U, CAN_TX_MAILBOX_NONE = 0x3U }
CAN Transmit Constants. More...
enum | can_rx_fifo_t { CAN_RX_FIFO0 = 0x0U, CAN_RX_FIFO1 = 0x1U }
CAN Receive fifo Number. More...
enum can_flag_t {
CAN_FLAG_SLPS = (1U << 1), CAN_FLAG_ERR = (1U << 2), CAN_FLAG_WK = (1U << 3), CAN_FLAG_SLP = (1U << 4),
CAN_FLAG_M0REQC = (1U << 20) | (1U << 0), CAN_FLAG_M0TXC = (1U << 20) | (1U << 1), CAN_FLAG_M1REQC = (1U << 20) | (1U << 8), CAN_FLAG_M1TXC = (1U << 20) | (1U << 9),
CAN_FLAG_M2REQC = (1U << 20) | (1U << 16), CAN_FLAG_M2TXC = (1U << 20) | (1U << 17), CAN_FLAG_TXM0 = (1U << 20) | (1U << 26), CAN_FLAG_TXM1 = (1U << 20) | (1U << 27),
CAN_FLAG_TXM2 = (1U << 20) | (1U << 28), CAN_FLAG_FF0 = (2U << 20) | (1U << 3), CAN_FLAG_FOV0 = (2U << 20) | (1U << 4), CAN_FLAG_FF1 = (3U << 20) | (1U << 3),
CAN_FLAG_FOV1 = (3U << 20) | (1U << 4), CAN_FLAG_WARN = (4U << 20) | (1U << 0), CAN_FLAG_PERR = (4U << 20) | (1U << 1), CAN_FLAG_BOF = (4U << 20) | (1U << 2)
}
CAN Flags. More...
enum can_it_t {
CAN_IT_TXM = (1U << 0), CAN_IT_FP0 = (1U << 1), CAN_IT_FF0 = (1U << 2), CAN_IT_FOV0 = (1U << 3),
CAN_IT_FP1 = (1U << 4), CAN_IT_FF1 = (1U << 5), CAN_IT_FOV1 = (1U << 6), CAN_IT_WARN = (1U << 8),
CAN_IT_PERR = (1U << 9), CAN_IT_BOF = (1U << 10), CAN_IT_PRERR = (1U << 11), CAN_IT_ERR = (1U << 15),
CAN_IT_WK = (1U << 16), CAN_IT_SLP = (1U << 17)
}
CAN Interrupts. More...

Detailed Description

Typedef Documentation

◆ can_handle_t

typedef struct can_handle_s can_handle_t

CAN handle Structure definition.

Enumeration Type Documentation

◆ can_error_t

enum can_error_t

CAN Error Code.

Enumerator
CAN_ERROR_NONE | No error
CAN_ERROR_EWG | EWG error
CAN_ERROR_EPV | EPV error
CAN_ERROR_BOF | BOF error
CAN_ERROR_STF | Stuff error
CAN_ERROR_FOR | Form error
CAN_ERROR_ACK | Acknowledgment error
CAN_ERROR_BR | Bit recessive
CAN_ERROR_BD | LEC dominant
CAN_ERROR_CRC | LEC transfer error
CAN_ERROR_UNK | Unknown error

Definition at line 57 of file ald_can.h.

57 {
58 CAN_ERROR_NONE = 0x00U,
59 CAN_ERROR_EWG = 0x01U,
60 CAN_ERROR_EPV = 0x02U,
61 CAN_ERROR_BOF = 0x04U,
62 CAN_ERROR_STF = 0x08U,
63 CAN_ERROR_FOR = 0x10U,
64 CAN_ERROR_ACK = 0x20U,
65 CAN_ERROR_BR = 0x40U,
66 CAN_ERROR_BD = 0x80U,
67 CAN_ERROR_CRC = 0x100U,
68 CAN_ERROR_UNK = 0x200U,
69 } can_error_t;
CAN_ERROR_UNK
Definition: ald_can.h:68
CAN_ERROR_BR
Definition: ald_can.h:65
CAN_ERROR_BD
Definition: ald_can.h:66
CAN_ERROR_EWG
Definition: ald_can.h:59
can_error_t
can_error_t
CAN Error Code.
Definition: ald_can.h:57
CAN_ERROR_NONE
Definition: ald_can.h:58
CAN_ERROR_ACK
Definition: ald_can.h:64
CAN_ERROR_CRC
Definition: ald_can.h:67
CAN_ERROR_BOF
Definition: ald_can.h:61
CAN_ERROR_EPV
Definition: ald_can.h:60
CAN_ERROR_FOR
Definition: ald_can.h:63
CAN_ERROR_STF
Definition: ald_can.h:62

◆ can_filter_fifo_t

enum can_filter_fifo_t

CAN Filter fifo.

Enumerator
CAN_FILTER_FIFO0 | FIFO 0 assignment for filter
CAN_FILTER_FIFO1 | FIFO 1 assignment for filter

Definition at line 146 of file ald_can.h.

146 {
147 CAN_FILTER_FIFO0 = 0x0U,
148 CAN_FILTER_FIFO1 = 0x1U,
149 } can_filter_fifo_t;
CAN_FILTER_FIFO0
Definition: ald_can.h:147
can_filter_fifo_t
can_filter_fifo_t
CAN Filter fifo.
Definition: ald_can.h:146
CAN_FILTER_FIFO1
Definition: ald_can.h:148

◆ can_filter_mode_t

enum can_filter_mode_t

CAN Filter Mode.

Enumerator
CAN_FILTER_MODE_MASK | Identifier mask mode
CAN_FILTER_MODE_LIST | Identifier list mode

Definition at line 130 of file ald_can.h.

130 {
131 CAN_FILTER_MODE_MASK = 0x0U,
132 CAN_FILTER_MODE_LIST = 0x1U,
133 } can_filter_mode_t;
CAN_FILTER_MODE_MASK
Definition: ald_can.h:131
can_filter_mode_t
can_filter_mode_t
CAN Filter Mode.
Definition: ald_can.h:130
CAN_FILTER_MODE_LIST
Definition: ald_can.h:132

◆ can_filter_scale_t

enum can_filter_scale_t

CAN Filter Scale.

Enumerator
CAN_FILTER_SCALE_16 | Two 16-bit filters
CAN_FILTER_SCALE_32 | One 32-bit filter

Definition at line 138 of file ald_can.h.

138 {
139 CAN_FILTER_SCALE_16 = 0x0U,
140 CAN_FILTER_SCALE_32 = 0x1U,
141 } can_filter_scale_t;
can_filter_scale_t
can_filter_scale_t
CAN Filter Scale.
Definition: ald_can.h:138
CAN_FILTER_SCALE_16
Definition: ald_can.h:139
CAN_FILTER_SCALE_32
Definition: ald_can.h:140

◆ can_flag_t

enum can_flag_t

CAN Flags.

Enumerator
CAN_FLAG_SLPS | Sleep acknowledge flag
CAN_FLAG_ERR | Error flag
CAN_FLAG_WK | Wake up flag
CAN_FLAG_SLP | Sleep acknowledge flag
CAN_FLAG_M0REQC | Request MailBox0 flag
CAN_FLAG_M0TXC | Transmission OK MailBox0 flag
CAN_FLAG_M1REQC | Request MailBox1 flag
CAN_FLAG_M1TXC | Transmission OK MailBox1 flag
CAN_FLAG_M2REQC | Request MailBox2 flag
CAN_FLAG_M2TXC | Transmission OK MailBox2 flag
CAN_FLAG_TXM0 | Transmit mailbox 0 empty flag
CAN_FLAG_TXM1 | Transmit mailbox 1 empty flag
CAN_FLAG_TXM2 | Transmit mailbox 2 empty flag
CAN_FLAG_FF0 | FIFO 0 Full flag
CAN_FLAG_FOV0 | FIFO 0 Overrun flag
CAN_FLAG_FF1 | FIFO 1 Full flag
CAN_FLAG_FOV1 | FIFO 1 Overrun flag
CAN_FLAG_WARN | Error warning flag
CAN_FLAG_PERR | Error passive flag
CAN_FLAG_BOF | Bus-Off flag

Definition at line 188 of file ald_can.h.

188 {
189 CAN_FLAG_SLPS = (1U << 1),
190 CAN_FLAG_ERR = (1U << 2),
191 CAN_FLAG_WK = (1U << 3),
192 CAN_FLAG_SLP = (1U << 4),
193 CAN_FLAG_M0REQC = (1U << 20) | (1U << 0),
194 CAN_FLAG_M0TXC = (1U << 20) | (1U << 1),
195 CAN_FLAG_M1REQC = (1U << 20) | (1U << 8),
196 CAN_FLAG_M1TXC = (1U << 20) | (1U << 9),
197 CAN_FLAG_M2REQC = (1U << 20) | (1U << 16),
198 CAN_FLAG_M2TXC = (1U << 20) | (1U << 17),
199 CAN_FLAG_TXM0 = (1U << 20) | (1U << 26),
200 CAN_FLAG_TXM1 = (1U << 20) | (1U << 27),
201 CAN_FLAG_TXM2 = (1U << 20) | (1U << 28),
202 CAN_FLAG_FF0 = (2U << 20) | (1U << 3),
203 CAN_FLAG_FOV0 = (2U << 20) | (1U << 4),
204 CAN_FLAG_FF1 = (3U << 20) | (1U << 3),
205 CAN_FLAG_FOV1 = (3U << 20) | (1U << 4),
206 CAN_FLAG_WARN = (4U << 20) | (1U << 0),
207 CAN_FLAG_PERR = (4U << 20) | (1U << 1),
208 CAN_FLAG_BOF = (4U << 20) | (1U << 2),
209 } can_flag_t;
CAN_FLAG_SLPS
Definition: ald_can.h:189
CAN_FLAG_ERR
Definition: ald_can.h:190
CAN_FLAG_M2REQC
Definition: ald_can.h:197
CAN_FLAG_M2TXC
Definition: ald_can.h:198
CAN_FLAG_SLP
Definition: ald_can.h:192
CAN_FLAG_FF0
Definition: ald_can.h:202
CAN_FLAG_TXM0
Definition: ald_can.h:199
CAN_FLAG_M0TXC
Definition: ald_can.h:194
CAN_FLAG_WK
Definition: ald_can.h:191
can_flag_t
can_flag_t
CAN Flags.
Definition: ald_can.h:188
CAN_FLAG_BOF
Definition: ald_can.h:208
CAN_FLAG_M1TXC
Definition: ald_can.h:196
CAN_FLAG_M1REQC
Definition: ald_can.h:195
CAN_FLAG_M0REQC
Definition: ald_can.h:193
CAN_FLAG_TXM1
Definition: ald_can.h:200
CAN_FLAG_FOV0
Definition: ald_can.h:203
CAN_FLAG_FF1
Definition: ald_can.h:204
CAN_FLAG_PERR
Definition: ald_can.h:207
CAN_FLAG_TXM2
Definition: ald_can.h:201
CAN_FLAG_WARN
Definition: ald_can.h:206
CAN_FLAG_FOV1
Definition: ald_can.h:205

◆ can_id_type_t

enum can_id_type_t

CAN Identifier Type.

Enumerator
CAN_ID_STD | Standard Id
CAN_ID_EXT | Extended Id

Definition at line 154 of file ald_can.h.

154 {
155 CAN_ID_STD = 0x0U,
156 CAN_ID_EXT = 0x1U,
157 } can_id_type_t;
CAN_ID_STD
Definition: ald_can.h:155
CAN_ID_EXT
Definition: ald_can.h:156
can_id_type_t
can_id_type_t
CAN Identifier Type.
Definition: ald_can.h:154

◆ can_it_t

enum can_it_t

CAN Interrupts.

Enumerator
CAN_IT_TXM | Transmit mailbox empty interrupt bit
CAN_IT_FP0 | FIFO0 message pending interrupt bit
CAN_IT_FF0 | FIFO0 full interrupt bit
CAN_IT_FOV0 | FIFO0 overrun interrupt bit
CAN_IT_FP1 | FIFO1 message pending interrupt bit
CAN_IT_FF1 | FIFO1 full interrupt bit
CAN_IT_FOV1 | FIFO1 overrun interrupt bit
CAN_IT_WARN | Error warning interrupt bit
CAN_IT_PERR | Error passive interrupt bit
CAN_IT_BOF | Bus-off interrupt bit
CAN_IT_PRERR | Last error code interrupt bit
CAN_IT_ERR | Error interrupt bit
CAN_IT_WK | wake-up interrupt bit
CAN_IT_SLP | sleep interrupt bit

Definition at line 214 of file ald_can.h.

214 {
215 CAN_IT_TXM = (1U << 0),
216 CAN_IT_FP0 = (1U << 1),
217 CAN_IT_FF0 = (1U << 2),
218 CAN_IT_FOV0 = (1U << 3),
219 CAN_IT_FP1 = (1U << 4),
220 CAN_IT_FF1 = (1U << 5),
221 CAN_IT_FOV1 = (1U << 6),
222 CAN_IT_WARN = (1U << 8),
223 CAN_IT_PERR = (1U << 9),
224 CAN_IT_BOF = (1U << 10),
225 CAN_IT_PRERR = (1U << 11),
226 CAN_IT_ERR = (1U << 15),
227 CAN_IT_WK = (1U << 16),
228 CAN_IT_SLP = (1U << 17),
229 } can_it_t;
CAN_IT_FP1
Definition: ald_can.h:219
CAN_IT_FF0
Definition: ald_can.h:217
CAN_IT_SLP
Definition: ald_can.h:228
CAN_IT_ERR
Definition: ald_can.h:226
CAN_IT_WK
Definition: ald_can.h:227
CAN_IT_FF1
Definition: ald_can.h:220
CAN_IT_WARN
Definition: ald_can.h:222
can_it_t
can_it_t
CAN Interrupts.
Definition: ald_can.h:214
CAN_IT_TXM
Definition: ald_can.h:215
CAN_IT_PRERR
Definition: ald_can.h:225
CAN_IT_PERR
Definition: ald_can.h:223
CAN_IT_FOV1
Definition: ald_can.h:221
CAN_IT_FOV0
Definition: ald_can.h:218
CAN_IT_BOF
Definition: ald_can.h:224
CAN_IT_FP0
Definition: ald_can.h:216

◆ can_operate_mode_t

enum can_operate_mode_t

CAN Operating Mode.

Enumerator
CAN_MODE_NORMAL | Normal mode
CAN_MODE_LOOPBACK | Loopback mode
CAN_MODE_SILENT | Silent mode
CAN_MODE_SILENT_LOOPBACK | Loopback combined with silent mode

Definition at line 74 of file ald_can.h.

74 {
75 CAN_MODE_NORMAL = 0x00U,
76 CAN_MODE_LOOPBACK = 0x01U,
77 CAN_MODE_SILENT = 0x02U,
78 CAN_MODE_SILENT_LOOPBACK = 0x03U,
79 } can_operate_mode_t;
CAN_MODE_SILENT_LOOPBACK
Definition: ald_can.h:78
CAN_MODE_SILENT
Definition: ald_can.h:77
CAN_MODE_LOOPBACK
Definition: ald_can.h:76
CAN_MODE_NORMAL
Definition: ald_can.h:75
can_operate_mode_t
can_operate_mode_t
CAN Operating Mode.
Definition: ald_can.h:74

◆ can_remote_req_t

enum can_remote_req_t

CAN Remote Transmission Request.

Enumerator
CAN_RTR_DATA | Data frame
CAN_RTR_REMOTE | Remote frame

Definition at line 162 of file ald_can.h.

162 {
163 CAN_RTR_DATA = 0x0U,
164 CAN_RTR_REMOTE = 0x1U,
165 } can_remote_req_t;
CAN_RTR_DATA
Definition: ald_can.h:163
CAN_RTR_REMOTE
Definition: ald_can.h:164
can_remote_req_t
can_remote_req_t
CAN Remote Transmission Request.
Definition: ald_can.h:162

◆ can_rx_fifo_t

enum can_rx_fifo_t

CAN Receive fifo Number.

Enumerator
CAN_RX_FIFO0 | CAN fifo 0 used to receive
CAN_RX_FIFO1 | CAN fifo 1 used to receive

Definition at line 180 of file ald_can.h.

180 {
181 CAN_RX_FIFO0 = 0x0U,
182 CAN_RX_FIFO1 = 0x1U,
183 } can_rx_fifo_t;
CAN_RX_FIFO1
Definition: ald_can.h:182
can_rx_fifo_t
can_rx_fifo_t
CAN Receive fifo Number.
Definition: ald_can.h:180
CAN_RX_FIFO0
Definition: ald_can.h:181

◆ can_seg1_t

enum can_seg1_t

CAN Time Quantum in Bit Segment 1.

Enumerator
CAN_SEG1_1 | 1 time quantum
CAN_SEG1_2 | 2 time quantum
CAN_SEG1_3 | 3 time quantum
CAN_SEG1_4 | 4 time quantum
CAN_SEG1_5 | 5 time quantum
CAN_SEG1_6 | 6 time quantum
CAN_SEG1_7 | 7 time quantum
CAN_SEG1_8 | 8 time quantum
CAN_SEG1_9 | 9 time quantum
CAN_SEG1_10 | 10 time quantum
CAN_SEG1_11 | 11 time quantum
CAN_SEG1_12 | 12 time quantum
CAN_SEG1_13 | 13 time quantum
CAN_SEG1_14 | 14 time quantum
CAN_SEG1_15 | 15 time quantum
CAN_SEG1_16 | 16 time quantum

Definition at line 94 of file ald_can.h.

94 {
95 CAN_SEG1_1 = 0x0U,
96 CAN_SEG1_2 = 0x1U,
97 CAN_SEG1_3 = 0x2U,
98 CAN_SEG1_4 = 0x3U,
99 CAN_SEG1_5 = 0x4U,
100 CAN_SEG1_6 = 0x5U,
101 CAN_SEG1_7 = 0x6U,
102 CAN_SEG1_8 = 0x7U,
103 CAN_SEG1_9 = 0x8U,
104 CAN_SEG1_10 = 0x9U,
105 CAN_SEG1_11 = 0xAU,
106 CAN_SEG1_12 = 0xBU,
107 CAN_SEG1_13 = 0xCU,
108 CAN_SEG1_14 = 0xDU,
109 CAN_SEG1_15 = 0xEU,
110 CAN_SEG1_16 = 0xFU,
111 } can_seg1_t;
CAN_SEG1_16
Definition: ald_can.h:110
CAN_SEG1_8
Definition: ald_can.h:102
CAN_SEG1_11
Definition: ald_can.h:105
CAN_SEG1_13
Definition: ald_can.h:107
can_seg1_t
can_seg1_t
CAN Time Quantum in Bit Segment 1.
Definition: ald_can.h:94
CAN_SEG1_14
Definition: ald_can.h:108
CAN_SEG1_3
Definition: ald_can.h:97
CAN_SEG1_7
Definition: ald_can.h:101
CAN_SEG1_4
Definition: ald_can.h:98
CAN_SEG1_2
Definition: ald_can.h:96
CAN_SEG1_12
Definition: ald_can.h:106
CAN_SEG1_6
Definition: ald_can.h:100
CAN_SEG1_15
Definition: ald_can.h:109
CAN_SEG1_5
Definition: ald_can.h:99
CAN_SEG1_1
Definition: ald_can.h:95
CAN_SEG1_10
Definition: ald_can.h:104
CAN_SEG1_9
Definition: ald_can.h:103

◆ can_seg2_t

enum can_seg2_t

CAN Time Quantum in Bit Segment 2.

Enumerator
CAN_SEG2_1 | 1 time quantum
CAN_SEG2_2 | 2 time quantum
CAN_SEG2_3 | 3 time quantum
CAN_SEG2_4 | 4 time quantum
CAN_SEG2_5 | 5 time quantum
CAN_SEG2_6 | 6 time quantum
CAN_SEG2_7 | 7 time quantum
CAN_SEG2_8 | 8 time quantum

Definition at line 116 of file ald_can.h.

116 {
117 CAN_SEG2_1 = 0x0U,
118 CAN_SEG2_2 = 0x1U,
119 CAN_SEG2_3 = 0x2U,
120 CAN_SEG2_4 = 0x3U,
121 CAN_SEG2_5 = 0x4U,
122 CAN_SEG2_6 = 0x5U,
123 CAN_SEG2_7 = 0x6U,
124 CAN_SEG2_8 = 0x7U,
125 } can_seg2_t;
CAN_SEG2_3
Definition: ald_can.h:119
CAN_SEG2_5
Definition: ald_can.h:121
CAN_SEG2_2
Definition: ald_can.h:118
CAN_SEG2_1
Definition: ald_can.h:117
can_seg2_t
can_seg2_t
CAN Time Quantum in Bit Segment 2.
Definition: ald_can.h:116
CAN_SEG2_4
Definition: ald_can.h:120
CAN_SEG2_6
Definition: ald_can.h:122
CAN_SEG2_7
Definition: ald_can.h:123
CAN_SEG2_8
Definition: ald_can.h:124

◆ can_sjw_t

enum can_sjw_t

CAN Synchronization Jump Width.

Enumerator
CAN_SJW_1 | 1 time quantum
CAN_SJW_2 | 2 time quantum
CAN_SJW_3 | 3 time quantum
CAN_SJW_4 | 4 time quantum

Definition at line 84 of file ald_can.h.

84 {
85 CAN_SJW_1 = 0x0U,
86 CAN_SJW_2 = 0x1U,
87 CAN_SJW_3 = 0x2U,
88 CAN_SJW_4 = 0x3U,
89 } can_sjw_t;
CAN_SJW_3
Definition: ald_can.h:87
CAN_SJW_1
Definition: ald_can.h:85
CAN_SJW_4
Definition: ald_can.h:88
CAN_SJW_2
Definition: ald_can.h:86
can_sjw_t
can_sjw_t
CAN Synchronization Jump Width.
Definition: ald_can.h:84

◆ can_state_t

enum can_state_t

ALD State structures definition.

Enumerator
CAN_STATE_RESET | CAN not yet initialized or disabled
CAN_STATE_READY | CAN initialized and ready for use
CAN_STATE_BUSY | CAN process is ongoing
CAN_STATE_BUSY_TX | CAN process is ongoing
CAN_STATE_BUSY_RX0 | CAN process is ongoing
CAN_STATE_BUSY_RX1 | CAN process is ongoing
CAN_STATE_BUSY_TX_RX0 | CAN process is ongoing
CAN_STATE_BUSY_TX_RX1 | CAN process is ongoing
CAN_STATE_BUSY_RX0_RX1 | CAN process is ongoing
CAN_STATE_BUSY_TX_RX0_RX1 | CAN process is ongoing
CAN_STATE_TIMEOUT | CAN in Timeout state
CAN_STATE_ERROR | CAN error state

Definition at line 39 of file ald_can.h.

39 {
40 CAN_STATE_RESET = 0x00U,
41 CAN_STATE_READY = 0x01U,
42 CAN_STATE_BUSY = 0x02U,
43 CAN_STATE_BUSY_TX = 0x11U,
44 CAN_STATE_BUSY_RX0 = 0x21U,
45 CAN_STATE_BUSY_RX1 = 0x41U,
46 CAN_STATE_BUSY_TX_RX0 = 0x31U,
47 CAN_STATE_BUSY_TX_RX1 = 0x51U,
48 CAN_STATE_BUSY_RX0_RX1 = 0x61U,
49 CAN_STATE_BUSY_TX_RX0_RX1 = 0x71U,
50 CAN_STATE_TIMEOUT = 0x04U,
51 CAN_STATE_ERROR = 0x08U,
52 } can_state_t;
CAN_STATE_BUSY_RX1
Definition: ald_can.h:45
CAN_STATE_BUSY_TX_RX0
Definition: ald_can.h:46
CAN_STATE_ERROR
Definition: ald_can.h:51
CAN_STATE_READY
Definition: ald_can.h:41
CAN_STATE_TIMEOUT
Definition: ald_can.h:50
CAN_STATE_BUSY_TX
Definition: ald_can.h:43
CAN_STATE_BUSY_RX0_RX1
Definition: ald_can.h:48
can_state_t
can_state_t
ALD State structures definition.
Definition: ald_can.h:39
CAN_STATE_BUSY
Definition: ald_can.h:42
CAN_STATE_BUSY_RX0
Definition: ald_can.h:44
CAN_STATE_BUSY_TX_RX0_RX1
Definition: ald_can.h:49
CAN_STATE_BUSY_TX_RX1
Definition: ald_can.h:47
CAN_STATE_RESET
Definition: ald_can.h:40

◆ can_tx_mailbox_t

enum can_tx_mailbox_t

CAN Transmit Constants.

Enumerator
CAN_TX_MAILBOX_0 | TX mailbox index 0
CAN_TX_MAILBOX_1 | TX mailbox index 1
CAN_TX_MAILBOX_2 | TX mailbox index 2
CAN_TX_MAILBOX_NONE | MailBox can't be used

Definition at line 170 of file ald_can.h.

170 {
171 CAN_TX_MAILBOX_0 = 0x0U,
172 CAN_TX_MAILBOX_1 = 0x1U,
173 CAN_TX_MAILBOX_2 = 0x2U,
174 CAN_TX_MAILBOX_NONE = 0x3U,
175 } can_tx_mailbox_t;
can_tx_mailbox_t
can_tx_mailbox_t
CAN Transmit Constants.
Definition: ald_can.h:170
CAN_TX_MAILBOX_NONE
Definition: ald_can.h:174
CAN_TX_MAILBOX_2
Definition: ald_can.h:173
CAN_TX_MAILBOX_1
Definition: ald_can.h:172
CAN_TX_MAILBOX_0
Definition: ald_can.h:171


ALD User Manual: can_filter_t Struct Reference

Data Fields
can_filter_t Struct Reference
EASTSOFT ES32F3xx ALD » CAN » CAN Public Types

CAN filter configuration structure definition. More...

#include <ald_can.h>

Data Fields

uint32_t | id_high
uint32_t | id_low
uint32_t | mask_id_high
uint32_t | mask_id_low
can_filter_fifo_t fifo
uint32_t | number
can_filter_mode_t mode
can_filter_scale_t scale
type_func_t active

Detailed Description

CAN filter configuration structure definition.

Definition at line 234 of file ald_can.h.

Field Documentation

◆ active

type_func_t active

Enable or disable the filter.

Definition at line 243 of file ald_can.h.

◆ fifo

can_filter_fifo_t fifo

Specifies the fifo (0 or 1) which will be assigned to the filter.

Definition at line 239 of file ald_can.h.

◆ id_high

uint32_t id_high

Specifies the filter identification number

Definition at line 235 of file ald_can.h.

◆ id_low

uint32_t id_low

Specifies the filter identification number

Definition at line 236 of file ald_can.h.

◆ mask_id_high

uint32_t mask_id_high

Specifies the filter mask number or identification number

Definition at line 237 of file ald_can.h.

◆ mask_id_low

uint32_t mask_id_low

Specifies the filter mask number or identification number

Definition at line 238 of file ald_can.h.

◆ mode

can_filter_mode_t mode

Specifies the filter mode to be initialized.

Definition at line 241 of file ald_can.h.

◆ number

uint32_t number

Specifies the filter which will be initialized.

Definition at line 240 of file ald_can.h.

◆ scale

can_filter_scale_t scale

Specifies the filter scale.

Definition at line 242 of file ald_can.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_can.h


ALD User Manual: can_init_t Struct Reference

Data Fields
can_init_t Struct Reference
EASTSOFT ES32F3xx ALD » CAN » CAN Public Types

CAN init structure definition. More...

#include <ald_can.h>

Data Fields

uint32_t psc
can_operate_mode_t mode
can_sjw_t sjw
can_seg1_t seg1
can_seg2_t seg2
type_func_t ttcm
type_func_t abom
type_func_t awk
type_func_t artx
type_func_t rfom
type_func_t txmp

Detailed Description

CAN init structure definition.

Definition at line 249 of file ald_can.h.

Field Documentation

◆ abom

type_func_t abom

Enable or disable the automatic bus-off management.

Definition at line 257 of file ald_can.h.

◆ artx

type_func_t artx

Enable or disable the non-automatic retransmission mode.

Definition at line 259 of file ald_can.h.

◆ awk

type_func_t awk

Enable or disable the automatic wake-up mode.

Definition at line 258 of file ald_can.h.

◆ mode

can_operate_mode_t mode

Specifies the CAN operating mode.

Definition at line 251 of file ald_can.h.

◆ psc

uint32_t psc

Specifies the length of a time quantum.

Definition at line 250 of file ald_can.h.

◆ rfom

type_func_t rfom

Enable or disable the Receive fifo Locked mode.

Definition at line 260 of file ald_can.h.

◆ seg1

can_seg1_t seg1

Specifies the number of time quanta in Bit Segment 1.

Definition at line 254 of file ald_can.h.

◆ seg2

can_seg2_t seg2

Specifies the number of time quanta in Bit Segment 2.

Definition at line 255 of file ald_can.h.

◆ sjw

can_sjw_t sjw

Specifies the maximum number of time quanta the CAN hardware is allowed to lengthen or shorten a bit to perform resynchronization.

Definition at line 252 of file ald_can.h.

◆ ttcm

type_func_t ttcm

Enable or disable the time triggered communication mode.

Definition at line 256 of file ald_can.h.

◆ txmp

type_func_t txmp

Enable or disable the transmit fifo priority.

Definition at line 261 of file ald_can.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_can.h


ALD User Manual: can_tx_msg_t Struct Reference

Data Fields
can_tx_msg_t Struct Reference
EASTSOFT ES32F3xx ALD » CAN » CAN Public Types

CAN Tx message structure definition. More...

#include <ald_can.h>

Data Fields

uint32_t | std
uint32_t | ext
can_id_type_t type
can_remote_req_t rtr
uint32_t | len
uint8_t | data [8]

Detailed Description

CAN Tx message structure definition.

Definition at line 267 of file ald_can.h.

Field Documentation

◆ data

uint8_t data[8]

Contains the data to be transmitted.

Definition at line 273 of file ald_can.h.

◆ ext

uint32_t ext

Specifies the extended identifier.

Definition at line 269 of file ald_can.h.

◆ len

uint32_t len

Specifies the length of the frame that will be transmitted.

Definition at line 272 of file ald_can.h.

◆ rtr

can_remote_req_t rtr

Specifies the type of frame for the message that will be transmitted.

Definition at line 271 of file ald_can.h.

◆ std

uint32_t std

Specifies the standard identifier.

Definition at line 268 of file ald_can.h.

◆ type

can_id_type_t type

Specifies the type of identifier for the message that will be transmitted.

Definition at line 270 of file ald_can.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_can.h


ALD User Manual: can_rx_msg_t Struct Reference

Data Fields
can_rx_msg_t Struct Reference
EASTSOFT ES32F3xx ALD » CAN » CAN Public Types

CAN Rx message structure definition. More...

#include <ald_can.h>

Data Fields

uint32_t | std
uint32_t | ext
can_id_type_t type
can_remote_req_t rtr
uint32_t | len
uint8_t | data [8]
uint32_t | fmi
can_rx_fifo_t num

Detailed Description

CAN Rx message structure definition.

Definition at line 279 of file ald_can.h.

Field Documentation

◆ data

uint8_t data[8]

Contains the data to be received.

Definition at line 285 of file ald_can.h.

◆ ext

uint32_t ext

Specifies the extended identifier.

Definition at line 281 of file ald_can.h.

◆ fmi

uint32_t fmi

Specifies the index of the filter the message stored in the mailbox passes through.

Definition at line 286 of file ald_can.h.

◆ len

uint32_t len

Specifies the length of the frame that will be received.

Definition at line 284 of file ald_can.h.

◆ num

can_rx_fifo_t num

Specifies the receive fifo number.

Definition at line 287 of file ald_can.h.

◆ rtr

can_remote_req_t rtr

Specifies the type of frame for the received message.

Definition at line 283 of file ald_can.h.

◆ std

uint32_t std

Specifies the standard identifier.

Definition at line 280 of file ald_can.h.

◆ type

can_id_type_t type

Specifies the type of identifier for the message that will be received.

Definition at line 282 of file ald_can.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_can.h


ALD User Manual: can_handle_s Struct Reference

Data Fields
can_handle_s Struct Reference
EASTSOFT ES32F3xx ALD » CAN » CAN Public Types

CAN handle Structure definition. More...

#include <ald_can.h>

Collaboration diagram for can_handle_s:
[legend]

Data Fields

CAN_TypeDef * | perh
can_init_t init
can_rx_msg_t * rx0_msg
can_rx_msg_t * rx1_msg
lock_state_t lock
can_state_t state
can_error_t err
void(* | tx_cplt_cbk )(struct can_handle_s *arg)
void(* | rx_cplt_cbk )(struct can_handle_s *arg, can_rx_fifo_t num)
void(* | error_cbk )(struct can_handle_s *arg)

Detailed Description

CAN handle Structure definition.

Definition at line 293 of file ald_can.h.

Field Documentation

◆ err

can_error_t err

CAN Error code

Definition at line 300 of file ald_can.h.

◆ error_cbk

void(* error_cbk) (struct can_handle_s *arg)

error callback

Definition at line 304 of file ald_can.h.

◆ init

can_init_t init

CAN required parameters

Definition at line 295 of file ald_can.h.

◆ lock

lock_state_t lock

CAN locking object

Definition at line 298 of file ald_can.h.

◆ perh

CAN_TypeDef* perh

Register base address

Definition at line 294 of file ald_can.h.

◆ rx0_msg

can_rx_msg_t* rx0_msg

Pointer to receive message from FIFO0

Definition at line 296 of file ald_can.h.

◆ rx1_msg

can_rx_msg_t* rx1_msg

Pointer to receive message from FIFO1

Definition at line 297 of file ald_can.h.

◆ rx_cplt_cbk

void(* rx_cplt_cbk) (struct can_handle_s *arg, can_rx_fifo_t num)

Rx completed callback

Definition at line 303 of file ald_can.h.

◆ state

can_state_t state

CAN communication state

Definition at line 299 of file ald_can.h.

◆ tx_cplt_cbk

void(* tx_cplt_cbk) (struct can_handle_s *arg)

Tx completed callback

Definition at line 302 of file ald_can.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_can.h


ALD User Manual: CAN Public Macros

Macros
CAN Public Macros
EASTSOFT ES32F3xx ALD » CAN
Collaboration diagram for CAN Public Macros:

Macros

#define | CAN_RESET_HANDLE_STATE(x) ((x)->state = CAN_STATE_RESET)
#define | CAN_RX_MSG_PENDING(x, y)
#define | CAN_DBG_FREEZE(x, y) (MODIFY_REG((x)->perh->CON, CAN_CON_DBGSTP_MSK, (y) << CAN_CON_DBGSTP_POS))
#define | CAN_TX_STAMP_ENABLE(x, y) (SET_BIT((x)->perh->TxMailBox[(y)].TXFCON, CAN_TXFCON0_TXGT_MSK))
#define | CAN_TX_STAMP_DISABLE(x, y) (CLEAR_BIT((x)->perh->TxMailBox[(y)].TXFCON, CAN_TXFCON0_TXGT_MSK))

Detailed Description

Macro Definition Documentation

◆ CAN_DBG_FREEZE

#define CAN_DBG_FREEZE | ( | x,
 |  | y
 | ) | (MODIFY_REG((x)->perh->CON, CAN_CON_DBGSTP_MSK, (y) << CAN_CON_DBGSTP_POS))

Definition at line 316 of file ald_can.h.

◆ CAN_RESET_HANDLE_STATE

#define CAN_RESET_HANDLE_STATE ( x ) ((x)->state = CAN_STATE_RESET)

Definition at line 313 of file ald_can.h.

◆ CAN_RX_MSG_PENDING

#define CAN_RX_MSG_PENDING | ( | x,
 |  | y
 | ) |
Value:
(((y) == CAN_RX_FIFO0) ? \
(READ_BIT((x)->perh->RXF0, CAN_RXF0_PEND_MSK)) : (READ_BIT((x)->perh->RXF1, CAN_RXF1_PEND_MSK)))
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
CAN_RX_FIFO0
Definition: ald_can.h:181

Definition at line 314 of file ald_can.h.

◆ CAN_TX_STAMP_DISABLE

#define CAN_TX_STAMP_DISABLE | ( | x,
 |  | y
 | ) | (CLEAR_BIT((x)->perh->TxMailBox[(y)].TXFCON, CAN_TXFCON0_TXGT_MSK))

Definition at line 318 of file ald_can.h.

◆ CAN_TX_STAMP_ENABLE

#define CAN_TX_STAMP_ENABLE | ( | x,
 |  | y
 | ) | (SET_BIT((x)->perh->TxMailBox[(y)].TXFCON, CAN_TXFCON0_TXGT_MSK))

Definition at line 317 of file ald_can.h.


ALD User Manual: CAN Private Macros

Macros
CAN Private Macros
EASTSOFT ES32F3xx ALD » CAN EASTSOFT ES32F3xx ALD » | RTC
Collaboration diagram for CAN Private Macros:

Macros

#define | IS_CAN_ALL(x) ((x) == CAN0)
#define | IS_CAN_FILTER_NUMBER(x) ((x) <= 13)
#define | IS_CAN_MODE(x)
#define | IS_CAN_SJW(x)
#define | IS_CAN_BS1(x) ((x) <= CAN_SEG1_16)
#define | IS_CAN_BS2(x) ((x) <= CAN_SEG2_8)
#define | IS_CAN_FILTER_MODE(x)
#define | IS_CAN_FILTER_SCALE(x)
#define | IS_CAN_FILTER_FIFO(x)
#define | IS_CAN_IDTYPE(x)
#define | IS_CAN_RTR(x) (((x) == CAN_RTR_DATA) || ((x) == CAN_RTR_REMOTE))
#define | IS_CAN_FIFO(x) (((x) == CAN_RX_FIFO0) || ((x) == CAN_RX_FIFO1))
#define | IS_CAN_TX_MAILBOX(x) ((x) <= CAN_TX_MAILBOX_NONE)
#define | IS_CAN_STDID(x) ((x) <= ((uint32_t)0x7FF))
#define | IS_CAN_EXTID(x) ((x) <= ((uint32_t)0x1FFFFFFF))
#define | IS_CAN_DATA_LEN(x) ((x) <= ((uint8_t)0x08))
#define | IS_CAN_PRESCALER(x) (((x) >= 1) && ((x) <= 1024))
#define | IS_CAN_GET_FLAG(x)
#define | IS_CAN_CLEAR_FLAG(x)
#define | IS_CAN_IT(x)
#define | CAN_TIMEOUT_VALUE 100
#define | CAN_STATE_TX_MASK (1U << 4)
#define | CAN_STATE_RX0_MASK (1U << 5)
#define | CAN_STATE_RX1_MASK (1U << 6)
#define | RTC_CALI_UNLOCK() (WRITE_REG(RTC->CALWPR, 0x699655AAU))
#define | RTC_CALI_LOCK() (WRITE_REG(RTC->CALWPR, 0x0U))
#define | ALARM_MASK_ALL 0x40808080
#define | RTC_TIMEOUT_VALUE 100
#define | IS_SHIFT_SUB_SS(x) ((x) < (1U << 15))
#define | IS_RTC_HOUR_FORMAT(x)
#define | IS_RTC_OUTPUT_SEL(x)
#define | IS_RTC_OUTPUT_POLARITY(x)
#define | IS_RTC_SOURCE_SEL(x)
#define | IS_RTC_ALARM(x)
#define | IS_RTC_ALARM_SEL(x)
#define | IS_RTC_ALARM_MASK(x)
#define | IS_RTC_ALARM_SS_MASK(x)
#define | IS_RTC_TS_SIGNAL(x)
#define | IS_RTC_TS_STYLE(x)
#define | IS_RTC_FORMAT(x)
#define | IS_RTC_TAMPER(x)
#define | IS_RTC_TAMPER_TRIGGER(x)
#define | IS_RTC_TAMPER_SAMPLING_FREQ(x)
#define | IS_RTC_TAMPER_DURATION(x)
#define | IS_RTC_WAKEUP_CLOCK(x)
#define | IS_RTC_CLOCK_OUTPUT(x)
#define | IS_RTC_CALI_FREQ(x)
#define | IS_RTC_CALI_TC(x)
#define | IS_RTC_CALC_FREQ(x)
#define | IS_RTC_CALI_CALC(x)
#define | IS_RTC_IT(x)
#define | IS_RTC_IF(x)
#define | IS_RTC_SECOND(x) ((x) < 60)
#define | IS_RTC_MINUTE(x) ((x) < 60)
#define | IS_RTC_HOUR(x) ((x) < 24)
#define | IS_RTC_DAY(x) (((x) > 0) && ((x) < 32))
#define | IS_RTC_MONTH(x) (((x) > 0) && ((x) < 13))
#define | IS_RTC_YEAR(x) ((x) < 100)

Detailed Description

Macro Definition Documentation

◆ ALARM_MASK_ALL

#define ALARM_MASK_ALL 0x40808080

Definition at line 425 of file ald_rtc.h.

◆ CAN_STATE_RX0_MASK

#define CAN_STATE_RX0_MASK (1U << 5)

Definition at line 399 of file ald_can.h.

◆ CAN_STATE_RX1_MASK

#define CAN_STATE_RX1_MASK (1U << 6)

Definition at line 400 of file ald_can.h.

◆ CAN_STATE_TX_MASK

#define CAN_STATE_TX_MASK (1U << 4)

Definition at line 398 of file ald_can.h.

◆ CAN_TIMEOUT_VALUE

#define CAN_TIMEOUT_VALUE 100

Definition at line 397 of file ald_can.h.

◆ IS_CAN_ALL

#define IS_CAN_ALL ( x ) ((x) == CAN0)

Definition at line 326 of file ald_can.h.

◆ IS_CAN_BS1

#define IS_CAN_BS1 ( x ) ((x) <= CAN_SEG1_16)

Definition at line 336 of file ald_can.h.

◆ IS_CAN_BS2

#define IS_CAN_BS2 ( x ) ((x) <= CAN_SEG2_8)

Definition at line 337 of file ald_can.h.

◆ IS_CAN_CLEAR_FLAG

#define IS_CAN_CLEAR_FLAG ( x )
Value:
(((x) == CAN_FLAG_ERR) || \
((x) == CAN_FLAG_WK) || \
((x) == CAN_FLAG_SLP) || \
((x) == CAN_FLAG_M0REQC) || \
((x) == CAN_FLAG_M1REQC) || \
((x) == CAN_FLAG_M2REQC) || \
((x) == CAN_FLAG_FF0) || \
((x) == CAN_FLAG_FOV0) || \
((x) == CAN_FLAG_FF1) || \
((x) == CAN_FLAG_FOV1))
CAN_FLAG_ERR
Definition: ald_can.h:190
CAN_FLAG_M2REQC
Definition: ald_can.h:197
CAN_FLAG_SLP
Definition: ald_can.h:192
CAN_FLAG_FF0
Definition: ald_can.h:202
CAN_FLAG_WK
Definition: ald_can.h:191
CAN_FLAG_M1REQC
Definition: ald_can.h:195
CAN_FLAG_M0REQC
Definition: ald_can.h:193
CAN_FLAG_FOV0
Definition: ald_can.h:203
CAN_FLAG_FF1
Definition: ald_can.h:204
CAN_FLAG_FOV1
Definition: ald_can.h:205

Definition at line 373 of file ald_can.h.

◆ IS_CAN_DATA_LEN

#define IS_CAN_DATA_LEN ( x ) ((x) <= ((uint8_t)0x08))

Definition at line 351 of file ald_can.h.

◆ IS_CAN_EXTID

#define IS_CAN_EXTID ( x ) ((x) <= ((uint32_t)0x1FFFFFFF))

Definition at line 350 of file ald_can.h.

◆ IS_CAN_FIFO

#define IS_CAN_FIFO ( x ) (((x) == CAN_RX_FIFO0) || ((x) == CAN_RX_FIFO1))

Definition at line 347 of file ald_can.h.

◆ IS_CAN_FILTER_FIFO

#define IS_CAN_FILTER_FIFO ( x )
Value:
(((x) == CAN_FILTER_FIFO0) || \
((x) == CAN_FILTER_FIFO1))
CAN_FILTER_FIFO0
Definition: ald_can.h:147
CAN_FILTER_FIFO1
Definition: ald_can.h:148

Definition at line 342 of file ald_can.h.

◆ IS_CAN_FILTER_MODE

#define IS_CAN_FILTER_MODE ( x )
Value:
(((x) == CAN_FILTER_MODE_MASK) || \
((x) == CAN_FILTER_MODE_LIST))
CAN_FILTER_MODE_MASK
Definition: ald_can.h:131
CAN_FILTER_MODE_LIST
Definition: ald_can.h:132

Definition at line 338 of file ald_can.h.

◆ IS_CAN_FILTER_NUMBER

#define IS_CAN_FILTER_NUMBER ( x ) ((x) <= 13)

Definition at line 327 of file ald_can.h.

◆ IS_CAN_FILTER_SCALE

#define IS_CAN_FILTER_SCALE ( x )
Value:
(((x) == CAN_FILTER_SCALE_16) || \
((x) == CAN_FILTER_SCALE_32))
CAN_FILTER_SCALE_16
Definition: ald_can.h:139
CAN_FILTER_SCALE_32
Definition: ald_can.h:140

Definition at line 340 of file ald_can.h.

◆ IS_CAN_GET_FLAG

#define IS_CAN_GET_FLAG ( x )
Value:
(((x) == CAN_FLAG_SLPS) || \
((x) == CAN_FLAG_ERR) || \
((x) == CAN_FLAG_WK) || \
((x) == CAN_FLAG_SLP) || \
((x) == CAN_FLAG_M0REQC) || \
((x) == CAN_FLAG_M0TXC) || \
((x) == CAN_FLAG_M1REQC) || \
((x) == CAN_FLAG_M1TXC) || \
((x) == CAN_FLAG_M2REQC) || \
((x) == CAN_FLAG_M2TXC) || \
((x) == CAN_FLAG_TXM0) || \
((x) == CAN_FLAG_TXM1) || \
((x) == CAN_FLAG_TXM2) || \
((x) == CAN_FLAG_FF0) || \
((x) == CAN_FLAG_FOV0) || \
((x) == CAN_FLAG_FF1) || \
((x) == CAN_FLAG_FOV1) || \
((x) == CAN_FLAG_WARN) || \
((x) == CAN_FLAG_PERR) || \
((x) == CAN_FLAG_BOF))
CAN_FLAG_SLPS
Definition: ald_can.h:189
CAN_FLAG_ERR
Definition: ald_can.h:190
CAN_FLAG_M2REQC
Definition: ald_can.h:197
CAN_FLAG_M2TXC
Definition: ald_can.h:198
CAN_FLAG_SLP
Definition: ald_can.h:192
CAN_FLAG_FF0
Definition: ald_can.h:202
CAN_FLAG_TXM0
Definition: ald_can.h:199
CAN_FLAG_M0TXC
Definition: ald_can.h:194
CAN_FLAG_WK
Definition: ald_can.h:191
CAN_FLAG_BOF
Definition: ald_can.h:208
CAN_FLAG_M1TXC
Definition: ald_can.h:196
CAN_FLAG_M1REQC
Definition: ald_can.h:195
CAN_FLAG_M0REQC
Definition: ald_can.h:193
CAN_FLAG_TXM1
Definition: ald_can.h:200
CAN_FLAG_FOV0
Definition: ald_can.h:203
CAN_FLAG_FF1
Definition: ald_can.h:204
CAN_FLAG_PERR
Definition: ald_can.h:207
CAN_FLAG_TXM2
Definition: ald_can.h:201
CAN_FLAG_WARN
Definition: ald_can.h:206
CAN_FLAG_FOV1
Definition: ald_can.h:205

Definition at line 353 of file ald_can.h.

◆ IS_CAN_IDTYPE

#define IS_CAN_IDTYPE ( x )
Value:
(((x) == CAN_ID_STD) || \
((x) == CAN_ID_EXT))
CAN_ID_STD
Definition: ald_can.h:155
CAN_ID_EXT
Definition: ald_can.h:156

Definition at line 344 of file ald_can.h.

◆ IS_CAN_IT

#define IS_CAN_IT ( x )
Value:
(((x) == CAN_IT_TXM) || \
((x) == CAN_IT_FP0) || \
((x) == CAN_IT_FF0) || \
((x) == CAN_IT_FOV0) || \
((x) == CAN_IT_FP1) || \
((x) == CAN_IT_FF1) || \
((x) == CAN_IT_FOV1) || \
((x) == CAN_IT_WARN) || \
((x) == CAN_IT_PERR) || \
((x) == CAN_IT_BOF) || \
((x) == CAN_IT_PRERR) || \
((x) == CAN_IT_ERR) || \
((x) == CAN_IT_WK) || \
((x) == CAN_IT_SLP))
CAN_IT_FP1
Definition: ald_can.h:219
CAN_IT_FF0
Definition: ald_can.h:217
CAN_IT_SLP
Definition: ald_can.h:228
CAN_IT_ERR
Definition: ald_can.h:226
CAN_IT_WK
Definition: ald_can.h:227
CAN_IT_FF1
Definition: ald_can.h:220
CAN_IT_WARN
Definition: ald_can.h:222
CAN_IT_TXM
Definition: ald_can.h:215
CAN_IT_PRERR
Definition: ald_can.h:225
CAN_IT_PERR
Definition: ald_can.h:223
CAN_IT_FOV1
Definition: ald_can.h:221
CAN_IT_FOV0
Definition: ald_can.h:218
CAN_IT_BOF
Definition: ald_can.h:224
CAN_IT_FP0
Definition: ald_can.h:216

Definition at line 383 of file ald_can.h.

◆ IS_CAN_MODE

#define IS_CAN_MODE ( x )
Value:
(((x) == CAN_MODE_NORMAL) || \
((x) == CAN_MODE_LOOPBACK) || \
((x) == CAN_MODE_SILENT) || \
((x) == CAN_MODE_SILENT_LOOPBACK))
CAN_MODE_SILENT_LOOPBACK
Definition: ald_can.h:78
CAN_MODE_SILENT
Definition: ald_can.h:77
CAN_MODE_LOOPBACK
Definition: ald_can.h:76
CAN_MODE_NORMAL
Definition: ald_can.h:75

Definition at line 328 of file ald_can.h.

◆ IS_CAN_PRESCALER

#define IS_CAN_PRESCALER ( x ) (((x) >= 1) && ((x) <= 1024))

Definition at line 352 of file ald_can.h.

◆ IS_CAN_RTR

#define IS_CAN_RTR ( x ) (((x) == CAN_RTR_DATA) || ((x) == CAN_RTR_REMOTE))

Definition at line 346 of file ald_can.h.

◆ IS_CAN_SJW

#define IS_CAN_SJW ( x )
Value:
(((x) == CAN_SJW_1) || \
((x) == CAN_SJW_2) || \
((x) == CAN_SJW_3) || \
((x) == CAN_SJW_4))
CAN_SJW_3
Definition: ald_can.h:87
CAN_SJW_1
Definition: ald_can.h:85
CAN_SJW_4
Definition: ald_can.h:88
CAN_SJW_2
Definition: ald_can.h:86

Definition at line 332 of file ald_can.h.

◆ IS_CAN_STDID

#define IS_CAN_STDID ( x ) ((x) <= ((uint32_t)0x7FF))

Definition at line 349 of file ald_can.h.

◆ IS_CAN_TX_MAILBOX

#define IS_CAN_TX_MAILBOX ( x ) ((x) <= CAN_TX_MAILBOX_NONE)

Definition at line 348 of file ald_can.h.

◆ IS_RTC_ALARM

#define IS_RTC_ALARM ( x )
Value:
(((x) == RTC_ALARM_A) || \
((x) == RTC_ALARM_B))
RTC_ALARM_B
Definition: ald_rtc.h:118
RTC_ALARM_A
Definition: ald_rtc.h:117

Definition at line 441 of file ald_rtc.h.

◆ IS_RTC_ALARM_MASK

#define IS_RTC_ALARM_MASK ( x )
Value:
(((x) == RTC_ALARM_MASK_NONE) || \
((x) == RTC_ALARM_MASK_WEEK_DAY) || \
((x) == RTC_ALARM_MASK_HOUR) || \
((x) == RTC_ALARM_MASK_MINUTE) || \
((x) == RTC_ALARM_MASK_SECOND) || \
((x) == RTC_ALARM_MASK_ALL))
RTC_ALARM_MASK_ALL
Definition: ald_rtc.h:130
RTC_ALARM_MASK_WEEK_DAY
Definition: ald_rtc.h:126
RTC_ALARM_MASK_MINUTE
Definition: ald_rtc.h:128
RTC_ALARM_MASK_HOUR
Definition: ald_rtc.h:127
RTC_ALARM_MASK_NONE
Definition: ald_rtc.h:125
RTC_ALARM_MASK_SECOND
Definition: ald_rtc.h:129

Definition at line 445 of file ald_rtc.h.

◆ IS_RTC_ALARM_SEL

#define IS_RTC_ALARM_SEL ( x )
Value:
(((x) == RTC_SELECT_DAY) || \
((x) == RTC_SELECT_WEEK))
RTC_SELECT_WEEK
Definition: ald_rtc.h:159
RTC_SELECT_DAY
Definition: ald_rtc.h:158

Definition at line 443 of file ald_rtc.h.

◆ IS_RTC_ALARM_SS_MASK

#define IS_RTC_ALARM_SS_MASK ( x )
Value:
(((x) == RTC_ALARM_SS_MASK_NONE) || \
((x) == RTC_ALARM_SS_MASK_14_1) || \
((x) == RTC_ALARM_SS_MASK_14_2) || \
((x) == RTC_ALARM_SS_MASK_14_3) || \
((x) == RTC_ALARM_SS_MASK_14_4) || \
((x) == RTC_ALARM_SS_MASK_14_5) || \
((x) == RTC_ALARM_SS_MASK_14_6) || \
((x) == RTC_ALARM_SS_MASK_14_7) || \
((x) == RTC_ALARM_SS_MASK_14_8) || \
((x) == RTC_ALARM_SS_MASK_14_9) || \
((x) == RTC_ALARM_SS_MASK_14_10) || \
((x) == RTC_ALARM_SS_MASK_14_11) || \
((x) == RTC_ALARM_SS_MASK_14_12) || \
((x) == RTC_ALARM_SS_MASK_14_13) || \
((x) == RTC_ALARM_SS_MASK_14) || \
((x) == RTC_ALARM_SS_MASK_ALL))
RTC_ALARM_SS_MASK_14_1
Definition: ald_rtc.h:138
RTC_ALARM_SS_MASK_14_11
Definition: ald_rtc.h:148
RTC_ALARM_SS_MASK_14_8
Definition: ald_rtc.h:145
RTC_ALARM_SS_MASK_14_13
Definition: ald_rtc.h:150
RTC_ALARM_SS_MASK_14_9
Definition: ald_rtc.h:146
RTC_ALARM_SS_MASK_14_3
Definition: ald_rtc.h:140
RTC_ALARM_SS_MASK_14_2
Definition: ald_rtc.h:139
RTC_ALARM_SS_MASK_14
Definition: ald_rtc.h:151
RTC_ALARM_SS_MASK_14_10
Definition: ald_rtc.h:147
RTC_ALARM_SS_MASK_14_6
Definition: ald_rtc.h:143
RTC_ALARM_SS_MASK_14_7
Definition: ald_rtc.h:144
RTC_ALARM_SS_MASK_14_4
Definition: ald_rtc.h:141
RTC_ALARM_SS_MASK_ALL
Definition: ald_rtc.h:152
RTC_ALARM_SS_MASK_14_5
Definition: ald_rtc.h:142
RTC_ALARM_SS_MASK_14_12
Definition: ald_rtc.h:149
RTC_ALARM_SS_MASK_NONE
Definition: ald_rtc.h:137

Definition at line 451 of file ald_rtc.h.

◆ IS_RTC_CALC_FREQ

#define IS_RTC_CALC_FREQ ( x )
Value:
(((x) == RTC_CALI_CALC_FREQ_10_SEC) || \
((x) == RTC_CALI_CALC_FREQ_20_SEC) || \
((x) == RTC_CALI_CALC_FREQ_1_MIN) || \
((x) == RTC_CALI_CALC_FREQ_2_MIN) || \
((x) == RTC_CALI_CALC_FREQ_5_MIN) || \
((x) == RTC_CALI_CALC_FREQ_10_MIN) || \
((x) == RTC_CALI_CALC_FREQ_20_MIN) || \
((x) == RTC_CALI_CALC_FREQ_1_HOUR))
RTC_CALI_CALC_FREQ_1_MIN
Definition: ald_rtc.h:299
RTC_CALI_CALC_FREQ_20_MIN
Definition: ald_rtc.h:303
RTC_CALI_CALC_FREQ_20_SEC
Definition: ald_rtc.h:298
RTC_CALI_CALC_FREQ_10_MIN
Definition: ald_rtc.h:302
RTC_CALI_CALC_FREQ_5_MIN
Definition: ald_rtc.h:301
RTC_CALI_CALC_FREQ_10_SEC
Definition: ald_rtc.h:297
RTC_CALI_CALC_FREQ_1_HOUR
Definition: ald_rtc.h:304
RTC_CALI_CALC_FREQ_2_MIN
Definition: ald_rtc.h:300

Definition at line 513 of file ald_rtc.h.

◆ IS_RTC_CALI_CALC

#define IS_RTC_CALI_CALC ( x )
Value:
(((x) == RTC_CALI_CALC_4) || \
((x) == RTC_CALI_CALC_2))
RTC_CALI_CALC_4
Definition: ald_rtc.h:311
RTC_CALI_CALC_2
Definition: ald_rtc.h:312

Definition at line 521 of file ald_rtc.h.

◆ IS_RTC_CALI_FREQ

#define IS_RTC_CALI_FREQ ( x )
Value:
(((x) == RTC_CALI_FREQ_10_SEC) || \
((x) == RTC_CALI_FREQ_20_SEC) || \
((x) == RTC_CALI_FREQ_1_MIN) || \
((x) == RTC_CALI_FREQ_2_MIN) || \
((x) == RTC_CALI_FREQ_5_MIN) || \
((x) == RTC_CALI_FREQ_10_MIN) || \
((x) == RTC_CALI_FREQ_20_MIN) || \
((x) == RTC_CALI_FREQ_1_SEC))
RTC_CALI_FREQ_20_MIN
Definition: ald_rtc.h:279
RTC_CALI_FREQ_1_SEC
Definition: ald_rtc.h:280
RTC_CALI_FREQ_2_MIN
Definition: ald_rtc.h:276
RTC_CALI_FREQ_5_MIN
Definition: ald_rtc.h:277
RTC_CALI_FREQ_10_SEC
Definition: ald_rtc.h:273
RTC_CALI_FREQ_1_MIN
Definition: ald_rtc.h:275
RTC_CALI_FREQ_20_SEC
Definition: ald_rtc.h:274
RTC_CALI_FREQ_10_MIN
Definition: ald_rtc.h:278

Definition at line 501 of file ald_rtc.h.

◆ IS_RTC_CALI_TC

#define IS_RTC_CALI_TC ( x )
Value:
(((x) == RTC_CALI_TC_NONE) || \
((x) == RTC_CALI_TC_AUTO_BY_HW) || \
((x) == RTC_CALI_TC_AUTO_BY_SF) || \
((x) == RTC_CALI_TC_AUTO_BY_HW_SF))
RTC_CALI_TC_AUTO_BY_SF
Definition: ald_rtc.h:289
RTC_CALI_TC_NONE
Definition: ald_rtc.h:287
RTC_CALI_TC_AUTO_BY_HW_SF
Definition: ald_rtc.h:290
RTC_CALI_TC_AUTO_BY_HW
Definition: ald_rtc.h:288

Definition at line 509 of file ald_rtc.h.

◆ IS_RTC_CLOCK_OUTPUT

#define IS_RTC_CLOCK_OUTPUT ( x )
Value:
(((x) == RTC_CLOCK_OUTPUT_32768) || \
((x) == RTC_CLOCK_OUTPUT_1024) || \
((x) == RTC_CLOCK_OUTPUT_32) || \
((x) == RTC_CLOCK_OUTPUT_1) || \
((x) == RTC_CLOCK_OUTPUT_CAL_1) || \
((x) == RTC_CLOCK_OUTPUT_EXA_1))
RTC_CLOCK_OUTPUT_EXA_1
Definition: ald_rtc.h:266
RTC_CLOCK_OUTPUT_1
Definition: ald_rtc.h:264
RTC_CLOCK_OUTPUT_CAL_1
Definition: ald_rtc.h:265
RTC_CLOCK_OUTPUT_1024
Definition: ald_rtc.h:262
RTC_CLOCK_OUTPUT_32
Definition: ald_rtc.h:263
RTC_CLOCK_OUTPUT_32768
Definition: ald_rtc.h:261

Definition at line 495 of file ald_rtc.h.

◆ IS_RTC_DAY

#define IS_RTC_DAY ( x ) (((x) > 0) && ((x) < 32))

Definition at line 560 of file ald_rtc.h.

◆ IS_RTC_FORMAT

#define IS_RTC_FORMAT ( x )
Value:
(((x) == RTC_FORMAT_DEC) || \
((x) == RTC_FORMAT_BCD))
RTC_FORMAT_DEC
Definition: ald_rtc.h:109
RTC_FORMAT_BCD
Definition: ald_rtc.h:110

Definition at line 471 of file ald_rtc.h.

◆ IS_RTC_HOUR

#define IS_RTC_HOUR ( x ) ((x) < 24)

Definition at line 559 of file ald_rtc.h.

◆ IS_RTC_HOUR_FORMAT

#define IS_RTC_HOUR_FORMAT ( x )
Value:
(((x) == RTC_HOUR_FORMAT_24) || \
((x) == RTC_HOUR_FORMAT_12))
RTC_HOUR_FORMAT_12
Definition: ald_rtc.h:43
RTC_HOUR_FORMAT_24
Definition: ald_rtc.h:42

Definition at line 429 of file ald_rtc.h.

◆ IS_RTC_IF

#define IS_RTC_IF ( x )
Value:
(((x) == RTC_IF_SEC) || \
((x) == RTC_IF_MIN) || \
((x) == RTC_IF_HR) || \
((x) == RTC_IF_DAY) || \
((x) == RTC_IF_MON) || \
((x) == RTC_IF_YR) || \
((x) == RTC_IF_ALMA) || \
((x) == RTC_IF_ALMB) || \
((x) == RTC_IF_TS) || \
((x) == RTC_IF_TSOV) || \
((x) == RTC_IF_TP0) || \
((x) == RTC_IF_TP1) || \
((x) == RTC_IF_RSC) || \
((x) == RTC_IF_SFC) || \
((x) == RTC_IF_WU) || \
((x) == RTC_IF_TCC) || \
((x) == RTC_IF_TCE))
RTC_IF_ALMA
Definition: ald_rtc.h:359
RTC_IF_TSOV
Definition: ald_rtc.h:362
RTC_IF_YR
Definition: ald_rtc.h:358
RTC_IF_SEC
Definition: ald_rtc.h:353
RTC_IF_TP0
Definition: ald_rtc.h:363
RTC_IF_HR
Definition: ald_rtc.h:355
RTC_IF_TS
Definition: ald_rtc.h:361
RTC_IF_DAY
Definition: ald_rtc.h:356
RTC_IF_TCE
Definition: ald_rtc.h:369
RTC_IF_MON
Definition: ald_rtc.h:357
RTC_IF_RSC
Definition: ald_rtc.h:365
RTC_IF_MIN
Definition: ald_rtc.h:354
RTC_IF_WU
Definition: ald_rtc.h:367
RTC_IF_ALMB
Definition: ald_rtc.h:360
RTC_IF_TCC
Definition: ald_rtc.h:368
RTC_IF_SFC
Definition: ald_rtc.h:366
RTC_IF_TP1
Definition: ald_rtc.h:364

Definition at line 540 of file ald_rtc.h.

◆ IS_RTC_IT

#define IS_RTC_IT ( x )
Value:
(((x) == RTC_IT_SEC) || \
((x) == RTC_IT_MIN) || \
((x) == RTC_IT_HR) || \
((x) == RTC_IT_DAY) || \
((x) == RTC_IT_MON) || \
((x) == RTC_IT_YR) || \
((x) == RTC_IT_ALMA) || \
((x) == RTC_IT_ALMB) || \
((x) == RTC_IT_TS) || \
((x) == RTC_IT_TSOV) || \
((x) == RTC_IT_TP0) || \
((x) == RTC_IT_TP1) || \
((x) == RTC_IT_RSC) || \
((x) == RTC_IT_SFC) || \
((x) == RTC_IT_WU) || \
((x) == RTC_IT_TCC) || \
((x) == RTC_IT_TCE))
RTC_IT_WU
Definition: ald_rtc.h:344
RTC_IT_TCC
Definition: ald_rtc.h:345
RTC_IT_TP1
Definition: ald_rtc.h:341
RTC_IT_TCE
Definition: ald_rtc.h:346
RTC_IT_TSOV
Definition: ald_rtc.h:339
RTC_IT_MON
Definition: ald_rtc.h:334
RTC_IT_MIN
Definition: ald_rtc.h:331
RTC_IT_TP0
Definition: ald_rtc.h:340
RTC_IT_YR
Definition: ald_rtc.h:335
RTC_IT_DAY
Definition: ald_rtc.h:333
RTC_IT_SFC
Definition: ald_rtc.h:343
RTC_IT_HR
Definition: ald_rtc.h:332
RTC_IT_TS
Definition: ald_rtc.h:338
RTC_IT_SEC
Definition: ald_rtc.h:330
RTC_IT_RSC
Definition: ald_rtc.h:342
RTC_IT_ALMA
Definition: ald_rtc.h:336
RTC_IT_ALMB
Definition: ald_rtc.h:337

Definition at line 523 of file ald_rtc.h.

◆ IS_RTC_MINUTE

#define IS_RTC_MINUTE ( x ) ((x) < 60)

Definition at line 558 of file ald_rtc.h.

◆ IS_RTC_MONTH

#define IS_RTC_MONTH ( x ) (((x) > 0) && ((x) < 13))

Definition at line 561 of file ald_rtc.h.

◆ IS_RTC_OUTPUT_POLARITY

#define IS_RTC_OUTPUT_POLARITY ( x )
Value:
(((x) == RTC_OUTPUT_POLARITY_HIGH) || \
((x) == RTC_OUTPUT_POLARITY_LOW))
RTC_OUTPUT_POLARITY_LOW
Definition: ald_rtc.h:61
RTC_OUTPUT_POLARITY_HIGH
Definition: ald_rtc.h:60

Definition at line 435 of file ald_rtc.h.

◆ IS_RTC_OUTPUT_SEL

#define IS_RTC_OUTPUT_SEL ( x )
Value:
(((x) == RTC_OUTPUT_DISABLE) || \
((x) == RTC_OUTPUT_ALARM_A) || \
((x) == RTC_OUTPUT_ALARM_B) || \
((x) == RTC_OUTPUT_WAKEUP))
RTC_OUTPUT_DISABLE
Definition: ald_rtc.h:50
RTC_OUTPUT_WAKEUP
Definition: ald_rtc.h:53
RTC_OUTPUT_ALARM_B
Definition: ald_rtc.h:52
RTC_OUTPUT_ALARM_A
Definition: ald_rtc.h:51

Definition at line 431 of file ald_rtc.h.

◆ IS_RTC_SECOND

#define IS_RTC_SECOND ( x ) ((x) < 60)

Definition at line 557 of file ald_rtc.h.

◆ IS_RTC_SOURCE_SEL

#define IS_RTC_SOURCE_SEL ( x )
Value:
(((x) == RTC_SOURCE_LOSC) || \
((x) == RTC_SOURCE_LRC) || \
((x) == RTC_SOURCE_HRC_DIV_1M ) || \
((x) == RTC_SOURCE_HOSC_DIV_1M))
RTC_SOURCE_HRC_DIV_1M
Definition: ald_rtc.h:81
RTC_SOURCE_LRC
Definition: ald_rtc.h:80
RTC_SOURCE_LOSC
Definition: ald_rtc.h:79
RTC_SOURCE_HOSC_DIV_1M
Definition: ald_rtc.h:82

Definition at line 437 of file ald_rtc.h.

◆ IS_RTC_TAMPER

#define IS_RTC_TAMPER ( x )
Value:
(((x) == RTC_TAMPER_0) || \
((x) == RTC_TAMPER_1))
RTC_TAMPER_0
Definition: ald_rtc.h:198
RTC_TAMPER_1
Definition: ald_rtc.h:199

Definition at line 473 of file ald_rtc.h.

◆ IS_RTC_TAMPER_DURATION

#define IS_RTC_TAMPER_DURATION ( x )
Value:
(((x) == RTC_TAMPER_DURATION_1) || \
((x) == RTC_TAMPER_DURATION_2) || \
((x) == RTC_TAMPER_DURATION_4) || \
((x) == RTC_TAMPER_DURATION_8))
RTC_TAMPER_DURATION_4
Definition: ald_rtc.h:230
RTC_TAMPER_DURATION_2
Definition: ald_rtc.h:229
RTC_TAMPER_DURATION_1
Definition: ald_rtc.h:228
RTC_TAMPER_DURATION_8
Definition: ald_rtc.h:231

Definition at line 485 of file ald_rtc.h.

◆ IS_RTC_TAMPER_SAMPLING_FREQ

#define IS_RTC_TAMPER_SAMPLING_FREQ ( x )
Value:
(((x) == RTC_TAMPER_SAMPLING_FREQ_32768) || \
((x) == RTC_TAMPER_SAMPLING_FREQ_16384) || \
((x) == RTC_TAMPER_SAMPLING_FREQ_8192) || \
((x) == RTC_TAMPER_SAMPLING_FREQ_4096) || \
((x) == RTC_TAMPER_SAMPLING_FREQ_2048) || \
((x) == RTC_TAMPER_SAMPLING_FREQ_1024) || \
((x) == RTC_TAMPER_SAMPLING_FREQ_512) || \
((x) == RTC_TAMPER_SAMPLING_FREQ_256))
RTC_TAMPER_SAMPLING_FREQ_512
Definition: ald_rtc.h:220
RTC_TAMPER_SAMPLING_FREQ_256
Definition: ald_rtc.h:221
RTC_TAMPER_SAMPLING_FREQ_4096
Definition: ald_rtc.h:217
RTC_TAMPER_SAMPLING_FREQ_32768
Definition: ald_rtc.h:214
RTC_TAMPER_SAMPLING_FREQ_8192
Definition: ald_rtc.h:216
RTC_TAMPER_SAMPLING_FREQ_16384
Definition: ald_rtc.h:215
RTC_TAMPER_SAMPLING_FREQ_2048
Definition: ald_rtc.h:218
RTC_TAMPER_SAMPLING_FREQ_1024
Definition: ald_rtc.h:219

Definition at line 477 of file ald_rtc.h.

◆ IS_RTC_TAMPER_TRIGGER

#define IS_RTC_TAMPER_TRIGGER ( x )
Value:
(((x) == RTC_TAMPER_TRIGGER_LOW) || \
((x) == RTC_TAMPER_TRIGGER_HIGH))
RTC_TAMPER_TRIGGER_LOW
Definition: ald_rtc.h:206
RTC_TAMPER_TRIGGER_HIGH
Definition: ald_rtc.h:207

Definition at line 475 of file ald_rtc.h.

◆ IS_RTC_TS_SIGNAL

#define IS_RTC_TS_SIGNAL ( x )
Value:
(((x) == RTC_TS_SIGNAL_SEL_TAMPER0) || \
((x) == RTC_TS_SIGNAL_SEL_TAMPER1))
RTC_TS_SIGNAL_SEL_TAMPER0
Definition: ald_rtc.h:182
RTC_TS_SIGNAL_SEL_TAMPER1
Definition: ald_rtc.h:183

Definition at line 467 of file ald_rtc.h.

◆ IS_RTC_TS_STYLE

#define IS_RTC_TS_STYLE ( x )
Value:
(((x) == RTC_TS_RISING_EDGE) || \
((x) == RTC_TS_FALLING_EDGE))
RTC_TS_RISING_EDGE
Definition: ald_rtc.h:190
RTC_TS_FALLING_EDGE
Definition: ald_rtc.h:191

Definition at line 469 of file ald_rtc.h.

◆ IS_RTC_WAKEUP_CLOCK

#define IS_RTC_WAKEUP_CLOCK ( x )
Value:
(((x) == RTC_WAKEUP_CLOCK_DIV_16) || \
((x) == RTC_WAKEUP_CLOCK_DIV_8) || \
((x) == RTC_WAKEUP_CLOCK_DIV_4) || \
((x) == RTC_WAKEUP_CLOCK_DIV_2) || \
((x) == RTC_WAKEUP_CLOCK_1HZ) || \
((x) == RTC_WAKEUP_CLOCK_1HZ_PULS))
RTC_WAKEUP_CLOCK_DIV_16
Definition: ald_rtc.h:249
RTC_WAKEUP_CLOCK_DIV_8
Definition: ald_rtc.h:250
RTC_WAKEUP_CLOCK_DIV_2
Definition: ald_rtc.h:252
RTC_WAKEUP_CLOCK_1HZ
Definition: ald_rtc.h:253
RTC_WAKEUP_CLOCK_DIV_4
Definition: ald_rtc.h:251
RTC_WAKEUP_CLOCK_1HZ_PULS
Definition: ald_rtc.h:254

Definition at line 489 of file ald_rtc.h.

◆ IS_RTC_YEAR

#define IS_RTC_YEAR ( x ) ((x) < 100)

Definition at line 562 of file ald_rtc.h.

◆ IS_SHIFT_SUB_SS

#define IS_SHIFT_SUB_SS ( x ) ((x) < (1U << 15))

Definition at line 428 of file ald_rtc.h.

◆ RTC_CALI_LOCK

#define RTC_CALI_LOCK ( ) (WRITE_REG(RTC->CALWPR, 0x0U))

Definition at line 424 of file ald_rtc.h.

◆ RTC_CALI_UNLOCK

#define RTC_CALI_UNLOCK ( ) (WRITE_REG(RTC->CALWPR, 0x699655AAU))

Definition at line 423 of file ald_rtc.h.

◆ RTC_TIMEOUT_VALUE

#define RTC_TIMEOUT_VALUE 100

Definition at line 426 of file ald_rtc.h.


ALD User Manual: CMU

Modules
CMU
EASTSOFT ES32F3xx ALD

CMU module driver. More...

Collaboration diagram for CMU:

Modules

CMU Private Variables
CMU Private Functions
CMU Public Functions
CMU Public Macros
CMU Public Types
CMU Private Macros

Detailed Description

CMU module driver.


ALD User Manual: CMU Private Variables

Variables
CMU Private Variables
EASTSOFT ES32F3xx ALD » CMU
Collaboration diagram for CMU Private Variables:

Variables

uint32_t __system_clock = 24000000U

Detailed Description

Variable Documentation

◆ __system_clock

uint32_t __system_clock = 24000000U

Definition at line 144 of file ald_cmu.c.


ALD User Manual: CMU Private Functions

Functions
CMU Private Functions
EASTSOFT ES32F3xx ALD » CMU
Collaboration diagram for CMU Private Functions:

Functions

static void | cmu_clock_update (uint32_t clock)
Update the current system clock. This function will be invoked, when system clock has changed. More...
void | ald_cmu_irq_handler (void)
CMU module interrupt handler. More...

Detailed Description

Function Documentation

◆ ald_cmu_irq_handler()

void ald_cmu_irq_handler ( void )

CMU module interrupt handler.

Return values
None

Definition at line 174 of file ald_cmu.c.

175 {
176 /* HOSC stop */
177 if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK)) {
178 SYSCFG_UNLOCK();
179 SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK);
180 SYSCFG_LOCK();
181
182 if ((READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK))
183 && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1)
184 || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))))
185 cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000);
186 ald_cmu_irq_cbk(CMU_HOSC_STOP);
187 }
188
189 /* HOSC start */
190 if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIE_MSK)) {
191 SYSCFG_UNLOCK();
192 SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK);
193 SYSCFG_LOCK();
194
195 if (!(READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK))
196 && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))
197 cmu_clock_update((READ_BITS(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, CMU_HOSCCFG_FREQ_POSS) + 1) * 1000000);
198 ald_cmu_irq_cbk(CMU_HOSC_START);
199 }
200
201 /* LOSC stop */
202 if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK)) {
203 SYSCFG_UNLOCK();
204 SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK);
205 SYSCFG_LOCK();
206 ald_cmu_irq_cbk(CMU_LOSC_STOP);
207 }
208
209 /* LOSC start */
210 if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIE_MSK)) {
211 SYSCFG_UNLOCK();
212 SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK);
213 SYSCFG_LOCK();
214 ald_cmu_irq_cbk(CMU_LOSC_START);
215 }
216
217 /* PLL1 lose */
218 if (READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK) && READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK)) {
219 SYSCFG_UNLOCK();
220 SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK);
221 SYSCFG_LOCK();
222
223 if (READ_BIT(CMU->PULMCR, CMU_PULMCR_CLKS_MSK)
224 && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1)
225 || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))))
226 cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000);
227 ald_cmu_irq_cbk(CMU_PLL1_UNLOCK);
228 }
229
230 return;
231 }
CMU_LOSC_STOP
Definition: ald_cmu.h:464
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
CMU_HOSC_START
Definition: ald_cmu.h:468
CMU_PLL1_UNLOCK
Definition: ald_cmu.h:466
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
CMU_HOSC_STOP
Definition: ald_cmu.h:465
CMU_LOSC_START
Definition: ald_cmu.h:467
cmu_clock_update
static void cmu_clock_update(uint32_t clock)
Update the current system clock. This function will be invoked, when system clock has changed...
Definition: ald_cmu.c:160
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
ald_cmu_irq_cbk
__weak void ald_cmu_irq_cbk(cmu_security_t se)
Interrupt callback function.
Definition: ald_cmu.c:799

◆ cmu_clock_update()

static void cmu_clock_update ( uint32_t clock )
static

Update the current system clock. This function will be invoked, when system clock has changed.

Parameters
clock The new clock.
Return values
None

Definition at line 160 of file ald_cmu.c.

161 {
162 __system_clock = clock;
163
164 if (clock > 1000000)
165 ald_tick_init(TICK_INT_PRIORITY);
166
167 return;
168 }
__system_clock
uint32_t __system_clock
Definition: ald_cmu.c:144
ald_tick_init
__weak void ald_tick_init(uint32_t prio)
This function configures the source of the time base. The time source is configured to have 1ms time ...
Definition: utils.c:138
TICK_INT_PRIORITY
#define TICK_INT_PRIORITY
Definition: ald_conf.h:62


ALD User Manual: CMU Public Functions

Modules
CMU Public Functions
EASTSOFT ES32F3xx ALD » CMU
Collaboration diagram for CMU Public Functions:

Modules

System clock configuration
System clock configuration functions.
BUS division control
BUS division control functions.
Clock safe configure
Clock safe configure functions.
Clock output configure
Clock output configure functions.
Peripheral Clock configure
Peripheral clock configure functions.

Detailed Description


ALD User Manual: System clock configuration

Functions
System clock configuration
EASTSOFT ES32F3xx ALD » CMU » CMU Public Functions

System clock configuration functions. More...

Collaboration diagram for System clock configuration:

Functions

ald_status_t | ald_cmu_clock_config_default (void)
Configure system clock using default. Select CMU_CLOCK_HRC(24MHz) as system clock and enable CMU_CLOCK_LRC(32768Hz). More...
ald_status_t | ald_cmu_clock_config (cmu_clock_t clk, uint32_t clock)
Configure system clock using specified parameters. More...
void | ald_cmu_pll1_config (cmu_pll1_input_t input, cmu_pll1_output_t output)
Configure PLL1 using specified parameters. More...
uint32_t | ald_cmu_get_clock (void)
Gets current system clock. More...

Detailed Description

System clock configuration functions.

==============================================================================
            ##### System clock Configuration functions #####
==============================================================================
  [..]  This section provides functions allowing to:
    (+) Configure system clock using default parameters.
    (+) Configure system clock using specified parameters.
    (+) Configure PLL1 using specified parameters.
    (+) Get system clock.

Function Documentation

◆ ald_cmu_clock_config()

ald_status_t ald_cmu_clock_config | ( | cmu_clock_t | clk,
 |  | uint32_t | clock
 | ) |  |

Configure system clock using specified parameters.

Parameters
clk The parameter can be one of the following:
  • CMU_CLOCK_HRC 2MHz or 24MHz
  • CMU_CLOCK_LRC 32768Hz
  • CMU_CLOCK_LOSC 32768Hz
  • CMU_CLOCK_PLL1 One of cmu_pll1_output_t
  • CMU_CLOCK_HOSC 1MHz – 24MHz
clock The clock which will be set. the value depends on the parameter of clk.
Return values
The status of ALD.

Definition at line 307 of file ald_cmu.c.

308 {
309 uint32_t cnt = 4000;
310
311 assert_param(IS_CMU_CLOCK(clk));
312 SYSCFG_UNLOCK();
313
314 switch (clk) {
315 case CMU_CLOCK_HRC:
316 assert_param(clock == 24000000 || clock == 2000000);
317
318 MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS);
319 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
320
321 if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) {
322 SYSCFG_LOCK();
323 return ERROR;
324 }
325
326 if (clock == 24000000)
327 CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK);
328 else
329 SET_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK);
330
331 SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK);
332
333 for (cnt = 4000; cnt; --cnt);
334 cnt = 4000;
335 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCACT_MSK))) && (--cnt));
336 cnt = 4000;
337 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCRDY_MSK))) && (--cnt));
338
339 cmu_clock_update(clock);
340 break;
341
342 case CMU_CLOCK_LRC:
343 /* Close SysTick interrupt in lower clock */
344 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
345
346 MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LRC << CMU_CSR_SYS_CMD_POSS);
347 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
348
349 if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LRC) {
350 SYSCFG_LOCK();
351 return ERROR;
352 }
353
354 SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK);
355
356 cnt = 4000;
357 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCACT_MSK))) && (--cnt));
358 cnt = 4000;
359 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCRDY_MSK))) && (--cnt));
360
361 cmu_clock_update(32768);
362 break;
363
364 case CMU_CLOCK_LOSC:
365 /* Close SysTick interrupt in lower clock */
366 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
367
368 MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LOSC << CMU_CSR_SYS_CMD_POSS);
369 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
370
371 if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LOSC) {
372 SYSCFG_LOCK();
373 return ERROR;
374 }
375
376 SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK);
377
378 cnt = 4000;
379 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCACT_MSK))) && (--cnt));
380 cnt = 4000;
381 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCRDY_MSK))) && (--cnt));
382
383 cmu_clock_update(32768);
384 break;
385
386 case CMU_CLOCK_PLL1:
387 for (cnt = 0; cnt < 5000; ++cnt);
388 MODIFY_REG(CMU->CSR, CMU_CSR_CFT_CMD_MSK, 0xAA << CMU_CSR_CFT_CMD_POSS);
389 MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_PLL1 << CMU_CSR_SYS_CMD_POSS);
390 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
391
392 if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_PLL1) {
393 SYSCFG_LOCK();
394 return ERROR;
395 }
396
397 SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK);
398
399 for (cnt = 0; cnt < 5000; ++cnt);
400 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1ACT_MSK))) && (--cnt));
401 cnt = 4000;
402 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt));
403
404 if (clock == 96000000) {
405 ald_cmu_div_config(CMU_HCLK_1, CMU_DIV_2);
406 ald_cmu_div_config(CMU_HCLK_2, CMU_DIV_2);
407 ald_cmu_div_config(CMU_PCLK_1, CMU_DIV_2);
408 ald_cmu_div_config(CMU_PCLK_2, CMU_DIV_4);
409 for (cnt = 0; cnt < 20000; ++cnt);
410 }
411 if (clock == 72000000) {
412 ald_cmu_div_config(CMU_PCLK_2, CMU_DIV_4);
413 }
414 if ((clock == 48000000) || (clock == 36000000)) {
415 ald_cmu_div_config(CMU_PCLK_2, CMU_DIV_2);
416 }
417
418 cmu_clock_update(clock);
419 break;
420
421 case CMU_CLOCK_HOSC:
422 assert_param(clock <= 24000000);
423
424 MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HOSC << CMU_CSR_SYS_CMD_POSS);
425 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
426
427 if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HOSC) {
428 SYSCFG_LOCK();
429 return ERROR;
430 }
431
432 SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK);
433 MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 1000000 - 1);
434
435 for (cnt = 8000; cnt; --cnt);
436 cnt = 4000;
437 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCACT_MSK))) && (--cnt));
438 cnt = 4000;
439 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt));
440
441 cmu_clock_update(clock);
442 break;
443
444 default:
445 break;
446 }
447
448 SYSCFG_LOCK();
449 return OK;
450 }
OK
Definition: utils.h:55
CMU_DIV_2
Definition: ald_cmu.h:231
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
CMU_CLOCK_HOSC
Definition: ald_cmu.h:177
CMU_CLOCK_HRC
Definition: ald_cmu.h:173
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
CMU_CLOCK_LOSC
Definition: ald_cmu.h:175
IS_CMU_CLOCK
#define IS_CMU_CLOCK(x)
Definition: ald_cmu.h:511
CMU_CLOCK_PLL1
Definition: ald_cmu.h:176
CMU_CLOCK_LRC
Definition: ald_cmu.h:174
CMU_HCLK_1
Definition: ald_cmu.h:249
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
CMU_HCLK_2
Definition: ald_cmu.h:250
ald_cmu_div_config
void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div)
Configure the bus division.
Definition: ald_cmu.c:543
CMU_PCLK_1
Definition: ald_cmu.h:252
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
cmu_clock_update
static void cmu_clock_update(uint32_t clock)
Update the current system clock. This function will be invoked, when system clock has changed...
Definition: ald_cmu.c:160
CMU_PCLK_2
Definition: ald_cmu.h:253
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
CMU_DIV_4
Definition: ald_cmu.h:232
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
ERROR
Definition: utils.h:56

◆ ald_cmu_clock_config_default()

ald_status_t ald_cmu_clock_config_default ( void )

Configure system clock using default. Select CMU_CLOCK_HRC(24MHz) as system clock and enable CMU_CLOCK_LRC(32768Hz).

Return values
The status of ALD.

Definition at line 263 of file ald_cmu.c.

264 {
265 uint32_t cnt = 4000, tmp;
266
267 SYSCFG_UNLOCK();
268
269 /* Select HRC */
270 MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS);
271
272 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
273
274 if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) {
275 SYSCFG_LOCK();
276 return ERROR;
277 }
278
279 WRITE_REG(CMU->CFGR, 0x0);
280 CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK); /* Select 24Mhz */
281
282 tmp = READ_REG(CMU->CLKENR);
283 /* Enable HRC/LRC/LOSC */
284 SET_BIT(tmp, CMU_CLKENR_HRCEN_MSK | CMU_CLKENR_LRCEN_MSK | CMU_CLKENR_LOSCEN_MSK);
285 WRITE_REG(CMU->CLKENR, tmp);
286 /* Reset LRC */
287 for (cnt = 0; cnt < 10000; ++cnt);
288 CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK);
289 SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK);
290
291 SYSCFG_LOCK();
292 return OK;
293 }
OK
Definition: utils.h:55
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
READ_REG
#define READ_REG(reg)
Definition: type.h:73
CMU_CLOCK_HRC
Definition: ald_cmu.h:173
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
ERROR
Definition: utils.h:56

◆ ald_cmu_get_clock()

uint32_t ald_cmu_get_clock ( void )

Gets current system clock.

Return values
The value of system clock.

Definition at line 506 of file ald_cmu.c.

507 {
508 return __system_clock;
509 }
__system_clock
uint32_t __system_clock
Definition: ald_cmu.c:144

◆ ald_cmu_pll1_config()

void ald_cmu_pll1_config | ( | cmu_pll1_input_t | input,
 |  | cmu_pll1_output_t | output
 | ) |  |

Configure PLL1 using specified parameters.

Parameters
input | The input clock type.
output | The output clock which can be 36MHz/48MHz/72MHz/96MHz. When input = CMU_PLL1_INPUT_PLL2; then output must be CMU_PLL1_OUTPUT_36M, and then the real clock is (32768x1024)Hz.
Return values
None

Definition at line 462 of file ald_cmu.c.

463 {
464 uint32_t cnt = 4000;
465
466 assert_param(IS_CMU_PLL1_INPUT(input));
467 assert_param(IS_CMU_PLL1_OUTPUT(output));
468
469 SYSCFG_UNLOCK();
470
471 if (input == CMU_PLL1_INPUT_HRC_6) {
472 SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK);
473 }
474 else if (input == CMU_PLL1_INPUT_PLL2) {
475 SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK);
476 CLEAR_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2RFS_MSK);
477 SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK);
478 }
479 else {
480 SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK);
481 for (cnt = 0; cnt < 10000; ++cnt);
482 cnt = 20000;
483 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt));
484 }
485
486 MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1RFS_MSK, input << CMU_PLLCFG_PLL1RFS_POSS);
487 MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1OS_MSK, output << CMU_PLLCFG_PLL1OS_POSS);
488 SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK);
489
490 for (cnt = 0; cnt < 4000; ++cnt);
491 while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL1LCKN_MSK)) && (--cnt));
492 cnt = 4000;
493 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt));
494
495 SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK);
496 MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 0x3 << CMU_PULMCR_MODE_POSS);
497
498 SYSCFG_LOCK();
499 return;
500 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
IS_CMU_PLL1_INPUT
#define IS_CMU_PLL1_INPUT(x)
Definition: ald_cmu.h:526
CMU_PLL1_INPUT_HRC_6
Definition: ald_cmu.h:196
CMU_PLL1_INPUT_PLL2
Definition: ald_cmu.h:197
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39


ALD User Manual: BUS division control

Functions
BUS division control
EASTSOFT ES32F3xx ALD » CMU » CMU Public Functions

BUS division control functions. More...

Collaboration diagram for BUS division control:

Functions

void | ald_cmu_div_config (cmu_bus_t bus, cmu_div_t div)
Configure the bus division. More...
uint32_t | ald_cmu_get_hclk1_clock (void)
Get AHB1 clock. More...
uint32_t | ald_cmu_get_hclk2_clock (void)
Get AHB2 clock. More...
uint32_t | ald_cmu_get_sys_clock (void)
Get SYS clock. More...
uint32_t | ald_cmu_get_pclk1_clock (void)
Get APB1 clock. More...
uint32_t | ald_cmu_get_pclk2_clock (void)
Get APB2 clock. More...

Detailed Description

BUS division control functions.

==============================================================================
            ##### BUS division control functions #####
==============================================================================
  [..]  This section provides functions allowing to:
    (+) Configure the bus division.
    (+) Get ahb1 clock.
    (+) Get sys bus clock.
    (+) Get apb1 clock.
    (+) Get apb2 clock.

Function Documentation

◆ ald_cmu_div_config()

void ald_cmu_div_config | ( | cmu_bus_t | bus,
 |  | cmu_div_t | div
 | ) |  |

Configure the bus division.

Parameters
bus The type of bus:
  • CMU_HCLK_1
  • CMU_SYS
  • CMU_PCLK_1
  • CMU_PCLK_2
div The value of divider.
Return values
None

Definition at line 543 of file ald_cmu.c.

544 {
545 assert_param(IS_CMU_BUS(bus));
546 assert_param(IS_CMU_DIV(div));
547
548 SYSCFG_UNLOCK();
549
550 switch (bus) {
551 case CMU_HCLK_1:
552 MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, div << CMU_CFGR_HCLK1DIV_POSS);
553 break;
554
555 case CMU_HCLK_2:
556 MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK2DIV_MSK, div << CMU_CFGR_HCLK2DIV_POSS);
557 break;
558
559 case CMU_SYS:
560 MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, div << CMU_CFGR_SYSDIV_POSS);
561
562 if ((__system_clock >> div) <= 1000000) {
563 /* Close SysTick interrupt in lower clock */
564 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
565 }
566 else {
567 ald_tick_init(TICK_INT_PRIORITY);
568 }
569
570 break;
571
572 case CMU_PCLK_1:
573 MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, div << CMU_CFGR_PCLK1DIV_POSS);
574 break;
575
576 case CMU_PCLK_2:
577 MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, div << CMU_CFGR_PCLK2DIV_POSS);
578 break;
579
580 default:
581 break;
582 }
583
584 SYSCFG_LOCK();
585 return;
586 }
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
__system_clock
uint32_t __system_clock
Definition: ald_cmu.c:144
ald_tick_init
__weak void ald_tick_init(uint32_t prio)
This function configures the source of the time base. The time source is configured to have 1ms time ...
Definition: utils.c:138
CMU_HCLK_1
Definition: ald_cmu.h:249
IS_CMU_DIV
#define IS_CMU_DIV(x)
Definition: ald_cmu.h:539
CMU_HCLK_2
Definition: ald_cmu.h:250
CMU_PCLK_1
Definition: ald_cmu.h:252
CMU_PCLK_2
Definition: ald_cmu.h:253
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
CMU_SYS
Definition: ald_cmu.h:251
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
TICK_INT_PRIORITY
#define TICK_INT_PRIORITY
Definition: ald_conf.h:62
IS_CMU_BUS
#define IS_CMU_BUS(x)
Definition: ald_cmu.h:552

◆ ald_cmu_get_hclk1_clock()

uint32_t ald_cmu_get_hclk1_clock ( void )

Get AHB1 clock.

Return values
The value of AHB1 clock.

Definition at line 592 of file ald_cmu.c.

593 {
594 uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS);
595 uint32_t ahb_div = READ_BITS(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, CMU_CFGR_HCLK1DIV_POSS);
596
597 return (__system_clock >> sys_div) >> ahb_div;
598 }
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
__system_clock
uint32_t __system_clock
Definition: ald_cmu.c:144

◆ ald_cmu_get_hclk2_clock()

uint32_t ald_cmu_get_hclk2_clock ( void )

Get AHB2 clock.

Return values
The value of AHB2 clock.

Definition at line 604 of file ald_cmu.c.

605 {
606 uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS);
607 uint32_t ahb_div = READ_BITS(CMU->CFGR, CMU_CFGR_HCLK2DIV_MSK, CMU_CFGR_HCLK2DIV_POSS);
608
609 return (__system_clock >> sys_div) >> ahb_div;
610 }
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
__system_clock
uint32_t __system_clock
Definition: ald_cmu.c:144

◆ ald_cmu_get_pclk1_clock()

uint32_t ald_cmu_get_pclk1_clock ( void )

Get APB1 clock.

Return values
The value of APB1 clock.

Definition at line 627 of file ald_cmu.c.

628 {
629 uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS);
630 uint32_t apb1_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, CMU_CFGR_PCLK1DIV_POSS);
631
632 return (__system_clock >> sys_div) >> apb1_div;
633 }
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
__system_clock
uint32_t __system_clock
Definition: ald_cmu.c:144

◆ ald_cmu_get_pclk2_clock()

uint32_t ald_cmu_get_pclk2_clock ( void )

Get APB2 clock.

Return values
The value of APB2 clock.

Definition at line 639 of file ald_cmu.c.

640 {
641 uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS);
642 uint32_t apb2_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, CMU_CFGR_PCLK2DIV_POSS);
643
644 return (__system_clock >> sys_div) >> apb2_div;
645 }
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
__system_clock
uint32_t __system_clock
Definition: ald_cmu.c:144

◆ ald_cmu_get_sys_clock()

uint32_t ald_cmu_get_sys_clock ( void )

Get SYS clock.

Return values
The value of SYS clock

Definition at line 616 of file ald_cmu.c.

617 {
618 uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS);
619
620 return __system_clock >> sys_div;
621 }
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
__system_clock
uint32_t __system_clock
Definition: ald_cmu.c:144


ALD User Manual: Clock safe configure

Functions
Clock safe configure
EASTSOFT ES32F3xx ALD » CMU » CMU Public Functions

Clock safe configure functions. More...

Collaboration diagram for Clock safe configure:

Functions

void | ald_cmu_hosc_safe_config (cmu_hosc_range_t clock, type_func_t status)
Enable/Disable outer high crystal safe mode. More...
void | ald_cmu_losc_safe_config (type_func_t status)
Enable/Disable outer low crystal safe mode. More...
void | ald_cmu_pll_safe_config (type_func_t status)
Enable/Disable PLL1 safe mode. More...
uint32_t | ald_cmu_current_clock_source_get (cmu_clock_safe_type_t type)
Get current clock source. More...
flag_status_t | ald_cmu_get_clock_state (cmu_clock_state_t sr)
Get clock state. More...
__weak void | ald_cmu_irq_cbk (cmu_security_t se)
Interrupt callback function. More...
void | ald_cmu_irq_handler (void)
CMU module interrupt handler. More...

Detailed Description

Clock safe configure functions.

==============================================================================
            ##### Clock safe configure functions #####
==============================================================================
  [..]  This section provides functions allowing to:
    (+) Enable/Disable outer high crystal safe mode.
    (+) Enable/Disable outer low crystal safe mode.
    (+) Enable/Disable PLL1 safe mode.
    (+) Interrupt callback function.

Function Documentation

◆ ald_cmu_current_clock_source_get()

uint32_t ald_cmu_current_clock_source_get ( cmu_clock_safe_type_t type )

Get current clock source.

Parameters
type Type of source: HOSC/LOSC/PLL.
Return values
Status
  • 0: Current clock is HOSC, LOSC or PLL
  • 1: Current clock is HRC, LRC or HRC

Definition at line 766 of file ald_cmu.c.

767 {
768 assert_param(IS_CMU_SAFE_CLOCK_TYPE(type));
769
770 if (type == CMU_SAFE_CLK_HOSC)
771 return READ_BITS(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK, CMU_HOSMCR_CLKS_POS);
772 else if (type == CMU_SAFE_CLK_LOSC)
773 return READ_BITS(CMU->LOSMCR, CMU_LOSMCR_CLKS_MSK, CMU_LOSMCR_CLKS_POS);
774 else
775 return READ_BITS(CMU->PULMCR, CMU_PULMCR_CLKS_MSK, CMU_PULMCR_CLKS_POS);
776 }
assert_param
#define assert_param(x)
Definition: type.h:88
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
CMU_SAFE_CLK_LOSC
Definition: ald_cmu.h:222
CMU_SAFE_CLK_HOSC
Definition: ald_cmu.h:221
IS_CMU_SAFE_CLOCK_TYPE
#define IS_CMU_SAFE_CLOCK_TYPE(x)
Definition: ald_cmu.h:578

◆ ald_cmu_get_clock_state()

flag_status_t ald_cmu_get_clock_state ( cmu_clock_state_t sr )

Get clock state.

Parameters
sr The state type, see cmu_clock_state_t.
Return values
SET/RESET

Definition at line 783 of file ald_cmu.c.

784 {
785 assert_param(IS_CMU_CLOCK_STATE(sr));
786
787 if (READ_BIT(CMU->CLKSR, sr))
788 return SET;
789
790 return RESET;
791 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
RESET
Definition: type.h:38
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
IS_CMU_CLOCK_STATE
#define IS_CMU_CLOCK_STATE(x)
Definition: ald_cmu.h:680

◆ ald_cmu_hosc_safe_config()

void ald_cmu_hosc_safe_config | ( | cmu_hosc_range_t | clock,
 |  | type_func_t | status
 | ) |  |

Enable/Disable outer high crystal safe mode.

Parameters
clock | the value of outer crystal frequency.
status | The new status.
Return values
None

Definition at line 673 of file ald_cmu.c.

674 {
675 assert_param(IS_CMU_HOSC_RANGE(clock));
676 assert_param(IS_FUNC_STATE(status));
677
678 SYSCFG_UNLOCK();
679
680 if (status) {
681 SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK);
682 MODIFY_REG(CMU->HOSMCR, CMU_HOSMCR_FRQS_MSK, clock << CMU_HOSMCR_FRQS_POSS);
683 SET_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK);
684 SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK);
685
686 ald_mcu_irq_config(CMU_IRQn, 3, 3, ENABLE);
687 }
688 else {
689 CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK);
690 CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK);
691
692 if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0)
693 ald_mcu_irq_config(CMU_IRQn, 3, 3, DISABLE);
694 }
695
696 SYSCFG_LOCK();
697 return;
698 }
ENABLE
Definition: type.h:49
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
DISABLE
Definition: type.h:48
IS_CMU_HOSC_RANGE
#define IS_CMU_HOSC_RANGE(x)
Definition: ald_cmu.h:534
ald_mcu_irq_config
void ald_mcu_irq_config(IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, type_func_t status)
Configure interrupt.
Definition: utils.c:375
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_cmu_irq_cbk()

void ald_cmu_irq_cbk ( cmu_security_t se )

Interrupt callback function.

Note
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values
None

Definition at line 799 of file ald_cmu.c.

800 {
801 return;
802 }

◆ ald_cmu_irq_handler()

void ald_cmu_irq_handler ( void )

CMU module interrupt handler.

Return values
None

Definition at line 174 of file ald_cmu.c.

175 {
176 /* HOSC stop */
177 if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK)) {
178 SYSCFG_UNLOCK();
179 SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK);
180 SYSCFG_LOCK();
181
182 if ((READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK))
183 && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1)
184 || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))))
185 cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000);
186 ald_cmu_irq_cbk(CMU_HOSC_STOP);
187 }
188
189 /* HOSC start */
190 if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIE_MSK)) {
191 SYSCFG_UNLOCK();
192 SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK);
193 SYSCFG_LOCK();
194
195 if (!(READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK))
196 && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))
197 cmu_clock_update((READ_BITS(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, CMU_HOSCCFG_FREQ_POSS) + 1) * 1000000);
198 ald_cmu_irq_cbk(CMU_HOSC_START);
199 }
200
201 /* LOSC stop */
202 if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK)) {
203 SYSCFG_UNLOCK();
204 SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK);
205 SYSCFG_LOCK();
206 ald_cmu_irq_cbk(CMU_LOSC_STOP);
207 }
208
209 /* LOSC start */
210 if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIE_MSK)) {
211 SYSCFG_UNLOCK();
212 SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK);
213 SYSCFG_LOCK();
214 ald_cmu_irq_cbk(CMU_LOSC_START);
215 }
216
217 /* PLL1 lose */
218 if (READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK) && READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK)) {
219 SYSCFG_UNLOCK();
220 SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK);
221 SYSCFG_LOCK();
222
223 if (READ_BIT(CMU->PULMCR, CMU_PULMCR_CLKS_MSK)
224 && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1)
225 || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))))
226 cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000);
227 ald_cmu_irq_cbk(CMU_PLL1_UNLOCK);
228 }
229
230 return;
231 }
CMU_LOSC_STOP
Definition: ald_cmu.h:464
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
CMU_HOSC_START
Definition: ald_cmu.h:468
CMU_PLL1_UNLOCK
Definition: ald_cmu.h:466
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
CMU_HOSC_STOP
Definition: ald_cmu.h:465
CMU_LOSC_START
Definition: ald_cmu.h:467
cmu_clock_update
static void cmu_clock_update(uint32_t clock)
Update the current system clock. This function will be invoked, when system clock has changed...
Definition: ald_cmu.c:160
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
ald_cmu_irq_cbk
__weak void ald_cmu_irq_cbk(cmu_security_t se)
Interrupt callback function.
Definition: ald_cmu.c:799

◆ ald_cmu_losc_safe_config()

void ald_cmu_losc_safe_config ( type_func_t status )

Enable/Disable outer low crystal safe mode.

Parameters
status The new status.
Return values
None

Definition at line 705 of file ald_cmu.c.

706 {
707 assert_param(IS_FUNC_STATE(status));
708 SYSCFG_UNLOCK();
709
710 if (status) {
711 SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK);
712 SET_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK);
713 SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK);
714
715 ald_mcu_irq_config(CMU_IRQn, 3, 3, ENABLE);
716 }
717 else {
718 CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK);
719 CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK);
720
721 if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0)
722 ald_mcu_irq_config(CMU_IRQn, 3, 3, DISABLE);
723 }
724
725 SYSCFG_LOCK();
726 return;
727 }
ENABLE
Definition: type.h:49
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
DISABLE
Definition: type.h:48
ald_mcu_irq_config
void ald_mcu_irq_config(IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, type_func_t status)
Configure interrupt.
Definition: utils.c:375
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_cmu_pll_safe_config()

void ald_cmu_pll_safe_config ( type_func_t status )

Enable/Disable PLL1 safe mode.

Parameters
status The new status.
Return values
None

Definition at line 734 of file ald_cmu.c.

735 {
736 assert_param(IS_FUNC_STATE(status));
737 SYSCFG_UNLOCK();
738
739 if (status) {
740 SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK);
741 MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 2 << CMU_PULMCR_MODE_POSS);
742 SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK);
743 SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK);
744
745 ald_mcu_irq_config(CMU_IRQn, 3, 3, ENABLE);
746 }
747 else {
748 CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK);
749 CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK);
750
751 if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0)
752 ald_mcu_irq_config(CMU_IRQn, 3, 3, DISABLE);
753 }
754
755 SYSCFG_LOCK();
756 return;
757 }
ENABLE
Definition: type.h:49
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
DISABLE
Definition: type.h:48
ald_mcu_irq_config
void ald_mcu_irq_config(IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, type_func_t status)
Configure interrupt.
Definition: utils.c:375
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73


ALD User Manual: Clock output configure

Functions
Clock output configure
EASTSOFT ES32F3xx ALD » CMU » CMU Public Functions

Clock output configure functions. More...

Collaboration diagram for Clock output configure:

Functions

void | ald_cmu_output_high_clock_config (cmu_output_high_sel_t sel, cmu_output_high_div_t div, type_func_t status)
Configure the high-speed clock output. More...
void | ald_cmu_output_low_clock_config (cmu_output_low_sel_t sel, type_func_t status)
Configure the low-speed clock output. More...

Detailed Description

Clock output configure functions.

==============================================================================
            ##### Clock output configure functions #####
==============================================================================
  [..]  This section provides functions allowing to:
    (+) Configure the high-speed clock output.
    (+) Configure the low-speed clock output.

Function Documentation

◆ ald_cmu_output_high_clock_config()

void ald_cmu_output_high_clock_config | ( | cmu_output_high_sel_t | sel,
 |  | cmu_output_high_div_t | div,
 |  | type_func_t | status
 | ) |  |

Configure the high-speed clock output.

Parameters
sel Select the source:
  • CMU_OUTPUT_HIGH_SEL_HOSC
  • CMU_OUTPUT_HIGH_SEL_LOSC
  • CMU_OUTPUT_HIGH_SEL_HRC
  • CMU_OUTPUT_HIGH_SEL_LRC
  • CMU_OUTPUT_HIGH_SEL_HOSM
  • CMU_OUTPUT_HIGH_SEL_PLL1
  • CMU_OUTPUT_HIGH_SEL_PLL2
  • CMU_OUTPUT_HIGH_SEL_SYSCLK
div The value of divider:
  • CMU_OUTPUT_DIV_1
  • CMU_OUTPUT_DIV_2
  • CMU_OUTPUT_DIV_4
  • CMU_OUTPUT_DIV_8
  • CMU_OUTPUT_DIV_16
  • CMU_OUTPUT_DIV_32
  • CMU_OUTPUT_DIV_64
  • CMU_OUTPUT_DIV_128
status The new status.
Return values
None

Definition at line 845 of file ald_cmu.c.

847 {
848 assert_param(IS_CMU_OUTPUT_HIGH_SEL(sel));
849 assert_param(IS_CMU_OUTPUT_HIGH_DIV(div));
850 assert_param(IS_FUNC_STATE(status));
851
852 SYSCFG_UNLOCK();
853
854 if (status) {
855 MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCOS_MSK, sel << CMU_CLKOCR_HSCOS_POSS);
856 MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCODIV_MSK, div << CMU_CLKOCR_HSCODIV_POSS);
857 SET_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK);
858 }
859 else {
860 CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK);
861 }
862
863 SYSCFG_LOCK();
864 return;
865 }
IS_CMU_OUTPUT_HIGH_DIV
#define IS_CMU_OUTPUT_HIGH_DIV(x)
Definition: ald_cmu.h:565
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
IS_CMU_OUTPUT_HIGH_SEL
#define IS_CMU_OUTPUT_HIGH_SEL(x)
Definition: ald_cmu.h:557
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_cmu_output_low_clock_config()

void ald_cmu_output_low_clock_config | ( | cmu_output_low_sel_t | sel,
 |  | type_func_t | status
 | ) |  |

Configure the low-speed clock output.

Parameters
sel Select the source:
  • CMU_OUTPUT_LOW_SEL_LOSC
  • CMU_OUTPUT_LOW_SEL_LRC
  • CMU_OUTPUT_LOW_SEL_LOSM
  • CMU_OUTPUT_LOW_SEL_BUZZ
  • CMU_OUTPUT_LOW_SEL_ULRC
status The new status.
Return values
None

Definition at line 878 of file ald_cmu.c.

879 {
880 assert_param(IS_CMU_OUTPUT_LOW_SEL(sel));
881 assert_param(IS_FUNC_STATE(status));
882
883 SYSCFG_UNLOCK();
884
885 if (status) {
886 MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_LSCOS_MSK, sel << CMU_CLKOCR_LSCOS_POSS);
887 SET_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK);
888 }
889 else {
890 CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK);
891 }
892
893 SYSCFG_LOCK();
894 return;
895 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_CMU_OUTPUT_LOW_SEL
#define IS_CMU_OUTPUT_LOW_SEL(x)
Definition: ald_cmu.h:573
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73


ALD User Manual: Peripheral Clock configure

Functions
Peripheral Clock configure
EASTSOFT ES32F3xx ALD » CMU » CMU Public Functions

Peripheral clock configure functions. More...

Collaboration diagram for Peripheral Clock configure:

Functions

void | ald_cmu_buzz_config (cmu_buzz_div_t div, uint16_t dat, type_func_t status)
Configure buzz clock. freq = sysclk / (2^(div + 1) * (dat + 1)) More...
void | ald_cmu_lptim0_clock_select (cmu_lp_perh_clock_sel_t clock)
Select lptim0 clock source. More...
void | ald_cmu_lpuart0_clock_select (cmu_lp_perh_clock_sel_t clock)
Select lpuart0 clock source. More...
void | ald_cmu_lcd_clock_select (cmu_lcd_clock_sel_t clock)
Select lcd clock source. More...
void | ald_cmu_qspi_clock_select (cmu_qspi_clock_sel_t clock)
Select QSPI clock source. More...
void | ald_cmu_usb_clock_config (cmu_usb_clock_sel_t clock, cmu_usb_div_t div)
Configure USB clock source. More...
void | ald_cmu_perh_clock_config (cmu_perh_t perh, type_func_t status)
Enable/Disable peripheral clock. More...
void | ald_cmu_stop1_clock_sel (cmu_stop1_clock_t clock)
Select stop1 clock. More...

Detailed Description

Peripheral clock configure functions.

==============================================================================
            ##### Peripheral clock configure functions #####
==============================================================================
  [..]  This section provides functions allowing to:
    (+) Configure buzz clock.
    (+) Select lptim0 clock source.
    (+) Select lpuart0 clock source.
    (+) Select lcd clock source.
    (+) Enable/Disable peripheral clock.

Function Documentation

◆ ald_cmu_buzz_config()

void ald_cmu_buzz_config | ( | cmu_buzz_div_t | div,
 |  | uint16_t | dat,
 |  | type_func_t | status
 | ) |  |

Configure buzz clock. freq = sysclk / (2^(div + 1) * (dat + 1))

Parameters
div | The value of divider.
dat | The value of coefficient.
status | The new status.
Return values
None

Definition at line 926 of file ald_cmu.c.

927 {
928 assert_param(IS_CMU_BUZZ_DIV(div));
929 assert_param(IS_FUNC_STATE(status));
930
931 SYSCFG_UNLOCK();
932
933 if (status) {
934 MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DIV_MSK, div << CMU_BUZZCR_DIV_POSS);
935 MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DAT_MSK, dat << CMU_BUZZCR_DAT_POSS);
936 SET_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK);
937 }
938 else {
939 CLEAR_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK);
940 }
941
942 SYSCFG_LOCK();
943 return;
944 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_CMU_BUZZ_DIV
#define IS_CMU_BUZZ_DIV(x)
Definition: ald_cmu.h:581
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_cmu_lcd_clock_select()

void ald_cmu_lcd_clock_select ( cmu_lcd_clock_sel_t clock )

Select lcd clock source.

Parameters
clock The clock source:
  • CMU_LCD_SEL_LOSM
  • CMU_LCD_SEL_LOSC
  • CMU_LCD_SEL_LRC
  • CMU_LCD_SEL_ULRC
  • CMU_LCD_SEL_HRC_1M
  • CMU_LCD_SEL_HOSC_1M
Return values
None

Definition at line 1013 of file ald_cmu.c.

1014 {
1015 assert_param(IS_CMU_LCD_CLOCK_SEL(clock));
1016
1017 SYSCFG_UNLOCK();
1018 MODIFY_REG(CMU->PERICR, CMU_PERICR_LCD_MSK, clock << CMU_PERICR_LCD_POSS);
1019 SYSCFG_LOCK();
1020
1021 return;
1022 }
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
IS_CMU_LCD_CLOCK_SEL
#define IS_CMU_LCD_CLOCK_SEL(x)
Definition: ald_cmu.h:601
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39

◆ ald_cmu_lptim0_clock_select()

void ald_cmu_lptim0_clock_select ( cmu_lp_perh_clock_sel_t clock )

Select lptim0 clock source.

Parameters
clock The clock source:
  • CMU_LP_PERH_CLOCK_SEL_PCLK2
  • CMU_LP_PERH_CLOCK_SEL_PLL1
  • CMU_LP_PERH_CLOCK_SEL_PLL2
  • CMU_LP_PERH_CLOCK_SEL_HRC
  • CMU_LP_PERH_CLOCK_SEL_HOSC
  • CMU_LP_PERH_CLOCK_SEL_LRC
  • CMU_LP_PERH_CLOCK_SEL_LOSC
  • CMU_LP_PERH_CLOCK_SEL_ULRC
  • CMU_LP_PERH_CLOCK_SEL_HRC_1M
  • CMU_LP_PERH_CLOCK_SEL_HOSC_1M
  • CMU_LP_PERH_CLOCK_SEL_LOSM
  • CMU_LP_PERH_CLOCK_SEL_HOSM
Return values
None

Definition at line 963 of file ald_cmu.c.

964 {
965 assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock));
966
967 SYSCFG_UNLOCK();
968 MODIFY_REG(CMU->PERICR, CMU_PERICR_LPTIM0_MSK, clock << CMU_PERICR_LPTIM0_POSS);
969 SYSCFG_LOCK();
970
971 return;
972 }
IS_CMU_LP_PERH_CLOCK_SEL
#define IS_CMU_LP_PERH_CLOCK_SEL(x)
Definition: ald_cmu.h:589
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39

◆ ald_cmu_lpuart0_clock_select()

void ald_cmu_lpuart0_clock_select ( cmu_lp_perh_clock_sel_t clock )

Select lpuart0 clock source.

Parameters
clock The clock source:
  • CMU_LP_PERH_CLOCK_SEL_PCLK2
  • CMU_LP_PERH_CLOCK_SEL_PLL1
  • CMU_LP_PERH_CLOCK_SEL_PLL2
  • CMU_LP_PERH_CLOCK_SEL_HRC
  • CMU_LP_PERH_CLOCK_SEL_HOSC
  • CMU_LP_PERH_CLOCK_SEL_LRC
  • CMU_LP_PERH_CLOCK_SEL_LOSC
  • CMU_LP_PERH_CLOCK_SEL_ULRC
  • CMU_LP_PERH_CLOCK_SEL_HRC_1M
  • CMU_LP_PERH_CLOCK_SEL_HOSC_1M
  • CMU_LP_PERH_CLOCK_SEL_LOSM
  • CMU_LP_PERH_CLOCK_SEL_HOSM
Return values
None

Definition at line 991 of file ald_cmu.c.

992 {
993 assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock));
994
995 SYSCFG_UNLOCK();
996 MODIFY_REG(CMU->PERICR, CMU_PERICR_LPUART0_MSK, clock << CMU_PERICR_LPUART0_POSS);
997 SYSCFG_LOCK();
998
999 return;
1000 }
IS_CMU_LP_PERH_CLOCK_SEL
#define IS_CMU_LP_PERH_CLOCK_SEL(x)
Definition: ald_cmu.h:589
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39

◆ ald_cmu_perh_clock_config()

void ald_cmu_perh_clock_config | ( | cmu_perh_t | perh,
 |  | type_func_t | status
 | ) |  |

Enable/Disable peripheral clock.

Parameters
perh | The type of peripheral, you can see cmu_perh_t
status | The new status.
Return values
None

Definition at line 1071 of file ald_cmu.c.

1072 {
1073 uint32_t idx, pos;
1074
1075 assert_param(IS_CMU_PERH(perh));
1076 assert_param(IS_FUNC_STATE(status));
1077
1078 SYSCFG_UNLOCK();
1079
1080 if (perh == CMU_PERH_ALL) {
1081 if (status) {
1082 WRITE_REG(CMU->AHB1ENR, ~0);
1083 WRITE_REG(CMU->APB1ENR, ~0);
1084 WRITE_REG(CMU->APB2ENR, ~0);
1085 }
1086 else {
1087 WRITE_REG(CMU->AHB1ENR, 0);
1088 WRITE_REG(CMU->APB1ENR, 0);
1089 WRITE_REG(CMU->APB2ENR, 0);
1090 }
1091
1092 SYSCFG_LOCK();
1093 return;
1094 }
1095
1096 idx = (perh >> 27) & 0x3;
1097 pos = perh & ~(0x3 << 27);
1098
1099 if (status) {
1100 switch (idx) {
1101 case 0:
1102 SET_BIT(CMU->AHB1ENR, pos);
1103 break;
1104
1105 case 1:
1106 SET_BIT(CMU->APB1ENR, pos);
1107 break;
1108
1109 case 2:
1110 SET_BIT(CMU->APB2ENR, pos);
1111 break;
1112
1113 default:
1114 break;
1115 }
1116 }
1117 else {
1118 switch (idx) {
1119 case 0:
1120 CLEAR_BIT(CMU->AHB1ENR, pos);
1121 break;
1122
1123 case 1:
1124 CLEAR_BIT(CMU->APB1ENR, pos);
1125 break;
1126
1127 case 2:
1128 CLEAR_BIT(CMU->APB2ENR, pos);
1129 break;
1130
1131 default:
1132 break;
1133 }
1134 }
1135
1136 SYSCFG_LOCK();
1137 return;
1138 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_CMU_PERH
#define IS_CMU_PERH(x)
Definition: ald_cmu.h:631
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
CMU_PERH_ALL
Definition: ald_cmu.h:457
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_cmu_qspi_clock_select()

void ald_cmu_qspi_clock_select ( cmu_qspi_clock_sel_t clock )

Select QSPI clock source.

Parameters
clock The clock source, see cmu_qspi_clock_sel_t.
Return values
None

Definition at line 1029 of file ald_cmu.c.

1030 {
1031 assert_param(IS_CMU_QSPI_CLOCK_SEL(clock));
1032
1033 SYSCFG_UNLOCK();
1034 MODIFY_REG(CMU->PERICR, CMU_PERICR_QSPICS_MSK, clock << CMU_PERICR_QSPICS_POSS);
1035 SYSCFG_LOCK();
1036
1037 return;
1038 }
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
IS_CMU_QSPI_CLOCK_SEL
#define IS_CMU_QSPI_CLOCK_SEL(x)
Definition: ald_cmu.h:607
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39

◆ ald_cmu_stop1_clock_sel()

void ald_cmu_stop1_clock_sel ( cmu_stop1_clock_t clock )

Select stop1 clock.

Parameters
clock See cmu_stop1_clock_t
Return values
None

Definition at line 1145 of file ald_cmu.c.

1146 {
1147 assert_param(IS_CMU_STOP1_CLOCK(clock));
1148
1149 SYSCFG_UNLOCK();
1150 MODIFY_REG(CMU->LPENR, CMU_LPENR_STOP1CS_MSK, clock << CMU_LPENR_STOP1CS_POSS);
1151 SYSCFG_LOCK();
1152 return;
1153 }
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
IS_CMU_STOP1_CLOCK
#define IS_CMU_STOP1_CLOCK(x)
Definition: ald_cmu.h:693
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39

◆ ald_cmu_usb_clock_config()

void ald_cmu_usb_clock_config | ( | cmu_usb_clock_sel_t | clock,
 |  | cmu_usb_div_t | div
 | ) |  |

Configure USB clock source.

Parameters
clock | The clock source, see cmu_usb_clock_sel_t.
div | The clock division, see cmu_usb_div_t.
Return values
None

Definition at line 1046 of file ald_cmu.c.

1047 {
1048 assert_param(IS_CMU_USB_CLOCK_SEL(clock));
1049 assert_param(IS_CMU_USB_DIV(div));
1050
1051 SYSCFG_UNLOCK();
1052
1053 if (clock == CMU_USB_CLOCK_SEL_HRC)
1054 SET_BIT(SYSCFG->USBCFG, SYSCFG_USBCFG_CLKRDYBP_MSK);
1055 else
1056 CLEAR_BIT(SYSCFG->USBCFG, SYSCFG_USBCFG_CLKRDYBP_MSK);
1057
1058 MODIFY_REG(CMU->PERICR, CMU_PERICR_USBPHYCS_MSK, clock << CMU_PERICR_USBPHYCS_POSS);
1059 MODIFY_REG(CMU->PERIDIVR, CMU_PERIDIVR_USBPHYDIV_MSK, div << CMU_PERIDIVR_USBPHYDIV_POSS);
1060 SYSCFG_LOCK();
1061
1062 return;
1063 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
IS_CMU_USB_DIV
#define IS_CMU_USB_DIV(x)
Definition: ald_cmu.h:618
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_CMU_USB_CLOCK_SEL
#define IS_CMU_USB_CLOCK_SEL(x)
Definition: ald_cmu.h:613
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
CMU_USB_CLOCK_SEL_HRC
Definition: ald_cmu.h:356


ALD User Manual: CMU Public Macros

Macros
CMU Public Macros
EASTSOFT ES32F3xx ALD » CMU
Collaboration diagram for CMU Public Macros:

Macros

#define | CMU_HRC_SEL_BY_SW()
#define | CMU_HRC_SEL_BY_CFGW()
#define | CMU_HRC_DIV_1MHZ_ENABLE()
#define | CMU_HRC_DIV_1MHZ_DISABLE()
#define | CMU_HOSC_DIV_1MHZ_ENABLE()
#define | CMU_HOSC_DIV_1MHZ_DISABLE()
#define | CMU_LOSC_ENABLE()
#define | CMU_LOSC_DISABLE()
#define | CMU_LRC_ENABLE()
#define | CMU_LRC_DISABLE()
#define | CMU_ULRC_ENABLE()
#define | CMU_ULRC_DISABLE()
#define | CMU_LP_LRC_ENABLE()
#define | CMU_LP_LRC_DISABLE()
#define | CMU_LP_LOSC_ENABLE()
#define | CMU_LP_LOSC_DISABLE()
#define | CMU_LP_HRC_ENABLE()
#define | CMU_LP_HRC_DISABLE()
#define | CMU_LP_HOSC_ENABLE()
#define | CMU_LP_HOSC_DISABLE()

Detailed Description

Macro Definition Documentation

◆ CMU_HOSC_DIV_1MHZ_DISABLE

#define CMU_HOSC_DIV_1MHZ_DISABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HOSC1MEN_MSK);\
SYSCFG_LOCK(); \
} while (0)

Definition at line 69 of file ald_cmu.h.

◆ CMU_HOSC_DIV_1MHZ_ENABLE

#define CMU_HOSC_DIV_1MHZ_ENABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSC1MEN_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 63 of file ald_cmu.h.

◆ CMU_HRC_DIV_1MHZ_DISABLE

#define CMU_HRC_DIV_1MHZ_DISABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HRC1MEN_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 57 of file ald_cmu.h.

◆ CMU_HRC_DIV_1MHZ_ENABLE

#define CMU_HRC_DIV_1MHZ_ENABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
SET_BIT(CMU->CLKENR, CMU_CLKENR_HRC1MEN_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 51 of file ald_cmu.h.

◆ CMU_HRC_SEL_BY_CFGW

#define CMU_HRC_SEL_BY_CFGW ( )
Value:
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFCS_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 45 of file ald_cmu.h.

◆ CMU_HRC_SEL_BY_SW

#define CMU_HRC_SEL_BY_SW ( )
Value:
do { \
SYSCFG_UNLOCK(); \
SET_BIT(CMU->CFGR, CMU_CFGR_HRCFCS_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 39 of file ald_cmu.h.

◆ CMU_LOSC_DISABLE

#define CMU_LOSC_DISABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 81 of file ald_cmu.h.

◆ CMU_LOSC_ENABLE

#define CMU_LOSC_ENABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 75 of file ald_cmu.h.

◆ CMU_LP_HOSC_DISABLE

#define CMU_LP_HOSC_DISABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 155 of file ald_cmu.h.

◆ CMU_LP_HOSC_ENABLE

#define CMU_LP_HOSC_ENABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 149 of file ald_cmu.h.

◆ CMU_LP_HRC_DISABLE

#define CMU_LP_HRC_DISABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 143 of file ald_cmu.h.

◆ CMU_LP_HRC_ENABLE

#define CMU_LP_HRC_ENABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 137 of file ald_cmu.h.

◆ CMU_LP_LOSC_DISABLE

#define CMU_LP_LOSC_DISABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 131 of file ald_cmu.h.

◆ CMU_LP_LOSC_ENABLE

#define CMU_LP_LOSC_ENABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 125 of file ald_cmu.h.

◆ CMU_LP_LRC_DISABLE

#define CMU_LP_LRC_DISABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 119 of file ald_cmu.h.

◆ CMU_LP_LRC_ENABLE

#define CMU_LP_LRC_ENABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 113 of file ald_cmu.h.

◆ CMU_LRC_DISABLE

#define CMU_LRC_DISABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 93 of file ald_cmu.h.

◆ CMU_LRC_ENABLE

#define CMU_LRC_ENABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 87 of file ald_cmu.h.

◆ CMU_ULRC_DISABLE

#define CMU_ULRC_DISABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 105 of file ald_cmu.h.

◆ CMU_ULRC_ENABLE

#define CMU_ULRC_ENABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
SET_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 99 of file ald_cmu.h.


ALD User Manual: CMU Public Types

Enumerations
CMU Public Types
EASTSOFT ES32F3xx ALD » CMU
Collaboration diagram for CMU Public Types:

Enumerations

enum cmu_clock_t {
CMU_CLOCK_HRC = 0x1U, CMU_CLOCK_LRC = 0x2U, CMU_CLOCK_LOSC = 0x3U, CMU_CLOCK_PLL1 = 0x4U,
CMU_CLOCK_HOSC = 0x5U
}
CMU state structure definition. More...
enum | cmu_pll1_output_t { CMU_PLL1_OUTPUT_36M = 0x0U, CMU_PLL1_OUTPUT_48M = 0x1U }
PLL1 output clock. More...
enum cmu_pll1_input_t {
CMU_PLL1_INPUT_HRC_6 = 0x0U, CMU_PLL1_INPUT_PLL2 = 0x1U, CMU_PLL1_INPUT_HOSC = 0x2U, CMU_PLL1_INPUT_HOSC_2 = 0x3U,
CMU_PLL1_INPUT_HOSC_3 = 0x4U, CMU_PLL1_INPUT_HOSC_4 = 0x5U, CMU_PLL1_INPUT_HOSC_5 = 0x6U, CMU_PLL1_INPUT_HOSC_6 = 0x7U
}
PLL1 referance clock. More...
enum cmu_hosc_range_t {
CMU_HOSC_2M = 0x0U, CMU_HOSC_4M = 0x1U, CMU_HOSC_8M = 0x2U, CMU_HOSC_16M = 0x3U,
CMU_HOSC_24M = 0x4U
}
HOSC range. More...
enum | cmu_clock_safe_type_t { CMU_SAFE_CLK_HOSC = 0x0U, CMU_SAFE_CLK_LOSC = 0x1U, CMU_SAFE_CLK_PLL = 0x2U }
Safe clock source type. More...
enum cmu_div_t {
CMU_DIV_1 = 0x0U, CMU_DIV_2 = 0x1U, CMU_DIV_4 = 0x2U, CMU_DIV_8 = 0x3U,
CMU_DIV_16 = 0x4U, CMU_DIV_32 = 0x5U, CMU_DIV_64 = 0x6U, CMU_DIV_128 = 0x7U,
CMU_DIV_256 = 0x8U, CMU_DIV_512 = 0x9U, CMU_DIV_1024 = 0xAU, CMU_DIV_2048 = 0xBU,
CMU_DIV_4096 = 0xCU
}
Frequency division select bit. More...
enum cmu_bus_t {
CMU_HCLK_1 = 0x0U, CMU_HCLK_2 = 0x1U, CMU_SYS = 0x2U, CMU_PCLK_1 = 0x3U,
CMU_PCLK_2 = 0x4U
}
Bus type. More...
enum cmu_output_high_sel_t {
CMU_OUTPUT_HIGH_SEL_HOSC = 0x0U, CMU_OUTPUT_HIGH_SEL_LOSC = 0x1U, CMU_OUTPUT_HIGH_SEL_HRC = 0x2U, CMU_OUTPUT_HIGH_SEL_LRC = 0x3U,
CMU_OUTPUT_HIGH_SEL_HOSM = 0x4U, CMU_OUTPUT_HIGH_SEL_PLL1 = 0x5U, CMU_OUTPUT_HIGH_SEL_PLL2 = 0x6U, CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7U
}
Output high clock select. More...
enum cmu_output_high_div_t {
CMU_OUTPUT_DIV_1 = 0x0U, CMU_OUTPUT_DIV_2 = 0x1U, CMU_OUTPUT_DIV_4 = 0x2U, CMU_OUTPUT_DIV_8 = 0x3U,
CMU_OUTPUT_DIV_16 = 0x4U, CMU_OUTPUT_DIV_32 = 0x5U, CMU_OUTPUT_DIV_64 = 0x6U, CMU_OUTPUT_DIV_128 = 0x7U
}
Output frequency division. More...
enum cmu_output_low_sel_t {
CMU_OUTPUT_LOW_SEL_LOSC = 0x0U, CMU_OUTPUT_LOW_SEL_LRC = 0x1U, CMU_OUTPUT_LOW_SEL_LOSM = 0x2U, CMU_OUTPUT_LOW_SEL_BUZZ = 0x3U,
CMU_OUTPUT_LOW_SEL_ULRC = 0x4U
}
Output low clock select. More...
enum cmu_buzz_div_t {
CMU_BUZZ_DIV_2 = 0x0U, CMU_BUZZ_DIV_4 = 0x1U, CMU_BUZZ_DIV_8 = 0x2U, CMU_BUZZ_DIV_16 = 0x3U,
CMU_BUZZ_DIV_32 = 0x4U, CMU_BUZZ_DIV_64 = 0x5U, CMU_BUZZ_DIV_128 = 0x6U, CMU_BUZZ_DIV_256 = 0x7U
}
BUZZ frequency division. More...
enum cmu_lp_perh_clock_sel_t {
CMU_LP_PERH_CLOCK_SEL_PCLK2 = 0x0U, CMU_LP_PERH_CLOCK_SEL_PLL1 = 0x1U, CMU_LP_PERH_CLOCK_SEL_PLL2 = 0x2U, CMU_LP_PERH_CLOCK_SEL_HRC = 0x3U,
CMU_LP_PERH_CLOCK_SEL_HOSC = 0x4U, CMU_LP_PERH_CLOCK_SEL_LRC = 0x5U, CMU_LP_PERH_CLOCK_SEL_LOSC = 0x6U, CMU_LP_PERH_CLOCK_SEL_ULRC = 0x7U,
CMU_LP_PERH_CLOCK_SEL_HRC_1M = 0x8U, CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9U, CMU_LP_PERH_CLOCK_SEL_LOSM = 0xAU, CMU_LP_PERH_CLOCK_SEL_HOSM = 0xBU
}
Low power peripheral clock select. More...
enum cmu_lcd_clock_sel_t {
CMU_LCD_SEL_LOSM = 0x0U, CMU_LCD_SEL_LOSC = 0x1U, CMU_LCD_SEL_LRC = 0x2U, CMU_LCD_SEL_ULRC = 0x3U,
CMU_LCD_SEL_HRC_1M = 0x4U, CMU_LCD_SEL_HOSC_1M = 0x5U
}
LCD clock select. More...
enum cmu_qspi_clock_sel_t {
CMU_QSPI_CLOCK_SEL_PCLK1 = 0x0U, CMU_QSPI_CLOCK_SEL_HCLK2 = 0x1U, CMU_QSPI_CLOCK_SEL_HRC = 0x2U, CMU_QSPI_CLOCK_SEL_HOSC = 0x3U,
CMU_QSPI_CLOCK_SEL_PLL1 = 0x4U, CMU_QSPI_CLOCK_SEL_HOSM = 0x5U
}
QSPI clock select. More...
enum cmu_usb_clock_sel_t {
CMU_USB_CLOCK_SEL_HOSC = 0x0U, CMU_USB_CLOCK_SEL_HRC = 0x1U, CMU_USB_CLOCK_SEL_PCLK1 = 0x2U, CMU_USB_CLOCK_SEL_PLL1 = 0x3U,
CMU_USB_CLOCK_SEL_HOSM = 0x4U
}
USB clock select. More...
enum cmu_usb_div_t {
CMU_USB_DIV_1 = 0x0U, CMU_USB_DIV_2 = 0x1U, CMU_USB_DIV_4 = 0x2U, CMU_USB_DIV_8 = 0x3U,
CMU_USB_DIV_16 = 0x4U, CMU_USB_DIV_32 = 0x5U, CMU_USB_DIV_64 = 0x6U, CMU_USB_DIV_128 = 0x7U,
CMU_USB_DIV_256 = 0x8U, CMU_USB_DIV_512 = 0x9U, CMU_USB_DIV_1024 = 0xAU, CMU_USB_DIV_2048 = 0xBU,
CMU_USB_DIV_4096 = 0xCU
}
USB clock division. More...
enum cmu_perh_t {
CMU_PERH_GPIO = (1U << 0), CMU_PERH_CRC = (1U << 1), CMU_PERH_CALC = (1U << 2), CMU_PERH_CRYPT = (1U << 3),
CMU_PERH_TRNG = (1U << 4), CMU_PERH_PIS = (1U << 5), CMU_PERH_EBI = (1U << 6), CMU_PERH_QSPI_H = (1U << 7),
CMU_PERH_DMA = (1U << 8), CMU_PERH_USB = (1U << 10), CMU_PERH_ECC = (1U << 11), CMU_PERH_TIMER0 = (1U << 0) | (1U << 27),
CMU_PERH_TIMER1 = (1U << 1) | (1U << 27), CMU_PERH_TIMER2 = (1U << 2) | (1U << 27), CMU_PERH_TIMER3 = (1U << 3) | (1U << 27), CMU_PERH_TIMER4 = (1U << 4) | (1U << 27),
CMU_PERH_TIMER5 = (1U << 5) | (1U << 27), CMU_PERH_TIMER6 = (1U << 6) | (1U << 27), CMU_PERH_TIMER7 = (1U << 7) | (1U << 27), CMU_PERH_UART0 = (1U << 8) | (1U << 27),
CMU_PERH_UART1 = (1U << 9) | (1U << 27), CMU_PERH_UART2 = (1U << 10) | (1U << 27), CMU_PERH_UART3 = (1U << 11) | (1U << 27), CMU_PERH_UART4 = (1U << 12) | (1U << 27),
CMU_PERH_UART5 = (1U << 13) | (1U << 27), CMU_PERH_SPI0 = (1U << 16) | (1U << 27), CMU_PERH_SPI1 = (1U << 17) | (1U << 27), CMU_PERH_SPI2 = (1U << 18) | (1U << 27),
CMU_PERH_I2C0 = (1U << 20) | (1U << 27), CMU_PERH_I2C1 = (1U << 21) | (1U << 27), CMU_PERH_CAN = (1U << 24) | (1U << 27), CMU_PERH_QSPI_P = (1U << 25) | (1U << 27),
CMU_PERH_LPTIM0 = (1U << 0) | (1U << 28), CMU_PERH_LPUART0 = (1U << 2) | (1U << 28), CMU_PERH_ADC0 = (1U << 4) | (1U << 28), CMU_PERH_ADC1 = (1U << 5) | (1U << 28),
CMU_PERH_ACMP0 = (1U << 6) | (1U << 28), CMU_PERH_ACMP1 = (1U << 7) | (1U << 28), CMU_PERH_OPAMP = (1U << 8) | (1U << 28), CMU_PERH_DAC0 = (1U << 9) | (1U << 28),
CMU_PERH_ACMP2 = (1U << 11) | (1U << 28), CMU_PERH_WWDT = (1U << 12) | (1U << 28), CMU_PERH_LCD = (1U << 13) | (1U << 28), CMU_PERH_IWDT = (1U << 14) | (1U << 28),
CMU_PERH_RTC = (1U << 15) | (1U << 28), CMU_PERH_TSENSE = (1U << 16) | (1U << 28), CMU_PERH_BKPC = (1U << 17) | (1U << 28), CMU_PERH_DBGC = (1U << 19) | (1U << 28),
CMU_PERH_ALL = (0x7FFFFFFFU)
}
Peripheral clock enable/disable. More...
enum cmu_security_t {
CMU_LOSC_STOP = 0x0U, CMU_HOSC_STOP = 0x1U, CMU_PLL1_UNLOCK = 0x2U, CMU_LOSC_START = 0x3U,
CMU_HOSC_START = 0x4U
}
CMU interrupt type. More...
enum cmu_clock_state_t {
CMU_CLOCK_STATE_HOSCACT = (1U << 0), CMU_CLOCK_STATE_LOSCACT = (1U << 1), CMU_CLOCK_STATE_HRCACT = (1U << 2), CMU_CLOCK_STATE_LRCACT = (1U << 3),
CMU_CLOCK_STATE_ULRCACT = (1U << 4), CMU_CLOCK_STATE_PLL1ACT = (1U << 8), CMU_CLOCK_STATE_PLL2ACT = (1U << 9), CMU_CLOCK_STATE_HOSCRDY = (1U << 16),
CMU_CLOCK_STATE_LOSCRDY = (1U << 17), CMU_CLOCK_STATE_HRCRDY = (1U << 18), CMU_CLOCK_STATE_LRCRDY = (1U << 19), CMU_CLOCK_STATE_PLL1RDY = (1U << 24),
CMU_CLOCK_STATE_PLL2RDY = (1U << 25)
}
CMU clock state type. More...
enum cmu_stop1_clock_t {
CMU_STOP1_CLOCK_LRC = 0x0U, CMU_STOP1_CLOCK_HRC_24M = 0x1U, CMU_STOP1_CLOCK_HRC_2M = 0x2U, CMU_STOP1_CLOCK_HRC_1M = 0x3U,
CMU_STOP1_CLOCK_HOSC = 0x4U, CMU_STOP1_CLOCK_HOSC_1M = 0x5U, CMU_STOP1_CLOCK_HOSCM = 0x6U
}
Stop1 clock select type. More...

Detailed Description

Enumeration Type Documentation

◆ cmu_bus_t

enum cmu_bus_t

Bus type.

Enumerator
CMU_HCLK_1 | AHB1 bus
CMU_HCLK_2 | AHB2 bus
CMU_SYS | SYS bus
CMU_PCLK_1 | APB1 bus
CMU_PCLK_2 | APB2 bus

Definition at line 248 of file ald_cmu.h.

248 {
249 CMU_HCLK_1 = 0x0U,
250 CMU_HCLK_2 = 0x1U,
251 CMU_SYS = 0x2U,
252 CMU_PCLK_1 = 0x3U,
253 CMU_PCLK_2 = 0x4U,
254 } cmu_bus_t;
cmu_bus_t
cmu_bus_t
Bus type.
Definition: ald_cmu.h:248
CMU_HCLK_1
Definition: ald_cmu.h:249
CMU_HCLK_2
Definition: ald_cmu.h:250
CMU_PCLK_1
Definition: ald_cmu.h:252
CMU_PCLK_2
Definition: ald_cmu.h:253
CMU_SYS
Definition: ald_cmu.h:251

◆ cmu_buzz_div_t

enum cmu_buzz_div_t

BUZZ frequency division.

Enumerator
CMU_BUZZ_DIV_2 | Division by 2
CMU_BUZZ_DIV_4 | Division by 4
CMU_BUZZ_DIV_8 | Division by 8
CMU_BUZZ_DIV_16 | Division by 16
CMU_BUZZ_DIV_32 | Division by 32
CMU_BUZZ_DIV_64 | Division by 64
CMU_BUZZ_DIV_128 | Division by 128
CMU_BUZZ_DIV_256 | Division by 256

Definition at line 298 of file ald_cmu.h.

298 {
299 CMU_BUZZ_DIV_2 = 0x0U,
300 CMU_BUZZ_DIV_4 = 0x1U,
301 CMU_BUZZ_DIV_8 = 0x2U,
302 CMU_BUZZ_DIV_16 = 0x3U,
303 CMU_BUZZ_DIV_32 = 0x4U,
304 CMU_BUZZ_DIV_64 = 0x5U,
305 CMU_BUZZ_DIV_128 = 0x6U,
306 CMU_BUZZ_DIV_256 = 0x7U,
307 } cmu_buzz_div_t;
CMU_BUZZ_DIV_2
Definition: ald_cmu.h:299
CMU_BUZZ_DIV_256
Definition: ald_cmu.h:306
CMU_BUZZ_DIV_32
Definition: ald_cmu.h:303
CMU_BUZZ_DIV_8
Definition: ald_cmu.h:301
CMU_BUZZ_DIV_4
Definition: ald_cmu.h:300
CMU_BUZZ_DIV_64
Definition: ald_cmu.h:304
CMU_BUZZ_DIV_16
Definition: ald_cmu.h:302
CMU_BUZZ_DIV_128
Definition: ald_cmu.h:305
cmu_buzz_div_t
cmu_buzz_div_t
BUZZ frequency division.
Definition: ald_cmu.h:298

◆ cmu_clock_safe_type_t

enum cmu_clock_safe_type_t

Safe clock source type.

Enumerator
CMU_SAFE_CLK_HOSC | HOSC
CMU_SAFE_CLK_LOSC | LOSC
CMU_SAFE_CLK_PLL | PLL

Definition at line 220 of file ald_cmu.h.

220 {
221 CMU_SAFE_CLK_HOSC = 0x0U,
222 CMU_SAFE_CLK_LOSC = 0x1U,
223 CMU_SAFE_CLK_PLL = 0x2U,
224 } cmu_clock_safe_type_t;
CMU_SAFE_CLK_PLL
Definition: ald_cmu.h:223
CMU_SAFE_CLK_LOSC
Definition: ald_cmu.h:222
CMU_SAFE_CLK_HOSC
Definition: ald_cmu.h:221
cmu_clock_safe_type_t
cmu_clock_safe_type_t
Safe clock source type.
Definition: ald_cmu.h:220

◆ cmu_clock_state_t

enum cmu_clock_state_t

CMU clock state type.

Enumerator
CMU_CLOCK_STATE_HOSCACT | HOSC active
CMU_CLOCK_STATE_LOSCACT | LOSC active
CMU_CLOCK_STATE_HRCACT | HRC active
CMU_CLOCK_STATE_LRCACT | LRC active
CMU_CLOCK_STATE_ULRCACT | ULRC active
CMU_CLOCK_STATE_PLL1ACT | PLL1 active
CMU_CLOCK_STATE_PLL2ACT | PLL2 active
CMU_CLOCK_STATE_HOSCRDY | HOSC ready
CMU_CLOCK_STATE_LOSCRDY | LOSC ready
CMU_CLOCK_STATE_HRCRDY | HRC ready
CMU_CLOCK_STATE_LRCRDY | LRC ready
CMU_CLOCK_STATE_PLL1RDY | PLL1 ready
CMU_CLOCK_STATE_PLL2RDY | PLL2 ready

Definition at line 474 of file ald_cmu.h.

474 {
475 CMU_CLOCK_STATE_HOSCACT = (1U << 0),
476 CMU_CLOCK_STATE_LOSCACT = (1U << 1),
477 CMU_CLOCK_STATE_HRCACT = (1U << 2),
478 CMU_CLOCK_STATE_LRCACT = (1U << 3),
479 CMU_CLOCK_STATE_ULRCACT = (1U << 4),
480 CMU_CLOCK_STATE_PLL1ACT = (1U << 8),
481 CMU_CLOCK_STATE_PLL2ACT = (1U << 9),
482 CMU_CLOCK_STATE_HOSCRDY = (1U << 16),
483 CMU_CLOCK_STATE_LOSCRDY = (1U << 17),
484 CMU_CLOCK_STATE_HRCRDY = (1U << 18),
485 CMU_CLOCK_STATE_LRCRDY = (1U << 19),
486 CMU_CLOCK_STATE_PLL1RDY = (1U << 24),
487 CMU_CLOCK_STATE_PLL2RDY = (1U << 25),
488 } cmu_clock_state_t;
CMU_CLOCK_STATE_LRCRDY
Definition: ald_cmu.h:485
CMU_CLOCK_STATE_HRCACT
Definition: ald_cmu.h:477
CMU_CLOCK_STATE_PLL1ACT
Definition: ald_cmu.h:480
CMU_CLOCK_STATE_LOSCACT
Definition: ald_cmu.h:476
cmu_clock_state_t
cmu_clock_state_t
CMU clock state type.
Definition: ald_cmu.h:474
CMU_CLOCK_STATE_HRCRDY
Definition: ald_cmu.h:484
CMU_CLOCK_STATE_PLL1RDY
Definition: ald_cmu.h:486
CMU_CLOCK_STATE_ULRCACT
Definition: ald_cmu.h:479
CMU_CLOCK_STATE_LRCACT
Definition: ald_cmu.h:478
CMU_CLOCK_STATE_HOSCACT
Definition: ald_cmu.h:475
CMU_CLOCK_STATE_LOSCRDY
Definition: ald_cmu.h:483
CMU_CLOCK_STATE_PLL2RDY
Definition: ald_cmu.h:487
CMU_CLOCK_STATE_PLL2ACT
Definition: ald_cmu.h:481
CMU_CLOCK_STATE_HOSCRDY
Definition: ald_cmu.h:482

◆ cmu_clock_t

enum cmu_clock_t

CMU state structure definition.

Enumerator
CMU_CLOCK_HRC | HRC
CMU_CLOCK_LRC | LRC
CMU_CLOCK_LOSC | LOSC
CMU_CLOCK_PLL1 | PLL1
CMU_CLOCK_HOSC | HOSC

Definition at line 172 of file ald_cmu.h.

172 {
173 CMU_CLOCK_HRC = 0x1U,
174 CMU_CLOCK_LRC = 0x2U,
175 CMU_CLOCK_LOSC = 0x3U,
176 CMU_CLOCK_PLL1 = 0x4U,
177 CMU_CLOCK_HOSC = 0x5U,
178 } cmu_clock_t;
CMU_CLOCK_HOSC
Definition: ald_cmu.h:177
CMU_CLOCK_HRC
Definition: ald_cmu.h:173
CMU_CLOCK_LOSC
Definition: ald_cmu.h:175
cmu_clock_t
cmu_clock_t
CMU state structure definition.
Definition: ald_cmu.h:172
CMU_CLOCK_PLL1
Definition: ald_cmu.h:176
CMU_CLOCK_LRC
Definition: ald_cmu.h:174

◆ cmu_div_t

enum cmu_div_t

Frequency division select bit.

Enumerator
CMU_DIV_1 | Division by 1
CMU_DIV_2 | Division by 2
CMU_DIV_4 | Division by 4
CMU_DIV_8 | Division by 8
CMU_DIV_16 | Division by 16
CMU_DIV_32 | Division by 32
CMU_DIV_64 | Division by 64
CMU_DIV_128 | Division by 128
CMU_DIV_256 | Division by 256
CMU_DIV_512 | Division by 512
CMU_DIV_1024 | Division by 1024
CMU_DIV_2048 | Division by 2048
CMU_DIV_4096 | Division by 4096

Definition at line 229 of file ald_cmu.h.

229 {
230 CMU_DIV_1 = 0x0U,
231 CMU_DIV_2 = 0x1U,
232 CMU_DIV_4 = 0x2U,
233 CMU_DIV_8 = 0x3U,
234 CMU_DIV_16 = 0x4U,
235 CMU_DIV_32 = 0x5U,
236 CMU_DIV_64 = 0x6U,
237 CMU_DIV_128 = 0x7U,
238 CMU_DIV_256 = 0x8U,
239 CMU_DIV_512 = 0x9U,
240 CMU_DIV_1024 = 0xAU,
241 CMU_DIV_2048 = 0xBU,
242 CMU_DIV_4096 = 0xCU,
243 } cmu_div_t;
CMU_DIV_2
Definition: ald_cmu.h:231
CMU_DIV_256
Definition: ald_cmu.h:238
CMU_DIV_8
Definition: ald_cmu.h:233
CMU_DIV_4096
Definition: ald_cmu.h:242
CMU_DIV_1
Definition: ald_cmu.h:230
CMU_DIV_16
Definition: ald_cmu.h:234
CMU_DIV_512
Definition: ald_cmu.h:239
CMU_DIV_2048
Definition: ald_cmu.h:241
CMU_DIV_1024
Definition: ald_cmu.h:240
CMU_DIV_128
Definition: ald_cmu.h:237
CMU_DIV_64
Definition: ald_cmu.h:236
cmu_div_t
cmu_div_t
Frequency division select bit.
Definition: ald_cmu.h:229
CMU_DIV_4
Definition: ald_cmu.h:232
CMU_DIV_32
Definition: ald_cmu.h:235

◆ cmu_hosc_range_t

enum cmu_hosc_range_t

HOSC range.

Enumerator
CMU_HOSC_2M | 0~2MHz
CMU_HOSC_4M | 2~4MHz
CMU_HOSC_8M | 4~8MHz
CMU_HOSC_16M | 8~16MHz
CMU_HOSC_24M | 16~24MHz

Definition at line 209 of file ald_cmu.h.

209 {
210 CMU_HOSC_2M = 0x0U,
211 CMU_HOSC_4M = 0x1U,
212 CMU_HOSC_8M = 0x2U,
213 CMU_HOSC_16M = 0x3U,
214 CMU_HOSC_24M = 0x4U,
215 } cmu_hosc_range_t;
cmu_hosc_range_t
cmu_hosc_range_t
HOSC range.
Definition: ald_cmu.h:209
CMU_HOSC_4M
Definition: ald_cmu.h:211
CMU_HOSC_8M
Definition: ald_cmu.h:212
CMU_HOSC_2M
Definition: ald_cmu.h:210
CMU_HOSC_24M
Definition: ald_cmu.h:214
CMU_HOSC_16M
Definition: ald_cmu.h:213

◆ cmu_lcd_clock_sel_t

enum cmu_lcd_clock_sel_t

LCD clock select.

Enumerator
CMU_LCD_SEL_LOSM | Select LOSM
CMU_LCD_SEL_LOSC | Select LOSC
CMU_LCD_SEL_LRC | Select LRC
CMU_LCD_SEL_ULRC | Select ULRC
CMU_LCD_SEL_HRC_1M | Select HRC down to 1MHz
CMU_LCD_SEL_HOSC_1M | Select HOSC down to 1MHz

Definition at line 330 of file ald_cmu.h.

330 {
331 CMU_LCD_SEL_LOSM = 0x0U,
332 CMU_LCD_SEL_LOSC = 0x1U,
333 CMU_LCD_SEL_LRC = 0x2U,
334 CMU_LCD_SEL_ULRC = 0x3U,
335 CMU_LCD_SEL_HRC_1M = 0x4U,
336 CMU_LCD_SEL_HOSC_1M = 0x5U,
337 } cmu_lcd_clock_sel_t;
CMU_LCD_SEL_LOSM
Definition: ald_cmu.h:331
CMU_LCD_SEL_HOSC_1M
Definition: ald_cmu.h:336
CMU_LCD_SEL_LRC
Definition: ald_cmu.h:333
CMU_LCD_SEL_ULRC
Definition: ald_cmu.h:334
CMU_LCD_SEL_LOSC
Definition: ald_cmu.h:332
cmu_lcd_clock_sel_t
cmu_lcd_clock_sel_t
LCD clock select.
Definition: ald_cmu.h:330
CMU_LCD_SEL_HRC_1M
Definition: ald_cmu.h:335

◆ cmu_lp_perh_clock_sel_t

enum cmu_lp_perh_clock_sel_t

Low power peripheral clock select.

Enumerator
CMU_LP_PERH_CLOCK_SEL_PCLK2 | Select PCLK2
CMU_LP_PERH_CLOCK_SEL_PLL1 | Select PLL1
CMU_LP_PERH_CLOCK_SEL_PLL2 | Select PLL2
CMU_LP_PERH_CLOCK_SEL_HRC | Select HRC
CMU_LP_PERH_CLOCK_SEL_HOSC | Select HOSC
CMU_LP_PERH_CLOCK_SEL_LRC | Select LRC
CMU_LP_PERH_CLOCK_SEL_LOSC | Select LOSC
CMU_LP_PERH_CLOCK_SEL_ULRC | Select ULRC
CMU_LP_PERH_CLOCK_SEL_HRC_1M | Select HRC down to 1MHz
CMU_LP_PERH_CLOCK_SEL_HOSC_1M | Select HOSC down to 1MHz
CMU_LP_PERH_CLOCK_SEL_LOSM | Select LOSM
CMU_LP_PERH_CLOCK_SEL_HOSM | Select HOSM

Definition at line 312 of file ald_cmu.h.

312 {
313 CMU_LP_PERH_CLOCK_SEL_PCLK2 = 0x0U,
314 CMU_LP_PERH_CLOCK_SEL_PLL1 = 0x1U,
315 CMU_LP_PERH_CLOCK_SEL_PLL2 = 0x2U,
316 CMU_LP_PERH_CLOCK_SEL_HRC = 0x3U,
317 CMU_LP_PERH_CLOCK_SEL_HOSC = 0x4U,
318 CMU_LP_PERH_CLOCK_SEL_LRC = 0x5U,
319 CMU_LP_PERH_CLOCK_SEL_LOSC = 0x6U,
320 CMU_LP_PERH_CLOCK_SEL_ULRC = 0x7U,
321 CMU_LP_PERH_CLOCK_SEL_HRC_1M = 0x8U,
322 CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9U,
323 CMU_LP_PERH_CLOCK_SEL_LOSM = 0xAU,
324 CMU_LP_PERH_CLOCK_SEL_HOSM = 0xBU,
325 } cmu_lp_perh_clock_sel_t;
CMU_LP_PERH_CLOCK_SEL_HRC_1M
Definition: ald_cmu.h:321
CMU_LP_PERH_CLOCK_SEL_LOSC
Definition: ald_cmu.h:319
CMU_LP_PERH_CLOCK_SEL_PLL1
Definition: ald_cmu.h:314
CMU_LP_PERH_CLOCK_SEL_HOSC_1M
Definition: ald_cmu.h:322
CMU_LP_PERH_CLOCK_SEL_ULRC
Definition: ald_cmu.h:320
CMU_LP_PERH_CLOCK_SEL_PCLK2
Definition: ald_cmu.h:313
CMU_LP_PERH_CLOCK_SEL_PLL2
Definition: ald_cmu.h:315
CMU_LP_PERH_CLOCK_SEL_LOSM
Definition: ald_cmu.h:323
CMU_LP_PERH_CLOCK_SEL_HOSM
Definition: ald_cmu.h:324
cmu_lp_perh_clock_sel_t
cmu_lp_perh_clock_sel_t
Low power peripheral clock select.
Definition: ald_cmu.h:312
CMU_LP_PERH_CLOCK_SEL_HRC
Definition: ald_cmu.h:316
CMU_LP_PERH_CLOCK_SEL_LRC
Definition: ald_cmu.h:318
CMU_LP_PERH_CLOCK_SEL_HOSC
Definition: ald_cmu.h:317

◆ cmu_output_high_div_t

enum cmu_output_high_div_t

Output frequency division.

Enumerator
CMU_OUTPUT_DIV_1 | Division by 1
CMU_OUTPUT_DIV_2 | Division by 2
CMU_OUTPUT_DIV_4 | Division by 4
CMU_OUTPUT_DIV_8 | Division by 8
CMU_OUTPUT_DIV_16 | Division by 16
CMU_OUTPUT_DIV_32 | Division by 32
CMU_OUTPUT_DIV_64 | Division by 64
CMU_OUTPUT_DIV_128 | Division by 128

Definition at line 273 of file ald_cmu.h.

273 {
274 CMU_OUTPUT_DIV_1 = 0x0U,
275 CMU_OUTPUT_DIV_2 = 0x1U,
276 CMU_OUTPUT_DIV_4 = 0x2U,
277 CMU_OUTPUT_DIV_8 = 0x3U,
278 CMU_OUTPUT_DIV_16 = 0x4U,
279 CMU_OUTPUT_DIV_32 = 0x5U,
280 CMU_OUTPUT_DIV_64 = 0x6U,
281 CMU_OUTPUT_DIV_128 = 0x7U,
282 } cmu_output_high_div_t;
CMU_OUTPUT_DIV_16
Definition: ald_cmu.h:278
CMU_OUTPUT_DIV_32
Definition: ald_cmu.h:279
cmu_output_high_div_t
cmu_output_high_div_t
Output frequency division.
Definition: ald_cmu.h:273
CMU_OUTPUT_DIV_64
Definition: ald_cmu.h:280
CMU_OUTPUT_DIV_8
Definition: ald_cmu.h:277
CMU_OUTPUT_DIV_2
Definition: ald_cmu.h:275
CMU_OUTPUT_DIV_4
Definition: ald_cmu.h:276
CMU_OUTPUT_DIV_1
Definition: ald_cmu.h:274
CMU_OUTPUT_DIV_128
Definition: ald_cmu.h:281

◆ cmu_output_high_sel_t

enum cmu_output_high_sel_t

Output high clock select.

Enumerator
CMU_OUTPUT_HIGH_SEL_HOSC | Select HOSC
CMU_OUTPUT_HIGH_SEL_LOSC | Select LOSC
CMU_OUTPUT_HIGH_SEL_HRC | Select HRC
CMU_OUTPUT_HIGH_SEL_LRC | Select LRC
CMU_OUTPUT_HIGH_SEL_HOSM | Select HOSM
CMU_OUTPUT_HIGH_SEL_PLL1 | Select PLL1
CMU_OUTPUT_HIGH_SEL_PLL2 | Select PLL2
CMU_OUTPUT_HIGH_SEL_SYSCLK | Select SYSCLK

Definition at line 259 of file ald_cmu.h.

259 {
260 CMU_OUTPUT_HIGH_SEL_HOSC = 0x0U,
261 CMU_OUTPUT_HIGH_SEL_LOSC = 0x1U,
262 CMU_OUTPUT_HIGH_SEL_HRC = 0x2U,
263 CMU_OUTPUT_HIGH_SEL_LRC = 0x3U,
264 CMU_OUTPUT_HIGH_SEL_HOSM = 0x4U,
265 CMU_OUTPUT_HIGH_SEL_PLL1 = 0x5U,
266 CMU_OUTPUT_HIGH_SEL_PLL2 = 0x6U,
267 CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7U,
268 } cmu_output_high_sel_t;
CMU_OUTPUT_HIGH_SEL_HOSC
Definition: ald_cmu.h:260
cmu_output_high_sel_t
cmu_output_high_sel_t
Output high clock select.
Definition: ald_cmu.h:259
CMU_OUTPUT_HIGH_SEL_PLL1
Definition: ald_cmu.h:265
CMU_OUTPUT_HIGH_SEL_HOSM
Definition: ald_cmu.h:264
CMU_OUTPUT_HIGH_SEL_SYSCLK
Definition: ald_cmu.h:267
CMU_OUTPUT_HIGH_SEL_HRC
Definition: ald_cmu.h:262
CMU_OUTPUT_HIGH_SEL_LOSC
Definition: ald_cmu.h:261
CMU_OUTPUT_HIGH_SEL_LRC
Definition: ald_cmu.h:263
CMU_OUTPUT_HIGH_SEL_PLL2
Definition: ald_cmu.h:266

◆ cmu_output_low_sel_t

enum cmu_output_low_sel_t

Output low clock select.

Enumerator
CMU_OUTPUT_LOW_SEL_LOSC | Select LOSC
CMU_OUTPUT_LOW_SEL_LRC | Select LRC
CMU_OUTPUT_LOW_SEL_LOSM | Select LOSM
CMU_OUTPUT_LOW_SEL_BUZZ | Select BUZZ
CMU_OUTPUT_LOW_SEL_ULRC | Select ULRC

Definition at line 287 of file ald_cmu.h.

287 {
288 CMU_OUTPUT_LOW_SEL_LOSC = 0x0U,
289 CMU_OUTPUT_LOW_SEL_LRC = 0x1U,
290 CMU_OUTPUT_LOW_SEL_LOSM = 0x2U,
291 CMU_OUTPUT_LOW_SEL_BUZZ = 0x3U,
292 CMU_OUTPUT_LOW_SEL_ULRC = 0x4U,
293 } cmu_output_low_sel_t;
cmu_output_low_sel_t
cmu_output_low_sel_t
Output low clock select.
Definition: ald_cmu.h:287
CMU_OUTPUT_LOW_SEL_LOSM
Definition: ald_cmu.h:290
CMU_OUTPUT_LOW_SEL_LOSC
Definition: ald_cmu.h:288
CMU_OUTPUT_LOW_SEL_ULRC
Definition: ald_cmu.h:292
CMU_OUTPUT_LOW_SEL_BUZZ
Definition: ald_cmu.h:291
CMU_OUTPUT_LOW_SEL_LRC
Definition: ald_cmu.h:289

◆ cmu_perh_t

enum cmu_perh_t

Peripheral clock enable/disable.

  In this module, for the convenience of code maintenance,
  TIMERx is used to indicate the sequence of the timer peripheral.
  Different product series TIMERx represent different meanings:
  1. For ES32F36xx series:
  TIMER0 ----> AD16C4T0
  TIMER1 ----> AD16C4T1
  TIMER2 ----> GP32C4T0
  TIMER3 ----> GP32C4T1
  TIMER4 ----> BS16T0
  TIMER5 ----> BS16T1
  TIMER6 ----> GP16C4T0
  TIMER7 ----> GP16C4T1

  2. For ES32F393x/ES32F336x/ES32F392x series:
  TIMER0 ----> GP16C4T0
  TIMER1 ----> GP16C4T1
  TIMER2 ----> GP32C4T0
  TIMER3 ----> GP32C4T1
  TIMER4 ----> BS16T0
  TIMER5 ----> BS16T1
  TIMER6 ----> GP16C4T2
  TIMER7 ----> GP16C4T3

Enumerator
CMU_PERH_GPIO | GPIO
CMU_PERH_CRC | CRC
CMU_PERH_CALC | CALC
CMU_PERH_CRYPT | CRYPT
CMU_PERH_TRNG | TRNG
CMU_PERH_PIS | PIS
CMU_PERH_EBI | EBI
CMU_PERH_QSPI_H | QSPI AHB
CMU_PERH_DMA | DMA
CMU_PERH_USB | USB
CMU_PERH_ECC | ECC
CMU_PERH_TIMER0 | TIMER0
CMU_PERH_TIMER1 | TIMER1
CMU_PERH_TIMER2 | TIMER2
CMU_PERH_TIMER3 | TIMER3
CMU_PERH_TIMER4 | TIMER4
CMU_PERH_TIMER5 | TIMER5
CMU_PERH_TIMER6 | TIMER6
CMU_PERH_TIMER7 | TIMER7
CMU_PERH_UART0 | UART0
CMU_PERH_UART1 | UART1
CMU_PERH_UART2 | UART2
CMU_PERH_UART3 | UART3
CMU_PERH_UART4 | UART4
CMU_PERH_UART5 | UART5
CMU_PERH_SPI0 | SPI0
CMU_PERH_SPI1 | SPI1
CMU_PERH_SPI2 | SPI2
CMU_PERH_I2C0 | I2C0
CMU_PERH_I2C1 | I2C1
CMU_PERH_CAN | CAN
CMU_PERH_QSPI_P | QSPI APB
CMU_PERH_LPTIM0 | LPTIM0
CMU_PERH_LPUART0 | LPUART0
CMU_PERH_ADC0 | ADC0
CMU_PERH_ADC1 | ADC1
CMU_PERH_ACMP0 | ACMP0
CMU_PERH_ACMP1 | ACMP1
CMU_PERH_OPAMP | OPAMP
CMU_PERH_DAC0 | DAC0
CMU_PERH_ACMP2 | ACMP2
CMU_PERH_WWDT | WWDT
CMU_PERH_LCD | LCD
CMU_PERH_IWDT | IWDT
CMU_PERH_RTC | RTC
CMU_PERH_TSENSE | TSENSE
CMU_PERH_BKPC | BKPC
CMU_PERH_DBGC | DBGC
CMU_PERH_ALL | ALL

Definition at line 408 of file ald_cmu.h.

408 {
409 CMU_PERH_GPIO = (1U << 0),
410 CMU_PERH_CRC = (1U << 1),
411 CMU_PERH_CALC = (1U << 2),
412 CMU_PERH_CRYPT = (1U << 3),
413 CMU_PERH_TRNG = (1U << 4),
414 CMU_PERH_PIS = (1U << 5),
415 CMU_PERH_EBI = (1U << 6),
416 CMU_PERH_QSPI_H = (1U << 7),
417 CMU_PERH_DMA = (1U << 8),
418 CMU_PERH_USB = (1U << 10),
419 CMU_PERH_ECC = (1U << 11),
420 CMU_PERH_TIMER0 = (1U << 0) | (1U << 27),
421 CMU_PERH_TIMER1 = (1U << 1) | (1U << 27),
422 CMU_PERH_TIMER2 = (1U << 2) | (1U << 27),
423 CMU_PERH_TIMER3 = (1U << 3) | (1U << 27),
424 CMU_PERH_TIMER4 = (1U << 4) | (1U << 27),
425 CMU_PERH_TIMER5 = (1U << 5) | (1U << 27),
426 CMU_PERH_TIMER6 = (1U << 6) | (1U << 27),
427 CMU_PERH_TIMER7 = (1U << 7) | (1U << 27),
428 CMU_PERH_UART0 = (1U << 8) | (1U << 27),
429 CMU_PERH_UART1 = (1U << 9) | (1U << 27),
430 CMU_PERH_UART2 = (1U << 10) | (1U << 27),
431 CMU_PERH_UART3 = (1U << 11) | (1U << 27),
432 CMU_PERH_UART4 = (1U << 12) | (1U << 27),
433 CMU_PERH_UART5 = (1U << 13) | (1U << 27),
434 CMU_PERH_SPI0 = (1U << 16) | (1U << 27),
435 CMU_PERH_SPI1 = (1U << 17) | (1U << 27),
436 CMU_PERH_SPI2 = (1U << 18) | (1U << 27),
437 CMU_PERH_I2C0 = (1U << 20) | (1U << 27),
438 CMU_PERH_I2C1 = (1U << 21) | (1U << 27),
439 CMU_PERH_CAN = (1U << 24) | (1U << 27),
440 CMU_PERH_QSPI_P = (1U << 25) | (1U << 27),
441 CMU_PERH_LPTIM0 = (1U << 0) | (1U << 28),
442 CMU_PERH_LPUART0 = (1U << 2) | (1U << 28),
443 CMU_PERH_ADC0 = (1U << 4) | (1U << 28),
444 CMU_PERH_ADC1 = (1U << 5) | (1U << 28),
445 CMU_PERH_ACMP0 = (1U << 6) | (1U << 28),
446 CMU_PERH_ACMP1 = (1U << 7) | (1U << 28),
447 CMU_PERH_OPAMP = (1U << 8) | (1U << 28),
448 CMU_PERH_DAC0 = (1U << 9) | (1U << 28),
449 CMU_PERH_ACMP2 = (1U << 11) | (1U << 28),
450 CMU_PERH_WWDT = (1U << 12) | (1U << 28),
451 CMU_PERH_LCD = (1U << 13) | (1U << 28),
452 CMU_PERH_IWDT = (1U << 14) | (1U << 28),
453 CMU_PERH_RTC = (1U << 15) | (1U << 28),
454 CMU_PERH_TSENSE = (1U << 16) | (1U << 28),
455 CMU_PERH_BKPC = (1U << 17) | (1U << 28),
456 CMU_PERH_DBGC = (1U << 19) | (1U << 28),
457 CMU_PERH_ALL = (0x7FFFFFFFU),
458 } cmu_perh_t;
CMU_PERH_UART4
Definition: ald_cmu.h:432
CMU_PERH_EBI
Definition: ald_cmu.h:415
CMU_PERH_DBGC
Definition: ald_cmu.h:456
CMU_PERH_TIMER5
Definition: ald_cmu.h:425
CMU_PERH_LPUART0
Definition: ald_cmu.h:442
CMU_PERH_PIS
Definition: ald_cmu.h:414
CMU_PERH_TIMER4
Definition: ald_cmu.h:424
CMU_PERH_ECC
Definition: ald_cmu.h:419
CMU_PERH_CAN
Definition: ald_cmu.h:439
CMU_PERH_ACMP0
Definition: ald_cmu.h:445
CMU_PERH_IWDT
Definition: ald_cmu.h:452
CMU_PERH_TIMER6
Definition: ald_cmu.h:426
CMU_PERH_TIMER3
Definition: ald_cmu.h:423
CMU_PERH_TIMER0
Definition: ald_cmu.h:420
CMU_PERH_ADC0
Definition: ald_cmu.h:443
CMU_PERH_CALC
Definition: ald_cmu.h:411
CMU_PERH_UART5
Definition: ald_cmu.h:433
CMU_PERH_QSPI_H
Definition: ald_cmu.h:416
CMU_PERH_UART0
Definition: ald_cmu.h:428
CMU_PERH_RTC
Definition: ald_cmu.h:453
CMU_PERH_TIMER7
Definition: ald_cmu.h:427
CMU_PERH_ALL
Definition: ald_cmu.h:457
CMU_PERH_UART3
Definition: ald_cmu.h:431
CMU_PERH_ACMP1
Definition: ald_cmu.h:446
CMU_PERH_BKPC
Definition: ald_cmu.h:455
CMU_PERH_UART1
Definition: ald_cmu.h:429
CMU_PERH_TSENSE
Definition: ald_cmu.h:454
CMU_PERH_GPIO
Definition: ald_cmu.h:409
CMU_PERH_LPTIM0
Definition: ald_cmu.h:441
CMU_PERH_SPI1
Definition: ald_cmu.h:435
CMU_PERH_I2C1
Definition: ald_cmu.h:438
CMU_PERH_SPI0
Definition: ald_cmu.h:434
CMU_PERH_DAC0
Definition: ald_cmu.h:448
CMU_PERH_OPAMP
Definition: ald_cmu.h:447
CMU_PERH_USB
Definition: ald_cmu.h:418
CMU_PERH_LCD
Definition: ald_cmu.h:451
CMU_PERH_WWDT
Definition: ald_cmu.h:450
CMU_PERH_SPI2
Definition: ald_cmu.h:436
CMU_PERH_ADC1
Definition: ald_cmu.h:444
CMU_PERH_CRYPT
Definition: ald_cmu.h:412
CMU_PERH_UART2
Definition: ald_cmu.h:430
CMU_PERH_TRNG
Definition: ald_cmu.h:413
CMU_PERH_TIMER1
Definition: ald_cmu.h:421
CMU_PERH_DMA
Definition: ald_cmu.h:417
CMU_PERH_QSPI_P
Definition: ald_cmu.h:440
CMU_PERH_CRC
Definition: ald_cmu.h:410
CMU_PERH_I2C0
Definition: ald_cmu.h:437
cmu_perh_t
cmu_perh_t
Peripheral clock enable/disable.
Definition: ald_cmu.h:408
CMU_PERH_ACMP2
Definition: ald_cmu.h:449
CMU_PERH_TIMER2
Definition: ald_cmu.h:422

◆ cmu_pll1_input_t

enum cmu_pll1_input_t

PLL1 referance clock.

Enumerator
CMU_PLL1_INPUT_HRC_6 | HRC / 6
CMU_PLL1_INPUT_PLL2 | PLL2
CMU_PLL1_INPUT_HOSC | HOSC / 1
CMU_PLL1_INPUT_HOSC_2 | HOSC / 2
CMU_PLL1_INPUT_HOSC_3 | HOSC / 3
CMU_PLL1_INPUT_HOSC_4 | HOSC / 4
CMU_PLL1_INPUT_HOSC_5 | HOSC / 5
CMU_PLL1_INPUT_HOSC_6 | HOSC / 6

Definition at line 195 of file ald_cmu.h.

195 {
196 CMU_PLL1_INPUT_HRC_6 = 0x0U,
197 CMU_PLL1_INPUT_PLL2 = 0x1U,
198 CMU_PLL1_INPUT_HOSC = 0x2U,
199 CMU_PLL1_INPUT_HOSC_2 = 0x3U,
200 CMU_PLL1_INPUT_HOSC_3 = 0x4U,
201 CMU_PLL1_INPUT_HOSC_4 = 0x5U,
202 CMU_PLL1_INPUT_HOSC_5 = 0x6U,
203 CMU_PLL1_INPUT_HOSC_6 = 0x7U,
204 } cmu_pll1_input_t;
CMU_PLL1_INPUT_HOSC_2
Definition: ald_cmu.h:199
CMU_PLL1_INPUT_HRC_6
Definition: ald_cmu.h:196
CMU_PLL1_INPUT_PLL2
Definition: ald_cmu.h:197
CMU_PLL1_INPUT_HOSC_6
Definition: ald_cmu.h:203
cmu_pll1_input_t
cmu_pll1_input_t
PLL1 referance clock.
Definition: ald_cmu.h:195
CMU_PLL1_INPUT_HOSC_4
Definition: ald_cmu.h:201
CMU_PLL1_INPUT_HOSC_5
Definition: ald_cmu.h:202
CMU_PLL1_INPUT_HOSC
Definition: ald_cmu.h:198
CMU_PLL1_INPUT_HOSC_3
Definition: ald_cmu.h:200

◆ cmu_pll1_output_t

enum cmu_pll1_output_t

PLL1 output clock.

Enumerator
CMU_PLL1_OUTPUT_36M | x9 (36MHz)
CMU_PLL1_OUTPUT_48M | x12 (48MHz)

Definition at line 183 of file ald_cmu.h.

183 {
184 CMU_PLL1_OUTPUT_36M = 0x0U,
185 CMU_PLL1_OUTPUT_48M = 0x1U,
186 #if defined(ES32F36xx) || defined(ES32F39xx)
187 CMU_PLL1_OUTPUT_72M = 0x2U,
188 CMU_PLL1_OUTPUT_96M = 0x3U,
189 #endif
190 } cmu_pll1_output_t;
CMU_PLL1_OUTPUT_36M
Definition: ald_cmu.h:184
cmu_pll1_output_t
cmu_pll1_output_t
PLL1 output clock.
Definition: ald_cmu.h:183
CMU_PLL1_OUTPUT_48M
Definition: ald_cmu.h:185

◆ cmu_qspi_clock_sel_t

enum cmu_qspi_clock_sel_t

QSPI clock select.

Enumerator
CMU_QSPI_CLOCK_SEL_PCLK1 | Select PCLK1
CMU_QSPI_CLOCK_SEL_HCLK2 | Select HCLK2
CMU_QSPI_CLOCK_SEL_HRC | Select HRC
CMU_QSPI_CLOCK_SEL_HOSC | Select HOSC
CMU_QSPI_CLOCK_SEL_PLL1 | Select PLL1
CMU_QSPI_CLOCK_SEL_HOSM | Select HOSC security management

Definition at line 342 of file ald_cmu.h.

342 {
343 CMU_QSPI_CLOCK_SEL_PCLK1 = 0x0U,
344 CMU_QSPI_CLOCK_SEL_HCLK2 = 0x1U,
345 CMU_QSPI_CLOCK_SEL_HRC = 0x2U,
346 CMU_QSPI_CLOCK_SEL_HOSC = 0x3U,
347 CMU_QSPI_CLOCK_SEL_PLL1 = 0x4U,
348 CMU_QSPI_CLOCK_SEL_HOSM = 0x5U,
349 } cmu_qspi_clock_sel_t;
CMU_QSPI_CLOCK_SEL_HRC
Definition: ald_cmu.h:345
CMU_QSPI_CLOCK_SEL_HOSM
Definition: ald_cmu.h:348
CMU_QSPI_CLOCK_SEL_HOSC
Definition: ald_cmu.h:346
CMU_QSPI_CLOCK_SEL_HCLK2
Definition: ald_cmu.h:344
CMU_QSPI_CLOCK_SEL_PCLK1
Definition: ald_cmu.h:343
CMU_QSPI_CLOCK_SEL_PLL1
Definition: ald_cmu.h:347
cmu_qspi_clock_sel_t
cmu_qspi_clock_sel_t
QSPI clock select.
Definition: ald_cmu.h:342

◆ cmu_security_t

enum cmu_security_t

CMU interrupt type.

Enumerator
CMU_LOSC_STOP | LOSC STOP INTERRUPT
CMU_HOSC_STOP | HOSC STOP INTERRUPT
CMU_PLL1_UNLOCK | PLL1 UNLOCK INTERRUPT
CMU_LOSC_START | LOSC START INTERRUPT
CMU_HOSC_START | HOSC START INTERRUPT

Definition at line 463 of file ald_cmu.h.

463 {
464 CMU_LOSC_STOP = 0x0U,
465 CMU_HOSC_STOP = 0x1U,
466 CMU_PLL1_UNLOCK = 0x2U,
467 CMU_LOSC_START = 0x3U,
468 CMU_HOSC_START = 0x4U,
469 } cmu_security_t;
CMU_LOSC_STOP
Definition: ald_cmu.h:464
CMU_HOSC_START
Definition: ald_cmu.h:468
CMU_PLL1_UNLOCK
Definition: ald_cmu.h:466
cmu_security_t
cmu_security_t
CMU interrupt type.
Definition: ald_cmu.h:463
CMU_HOSC_STOP
Definition: ald_cmu.h:465
CMU_LOSC_START
Definition: ald_cmu.h:467

◆ cmu_stop1_clock_t

enum cmu_stop1_clock_t

Stop1 clock select type.

Enumerator
CMU_STOP1_CLOCK_LRC | LRC
CMU_STOP1_CLOCK_HRC_24M | HRC 24MHz
CMU_STOP1_CLOCK_HRC_2M | HRC 2MHz
CMU_STOP1_CLOCK_HRC_1M | HRC divides to 1MHz
CMU_STOP1_CLOCK_HOSC | HOSC
CMU_STOP1_CLOCK_HOSC_1M | HOSC divides to 1MHz
CMU_STOP1_CLOCK_HOSCM | HOSC security management

Definition at line 493 of file ald_cmu.h.

493 {
494 CMU_STOP1_CLOCK_LRC = 0x0U,
495 CMU_STOP1_CLOCK_HRC_24M = 0x1U,
496 CMU_STOP1_CLOCK_HRC_2M = 0x2U,
497 CMU_STOP1_CLOCK_HRC_1M = 0x3U,
498 CMU_STOP1_CLOCK_HOSC = 0x4U,
499 CMU_STOP1_CLOCK_HOSC_1M = 0x5U,
500 CMU_STOP1_CLOCK_HOSCM = 0x6U,
501 } cmu_stop1_clock_t;
CMU_STOP1_CLOCK_HRC_1M
Definition: ald_cmu.h:497
CMU_STOP1_CLOCK_LRC
Definition: ald_cmu.h:494
CMU_STOP1_CLOCK_HOSCM
Definition: ald_cmu.h:500
CMU_STOP1_CLOCK_HOSC
Definition: ald_cmu.h:498
CMU_STOP1_CLOCK_HRC_2M
Definition: ald_cmu.h:496
CMU_STOP1_CLOCK_HOSC_1M
Definition: ald_cmu.h:499
cmu_stop1_clock_t
cmu_stop1_clock_t
Stop1 clock select type.
Definition: ald_cmu.h:493
CMU_STOP1_CLOCK_HRC_24M
Definition: ald_cmu.h:495

◆ cmu_usb_clock_sel_t

enum cmu_usb_clock_sel_t

USB clock select.

Enumerator
CMU_USB_CLOCK_SEL_HOSC | Select HOSC
CMU_USB_CLOCK_SEL_HRC | Select HRC
CMU_USB_CLOCK_SEL_PCLK1 | Select PCLK1
CMU_USB_CLOCK_SEL_PLL1 | Select PLL1
CMU_USB_CLOCK_SEL_HOSM | Select HOSC security management

Definition at line 354 of file ald_cmu.h.

354 {
355 CMU_USB_CLOCK_SEL_HOSC = 0x0U,
356 CMU_USB_CLOCK_SEL_HRC = 0x1U,
357 CMU_USB_CLOCK_SEL_PCLK1 = 0x2U,
358 CMU_USB_CLOCK_SEL_PLL1 = 0x3U,
359 CMU_USB_CLOCK_SEL_HOSM = 0x4U,
360 } cmu_usb_clock_sel_t;
CMU_USB_CLOCK_SEL_HOSM
Definition: ald_cmu.h:359
cmu_usb_clock_sel_t
cmu_usb_clock_sel_t
USB clock select.
Definition: ald_cmu.h:354
CMU_USB_CLOCK_SEL_HOSC
Definition: ald_cmu.h:355
CMU_USB_CLOCK_SEL_PCLK1
Definition: ald_cmu.h:357
CMU_USB_CLOCK_SEL_PLL1
Definition: ald_cmu.h:358
CMU_USB_CLOCK_SEL_HRC
Definition: ald_cmu.h:356

◆ cmu_usb_div_t

enum cmu_usb_div_t

USB clock division.

Enumerator
CMU_USB_DIV_1 | Division by 1
CMU_USB_DIV_2 | Division by 2
CMU_USB_DIV_4 | Division by 4
CMU_USB_DIV_8 | Division by 8
CMU_USB_DIV_16 | Division by 16
CMU_USB_DIV_32 | Division by 32
CMU_USB_DIV_64 | Division by 64
CMU_USB_DIV_128 | Division by 128
CMU_USB_DIV_256 | Division by 256
CMU_USB_DIV_512 | Division by 512
CMU_USB_DIV_1024 | Division by 1024
CMU_USB_DIV_2048 | Division by 2048
CMU_USB_DIV_4096 | Division by 4096

Definition at line 365 of file ald_cmu.h.

365 {
366 CMU_USB_DIV_1 = 0x0U,
367 CMU_USB_DIV_2 = 0x1U,
368 CMU_USB_DIV_4 = 0x2U,
369 CMU_USB_DIV_8 = 0x3U,
370 CMU_USB_DIV_16 = 0x4U,
371 CMU_USB_DIV_32 = 0x5U,
372 CMU_USB_DIV_64 = 0x6U,
373 CMU_USB_DIV_128 = 0x7U,
374 CMU_USB_DIV_256 = 0x8U,
375 CMU_USB_DIV_512 = 0x9U,
376 CMU_USB_DIV_1024 = 0xAU,
377 CMU_USB_DIV_2048 = 0xBU,
378 CMU_USB_DIV_4096 = 0xCU,
379 } cmu_usb_div_t;
CMU_USB_DIV_32
Definition: ald_cmu.h:371
CMU_USB_DIV_16
Definition: ald_cmu.h:370
CMU_USB_DIV_1024
Definition: ald_cmu.h:376
cmu_usb_div_t
cmu_usb_div_t
USB clock division.
Definition: ald_cmu.h:365
CMU_USB_DIV_1
Definition: ald_cmu.h:366
CMU_USB_DIV_2048
Definition: ald_cmu.h:377
CMU_USB_DIV_512
Definition: ald_cmu.h:375
CMU_USB_DIV_64
Definition: ald_cmu.h:372
CMU_USB_DIV_2
Definition: ald_cmu.h:367
CMU_USB_DIV_8
Definition: ald_cmu.h:369
CMU_USB_DIV_256
Definition: ald_cmu.h:374
CMU_USB_DIV_4096
Definition: ald_cmu.h:378
CMU_USB_DIV_128
Definition: ald_cmu.h:373
CMU_USB_DIV_4
Definition: ald_cmu.h:368


ALD User Manual: CMU Private Macros

Macros
CMU Private Macros
EASTSOFT ES32F3xx ALD » CMU
Collaboration diagram for CMU Private Macros:

Macros

#define | IS_CMU_CLOCK(x)
#define | IS_CMU_PLL1_INPUT(x)
#define | IS_CMU_HOSC_RANGE(x)
#define | IS_CMU_DIV(x)
#define | IS_CMU_BUS(x)
#define | IS_CMU_OUTPUT_HIGH_SEL(x)
#define | IS_CMU_OUTPUT_HIGH_DIV(x)
#define | IS_CMU_OUTPUT_LOW_SEL(x)
#define | IS_CMU_SAFE_CLOCK_TYPE(x)
#define | IS_CMU_BUZZ_DIV(x)
#define | IS_CMU_LP_PERH_CLOCK_SEL(x)
#define | IS_CMU_LCD_CLOCK_SEL(x)
#define | IS_CMU_QSPI_CLOCK_SEL(x)
#define | IS_CMU_USB_CLOCK_SEL(x)
#define | IS_CMU_USB_DIV(x)
#define | IS_CMU_PERH(x)
#define | IS_CMU_CLOCK_STATE(x)
#define | IS_CMU_STOP1_CLOCK(x)

Detailed Description

Macro Definition Documentation

◆ IS_CMU_BUS

#define IS_CMU_BUS ( x )
Value:
(((x) == CMU_HCLK_1) || \
((x) == CMU_HCLK_2) || \
((x) == CMU_SYS) || \
((x) == CMU_PCLK_1) || \
((x) == CMU_PCLK_2))
CMU_HCLK_1
Definition: ald_cmu.h:249
CMU_HCLK_2
Definition: ald_cmu.h:250
CMU_PCLK_1
Definition: ald_cmu.h:252
CMU_PCLK_2
Definition: ald_cmu.h:253
CMU_SYS
Definition: ald_cmu.h:251

Definition at line 552 of file ald_cmu.h.

◆ IS_CMU_BUZZ_DIV

#define IS_CMU_BUZZ_DIV ( x )
Value:
(((x) == CMU_BUZZ_DIV_2) || \
((x) == CMU_BUZZ_DIV_4) || \
((x) == CMU_BUZZ_DIV_8) || \
((x) == CMU_BUZZ_DIV_16) || \
((x) == CMU_BUZZ_DIV_32) || \
((x) == CMU_BUZZ_DIV_64) || \
((x) == CMU_BUZZ_DIV_128) || \
((x) == CMU_BUZZ_DIV_256))
CMU_BUZZ_DIV_2
Definition: ald_cmu.h:299
CMU_BUZZ_DIV_256
Definition: ald_cmu.h:306
CMU_BUZZ_DIV_32
Definition: ald_cmu.h:303
CMU_BUZZ_DIV_8
Definition: ald_cmu.h:301
CMU_BUZZ_DIV_4
Definition: ald_cmu.h:300
CMU_BUZZ_DIV_64
Definition: ald_cmu.h:304
CMU_BUZZ_DIV_16
Definition: ald_cmu.h:302
CMU_BUZZ_DIV_128
Definition: ald_cmu.h:305

Definition at line 581 of file ald_cmu.h.

◆ IS_CMU_CLOCK

#define IS_CMU_CLOCK ( x )
Value:
(((x) == CMU_CLOCK_HRC) || \
((x) == CMU_CLOCK_LRC) || \
((x) == CMU_CLOCK_LOSC) || \
((x) == CMU_CLOCK_PLL1) || \
((x) == CMU_CLOCK_HOSC))
CMU_CLOCK_HOSC
Definition: ald_cmu.h:177
CMU_CLOCK_HRC
Definition: ald_cmu.h:173
CMU_CLOCK_LOSC
Definition: ald_cmu.h:175
CMU_CLOCK_PLL1
Definition: ald_cmu.h:176
CMU_CLOCK_LRC
Definition: ald_cmu.h:174

Definition at line 511 of file ald_cmu.h.

◆ IS_CMU_CLOCK_STATE

#define IS_CMU_CLOCK_STATE ( x )
Value:
(((x) == CMU_CLOCK_STATE_HOSCACT) || \
((x) == CMU_CLOCK_STATE_LOSCACT) || \
((x) == CMU_CLOCK_STATE_HRCACT) || \
((x) == CMU_CLOCK_STATE_LRCACT) || \
((x) == CMU_CLOCK_STATE_ULRCACT) || \
((x) == CMU_CLOCK_STATE_PLL1ACT) || \
((x) == CMU_CLOCK_STATE_PLL2ACT) || \
((x) == CMU_CLOCK_STATE_HOSCRDY) || \
((x) == CMU_CLOCK_STATE_LOSCRDY) || \
((x) == CMU_CLOCK_STATE_HRCRDY) || \
((x) == CMU_CLOCK_STATE_LRCRDY) || \
((x) == CMU_CLOCK_STATE_PLL1RDY) || \
((x) == CMU_CLOCK_STATE_PLL2RDY))
CMU_CLOCK_STATE_LRCRDY
Definition: ald_cmu.h:485
CMU_CLOCK_STATE_HRCACT
Definition: ald_cmu.h:477
CMU_CLOCK_STATE_PLL1ACT
Definition: ald_cmu.h:480
CMU_CLOCK_STATE_LOSCACT
Definition: ald_cmu.h:476
CMU_CLOCK_STATE_HRCRDY
Definition: ald_cmu.h:484
CMU_CLOCK_STATE_PLL1RDY
Definition: ald_cmu.h:486
CMU_CLOCK_STATE_ULRCACT
Definition: ald_cmu.h:479
CMU_CLOCK_STATE_LRCACT
Definition: ald_cmu.h:478
CMU_CLOCK_STATE_HOSCACT
Definition: ald_cmu.h:475
CMU_CLOCK_STATE_LOSCRDY
Definition: ald_cmu.h:483
CMU_CLOCK_STATE_PLL2RDY
Definition: ald_cmu.h:487
CMU_CLOCK_STATE_PLL2ACT
Definition: ald_cmu.h:481
CMU_CLOCK_STATE_HOSCRDY
Definition: ald_cmu.h:482

Definition at line 680 of file ald_cmu.h.

◆ IS_CMU_DIV

#define IS_CMU_DIV ( x )
Value:
(((x) == CMU_DIV_1) || \
((x) == CMU_DIV_2) || \
((x) == CMU_DIV_4) || \
((x) == CMU_DIV_8) || \
((x) == CMU_DIV_16) || \
((x) == CMU_DIV_32) || \
((x) == CMU_DIV_64) || \
((x) == CMU_DIV_128) || \
((x) == CMU_DIV_256) || \
((x) == CMU_DIV_512) || \
((x) == CMU_DIV_1024) || \
((x) == CMU_DIV_2048) || \
((x) == CMU_DIV_4096))
CMU_DIV_2
Definition: ald_cmu.h:231
CMU_DIV_256
Definition: ald_cmu.h:238
CMU_DIV_8
Definition: ald_cmu.h:233
CMU_DIV_4096
Definition: ald_cmu.h:242
CMU_DIV_1
Definition: ald_cmu.h:230
CMU_DIV_16
Definition: ald_cmu.h:234
CMU_DIV_512
Definition: ald_cmu.h:239
CMU_DIV_2048
Definition: ald_cmu.h:241
CMU_DIV_1024
Definition: ald_cmu.h:240
CMU_DIV_128
Definition: ald_cmu.h:237
CMU_DIV_64
Definition: ald_cmu.h:236
CMU_DIV_4
Definition: ald_cmu.h:232
CMU_DIV_32
Definition: ald_cmu.h:235

Definition at line 539 of file ald_cmu.h.

◆ IS_CMU_HOSC_RANGE

#define IS_CMU_HOSC_RANGE ( x )
Value:
(((x) == CMU_HOSC_2M) || \
((x) == CMU_HOSC_4M) || \
((x) == CMU_HOSC_8M) || \
((x) == CMU_HOSC_16M) || \
((x) == CMU_HOSC_24M))
CMU_HOSC_4M
Definition: ald_cmu.h:211
CMU_HOSC_8M
Definition: ald_cmu.h:212
CMU_HOSC_2M
Definition: ald_cmu.h:210
CMU_HOSC_24M
Definition: ald_cmu.h:214
CMU_HOSC_16M
Definition: ald_cmu.h:213

Definition at line 534 of file ald_cmu.h.

◆ IS_CMU_LCD_CLOCK_SEL

#define IS_CMU_LCD_CLOCK_SEL ( x )
Value:
(((x) == CMU_LCD_SEL_LOSM) || \
((x) == CMU_LCD_SEL_LOSC) || \
((x) == CMU_LCD_SEL_LRC) || \
((x) == CMU_LCD_SEL_ULRC) || \
((x) == CMU_LCD_SEL_HRC_1M) || \
((x) == CMU_LCD_SEL_HOSC_1M))
CMU_LCD_SEL_LOSM
Definition: ald_cmu.h:331
CMU_LCD_SEL_HOSC_1M
Definition: ald_cmu.h:336
CMU_LCD_SEL_LRC
Definition: ald_cmu.h:333
CMU_LCD_SEL_ULRC
Definition: ald_cmu.h:334
CMU_LCD_SEL_LOSC
Definition: ald_cmu.h:332
CMU_LCD_SEL_HRC_1M
Definition: ald_cmu.h:335

Definition at line 601 of file ald_cmu.h.

◆ IS_CMU_LP_PERH_CLOCK_SEL

#define IS_CMU_LP_PERH_CLOCK_SEL ( x )
Value:
(((x) == CMU_LP_PERH_CLOCK_SEL_PCLK2) || \
((x) == CMU_LP_PERH_CLOCK_SEL_PLL1) || \
((x) == CMU_LP_PERH_CLOCK_SEL_PLL2) || \
((x) == CMU_LP_PERH_CLOCK_SEL_HRC) || \
((x) == CMU_LP_PERH_CLOCK_SEL_HOSC) || \
((x) == CMU_LP_PERH_CLOCK_SEL_LRC) || \
((x) == CMU_LP_PERH_CLOCK_SEL_LOSC) || \
((x) == CMU_LP_PERH_CLOCK_SEL_ULRC) || \
((x) == CMU_LP_PERH_CLOCK_SEL_HRC_1M) || \
((x) == CMU_LP_PERH_CLOCK_SEL_HOSC_1M) || \
((x) == CMU_LP_PERH_CLOCK_SEL_LOSM) || \
((x) == CMU_LP_PERH_CLOCK_SEL_HOSM))
CMU_LP_PERH_CLOCK_SEL_HRC_1M
Definition: ald_cmu.h:321
CMU_LP_PERH_CLOCK_SEL_LOSC
Definition: ald_cmu.h:319
CMU_LP_PERH_CLOCK_SEL_PLL1
Definition: ald_cmu.h:314
CMU_LP_PERH_CLOCK_SEL_HOSC_1M
Definition: ald_cmu.h:322
CMU_LP_PERH_CLOCK_SEL_ULRC
Definition: ald_cmu.h:320
CMU_LP_PERH_CLOCK_SEL_PCLK2
Definition: ald_cmu.h:313
CMU_LP_PERH_CLOCK_SEL_PLL2
Definition: ald_cmu.h:315
CMU_LP_PERH_CLOCK_SEL_LOSM
Definition: ald_cmu.h:323
CMU_LP_PERH_CLOCK_SEL_HOSM
Definition: ald_cmu.h:324
CMU_LP_PERH_CLOCK_SEL_HRC
Definition: ald_cmu.h:316
CMU_LP_PERH_CLOCK_SEL_LRC
Definition: ald_cmu.h:318
CMU_LP_PERH_CLOCK_SEL_HOSC
Definition: ald_cmu.h:317

Definition at line 589 of file ald_cmu.h.

◆ IS_CMU_OUTPUT_HIGH_DIV

#define IS_CMU_OUTPUT_HIGH_DIV ( x )
Value:
(((x) == CMU_OUTPUT_DIV_1) || \
((x) == CMU_OUTPUT_DIV_2) || \
((x) == CMU_OUTPUT_DIV_4) || \
((x) == CMU_OUTPUT_DIV_8) || \
((x) == CMU_OUTPUT_DIV_16) || \
((x) == CMU_OUTPUT_DIV_32) || \
((x) == CMU_OUTPUT_DIV_64) || \
((x) == CMU_OUTPUT_DIV_128))
CMU_OUTPUT_DIV_16
Definition: ald_cmu.h:278
CMU_OUTPUT_DIV_32
Definition: ald_cmu.h:279
CMU_OUTPUT_DIV_64
Definition: ald_cmu.h:280
CMU_OUTPUT_DIV_8
Definition: ald_cmu.h:277
CMU_OUTPUT_DIV_2
Definition: ald_cmu.h:275
CMU_OUTPUT_DIV_4
Definition: ald_cmu.h:276
CMU_OUTPUT_DIV_1
Definition: ald_cmu.h:274
CMU_OUTPUT_DIV_128
Definition: ald_cmu.h:281

Definition at line 565 of file ald_cmu.h.

◆ IS_CMU_OUTPUT_HIGH_SEL

#define IS_CMU_OUTPUT_HIGH_SEL ( x )
Value:
(((x) == CMU_OUTPUT_HIGH_SEL_HOSC) || \
((x) == CMU_OUTPUT_HIGH_SEL_LOSC) || \
((x) == CMU_OUTPUT_HIGH_SEL_HRC) || \
((x) == CMU_OUTPUT_HIGH_SEL_LRC) || \
((x) == CMU_OUTPUT_HIGH_SEL_HOSM) || \
((x) == CMU_OUTPUT_HIGH_SEL_PLL1) || \
((x) == CMU_OUTPUT_HIGH_SEL_PLL2) || \
((x) == CMU_OUTPUT_HIGH_SEL_SYSCLK))
CMU_OUTPUT_HIGH_SEL_HOSC
Definition: ald_cmu.h:260
CMU_OUTPUT_HIGH_SEL_PLL1
Definition: ald_cmu.h:265
CMU_OUTPUT_HIGH_SEL_HOSM
Definition: ald_cmu.h:264
CMU_OUTPUT_HIGH_SEL_SYSCLK
Definition: ald_cmu.h:267
CMU_OUTPUT_HIGH_SEL_HRC
Definition: ald_cmu.h:262
CMU_OUTPUT_HIGH_SEL_LOSC
Definition: ald_cmu.h:261
CMU_OUTPUT_HIGH_SEL_LRC
Definition: ald_cmu.h:263
CMU_OUTPUT_HIGH_SEL_PLL2
Definition: ald_cmu.h:266

Definition at line 557 of file ald_cmu.h.

◆ IS_CMU_OUTPUT_LOW_SEL

#define IS_CMU_OUTPUT_LOW_SEL ( x )
Value:
(((x) == CMU_OUTPUT_LOW_SEL_LOSC) || \
((x) == CMU_OUTPUT_LOW_SEL_LRC ) || \
((x) == CMU_OUTPUT_LOW_SEL_LOSM) || \
((x) == CMU_OUTPUT_LOW_SEL_BUZZ) || \
((x) == CMU_OUTPUT_LOW_SEL_ULRC))
CMU_OUTPUT_LOW_SEL_LOSM
Definition: ald_cmu.h:290
CMU_OUTPUT_LOW_SEL_LOSC
Definition: ald_cmu.h:288
CMU_OUTPUT_LOW_SEL_ULRC
Definition: ald_cmu.h:292
CMU_OUTPUT_LOW_SEL_BUZZ
Definition: ald_cmu.h:291
CMU_OUTPUT_LOW_SEL_LRC
Definition: ald_cmu.h:289

Definition at line 573 of file ald_cmu.h.

◆ IS_CMU_PERH

#define IS_CMU_PERH ( x )

Definition at line 631 of file ald_cmu.h.

◆ IS_CMU_PLL1_INPUT

#define IS_CMU_PLL1_INPUT ( x )
Value:
(((x) == CMU_PLL1_INPUT_HRC_6) || \
((x) == CMU_PLL1_INPUT_PLL2) || \
((x) == CMU_PLL1_INPUT_HOSC) || \
((x) == CMU_PLL1_INPUT_HOSC_2) || \
((x) == CMU_PLL1_INPUT_HOSC_3) || \
((x) == CMU_PLL1_INPUT_HOSC_4) || \
((x) == CMU_PLL1_INPUT_HOSC_5) || \
((x) == CMU_PLL1_INPUT_HOSC_6))
CMU_PLL1_INPUT_HOSC_2
Definition: ald_cmu.h:199
CMU_PLL1_INPUT_HRC_6
Definition: ald_cmu.h:196
CMU_PLL1_INPUT_PLL2
Definition: ald_cmu.h:197
CMU_PLL1_INPUT_HOSC_6
Definition: ald_cmu.h:203
CMU_PLL1_INPUT_HOSC_4
Definition: ald_cmu.h:201
CMU_PLL1_INPUT_HOSC_5
Definition: ald_cmu.h:202
CMU_PLL1_INPUT_HOSC
Definition: ald_cmu.h:198
CMU_PLL1_INPUT_HOSC_3
Definition: ald_cmu.h:200

Definition at line 526 of file ald_cmu.h.

◆ IS_CMU_QSPI_CLOCK_SEL

#define IS_CMU_QSPI_CLOCK_SEL ( x )
Value:
(((x) == CMU_QSPI_CLOCK_SEL_PCLK1) || \
((x) == CMU_QSPI_CLOCK_SEL_HCLK2) || \
((x) == CMU_QSPI_CLOCK_SEL_HRC) || \
((x) == CMU_QSPI_CLOCK_SEL_HOSC) || \
((x) == CMU_QSPI_CLOCK_SEL_PLL1) || \
((x) == CMU_QSPI_CLOCK_SEL_HOSM))
CMU_QSPI_CLOCK_SEL_HRC
Definition: ald_cmu.h:345
CMU_QSPI_CLOCK_SEL_HOSM
Definition: ald_cmu.h:348
CMU_QSPI_CLOCK_SEL_HOSC
Definition: ald_cmu.h:346
CMU_QSPI_CLOCK_SEL_HCLK2
Definition: ald_cmu.h:344
CMU_QSPI_CLOCK_SEL_PCLK1
Definition: ald_cmu.h:343
CMU_QSPI_CLOCK_SEL_PLL1
Definition: ald_cmu.h:347

Definition at line 607 of file ald_cmu.h.

◆ IS_CMU_SAFE_CLOCK_TYPE

#define IS_CMU_SAFE_CLOCK_TYPE ( x )
Value:
(((x) == CMU_SAFE_CLK_HOSC) || \
((x) == CMU_SAFE_CLK_LOSC) || \
((x) == CMU_SAFE_CLK_PLL))
CMU_SAFE_CLK_PLL
Definition: ald_cmu.h:223
CMU_SAFE_CLK_LOSC
Definition: ald_cmu.h:222
CMU_SAFE_CLK_HOSC
Definition: ald_cmu.h:221

Definition at line 578 of file ald_cmu.h.

◆ IS_CMU_STOP1_CLOCK

#define IS_CMU_STOP1_CLOCK ( x )
Value:
(((x) == CMU_STOP1_CLOCK_LRC) || \
((x) == CMU_STOP1_CLOCK_HRC_24M) || \
((x) == CMU_STOP1_CLOCK_HRC_2M) || \
((x) == CMU_STOP1_CLOCK_HRC_1M) || \
((x) == CMU_STOP1_CLOCK_HOSC) || \
((x) == CMU_STOP1_CLOCK_HOSC_1M) || \
((x) == CMU_STOP1_CLOCK_HOSCM))
CMU_STOP1_CLOCK_HRC_1M
Definition: ald_cmu.h:497
CMU_STOP1_CLOCK_LRC
Definition: ald_cmu.h:494
CMU_STOP1_CLOCK_HOSCM
Definition: ald_cmu.h:500
CMU_STOP1_CLOCK_HOSC
Definition: ald_cmu.h:498
CMU_STOP1_CLOCK_HRC_2M
Definition: ald_cmu.h:496
CMU_STOP1_CLOCK_HOSC_1M
Definition: ald_cmu.h:499
CMU_STOP1_CLOCK_HRC_24M
Definition: ald_cmu.h:495

Definition at line 693 of file ald_cmu.h.

◆ IS_CMU_USB_CLOCK_SEL

#define IS_CMU_USB_CLOCK_SEL ( x )
Value:
(((x) == CMU_USB_CLOCK_SEL_HOSC) || \
((x) == CMU_USB_CLOCK_SEL_HRC) || \
((x) == CMU_USB_CLOCK_SEL_PCLK1) || \
((x) == CMU_USB_CLOCK_SEL_PLL1) || \
((x) == CMU_USB_CLOCK_SEL_HOSM))
CMU_USB_CLOCK_SEL_HOSM
Definition: ald_cmu.h:359
CMU_USB_CLOCK_SEL_HOSC
Definition: ald_cmu.h:355
CMU_USB_CLOCK_SEL_PCLK1
Definition: ald_cmu.h:357
CMU_USB_CLOCK_SEL_PLL1
Definition: ald_cmu.h:358
CMU_USB_CLOCK_SEL_HRC
Definition: ald_cmu.h:356

Definition at line 613 of file ald_cmu.h.

◆ IS_CMU_USB_DIV

#define IS_CMU_USB_DIV ( x )
Value:
(((x) == CMU_USB_DIV_1) || \
((x) == CMU_USB_DIV_2) || \
((x) == CMU_USB_DIV_4) || \
((x) == CMU_USB_DIV_8) || \
((x) == CMU_USB_DIV_16) || \
((x) == CMU_USB_DIV_32) || \
((x) == CMU_USB_DIV_64) || \
((x) == CMU_USB_DIV_128) || \
((x) == CMU_USB_DIV_256) || \
((x) == CMU_USB_DIV_512) || \
((x) == CMU_USB_DIV_1024) || \
((x) == CMU_USB_DIV_2048) || \
((x) == CMU_USB_DIV_4096))
CMU_USB_DIV_32
Definition: ald_cmu.h:371
CMU_USB_DIV_16
Definition: ald_cmu.h:370
CMU_USB_DIV_1024
Definition: ald_cmu.h:376
CMU_USB_DIV_1
Definition: ald_cmu.h:366
CMU_USB_DIV_2048
Definition: ald_cmu.h:377
CMU_USB_DIV_512
Definition: ald_cmu.h:375
CMU_USB_DIV_64
Definition: ald_cmu.h:372
CMU_USB_DIV_2
Definition: ald_cmu.h:367
CMU_USB_DIV_8
Definition: ald_cmu.h:369
CMU_USB_DIV_256
Definition: ald_cmu.h:374
CMU_USB_DIV_4096
Definition: ald_cmu.h:378
CMU_USB_DIV_128
Definition: ald_cmu.h:373
CMU_USB_DIV_4
Definition: ald_cmu.h:368

Definition at line 618 of file ald_cmu.h.


ALD User Manual: CRC

Modules
CRC
EASTSOFT ES32F3xx ALD

CRC module driver. More...

Collaboration diagram for CRC:

Modules

CRC Public Functions
CRC Private Functions
CRC Private functions.
CRC Public Types
CRC Public Macros
CRC Private Macros

Detailed Description

CRC module driver.


ALD User Manual: CRC Public Functions

Modules
CRC Public Functions
EASTSOFT ES32F3xx ALD » CRC
Collaboration diagram for CRC Public Functions:

Modules

Initialization functions
Initialization and Configuration functions.
Calculate functions
Calculate functions.
DMA operation functions
DMA operation functions.
Peripheral State and Errors functions
CRC State and Errors functions.

Detailed Description


ALD User Manual: Initialization functions

Functions
Initialization functions
EASTSOFT ES32F3xx ALD » CRC » CRC Public Functions

Initialization and Configuration functions. More...

Collaboration diagram for Initialization functions:

Functions

ald_status_t | ald_crc_init (crc_handle_t *hperh)
Initializes the CRC mode according to the specified parameters in the crc_handle_t and create the associated handle. More...
void | ald_crc_reset (crc_handle_t *hperh)
Reset the CRC peripheral. More...

Detailed Description

Initialization and Configuration functions.

Function Documentation

◆ ald_crc_init()

ald_status_t ald_crc_init ( crc_handle_t * hperh )

Initializes the CRC mode according to the specified parameters in the crc_handle_t and create the associated handle.

Parameters
hperh Pointer to a crc_handle_t structure that contains the configuration information for the specified CRC module.
Return values
Status,see ald_status_t.

Definition at line 58 of file ald_crc.c.

59 {
60 uint32_t tmp = 0;
61
62 if (hperh == NULL)
63 return ERROR;
64
65 assert_param(IS_CRC(hperh->perh));
66 assert_param(IS_CRC_MODE(hperh->init.mode));
67 assert_param(IS_FUNC_STATE(hperh->init.chs_rev));
68 assert_param(IS_FUNC_STATE(hperh->init.data_inv));
69 assert_param(IS_FUNC_STATE(hperh->init.data_rev));
70 assert_param(IS_FUNC_STATE(hperh->init.chs_inv));
71
72 ald_crc_reset(hperh);
73 __LOCK(hperh);
74
75 CRC_ENABLE(hperh);
76
77 tmp = hperh->perh->CR;
78
79 tmp |= ((hperh->init.chs_rev << CRC_CR_CHSREV_POS) | (hperh->init.data_inv << CRC_CR_DATREV_POS) |
80 (hperh->init.chs_inv << CRC_CR_CHSINV_POS) | (hperh->init.mode << CRC_CR_MODE_POSS) |
81 (CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS) | (hperh->init.data_rev << CRC_CR_DATREV_POS) |
82 (0 << CRC_CR_BYTORD_POS));
83
84 hperh->perh->CR = tmp;
85 hperh->perh->SEED = hperh->init.seed;
86 CRC_RESET(hperh);
87
88 hperh->state = CRC_STATE_READY;
89
90 __UNLOCK(hperh);
91 return OK;
92 }
crc_handle_s::init
crc_init_t init
Definition: ald_crc.h:94
crc_init_t::chs_inv
type_func_t chs_inv
Definition: ald_crc.h:85
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
crc_init_t::data_rev
type_func_t data_rev
Definition: ald_crc.h:82
assert_param
#define assert_param(x)
Definition: type.h:88
ald_crc_reset
void ald_crc_reset(crc_handle_t *hperh)
Reset the CRC peripheral.
Definition: ald_crc.c:458
crc_init_t::mode
crc_mode_t mode
Definition: ald_crc.h:81
IS_CRC_MODE
#define IS_CRC_MODE(x)
Definition: ald_crc.h:127
CRC_DATASIZE_8
Definition: ald_crc.h:54
CRC_RESET
#define CRC_RESET(handle)
Definition: ald_crc.h:115
crc_init_t::seed
uint32_t seed
Definition: ald_crc.h:86
crc_init_t::chs_rev
type_func_t chs_rev
Definition: ald_crc.h:84
CRC_ENABLE
#define CRC_ENABLE(handle)
Definition: ald_crc.h:113
crc_handle_s::perh
CRC_TypeDef * perh
Definition: ald_crc.h:93
crc_init_t::data_inv
type_func_t data_inv
Definition: ald_crc.h:83
crc_handle_s::state
crc_state_t state
Definition: ald_crc.h:101
__LOCK
#define __LOCK(x)
Definition: utils.h:92
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
ERROR
Definition: utils.h:56
IS_CRC
#define IS_CRC(x)
Definition: ald_crc.h:126
CRC_STATE_READY
Definition: ald_crc.h:72

◆ ald_crc_reset()

void ald_crc_reset ( crc_handle_t * hperh )

Reset the CRC peripheral.

Parameters
hperh Pointer to a crc_handle_t structure that contains the configuration information for the specified CRC module.
Return values
None

Definition at line 458 of file ald_crc.c.

459 {
460 hperh->perh->DATA = 0x0;
461 hperh->perh->CR = 0x2;
462 hperh->perh->SEED = 0xFFFFFFFF;
463
464 hperh->state = CRC_STATE_READY;
465 __UNLOCK(hperh);
466 return;
467 }
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
crc_handle_s::perh
CRC_TypeDef * perh
Definition: ald_crc.h:93
crc_handle_s::state
crc_state_t state
Definition: ald_crc.h:101
CRC_STATE_READY
Definition: ald_crc.h:72


ALD User Manual: Calculate functions

Functions
Calculate functions
EASTSOFT ES32F3xx ALD » CRC » CRC Public Functions

Calculate functions. More...

Collaboration diagram for Calculate functions:

Functions

uint32_t | ald_crc_calculate (crc_handle_t *hperh, uint8_t *buf, uint32_t size)
Calculate the crc value of data by byte. More...
uint32_t | ald_crc_calculate_halfword (crc_handle_t *hperh, uint16_t *buf, uint32_t size)
Calculate the crc value of data by halfword. More...
uint32_t | ald_crc_calculate_word (crc_handle_t *hperh, uint32_t *buf, uint32_t size)
Calculate the crc value of data by word. More...

Detailed Description

Calculate functions.

Function Documentation

◆ ald_crc_calculate()

uint32_t ald_crc_calculate | ( | crc_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint32_t | size
 | ) |  |

Calculate the crc value of data by byte.

Parameters
hperh | Pointer to a crc_handle_t structure that contains the configuration information for the specified CRC module.
buf | Pointer to data buffer
size | The size of data to be calculate
Return values
result,the result of a amount data

Definition at line 111 of file ald_crc.c.

112 {
113 uint32_t i;
114 uint32_t ret;
115
116 assert_param(IS_CRC(hperh->perh));
117
118 if (buf == NULL || size == 0)
119 return 0;
120
121 __LOCK(hperh);
122 MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS);
123 hperh->state = CRC_STATE_BUSY;
124
125 for (i = 0; i < size; i++)
126 *((volatile uint8_t *)&(hperh->perh->DATA)) = buf[i];
127
128 ret = CRC->CHECKSUM;
129 hperh->state = CRC_STATE_READY;
130 __UNLOCK(hperh);
131
132 return ret;
133 }
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
CRC_DATASIZE_8
Definition: ald_crc.h:54
CRC_STATE_BUSY
Definition: ald_crc.h:73
crc_handle_s::perh
CRC_TypeDef * perh
Definition: ald_crc.h:93
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
crc_handle_s::state
crc_state_t state
Definition: ald_crc.h:101
__LOCK
#define __LOCK(x)
Definition: utils.h:92
IS_CRC
#define IS_CRC(x)
Definition: ald_crc.h:126
CRC_STATE_READY
Definition: ald_crc.h:72

◆ ald_crc_calculate_halfword()

uint32_t ald_crc_calculate_halfword | ( | crc_handle_t * | hperh,
 |  | uint16_t * | buf,
 |  | uint32_t | size
 | ) |  |

Calculate the crc value of data by halfword.

Parameters
hperh | Pointer to a crc_handle_t structure that contains the configuration information for the specified CRC module.
buf | Pointer to data buffer
size | The size of data to be calculate,width is 2 bytes.
Return values
result,the result of a amount data

Definition at line 143 of file ald_crc.c.

144 {
145 uint32_t i;
146 uint32_t ret;
147
148 assert_param(IS_CRC(hperh->perh));
149
150 if (buf == NULL || size == 0)
151 return 0;
152
153 __LOCK(hperh);
154 MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS);
155 hperh->state = CRC_STATE_BUSY;
156
157 for (i = 0; i < size; i++)
158 *((volatile uint16_t *)&(hperh->perh->DATA)) = buf[i];
159
160 ret = CRC->CHECKSUM;
161 hperh->state = CRC_STATE_READY;
162 __UNLOCK(hperh);
163
164 return ret;
165 }
CRC_DATASIZE_16
Definition: ald_crc.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
CRC_STATE_BUSY
Definition: ald_crc.h:73
crc_handle_s::perh
CRC_TypeDef * perh
Definition: ald_crc.h:93
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
crc_handle_s::state
crc_state_t state
Definition: ald_crc.h:101
__LOCK
#define __LOCK(x)
Definition: utils.h:92
IS_CRC
#define IS_CRC(x)
Definition: ald_crc.h:126
CRC_STATE_READY
Definition: ald_crc.h:72

◆ ald_crc_calculate_word()

uint32_t ald_crc_calculate_word | ( | crc_handle_t * | hperh,
 |  | uint32_t * | buf,
 |  | uint32_t | size
 | ) |  |

Calculate the crc value of data by word.

Parameters
hperh | Pointer to a crc_handle_t structure that contains the configuration information for the specified CRC module.
buf | Pointer to data buffer
size | The size of data to be calculate,width is 4 bytes
Return values
result,the result of a amount data

Definition at line 175 of file ald_crc.c.

176 {
177 uint32_t i;
178 uint32_t ret;
179
180 assert_param(IS_CRC(hperh->perh));
181
182 if (buf == NULL || size == 0)
183 return 0;
184
185 __LOCK(hperh);
186 MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS);
187 hperh->state = CRC_STATE_BUSY;
188
189 for (i = 0; i < size; i++)
190 CRC->DATA = buf[i];
191
192 for (i = 0; i < 3; i++);
193
194 ret = CRC->CHECKSUM;
195 hperh->state = CRC_STATE_READY;
196 __UNLOCK(hperh);
197
198 return ret;
199 }
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
CRC_STATE_BUSY
Definition: ald_crc.h:73
crc_handle_s::perh
CRC_TypeDef * perh
Definition: ald_crc.h:93
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
crc_handle_s::state
crc_state_t state
Definition: ald_crc.h:101
CRC_DATASIZE_32
Definition: ald_crc.h:56
__LOCK
#define __LOCK(x)
Definition: utils.h:92
IS_CRC
#define IS_CRC(x)
Definition: ald_crc.h:126
CRC_STATE_READY
Definition: ald_crc.h:72


ALD User Manual: DMA operation functions

Functions
DMA operation functions
EASTSOFT ES32F3xx ALD » CRC » CRC Public Functions

DMA operation functions. More...

Collaboration diagram for DMA operation functions:

Functions

ald_status_t | ald_crc_calculate_by_dma (crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
Calculate an amount of data used dma channel. More...
ald_status_t | ald_crc_calculate_halfword_by_dma (crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
Calculate an amount of data used dma channel,data width is half-word. More...
ald_status_t | ald_crc_calculate_word_by_dma (crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
Calculate an amount of data used dma channel,data width is word. More...
ald_status_t | ald_crc_dma_pause (crc_handle_t *hperh)
Pauses the DMA Transfer. More...
ald_status_t | ald_crc_dma_resume (crc_handle_t *hperh)
Resumes the DMA Transfer. More...
ald_status_t | ald_crc_dma_stop (crc_handle_t *hperh)
Stops the DMA Transfer. More...

Detailed Description

DMA operation functions.

Function Documentation

◆ ald_crc_calculate_by_dma()

ald_status_t ald_crc_calculate_by_dma | ( | crc_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint32_t * | res,
 |  | uint16_t | size,
 |  | uint8_t | channel
 | ) |  |

Calculate an amount of data used dma channel.

Parameters
hperh | Pointer to a crc_handle_t structure that contains the configuration information for the specified CRC module.
buf | Pointer to data buffer
res | Pointer to result
size | Amount of data to be Calculate
channel | DMA channel as CRC transmit
Return values
Status,see ald_status_t.

Definition at line 221 of file ald_crc.c.

222 {
223 if (hperh->state != CRC_STATE_READY)
224 return BUSY;
225
226 if (buf == NULL || size == 0)
227 return ERROR;
228
229 __LOCK(hperh);
230 MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS);
231
232 hperh->state = CRC_STATE_BUSY;
233
234 hperh->cal_buf = buf;
235 hperh->cal_res = res;
236
237 if (hperh->hdma.perh == NULL)
238 hperh->hdma.perh = DMA0;
239
240 hperh->hdma.cplt_arg = (void *)hperh;
241 hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt;
242 hperh->hdma.err_arg = (void *)hperh;
243 hperh->hdma.err_cbk = &crc_dma_error;
244
245 ald_dma_config_struct(&(hperh->hdma.config));
246 hperh->hdma.config.data_width = DMA_DATA_SIZE_BYTE;
247 hperh->hdma.config.src = (void *)buf;
248 hperh->hdma.config.dst = (void *)&hperh->perh->DATA;
249 hperh->hdma.config.size = size;
250 hperh->hdma.config.src_inc = DMA_DATA_INC_BYTE;
251 hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE;
252 hperh->hdma.config.msel = DMA_MSEL_CRC;
253 hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE;
254 hperh->hdma.config.channel = channel;
255 hperh->hdma.config.burst = ENABLE;
256 ald_dma_config_basic(&(hperh->hdma));
257
258 __UNLOCK(hperh);
259 CRC_DMA_ENABLE(hperh);
260
261 return OK;
262 }
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
BUSY
Definition: utils.h:57
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
crc_dma_calculate_cplt
static void crc_dma_calculate_cplt(void *arg)
DMA CRC calculate process complete callback.
Definition: ald_crc.c:476
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
crc_handle_s::cal_buf
uint8_t * cal_buf
Definition: ald_crc.h:95
DMA_DATA_SIZE_BYTE
Definition: ald_dma.h:227
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
CRC_DMA_ENABLE
#define CRC_DMA_ENABLE(handle)
Definition: ald_crc.h:116
crc_dma_error
static void crc_dma_error(void *arg)
DMA CRC communication error callback.
Definition: ald_crc.c:495
CRC_DATASIZE_8
Definition: ald_crc.h:54
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
CRC_STATE_BUSY
Definition: ald_crc.h:73
DMA_DATA_INC_BYTE
Definition: ald_dma.h:217
crc_handle_s::cal_res
uint32_t * cal_res
Definition: ald_crc.h:96
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
crc_handle_s::perh
CRC_TypeDef * perh
Definition: ald_crc.h:93
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
DMA_MSEL_CRC
Definition: ald_dma.h:83
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
DMA_MSIGSEL_NONE
Definition: ald_dma.h:115
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
crc_handle_s::hdma
dma_handle_t hdma
Definition: ald_crc.h:98
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
crc_handle_s::state
crc_state_t state
Definition: ald_crc.h:101
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
CRC_STATE_READY
Definition: ald_crc.h:72

◆ ald_crc_calculate_halfword_by_dma()

ald_status_t ald_crc_calculate_halfword_by_dma | ( | crc_handle_t * | hperh,
 |  | uint16_t * | buf,
 |  | uint32_t * | res,
 |  | uint16_t | size,
 |  | uint8_t | channel
 | ) |  |

Calculate an amount of data used dma channel,data width is half-word.

Parameters
hperh | Pointer to a crc_handle_t structure that contains the configuration information for the specified CRC module.
buf | Pointer to half_word data buffer
res | Pointer to result
size | Amount of half_word data to be Calculate
channel | DMA channel as CRC transmit
Return values
Status,see ald_status_t.

Definition at line 274 of file ald_crc.c.

275 {
276 if (hperh->state != CRC_STATE_READY)
277 return BUSY;
278
279 if (buf == NULL || size == 0)
280 return ERROR;
281
282 __LOCK(hperh);
283 MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS);
284
285 hperh->state = CRC_STATE_BUSY;
286
287 hperh->cal_buf = (uint8_t *)buf;
288 hperh->cal_res = res;
289
290 if (hperh->hdma.perh == NULL)
291 hperh->hdma.perh = DMA0;
292
293 hperh->hdma.cplt_arg = (void *)hperh;
294 hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt;
295 hperh->hdma.err_arg = (void *)hperh;
296 hperh->hdma.err_cbk = &crc_dma_error;
297
298 ald_dma_config_struct(&(hperh->hdma.config));
299 hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD;
300 hperh->hdma.config.src = (void *)buf;
301 hperh->hdma.config.dst = (void *)&hperh->perh->DATA;
302 hperh->hdma.config.size = size;
303 hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD;
304 hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE;
305 hperh->hdma.config.msel = DMA_MSEL_CRC;
306 hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE;
307 hperh->hdma.config.channel = channel;
308 hperh->hdma.config.burst = ENABLE;
309 ald_dma_config_basic(&(hperh->hdma));
310
311 __UNLOCK(hperh);
312 CRC_DMA_ENABLE(hperh);
313
314 return OK;
315 }
CRC_DATASIZE_16
Definition: ald_crc.h:55
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
BUSY
Definition: utils.h:57
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
crc_dma_calculate_cplt
static void crc_dma_calculate_cplt(void *arg)
DMA CRC calculate process complete callback.
Definition: ald_crc.c:476
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
crc_handle_s::cal_buf
uint8_t * cal_buf
Definition: ald_crc.h:95
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
CRC_DMA_ENABLE
#define CRC_DMA_ENABLE(handle)
Definition: ald_crc.h:116
crc_dma_error
static void crc_dma_error(void *arg)
DMA CRC communication error callback.
Definition: ald_crc.c:495
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
CRC_STATE_BUSY
Definition: ald_crc.h:73
crc_handle_s::cal_res
uint32_t * cal_res
Definition: ald_crc.h:96
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
crc_handle_s::perh
CRC_TypeDef * perh
Definition: ald_crc.h:93
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
DMA_MSEL_CRC
Definition: ald_dma.h:83
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
DMA_MSIGSEL_NONE
Definition: ald_dma.h:115
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
crc_handle_s::hdma
dma_handle_t hdma
Definition: ald_crc.h:98
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
crc_handle_s::state
crc_state_t state
Definition: ald_crc.h:101
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
CRC_STATE_READY
Definition: ald_crc.h:72

◆ ald_crc_calculate_word_by_dma()

ald_status_t ald_crc_calculate_word_by_dma | ( | crc_handle_t * | hperh,
 |  | uint32_t * | buf,
 |  | uint32_t * | res,
 |  | uint16_t | size,
 |  | uint8_t | channel
 | ) |  |

Calculate an amount of data used dma channel,data width is word.

Parameters
hperh | Pointer to a crc_handle_t structure that contains the configuration information for the specified CRC module.
buf | Pointer to word data buffer
res | Pointer to result
size | Amount of word data to be Calculate
channel | DMA channel as CRC transmit
Return values
Status,see ald_status_t.

Definition at line 327 of file ald_crc.c.

328 {
329 if (hperh->state != CRC_STATE_READY)
330 return BUSY;
331
332 if (buf == NULL || size == 0)
333 return ERROR;
334
335 __LOCK(hperh);
336 MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS);
337
338 hperh->state = CRC_STATE_BUSY;
339
340 hperh->cal_buf = (uint8_t *)buf;
341 hperh->cal_res = res;
342
343 if (hperh->hdma.perh == NULL)
344 hperh->hdma.perh = DMA0;
345
346 hperh->hdma.cplt_arg = (void *)hperh;
347 hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt;
348 hperh->hdma.err_arg = (void *)hperh;
349 hperh->hdma.err_cbk = &crc_dma_error;
350
351 ald_dma_config_struct(&(hperh->hdma.config));
352 hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD;
353 hperh->hdma.config.src = (void *)buf;
354 hperh->hdma.config.dst = (void *)&hperh->perh->DATA;
355 hperh->hdma.config.size = size;
356 hperh->hdma.config.src_inc = DMA_DATA_INC_WORD;
357 hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE;
358 hperh->hdma.config.msel = DMA_MSEL_CRC;
359 hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE;
360 hperh->hdma.config.channel = channel;
361 hperh->hdma.config.burst = ENABLE;
362 ald_dma_config_basic(&(hperh->hdma));
363
364 __UNLOCK(hperh);
365 CRC_DMA_ENABLE(hperh);
366
367 return OK;
368 }
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
BUSY
Definition: utils.h:57
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
crc_dma_calculate_cplt
static void crc_dma_calculate_cplt(void *arg)
DMA CRC calculate process complete callback.
Definition: ald_crc.c:476
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
DMA_DATA_INC_WORD
Definition: ald_dma.h:219
DMA_DATA_SIZE_WORD
Definition: ald_dma.h:229
crc_handle_s::cal_buf
uint8_t * cal_buf
Definition: ald_crc.h:95
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
CRC_DMA_ENABLE
#define CRC_DMA_ENABLE(handle)
Definition: ald_crc.h:116
crc_dma_error
static void crc_dma_error(void *arg)
DMA CRC communication error callback.
Definition: ald_crc.c:495
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
CRC_STATE_BUSY
Definition: ald_crc.h:73
crc_handle_s::cal_res
uint32_t * cal_res
Definition: ald_crc.h:96
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
crc_handle_s::perh
CRC_TypeDef * perh
Definition: ald_crc.h:93
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
DMA_MSEL_CRC
Definition: ald_dma.h:83
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
DMA_MSIGSEL_NONE
Definition: ald_dma.h:115
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
crc_handle_s::hdma
dma_handle_t hdma
Definition: ald_crc.h:98
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
crc_handle_s::state
crc_state_t state
Definition: ald_crc.h:101
CRC_DATASIZE_32
Definition: ald_crc.h:56
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
CRC_STATE_READY
Definition: ald_crc.h:72

◆ ald_crc_dma_pause()

ald_status_t ald_crc_dma_pause ( crc_handle_t * hperh )

Pauses the DMA Transfer.

Parameters
hperh Pointer to a crc_handle_t structure that contains the configuration information for the specified CRC module.
Return values
Status,see ald_status_t.

Definition at line 377 of file ald_crc.c.

378 {
379 __LOCK(hperh);
380 CRC_DMA_DISABLE(hperh);
381 __UNLOCK(hperh);
382
383 return OK;
384 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CRC_DMA_DISABLE
#define CRC_DMA_DISABLE(handle)
Definition: ald_crc.h:117
__LOCK
#define __LOCK(x)
Definition: utils.h:92

◆ ald_crc_dma_resume()

ald_status_t ald_crc_dma_resume ( crc_handle_t * hperh )

Resumes the DMA Transfer.

Parameters
hperh Pointer to a crc_handle_t structure that contains the configuration information for the specified CRC module.
Return values
Status,see ald_status_t.

Definition at line 392 of file ald_crc.c.

393 {
394 __LOCK(hperh);
395 CRC_DMA_ENABLE(hperh);
396 __UNLOCK(hperh);
397
398 return OK;
399 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CRC_DMA_ENABLE
#define CRC_DMA_ENABLE(handle)
Definition: ald_crc.h:116
__LOCK
#define __LOCK(x)
Definition: utils.h:92

◆ ald_crc_dma_stop()

ald_status_t ald_crc_dma_stop ( crc_handle_t * hperh )

Stops the DMA Transfer.

Parameters
hperh Pointer to a crc_handle_t structure that contains the configuration information for the specified CRC module.
Return values
Status,see ald_status_t.

Definition at line 407 of file ald_crc.c.

408 {
409 __LOCK(hperh);
410 CRC_DMA_DISABLE(hperh);
411 __UNLOCK(hperh);
412
413 hperh->state = CRC_STATE_READY;
414 return OK;
415 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CRC_DMA_DISABLE
#define CRC_DMA_DISABLE(handle)
Definition: ald_crc.h:117
crc_handle_s::state
crc_state_t state
Definition: ald_crc.h:101
__LOCK
#define __LOCK(x)
Definition: utils.h:92
CRC_STATE_READY
Definition: ald_crc.h:72


ALD User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
EASTSOFT ES32F3xx ALD » CRC » CRC Public Functions

CRC State and Errors functions. More...

Collaboration diagram for Peripheral State and Errors functions:

Functions

crc_state_t ald_crc_get_state (crc_handle_t *hperh)
Returns the CRC state. More...

Detailed Description

CRC State and Errors functions.

Function Documentation

◆ ald_crc_get_state()

crc_state_t ald_crc_get_state ( crc_handle_t * hperh )

Returns the CRC state.

Parameters
hperh Pointer to a crc_handle_t structure that contains the configuration information for the specified CRC module.
Return values
CRC state

Definition at line 433 of file ald_crc.c.

434 {
435 assert_param(IS_CRC(hperh->perh));
436
437 return hperh->state;
438 }
assert_param
#define assert_param(x)
Definition: type.h:88
crc_handle_s::perh
CRC_TypeDef * perh
Definition: ald_crc.h:93
crc_handle_s::state
crc_state_t state
Definition: ald_crc.h:101
IS_CRC
#define IS_CRC(x)
Definition: ald_crc.h:126


ALD User Manual: CRC Private Functions

Functions
CRC Private Functions
EASTSOFT ES32F3xx ALD » CRC

CRC Private functions. More...

Collaboration diagram for CRC Private Functions:

Functions

void | ald_crc_reset (crc_handle_t *hperh)
Reset the CRC peripheral. More...
static void | crc_dma_calculate_cplt (void *arg)
DMA CRC calculate process complete callback. More...
static void | crc_dma_error (void *arg)
DMA CRC communication error callback. More...

Detailed Description

CRC Private functions.

Function Documentation

◆ ald_crc_reset()

void ald_crc_reset ( crc_handle_t * hperh )

Reset the CRC peripheral.

Parameters
hperh Pointer to a crc_handle_t structure that contains the configuration information for the specified CRC module.
Return values
None

Definition at line 458 of file ald_crc.c.

459 {
460 hperh->perh->DATA = 0x0;
461 hperh->perh->CR = 0x2;
462 hperh->perh->SEED = 0xFFFFFFFF;
463
464 hperh->state = CRC_STATE_READY;
465 __UNLOCK(hperh);
466 return;
467 }
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
crc_handle_s::perh
CRC_TypeDef * perh
Definition: ald_crc.h:93
crc_handle_s::state
crc_state_t state
Definition: ald_crc.h:101
CRC_STATE_READY
Definition: ald_crc.h:72

◆ crc_dma_calculate_cplt()

static void crc_dma_calculate_cplt ( void * arg )
static

DMA CRC calculate process complete callback.

Parameters
arg Pointer to a crc_handle_t structure that contains the configuration information for the specified CRC module.
Return values
None

Definition at line 476 of file ald_crc.c.

477 {
478 crc_handle_t *hperh = (crc_handle_t *)arg;
479
480 *(hperh->cal_res) = CRC->CHECKSUM;
481 CRC_DMA_DISABLE(hperh);
482
483 hperh->state = CRC_STATE_READY;
484
485 if (hperh->cal_cplt_cbk)
486 hperh->cal_cplt_cbk(hperh);
487 }
crc_handle_s
CRC Handle Structure definition.
Definition: ald_crc.h:92
crc_handle_s::cal_cplt_cbk
void(* cal_cplt_cbk)(struct crc_handle_s *arg)
Definition: ald_crc.h:103
CRC_DMA_DISABLE
#define CRC_DMA_DISABLE(handle)
Definition: ald_crc.h:117
crc_handle_s::cal_res
uint32_t * cal_res
Definition: ald_crc.h:96
crc_handle_s::state
crc_state_t state
Definition: ald_crc.h:101
CRC_STATE_READY
Definition: ald_crc.h:72

◆ crc_dma_error()

static void crc_dma_error ( void * arg )
static

DMA CRC communication error callback.

Parameters
arg Pointer to a crc_handle_t structure that contains the configuration information for the specified CRC module.
Return values
None

Definition at line 495 of file ald_crc.c.

496 {
497 crc_handle_t *hperh = (crc_handle_t *)arg;
498
499 CRC_CLEAR_ERROR_FLAG(hperh);
500 CRC_DMA_DISABLE(hperh);
501
502 hperh->state = CRC_STATE_READY;
503
504 if (hperh->err_cplt_cbk)
505 hperh->err_cplt_cbk(hperh);
506 }
crc_handle_s
CRC Handle Structure definition.
Definition: ald_crc.h:92
CRC_CLEAR_ERROR_FLAG
#define CRC_CLEAR_ERROR_FLAG(handle)
Definition: ald_crc.h:118
crc_handle_s::err_cplt_cbk
void(* err_cplt_cbk)(struct crc_handle_s *arg)
Definition: ald_crc.h:104
CRC_DMA_DISABLE
#define CRC_DMA_DISABLE(handle)
Definition: ald_crc.h:117
crc_handle_s::state
crc_state_t state
Definition: ald_crc.h:101
CRC_STATE_READY
Definition: ald_crc.h:72


ALD User Manual: CRC Public Types

Data Structures | Typedefs | Enumerations
CRC Public Types
EASTSOFT ES32F3xx ALD » CRC
Collaboration diagram for CRC Public Types:

Data Structures

struct | crc_init_t
CRC init structure definition. More...
struct | crc_handle_s
CRC Handle Structure definition. More...

Typedefs

typedef struct crc_handle_s crc_handle_t
CRC Handle Structure definition. More...

Enumerations

enum | crc_mode_t { CRC_MODE_CCITT = 0U, CRC_MODE_8 = 1U, CRC_MODE_16 = 2U, CRC_MODE_32 = 3U }
CRC mode. More...
enum | crc_datasize_t { CRC_LEN_AUTO = 0U, CRC_DATASIZE_8 = 1U, CRC_DATASIZE_16 = 2U, CRC_DATASIZE_32 = 3U }
CRC input length. More...
enum | crc_werr_t { CRC_WERR_NO = 0U, CRC_WERR_ERR = 1U }
CRC whether write error or no. More...
enum | crc_state_t { CRC_STATE_RESET = 0x0U, CRC_STATE_READY = 0x1U, CRC_STATE_BUSY = 0x2U, CRC_STATE_ERROR = 0x4U }
CRC state structures definition. More...

Detailed Description

Typedef Documentation

◆ crc_handle_t

typedef struct crc_handle_s crc_handle_t

CRC Handle Structure definition.

Enumeration Type Documentation

◆ crc_datasize_t

enum crc_datasize_t

CRC input length.

Enumerator
CRC_LEN_AUTO | Auto
CRC_DATASIZE_8 | Byte
CRC_DATASIZE_16 | Half word
CRC_DATASIZE_32 | Word

Definition at line 52 of file ald_crc.h.

52 {
53 CRC_LEN_AUTO = 0U,
54 CRC_DATASIZE_8 = 1U,
55 CRC_DATASIZE_16 = 2U,
56 CRC_DATASIZE_32 = 3U,
57 } crc_datasize_t;
CRC_DATASIZE_16
Definition: ald_crc.h:55
CRC_DATASIZE_8
Definition: ald_crc.h:54
CRC_LEN_AUTO
Definition: ald_crc.h:53
crc_datasize_t
crc_datasize_t
CRC input length.
Definition: ald_crc.h:52
CRC_DATASIZE_32
Definition: ald_crc.h:56

◆ crc_mode_t

enum crc_mode_t

CRC mode.

Enumerator
CRC_MODE_CCITT | Ccitt
CRC_MODE_8 | Crc8
CRC_MODE_16 | Crc16
CRC_MODE_32 | Crc32

Definition at line 42 of file ald_crc.h.

42 {
43 CRC_MODE_CCITT = 0U,
44 CRC_MODE_8 = 1U,
45 CRC_MODE_16 = 2U,
46 CRC_MODE_32 = 3U,
47 } crc_mode_t;
crc_mode_t
crc_mode_t
CRC mode.
Definition: ald_crc.h:42
CRC_MODE_8
Definition: ald_crc.h:44
CRC_MODE_16
Definition: ald_crc.h:45
CRC_MODE_CCITT
Definition: ald_crc.h:43
CRC_MODE_32
Definition: ald_crc.h:46

◆ crc_state_t

enum crc_state_t

CRC state structures definition.

Enumerator
CRC_STATE_RESET | Peripheral is not initialized
CRC_STATE_READY | Peripheral Initialized and ready for use
CRC_STATE_BUSY | An internal process is ongoing
CRC_STATE_ERROR | Error

Definition at line 70 of file ald_crc.h.

70 {
71 CRC_STATE_RESET = 0x0U,
72 CRC_STATE_READY = 0x1U,
73 CRC_STATE_BUSY = 0x2U,
74 CRC_STATE_ERROR = 0x4U,
75 } crc_state_t;
CRC_STATE_ERROR
Definition: ald_crc.h:74
CRC_STATE_RESET
Definition: ald_crc.h:71
CRC_STATE_BUSY
Definition: ald_crc.h:73
crc_state_t
crc_state_t
CRC state structures definition.
Definition: ald_crc.h:70
CRC_STATE_READY
Definition: ald_crc.h:72

◆ crc_werr_t

enum crc_werr_t

CRC whether write error or no.

Enumerator
CRC_WERR_NO | No error
CRC_WERR_ERR | Error

Definition at line 62 of file ald_crc.h.

62 {
63 CRC_WERR_NO = 0U,
64 CRC_WERR_ERR = 1U,
65 } crc_werr_t;
crc_werr_t
crc_werr_t
CRC whether write error or no.
Definition: ald_crc.h:62
CRC_WERR_ERR
Definition: ald_crc.h:64
CRC_WERR_NO
Definition: ald_crc.h:63


ALD User Manual: crc_init_t Struct Reference

Data Fields
crc_init_t Struct Reference
EASTSOFT ES32F3xx ALD » CRC » CRC Public Types

CRC init structure definition. More...

#include <ald_crc.h>

Data Fields

crc_mode_t mode
type_func_t data_rev
type_func_t data_inv
type_func_t chs_rev
type_func_t chs_inv
uint32_t seed

Detailed Description

CRC init structure definition.

Definition at line 80 of file ald_crc.h.

Field Documentation

◆ chs_inv

type_func_t chs_inv

CRC check sum inverse or no

Definition at line 85 of file ald_crc.h.

◆ chs_rev

type_func_t chs_rev

CRC check sum reverse or no

Definition at line 84 of file ald_crc.h.

◆ data_inv

type_func_t data_inv

CRC data inverse or no

Definition at line 83 of file ald_crc.h.

◆ data_rev

type_func_t data_rev

CRC data reverse or no

Definition at line 82 of file ald_crc.h.

◆ mode

crc_mode_t mode

CRC mode

Definition at line 81 of file ald_crc.h.

◆ seed

uint32_t seed

CRC seed

Definition at line 86 of file ald_crc.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_crc.h


ALD User Manual: crc_handle_s Struct Reference

Data Fields
crc_handle_s Struct Reference
EASTSOFT ES32F3xx ALD » CRC » CRC Public Types

CRC Handle Structure definition. More...

#include <ald_crc.h>

Collaboration diagram for crc_handle_s:
[legend]

Data Fields

CRC_TypeDef * | perh
crc_init_t init
uint8_t * | cal_buf
uint32_t * | cal_res
dma_handle_t hdma
lock_state_t lock
crc_state_t state
void(* | cal_cplt_cbk )(struct crc_handle_s *arg)
void(* | err_cplt_cbk )(struct crc_handle_s *arg)

Detailed Description

CRC Handle Structure definition.

Definition at line 92 of file ald_crc.h.

Field Documentation

◆ cal_buf

uint8_t* cal_buf

The pointer of preparing buffer

Definition at line 95 of file ald_crc.h.

◆ cal_cplt_cbk

void(* cal_cplt_cbk) (struct crc_handle_s *arg)

Calculate completed callback

Definition at line 103 of file ald_crc.h.

◆ cal_res

uint32_t* cal_res

The pointer of result

Definition at line 96 of file ald_crc.h.

◆ err_cplt_cbk

void(* err_cplt_cbk) (struct crc_handle_s *arg)

Calculate error callback

Definition at line 104 of file ald_crc.h.

◆ hdma

dma_handle_t hdma

CRC DMA handle parameters

Definition at line 98 of file ald_crc.h.

◆ init

crc_init_t init

CRC required parameters

Definition at line 94 of file ald_crc.h.

◆ lock

lock_state_t lock

Locking object

Definition at line 100 of file ald_crc.h.

◆ perh

CRC_TypeDef* perh

Register base address

Definition at line 93 of file ald_crc.h.

◆ state

crc_state_t state

CRC operation state

Definition at line 101 of file ald_crc.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_crc.h


ALD User Manual: CRC Public Macros

Macros
CRC Public Macros
EASTSOFT ES32F3xx ALD » CRC
Collaboration diagram for CRC Public Macros:

Macros

#define | CRC_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
#define | CRC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
#define | CRC_RESET(handle) (SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK))
#define | CRC_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
#define | CRC_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
#define | CRC_CLEAR_ERROR_FLAG(handle) (SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK))

Detailed Description

Macro Definition Documentation

◆ CRC_CLEAR_ERROR_FLAG

#define CRC_CLEAR_ERROR_FLAG ( handle ) (SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK))

Definition at line 118 of file ald_crc.h.

◆ CRC_DISABLE

#define CRC_DISABLE ( handle ) (CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK))

Definition at line 114 of file ald_crc.h.

◆ CRC_DMA_DISABLE

#define CRC_DMA_DISABLE ( handle ) (CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))

Definition at line 117 of file ald_crc.h.

◆ CRC_DMA_ENABLE

#define CRC_DMA_ENABLE ( handle ) (SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))

Definition at line 116 of file ald_crc.h.

◆ CRC_ENABLE

#define CRC_ENABLE ( handle ) (SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK))

Definition at line 113 of file ald_crc.h.

◆ CRC_RESET

#define CRC_RESET ( handle ) (SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK))

Definition at line 115 of file ald_crc.h.


ALD User Manual: CRC Private Macros

Macros
CRC Private Macros
EASTSOFT ES32F3xx ALD » CRC
Collaboration diagram for CRC Private Macros:

Macros

#define | IS_CRC(x) ((x) == CRC)
#define | IS_CRC_MODE(x)

Detailed Description

Macro Definition Documentation

◆ IS_CRC

#define IS_CRC ( x ) ((x) == CRC)

Definition at line 126 of file ald_crc.h.

◆ IS_CRC_MODE

#define IS_CRC_MODE ( x )
Value:
(((x) == CRC_MODE_CCITT) || \
((x) == CRC_MODE_8) || \
((x) == CRC_MODE_16) || \
((x) == CRC_MODE_32))
CRC_MODE_8
Definition: ald_crc.h:44
CRC_MODE_16
Definition: ald_crc.h:45
CRC_MODE_CCITT
Definition: ald_crc.h:43
CRC_MODE_32
Definition: ald_crc.h:46

Definition at line 127 of file ald_crc.h.


ALD User Manual: CRYPT

Modules
CRYPT
EASTSOFT ES32F3xx ALD

CRYPT module driver. More...

Collaboration diagram for CRYPT:

Modules

CRYPT Public Functions
CRYPT Private Functions
CRYPT Private functions.
CRYPT Public Types
CRYPT Public Macros
CRYPT Private Macros

Detailed Description

CRYPT module driver.


ALD User Manual: CRYPT Public Functions

Modules
CRYPT Public Functions
EASTSOFT ES32F3xx ALD » CRYPT
Collaboration diagram for CRYPT Public Functions:

Modules

Initialization functions
Initialization and Configuration functions.
Encrypt or Decrypt functions
Encrypt or Decrypt functions.
DMA operation functions
DMA operation functions.
Peripheral Control functions
CRYPT control functions.
Peripheral State and Errors functions
State and Errors functions.

Detailed Description


ALD User Manual: Initialization functions

Functions
Initialization functions
EASTSOFT ES32F3xx ALD » CRYPT » CRYPT Public Functions

Initialization and Configuration functions. More...

Collaboration diagram for Initialization functions:

Functions

ald_status_t | ald_crypt_init (crypt_handle_t *hperh)
Initializes the CRYPT mode according to the specified parameters in the crypt_init_t and create the associated handle. More...
ald_status_t | ald_crypt_write_key (crypt_handle_t *hperh, uint32_t *key, crypt_key_len_t len)
Write the Content of KEY. More...
ald_status_t | ald_crypt_read_key (crypt_handle_t *hperh, uint32_t *key, crypt_key_len_t len)
Read the Content of KEY. More...
ald_status_t | ald_crypt_write_ivr (crypt_handle_t *hperh, uint32_t *iv, crypt_ivr_len_t len)
Write the Content of IV if you use CBC mode. More...
ald_status_t | ald_crypt_read_ivr (crypt_handle_t *hperh, uint32_t *iv, crypt_ivr_len_t len)
Read the Content of IV. More...

Detailed Description

Initialization and Configuration functions.

Function Documentation

◆ ald_crypt_init()

ald_status_t ald_crypt_init ( crypt_handle_t * hperh )

Initializes the CRYPT mode according to the specified parameters in the crypt_init_t and create the associated handle.

Parameters
hperh Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
Return values
Status,see ald_status_t.

Definition at line 61 of file ald_crypt.c.

62 {
63 uint32_t tmp = 0;
64
65 if (hperh == NULL)
66 return ERROR;
67
68 assert_param(IS_CRYPT(hperh->perh));
69 assert_param(IS_CRYPT_MODE(hperh->init.mode));
70 assert_param(IS_CRYPT_KS(hperh->init.key));
71
72 if ((hperh->init.key == CRYPT_DES_KEYS_1 || hperh->init.key == CRYPT_DES_KEYS_2 || hperh->init.key == CRYPT_DES_KEYS_3)
73 && (hperh->init.mode == CRYPT_MODE_CTR)) {
74 return ERROR;
75 }
76
77 __LOCK(hperh);
78 crypt_reset(hperh);
79
80 if (hperh->state == CRYPT_STATE_RESET)
81 __UNLOCK(hperh);
82
83 tmp = hperh->perh->CON;
84 switch (hperh->init.key) {
85 case CRYPT_AES_BITS_128:
86 tmp |= ((CRYPT_CRYSEL_AES << CRYPT_CON_CRYSEL_POS) | \
87 (CRYPT_BITS_128 << CRYPT_CON_AESKS_POSS));
88 hperh->step = 4;
89 break;
90
91 case CRYPT_AES_BITS_192:
92 tmp |= ((CRYPT_CRYSEL_AES << CRYPT_CON_CRYSEL_POS) | \
93 (CRYPT_BITS_192 << CRYPT_CON_AESKS_POSS));
94 hperh->step = 4;
95 break;
96
97 case CRYPT_AES_BITS_256:
98 tmp |= ((CRYPT_CRYSEL_AES << CRYPT_CON_CRYSEL_POS) | \
99 (CRYPT_BITS_256 << CRYPT_CON_AESKS_POSS));
100 hperh->step = 4;
101 break;
102
103 case CRYPT_DES_KEYS_1:
104 SET_BIT(tmp, CRYPT_CON_CRYSEL_MSK);
105 hperh->step = 2;
106 break;
107
108 case CRYPT_DES_KEYS_2:
109 SET_BIT(tmp, CRYPT_CON_CRYSEL_MSK);
110 tmp |= ((1 << CRYPT_CON_TDES_POS) | (CRYPT_KEYS_2 << CRYPT_CON_DESKS_POS));
111 hperh->step = 2;
112 break;
113
114 case CRYPT_DES_KEYS_3:
115 SET_BIT(tmp, CRYPT_CON_CRYSEL_MSK);
116 tmp |= ((1 << CRYPT_CON_TDES_POS) | (CRYPT_KEYS_3 << CRYPT_CON_DESKS_POS));
117 hperh->step = 2;
118 break;
119
120 default:
121 hperh->state = CRYPT_STATE_ERROR;
122 __UNLOCK(hperh);
123 return ERROR;
124 }
125
126 tmp |= ((1 << CRYPT_CON_FIFOODR_POS) | (hperh->init.mode << CRYPT_CON_MODE_POSS) | \
127 (hperh->init.type << CRYPT_CON_TYPE_POSS) | (1 << CRYPT_CON_FIFOEN_POS));
128 hperh->perh->CON = tmp;
129
130 hperh->state = CRYPT_STATE_READY;
131 __UNLOCK(hperh);
132 return OK;
133 }
CRYPT_DES_KEYS_3
Definition: ald_crypt.h:117
crypt_init_t::key
crypt_ks_t key
Definition: ald_crypt.h:164
crypt_handle_s::step
uint32_t step
Definition: ald_crypt.h:181
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
crypt_init_t::mode
crypt_mode_t mode
Definition: ald_crypt.h:162
assert_param
#define assert_param(x)
Definition: type.h:88
CRYPT_STATE_RESET
Definition: ald_crypt.h:124
CRYPT_BITS_128
Definition: ald_crypt.h:51
CRYPT_KEYS_2
Definition: ald_crypt.h:79
crypt_handle_s::state
crypt_state_t state
Definition: ald_crypt.h:188
CRYPT_BITS_192
Definition: ald_crypt.h:52
crypt_reset
void crypt_reset(crypt_handle_t *hperh)
Reset the CRYPT peripheral.
Definition: ald_crypt.c:1069
CRYPT_STATE_ERROR
Definition: ald_crypt.h:127
crypt_handle_s::perh
CRYPT_TypeDef * perh
Definition: ald_crypt.h:171
IS_CRYPT
#define IS_CRYPT(x)
Definition: ald_crypt.h:220
crypt_handle_s::init
crypt_init_t init
Definition: ald_crypt.h:172
CRYPT_STATE_READY
Definition: ald_crypt.h:125
CRYPT_AES_BITS_128
Definition: ald_crypt.h:112
CRYPT_AES_BITS_256
Definition: ald_crypt.h:114
CRYPT_MODE_CTR
Definition: ald_crypt.h:62
CRYPT_AES_BITS_192
Definition: ald_crypt.h:113
crypt_init_t::type
crypt_data_t type
Definition: ald_crypt.h:163
IS_CRYPT_KS
#define IS_CRYPT_KS(x)
Definition: ald_crypt.h:224
CRYPT_KEYS_3
Definition: ald_crypt.h:80
CRYPT_CRYSEL_AES
Definition: ald_crypt.h:88
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_CRYPT_MODE
#define IS_CRYPT_MODE(x)
Definition: ald_crypt.h:221
CRYPT_BITS_256
Definition: ald_crypt.h:53
CRYPT_DES_KEYS_2
Definition: ald_crypt.h:116
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
CRYPT_DES_KEYS_1
Definition: ald_crypt.h:115

◆ ald_crypt_read_ivr()

ald_status_t ald_crypt_read_ivr | ( | crypt_handle_t * | hperh,
 |  | uint32_t * | iv,
 |  | crypt_ivr_len_t | len
 | ) |  |

Read the Content of IV.

Parameters
hperh | Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
iv | Pointer to iv data buffer
len | the length of iv(32 bits)
Return values
Status,see ald_status_t.

Definition at line 319 of file ald_crypt.c.

320 {
321 uint32_t *temp = iv;
322
323 if ((hperh == NULL) || (iv == NULL))
324 return ERROR;
325 if (hperh->state == CRYPT_STATE_BUSY)
326 return BUSY;
327
328 assert_param(IS_CRYPT(hperh->perh));
329 assert_param(IS_CRYPT_IV_LEN(len));
330
331 switch (len) {
332 case IV_4_LEN:
333 *temp++ = hperh->perh->IV[3];
334 *temp++ = hperh->perh->IV[2];
335 *temp++ = hperh->perh->IV[1];
336 *temp = hperh->perh->IV[0];
337 break;
338
339 case IV_2_LEN:
340 *temp++ = hperh->perh->IV[1];
341 *temp = hperh->perh->IV[0];
342 break;
343
344 default:
345 break;
346 }
347
348 return OK;
349 }
IV_2_LEN
Definition: ald_crypt.h:144
IV_4_LEN
Definition: ald_crypt.h:145
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
crypt_handle_s::state
crypt_state_t state
Definition: ald_crypt.h:188
IS_CRYPT_IV_LEN
#define IS_CRYPT_IV_LEN(x)
Definition: ald_crypt.h:234
CRYPT_STATE_BUSY
Definition: ald_crypt.h:126
crypt_handle_s::perh
CRYPT_TypeDef * perh
Definition: ald_crypt.h:171
IS_CRYPT
#define IS_CRYPT(x)
Definition: ald_crypt.h:220
ERROR
Definition: utils.h:56

◆ ald_crypt_read_key()

ald_status_t ald_crypt_read_key | ( | crypt_handle_t * | hperh,
 |  | uint32_t * | key,
 |  | crypt_key_len_t | len
 | ) |  |

Read the Content of KEY.

Parameters
hperh | Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
key | Pointer to key data buffer
len | The length of key(32 bits)
Return values
Status,see ald_status_t.

Definition at line 212 of file ald_crypt.c.

213 {
214 uint32_t *temp = key;
215
216 if ((hperh == NULL) || (key == NULL))
217 return ERROR;
218 if (hperh->state == CRYPT_STATE_BUSY)
219 return BUSY;
220
221 assert_param(IS_CRYPT(hperh->perh));
222 assert_param(IS_CRYPT_KEY_LEN(len));
223
224 switch (len) {
225 case KEY_8_LEN:
226 *temp++ = hperh->perh->KEY[7];
227 *temp++ = hperh->perh->KEY[6];
228 *temp++ = hperh->perh->KEY[5];
229 *temp++ = hperh->perh->KEY[4];
230 *temp++ = hperh->perh->KEY[3];
231 *temp++ = hperh->perh->KEY[2];
232 *temp++ = hperh->perh->KEY[1];
233 *temp = hperh->perh->KEY[0];
234 break;
235
236 case KEY_6_LEN:
237 *temp++ = hperh->perh->KEY[5];
238 *temp++ = hperh->perh->KEY[4];
239 *temp++ = hperh->perh->KEY[3];
240 *temp++ = hperh->perh->KEY[2];
241 *temp++ = hperh->perh->KEY[1];
242 *temp = hperh->perh->KEY[0];
243 break;
244
245 case KEY_4_LEN:
246 *temp++ = hperh->perh->KEY[3];
247 *temp++ = hperh->perh->KEY[2];
248 *temp++ = hperh->perh->KEY[1];
249 *temp = hperh->perh->KEY[0];
250 break;
251
252 case KEY_2_LEN:
253 *temp++ = hperh->perh->KEY[1];
254 *temp = hperh->perh->KEY[0];
255 break;
256
257 default:
258 break;
259 }
260
261 return OK;
262 }
KEY_6_LEN
Definition: ald_crypt.h:136
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
crypt_handle_s::state
crypt_state_t state
Definition: ald_crypt.h:188
CRYPT_STATE_BUSY
Definition: ald_crypt.h:126
crypt_handle_s::perh
CRYPT_TypeDef * perh
Definition: ald_crypt.h:171
IS_CRYPT
#define IS_CRYPT(x)
Definition: ald_crypt.h:220
KEY_8_LEN
Definition: ald_crypt.h:137
IS_CRYPT_KEY_LEN
#define IS_CRYPT_KEY_LEN(x)
Definition: ald_crypt.h:236
KEY_4_LEN
Definition: ald_crypt.h:135
KEY_2_LEN
Definition: ald_crypt.h:134
ERROR
Definition: utils.h:56

◆ ald_crypt_write_ivr()

ald_status_t ald_crypt_write_ivr | ( | crypt_handle_t * | hperh,
 |  | uint32_t * | iv,
 |  | crypt_ivr_len_t | len
 | ) |  |

Write the Content of IV if you use CBC mode.

Parameters
hperh | Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
iv | Pointer to iv data buffer
len | the length of iv(32 bits)
Return values
Status,see ald_status_t.

Definition at line 272 of file ald_crypt.c.

273 {
274 uint32_t *temp = iv;
275 uint32_t i;
276
277 if ((hperh == NULL) || (iv == NULL))
278 return ERROR;
279 if (hperh->state == CRYPT_STATE_BUSY)
280 return BUSY;
281
282 assert_param(IS_CRYPT(hperh->perh));
283 assert_param(IS_CRYPT_IV_LEN(len));
284
285 switch (len) {
286 case IV_4_LEN:
287 hperh->perh->IV[3] = *temp++;
288 hperh->perh->IV[2] = *temp++;
289 hperh->perh->IV[1] = *temp++;
290 hperh->perh->IV[0] = *temp;
291 break;
292
293 case IV_2_LEN:
294 hperh->perh->IV[1] = *temp++;
295 hperh->perh->IV[0] = *temp;
296 break;
297
298 default:
299 break;
300 }
301
302 for (i = 0; i < len; i++)
303 hperh->iv[i] = *iv++;
304
305 hperh->iv_size = len;
306
307 CRYPT_IVEN_ENABLE(hperh);
308 return OK;
309 }
IV_2_LEN
Definition: ald_crypt.h:144
IV_4_LEN
Definition: ald_crypt.h:145
crypt_handle_s::iv_size
uint32_t iv_size
Definition: ald_crypt.h:184
OK
Definition: utils.h:55
crypt_handle_s::iv
uint32_t iv[4]
Definition: ald_crypt.h:183
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
crypt_handle_s::state
crypt_state_t state
Definition: ald_crypt.h:188
IS_CRYPT_IV_LEN
#define IS_CRYPT_IV_LEN(x)
Definition: ald_crypt.h:234
CRYPT_STATE_BUSY
Definition: ald_crypt.h:126
crypt_handle_s::perh
CRYPT_TypeDef * perh
Definition: ald_crypt.h:171
IS_CRYPT
#define IS_CRYPT(x)
Definition: ald_crypt.h:220
ERROR
Definition: utils.h:56
CRYPT_IVEN_ENABLE
#define CRYPT_IVEN_ENABLE(handle)
Definition: ald_crypt.h:203

◆ ald_crypt_write_key()

ald_status_t ald_crypt_write_key | ( | crypt_handle_t * | hperh,
 |  | uint32_t * | key,
 |  | crypt_key_len_t | len
 | ) |  |

Write the Content of KEY.

Parameters
hperh | Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
key | Pointer to key data buffer
len | The length of key(32 bits)
Return values
Status,see ald_status_t.

Definition at line 143 of file ald_crypt.c.

144 {
145 uint32_t *temp = key;
146 uint32_t i;
147
148 if ((hperh == NULL) || (key == NULL))
149 return ERROR;
150 if (hperh->state == CRYPT_STATE_BUSY)
151 return BUSY;
152
153 assert_param(IS_CRYPT(hperh->perh));
154 assert_param(IS_CRYPT_KEY_LEN(len));
155
156 if ((hperh->init.key & 0xF) != len)
157 return ERROR;
158
159 switch (len) {
160 case KEY_8_LEN:
161 hperh->perh->KEY[7] = *temp++;
162 hperh->perh->KEY[6] = *temp++;
163 hperh->perh->KEY[5] = *temp++;
164 hperh->perh->KEY[4] = *temp++;
165 hperh->perh->KEY[3] = *temp++;
166 hperh->perh->KEY[2] = *temp++;
167 hperh->perh->KEY[1] = *temp++;
168 hperh->perh->KEY[0] = *temp;
169 break;
170
171 case KEY_6_LEN:
172 hperh->perh->KEY[5] = *temp++;
173 hperh->perh->KEY[4] = *temp++;
174 hperh->perh->KEY[3] = *temp++;
175 hperh->perh->KEY[2] = *temp++;
176 hperh->perh->KEY[1] = *temp++;
177 hperh->perh->KEY[0] = *temp;
178 break;
179
180 case KEY_4_LEN:
181 hperh->perh->KEY[3] = *temp++;
182 hperh->perh->KEY[2] = *temp++;
183 hperh->perh->KEY[1] = *temp++;
184 hperh->perh->KEY[0] = *temp;
185 break;
186
187 case KEY_2_LEN:
188 hperh->perh->KEY[1] = *temp++;
189 hperh->perh->KEY[0] = *temp;
190 break;
191
192 default:
193 break;
194 }
195
196 for (i = 0; i < len; i++)
197 hperh->key[i] = *key++;
198
199 hperh->key_size = len;
200
201 return OK;
202 }
crypt_init_t::key
crypt_ks_t key
Definition: ald_crypt.h:164
KEY_6_LEN
Definition: ald_crypt.h:136
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
crypt_handle_s::state
crypt_state_t state
Definition: ald_crypt.h:188
CRYPT_STATE_BUSY
Definition: ald_crypt.h:126
crypt_handle_s::perh
CRYPT_TypeDef * perh
Definition: ald_crypt.h:171
IS_CRYPT
#define IS_CRYPT(x)
Definition: ald_crypt.h:220
KEY_8_LEN
Definition: ald_crypt.h:137
IS_CRYPT_KEY_LEN
#define IS_CRYPT_KEY_LEN(x)
Definition: ald_crypt.h:236
KEY_4_LEN
Definition: ald_crypt.h:135
crypt_handle_s::init
crypt_init_t init
Definition: ald_crypt.h:172
crypt_handle_s::key
uint32_t key[8]
Definition: ald_crypt.h:185
KEY_2_LEN
Definition: ald_crypt.h:134
crypt_handle_s::key_size
uint32_t key_size
Definition: ald_crypt.h:186
ERROR
Definition: utils.h:56


ALD User Manual: Encrypt or Decrypt functions

Functions
Encrypt or Decrypt functions
EASTSOFT ES32F3xx ALD » CRYPT » CRYPT Public Functions

Encrypt or Decrypt functions. More...

Collaboration diagram for Encrypt or Decrypt functions:

Functions

ald_status_t | ald_crypt_encrypt (crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size)
Encrypt an amount of data in blocking mode. More...
ald_status_t | ald_crypt_decrypt (crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size)
Decrypt an amount of data in blocking mode. More...
void | gcm_mul (uint32_t *res, uint32_t *data, uint32_t *iv)
ald_status_t | ald_crypt_gcm_verify (crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag)
verify an amount of data in gcm mode. More...
ald_status_t | ald_crypt_encrypt_by_it (crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size)
Encrypt an amount of data in non-blocking mode. More...
ald_status_t | ald_crypt_decrypt_by_it (crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size)
Decrypt an amount of data in non-blocking mode. More...
ald_status_t | ald_crypt_encrypt_by_dma (crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m)
Encrypt an amount of data in non-blocking mode. More...
ald_status_t | ald_crypt_decrypt_by_dma (crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m)
Decrypt an amount of data in non-blocking mode. More...

Detailed Description

Encrypt or Decrypt functions.

Function Documentation

◆ ald_crypt_decrypt()

ald_status_t ald_crypt_decrypt | ( | crypt_handle_t * | hperh,
 |  | uint8_t * | cipher_text,
 |  | uint8_t * | plain_text,
 |  | uint32_t | size
 | ) |  |

Decrypt an amount of data in blocking mode.

Parameters
hperh | Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
cipher_text | Pointer to cipher data buffer
plain_text | Pointer to plain data buffer
size | Amount of cipher data
Return values
Status,see ald_status_t.
Note
the size is multiple of 8(des) or 16(ase)

Definition at line 418 of file ald_crypt.c.

419 {
420 uint32_t count = 0;
421 uint32_t i;
422 uint32_t *plain_buf = (uint32_t*)plain_text;
423 uint32_t *cipher_buf = (uint32_t*)cipher_text;
424
425 if (hperh->init.mode == CRYPT_MODE_CTR) {
426 return ald_crypt_encrypt(hperh, cipher_text, plain_text, size);
427 }
428
429 if (hperh->state != CRYPT_STATE_READY)
430 return ERROR;
431
432 if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0))
433 return ERROR;
434
435 assert_param(IS_CRYPT(hperh->perh));
436
437 __LOCK(hperh);
438 hperh->state = CRYPT_STATE_BUSY;
439 CRYPT_SETDIR(hperh, CRYPT_DECRYPT);
440 count = size / (4 * hperh->step);
441
442 while (count--) {
443 for (i = 0; i < hperh->step; i++) {
444 CRYPT_WRITE_FIFO(hperh, *cipher_buf);
445 cipher_buf++;
446 }
447
448 while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET);
449
450 for (i = 0; i < hperh->step; i++)
451 *plain_buf++ = CRYPT_READ_FIFO(hperh);
452 }
453
454 hperh->state = CRYPT_STATE_READY;
455 __UNLOCK(hperh);
456
457 return OK;
458 }
crypt_handle_s::step
uint32_t step
Definition: ald_crypt.h:181
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
crypt_init_t::mode
crypt_mode_t mode
Definition: ald_crypt.h:162
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
ald_crypt_encrypt
ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size)
Encrypt an amount of data in blocking mode.
Definition: ald_crypt.c:370
crypt_handle_s::state
crypt_state_t state
Definition: ald_crypt.h:188
CRYPT_STATE_BUSY
Definition: ald_crypt.h:126
CRYPT_FLAG_DONE
Definition: ald_crypt.h:105
ald_crypt_get_flag_status
flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag)
Check whether the specified CRYPT flag is set or not.
Definition: ald_crypt.c:976
crypt_handle_s::perh
CRYPT_TypeDef * perh
Definition: ald_crypt.h:171
IS_CRYPT
#define IS_CRYPT(x)
Definition: ald_crypt.h:220
CRYPT_SETDIR
#define CRYPT_SETDIR(handle, dir)
Definition: ald_crypt.h:209
CRYPT_DECRYPT
Definition: ald_crypt.h:43
crypt_handle_s::init
crypt_init_t init
Definition: ald_crypt.h:172
CRYPT_WRITE_FIFO
#define CRYPT_WRITE_FIFO(handle, data)
Definition: ald_crypt.h:211
CRYPT_STATE_READY
Definition: ald_crypt.h:125
CRYPT_READ_FIFO
#define CRYPT_READ_FIFO(handle)
Definition: ald_crypt.h:212
CRYPT_MODE_CTR
Definition: ald_crypt.h:62
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56

◆ ald_crypt_decrypt_by_dma()

ald_status_t ald_crypt_decrypt_by_dma | ( | crypt_handle_t * | hperh,
 |  | uint8_t * | cipher_text,
 |  | uint8_t * | plain_text,
 |  | uint32_t | size,
 |  | uint8_t | channel_m2p,
 |  | uint8_t | channel_p2m
 | ) |  |

Decrypt an amount of data in non-blocking mode.

Parameters
hperh | Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
plain_text | Pointer to plain data buffer
cipher_text | Pointer to cipher data buffer
size | Amount of cipher data
channel_m2p | Memory to Crypt module DMA channel
channel_p2m | Crypt module to Memory DMA channel
Return values
Status,see ald_status_t.
Note
the size is multiple of 8(des) or 16(ase)

Definition at line 763 of file ald_crypt.c.

765 {
766 if (hperh->init.mode == CRYPT_MODE_CTR)
767 return ald_crypt_decrypt_by_dma(hperh, cipher_text, plain_text, size, channel_m2p, channel_p2m);
768
769 if (hperh->state != CRYPT_STATE_READY)
770 return ERROR;
771 if (plain_text == NULL || cipher_text == NULL || size == 0)
772 return ERROR;
773
774 __LOCK(hperh);
775 hperh->state = CRYPT_STATE_BUSY;
776
777 hperh->plain_text = plain_text;
778 hperh->cipher_text = cipher_text;
779 hperh->size = size;
780 hperh->count = size;
781
782 if (hperh->hdma_m2p.perh == NULL)
783 hperh->hdma_m2p.perh = DMA0;
784 if (hperh->hdma_p2m.perh == NULL)
785 hperh->hdma_p2m.perh = DMA0;
786
787
788 hperh->hdma_m2p.cplt_arg = NULL;
789 hperh->hdma_m2p.cplt_cbk = NULL;
790 hperh->hdma_m2p.err_arg = NULL;
791 hperh->hdma_m2p.err_cbk = NULL;
792
793 hperh->hdma_p2m.cplt_arg = (void *)hperh;
794 hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt;
795 hperh->hdma_p2m.err_arg = (void *)hperh;
796 hperh->hdma_p2m.err_cbk = &crypt_dma_error;
797
798 CRYPT_SETDIR(hperh, CRYPT_DECRYPT);
799
800 ald_dma_config_struct(&hperh->hdma_m2p.config);
801 hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD;
802 hperh->hdma_m2p.config.src = (void *)hperh->cipher_text;
803 hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO;
804 hperh->hdma_m2p.config.size = size / 4;
805 hperh->hdma_m2p.config.src_inc = DMA_DATA_INC_WORD;
806 hperh->hdma_m2p.config.dst_inc = DMA_DATA_INC_NONE;
807 hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT;
808 hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE;
809 hperh->hdma_m2p.config.burst = ENABLE;
810 hperh->hdma_m2p.config.channel = channel_m2p;
811 ald_dma_config_basic(&(hperh->hdma_m2p));
812
813 ald_dma_config_struct(&hperh->hdma_p2m.config);
814 hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD;
815 hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO;
816 hperh->hdma_p2m.config.dst = (void *)hperh->plain_text;
817 hperh->hdma_p2m.config.size = size / 4;
818 hperh->hdma_p2m.config.src_inc = DMA_DATA_INC_NONE;
819 hperh->hdma_p2m.config.dst_inc = DMA_DATA_INC_WORD;
820 hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT;
821 hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ;
822 hperh->hdma_m2p.config.burst = ENABLE;
823 hperh->hdma_p2m.config.channel = channel_p2m;
824 ald_dma_config_basic(&(hperh->hdma_p2m));
825
826 CRYPT_DMA_ENABLE(hperh);
827 __UNLOCK(hperh);
828
829 return OK;
830 }
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
crypt_init_t::mode
crypt_mode_t mode
Definition: ald_crypt.h:162
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
crypt_handle_s::plain_text
uint8_t * plain_text
Definition: ald_crypt.h:177
crypt_dma_error
static void crypt_dma_error(void *arg)
DMA CRYPT communication error callback.
Definition: ald_crypt.c:1122
crypt_handle_s::state
crypt_state_t state
Definition: ald_crypt.h:188
crypt_handle_s::size
uint32_t size
Definition: ald_crypt.h:179
CRYPT_STATE_BUSY
Definition: ald_crypt.h:126
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
ald_crypt_decrypt_by_dma
ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m)
Decrypt an amount of data in non-blocking mode.
Definition: ald_crypt.c:763
dma_config_t::src
void * src
Definition: ald_dma.h:278
DMA_DATA_INC_WORD
Definition: ald_dma.h:219
DMA_DATA_SIZE_WORD
Definition: ald_dma.h:229
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
crypt_handle_s::perh
CRYPT_TypeDef * perh
Definition: ald_crypt.h:171
CRYPT_SETDIR
#define CRYPT_SETDIR(handle, dir)
Definition: ald_crypt.h:209
crypt_handle_s::hdma_m2p
dma_handle_t hdma_m2p
Definition: ald_crypt.h:174
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
crypt_handle_s::cipher_text
uint8_t * cipher_text
Definition: ald_crypt.h:178
CRYPT_DECRYPT
Definition: ald_crypt.h:43
crypt_handle_s::init
crypt_init_t init
Definition: ald_crypt.h:172
CRYPT_STATE_READY
Definition: ald_crypt.h:125
CRYPT_MODE_CTR
Definition: ald_crypt.h:62
crypt_dma_crypt_cplt
static void crypt_dma_crypt_cplt(void *arg)
DMA CRYPT encrypt or decrypt process complete callback.
Definition: ald_crypt.c:1100
crypt_handle_s::hdma_p2m
dma_handle_t hdma_p2m
Definition: ald_crypt.h:175
DMA_MSIGSEL_CRYPT_WRITE
Definition: ald_dma.h:132
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
DMA_MSEL_CRYPT
Definition: ald_dma.h:80
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
CRYPT_DMA_ENABLE
#define CRYPT_DMA_ENABLE(handle)
Definition: ald_crypt.h:207
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
crypt_handle_s::count
uint32_t count
Definition: ald_crypt.h:180
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
DMA_MSIGSEL_CRYPT_READ
Definition: ald_dma.h:133
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294

◆ ald_crypt_decrypt_by_it()

ald_status_t ald_crypt_decrypt_by_it | ( | crypt_handle_t * | hperh,
 |  | uint8_t * | cipher_text,
 |  | uint8_t * | plain_text,
 |  | uint32_t | size
 | ) |  |

Decrypt an amount of data in non-blocking mode.

Parameters
hperh | Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
plain_text | Pointer to plain data buffer
cipher_text | Pointer to cipher data buffer
size | Amount of cipher data
Return values
Status,see ald_status_t.
Note
the size is multiple of 8(des) or 16(ase)

Definition at line 635 of file ald_crypt.c.

636 {
637 uint32_t i;
638 uint32_t *cipher_buf = (uint32_t*)cipher_text;
639
640 if (hperh->init.mode == CRYPT_MODE_CTR) {
641 return ald_crypt_decrypt_by_it(hperh, cipher_text, plain_text, size);
642 }
643
644 if (hperh->state != CRYPT_STATE_READY)
645 return ERROR;
646
647 if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0))
648 return ERROR;
649
650 assert_param(IS_CRYPT(hperh->perh));
651
652 __LOCK(hperh);
653 hperh->state = CRYPT_STATE_BUSY;
654 CRYPT_SETDIR(hperh, CRYPT_DECRYPT);
655 hperh->count = hperh->step;
656 hperh->plain_text = plain_text;
657 hperh->cipher_text = cipher_text;
658 hperh->size = size;
659 ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE);
660
661 for (i = 0; i < hperh->step; i++) {
662 CRYPT_WRITE_FIFO(hperh, *cipher_buf);
663 cipher_buf ++;
664 }
665
666 __UNLOCK(hperh);
667 return OK;
668 }
crypt_handle_s::step
uint32_t step
Definition: ald_crypt.h:181
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
crypt_init_t::mode
crypt_mode_t mode
Definition: ald_crypt.h:162
assert_param
#define assert_param(x)
Definition: type.h:88
crypt_handle_s::plain_text
uint8_t * plain_text
Definition: ald_crypt.h:177
crypt_handle_s::state
crypt_state_t state
Definition: ald_crypt.h:188
crypt_handle_s::size
uint32_t size
Definition: ald_crypt.h:179
CRYPT_STATE_BUSY
Definition: ald_crypt.h:126
crypt_handle_s::perh
CRYPT_TypeDef * perh
Definition: ald_crypt.h:171
IS_CRYPT
#define IS_CRYPT(x)
Definition: ald_crypt.h:220
CRYPT_SETDIR
#define CRYPT_SETDIR(handle, dir)
Definition: ald_crypt.h:209
crypt_handle_s::cipher_text
uint8_t * cipher_text
Definition: ald_crypt.h:178
CRYPT_IT_IT
Definition: ald_crypt.h:96
ald_crypt_interrupt_config
void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state)
Enables or disables the specified CRYPT interrupts.
Definition: ald_crypt.c:955
CRYPT_DECRYPT
Definition: ald_crypt.h:43
crypt_handle_s::init
crypt_init_t init
Definition: ald_crypt.h:172
CRYPT_WRITE_FIFO
#define CRYPT_WRITE_FIFO(handle, data)
Definition: ald_crypt.h:211
CRYPT_STATE_READY
Definition: ald_crypt.h:125
CRYPT_MODE_CTR
Definition: ald_crypt.h:62
ald_crypt_decrypt_by_it
ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size)
Decrypt an amount of data in non-blocking mode.
Definition: ald_crypt.c:635
crypt_handle_s::count
uint32_t count
Definition: ald_crypt.h:180
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56

◆ ald_crypt_encrypt()

ald_status_t ald_crypt_encrypt | ( | crypt_handle_t * | hperh,
 |  | uint8_t * | plain_text,
 |  | uint8_t * | cipher_text,
 |  | uint32_t | size
 | ) |  |

Encrypt an amount of data in blocking mode.

Parameters
hperh | Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
plain_text | Pointer to plain data buffer
cipher_text | Pointer to cipher data buffer
size | Amount of plain data
Return values
Status,see ald_status_t.
Note
the size is multiple of 8(des) or 16(ase)

Definition at line 370 of file ald_crypt.c.

371 {
372 uint32_t count = 0;
373 uint32_t i;
374 uint32_t *plain_buf = (uint32_t *)plain_text;
375 uint32_t *cipher_buf = (uint32_t *)cipher_text;
376
377 if (hperh->state != CRYPT_STATE_READY)
378 return ERROR;
379
380 if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0))
381 return ERROR;
382
383 assert_param(IS_CRYPT(hperh->perh));
384
385 __LOCK(hperh);
386 hperh->state = CRYPT_STATE_BUSY;
387 CRYPT_SETDIR(hperh, CRYPT_ENCRYPT);
388 count = size / (4 * hperh->step);
389
390 while (count--) {
391 for (i = 0; i < hperh->step; i++) {
392 CRYPT_WRITE_FIFO(hperh, *plain_buf);
393 plain_buf++;
394 }
395
396 while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET);
397
398 for (i = 0; i < hperh->step; i++)
399 *cipher_buf++ = CRYPT_READ_FIFO(hperh);
400 }
401
402 hperh->state = CRYPT_STATE_READY;
403 __UNLOCK(hperh);
404
405 return OK;
406 }
CRYPT_ENCRYPT
Definition: ald_crypt.h:44
crypt_handle_s::step
uint32_t step
Definition: ald_crypt.h:181
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
crypt_handle_s::state
crypt_state_t state
Definition: ald_crypt.h:188
CRYPT_STATE_BUSY
Definition: ald_crypt.h:126
CRYPT_FLAG_DONE
Definition: ald_crypt.h:105
ald_crypt_get_flag_status
flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag)
Check whether the specified CRYPT flag is set or not.
Definition: ald_crypt.c:976
crypt_handle_s::perh
CRYPT_TypeDef * perh
Definition: ald_crypt.h:171
IS_CRYPT
#define IS_CRYPT(x)
Definition: ald_crypt.h:220
CRYPT_SETDIR
#define CRYPT_SETDIR(handle, dir)
Definition: ald_crypt.h:209
CRYPT_WRITE_FIFO
#define CRYPT_WRITE_FIFO(handle, data)
Definition: ald_crypt.h:211
CRYPT_STATE_READY
Definition: ald_crypt.h:125
CRYPT_READ_FIFO
#define CRYPT_READ_FIFO(handle)
Definition: ald_crypt.h:212
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56

◆ ald_crypt_encrypt_by_dma()

ald_status_t ald_crypt_encrypt_by_dma | ( | crypt_handle_t * | hperh,
 |  | uint8_t * | plain_text,
 |  | uint8_t * | cipher_text,
 |  | uint32_t | size,
 |  | uint8_t | channel_m2p,
 |  | uint8_t | channel_p2m
 | ) |  |

Encrypt an amount of data in non-blocking mode.

Parameters
hperh | Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
plain_text | Pointer to plain data buffer
cipher_text | Pointer to cipher data buffer
size | Amount of plain data
channel_m2p | Memory to Crypt module DMA channel
channel_p2m | Crypt module to Memory DMA channel
Return values
Status,see ald_status_t.
Note
the size is multiple of 8(des) or 16(ase)

Definition at line 683 of file ald_crypt.c.

685 {
686 if (hperh->state != CRYPT_STATE_READY)
687 return ERROR;
688
689 if (plain_text == NULL || cipher_text == NULL || size == 0)
690 return ERROR;
691
692 assert_param(IS_CRYPT(hperh->perh));
693
694 __LOCK(hperh);
695 hperh->state = CRYPT_STATE_BUSY;
696
697 hperh->plain_text = plain_text;
698 hperh->cipher_text = cipher_text;
699 hperh->size = size;
700 hperh->count = size;
701
702 if (hperh->hdma_m2p.perh == NULL)
703 hperh->hdma_m2p.perh = DMA0;
704 if (hperh->hdma_p2m.perh == NULL)
705 hperh->hdma_p2m.perh = DMA0;
706
707 hperh->hdma_m2p.cplt_arg = NULL;
708 hperh->hdma_m2p.cplt_cbk = NULL;
709 hperh->hdma_m2p.err_arg = NULL;
710 hperh->hdma_m2p.err_cbk = NULL;
711
712 hperh->hdma_p2m.cplt_arg = (void *)hperh;
713 hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt;
714 hperh->hdma_p2m.err_arg = (void *)hperh;
715 hperh->hdma_p2m.err_cbk = &crypt_dma_error;
716
717 CRYPT_SETDIR(hperh, CRYPT_ENCRYPT);
718
719 ald_dma_config_struct(&hperh->hdma_m2p.config);
720 hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD;
721 hperh->hdma_m2p.config.src = (void *)hperh->plain_text;
722 hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO;
723 hperh->hdma_m2p.config.size = size / 4;
724 hperh->hdma_m2p.config.src_inc = DMA_DATA_INC_WORD;
725 hperh->hdma_m2p.config.dst_inc = DMA_DATA_INC_NONE;
726 hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT;
727 hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE;
728 hperh->hdma_m2p.config.burst = ENABLE;
729 hperh->hdma_m2p.config.channel = channel_m2p;
730 ald_dma_config_basic(&(hperh->hdma_m2p));
731
732 ald_dma_config_struct(&hperh->hdma_p2m.config);
733 hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD;
734 hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO;
735 hperh->hdma_p2m.config.dst = (void *)hperh->cipher_text;
736 hperh->hdma_p2m.config.size = size / 4;
737 hperh->hdma_p2m.config.src_inc = DMA_DATA_INC_NONE;
738 hperh->hdma_p2m.config.dst_inc = DMA_DATA_INC_WORD;
739 hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT;
740 hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ;
741 hperh->hdma_p2m.config.burst = ENABLE;
742 hperh->hdma_p2m.config.channel = channel_p2m;
743 ald_dma_config_basic(&(hperh->hdma_p2m));
744
745 CRYPT_DMA_ENABLE(hperh);
746 __UNLOCK(hperh);
747
748 return OK;
749 }
CRYPT_ENCRYPT
Definition: ald_crypt.h:44
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
assert_param
#define assert_param(x)
Definition: type.h:88
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
crypt_handle_s::plain_text
uint8_t * plain_text
Definition: ald_crypt.h:177
crypt_dma_error
static void crypt_dma_error(void *arg)
DMA CRYPT communication error callback.
Definition: ald_crypt.c:1122
crypt_handle_s::state
crypt_state_t state
Definition: ald_crypt.h:188
crypt_handle_s::size
uint32_t size
Definition: ald_crypt.h:179
CRYPT_STATE_BUSY
Definition: ald_crypt.h:126
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
DMA_DATA_INC_WORD
Definition: ald_dma.h:219
DMA_DATA_SIZE_WORD
Definition: ald_dma.h:229
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
crypt_handle_s::perh
CRYPT_TypeDef * perh
Definition: ald_crypt.h:171
IS_CRYPT
#define IS_CRYPT(x)
Definition: ald_crypt.h:220
CRYPT_SETDIR
#define CRYPT_SETDIR(handle, dir)
Definition: ald_crypt.h:209
crypt_handle_s::hdma_m2p
dma_handle_t hdma_m2p
Definition: ald_crypt.h:174
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
crypt_handle_s::cipher_text
uint8_t * cipher_text
Definition: ald_crypt.h:178
CRYPT_STATE_READY
Definition: ald_crypt.h:125
crypt_dma_crypt_cplt
static void crypt_dma_crypt_cplt(void *arg)
DMA CRYPT encrypt or decrypt process complete callback.
Definition: ald_crypt.c:1100
crypt_handle_s::hdma_p2m
dma_handle_t hdma_p2m
Definition: ald_crypt.h:175
DMA_MSIGSEL_CRYPT_WRITE
Definition: ald_dma.h:132
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
DMA_MSEL_CRYPT
Definition: ald_dma.h:80
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
CRYPT_DMA_ENABLE
#define CRYPT_DMA_ENABLE(handle)
Definition: ald_crypt.h:207
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
crypt_handle_s::count
uint32_t count
Definition: ald_crypt.h:180
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
DMA_MSIGSEL_CRYPT_READ
Definition: ald_dma.h:133
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294

◆ ald_crypt_encrypt_by_it()

ald_status_t ald_crypt_encrypt_by_it | ( | crypt_handle_t * | hperh,
 |  | uint8_t * | plain_text,
 |  | uint8_t * | cipher_text,
 |  | uint32_t | size
 | ) |  |

Encrypt an amount of data in non-blocking mode.

Parameters
hperh | Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
plain_text | Pointer to plain data buffer
cipher_text | Pointer to cipher data buffer
size | Amount of plain data
Return values
Status,see ald_status_t.
Note
the size is multiple of 8(des) or 16(ase)

Definition at line 594 of file ald_crypt.c.

595 {
596 uint32_t i;
597 uint32_t *plain_buf = (uint32_t *)plain_text;
598
599 if (hperh->state != CRYPT_STATE_READY)
600 return ERROR;
601
602 if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0))
603 return ERROR;
604
605 assert_param(IS_CRYPT(hperh->perh));
606
607 __LOCK(hperh);
608 hperh->state = CRYPT_STATE_BUSY;
609 CRYPT_SETDIR(hperh, CRYPT_ENCRYPT);
610 hperh->count = hperh->step;
611 hperh->plain_text = plain_text;
612 hperh->cipher_text = cipher_text;
613 hperh->size = size;
614 ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE);
615
616 for (i = 0; i < hperh->step; i++) {
617 CRYPT_WRITE_FIFO(hperh, *plain_buf);
618 ++plain_buf;
619 }
620
621 __UNLOCK(hperh);
622 return OK;
623 }
CRYPT_ENCRYPT
Definition: ald_crypt.h:44
crypt_handle_s::step
uint32_t step
Definition: ald_crypt.h:181
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
crypt_handle_s::plain_text
uint8_t * plain_text
Definition: ald_crypt.h:177
crypt_handle_s::state
crypt_state_t state
Definition: ald_crypt.h:188
crypt_handle_s::size
uint32_t size
Definition: ald_crypt.h:179
CRYPT_STATE_BUSY
Definition: ald_crypt.h:126
crypt_handle_s::perh
CRYPT_TypeDef * perh
Definition: ald_crypt.h:171
IS_CRYPT
#define IS_CRYPT(x)
Definition: ald_crypt.h:220
CRYPT_SETDIR
#define CRYPT_SETDIR(handle, dir)
Definition: ald_crypt.h:209
crypt_handle_s::cipher_text
uint8_t * cipher_text
Definition: ald_crypt.h:178
CRYPT_IT_IT
Definition: ald_crypt.h:96
ald_crypt_interrupt_config
void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state)
Enables or disables the specified CRYPT interrupts.
Definition: ald_crypt.c:955
CRYPT_WRITE_FIFO
#define CRYPT_WRITE_FIFO(handle, data)
Definition: ald_crypt.h:211
CRYPT_STATE_READY
Definition: ald_crypt.h:125
crypt_handle_s::count
uint32_t count
Definition: ald_crypt.h:180
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56

◆ ald_crypt_gcm_verify()

ald_status_t ald_crypt_gcm_verify | ( | crypt_handle_t * | hperh,
 |  | uint8_t * | cipher_text,
 |  | uint32_t | size,
 |  | uint8_t * | aadata,
 |  | uint32_t | alen,
 |  | uint8_t * | tag
 | ) |  |

verify an amount of data in gcm mode.

Parameters
hperh | Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
cipher_text | Pointer to cipher data buffer
size | Amount of cipher data
aadata | Pointer to additional authenticated data buffer
alen | Amount of additional authenticated data
tag | Pointer to authentication tag buffer
Return values
Status,see ald_status_t.

Definition at line 496 of file ald_crypt.c.

497 {
498 uint8_t GCM_HASH_in[0x60] = {0} ;
499 uint8_t ecb[16] = {0} ;
500 uint32_t x_temp[4];
501 uint64_t u, v;
502 uint32_t len = 0;
503 uint32_t j, i, k;
504 uint32_t *tag_temp, *cipher_text_temp;
505
506 /* calculate u and v */
507 u = 128 * ((size % 16) ? (size / 16 + 1) : size / 16) - size * 8;
508 v = 128 * ((alen % 16) ? (alen / 16 + 1): alen / 16) - alen * 8;
509
510 /* get the input of GHASH algorithm,the input:A||0^v||C||0^u||[len(A)]_64||[len(C)]_64 */
511 for (i = 0; i < alen; i++) {
512 GCM_HASH_in [i] = * (aadata + i);
513 }
514 len += alen;
515 for (i = 0; i < v / 8; i++) {
516 GCM_HASH_in[i + len] = 0;
517 }
518 len += v / 8;
519 for (i = 0; i < size; i++) {
520 GCM_HASH_in[i + len] = * (cipher_text + i);
521 }
522 len += size;
523 for (i = 0; i < u / 8; i++) {
524 GCM_HASH_in[i + len] = 0;
525 }
526 len += u / 8;
527
528 for (i = 0; i < 4; i++) {
529 GCM_HASH_in[i + len] = 0;
530 }
531 len += 4;
532
533 for (i = 0; i < 4; i++) {
534 GCM_HASH_in[i + len] = ((alen * 8) >> (8 * i)) & 0xFF;
535 }
536 len += 4;
537
538 for (i = 0; i < 4; i++) {
539 GCM_HASH_in[i + len] = 0;
540 }
541 len += 4;
542
543 for (i = 0; i < 4; i++) {
544 GCM_HASH_in[i + len] = ((size * 8) >> (8 * i)) & 0xFF;
545 }
546 len += 4;
547
548 CRYPT->CON &= ~(3U << CRYPT_CON_MODE_POSS);
549 CRYPT->CON |= (CRYPT_MODE_ECB << CRYPT_CON_MODE_POSS);
550
551 ald_crypt_encrypt(hperh, ecb, ecb, 16);
552
553 k = len / 16;
554 for (i = 0; i < 16; i++) {
555 tag[i] = 0;
556 }
557
558 cipher_text_temp = (uint32_t *)GCM_HASH_in;
559 tag_temp = (uint32_t *)tag;
560 for (i = 0; i < k; i++) {
561 for (j = 0; j < 4; j++) {
562 x_temp[j] = (*cipher_text_temp) ^ tag_temp[j];
563 ++cipher_text_temp;
564 }
565
566 gcm_mul((uint32_t *)tag_temp, x_temp, (uint32_t *)ecb);
567 }
568
569 /* calculate the authentication tag T,
570 * T = CIPH_K(J0)^S,J0=IV||0^31||1,CIPH_K is the algorithm of AES in ECB mode
571 */
572 tag_temp = (uint32_t *)tag;
573 ald_crypt_init(hperh);
574 CRYPT->CON &= ~(3U << CRYPT_CON_MODE_POSS);
575 CRYPT->CON |= (CRYPT_MODE_CTR << CRYPT_CON_MODE_POSS);
576 ald_crypt_write_key(hperh, hperh->key, KEY_4_LEN);
577 hperh->iv[3] = 1;
578 ald_crypt_write_ivr(hperh, hperh->iv, IV_4_LEN);
579 ald_crypt_encrypt(hperh, tag, tag, 16);
580
581 return OK;
582 }
IV_4_LEN
Definition: ald_crypt.h:145
OK
Definition: utils.h:55
crypt_handle_s::iv
uint32_t iv[4]
Definition: ald_crypt.h:183
ald_crypt_encrypt
ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size)
Encrypt an amount of data in blocking mode.
Definition: ald_crypt.c:370
ald_crypt_write_ivr
ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv, crypt_ivr_len_t len)
Write the Content of IV if you use CBC mode.
Definition: ald_crypt.c:272
CRYPT_MODE_ECB
Definition: ald_crypt.h:60
ald_crypt_init
ald_status_t ald_crypt_init(crypt_handle_t *hperh)
Initializes the CRYPT mode according to the specified parameters in the crypt_init_t and create the a...
Definition: ald_crypt.c:61
KEY_4_LEN
Definition: ald_crypt.h:135
CRYPT_MODE_CTR
Definition: ald_crypt.h:62
ald_crypt_write_key
ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t *key, crypt_key_len_t len)
Write the Content of KEY.
Definition: ald_crypt.c:143
crypt_handle_s::key
uint32_t key[8]
Definition: ald_crypt.h:185
gcm_mul
void gcm_mul(uint32_t *res, uint32_t *data, uint32_t *iv)
Definition: ald_crypt.c:460

◆ gcm_mul()

void gcm_mul | ( | uint32_t * | res,
 |  | uint32_t * | data,
 |  | uint32_t * | iv
 | ) |  |

Definition at line 460 of file ald_crypt.c.

461 {
462 CRYPT->CON = 0;
463 CRYPT->DATA[0] = data[3];
464 CRYPT->DATA[1] = data[2];
465 CRYPT->DATA[2] = data[1];
466 CRYPT->DATA[3] = data[0];
467 CRYPT->IV[0] = iv[3];
468 CRYPT->IV[1] = iv[2];
469 CRYPT->IV[2] = iv[1];
470 CRYPT->IV[3] = iv[0];
471 CRYPT->CON |= ((1 << CRYPT_CON_RESCLR_POS) | (3 << CRYPT_CON_MODE_POSS) | \
472 (1 << CRYPT_CON_GO_POS));
473
474 while (READ_BIT(CRYPT->IF, CRYPT_IF_MULTHIF_MSK) == 0);
475
476 res[3] = CRYPT->RES[0];
477 res[2] = CRYPT->RES[1];
478 res[1] = CRYPT->RES[2];
479 res[0] = CRYPT->RES[3];
480
481 SET_BIT(CRYPT->IFC, CRYPT_IFC_MULTHIFC_MSK);
482 return;
483 }
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67


ALD User Manual: DMA operation functions

Functions
DMA operation functions
EASTSOFT ES32F3xx ALD » CRYPT » CRYPT Public Functions

DMA operation functions. More...

Collaboration diagram for DMA operation functions:

Functions

ald_status_t | ald_crypt_dma_pause (crypt_handle_t *hperh)
Pauses the DMA Transfer. More...
ald_status_t | ald_crypt_dma_resume (crypt_handle_t *hperh)
Resumes the DMA Transfer. More...
ald_status_t | ald_crypt_dma_stop (crypt_handle_t *hperh)
Stops the DMA Transfer. More...
void | ald_crypt_irq_handler (crypt_handle_t *hperh)
This function handles CRYPT interrupt request. More...

Detailed Description

DMA operation functions.

Function Documentation

◆ ald_crypt_dma_pause()

ald_status_t ald_crypt_dma_pause ( crypt_handle_t * hperh )

Pauses the DMA Transfer.

Parameters
hperh Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
Return values
Status,see ald_status_t.

Definition at line 847 of file ald_crypt.c.

848 {
849 __LOCK(hperh);
850 CRYPT_DMA_DISABLE(hperh);
851 __UNLOCK(hperh);
852
853 return OK;
854
855 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CRYPT_DMA_DISABLE
#define CRYPT_DMA_DISABLE(handle)
Definition: ald_crypt.h:208
__LOCK
#define __LOCK(x)
Definition: utils.h:92

◆ ald_crypt_dma_resume()

ald_status_t ald_crypt_dma_resume ( crypt_handle_t * hperh )

Resumes the DMA Transfer.

Parameters
hperh Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
Return values
Status,see ald_status_t.

Definition at line 863 of file ald_crypt.c.

864 {
865 __LOCK(hperh);
866 CRYPT_DMA_ENABLE(hperh);
867 __UNLOCK(hperh);
868
869 return OK;
870 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CRYPT_DMA_ENABLE
#define CRYPT_DMA_ENABLE(handle)
Definition: ald_crypt.h:207
__LOCK
#define __LOCK(x)
Definition: utils.h:92

◆ ald_crypt_dma_stop()

ald_status_t ald_crypt_dma_stop ( crypt_handle_t * hperh )

Stops the DMA Transfer.

Parameters
hperh Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
Return values
Status,see ald_status_t.

Definition at line 878 of file ald_crypt.c.

879 {
880 __LOCK(hperh);
881 CRYPT_DMA_DISABLE(hperh);
882 __UNLOCK(hperh);
883
884 hperh->state = CRYPT_STATE_READY;
885 return OK;
886 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
crypt_handle_s::state
crypt_state_t state
Definition: ald_crypt.h:188
CRYPT_DMA_DISABLE
#define CRYPT_DMA_DISABLE(handle)
Definition: ald_crypt.h:208
CRYPT_STATE_READY
Definition: ald_crypt.h:125
__LOCK
#define __LOCK(x)
Definition: utils.h:92

◆ ald_crypt_irq_handler()

void ald_crypt_irq_handler ( crypt_handle_t * hperh )

This function handles CRYPT interrupt request.

Parameters
hperh Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
Return values
None

Definition at line 895 of file ald_crypt.c.

896 {
897 uint32_t i;
898 uint32_t *in_buf = (uint32_t *)hperh->cipher_text;
899 uint32_t *out_buf = (uint32_t *)hperh->plain_text;
900
901 if (READ_BIT(hperh->perh->CON, CRYPT_CON_ENCS_MSK) == (CRYPT_DECRYPT << CRYPT_CON_ENCS_POS)) {
902 in_buf = (uint32_t *)hperh->cipher_text + hperh->count;
903 out_buf = (uint32_t *)hperh->plain_text + hperh->count - hperh->step;
904 }
905 else {
906 in_buf = (uint32_t *)hperh->plain_text + hperh->count;
907 out_buf = (uint32_t *)hperh->cipher_text + hperh->count - hperh->step;
908 }
909
910 if (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_AESIF) == SET) {
911 ald_crypt_clear_flag_status(hperh, CRYPT_FLAG_AESIF);
912 }
913
914 if (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DESIF) == SET) {
915 ald_crypt_clear_flag_status(hperh, CRYPT_FLAG_DESIF);
916 }
917
918 for (i = 0; i < hperh->step; i++)
919 *out_buf++ = CRYPT_READ_FIFO(hperh);
920
921 hperh->count = hperh->count + hperh->step;
922 if (hperh->count > (hperh->size / 4)) {
923 hperh->count = 0;
924 hperh->state = CRYPT_STATE_READY;
925 hperh->crypt_cplt_cbk(hperh);
926 }
927 else {
928 for (i = 0; i < hperh->step; i++) {
929 CRYPT_WRITE_FIFO(hperh, *in_buf);
930 ++in_buf;
931 }
932 }
933 }
crypt_handle_s::step
uint32_t step
Definition: ald_crypt.h:181
crypt_handle_s::crypt_cplt_cbk
void(* crypt_cplt_cbk)(struct crypt_handle_s *arg)
Definition: ald_crypt.h:190
SET
Definition: type.h:39
crypt_handle_s::plain_text
uint8_t * plain_text
Definition: ald_crypt.h:177
crypt_handle_s::state
crypt_state_t state
Definition: ald_crypt.h:188
crypt_handle_s::size
uint32_t size
Definition: ald_crypt.h:179
CRYPT_FLAG_AESIF
Definition: ald_crypt.h:103
ald_crypt_clear_flag_status
void ald_crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag)
Clear the specified CRYPT pending flags.
Definition: ald_crypt.c:997
CRYPT_FLAG_DESIF
Definition: ald_crypt.h:104
ald_crypt_get_flag_status
flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag)
Check whether the specified CRYPT flag is set or not.
Definition: ald_crypt.c:976
crypt_handle_s::perh
CRYPT_TypeDef * perh
Definition: ald_crypt.h:171
crypt_handle_s::cipher_text
uint8_t * cipher_text
Definition: ald_crypt.h:178
CRYPT_DECRYPT
Definition: ald_crypt.h:43
CRYPT_WRITE_FIFO
#define CRYPT_WRITE_FIFO(handle, data)
Definition: ald_crypt.h:211
CRYPT_STATE_READY
Definition: ald_crypt.h:125
CRYPT_READ_FIFO
#define CRYPT_READ_FIFO(handle)
Definition: ald_crypt.h:212
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
crypt_handle_s::count
uint32_t count
Definition: ald_crypt.h:180


ALD User Manual: Peripheral Control functions

Functions
Peripheral Control functions
EASTSOFT ES32F3xx ALD » CRYPT » CRYPT Public Functions

CRYPT control functions. More...

Collaboration diagram for Peripheral Control functions:

Functions

void | ald_crypt_interrupt_config (crypt_handle_t *hperh, crypt_it_t it, type_func_t state)
Enables or disables the specified CRYPT interrupts. More...
flag_status_t | ald_crypt_get_flag_status (crypt_handle_t *hperh, crypt_flag_t flag)
Check whether the specified CRYPT flag is set or not. More...
void | ald_crypt_clear_flag_status (crypt_handle_t *hperh, crypt_flag_t flag)
Clear the specified CRYPT pending flags. More...
it_status_t | ald_crypt_get_it_status (crypt_handle_t *hperh, crypt_it_t it)
Checks whether the specified CRYPT interrupt has occurred or not. More...

Detailed Description

CRYPT control functions.

Function Documentation

◆ ald_crypt_clear_flag_status()

void ald_crypt_clear_flag_status | ( | crypt_handle_t * | hperh,
 |  | crypt_flag_t | flag
 | ) |  |

Clear the specified CRYPT pending flags.

Parameters
hperh Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
flag specifies the flag to check. This parameter can be any combination of the following values:
  • CRYPT_FLAG_AESIF: AES encrypt or decrypt Complete flag.
  • CRYPT_FLAG_DESIF: AES encrypt or decrypt Complete flag.
  • CRYPT_FLAG_DONE: encrypt or decrypt Complete flag.
Return values
None

Definition at line 997 of file ald_crypt.c.

998 {
999 assert_param(IS_CRYPT(hperh->perh));
1000 assert_param(IS_CRYPT_FLAG(flag));
1001
1002 CRYPT->IFC = (uint32_t)flag;
1003 return;
1004 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_CRYPT_FLAG
#define IS_CRYPT_FLAG(x)
Definition: ald_crypt.h:231
crypt_handle_s::perh
CRYPT_TypeDef * perh
Definition: ald_crypt.h:171
IS_CRYPT
#define IS_CRYPT(x)
Definition: ald_crypt.h:220

◆ ald_crypt_get_flag_status()

flag_status_t ald_crypt_get_flag_status | ( | crypt_handle_t * | hperh,
 |  | crypt_flag_t | flag
 | ) |  |

Check whether the specified CRYPT flag is set or not.

Parameters
hperh | Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
flag | specifies the flag to check. This parameter can be one of the crypt_flag_t.
Return values
Status
  • SET
  • RESET

Definition at line 976 of file ald_crypt.c.

977 {
978 assert_param(IS_CRYPT(hperh->perh));
979 assert_param(IS_CRYPT_FLAG(flag));
980
981 if (CRYPT->IF & flag)
982 return SET;
983
984 return RESET;
985 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
RESET
Definition: type.h:38
IS_CRYPT_FLAG
#define IS_CRYPT_FLAG(x)
Definition: ald_crypt.h:231
crypt_handle_s::perh
CRYPT_TypeDef * perh
Definition: ald_crypt.h:171
IS_CRYPT
#define IS_CRYPT(x)
Definition: ald_crypt.h:220

◆ ald_crypt_get_it_status()

it_status_t ald_crypt_get_it_status | ( | crypt_handle_t * | hperh,
 |  | crypt_it_t | it
 | ) |  |

Checks whether the specified CRYPT interrupt has occurred or not.

Parameters
hperh Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
it Specifies the CRYPT interrupt source to check. This parameter can be one of the following values:
  • crypt_it_t: CRYPT interrupt
Return values
Status
  • SET
  • RESET

Definition at line 1017 of file ald_crypt.c.

1018 {
1019 assert_param(IS_CRYPT_IT(it));
1020
1021 if (READ_BIT(CRYPT->CON, CRYPT_CON_IE_MSK))
1022 return SET;
1023
1024 return RESET;
1025 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
RESET
Definition: type.h:38
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
IS_CRYPT_IT
#define IS_CRYPT_IT(x)
Definition: ald_crypt.h:230

◆ ald_crypt_interrupt_config()

void ald_crypt_interrupt_config | ( | crypt_handle_t * | hperh,
 |  | crypt_it_t | it,
 |  | type_func_t | state
 | ) |  |

Enables or disables the specified CRYPT interrupts.

Parameters
hperh Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
it Specifies the CRYPT interrupt sources to be enabled or disabled. This parameter can be one of the following values:
  • crypt_it_t: CRYPT interrupt
state New status
  • ENABLE
  • DISABLE
Return values
None

Definition at line 955 of file ald_crypt.c.

956 {
957 assert_param(IS_CRYPT(hperh->perh));
958
959 if (it == CRYPT_IT_IT) {
960 CLEAR_BIT(CRYPT->CON, CRYPT_CON_IE_MSK);
961 CRYPT->CON |= (state << CRYPT_CON_IE_POS);
962 }
963
964 return;
965 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
crypt_handle_s::perh
CRYPT_TypeDef * perh
Definition: ald_crypt.h:171
IS_CRYPT
#define IS_CRYPT(x)
Definition: ald_crypt.h:220
CRYPT_IT_IT
Definition: ald_crypt.h:96


ALD User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
EASTSOFT ES32F3xx ALD » CRYPT » CRYPT Public Functions

State and Errors functions. More...

Collaboration diagram for Peripheral State and Errors functions:

Functions

crypt_state_t ald_crypt_get_state (crypt_handle_t *hperh)
Returns the CRYPT state. More...

Detailed Description

State and Errors functions.

Function Documentation

◆ ald_crypt_get_state()

crypt_state_t ald_crypt_get_state ( crypt_handle_t * hperh )

Returns the CRYPT state.

Parameters
hperh Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
Return values
CRYPT state

Definition at line 1043 of file ald_crypt.c.

1044 {
1045 assert_param(IS_CRYPT(hperh->perh));
1046
1047 return hperh->state;
1048 }
assert_param
#define assert_param(x)
Definition: type.h:88
crypt_handle_s::state
crypt_state_t state
Definition: ald_crypt.h:188
crypt_handle_s::perh
CRYPT_TypeDef * perh
Definition: ald_crypt.h:171
IS_CRYPT
#define IS_CRYPT(x)
Definition: ald_crypt.h:220


ALD User Manual: CRYPT Private Functions

Functions
CRYPT Private Functions
EASTSOFT ES32F3xx ALD » CRYPT EASTSOFT ES32F3xx ALD » | TRNG

CRYPT Private functions. More...

Collaboration diagram for CRYPT Private Functions:

Functions

void | crypt_reset (crypt_handle_t *hperh)
Reset the CRYPT peripheral. More...
static void | crypt_dma_crypt_cplt (void *arg)
DMA CRYPT encrypt or decrypt process complete callback. More...
static void | crypt_dma_error (void *arg)
DMA CRYPT communication error callback. More...

Detailed Description

CRYPT Private functions.

Function Documentation

◆ crypt_dma_crypt_cplt()

static void crypt_dma_crypt_cplt ( void * arg )
static

DMA CRYPT encrypt or decrypt process complete callback.

Parameters
arg Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
Return values
None

Definition at line 1100 of file ald_crypt.c.

1101 {
1102 crypt_handle_t *hperh = (crypt_handle_t *)arg;
1103
1104 CRYPT_DMA_DISABLE(hperh);
1105 hperh->count = 0;
1106 hperh->plain_text = NULL;
1107 hperh->cipher_text = NULL;
1108 hperh->size = 0;
1109
1110 hperh->state = CRYPT_STATE_READY;
1111
1112 if (hperh->crypt_cplt_cbk)
1113 hperh->crypt_cplt_cbk(hperh);
1114 }
crypt_handle_s::crypt_cplt_cbk
void(* crypt_cplt_cbk)(struct crypt_handle_s *arg)
Definition: ald_crypt.h:190
crypt_handle_s::plain_text
uint8_t * plain_text
Definition: ald_crypt.h:177
crypt_handle_s::state
crypt_state_t state
Definition: ald_crypt.h:188
crypt_handle_s::size
uint32_t size
Definition: ald_crypt.h:179
CRYPT_DMA_DISABLE
#define CRYPT_DMA_DISABLE(handle)
Definition: ald_crypt.h:208
crypt_handle_s::cipher_text
uint8_t * cipher_text
Definition: ald_crypt.h:178
CRYPT_STATE_READY
Definition: ald_crypt.h:125
crypt_handle_s::count
uint32_t count
Definition: ald_crypt.h:180
crypt_handle_s
CRYPT Handle Structure definition.
Definition: ald_crypt.h:170

◆ crypt_dma_error()

static void crypt_dma_error ( void * arg )
static

DMA CRYPT communication error callback.

Parameters
arg Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
Return values
None

Definition at line 1122 of file ald_crypt.c.

1123 {
1124 crypt_handle_t *hperh = (crypt_handle_t *)arg;
1125 CRYPT_DMA_DISABLE(hperh);
1126
1127 hperh->count = 0;
1128 hperh->plain_text = NULL;
1129 hperh->cipher_text = NULL;
1130 hperh->size = 0;
1131
1132 hperh->state = CRYPT_STATE_READY;
1133
1134 if (hperh->err_cplt_cbk)
1135 hperh->err_cplt_cbk(hperh);
1136 }
crypt_handle_s::err_cplt_cbk
void(* err_cplt_cbk)(struct crypt_handle_s *arg)
Definition: ald_crypt.h:191
crypt_handle_s::plain_text
uint8_t * plain_text
Definition: ald_crypt.h:177
crypt_handle_s::state
crypt_state_t state
Definition: ald_crypt.h:188
crypt_handle_s::size
uint32_t size
Definition: ald_crypt.h:179
CRYPT_DMA_DISABLE
#define CRYPT_DMA_DISABLE(handle)
Definition: ald_crypt.h:208
crypt_handle_s::cipher_text
uint8_t * cipher_text
Definition: ald_crypt.h:178
CRYPT_STATE_READY
Definition: ald_crypt.h:125
crypt_handle_s::count
uint32_t count
Definition: ald_crypt.h:180
crypt_handle_s
CRYPT Handle Structure definition.
Definition: ald_crypt.h:170

◆ crypt_reset()

void crypt_reset ( crypt_handle_t * hperh )

Reset the CRYPT peripheral.

Parameters
hperh Pointer to a crypt_handle_t structure that contains the configuration information for the specified CRYPT module.
Return values
None

Definition at line 1069 of file ald_crypt.c.

1070 {
1071 hperh->perh->DATA[0] = 0x0;
1072 hperh->perh->DATA[1] = 0x0;
1073 hperh->perh->DATA[2] = 0x0;
1074 hperh->perh->DATA[3] = 0x0;
1075 hperh->perh->KEY[0] = 0x0;
1076 hperh->perh->KEY[1] = 0x0;
1077 hperh->perh->KEY[2] = 0x0;
1078 hperh->perh->KEY[3] = 0x0;
1079 hperh->perh->KEY[4] = 0x0;
1080 hperh->perh->KEY[5] = 0x0;
1081 hperh->perh->KEY[6] = 0x0;
1082 hperh->perh->KEY[7] = 0x0;
1083 hperh->perh->IV[0] = 0x0;
1084 hperh->perh->IV[1] = 0x0;
1085 hperh->perh->IV[2] = 0x0;
1086 hperh->perh->IV[3] = 0x0;
1087 hperh->perh->CON = 0x0;
1088
1089 hperh->state = CRYPT_STATE_READY;
1090 __UNLOCK(hperh);
1091 }
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
crypt_handle_s::state
crypt_state_t state
Definition: ald_crypt.h:188
crypt_handle_s::perh
CRYPT_TypeDef * perh
Definition: ald_crypt.h:171
CRYPT_STATE_READY
Definition: ald_crypt.h:125


ALD User Manual: CRYPT Public Types

Data Structures | Typedefs | Enumerations
CRYPT Public Types
EASTSOFT ES32F3xx ALD » CRYPT
Collaboration diagram for CRYPT Public Types:

Data Structures

struct | crypt_init_t
CRYPT init structure definition. More...
struct | crypt_handle_s
CRYPT Handle Structure definition. More...

Typedefs

typedef struct crypt_handle_s crypt_handle_t
CRYPT Handle Structure definition. More...

Enumerations

enum | crypt_encs_t { CRYPT_DECRYPT = 0U, CRYPT_ENCRYPT = 1U }
CRYPT encrypt or decrypt select. More...
enum | crypt_aesks_t { CRYPT_BITS_128 = 0U, CRYPT_BITS_192 = 1U, CRYPT_BITS_256 = 2U }
CRYPT aes key select. More...
enum | crypt_mode_t { CRYPT_MODE_ECB = 0U, CRYPT_MODE_CBC = 1U, CRYPT_MODE_CTR = 2U }
CRYPT mode select. More...
enum | crypt_datatype_t { CRYPT_DATA_CHANGE_NO = 0U, CRYPT_DATA_CHANGE_16 = 1U, CRYPT_DATA_CHANGE_8 = 2U, CRYPT_DATA_CHANGE_1 = 3U }
CRYPT data type. More...
enum | crypt_desks_t { CRYPT_KEYS_2 = 0U, CRYPT_KEYS_3 = 1U, CRYPT_KEYS_1 = 2U }
CRYPT des key select. More...
enum | crypt_crysel_t { CRYPT_CRYSEL_AES = 0U, CRYPT_CRYSEL_DES = 1U }
CRYPT crypt select. More...
enum | crypt_it_t { CRYPT_IT_IT = 0x80U }
CRYPT interrupt. More...
enum | crypt_flag_t { CRYPT_FLAG_AESIF = 0x1U, CRYPT_FLAG_DESIF = 0x2U, CRYPT_FLAG_DONE = 0x100U }
CRYPT interrupt flag. More...
enum crypt_ks_t {
CRYPT_AES_BITS_128 = 0x4U, CRYPT_AES_BITS_192 = 0x6U, CRYPT_AES_BITS_256 = 0x8U, CRYPT_DES_KEYS_1 = 0x12U,
CRYPT_DES_KEYS_2 = 0x14U, CRYPT_DES_KEYS_3 = 0x16U
}
CRYPT key select. More...
enum | crypt_state_t { CRYPT_STATE_RESET = 0x0U, CRYPT_STATE_READY = 0x1U, CRYPT_STATE_BUSY = 0x2U, CRYPT_STATE_ERROR = 0x4U }
CRYPT state structures definition. More...
enum | crypt_key_len_t { KEY_2_LEN = 2U, KEY_4_LEN = 4U, KEY_6_LEN = 6U, KEY_8_LEN = 8U }
CRYPT key length. More...
enum | crypt_ivr_len_t { IV_2_LEN = 2U, IV_4_LEN = 4U }
CRYPT iv length. More...
enum | crypt_data_t { DATA_32_BIT = 0U, DATA_16_BIT = 1U, DATA_8_BIT = 2U, DATA_1_BIT = 3U }
CRYPT data type. More...

Detailed Description

Typedef Documentation

◆ crypt_handle_t

typedef struct crypt_handle_s crypt_handle_t

CRYPT Handle Structure definition.

Enumeration Type Documentation

◆ crypt_aesks_t

enum crypt_aesks_t

CRYPT aes key select.

Enumerator
CRYPT_BITS_128 | 128bit key for aes
CRYPT_BITS_192 | 192bit key for aes
CRYPT_BITS_256 | 256bit key for aes

Definition at line 50 of file ald_crypt.h.

50 {
51 CRYPT_BITS_128 = 0U,
52 CRYPT_BITS_192 = 1U,
53 CRYPT_BITS_256 = 2U,
54 } crypt_aesks_t;
CRYPT_BITS_128
Definition: ald_crypt.h:51
CRYPT_BITS_192
Definition: ald_crypt.h:52
crypt_aesks_t
crypt_aesks_t
CRYPT aes key select.
Definition: ald_crypt.h:50
CRYPT_BITS_256
Definition: ald_crypt.h:53

◆ crypt_crysel_t

enum crypt_crysel_t

CRYPT crypt select.

Enumerator
CRYPT_CRYSEL_AES | AES
CRYPT_CRYSEL_DES | DES

Definition at line 87 of file ald_crypt.h.

87 {
88 CRYPT_CRYSEL_AES = 0U,
89 CRYPT_CRYSEL_DES = 1U,
90 } crypt_crysel_t;
crypt_crysel_t
crypt_crysel_t
CRYPT crypt select.
Definition: ald_crypt.h:87
CRYPT_CRYSEL_DES
Definition: ald_crypt.h:89
CRYPT_CRYSEL_AES
Definition: ald_crypt.h:88

◆ crypt_data_t

enum crypt_data_t

CRYPT data type.

Enumerator
DATA_32_BIT | 32 bit data,don't swap
DATA_16_BIT | 16 bit data,swap
DATA_8_BIT | 8 bit data,swap
DATA_1_BIT | 1 bit data, swap

Definition at line 151 of file ald_crypt.h.

151 {
152 DATA_32_BIT = 0U,
153 DATA_16_BIT = 1U,
154 DATA_8_BIT = 2U,
155 DATA_1_BIT = 3U,
156 } crypt_data_t;
DATA_16_BIT
Definition: ald_crypt.h:153
DATA_8_BIT
Definition: ald_crypt.h:154
DATA_32_BIT
Definition: ald_crypt.h:152
crypt_data_t
crypt_data_t
CRYPT data type.
Definition: ald_crypt.h:151
DATA_1_BIT
Definition: ald_crypt.h:155

◆ crypt_datatype_t

enum crypt_datatype_t

CRYPT data type.

Enumerator
CRYPT_DATA_CHANGE_NO | No exchange
CRYPT_DATA_CHANGE_16 | 16bit exchange
CRYPT_DATA_CHANGE_8 | 8bit exchange
CRYPT_DATA_CHANGE_1 | 1bit exchange

Definition at line 68 of file ald_crypt.h.

68 {
69 CRYPT_DATA_CHANGE_NO = 0U,
70 CRYPT_DATA_CHANGE_16 = 1U,
71 CRYPT_DATA_CHANGE_8 = 2U,
72 CRYPT_DATA_CHANGE_1 = 3U,
73 } crypt_datatype_t;
CRYPT_DATA_CHANGE_8
Definition: ald_crypt.h:71
CRYPT_DATA_CHANGE_NO
Definition: ald_crypt.h:69
CRYPT_DATA_CHANGE_1
Definition: ald_crypt.h:72
crypt_datatype_t
crypt_datatype_t
CRYPT data type.
Definition: ald_crypt.h:68
CRYPT_DATA_CHANGE_16
Definition: ald_crypt.h:70

◆ crypt_desks_t

enum crypt_desks_t

CRYPT des key select.

Enumerator
CRYPT_KEYS_2 | 2 key for des
CRYPT_KEYS_3 | 3 key for des
CRYPT_KEYS_1 | 1 key for des

Definition at line 78 of file ald_crypt.h.

78 {
79 CRYPT_KEYS_2 = 0U,
80 CRYPT_KEYS_3 = 1U,
81 CRYPT_KEYS_1 = 2U,
82 } crypt_desks_t;
CRYPT_KEYS_2
Definition: ald_crypt.h:79
crypt_desks_t
crypt_desks_t
CRYPT des key select.
Definition: ald_crypt.h:78
CRYPT_KEYS_3
Definition: ald_crypt.h:80
CRYPT_KEYS_1
Definition: ald_crypt.h:81

◆ crypt_encs_t

enum crypt_encs_t

CRYPT encrypt or decrypt select.

Enumerator
CRYPT_DECRYPT | Decrypt
CRYPT_ENCRYPT | Encrypt

Definition at line 42 of file ald_crypt.h.

42 {
43 CRYPT_DECRYPT = 0U,
44 CRYPT_ENCRYPT = 1U,
45 } crypt_encs_t;
CRYPT_ENCRYPT
Definition: ald_crypt.h:44
crypt_encs_t
crypt_encs_t
CRYPT encrypt or decrypt select.
Definition: ald_crypt.h:42
CRYPT_DECRYPT
Definition: ald_crypt.h:43

◆ crypt_flag_t

enum crypt_flag_t

CRYPT interrupt flag.

Enumerator
CRYPT_FLAG_AESIF | Aes flag
CRYPT_FLAG_DESIF | Des flag
CRYPT_FLAG_DONE | Complete flag

Definition at line 102 of file ald_crypt.h.

102 {
103 CRYPT_FLAG_AESIF = 0x1U,
104 CRYPT_FLAG_DESIF = 0x2U,
105 CRYPT_FLAG_DONE = 0x100U,
106 } crypt_flag_t;
CRYPT_FLAG_AESIF
Definition: ald_crypt.h:103
CRYPT_FLAG_DONE
Definition: ald_crypt.h:105
CRYPT_FLAG_DESIF
Definition: ald_crypt.h:104
crypt_flag_t
crypt_flag_t
CRYPT interrupt flag.
Definition: ald_crypt.h:102

◆ crypt_it_t

enum crypt_it_t

CRYPT interrupt.

Enumerator
CRYPT_IT_IT

Interrupt

Definition at line 95 of file ald_crypt.h.

95 {
96 CRYPT_IT_IT = 0x80U,
97 } crypt_it_t;
CRYPT_IT_IT
Definition: ald_crypt.h:96
crypt_it_t
crypt_it_t
CRYPT interrupt.
Definition: ald_crypt.h:95

◆ crypt_ivr_len_t

enum crypt_ivr_len_t

CRYPT iv length.

Enumerator
IV_2_LEN | iv's lenth is 2
IV_4_LEN | iv's lenth is 4

Definition at line 143 of file ald_crypt.h.

143 {
144 IV_2_LEN = 2U,
145 IV_4_LEN = 4U,
146 } crypt_ivr_len_t;
IV_2_LEN
Definition: ald_crypt.h:144
IV_4_LEN
Definition: ald_crypt.h:145
crypt_ivr_len_t
crypt_ivr_len_t
CRYPT iv length.
Definition: ald_crypt.h:143

◆ crypt_key_len_t

enum crypt_key_len_t

CRYPT key length.

Enumerator
KEY_2_LEN | Key's lenth is 2
KEY_4_LEN | Key's lenth is 4
KEY_6_LEN | Key's lenth is 6
KEY_8_LEN | Key's lenth is 8

Definition at line 133 of file ald_crypt.h.

133 {
134 KEY_2_LEN = 2U,
135 KEY_4_LEN = 4U,
136 KEY_6_LEN = 6U,
137 KEY_8_LEN = 8U,
138 } crypt_key_len_t;
KEY_6_LEN
Definition: ald_crypt.h:136
KEY_8_LEN
Definition: ald_crypt.h:137
KEY_4_LEN
Definition: ald_crypt.h:135
KEY_2_LEN
Definition: ald_crypt.h:134
crypt_key_len_t
crypt_key_len_t
CRYPT key length.
Definition: ald_crypt.h:133

◆ crypt_ks_t

enum crypt_ks_t

CRYPT key select.

Enumerator
CRYPT_AES_BITS_128 | 128bit key of aes
CRYPT_AES_BITS_192 | 192bit key of aes
CRYPT_AES_BITS_256 | 192bit key of ase
CRYPT_DES_KEYS_1 | 1 key of des
CRYPT_DES_KEYS_2 | 2 key of des
CRYPT_DES_KEYS_3 | 3 key of des

Definition at line 111 of file ald_crypt.h.

111 {
112 CRYPT_AES_BITS_128 = 0x4U,
113 CRYPT_AES_BITS_192 = 0x6U,
114 CRYPT_AES_BITS_256 = 0x8U,
115 CRYPT_DES_KEYS_1 = 0x12U,
116 CRYPT_DES_KEYS_2 = 0x14U,
117 CRYPT_DES_KEYS_3 = 0x16U,
118 } crypt_ks_t;
CRYPT_DES_KEYS_3
Definition: ald_crypt.h:117
crypt_ks_t
crypt_ks_t
CRYPT key select.
Definition: ald_crypt.h:111
CRYPT_AES_BITS_128
Definition: ald_crypt.h:112
CRYPT_AES_BITS_256
Definition: ald_crypt.h:114
CRYPT_AES_BITS_192
Definition: ald_crypt.h:113
CRYPT_DES_KEYS_2
Definition: ald_crypt.h:116
CRYPT_DES_KEYS_1
Definition: ald_crypt.h:115

◆ crypt_mode_t

enum crypt_mode_t

CRYPT mode select.

Enumerator
CRYPT_MODE_ECB | ECB
CRYPT_MODE_CBC | CBC
CRYPT_MODE_CTR | CTR

Definition at line 59 of file ald_crypt.h.

59 {
60 CRYPT_MODE_ECB = 0U,
61 CRYPT_MODE_CBC = 1U,
62 CRYPT_MODE_CTR = 2U,
63 } crypt_mode_t;
CRYPT_MODE_CBC
Definition: ald_crypt.h:61
crypt_mode_t
crypt_mode_t
CRYPT mode select.
Definition: ald_crypt.h:59
CRYPT_MODE_ECB
Definition: ald_crypt.h:60
CRYPT_MODE_CTR
Definition: ald_crypt.h:62

◆ crypt_state_t

enum crypt_state_t

CRYPT state structures definition.

Enumerator
CRYPT_STATE_RESET | Peripheral is not initialized
CRYPT_STATE_READY | Peripheral Initialized and ready for use
CRYPT_STATE_BUSY | An internal process is ongoing
CRYPT_STATE_ERROR | Error

Definition at line 123 of file ald_crypt.h.

123 {
124 CRYPT_STATE_RESET = 0x0U,
125 CRYPT_STATE_READY = 0x1U,
126 CRYPT_STATE_BUSY = 0x2U,
127 CRYPT_STATE_ERROR = 0x4U,
128 } crypt_state_t;
CRYPT_STATE_RESET
Definition: ald_crypt.h:124
CRYPT_STATE_BUSY
Definition: ald_crypt.h:126
CRYPT_STATE_ERROR
Definition: ald_crypt.h:127
crypt_state_t
crypt_state_t
CRYPT state structures definition.
Definition: ald_crypt.h:123
CRYPT_STATE_READY
Definition: ald_crypt.h:125


ALD User Manual: crypt_init_t Struct Reference

Data Fields
crypt_init_t Struct Reference
EASTSOFT ES32F3xx ALD » CRYPT » CRYPT Public Types

CRYPT init structure definition. More...

#include <ald_crypt.h>

Data Fields

crypt_mode_t mode
crypt_data_t type
crypt_ks_t key

Detailed Description

CRYPT init structure definition.

Definition at line 161 of file ald_crypt.h.

Field Documentation

◆ key

crypt_ks_t key

Key select

Definition at line 164 of file ald_crypt.h.

◆ mode

crypt_mode_t mode

Crypt mode

Definition at line 162 of file ald_crypt.h.

◆ type

crypt_data_t type

Data type select

Definition at line 163 of file ald_crypt.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_crypt.h


ALD User Manual: crypt_handle_s Struct Reference

Data Fields
crypt_handle_s Struct Reference
EASTSOFT ES32F3xx ALD » CRYPT » CRYPT Public Types

CRYPT Handle Structure definition. More...

#include <ald_crypt.h>

Collaboration diagram for crypt_handle_s:
[legend]

Data Fields

CRYPT_TypeDef * | perh
crypt_init_t init
dma_handle_t hdma_m2p
dma_handle_t hdma_p2m
uint8_t * | plain_text
uint8_t * | cipher_text
uint32_t | size
uint32_t | count
uint32_t | step
uint32_t | dir
uint32_t | iv [4]
uint32_t | iv_size
uint32_t | key [8]
uint32_t | key_size
lock_state_t lock
crypt_state_t state
void(* | crypt_cplt_cbk )(struct crypt_handle_s *arg)
void(* | err_cplt_cbk )(struct crypt_handle_s *arg)

Detailed Description

CRYPT Handle Structure definition.

Definition at line 170 of file ald_crypt.h.

Field Documentation

◆ cipher_text

uint8_t* cipher_text

Pointer to cipher text

Definition at line 178 of file ald_crypt.h.

◆ count

uint32_t count

The count of crypt data buf

Definition at line 180 of file ald_crypt.h.

◆ crypt_cplt_cbk

void(* crypt_cplt_cbk) (struct crypt_handle_s *arg)

Crypt completed callback

Definition at line 190 of file ald_crypt.h.

◆ dir

uint32_t dir

ENCRYPT or DECRYPT

Definition at line 182 of file ald_crypt.h.

◆ err_cplt_cbk

void(* err_cplt_cbk) (struct crypt_handle_s *arg)

Crypt error callback

Definition at line 191 of file ald_crypt.h.

◆ hdma_m2p

dma_handle_t hdma_m2p

CRYPT DMA handle parameters memory to crypt module

Definition at line 174 of file ald_crypt.h.

◆ hdma_p2m

dma_handle_t hdma_p2m

CRYPT DMA handle parameters crypt module to memory

Definition at line 175 of file ald_crypt.h.

◆ init

crypt_init_t init

CRYPT required parameters

Definition at line 172 of file ald_crypt.h.

◆ iv

uint32_t iv[4]

The iv of crypt

Definition at line 183 of file ald_crypt.h.

◆ iv_size

uint32_t iv_size

The iv size

Definition at line 184 of file ald_crypt.h.

◆ key

uint32_t key[8]

The key of crypt

Definition at line 185 of file ald_crypt.h.

◆ key_size

uint32_t key_size

The key size

Definition at line 186 of file ald_crypt.h.

◆ lock

lock_state_t lock

Locking object

Definition at line 187 of file ald_crypt.h.

◆ perh

CRYPT_TypeDef* perh

Register base address

Definition at line 171 of file ald_crypt.h.

◆ plain_text

uint8_t* plain_text

Pointer to plain text

Definition at line 177 of file ald_crypt.h.

◆ size

uint32_t size

The size of crypt data buf

Definition at line 179 of file ald_crypt.h.

◆ state

crypt_state_t state

CRYPT operation state

Definition at line 188 of file ald_crypt.h.

◆ step

uint32_t step

The step of once crypt 2(des) or 4(aes)

Definition at line 181 of file ald_crypt.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_crypt.h


ALD User Manual: CRYPT Public Macros

Macros
CRYPT Public Macros
EASTSOFT ES32F3xx ALD » CRYPT
Collaboration diagram for CRYPT Public Macros:

Macros

#define | CRYPT_GO(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK))
#define | CRYPT_FIFOEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
#define | CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
#define | CRYPT_IVEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
#define | CRYPT_IVEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
#define | CRYPT_IE_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK))
#define | CRYPT_IE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK))
#define | CRYPT_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))
#define | CRYPT_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))
#define | CRYPT_SETDIR(handle, dir)
#define | CRYPT_WRITE_FIFO(handle, data) ((handle)->perh->FIFO = (data))
#define | CRYPT_READ_FIFO(handle) ((handle)->perh->FIFO)

Detailed Description

Macro Definition Documentation

◆ CRYPT_DMA_DISABLE

#define CRYPT_DMA_DISABLE ( handle ) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))

Definition at line 208 of file ald_crypt.h.

◆ CRYPT_DMA_ENABLE

#define CRYPT_DMA_ENABLE ( handle ) (SET_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))

Definition at line 207 of file ald_crypt.h.

◆ CRYPT_FIFOEN_DISABLE

#define CRYPT_FIFOEN_DISABLE ( handle ) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))

Definition at line 202 of file ald_crypt.h.

◆ CRYPT_FIFOEN_ENABLE

#define CRYPT_FIFOEN_ENABLE ( handle ) (SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))

Definition at line 201 of file ald_crypt.h.

◆ CRYPT_GO

#define CRYPT_GO ( handle ) (SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK))

Definition at line 200 of file ald_crypt.h.

◆ CRYPT_IE_DISABLE

#define CRYPT_IE_DISABLE ( handle ) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK))

Definition at line 206 of file ald_crypt.h.

◆ CRYPT_IE_ENABLE

#define CRYPT_IE_ENABLE ( handle ) (SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK))

Definition at line 205 of file ald_crypt.h.

◆ CRYPT_IVEN_DISABLE

#define CRYPT_IVEN_DISABLE ( handle ) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))

Definition at line 204 of file ald_crypt.h.

◆ CRYPT_IVEN_ENABLE

#define CRYPT_IVEN_ENABLE ( handle ) (SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))

Definition at line 203 of file ald_crypt.h.

◆ CRYPT_READ_FIFO

#define CRYPT_READ_FIFO ( handle ) ((handle)->perh->FIFO)

Definition at line 212 of file ald_crypt.h.

◆ CRYPT_SETDIR

#define CRYPT_SETDIR | ( | handle,
 |  | dir
 | ) |
Value:
do {(handle)->perh->CON &= ~(0x1 << CRYPT_CON_ENCS_POS); \
(handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0)

Definition at line 209 of file ald_crypt.h.

◆ CRYPT_WRITE_FIFO

#define CRYPT_WRITE_FIFO | ( | handle,
 |  | data
 | ) | ((handle)->perh->FIFO = (data))

Definition at line 211 of file ald_crypt.h.


ALD User Manual: CRYPT Private Macros

Macros
CRYPT Private Macros
EASTSOFT ES32F3xx ALD » CRYPT
Collaboration diagram for CRYPT Private Macros:

Macros

#define | IS_CRYPT(x) ((x) == CRYPT)
#define | IS_CRYPT_MODE(x)
#define | IS_CRYPT_KS(x)
#define | IS_CRYPT_IT(x) ((x) == CRYPT_IT_IT)
#define | IS_CRYPT_FLAG(x)
#define | IS_CRYPT_IV_LEN(x)
#define | IS_CRYPT_KEY_LEN(x)

Detailed Description

Macro Definition Documentation

◆ IS_CRYPT

#define IS_CRYPT ( x ) ((x) == CRYPT)

Definition at line 220 of file ald_crypt.h.

◆ IS_CRYPT_FLAG

#define IS_CRYPT_FLAG ( x )
Value:
(((x) == CRYPT_FLAG_AESIF) || \
((x) == CRYPT_FLAG_DESIF) || \
((x) == CRYPT_FLAG_DONE))
CRYPT_FLAG_AESIF
Definition: ald_crypt.h:103
CRYPT_FLAG_DONE
Definition: ald_crypt.h:105
CRYPT_FLAG_DESIF
Definition: ald_crypt.h:104

Definition at line 231 of file ald_crypt.h.

◆ IS_CRYPT_IT

#define IS_CRYPT_IT ( x ) ((x) == CRYPT_IT_IT)

Definition at line 230 of file ald_crypt.h.

◆ IS_CRYPT_IV_LEN

#define IS_CRYPT_IV_LEN ( x )
Value:
(((x) == IV_2_LEN) || \
((x) == IV_4_LEN))
IV_2_LEN
Definition: ald_crypt.h:144
IV_4_LEN
Definition: ald_crypt.h:145

Definition at line 234 of file ald_crypt.h.

◆ IS_CRYPT_KEY_LEN

#define IS_CRYPT_KEY_LEN ( x )
Value:
(((x) == KEY_2_LEN) || \
((x) == KEY_4_LEN) || \
((x) == KEY_6_LEN) || \
((x) == KEY_8_LEN))
KEY_6_LEN
Definition: ald_crypt.h:136
KEY_8_LEN
Definition: ald_crypt.h:137
KEY_4_LEN
Definition: ald_crypt.h:135
KEY_2_LEN
Definition: ald_crypt.h:134

Definition at line 236 of file ald_crypt.h.

◆ IS_CRYPT_KS

#define IS_CRYPT_KS ( x )
Value:
(((x) == CRYPT_AES_BITS_128) || \
((x) == CRYPT_AES_BITS_192) || \
((x) == CRYPT_AES_BITS_256) || \
((x) == CRYPT_DES_KEYS_1) || \
((x) == CRYPT_DES_KEYS_2) || \
((x) == CRYPT_DES_KEYS_3))
CRYPT_DES_KEYS_3
Definition: ald_crypt.h:117
CRYPT_AES_BITS_128
Definition: ald_crypt.h:112
CRYPT_AES_BITS_256
Definition: ald_crypt.h:114
CRYPT_AES_BITS_192
Definition: ald_crypt.h:113
CRYPT_DES_KEYS_2
Definition: ald_crypt.h:116
CRYPT_DES_KEYS_1
Definition: ald_crypt.h:115

Definition at line 224 of file ald_crypt.h.

◆ IS_CRYPT_MODE

#define IS_CRYPT_MODE ( x )
Value:
(((x) == CRYPT_MODE_ECB) || \
((x) == CRYPT_MODE_CBC) || \
((x) == CRYPT_MODE_CTR))
CRYPT_MODE_CBC
Definition: ald_crypt.h:61
CRYPT_MODE_ECB
Definition: ald_crypt.h:60
CRYPT_MODE_CTR
Definition: ald_crypt.h:62

Definition at line 221 of file ald_crypt.h.


ALD User Manual: DAC

Modules
DAC
EASTSOFT ES32F3xx ALD

DAC module driver. More...

Collaboration diagram for DAC:

Modules

DAC Public Functions
DAC Pubulic Types
DAC Public Macros
DAC Private Macros

Detailed Description

DAC module driver.


ALD User Manual: DAC Public Functions

Functions
DAC Public Functions
EASTSOFT ES32F3xx ALD » DAC
Collaboration diagram for DAC Public Functions:

Functions

ald_status_t | ald_dac_reset (dac_handle_t *hperh)
Reset the dac mode. More...
ald_status_t | ald_dac_init (dac_handle_t *hperh)
Initializes the DAC peripheral. More...
ald_status_t | ald_dac_channel_config (dac_handle_t *hperh, dac_channel_config_t *config, dac_channel_t ch)
Configure dac channel. More...
void | ald_dac_output_set (dac_handle_t *hperh, dac_channel_t ch, uint32_t value)
Set dac channel output value. More...
flag_status_t | ald_dac_get_status (dac_handle_t *hperh, dac_status_t status)
Checks whether the specified DAC flag is set or not. More...
void | ald_dac_interrupt_config (dac_handle_t *hperh, dac_it_t it, type_func_t state)
Enable or disable the specified interrupt. More...
it_status_t | ald_dac_get_it_status (dac_handle_t *hperh, dac_it_t it)
Get the status of DAC interrupt source. More...
flag_status_t | ald_dac_get_flag_status (dac_handle_t *hperh, dac_flag_t flag)
Checks whether the specified interrupt has occurred or not. More...
flag_status_t | ald_dac_get_mask_flag_status (dac_handle_t *hperh, dac_flag_t flag)
Get the status of interrupt flag and interupt source. More...
void | ald_dac_clear_flag_status (dac_handle_t *hperh, dac_flag_t flag)
Clear interrupt state flag. More...
void | ald_dac_irq_handler (dac_handle_t *hperh)
This function handles DAC event interrupt request. More...

Detailed Description

Function Documentation

◆ ald_dac_channel_config()

ald_status_t ald_dac_channel_config | ( | dac_handle_t * | hperh,
 |  | dac_channel_config_t * | config,
 |  | dac_channel_t | ch
 | ) |  |

Configure dac channel.

Parameters
hperh | Pointer to a dac_handle_t structure that contains the configuration information for the specified DAC module.
config | Pointer to a dac_channel_config_t structure that contains the configutation information for dac channel.
ch | Specifies which dac channel to be config.
Return values
Status,see ald_status_t.

Definition at line 112 of file ald_dac.c.

113 {
114 uint32_t tmp;
115
116 if ((hperh == NULL) || (config == NULL))
117 return ERROR;
118
119 assert_param(IS_DAC_TYPE(hperh->perh));
120 assert_param(IS_FUNC_STATE(config->enable));
121 assert_param(IS_DAC_TRIGGER_TYPE(config->trigger));
122 assert_param(IS_FUNC_STATE(config->refresh_en));
123 assert_param(IS_DAC_PISSEL_CH_TYPE(config->pis_ch));
124
125 __LOCK(hperh);
126 tmp = ((config->pis_ch << DAC_CH0CTRL_PISSEL_POSS) | (config->trigger << DAC_CH0CTRL_PISEN_POS) |
127 (config->refresh_en << DAC_CH0CTRL_RCYCLEN_POS) | (config->enable << DAC_CH0CTRL_EN_POS));
128
129 switch (ch) {
130 case DAC_CHANNEL_0:
131 hperh->perh->CH0CTRL = tmp;
132 break;
133
134 case DAC_CHANNEL_1:
135 hperh->perh->CH1CTRL = tmp;
136 break;
137
138 default:
139 break;
140 }
141
142 __UNLOCK(hperh);
143 return OK;
144 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
DAC_CHANNEL_0
Definition: ald_dac.h:42
dac_handle_s::perh
DAC_TypeDef * perh
Definition: ald_dac.h:192
dac_channel_config_t::trigger
dac_trigger_t trigger
Definition: ald_dac.h:183
IS_DAC_PISSEL_CH_TYPE
#define IS_DAC_PISSEL_CH_TYPE(x)
Definition: ald_dac.h:258
DAC_CHANNEL_1
Definition: ald_dac.h:43
IS_DAC_TYPE
#define IS_DAC_TYPE(x)
Definition: ald_dac.h:221
dac_channel_config_t::enable
type_func_t enable
Definition: ald_dac.h:182
__LOCK
#define __LOCK(x)
Definition: utils.h:92
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
ERROR
Definition: utils.h:56
IS_DAC_TRIGGER_TYPE
#define IS_DAC_TRIGGER_TYPE(x)
Definition: ald_dac.h:272
dac_channel_config_t::pis_ch
dac_pissel_t pis_ch
Definition: ald_dac.h:185
dac_channel_config_t::refresh_en
type_func_t refresh_en
Definition: ald_dac.h:184

◆ ald_dac_clear_flag_status()

void ald_dac_clear_flag_status | ( | dac_handle_t * | hperh,
 |  | dac_flag_t | flag
 | ) |  |

Clear interrupt state flag.

Parameters
hperh | Pointer to a dac_handle_t structure that contains the configuration information for the specified DAC.
flag | Specifies the interrupt type to clear
Return values
None

Definition at line 277 of file ald_dac.c.

278 {
279 assert_param(IS_DAC_TYPE(hperh->perh));
280 assert_param(IS_DAC_FLAG_TYPE(flag));
281
282 hperh->perh->IFC = flag;
283 return;
284 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_DAC_FLAG_TYPE
#define IS_DAC_FLAG_TYPE(x)
Definition: ald_dac.h:254
dac_handle_s::perh
DAC_TypeDef * perh
Definition: ald_dac.h:192
IS_DAC_TYPE
#define IS_DAC_TYPE(x)
Definition: ald_dac.h:221

◆ ald_dac_get_flag_status()

flag_status_t ald_dac_get_flag_status | ( | dac_handle_t * | hperh,
 |  | dac_flag_t | flag
 | ) |  |

Checks whether the specified interrupt has occurred or not.

Parameters
hperh | Pointer to a dac_handle_t structure that contains the configuration information for the specified DAC.
flag | Specifies the interrupt type to check.
Return values
The new state.

Definition at line 245 of file ald_dac.c.

246 {
247 assert_param(IS_DAC_TYPE(hperh->perh));
248 assert_param(IS_DAC_FLAG_TYPE(flag));
249
250 return hperh->perh->RIF & flag ? SET : RESET;
251 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_DAC_FLAG_TYPE
#define IS_DAC_FLAG_TYPE(x)
Definition: ald_dac.h:254
SET
Definition: type.h:39
dac_handle_s::perh
DAC_TypeDef * perh
Definition: ald_dac.h:192
RESET
Definition: type.h:38
IS_DAC_TYPE
#define IS_DAC_TYPE(x)
Definition: ald_dac.h:221

◆ ald_dac_get_it_status()

it_status_t ald_dac_get_it_status | ( | dac_handle_t * | hperh,
 |  | dac_it_t | it
 | ) |  |

Get the status of DAC interrupt source.

Parameters
hperh | Pointer to a dac_handle_t structure that contains the configuration information for the specified DAC.
it | Specifies the DAC interrupt source.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 230 of file ald_dac.c.

231 {
232 assert_param(IS_DAC_TYPE(hperh->perh));
233 assert_param(IS_DAC_INTERRUPT_TYPE(it));
234
235 return hperh->perh->IEV & it ? SET : RESET;
236 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
dac_handle_s::perh
DAC_TypeDef * perh
Definition: ald_dac.h:192
RESET
Definition: type.h:38
IS_DAC_INTERRUPT_TYPE
#define IS_DAC_INTERRUPT_TYPE(x)
Definition: ald_dac.h:250
IS_DAC_TYPE
#define IS_DAC_TYPE(x)
Definition: ald_dac.h:221

◆ ald_dac_get_mask_flag_status()

flag_status_t ald_dac_get_mask_flag_status | ( | dac_handle_t * | hperh,
 |  | dac_flag_t | flag
 | ) |  |

Get the status of interrupt flag and interupt source.

Parameters
hperh | Pointer to a dac_handle_t structure that contains the configuration information for the specified DAC.
flag | Specifies the DAC interrupt flag.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 262 of file ald_dac.c.

263 {
264 assert_param(IS_DAC_TYPE(hperh->perh));
265 assert_param(IS_DAC_FLAG_TYPE(flag));
266
267 return hperh->perh->IFM & flag ? SET : RESET;
268 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_DAC_FLAG_TYPE
#define IS_DAC_FLAG_TYPE(x)
Definition: ald_dac.h:254
SET
Definition: type.h:39
dac_handle_s::perh
DAC_TypeDef * perh
Definition: ald_dac.h:192
RESET
Definition: type.h:38
IS_DAC_TYPE
#define IS_DAC_TYPE(x)
Definition: ald_dac.h:221

◆ ald_dac_get_status()

flag_status_t ald_dac_get_status | ( | dac_handle_t * | hperh,
 |  | dac_status_t | status
 | ) |  |

Checks whether the specified DAC flag is set or not.

Parameters
hperh | Pointer to a dac_handle_t structure that contains the configuration information for the specified dac.
status | Specifies the flag to check.
Return values
The new state.

Definition at line 186 of file ald_dac.c.

187 {
188 assert_param(IS_DAC_TYPE(hperh->perh));
189 assert_param(IS_DAC_STATUS_TYPE(status));
190
191 return hperh->perh->STAT & status ? SET : RESET;
192 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
dac_handle_s::perh
DAC_TypeDef * perh
Definition: ald_dac.h:192
RESET
Definition: type.h:38
IS_DAC_STATUS_TYPE
#define IS_DAC_STATUS_TYPE(x)
Definition: ald_dac.h:270
IS_DAC_TYPE
#define IS_DAC_TYPE(x)
Definition: ald_dac.h:221

◆ ald_dac_init()

ald_status_t ald_dac_init ( dac_handle_t * hperh )

Initializes the DAC peripheral.

Parameters
hperh Pointer to a dac_handle_t structure that contains the configuration information for the specified DAC module.
Return values
Status,see ald_status_t.

Definition at line 59 of file ald_dac.c.

60 {
61 uint32_t tmp;
62
63 assert_param(IS_DAC_TYPE(hperh->perh));
64 assert_param(IS_DAC_CONVERT_TYPE(hperh->init.conv_mode));
65 assert_param(IS_DAC_OUTPUT_TYPE(hperh->init.out_mode));
66 assert_param(IS_DAC_NEG_REFRESH_TYPE(hperh->init.n_ref));
67 assert_param(IS_DAC_POS_REFRESH_TYPE(hperh->init.p_ref));
68 assert_param(IS_DAC_REFRESH_TYPE(hperh->init.refresh));
69 assert_param(IS_DAC_PRESCALE_TYPE(hperh->init.div));
70 assert_param(IS_FUNC_STATE(hperh->init.ch0_reset));
71 assert_param(IS_FUNC_STATE(hperh->init.o_ctrl_pis));
72 assert_param(IS_FUNC_STATE(hperh->init.sine));
73 assert_param(IS_FUNC_STATE(hperh->init.diff));
74
75 __LOCK(hperh);
76 ald_dac_reset(hperh);
77 DAC_CH0_DISABLE();
78 DAC_CH1_DISABLE();
79
80 MODIFY_REG(ADC0->CCR, ADC_CCR_VREFEN_MSK, 1 << ADC_CCR_VREFEN_POS);
81
82 if (hperh->init.p_ref == DAC_POS_REF_VREEFP_BUF || hperh->init.p_ref == DAC_POS_REF_2V)
83 SET_BIT(ADC0->CCR, (ADC_CCR_IREFEN_MSK | ADC_CCR_VRBUFEN_MSK | ADC_CCR_VCMBUFEN_MSK));
84
85 MODIFY_REG(ADC0->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS);
86 MODIFY_REG(ADC0->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POSS);
87
88 tmp = ((hperh->init.refresh << DAC_CON_RCYCLSEL_POSS) | (hperh->init.div << DAC_CON_PRES_POSS) |
89 (hperh->init.ch0_reset << DAC_CON_CH0PRESRST_POS) | ( hperh->init.o_ctrl_pis << DAC_CON_OUTENPIS_POS) |
90 (hperh->init.out_mode << DAC_CON_OUTMD_POSS) | (hperh->init.conv_mode << DAC_CON_CONVMD_POSS) |
91 (hperh->init.sine << DAC_CON_SINEMD_POS) | (hperh->init.diff << DAC_CON_DIFEN_POS));
92 hperh->perh->CON = tmp;
93
94 /* Automatic calibration */
95 SET_BIT(hperh->perh->CAL, DAC_CAL_SELF_CALEN_MSK);
96 for (tmp = 0; tmp < 1000; ++tmp);
97 CLEAR_BIT(hperh->perh->CAL, DAC_CAL_SELF_CALEN_MSK);
98
99 __UNLOCK(hperh);
100 return OK;
101 }
dac_init_t::conv_mode
dac_conv_mode_t conv_mode
Definition: ald_dac.h:166
DAC_CH0_DISABLE
#define DAC_CH0_DISABLE()
Definition: ald_dac.h:207
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
dac_init_t::n_ref
dac_neg_ref_t n_ref
Definition: ald_dac.h:174
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_DAC_NEG_REFRESH_TYPE
#define IS_DAC_NEG_REFRESH_TYPE(x)
Definition: ald_dac.h:229
dac_init_t::refresh
dac_refresh_t refresh
Definition: ald_dac.h:168
IS_DAC_POS_REFRESH_TYPE
#define IS_DAC_POS_REFRESH_TYPE(x)
Definition: ald_dac.h:231
ald_dac_reset
ald_status_t ald_dac_reset(dac_handle_t *hperh)
Reset the dac mode.
Definition: ald_dac.c:38
dac_handle_s::perh
DAC_TypeDef * perh
Definition: ald_dac.h:192
IS_DAC_REFRESH_TYPE
#define IS_DAC_REFRESH_TYPE(x)
Definition: ald_dac.h:235
IS_DAC_PRESCALE_TYPE
#define IS_DAC_PRESCALE_TYPE(x)
Definition: ald_dac.h:242
IS_DAC_CONVERT_TYPE
#define IS_DAC_CONVERT_TYPE(x)
Definition: ald_dac.h:222
dac_init_t::o_ctrl_pis
type_func_t o_ctrl_pis
Definition: ald_dac.h:171
dac_init_t::ch0_reset
type_func_t ch0_reset
Definition: ald_dac.h:170
dac_init_t::out_mode
dac_out_mode_t out_mode
Definition: ald_dac.h:167
dac_handle_s::init
dac_init_t init
Definition: ald_dac.h:193
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_DAC_OUTPUT_TYPE
#define IS_DAC_OUTPUT_TYPE(x)
Definition: ald_dac.h:225
DAC_POS_REF_VREEFP_BUF
Definition: ald_dac.h:99
DAC_POS_REF_2V
Definition: ald_dac.h:97
dac_init_t::diff
type_func_t diff
Definition: ald_dac.h:173
dac_init_t::p_ref
dac_pos_ref_t p_ref
Definition: ald_dac.h:175
IS_DAC_TYPE
#define IS_DAC_TYPE(x)
Definition: ald_dac.h:221
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dac_init_t::sine
type_func_t sine
Definition: ald_dac.h:172
__LOCK
#define __LOCK(x)
Definition: utils.h:92
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
DAC_CH1_DISABLE
#define DAC_CH1_DISABLE()
Definition: ald_dac.h:208
dac_init_t::div
dac_prescale_div_t div
Definition: ald_dac.h:169

◆ ald_dac_interrupt_config()

void ald_dac_interrupt_config | ( | dac_handle_t * | hperh,
 |  | dac_it_t | it,
 |  | type_func_t | state
 | ) |  |

Enable or disable the specified interrupt.

Parameters
hperh | Pointer to a dac_handle_t structure that contains the configuration information for the specified DAC.
it Specifies the interrupt type to be enabled or disabled
  • DAC_IT_CH0 Channel 0 conversion complete interrupt
  • DAC_IT_CH1 Channel 1 conversion complete interrupt
  • DAC_IT_CH0_UF Channel 0 data underflow interrupt
  • DAC_IT_CH1_UF Channel 1 data underflow interrupt
state | New state of the specified interrupt. This parameter can be: ENABLE or DISABLE
Return values
Status,see ald_status_t.

Definition at line 207 of file ald_dac.c.

208 {
209 assert_param(IS_DAC_TYPE(hperh->perh));
210 assert_param(IS_DAC_INTERRUPT_TYPE(it));
211 assert_param(IS_FUNC_STATE(state));
212
213 if (state)
214 hperh->perh->IES |= it;
215 else
216 hperh->perh->IEC = it;
217
218 return;
219 }
assert_param
#define assert_param(x)
Definition: type.h:88
dac_handle_s::perh
DAC_TypeDef * perh
Definition: ald_dac.h:192
IS_DAC_INTERRUPT_TYPE
#define IS_DAC_INTERRUPT_TYPE(x)
Definition: ald_dac.h:250
IS_DAC_TYPE
#define IS_DAC_TYPE(x)
Definition: ald_dac.h:221
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_dac_irq_handler()

void ald_dac_irq_handler ( dac_handle_t * hperh )

This function handles DAC event interrupt request.

Parameters
hperh Pointer to a dac_handle_t structure that contains the configuration information for the specified DAC.
Return values
None

Definition at line 292 of file ald_dac.c.

293 {
294 if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH0)) {
295 ald_dac_clear_flag_status(hperh, DAC_FLAG_CH0);
296
297 if (hperh->cbk)
298 hperh->cbk(hperh, DAC_EVENT_CH0_CPLT);
299 }
300
301 if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH1)) {
302 ald_dac_clear_flag_status(hperh, DAC_FLAG_CH1);
303
304 if (hperh->cbk)
305 hperh->cbk(hperh, DAC_EVENT_CH1_CPLT);
306 }
307
308 if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH0_UF)) {
309 ald_dac_clear_flag_status(hperh, DAC_FLAG_CH0_UF);
310
311 if (hperh->cbk)
312 hperh->cbk(hperh, DAC_EVENT_CH0_UF);
313 }
314
315 if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH1_UF)) {
316 ald_dac_clear_flag_status(hperh, DAC_FLAG_CH1_UF);
317
318 if (hperh->cbk)
319 hperh->cbk(hperh, DAC_EVENT_CH1_UF);
320 }
321
322 return;
323 }
DAC_EVENT_CH0_UF
#define DAC_EVENT_CH0_UF
Definition: ald_dac.h:212
ald_dac_clear_flag_status
void ald_dac_clear_flag_status(dac_handle_t *hperh, dac_flag_t flag)
Clear interrupt state flag.
Definition: ald_dac.c:277
DAC_FLAG_CH0
Definition: ald_dac.h:148
DAC_FLAG_CH0_UF
Definition: ald_dac.h:150
ald_dac_get_mask_flag_status
flag_status_t ald_dac_get_mask_flag_status(dac_handle_t *hperh, dac_flag_t flag)
Get the status of interrupt flag and interupt source.
Definition: ald_dac.c:262
DAC_FLAG_CH1_UF
Definition: ald_dac.h:151
DAC_EVENT_CH1_UF
#define DAC_EVENT_CH1_UF
Definition: ald_dac.h:213
DAC_FLAG_CH1
Definition: ald_dac.h:149
dac_handle_s::cbk
void(* cbk)(struct dac_handle_s *arg, uint32_t event)
Definition: ald_dac.h:196
DAC_EVENT_CH0_CPLT
#define DAC_EVENT_CH0_CPLT
Definition: ald_dac.h:210
DAC_EVENT_CH1_CPLT
#define DAC_EVENT_CH1_CPLT
Definition: ald_dac.h:211

◆ ald_dac_output_set()

void ald_dac_output_set | ( | dac_handle_t * | hperh,
 |  | dac_channel_t | ch,
 |  | uint32_t | value
 | ) |  |

Set dac channel output value.

Parameters
hperh | Pointer to a dac_handle_t structure that contains the configuration information for the specified DAC module.
ch | Specifies which dac channel to be set.
value | The value be converted,and the valid value is low 12 bit.
Return values
None

Definition at line 154 of file ald_dac.c.

155 {
156 assert_param(IS_DAC_TYPE(hperh->perh));
157 assert_param(IS_DAC_CHANNEL_TYPE(ch));
158
159 switch (ch) {
160 case DAC_CHANNEL_0:
161 hperh->perh->CH0DATA = value;
162 break;
163
164 case DAC_CHANNEL_1:
165 hperh->perh->CH1DATA = value;
166 break;
167
168 case DAC_CHANNEL_COMB:
169 hperh->perh->COMBDATA = value;
170 break;
171
172 default:
173 break;
174 }
175
176 return;
177 }
assert_param
#define assert_param(x)
Definition: type.h:88
DAC_CHANNEL_0
Definition: ald_dac.h:42
dac_handle_s::perh
DAC_TypeDef * perh
Definition: ald_dac.h:192
DAC_CHANNEL_COMB
Definition: ald_dac.h:44
IS_DAC_CHANNEL_TYPE
#define IS_DAC_CHANNEL_TYPE(x)
Definition: ald_dac.h:239
DAC_CHANNEL_1
Definition: ald_dac.h:43
IS_DAC_TYPE
#define IS_DAC_TYPE(x)
Definition: ald_dac.h:221

◆ ald_dac_reset()

ald_status_t ald_dac_reset ( dac_handle_t * hperh )

Reset the dac mode.

Parameters
hperh Pointer to a dac_handle_t structure that contains the configuration information for the specified DAC module.
Return values
Status,see ald_status_t.

Definition at line 38 of file ald_dac.c.

39 {
40 assert_param(IS_DAC_TYPE(hperh->perh));
41
42 hperh->perh->CON = 0;
43 hperh->perh->CH0CTRL = 0;
44 hperh->perh->CH1CTRL = 0;
45 hperh->perh->IES = 0;
46 hperh->perh->IEC = 0xFF;
47 hperh->perh->IFC = 0xFF;
48 hperh->perh->CAL = 0;
49
50 return OK;
51 }
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
dac_handle_s::perh
DAC_TypeDef * perh
Definition: ald_dac.h:192
IS_DAC_TYPE
#define IS_DAC_TYPE(x)
Definition: ald_dac.h:221


ALD User Manual: DAC Pubulic Types

Data Structures | Typedefs | Enumerations
DAC Pubulic Types
EASTSOFT ES32F3xx ALD » DAC
Collaboration diagram for DAC Pubulic Types:

Data Structures

struct | dac_init_t
DAC init structure definition. More...
struct | dac_channel_config_t
DAC channel initialize structure definition. More...
struct | dac_handle_s
DAC handle Structure definition. More...

Typedefs

typedef struct dac_handle_s dac_handle_t
DAC handle Structure definition. More...

Enumerations

enum | dac_channel_t { DAC_CHANNEL_0 = 1U, DAC_CHANNEL_1 = 2U, DAC_CHANNEL_COMB = 3U }
DAC channel. More...
enum | dac_conv_mode_t { DAC_CONV_MODE_CONTINUOUS = 0U, DAC_CONV_MODE_SAMPLEHOLD = 1U, DAC_CONV_MODE_SAMPLEOFF = 2U }
DAC convert mode. More...
enum | dac_out_mode_t { DAC_OUTPUT_DISABLE = 0U, DAC_OUTPUT_PIN = 1U, DAC_OUTPUT_ADC = 2U, DAC_OUTPUT_PIN_ADC = 3U }
DAC out mode. More...
enum dac_pissel_t {
DAC_PIS_CH_0 = 0U, DAC_PIS_CH_1 = 1U, DAC_PIS_CH_2 = 2U, DAC_PIS_CH_3 = 3U,
DAC_PIS_CH_4 = 4U, DAC_PIS_CH_5 = 5U, DAC_PIS_CH_6 = 6U, DAC_PIS_CH_7 = 7U,
DAC_PIS_CH_8 = 8U, DAC_PIS_CH_9 = 9U, DAC_PIS_CH_10 = 10U, DAC_PIS_CH_11 = 11U
}
DAC pis input channel. More...
enum | dac_neg_ref_t { DAC_NEG_REF_VSS = 0x0U, DAC_NEG_REF_VREFN = 0x1U }
DAC negative reference voltage definition. More...
enum | dac_pos_ref_t { DAC_POS_REF_VDD = 0x0U, DAC_POS_REF_2V = 0x1U, DAC_POS_REF_VREEFP = 0x2U, DAC_POS_REF_VREEFP_BUF = 0x3U }
DAC positive reference voltage definition. More...
enum | dac_refresh_t { DAC_REFRESH_8 = 0U, DAC_REFRESH_16 = 1U, DAC_REFRESH_32 = 2U, DAC_REFRESH_64 = 3U }
Refresh interval select. More...
enum dac_prescale_div_t {
DAC_PRES_DIV_1 = 0U, DAC_PRES_DIV_2 = 1U, DAC_PRES_DIV_4 = 2U, DAC_PRES_DIV_8 = 3U,
DAC_PRES_DIV_16 = 4U, DAC_PRES_DIV_32 = 5U, DAC_PRES_DIV_64 = 6U, DAC_PRES_DIV_128 = 7U
}
DAC prescale. More...
enum | dac_trigger_t { DAC_TRIGGER_BY_DATA = 0U, DAC_TRIGGER_BY_PIS = 1U }
DAC output trigger select. More...
enum | dac_it_t { DAC_IT_CH0 = (1U << 0), DAC_IT_CH1 = (1U << 1), DAC_IT_CH0_UF = (1U << 4), DAC_IT_CH1_UF = (1U << 5) }
DAC interrupt type. More...
enum | dac_flag_t { DAC_FLAG_CH0 = (1U << 0), DAC_FLAG_CH1 = (1U << 1), DAC_FLAG_CH0_UF = (1U << 4), DAC_FLAG_CH1_UF = (1U << 5) }
DAC interrupt flag type. More...
enum | dac_status_t { DAC_CH0_BSY = (1U << 0), DAC_CH1_BSY = (1U << 1) }
DAC state flag. More...

Detailed Description

Typedef Documentation

◆ dac_handle_t

typedef struct dac_handle_s dac_handle_t

DAC handle Structure definition.

Enumeration Type Documentation

◆ dac_channel_t

enum dac_channel_t

DAC channel.

Enumerator
DAC_CHANNEL_0 | DAC channel 0
DAC_CHANNEL_1 | DAC channel 1
DAC_CHANNEL_COMB | DAC channel 0 and 1

Definition at line 41 of file ald_dac.h.

41 {
42 DAC_CHANNEL_0 = 1U,
43 DAC_CHANNEL_1 = 2U,
44 DAC_CHANNEL_COMB = 3U,
45 } dac_channel_t;
DAC_CHANNEL_0
Definition: ald_dac.h:42
DAC_CHANNEL_COMB
Definition: ald_dac.h:44
DAC_CHANNEL_1
Definition: ald_dac.h:43
dac_channel_t
dac_channel_t
DAC channel.
Definition: ald_dac.h:41

◆ dac_conv_mode_t

enum dac_conv_mode_t

DAC convert mode.

Enumerator
DAC_CONV_MODE_CONTINUOUS | DAC set in continuous mode
DAC_CONV_MODE_SAMPLEHOLD | DAC set in sample/hold mode
DAC_CONV_MODE_SAMPLEOFF | DAC set in sample/shut off mode

Definition at line 50 of file ald_dac.h.

50 {
51 DAC_CONV_MODE_CONTINUOUS = 0U,
52 DAC_CONV_MODE_SAMPLEHOLD = 1U,
53 DAC_CONV_MODE_SAMPLEOFF = 2U,
54 } dac_conv_mode_t;
dac_conv_mode_t
dac_conv_mode_t
DAC convert mode.
Definition: ald_dac.h:50
DAC_CONV_MODE_SAMPLEOFF
Definition: ald_dac.h:53
DAC_CONV_MODE_CONTINUOUS
Definition: ald_dac.h:51
DAC_CONV_MODE_SAMPLEHOLD
Definition: ald_dac.h:52

◆ dac_flag_t

enum dac_flag_t

DAC interrupt flag type.

Enumerator
DAC_FLAG_CH0 | Channel 0 conversion complete interrupt flag
DAC_FLAG_CH1 | Channel 1 conversion complete interrupt flag
DAC_FLAG_CH0_UF | Channel 0 data underflow interrupt flag
DAC_FLAG_CH1_UF | Channel 1 data underflow interrupt flag

Definition at line 147 of file ald_dac.h.

147 {
148 DAC_FLAG_CH0 = (1U << 0),
149 DAC_FLAG_CH1 = (1U << 1),
150 DAC_FLAG_CH0_UF = (1U << 4),
151 DAC_FLAG_CH1_UF = (1U << 5),
152 } dac_flag_t;
dac_flag_t
dac_flag_t
DAC interrupt flag type.
Definition: ald_dac.h:147
DAC_FLAG_CH0
Definition: ald_dac.h:148
DAC_FLAG_CH0_UF
Definition: ald_dac.h:150
DAC_FLAG_CH1_UF
Definition: ald_dac.h:151
DAC_FLAG_CH1
Definition: ald_dac.h:149

◆ dac_it_t

enum dac_it_t

DAC interrupt type.

Enumerator
DAC_IT_CH0 | Channel 0 conversion complete interrupt
DAC_IT_CH1 | Channel 1 conversion complete interrupt
DAC_IT_CH0_UF | Channel 0 data underflow interrupt
DAC_IT_CH1_UF | Channel 1 data underflow interrupt

Definition at line 137 of file ald_dac.h.

137 {
138 DAC_IT_CH0 = (1U << 0),
139 DAC_IT_CH1 = (1U << 1),
140 DAC_IT_CH0_UF = (1U << 4),
141 DAC_IT_CH1_UF = (1U << 5),
142 } dac_it_t;
DAC_IT_CH1
Definition: ald_dac.h:139
DAC_IT_CH1_UF
Definition: ald_dac.h:141
dac_it_t
dac_it_t
DAC interrupt type.
Definition: ald_dac.h:137
DAC_IT_CH0
Definition: ald_dac.h:138
DAC_IT_CH0_UF
Definition: ald_dac.h:140

◆ dac_neg_ref_t

enum dac_neg_ref_t

DAC negative reference voltage definition.

Enumerator
DAC_NEG_REF_VSS | DAC negative regerence voltage vss
DAC_NEG_REF_VREFN | DAC negative regerence voltage vrefn

Definition at line 87 of file ald_dac.h.

87 {
88 DAC_NEG_REF_VSS = 0x0U,
89 DAC_NEG_REF_VREFN = 0x1U,
90 } dac_neg_ref_t;
DAC_NEG_REF_VREFN
Definition: ald_dac.h:89
dac_neg_ref_t
dac_neg_ref_t
DAC negative reference voltage definition.
Definition: ald_dac.h:87
DAC_NEG_REF_VSS
Definition: ald_dac.h:88

◆ dac_out_mode_t

enum dac_out_mode_t

DAC out mode.

Enumerator
DAC_OUTPUT_DISABLE | DAC output disable
DAC_OUTPUT_PIN | DAC output to pin enable
DAC_OUTPUT_ADC | DAC output to adc and acmp enable
DAC_OUTPUT_PIN_ADC | DAC output to pin, adc and acmp enable

Definition at line 59 of file ald_dac.h.

59 {
60 DAC_OUTPUT_DISABLE = 0U,
61 DAC_OUTPUT_PIN = 1U,
62 DAC_OUTPUT_ADC = 2U,
63 DAC_OUTPUT_PIN_ADC = 3U,
64 } dac_out_mode_t;
DAC_OUTPUT_ADC
Definition: ald_dac.h:62
DAC_OUTPUT_PIN
Definition: ald_dac.h:61
dac_out_mode_t
dac_out_mode_t
DAC out mode.
Definition: ald_dac.h:59
DAC_OUTPUT_DISABLE
Definition: ald_dac.h:60
DAC_OUTPUT_PIN_ADC
Definition: ald_dac.h:63

◆ dac_pissel_t

enum dac_pissel_t

DAC pis input channel.

Enumerator
DAC_PIS_CH_0 | PIS channel 0 triggers DAC channel conversion
DAC_PIS_CH_1 | PIS channel 1 triggers DAC channel conversion
DAC_PIS_CH_2 | PIS channel 2 triggers DAC channel conversion
DAC_PIS_CH_3 | PIS channel 3 triggers DAC channel conversion
DAC_PIS_CH_4 | PIS channel 4 triggers DAC channel conversion
DAC_PIS_CH_5 | PIS channel 5 triggers DAC channel conversion
DAC_PIS_CH_6 | PIS channel 6 triggers DAC channel conversion
DAC_PIS_CH_7 | PIS channel 7 triggers DAC channel conversion
DAC_PIS_CH_8 | PIS channel 8 triggers DAC channel conversion
DAC_PIS_CH_9 | PIS channel 9 triggers DAC channel conversion
DAC_PIS_CH_10 | PIS channel 10 triggers DAC channel conversion
DAC_PIS_CH_11 | PIS channel 11 triggers DAC channel conversion

Definition at line 69 of file ald_dac.h.

69 {
70 DAC_PIS_CH_0 = 0U,
71 DAC_PIS_CH_1 = 1U,
72 DAC_PIS_CH_2 = 2U,
73 DAC_PIS_CH_3 = 3U,
74 DAC_PIS_CH_4 = 4U,
75 DAC_PIS_CH_5 = 5U,
76 DAC_PIS_CH_6 = 6U,
77 DAC_PIS_CH_7 = 7U,
78 DAC_PIS_CH_8 = 8U,
79 DAC_PIS_CH_9 = 9U,
80 DAC_PIS_CH_10 = 10U,
81 DAC_PIS_CH_11 = 11U,
82 } dac_pissel_t;
DAC_PIS_CH_9
Definition: ald_dac.h:79
DAC_PIS_CH_11
Definition: ald_dac.h:81
DAC_PIS_CH_0
Definition: ald_dac.h:70
DAC_PIS_CH_6
Definition: ald_dac.h:76
DAC_PIS_CH_3
Definition: ald_dac.h:73
DAC_PIS_CH_10
Definition: ald_dac.h:80
dac_pissel_t
dac_pissel_t
DAC pis input channel.
Definition: ald_dac.h:69
DAC_PIS_CH_7
Definition: ald_dac.h:77
DAC_PIS_CH_2
Definition: ald_dac.h:72
DAC_PIS_CH_8
Definition: ald_dac.h:78
DAC_PIS_CH_4
Definition: ald_dac.h:74
DAC_PIS_CH_1
Definition: ald_dac.h:71
DAC_PIS_CH_5
Definition: ald_dac.h:75

◆ dac_pos_ref_t

enum dac_pos_ref_t

DAC positive reference voltage definition.

Enumerator
DAC_POS_REF_VDD | DAC posotove reference is VDD
DAC_POS_REF_2V | DAC posotove reference is internal 2V
DAC_POS_REF_VREEFP | DAC posotove reference is VREEFP
DAC_POS_REF_VREEFP_BUF | DAC posotove reference is VREEFP BUFFER

Definition at line 95 of file ald_dac.h.

95 {
96 DAC_POS_REF_VDD = 0x0U,
97 DAC_POS_REF_2V = 0x1U,
98 DAC_POS_REF_VREEFP = 0x2U,
99 DAC_POS_REF_VREEFP_BUF = 0x3U,
100 } dac_pos_ref_t;
DAC_POS_REF_VREEFP
Definition: ald_dac.h:98
dac_pos_ref_t
dac_pos_ref_t
DAC positive reference voltage definition.
Definition: ald_dac.h:95
DAC_POS_REF_VDD
Definition: ald_dac.h:96
DAC_POS_REF_VREEFP_BUF
Definition: ald_dac.h:99
DAC_POS_REF_2V
Definition: ald_dac.h:97

◆ dac_prescale_div_t

enum dac_prescale_div_t

DAC prescale.

Enumerator
DAC_PRES_DIV_1 | No division
DAC_PRES_DIV_2 | 2 clock division
DAC_PRES_DIV_4 | 4 clock division
DAC_PRES_DIV_8 | 8 clock division
DAC_PRES_DIV_16 | 16 clock division
DAC_PRES_DIV_32 | 32 clock division
DAC_PRES_DIV_64 | 64 clock division
DAC_PRES_DIV_128 | 128 clock division

Definition at line 115 of file ald_dac.h.

115 {
116 DAC_PRES_DIV_1 = 0U,
117 DAC_PRES_DIV_2 = 1U,
118 DAC_PRES_DIV_4 = 2U,
119 DAC_PRES_DIV_8 = 3U,
120 DAC_PRES_DIV_16 = 4U,
121 DAC_PRES_DIV_32 = 5U,
122 DAC_PRES_DIV_64 = 6U,
123 DAC_PRES_DIV_128 = 7U,
124 } dac_prescale_div_t;
DAC_PRES_DIV_8
Definition: ald_dac.h:119
DAC_PRES_DIV_32
Definition: ald_dac.h:121
DAC_PRES_DIV_4
Definition: ald_dac.h:118
DAC_PRES_DIV_2
Definition: ald_dac.h:117
DAC_PRES_DIV_64
Definition: ald_dac.h:122
DAC_PRES_DIV_1
Definition: ald_dac.h:116
dac_prescale_div_t
dac_prescale_div_t
DAC prescale.
Definition: ald_dac.h:115
DAC_PRES_DIV_128
Definition: ald_dac.h:123
DAC_PRES_DIV_16
Definition: ald_dac.h:120

◆ dac_refresh_t

enum dac_refresh_t

Refresh interval select.

Enumerator
DAC_REFRESH_8 | Channel refreshed every 8 cycles
DAC_REFRESH_16 | Channel refreshed every 16 cycles
DAC_REFRESH_32 | Channel refreshed every 32 cycles
DAC_REFRESH_64 | Channel refreshed every 64 cycles

Definition at line 105 of file ald_dac.h.

105 {
106 DAC_REFRESH_8 = 0U,
107 DAC_REFRESH_16 = 1U,
108 DAC_REFRESH_32 = 2U,
109 DAC_REFRESH_64 = 3U,
110 } dac_refresh_t;
DAC_REFRESH_8
Definition: ald_dac.h:106
DAC_REFRESH_16
Definition: ald_dac.h:107
dac_refresh_t
dac_refresh_t
Refresh interval select.
Definition: ald_dac.h:105
DAC_REFRESH_64
Definition: ald_dac.h:109
DAC_REFRESH_32
Definition: ald_dac.h:108

◆ dac_status_t

enum dac_status_t

DAC state flag.

Enumerator
DAC_CH0_BSY | Channel_0 is BUSY
DAC_CH1_BSY | Channel_1 is BUSY

Definition at line 157 of file ald_dac.h.

157 {
158 DAC_CH0_BSY = (1U << 0),
159 DAC_CH1_BSY = (1U << 1),
160 } dac_status_t;
DAC_CH0_BSY
Definition: ald_dac.h:158
DAC_CH1_BSY
Definition: ald_dac.h:159
dac_status_t
dac_status_t
DAC state flag.
Definition: ald_dac.h:157

◆ dac_trigger_t

enum dac_trigger_t

DAC output trigger select.

Enumerator
DAC_TRIGGER_BY_DATA | Channel is triggered by CHxDATA or COMBDATA write
DAC_TRIGGER_BY_PIS | Channel is triggered by PIS input

Definition at line 129 of file ald_dac.h.

129 {
130 DAC_TRIGGER_BY_DATA = 0U,
131 DAC_TRIGGER_BY_PIS = 1U,
132 } dac_trigger_t;
dac_trigger_t
dac_trigger_t
DAC output trigger select.
Definition: ald_dac.h:129
DAC_TRIGGER_BY_DATA
Definition: ald_dac.h:130
DAC_TRIGGER_BY_PIS
Definition: ald_dac.h:131


ALD User Manual: dac_init_t Struct Reference

Data Fields
dac_init_t Struct Reference
EASTSOFT ES32F3xx ALD » DAC » DAC Pubulic Types

DAC init structure definition. More...

#include <ald_dac.h>

Data Fields

dac_conv_mode_t conv_mode
dac_out_mode_t out_mode
dac_refresh_t refresh
dac_prescale_div_t div
type_func_t ch0_reset
type_func_t o_ctrl_pis
type_func_t sine
type_func_t diff
dac_neg_ref_t n_ref
dac_pos_ref_t p_ref

Detailed Description

DAC init structure definition.

Definition at line 165 of file ald_dac.h.

Field Documentation

◆ ch0_reset

type_func_t ch0_reset

Select if prescaler is reset on channel 0 start

Definition at line 170 of file ald_dac.h.

◆ conv_mode

dac_conv_mode_t conv_mode

Conversion mode

Definition at line 166 of file ald_dac.h.

◆ diff

type_func_t diff

Differential mode enable/disable

Definition at line 173 of file ald_dac.h.

◆ div

dac_prescale_div_t div

Prescaler setting

Definition at line 169 of file ald_dac.h.

◆ n_ref

dac_neg_ref_t n_ref

The negative reference voltage select

Definition at line 174 of file ald_dac.h.

◆ o_ctrl_pis

type_func_t o_ctrl_pis

Enable pis control of dac output enable

Definition at line 171 of file ald_dac.h.

◆ out_mode

dac_out_mode_t out_mode

Select output mode

Definition at line 167 of file ald_dac.h.

◆ p_ref

dac_pos_ref_t p_ref

The positive reference voltage select

Definition at line 175 of file ald_dac.h.

◆ refresh

dac_refresh_t refresh

Refresh interval select

Definition at line 168 of file ald_dac.h.

◆ sine

type_func_t sine

Sine mode enable/disable

Definition at line 172 of file ald_dac.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_dac.h


ALD User Manual: dac_channel_config_t Struct Reference

Data Fields
dac_channel_config_t Struct Reference
EASTSOFT ES32F3xx ALD » DAC » DAC Pubulic Types

DAC channel initialize structure definition. More...

#include <ald_dac.h>

Data Fields

type_func_t enable
dac_trigger_t trigger
type_func_t refresh_en
dac_pissel_t pis_ch

Detailed Description

DAC channel initialize structure definition.

Definition at line 181 of file ald_dac.h.

Field Documentation

◆ enable

type_func_t enable

DAC channel output enable/disable

Definition at line 182 of file ald_dac.h.

◆ pis_ch

dac_pissel_t pis_ch

Select channel pis input channel

Definition at line 185 of file ald_dac.h.

◆ refresh_en

type_func_t refresh_en

Set automatic refresh of channel function

Definition at line 184 of file ald_dac.h.

◆ trigger

dac_trigger_t trigger

Select channel conversion trigger

Definition at line 183 of file ald_dac.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_dac.h


ALD User Manual: dac_handle_s Struct Reference

Data Fields
dac_handle_s Struct Reference
EASTSOFT ES32F3xx ALD » DAC » DAC Pubulic Types

DAC handle Structure definition. More...

#include <ald_dac.h>

Collaboration diagram for dac_handle_s:
[legend]

Data Fields

DAC_TypeDef * | perh
dac_init_t init
lock_state_t lock
void(* | cbk )(struct dac_handle_s *arg, uint32_t event)

Detailed Description

DAC handle Structure definition.

Definition at line 191 of file ald_dac.h.

Field Documentation

◆ cbk

void(* cbk) (struct dac_handle_s *arg, uint32_t event)

DAC event callback

Definition at line 196 of file ald_dac.h.

◆ init

dac_init_t init

DAC initialize parameters

Definition at line 193 of file ald_dac.h.

◆ lock

lock_state_t lock

Locking object

Definition at line 194 of file ald_dac.h.

◆ perh

DAC_TypeDef* perh

Register base address

Definition at line 192 of file ald_dac.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_dac.h


ALD User Manual: DAC Public Macros

Macros
DAC Public Macros
EASTSOFT ES32F3xx ALD » DAC
Collaboration diagram for DAC Public Macros:

Macros

#define | DAC_CH0_ENABLE() (SET_BIT(DAC0->CH0CTRL, DAC_CH0CTRL_EN_MSK))
#define | DAC_CH1_ENABLE() (SET_BIT(DAC0->CH1CTRL, DAC_CH1CTRL_EN_MSK))
#define | DAC_CH0_DISABLE() (CLEAR_BIT(DAC0->CH0CTRL, DAC_CH0CTRL_EN_MSK))
#define | DAC_CH1_DISABLE() (CLEAR_BIT(DAC0->CH1CTRL, DAC_CH1CTRL_EN_MSK))
#define | DAC_EVENT_CH0_CPLT 0x0
#define | DAC_EVENT_CH1_CPLT 0x1
#define | DAC_EVENT_CH0_UF 0x2
#define | DAC_EVENT_CH1_UF 0x3

Detailed Description

Macro Definition Documentation

◆ DAC_CH0_DISABLE

#define DAC_CH0_DISABLE ( ) (CLEAR_BIT(DAC0->CH0CTRL, DAC_CH0CTRL_EN_MSK))

Definition at line 207 of file ald_dac.h.

◆ DAC_CH0_ENABLE

#define DAC_CH0_ENABLE ( ) (SET_BIT(DAC0->CH0CTRL, DAC_CH0CTRL_EN_MSK))

Definition at line 205 of file ald_dac.h.

◆ DAC_CH1_DISABLE

#define DAC_CH1_DISABLE ( ) (CLEAR_BIT(DAC0->CH1CTRL, DAC_CH1CTRL_EN_MSK))

Definition at line 208 of file ald_dac.h.

◆ DAC_CH1_ENABLE

#define DAC_CH1_ENABLE ( ) (SET_BIT(DAC0->CH1CTRL, DAC_CH1CTRL_EN_MSK))

Definition at line 206 of file ald_dac.h.

◆ DAC_EVENT_CH0_CPLT

#define DAC_EVENT_CH0_CPLT 0x0

Definition at line 210 of file ald_dac.h.

◆ DAC_EVENT_CH0_UF

#define DAC_EVENT_CH0_UF 0x2

Definition at line 212 of file ald_dac.h.

◆ DAC_EVENT_CH1_CPLT

#define DAC_EVENT_CH1_CPLT 0x1

Definition at line 211 of file ald_dac.h.

◆ DAC_EVENT_CH1_UF

#define DAC_EVENT_CH1_UF 0x3

Definition at line 213 of file ald_dac.h.


ALD User Manual: DAC Private Macros

Macros
DAC Private Macros
EASTSOFT ES32F3xx ALD » DAC
Collaboration diagram for DAC Private Macros:

Macros

#define | IS_DAC_TYPE(x) ((x) == DAC0)
#define | IS_DAC_CONVERT_TYPE(x)
#define | IS_DAC_OUTPUT_TYPE(x)
#define | IS_DAC_NEG_REFRESH_TYPE(x)
#define | IS_DAC_POS_REFRESH_TYPE(x)
#define | IS_DAC_REFRESH_TYPE(x)
#define | IS_DAC_CHANNEL_TYPE(x)
#define | IS_DAC_PRESCALE_TYPE(x)
#define | IS_DAC_INTERRUPT_TYPE(x)
#define | IS_DAC_FLAG_TYPE(x)
#define | IS_DAC_PISSEL_CH_TYPE(x)
#define | IS_DAC_STATUS_TYPE(x)
#define | IS_DAC_TRIGGER_TYPE(x)

Detailed Description

Macro Definition Documentation

◆ IS_DAC_CHANNEL_TYPE

#define IS_DAC_CHANNEL_TYPE ( x )
Value:
(((x) == DAC_CHANNEL_0) || \
((x) == DAC_CHANNEL_1) || \
((x) == DAC_CHANNEL_COMB))
DAC_CHANNEL_0
Definition: ald_dac.h:42
DAC_CHANNEL_COMB
Definition: ald_dac.h:44
DAC_CHANNEL_1
Definition: ald_dac.h:43

Definition at line 239 of file ald_dac.h.

◆ IS_DAC_CONVERT_TYPE

#define IS_DAC_CONVERT_TYPE ( x )
Value:
(((x) == DAC_CONV_MODE_CONTINUOUS) || \
((x) == DAC_CONV_MODE_SAMPLEHOLD) || \
((x) == DAC_CONV_MODE_SAMPLEOFF))
DAC_CONV_MODE_SAMPLEOFF
Definition: ald_dac.h:53
DAC_CONV_MODE_CONTINUOUS
Definition: ald_dac.h:51
DAC_CONV_MODE_SAMPLEHOLD
Definition: ald_dac.h:52

Definition at line 222 of file ald_dac.h.

◆ IS_DAC_FLAG_TYPE

#define IS_DAC_FLAG_TYPE ( x )
Value:
(((x) == DAC_FLAG_CH0) || \
((x) == DAC_FLAG_CH1) || \
((x) == DAC_FLAG_CH0_UF) || \
((x) == DAC_FLAG_CH1_UF))
DAC_FLAG_CH0
Definition: ald_dac.h:148
DAC_FLAG_CH0_UF
Definition: ald_dac.h:150
DAC_FLAG_CH1_UF
Definition: ald_dac.h:151
DAC_FLAG_CH1
Definition: ald_dac.h:149

Definition at line 254 of file ald_dac.h.

◆ IS_DAC_INTERRUPT_TYPE

#define IS_DAC_INTERRUPT_TYPE ( x )
Value:
(((x) == DAC_IT_CH0) || \
((x) == DAC_IT_CH1) || \
((x) == DAC_IT_CH0_UF) || \
((x) == DAC_IT_CH1_UF))
DAC_IT_CH1
Definition: ald_dac.h:139
DAC_IT_CH1_UF
Definition: ald_dac.h:141
DAC_IT_CH0
Definition: ald_dac.h:138
DAC_IT_CH0_UF
Definition: ald_dac.h:140

Definition at line 250 of file ald_dac.h.

◆ IS_DAC_NEG_REFRESH_TYPE

#define IS_DAC_NEG_REFRESH_TYPE ( x )
Value:
(((x) == DAC_NEG_REF_VSS) || \
((x) == DAC_NEG_REF_VREFN))
DAC_NEG_REF_VREFN
Definition: ald_dac.h:89
DAC_NEG_REF_VSS
Definition: ald_dac.h:88

Definition at line 229 of file ald_dac.h.

◆ IS_DAC_OUTPUT_TYPE

#define IS_DAC_OUTPUT_TYPE ( x )
Value:
(((x) == DAC_OUTPUT_DISABLE) || \
((x) == DAC_OUTPUT_PIN) || \
((x) == DAC_OUTPUT_ADC) || \
((x) == DAC_OUTPUT_PIN_ADC))
DAC_OUTPUT_ADC
Definition: ald_dac.h:62
DAC_OUTPUT_PIN
Definition: ald_dac.h:61
DAC_OUTPUT_DISABLE
Definition: ald_dac.h:60
DAC_OUTPUT_PIN_ADC
Definition: ald_dac.h:63

Definition at line 225 of file ald_dac.h.

◆ IS_DAC_PISSEL_CH_TYPE

#define IS_DAC_PISSEL_CH_TYPE ( x )
Value:
(((x) == DAC_PIS_CH_0) || \
((x) == DAC_PIS_CH_1) || \
((x) == DAC_PIS_CH_2) || \
((x) == DAC_PIS_CH_3) || \
((x) == DAC_PIS_CH_4) || \
((x) == DAC_PIS_CH_5) || \
((x) == DAC_PIS_CH_6) || \
((x) == DAC_PIS_CH_7) || \
((x) == DAC_PIS_CH_8) || \
((x) == DAC_PIS_CH_9) || \
((x) == DAC_PIS_CH_10) || \
((x) == DAC_PIS_CH_11))
DAC_PIS_CH_9
Definition: ald_dac.h:79
DAC_PIS_CH_11
Definition: ald_dac.h:81
DAC_PIS_CH_0
Definition: ald_dac.h:70
DAC_PIS_CH_6
Definition: ald_dac.h:76
DAC_PIS_CH_3
Definition: ald_dac.h:73
DAC_PIS_CH_10
Definition: ald_dac.h:80
DAC_PIS_CH_7
Definition: ald_dac.h:77
DAC_PIS_CH_2
Definition: ald_dac.h:72
DAC_PIS_CH_8
Definition: ald_dac.h:78
DAC_PIS_CH_4
Definition: ald_dac.h:74
DAC_PIS_CH_1
Definition: ald_dac.h:71
DAC_PIS_CH_5
Definition: ald_dac.h:75

Definition at line 258 of file ald_dac.h.

◆ IS_DAC_POS_REFRESH_TYPE

#define IS_DAC_POS_REFRESH_TYPE ( x )
Value:
(((x) == DAC_POS_REF_VDD) || \
((x) == DAC_POS_REF_2V) || \
((x) == DAC_POS_REF_VREEFP) || \
((x) == DAC_POS_REF_VREEFP_BUF))
DAC_POS_REF_VREEFP
Definition: ald_dac.h:98
DAC_POS_REF_VDD
Definition: ald_dac.h:96
DAC_POS_REF_VREEFP_BUF
Definition: ald_dac.h:99
DAC_POS_REF_2V
Definition: ald_dac.h:97

Definition at line 231 of file ald_dac.h.

◆ IS_DAC_PRESCALE_TYPE

#define IS_DAC_PRESCALE_TYPE ( x )
Value:
(((x) == DAC_PRES_DIV_1) || \
((x) == DAC_PRES_DIV_2) || \
((x) == DAC_PRES_DIV_4) || \
((x) == DAC_PRES_DIV_8) || \
((x) == DAC_PRES_DIV_16) || \
((x) == DAC_PRES_DIV_32) || \
((x) == DAC_PRES_DIV_64) || \
((x) == DAC_PRES_DIV_128))
DAC_PRES_DIV_8
Definition: ald_dac.h:119
DAC_PRES_DIV_32
Definition: ald_dac.h:121
DAC_PRES_DIV_4
Definition: ald_dac.h:118
DAC_PRES_DIV_2
Definition: ald_dac.h:117
DAC_PRES_DIV_64
Definition: ald_dac.h:122
DAC_PRES_DIV_1
Definition: ald_dac.h:116
DAC_PRES_DIV_128
Definition: ald_dac.h:123
DAC_PRES_DIV_16
Definition: ald_dac.h:120

Definition at line 242 of file ald_dac.h.

◆ IS_DAC_REFRESH_TYPE

#define IS_DAC_REFRESH_TYPE ( x )
Value:
(((x) == DAC_REFRESH_8) || \
((x) == DAC_REFRESH_16) || \
((x) == DAC_REFRESH_32) || \
((x) == DAC_REFRESH_64))
DAC_REFRESH_8
Definition: ald_dac.h:106
DAC_REFRESH_16
Definition: ald_dac.h:107
DAC_REFRESH_64
Definition: ald_dac.h:109
DAC_REFRESH_32
Definition: ald_dac.h:108

Definition at line 235 of file ald_dac.h.

◆ IS_DAC_STATUS_TYPE

#define IS_DAC_STATUS_TYPE ( x )
Value:
(((x) == DAC_CH0_BSY) || \
((x) == DAC_CH1_BSY))
DAC_CH0_BSY
Definition: ald_dac.h:158
DAC_CH1_BSY
Definition: ald_dac.h:159

Definition at line 270 of file ald_dac.h.

◆ IS_DAC_TRIGGER_TYPE

#define IS_DAC_TRIGGER_TYPE ( x )
Value:
(((x) == DAC_TRIGGER_BY_DATA) || \
((x) == DAC_TRIGGER_BY_PIS))
DAC_TRIGGER_BY_DATA
Definition: ald_dac.h:130
DAC_TRIGGER_BY_PIS
Definition: ald_dac.h:131

Definition at line 272 of file ald_dac.h.

◆ IS_DAC_TYPE

#define IS_DAC_TYPE ( x ) ((x) == DAC0)

Definition at line 221 of file ald_dac.h.


ALD User Manual: DBGC

Modules
DBGC
EASTSOFT ES32F3xx ALD

DBGC module driver. More...

Collaboration diagram for DBGC:

Modules

DBGC Public Types
DBGC Public Functions

Detailed Description

DBGC module driver.


ALD User Manual: DBGC Public Types

Enumerations
DBGC Public Types
EASTSOFT ES32F3xx ALD » DBGC
Collaboration diagram for DBGC Public Types:

Enumerations

enum dbgc_mode_t { DEBC_MODE_SLEEP = (1U << 0), DEBC_MODE_STOP1 = (1U << 1), DEBC_MODE_STOP2 = (1U << 2), DEBC_MODE_STANDBY = (1U << 3) }
Debug mode select. More...
enum dbgc_perh_t {
DEBC_PERH_TIMER0 = (1U << 0), DEBC_PERH_TIMER1 = (1U << 1), DEBC_PERH_TIMER2 = (1U << 2), DEBC_PERH_TIMER3 = (1U << 3),
DEBC_PERH_TIMER4 = (1U << 4), DEBC_PERH_TIMER5 = (1U << 5), DEBC_PERH_TIMER6 = (1U << 6), DEBC_PERH_TIMER7 = (1U << 7),
DEBC_PERH_I2C0 = (1U << 8), DEBC_PERH_I2C1 = (1U << 9), DEBC_PERH_CAN = (1U << 12), DEBC_PERH_LPTIM0 = (1U << 0) | (1U << 16),
DEBC_PERH_IWDT = (1U << 8) | (1U << 16), DEBC_PERH_WWDT = (1U << 9) | (1U << 16), DEBC_PERH_RTC = (1U << 10) | (1U << 16)
}
Debug peripheral select. More...

Detailed Description

Enumeration Type Documentation

◆ dbgc_mode_t

enum dbgc_mode_t

Debug mode select.

Enumerator
DEBC_MODE_SLEEP | Sleep mode
DEBC_MODE_STOP1 | STOP1 mode
DEBC_MODE_STOP2 | STOP2 mode
DEBC_MODE_STANDBY | Standby mode

Definition at line 44 of file ald_dbgc.h.

44 {
45 DEBC_MODE_SLEEP = (1U << 0),
46 DEBC_MODE_STOP1 = (1U << 1),
47 DEBC_MODE_STOP2 = (1U << 2),
48 DEBC_MODE_STANDBY = (1U << 3),
49 } dbgc_mode_t;
DEBC_MODE_SLEEP
Definition: ald_dbgc.h:45
DEBC_MODE_STOP1
Definition: ald_dbgc.h:46
dbgc_mode_t
dbgc_mode_t
Debug mode select.
Definition: ald_dbgc.h:44
DEBC_MODE_STANDBY
Definition: ald_dbgc.h:48
DEBC_MODE_STOP2
Definition: ald_dbgc.h:47

◆ dbgc_perh_t

enum dbgc_perh_t

Debug peripheral select.

Enumerator
DEBC_PERH_TIMER0 | AD16C4T0
DEBC_PERH_TIMER1 | BS16T0
DEBC_PERH_TIMER2 | GP16C2T0
DEBC_PERH_TIMER3 | GP16C2T1
DEBC_PERH_TIMER4 | BS16T1
DEBC_PERH_TIMER5 | BS16T2
DEBC_PERH_TIMER6 | GP16C4T0
DEBC_PERH_TIMER7 | BS16T3
DEBC_PERH_I2C0 | I2C0 SMBUS
DEBC_PERH_I2C1 | I2C1 SMBUS
DEBC_PERH_CAN | CAN
DEBC_PERH_LPTIM0 | LPTIM0
DEBC_PERH_IWDT | IWDT
DEBC_PERH_WWDT | WWDT
DEBC_PERH_RTC | RTC

Definition at line 54 of file ald_dbgc.h.

54 {
55 DEBC_PERH_TIMER0 = (1U << 0),
56 DEBC_PERH_TIMER1 = (1U << 1),
57 DEBC_PERH_TIMER2 = (1U << 2),
58 DEBC_PERH_TIMER3 = (1U << 3),
59 DEBC_PERH_TIMER4 = (1U << 4),
60 DEBC_PERH_TIMER5 = (1U << 5),
61 DEBC_PERH_TIMER6 = (1U << 6),
62 DEBC_PERH_TIMER7 = (1U << 7),
63 DEBC_PERH_I2C0 = (1U << 8),
64 DEBC_PERH_I2C1 = (1U << 9),
65 DEBC_PERH_CAN = (1U << 12),
66 DEBC_PERH_LPTIM0 = (1U << 0) | (1U << 16),
67 DEBC_PERH_IWDT = (1U << 8) | (1U << 16),
68 DEBC_PERH_WWDT = (1U << 9) | (1U << 16),
69 DEBC_PERH_RTC = (1U << 10) | (1U << 16),
70 } dbgc_perh_t;
DEBC_PERH_RTC
Definition: ald_dbgc.h:69
DEBC_PERH_TIMER2
Definition: ald_dbgc.h:57
DEBC_PERH_IWDT
Definition: ald_dbgc.h:67
DEBC_PERH_WWDT
Definition: ald_dbgc.h:68
DEBC_PERH_TIMER6
Definition: ald_dbgc.h:61
DEBC_PERH_I2C0
Definition: ald_dbgc.h:63
DEBC_PERH_TIMER4
Definition: ald_dbgc.h:59
DEBC_PERH_I2C1
Definition: ald_dbgc.h:64
dbgc_perh_t
dbgc_perh_t
Debug peripheral select.
Definition: ald_dbgc.h:54
DEBC_PERH_CAN
Definition: ald_dbgc.h:65
DEBC_PERH_TIMER0
Definition: ald_dbgc.h:55
DEBC_PERH_TIMER1
Definition: ald_dbgc.h:56
DEBC_PERH_TIMER3
Definition: ald_dbgc.h:58
DEBC_PERH_TIMER7
Definition: ald_dbgc.h:62
DEBC_PERH_TIMER5
Definition: ald_dbgc.h:60
DEBC_PERH_LPTIM0
Definition: ald_dbgc.h:66


ALD User Manual: DBGC Public Functions

Functions
DBGC Public Functions
EASTSOFT ES32F3xx ALD » DBGC
Collaboration diagram for DBGC Public Functions:

Functions

__INLINE uint32_t | ald_dbgc_get_rev_id (void)
Gets version. More...
__INLINE uint32_t | ald_dbgc_get_core_id (void)
Gets core id. More...
__INLINE uint32_t | ald_dbgc_get_device_id (void)
Gets device id. More...
__INLINE void | ald_dbgc_mode_config (dbgc_mode_t mode, type_func_t state)
Configures low power debug mode. More...
__INLINE void | ald_dbgc_perh_config (dbgc_perh_t perh, type_func_t state)
Configures peripheral debug mode. More...

Detailed Description

Function Documentation

◆ ald_dbgc_get_core_id()

__INLINE uint32_t ald_dbgc_get_core_id ( void )

Gets core id.

Return values
Core id

Definition at line 91 of file ald_dbgc.h.

92 {
93 return (DBGC->IDCODE >> 12) & 0xF;
94 }

◆ ald_dbgc_get_device_id()

__INLINE uint32_t ald_dbgc_get_device_id ( void )

Gets device id.

Return values
device id

Definition at line 100 of file ald_dbgc.h.

101 {
102 return DBGC->IDCODE & 0xFFF;
103 }

◆ ald_dbgc_get_rev_id()

__INLINE uint32_t ald_dbgc_get_rev_id ( void )

Gets version.

Return values
Version

Definition at line 82 of file ald_dbgc.h.

83 {
84 return (DBGC->IDCODE >> 16);
85 }

◆ ald_dbgc_mode_config()

__INLINE void ald_dbgc_mode_config | ( | dbgc_mode_t | mode,
 |  | type_func_t | state
 | ) |  |

Configures low power debug mode.

Parameters
mode | The mode of low power.
state | ENABLE/DISABLE
Return values
None

Definition at line 111 of file ald_dbgc.h.

112 {
113 if (state)
114 SET_BIT(DBGC->CR, mode);
115 else
116 CLEAR_BIT(DBGC->CR, mode);
117 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67

◆ ald_dbgc_perh_config()

__INLINE void ald_dbgc_perh_config | ( | dbgc_perh_t | perh,
 |  | type_func_t | state
 | ) |  |

Configures peripheral debug mode.

Parameters
perh | The peripheral.
state | ENABLE/DISABLE
Return values
None

Definition at line 125 of file ald_dbgc.h.

126 {
127 if ((perh >> 16) & 0x1) {
128 if (state)
129 SET_BIT(DBGC->APB2FZ, perh);
130 else
131 CLEAR_BIT(DBGC->APB2FZ, perh);
132 }
133 else {
134 if (state)
135 SET_BIT(DBGC->APB1FZ, perh);
136 else
137 CLEAR_BIT(DBGC->APB1FZ, perh);
138 }
139 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67


ALD User Manual: DMA

Modules
DMA
EASTSOFT ES32F3xx ALD

DMA module driver. More...

Collaboration diagram for DMA:

Modules

DMA Private Variables
DMA Private Functions
DMA Public Functions
DMA Public Macros
DMA Public Types
DMA Private Macros

Detailed Description

DMA module driver.


ALD User Manual: DMA Private Variables

Functions | Variables
DMA Private Variables
EASTSOFT ES32F3xx ALD » DMA
Collaboration diagram for DMA Private Variables:

Functions

dma_descriptor_t dma0_ctrl_base [28] __attribute__ ((aligned(512)))

Variables

dma_call_back_t dma0_cbk [12]

Detailed Description

Function Documentation

◆ __attribute__()

dma_descriptor_t dma0_ctrl_base [28] __attribute__ ( (aligned(512)) )

Variable Documentation

◆ dma0_cbk

dma_call_back_t dma0_cbk[12]

Definition at line 77 of file ald_dma.c.


ALD User Manual: DMA Private Functions

Functions
DMA Private Functions
EASTSOFT ES32F3xx ALD » DMA
Collaboration diagram for DMA Private Functions:

Functions

static void | dma_config_base (DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config_t *p)
Configure DMA channel using dma_config_t structure. More...
void | ald_dma_irq_handler (void)
Handle DMA interrupt. More...

Detailed Description

Function Documentation

◆ ald_dma_irq_handler()

void ald_dma_irq_handler ( void )

Handle DMA interrupt.

Return values
None

Definition at line 170 of file ald_dma.c.

171 {
172 uint32_t i, reg = DMA0->IFLAG;
173
174 for (i = 0; i < DMA_CH_COUNT; ++i) {
175 if (READ_BIT(reg, (1 << i))) {
176 if (dma0_cbk[i].cplt_cbk != NULL)
177 dma0_cbk[i].cplt_cbk(dma0_cbk[i].cplt_arg);
178
179 ald_dma_clear_flag_status(DMA0, i);
180 }
181 }
182
183 if (READ_BIT(reg, (1U << DMA_ERR))) {
184 ald_dma_clear_flag_status(DMA0, DMA_ERR);
185
186 for (i = 0; i < DMA_CH_COUNT; ++i) {
187 if (((DMA0->CHENSET >> i) & 0x1) && (dma0_cbk[i].err_cbk != NULL))
188 dma0_cbk[i].err_cbk(dma0_cbk[i].err_arg);
189 }
190 }
191
192 return;
193 }
dma_call_back_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:269
dma_call_back_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:268
dma0_cbk
dma_call_back_t dma0_cbk[12]
Definition: ald_dma.c:77
ald_dma_clear_flag_status
void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel)
Clear the specified channel pending flag.
Definition: ald_dma.c:952
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
DMA_ERR
#define DMA_ERR
Definition: ald_dma.h:40
DMA_CH_COUNT
#define DMA_CH_COUNT
Definition: ald_dma.h:39

◆ dma_config_base()

static void dma_config_base | ( | DMA_TypeDef * | DMAx,
 |  | dma_cycle_ctrl_t | mode,
 |  | dma_config_t * | p
 | ) |  |
static

Configure DMA channel using dma_config_t structure.

Parameters
DMAx | Pointer to DMA peripheral
mode | DMA transfer mode. see dma_cycle_ctrl_t
p | Pointer to dma_cycle_ctrl_t which contains DMA channel parameter. see dma_config_t
Return values
None

Definition at line 94 of file ald_dma.c.

95 {
96 dma_descriptor_t *descr;
97
98 assert_param(IS_DMA(DMAx));
99 assert_param(IS_CYCLECTRL_TYPE(mode));
100 assert_param(p->src != NULL);
101 assert_param(p->dst != NULL);
102 assert_param(IS_DMA_DATA_SIZE(p->size));
103 assert_param(IS_DMA_DATASIZE_TYPE(p->data_width));
104 assert_param(IS_DMA_DATAINC_TYPE(p->src_inc));
105 assert_param(IS_DMA_DATAINC_TYPE(p->dst_inc));
106 assert_param(IS_DMA_ARBITERCONFIG_TYPE(p->R_power));
107 assert_param(IS_FUNC_STATE(p->primary));
108 assert_param(IS_FUNC_STATE(p->burst));
109 assert_param(IS_FUNC_STATE(p->high_prio));
110 assert_param(IS_FUNC_STATE(p->interrupt));
111 assert_param(IS_DMA_MSEL_TYPE(p->msel));
112 assert_param(IS_DMA_MSIGSEL_TYPE(p->msigsel));
113 assert_param(IS_DMA_CHANNEL(p->channel));
114
115 if (p->primary)
116 descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + p->channel;
117 else
118 descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + p->channel;
119
120 if (p->src_inc == DMA_DATA_INC_NONE)
121 descr->src = p->src;
122 else
123 descr->src = (void *)((uint32_t)p->src + ((p->size - 1) << (uint32_t)p->src_inc));
124
125 if (p->dst_inc == DMA_DATA_INC_NONE)
126 descr->dst = p->dst;
127 else
128 descr->dst = (void *)((uint32_t)p->dst + ((p->size - 1) << (uint32_t)p->dst_inc));
129
130 descr->ctrl.cycle_ctrl = mode;
131 descr->ctrl.next_useburst = 0;
132 descr->ctrl.n_minus_1 = p->size - 1;
133 descr->ctrl.R_power = p->R_power;
134 descr->ctrl.src_prot_ctrl = 0,
135 descr->ctrl.dst_prot_ctrl = 0,
136 descr->ctrl.src_size = p->data_width;
137 descr->ctrl.src_inc = p->src_inc;
138 descr->ctrl.dst_size = p->data_width;
139 descr->ctrl.dst_inc = p->dst_inc;
140
141 if (p->primary)
142 WRITE_REG(DMAx->CHPRIALTCLR, (1 << p->channel));
143 else
144 WRITE_REG(DMAx->CHPRIALTSET, (1 << p->channel));
145
146 if (p->burst)
147 WRITE_REG(DMAx->CHUSEBURSTSET, (1 << p->channel));
148 else
149 WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << p->channel));
150
151 if (p->high_prio)
152 WRITE_REG(DMAx->CHPRSET, (1 << p->channel));
153 else
154 WRITE_REG(DMAx->CHPRCLR, (1 << p->channel));
155
156 if (p->interrupt)
157 SET_BIT(DMAx->IER, (1 << p->channel));
158 else
159 CLEAR_BIT(DMAx->IER, (1 << p->channel));
160
161 MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSEL_MSK, p->msel << DMA_CH0_SELCON_MSEL_POSS);
162 MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSIGSEL_MSK, p->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS);
163 return;
164 }
dma_ctrl_t::src_size
uint32_t src_size
Definition: ald_dma.h:195
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
dma_ctrl_t::dst_size
uint32_t dst_size
Definition: ald_dma.h:197
dma_ctrl_t::src_prot_ctrl
uint32_t src_prot_ctrl
Definition: ald_dma.h:193
dma_config_t::high_prio
type_func_t high_prio
Definition: ald_dma.h:287
dma_config_t::R_power
dma_arbiter_config_t R_power
Definition: ald_dma.h:284
dma_ctrl_t::src_inc
uint32_t src_inc
Definition: ald_dma.h:196
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_DMA_DATASIZE_TYPE
#define IS_DMA_DATASIZE_TYPE(x)
Definition: ald_dma.h:328
dma_ctrl_t::next_useburst
uint32_t next_useburst
Definition: ald_dma.h:190
IS_CYCLECTRL_TYPE
#define IS_CYCLECTRL_TYPE(x)
Definition: ald_dma.h:331
IS_DMA_DATA_SIZE
#define IS_DMA_DATA_SIZE(x)
Definition: ald_dma.h:352
dma_ctrl_t::dst_inc
uint32_t dst_inc
Definition: ald_dma.h:198
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
dma_descriptor_t::dst
void * dst
Definition: ald_dma.h:208
dma_ctrl_t::dst_prot_ctrl
uint32_t dst_prot_ctrl
Definition: ald_dma.h:194
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
IS_DMA_MSEL_TYPE
#define IS_DMA_MSEL_TYPE(x)
Definition: ald_dma.h:322
dma_config_t::primary
type_func_t primary
Definition: ald_dma.h:285
dma_descriptor_t::ctrl
dma_ctrl_t ctrl
Definition: ald_dma.h:209
IS_DMA_DATAINC_TYPE
#define IS_DMA_DATAINC_TYPE(x)
Definition: ald_dma.h:324
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
dma_descriptor_t::src
void * src
Definition: ald_dma.h:207
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
IS_DMA_MSIGSEL_TYPE
#define IS_DMA_MSIGSEL_TYPE(x)
Definition: ald_dma.h:323
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_DMA_CHANNEL
#define IS_DMA_CHANNEL(x)
Definition: ald_dma.h:351
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
dma_descriptor_t
Channel control data structure.
Definition: ald_dma.h:206
dma_ctrl_t::cycle_ctrl
uint32_t cycle_ctrl
Definition: ald_dma.h:189
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
dma_ctrl_t::R_power
uint32_t R_power
Definition: ald_dma.h:192
IS_DMA_ARBITERCONFIG_TYPE
#define IS_DMA_ARBITERCONFIG_TYPE(x)
Definition: ald_dma.h:339
dma_config_t::interrupt
type_func_t interrupt
Definition: ald_dma.h:288
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
dma_ctrl_t::n_minus_1
uint32_t n_minus_1
Definition: ald_dma.h:191
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
IS_DMA
#define IS_DMA(x)
Definition: ald_dma.h:350


ALD User Manual: DMA Public Functions

Modules
DMA Public Functions
EASTSOFT ES32F3xx ALD » DMA
Collaboration diagram for DMA Public Functions:

Modules

Initialization functions
Initialization functions.
Configure DMA channel functions
Configure DMA channel functions.
DMA Control functions
DMA control functions.

Detailed Description


ALD User Manual: Initialization functions

Functions
Initialization functions
EASTSOFT ES32F3xx ALD » DMA » DMA Public Functions

Initialization functions. More...

Collaboration diagram for Initialization functions:

Functions

void | ald_dma_reset (DMA_TypeDef *DMAx)
Reset the DMA register. More...
void | ald_dma_init (DMA_TypeDef *DMAx)
DMA module initialization, this function is invoked by ald_cmu_init(). More...
void | ald_dma_config_struct (dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t. More...
void | ald_dma_config_sg_alt_desc (dma_descriptor_t *desc, dma_config_t *config, uint8_t memory)
Configure dma_descriptor_t structure using specified parameter. More...

Detailed Description

Initialization functions.

===================================================================

                #### Initialization functions ####

===================================================================
[..]
This subsection provides two functions to Initilizate DMA:
(+) ald_dma_reset(): Reset the DMA register.

(+) ald_dma_init(): Initializate the DMA module. this function is
    invoked by ald_cmu_init().
    this function do this:
    (++) Initializte private variable dma_ctrl_base and dma_cbk.
    (++) Reset DMA register.
    (++) Set DMA interrupt priority: preempt_prio=1, sub_priority=1
    (++) Enable DMA interrupt.
    (++) Enable DMA bus error interrupt.
    (++) Configure CTRLBASE resigter.
    (++) Enable DMA module.

(+) ald_dma_config_struct(): Configure dma_config_t
    structure using default parameter.

(+) ald_dma_config_sg_alt_desc(): Configure dma_descriptor_t
    structure using specified parameter. This function used
    in scatter-gather mode(memory or peripheral).

Function Documentation

◆ ald_dma_config_sg_alt_desc()

void ald_dma_config_sg_alt_desc | ( | dma_descriptor_t * | desc,
 |  | dma_config_t * | config,
 |  | uint8_t | memory
 | ) |  |

Configure dma_descriptor_t structure using specified parameter.

Note
This function used in scatter-gather mode(memory or peripheral).
Parameters
desc | Address of the alternate descriptor.
config | Pointer to the dma_config_t structure.
memory | Memory or peripheral scatter-gather.
Return values
None

Definition at line 316 of file ald_dma.c.

317 {
318 if ((desc == NULL) || (config == NULL))
319 return;
320
321 if (config->src_inc == DMA_DATA_INC_NONE)
322 desc->src = config->src;
323 else
324 desc->src = (void *)((uint32_t)config->src + ((config->size - 1) << (uint32_t)config->data_width));
325
326 if (config->dst_inc == DMA_DATA_INC_NONE)
327 desc->dst = config->dst;
328 else
329 desc->dst = (void *)((uint32_t)config->dst + ((config->size - 1) << (uint32_t)config->data_width));
330
331 desc->ctrl.cycle_ctrl = memory ? DMA_CYCLE_CTRL_MEM_SG_ALTERNATE : DMA_CYCLE_CTRL_PER_SG_ALTERNATE;
332 desc->ctrl.next_useburst = memory ? 0 : 1;
333 desc->ctrl.n_minus_1 = config->size - 1;
334 desc->ctrl.R_power = config->R_power;
335 desc->ctrl.src_prot_ctrl = 0;
336 desc->ctrl.dst_prot_ctrl = 0;
337 desc->ctrl.src_size = config->data_width;
338 desc->ctrl.src_inc = config->src_inc;
339 desc->ctrl.dst_size = config->data_width;
340 desc->ctrl.dst_inc = config->dst_inc;
341
342 return;
343 }
dma_ctrl_t::src_size
uint32_t src_size
Definition: ald_dma.h:195
dma_ctrl_t::dst_size
uint32_t dst_size
Definition: ald_dma.h:197
dma_ctrl_t::src_prot_ctrl
uint32_t src_prot_ctrl
Definition: ald_dma.h:193
dma_config_t::R_power
dma_arbiter_config_t R_power
Definition: ald_dma.h:284
dma_ctrl_t::src_inc
uint32_t src_inc
Definition: ald_dma.h:196
dma_ctrl_t::next_useburst
uint32_t next_useburst
Definition: ald_dma.h:190
dma_ctrl_t::dst_inc
uint32_t dst_inc
Definition: ald_dma.h:198
dma_descriptor_t::dst
void * dst
Definition: ald_dma.h:208
dma_ctrl_t::dst_prot_ctrl
uint32_t dst_prot_ctrl
Definition: ald_dma.h:194
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
dma_descriptor_t::ctrl
dma_ctrl_t ctrl
Definition: ald_dma.h:209
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
dma_descriptor_t::src
void * src
Definition: ald_dma.h:207
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
DMA_CYCLE_CTRL_PER_SG_ALTERNATE
Definition: ald_dma.h:243
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
dma_ctrl_t::cycle_ctrl
uint32_t cycle_ctrl
Definition: ald_dma.h:189
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
dma_ctrl_t::R_power
uint32_t R_power
Definition: ald_dma.h:192
dma_ctrl_t::n_minus_1
uint32_t n_minus_1
Definition: ald_dma.h:191
DMA_CYCLE_CTRL_MEM_SG_ALTERNATE
Definition: ald_dma.h:241

◆ ald_dma_config_struct()

void ald_dma_config_struct ( dma_config_t * p )

Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.

Parameters
p Pointer to dma_config_t structure, see dma_config_t
Return values
None

Definition at line 294 of file ald_dma.c.

295 {
296 p->data_width = DMA_DATA_SIZE_BYTE;
297 p->src_inc = DMA_DATA_INC_BYTE;
298 p->dst_inc = DMA_DATA_INC_BYTE;
299 p->R_power = DMA_R_POWER_1;
300 p->primary = ENABLE;
301 p->burst = DISABLE;
302 p->high_prio = DISABLE;
303 p->interrupt = ENABLE;
304
305 return;
306 }
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
dma_config_t::high_prio
type_func_t high_prio
Definition: ald_dma.h:287
dma_config_t::R_power
dma_arbiter_config_t R_power
Definition: ald_dma.h:284
DISABLE
Definition: type.h:48
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::primary
type_func_t primary
Definition: ald_dma.h:285
DMA_DATA_SIZE_BYTE
Definition: ald_dma.h:227
DMA_DATA_INC_BYTE
Definition: ald_dma.h:217
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
dma_config_t::interrupt
type_func_t interrupt
Definition: ald_dma.h:288
DMA_R_POWER_1
Definition: ald_dma.h:251

◆ ald_dma_init()

void ald_dma_init ( DMA_TypeDef * DMAx )

DMA module initialization, this function is invoked by ald_cmu_init().

Parameters
DMAx Pointer to DMA peripheral
Return values
None

Definition at line 270 of file ald_dma.c.

271 {
272 assert_param(IS_DMA(DMAx));
273
274 memset(dma0_ctrl_base, 0x0, sizeof(dma0_ctrl_base));
275 memset(dma0_cbk, 0x0, sizeof(dma0_cbk));
276
277 ald_dma_reset(DMAx);
278 NVIC_SetPriority(DMA_IRQn, 2);
279 NVIC_EnableIRQ(DMA_IRQn);
280 SET_BIT(DMAx->IER, DMA_IER_DMAERRIE_MSK);
281
282 WRITE_REG(DMAx->CTRLBASE, (uint32_t)&dma0_ctrl_base);
283 SET_BIT(DMAx->CFG, DMA_CFG_MASTER_ENABLE_MSK);
284
285 return;
286 }
assert_param
#define assert_param(x)
Definition: type.h:88
dma0_cbk
dma_call_back_t dma0_cbk[12]
Definition: ald_dma.c:77
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
ald_dma_reset
void ald_dma_reset(DMA_TypeDef *DMAx)
Reset the DMA register.
Definition: ald_dma.c:242
IS_DMA
#define IS_DMA(x)
Definition: ald_dma.h:350

◆ ald_dma_reset()

void ald_dma_reset ( DMA_TypeDef * DMAx )

Reset the DMA register.

Parameters
DMAx Pointer to DMA peripheral
Return values
None

Definition at line 242 of file ald_dma.c.

243 {
244 uint32_t i;
245
246 assert_param(IS_DMA(DMAx));
247
248 WRITE_REG(DMAx->CFG, 0x0);
249 WRITE_REG(DMAx->CHUSEBURSTCLR, 0xFFF);
250 WRITE_REG(DMAx->CHREQMASKCLR, 0xFFF);
251 WRITE_REG(DMAx->CHENCLR, 0xFFF);
252 WRITE_REG(DMAx->CHPRIALTCLR, 0xFFF);
253 WRITE_REG(DMAx->CHPRCLR, 0xFFF);
254 WRITE_REG(DMAx->ERRCLR, 0x1);
255 WRITE_REG(DMAx->IER, 0x0);
256 WRITE_REG(DMAx->ICFR, 0x80000FFF);
257
258 for (i = 0; i < DMA_CH_COUNT; ++i)
259 WRITE_REG(DMAx->CH_SELCON[i], 0x0);
260
261 return;
262 }
assert_param
#define assert_param(x)
Definition: type.h:88
DMA_CH_COUNT
#define DMA_CH_COUNT
Definition: ald_dma.h:39
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
IS_DMA
#define IS_DMA(x)
Definition: ald_dma.h:350


ALD User Manual: Configure DMA channel functions

Functions
Configure DMA channel functions
EASTSOFT ES32F3xx ALD » DMA » DMA Public Functions

Configure DMA channel functions. More...

Collaboration diagram for Configure DMA channel functions:

Functions

void | ald_dma_config_auto (dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is automatic. This mode is used to carry data from memory to memory. More...
void | ald_dma_restart_auto (dma_handle_t *hperh, void *src, void *dst, uint16_t size)
Restart DMA transmitted. The DMA mode is automatic. The other parameters have not changed except 'size' and 'addr'. More...
void | ald_dma_config_auto_easy (DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, uint8_t channel, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is automatic. This mode is used to carry data from memory to memory. If User want use the dma easily, they can invoke this function. More...
void | ald_dma_config_basic (dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral. More...
void | ald_dma_restart_basic (dma_handle_t *hperh, void *src, void *dst, uint16_t size)
Restart DMA transmitted. The DMA mode is basic. The other parameters have not changed except 'size' and 'addr'. More...
void | ald_dma_config_basic_easy (DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is basic. This mode is used to carry data from peripheral to memory or negative direction. If user want use the dma easily, they can invoke this function. More...
void | ald_dma_config_ping_pong (DMA_TypeDef *DMAx, dma_config_t *config, uint8_t first, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is ping-pong. More...
void | ald_dma_config_sg_mem (DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t channel, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is memory scatter-gather. More...
void | ald_dma_config_sg_per (DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst, dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is peripheral scatter-gather. More...

Detailed Description

Configure DMA channel functions.

===================================================================

                #### Configure DMA channel functions ####

===================================================================
[..]
This subsection provides some functions allowing to configure
DMA channel. Include two type DMA transfer:
(+) Carry data from memory to memory, this mode APIs are:
    (++) ald_dma_config_auto(): Configure DMA channel according to
         the specified parameter in the dma_handle_t structure.
    (++) ald_dma_restart_auto(): Restart DMA transmitted.
    (++) ald_dma_config_auto_easy(): Configure DMA channel according
         to the specified parameter. If you want use the dma easily,
         you can invoke this function.
    (++) ald_dma_config_sg_mem(): Carry data used scatter-gather mode.
(+) Carry data from peripheral to memory or from memory to peripheral,
    this mode APIs are:
    (++) ald_dma_config_basic(): Configure DMA channel according to
         the specified parameter in the dma_handle_t structure.
    (++) ald_dma_restart_basic(): Restart DMA transmitted.
    (++) ald_dma_config_basic_easy(): Configure DMA channel according
         to the specified parameter. If you want use the dma easily,
         you can invoke this function.
    (++) ald_dma_ping_pong(): Carry data used ping-pong mode.
    (++) ald_dma_config_sg_per(): Carry data used scatter-gather mode.

Function Documentation

◆ ald_dma_config_auto()

void ald_dma_config_auto ( dma_handle_t * hperh )

Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is automatic. This mode is used to carry data from memory to memory.

Parameters
hperh Pointer to DMA_handle_t structure that contains configuration information for specified DMA channel.
Return values
None

Definition at line 392 of file ald_dma.c.

393 {
394 dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk;
395 dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk;
396 dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg;
397 dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg;
398 dma_config_base(hperh->perh, DMA_CYCLE_CTRL_AUTO, &hperh->config);
399
400 ald_dma_clear_flag_status(hperh->perh, hperh->config.channel);
401 WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel));
402 SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel));
403
404 return;
405 }
dma_call_back_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:270
dma_call_back_t::err_arg
void * err_arg
Definition: ald_dma.h:271
dma_call_back_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:269
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
dma_call_back_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:268
dma_config_base
static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config_t *p)
Configure DMA channel using dma_config_t structure.
Definition: ald_dma.c:94
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma0_cbk
dma_call_back_t dma0_cbk[12]
Definition: ald_dma.c:77
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
ald_dma_clear_flag_status
void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel)
Clear the specified channel pending flag.
Definition: ald_dma.c:952
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
DMA_CYCLE_CTRL_AUTO
Definition: ald_dma.h:238
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291

◆ ald_dma_config_auto_easy()

void ald_dma_config_auto_easy | ( | DMA_TypeDef * | DMAx,
 |  | void * | src,
 |  | void * | dst,
 |  | uint16_t | size,
 |  | uint8_t | channel,
 |  | void(*)(void *arg) | cbk
 | ) |  |

Configure DMA channel according to the specified parameter. The DMA mode is automatic. This mode is used to carry data from memory to memory. If User want use the dma easily, they can invoke this function.

Parameters
DMAx | Pointer to DMA peripheral
src | Source data begin pointer
dst | Destination data begin pointer
size | The total number of DMA transfers that DMA cycle contains
channel | Channel index which will be used.
cbk | DMA complete callback function
Return values
None

Definition at line 464 of file ald_dma.c.

466 {
467 dma_handle_t hperh;
468
469 assert_param(IS_DMA(DMAx));
470
471 ald_dma_config_struct(&hperh.config);
472 hperh.config.src = src;
473 hperh.config.dst = dst;
474 hperh.config.size = size;
475 hperh.config.msel = DMA_MSEL_NONE;
476 hperh.config.msigsel = DMA_MSIGSEL_NONE;
477 hperh.config.channel = channel;
478
479 hperh.perh = DMAx;
480 hperh.cplt_cbk = cbk;
481 hperh.cplt_arg = NULL;
482 hperh.err_cbk = NULL;
483
484 ald_dma_clear_flag_status(DMAx, channel);
485 ald_dma_config_auto(&hperh);
486
487 return;
488 }
DMA_MSEL_NONE
Definition: ald_dma.h:78
dma_handle_t
DMA handle structure definition.
Definition: ald_dma.h:297
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
assert_param
#define assert_param(x)
Definition: type.h:88
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src
void * src
Definition: ald_dma.h:278
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
ald_dma_clear_flag_status
void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel)
Clear the specified channel pending flag.
Definition: ald_dma.c:952
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
DMA_MSIGSEL_NONE
Definition: ald_dma.h:115
ald_dma_config_auto
void ald_dma_config_auto(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is automatic. This mode is used to carry data from memory to memory.
Definition: ald_dma.c:392
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
IS_DMA
#define IS_DMA(x)
Definition: ald_dma.h:350

◆ ald_dma_config_basic()

void ald_dma_config_basic ( dma_handle_t * hperh )

Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.

Parameters
hperh Pointer to dma_handle_t structure that contains configuration information for specified DMA channel.
Return values
None

Definition at line 499 of file ald_dma.c.

500 {
501 dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk;
502 dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk;
503 dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg;
504 dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg;
505
506 ald_dma_clear_flag_status(hperh->perh, hperh->config.channel);
507 dma_config_base(hperh->perh, DMA_CYCLE_CTRL_BASIC, &hperh->config);
508 WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel));
509
510 return;
511 }
dma_call_back_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:270
dma_call_back_t::err_arg
void * err_arg
Definition: ald_dma.h:271
dma_call_back_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:269
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
dma_call_back_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:268
dma_config_base
static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config_t *p)
Configure DMA channel using dma_config_t structure.
Definition: ald_dma.c:94
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma0_cbk
dma_call_back_t dma0_cbk[12]
Definition: ald_dma.c:77
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
ald_dma_clear_flag_status
void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel)
Clear the specified channel pending flag.
Definition: ald_dma.c:952
DMA_CYCLE_CTRL_BASIC
Definition: ald_dma.h:237
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291

◆ ald_dma_config_basic_easy()

void ald_dma_config_basic_easy | ( | DMA_TypeDef * | DMAx,
 |  | void * | src,
 |  | void * | dst,
 |  | uint16_t | size,
 |  | dma_msel_t | msel,
 |  | dma_msigsel_t | msigsel,
 |  | uint8_t | channel,
 |  | void(*)(void *arg) | cbk
 | ) |  |

Configure DMA channel according to the specified parameter. The DMA mode is basic. This mode is used to carry data from peripheral to memory or negative direction. If user want use the dma easily, they can invoke this function.

Parameters
DMAx | Pointer to DMA peripheral
src | Source data begin pointer
dst | Destination data begin pointer
size | The total number of DMA transfers that DMA cycle contains
msel | Input source to DMA channel dma_msel_t
msigsel | Input signal to DMA channel dma_msigsel_t
channel | Channel index which will be used
cbk | DMA complete callback function
Return values
None

Definition at line 571 of file ald_dma.c.

573 {
574 dma_handle_t hperh;
575
576 assert_param(IS_DMA(DMAx));
577 ald_dma_config_struct(&hperh.config);
578
579 if (((uint32_t)src) >= 0x40000000)
580 hperh.config.src_inc = DMA_DATA_INC_NONE;
581
582 if (((uint32_t)dst) >= 0x40000000)
583 hperh.config.dst_inc = DMA_DATA_INC_NONE;
584
585 hperh.config.src = src;
586 hperh.config.dst = dst;
587 hperh.config.size = size;
588 hperh.config.msel = msel;
589 hperh.config.msigsel = msigsel;
590 hperh.config.channel = channel;
591
592 hperh.perh = DMAx;
593 hperh.cplt_cbk = cbk;
594 hperh.cplt_arg = NULL;
595 hperh.err_cbk = NULL;
596
597 ald_dma_clear_flag_status(DMAx, channel);
598 ald_dma_config_basic(&hperh);
599
600 return;
601 }
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
dma_handle_t
DMA handle structure definition.
Definition: ald_dma.h:297
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
assert_param
#define assert_param(x)
Definition: type.h:88
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
ald_dma_clear_flag_status
void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel)
Clear the specified channel pending flag.
Definition: ald_dma.c:952
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
IS_DMA
#define IS_DMA(x)
Definition: ald_dma.h:350

◆ ald_dma_config_ping_pong()

void ald_dma_config_ping_pong | ( | DMA_TypeDef * | DMAx,
 |  | dma_config_t * | config,
 |  | uint8_t | first,
 |  | void(*)(void *arg) | cbk
 | ) |  |

Configure DMA channel according to the specified parameter. The DMA mode is ping-pong.

Note
The ping-pong mode does not support memory to memory.
Parameters
DMAx | Pointer to DMA peripheral.
config | Pointer to the dma_config_t structure which contains the specified parameters.
first | Whether it is the first transmission. 1-first, 0-not first.
cbk | DMA complete callback function.
Return values
None

Definition at line 614 of file ald_dma.c.

616 {
617 dma_descriptor_t *desc;
618
619 assert_param(IS_DMA(DMAx));
620 assert_param(config->src != NULL);
621 assert_param(config->dst != NULL);
622 assert_param(IS_DMA_DATA_SIZE(config->size));
623 assert_param(IS_DMA_DATASIZE_TYPE(config->data_width));
624 assert_param(IS_DMA_DATAINC_TYPE(config->src_inc));
625 assert_param(IS_DMA_DATAINC_TYPE(config->dst_inc));
626 assert_param(IS_DMA_ARBITERCONFIG_TYPE(config->R_power));
627 assert_param(IS_FUNC_STATE(config->primary));
628 assert_param(IS_FUNC_STATE(config->burst));
629 assert_param(IS_FUNC_STATE(config->high_prio));
630 assert_param(IS_FUNC_STATE(config->interrupt));
631 assert_param(IS_DMA_MSEL_TYPE(config->msel));
632 assert_param(IS_DMA_MSIGSEL_TYPE(config->msigsel));
633 assert_param(IS_DMA_CHANNEL(config->channel));
634
635 dma0_cbk[config->channel].cplt_cbk = cbk;
636 dma0_cbk[config->channel].err_cbk = NULL;
637 dma0_cbk[config->channel].cplt_arg = NULL;
638 dma0_cbk[config->channel].err_arg = NULL;
639
640 if (config->primary)
641 desc = (dma_descriptor_t *)(DMAx->CTRLBASE) + config->channel;
642 else
643 desc = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + config->channel;
644
645 if (config->src_inc == DMA_DATA_INC_NONE)
646 desc->src = config->src;
647 else
648 desc->src = (void *)((uint32_t)config->src + ((config->size - 1) << (uint32_t)config->data_width));
649
650 if (config->dst_inc == DMA_DATA_INC_NONE)
651 desc->dst = config->dst;
652 else
653 desc->dst = (void *)((uint32_t)config->dst + ((config->size - 1) << (uint32_t)config->data_width));
654
655 desc->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_PINGPONG;
656 desc->ctrl.next_useburst = 0;
657 desc->ctrl.n_minus_1 = config->size - 1;
658 desc->ctrl.R_power = config->R_power;
659 desc->ctrl.src_prot_ctrl = 0,
660 desc->ctrl.dst_prot_ctrl = 0,
661 desc->ctrl.src_size = config->data_width;
662 desc->ctrl.src_inc = config->src_inc;
663 desc->ctrl.dst_size = config->data_width;
664 desc->ctrl.dst_inc = config->dst_inc;
665
666 if (!first)
667 return;
668
669 if (config->primary)
670 WRITE_REG(DMAx->CHPRIALTCLR, (1 << config->channel));
671 else
672 WRITE_REG(DMAx->CHPRIALTSET, (1 << config->channel));
673
674 if (config->burst)
675 WRITE_REG(DMAx->CHUSEBURSTSET, (1 << config->channel));
676 else
677 WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << config->channel));
678
679 if (config->high_prio)
680 WRITE_REG(DMAx->CHPRSET, (1 << config->channel));
681 else
682 WRITE_REG(DMAx->CHPRCLR, (1 << config->channel));
683
684 if (config->interrupt)
685 SET_BIT(DMAx->IER, (1 << config->channel));
686 else
687 CLEAR_BIT(DMAx->IER, (1 << config->channel));
688
689 MODIFY_REG(DMAx->CH_SELCON[config->channel], DMA_CH0_SELCON_MSEL_MSK, config->msel << DMA_CH0_SELCON_MSEL_POSS);
690 MODIFY_REG(DMAx->CH_SELCON[config->channel], DMA_CH0_SELCON_MSIGSEL_MSK, config->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS);
691
692 WRITE_REG(DMAx->ICFR, (1 << config->channel));
693 WRITE_REG(DMAx->CHENSET, (1 << config->channel));
694
695 return;
696 }
dma_ctrl_t::src_size
uint32_t src_size
Definition: ald_dma.h:195
dma_call_back_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:270
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
dma_ctrl_t::dst_size
uint32_t dst_size
Definition: ald_dma.h:197
dma_ctrl_t::src_prot_ctrl
uint32_t src_prot_ctrl
Definition: ald_dma.h:193
dma_config_t::high_prio
type_func_t high_prio
Definition: ald_dma.h:287
dma_call_back_t::err_arg
void * err_arg
Definition: ald_dma.h:271
dma_config_t::R_power
dma_arbiter_config_t R_power
Definition: ald_dma.h:284
dma_call_back_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:269
dma_ctrl_t::src_inc
uint32_t src_inc
Definition: ald_dma.h:196
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_DMA_DATASIZE_TYPE
#define IS_DMA_DATASIZE_TYPE(x)
Definition: ald_dma.h:328
dma_ctrl_t::next_useburst
uint32_t next_useburst
Definition: ald_dma.h:190
IS_DMA_DATA_SIZE
#define IS_DMA_DATA_SIZE(x)
Definition: ald_dma.h:352
dma_ctrl_t::dst_inc
uint32_t dst_inc
Definition: ald_dma.h:198
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
dma_call_back_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:268
dma_descriptor_t::dst
void * dst
Definition: ald_dma.h:208
dma_ctrl_t::dst_prot_ctrl
uint32_t dst_prot_ctrl
Definition: ald_dma.h:194
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
IS_DMA_MSEL_TYPE
#define IS_DMA_MSEL_TYPE(x)
Definition: ald_dma.h:322
dma_config_t::primary
type_func_t primary
Definition: ald_dma.h:285
dma0_cbk
dma_call_back_t dma0_cbk[12]
Definition: ald_dma.c:77
dma_descriptor_t::ctrl
dma_ctrl_t ctrl
Definition: ald_dma.h:209
IS_DMA_DATAINC_TYPE
#define IS_DMA_DATAINC_TYPE(x)
Definition: ald_dma.h:324
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
dma_descriptor_t::src
void * src
Definition: ald_dma.h:207
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
IS_DMA_MSIGSEL_TYPE
#define IS_DMA_MSIGSEL_TYPE(x)
Definition: ald_dma.h:323
DMA_CYCLE_CTRL_PINGPONG
Definition: ald_dma.h:239
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_DMA_CHANNEL
#define IS_DMA_CHANNEL(x)
Definition: ald_dma.h:351
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
dma_descriptor_t
Channel control data structure.
Definition: ald_dma.h:206
dma_ctrl_t::cycle_ctrl
uint32_t cycle_ctrl
Definition: ald_dma.h:189
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
dma_ctrl_t::R_power
uint32_t R_power
Definition: ald_dma.h:192
IS_DMA_ARBITERCONFIG_TYPE
#define IS_DMA_ARBITERCONFIG_TYPE(x)
Definition: ald_dma.h:339
dma_config_t::interrupt
type_func_t interrupt
Definition: ald_dma.h:288
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
dma_ctrl_t::n_minus_1
uint32_t n_minus_1
Definition: ald_dma.h:191
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
IS_DMA
#define IS_DMA(x)
Definition: ald_dma.h:350

◆ ald_dma_config_sg_mem()

void ald_dma_config_sg_mem | ( | DMA_TypeDef * | DMAx,
 |  | dma_descriptor_t * | desc,
 |  | uint32_t | nr,
 |  | uint8_t | channel,
 |  | void(*)(void *arg) | cbk
 | ) |  |

Configure DMA channel according to the specified parameter. The DMA mode is memory scatter-gather.

Parameters
DMAx | Pointer to DMA peripheral.
desc | Pointer to first alternate descriptor.
nr | Number of the alternate descriptor.
channel | Channel index which will be used.
cbk | DMA complete callback function.
Return values
None

Definition at line 708 of file ald_dma.c.

710 {
711 dma_descriptor_t *tmp = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel;
712 dma_descriptor_t *_tmp = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel;
713
714 assert_param(IS_DMA(DMAx));
715 assert_param(IS_DMA_CHANNEL(channel));
716
717 if ((desc == NULL) || (nr == 0))
718 return;
719
720 dma0_cbk[channel].cplt_cbk = cbk;
721 dma0_cbk[channel].err_cbk = NULL;
722 dma0_cbk[channel].cplt_arg = NULL;
723 dma0_cbk[channel].err_arg = NULL;
724
725 tmp->src = (void *)((uint32_t)desc + (((nr << 2) - 1) << DMA_DATA_INC_WORD));
726 tmp->dst = (void *)((uint32_t)_tmp + ((4 - 1) << DMA_DATA_INC_WORD));
727 tmp->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_MEM_SG_PRIMARY;
728 tmp->ctrl.next_useburst = 0;
729 tmp->ctrl.n_minus_1 = (nr << 2) - 1;
730 tmp->ctrl.R_power = DMA_R_POWER_4;
731 tmp->ctrl.src_prot_ctrl = 0,
732 tmp->ctrl.dst_prot_ctrl = 0,
733 tmp->ctrl.src_size = DMA_DATA_SIZE_WORD;
734 tmp->ctrl.src_inc = DMA_DATA_INC_WORD;
735 tmp->ctrl.dst_size = DMA_DATA_SIZE_WORD;
736 tmp->ctrl.dst_inc = DMA_DATA_INC_WORD;
737
738 desc[nr - 1].ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO;
739 WRITE_REG(DMAx->CHPRIALTCLR, (1 << channel));
740 WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << channel));
741 WRITE_REG(DMAx->CHPRCLR, (1 << channel));
742
743 WRITE_REG(DMAx->ICFR, (1 << channel));
744 SET_BIT(DMAx->IER, (1 << channel));
745 WRITE_REG(DMAx->CHENSET, (1 << channel));
746 SET_BIT(DMAx->CHSWREQ, (1 << channel));
747
748 return;
749 }
DMA_R_POWER_4
Definition: ald_dma.h:253
dma_ctrl_t::src_size
uint32_t src_size
Definition: ald_dma.h:195
dma_call_back_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:270
dma_ctrl_t::dst_size
uint32_t dst_size
Definition: ald_dma.h:197
dma_ctrl_t::src_prot_ctrl
uint32_t src_prot_ctrl
Definition: ald_dma.h:193
dma_call_back_t::err_arg
void * err_arg
Definition: ald_dma.h:271
dma_call_back_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:269
dma_ctrl_t::src_inc
uint32_t src_inc
Definition: ald_dma.h:196
assert_param
#define assert_param(x)
Definition: type.h:88
dma_ctrl_t::next_useburst
uint32_t next_useburst
Definition: ald_dma.h:190
dma_ctrl_t::dst_inc
uint32_t dst_inc
Definition: ald_dma.h:198
DMA_CYCLE_CTRL_MEM_SG_PRIMARY
Definition: ald_dma.h:240
dma_call_back_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:268
dma_descriptor_t::dst
void * dst
Definition: ald_dma.h:208
dma_ctrl_t::dst_prot_ctrl
uint32_t dst_prot_ctrl
Definition: ald_dma.h:194
DMA_DATA_INC_WORD
Definition: ald_dma.h:219
DMA_DATA_SIZE_WORD
Definition: ald_dma.h:229
dma0_cbk
dma_call_back_t dma0_cbk[12]
Definition: ald_dma.c:77
dma_descriptor_t::ctrl
dma_ctrl_t ctrl
Definition: ald_dma.h:209
dma_descriptor_t::src
void * src
Definition: ald_dma.h:207
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_DMA_CHANNEL
#define IS_DMA_CHANNEL(x)
Definition: ald_dma.h:351
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
dma_descriptor_t
Channel control data structure.
Definition: ald_dma.h:206
dma_ctrl_t::cycle_ctrl
uint32_t cycle_ctrl
Definition: ald_dma.h:189
dma_ctrl_t::R_power
uint32_t R_power
Definition: ald_dma.h:192
DMA_CYCLE_CTRL_AUTO
Definition: ald_dma.h:238
dma_ctrl_t::n_minus_1
uint32_t n_minus_1
Definition: ald_dma.h:191
IS_DMA
#define IS_DMA(x)
Definition: ald_dma.h:350

◆ ald_dma_config_sg_per()

void ald_dma_config_sg_per | ( | DMA_TypeDef * | DMAx,
 |  | dma_descriptor_t * | desc,
 |  | uint32_t | nr,
 |  | uint8_t | burst,
 |  | dma_msel_t | msel,
 |  | dma_msigsel_t | msigsel,
 |  | uint8_t | channel,
 |  | void(*)(void *arg) | cbk
 | ) |  |

Configure DMA channel according to the specified parameter. The DMA mode is peripheral scatter-gather.

Note
The size of the first transmission must be 5.
Parameters
DMAx | Pointer to DMA peripheral.
desc | Pointer to first alternate descriptor.
nr | Number of the alternate descriptor.
burst | 1-Enable burst, 0-Disable burst.
msel | Input source to DMA channel dma_msel_t
msigsel | Input signal to DMA channel dma_msigsel_t
channel | Channel index which will be used.
cbk | DMA complete callback function.
Return values
None

Definition at line 765 of file ald_dma.c.

767 {
768 dma_descriptor_t *tmp = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel;
769 dma_descriptor_t *_tmp = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel;
770
771 assert_param(IS_DMA(DMAx));
772 assert_param(IS_DMA_MSEL_TYPE(msel));
773 assert_param(IS_DMA_MSIGSEL_TYPE(msigsel));
774 assert_param(IS_DMA_CHANNEL(channel));
775
776 if ((desc == NULL) || (nr == 0))
777 return;
778
779 dma0_cbk[channel].cplt_cbk = cbk;
780 dma0_cbk[channel].err_cbk = NULL;
781 dma0_cbk[channel].cplt_arg = NULL;
782 dma0_cbk[channel].err_arg = NULL;
783
784 tmp->src = (void *)((uint32_t)desc + (((nr << 2) - 1) << DMA_DATA_INC_WORD));
785 tmp->dst = (void *)((uint32_t)_tmp + ((4 - 1) << DMA_DATA_INC_WORD));
786 tmp->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_PER_SG_PRIMARY;
787 tmp->ctrl.next_useburst = 0;
788 tmp->ctrl.n_minus_1 = (nr << 2) - 1;
789 tmp->ctrl.R_power = DMA_R_POWER_4;
790 tmp->ctrl.src_prot_ctrl = 0,
791 tmp->ctrl.dst_prot_ctrl = 0,
792 tmp->ctrl.src_size = DMA_DATA_SIZE_WORD;
793 tmp->ctrl.src_inc = DMA_DATA_INC_WORD;
794 tmp->ctrl.dst_size = DMA_DATA_SIZE_WORD;
795 tmp->ctrl.dst_inc = DMA_DATA_INC_WORD;
796
797 desc[nr - 1].ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC;
798 WRITE_REG(DMAx->CHPRIALTCLR, (1 << channel));
799 burst ? (DMAx->CHUSEBURSTSET = (1 << channel)) : (DMAx->CHUSEBURSTCLR, (1 << channel));
800 WRITE_REG(DMAx->CHPRCLR, (1 << channel));
801
802 MODIFY_REG(DMAx->CH_SELCON[channel], DMA_CH0_SELCON_MSEL_MSK, msel << DMA_CH0_SELCON_MSEL_POSS);
803 MODIFY_REG(DMAx->CH_SELCON[channel], DMA_CH0_SELCON_MSIGSEL_MSK, msigsel << DMA_CH0_SELCON_MSIGSEL_POSS);
804
805 WRITE_REG(DMAx->ICFR, (1 << channel));
806 SET_BIT(DMAx->IER, (1 << channel));
807 WRITE_REG(DMAx->CHENSET, (1 << channel));
808
809 return;
810 }
DMA_R_POWER_4
Definition: ald_dma.h:253
dma_ctrl_t::src_size
uint32_t src_size
Definition: ald_dma.h:195
dma_call_back_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:270
dma_ctrl_t::dst_size
uint32_t dst_size
Definition: ald_dma.h:197
dma_ctrl_t::src_prot_ctrl
uint32_t src_prot_ctrl
Definition: ald_dma.h:193
dma_call_back_t::err_arg
void * err_arg
Definition: ald_dma.h:271
dma_call_back_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:269
dma_ctrl_t::src_inc
uint32_t src_inc
Definition: ald_dma.h:196
assert_param
#define assert_param(x)
Definition: type.h:88
dma_ctrl_t::next_useburst
uint32_t next_useburst
Definition: ald_dma.h:190
dma_ctrl_t::dst_inc
uint32_t dst_inc
Definition: ald_dma.h:198
dma_call_back_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:268
dma_descriptor_t::dst
void * dst
Definition: ald_dma.h:208
dma_ctrl_t::dst_prot_ctrl
uint32_t dst_prot_ctrl
Definition: ald_dma.h:194
IS_DMA_MSEL_TYPE
#define IS_DMA_MSEL_TYPE(x)
Definition: ald_dma.h:322
DMA_DATA_INC_WORD
Definition: ald_dma.h:219
DMA_DATA_SIZE_WORD
Definition: ald_dma.h:229
dma0_cbk
dma_call_back_t dma0_cbk[12]
Definition: ald_dma.c:77
dma_descriptor_t::ctrl
dma_ctrl_t ctrl
Definition: ald_dma.h:209
DMA_CYCLE_CTRL_PER_SG_PRIMARY
Definition: ald_dma.h:242
DMA_CYCLE_CTRL_BASIC
Definition: ald_dma.h:237
dma_descriptor_t::src
void * src
Definition: ald_dma.h:207
IS_DMA_MSIGSEL_TYPE
#define IS_DMA_MSIGSEL_TYPE(x)
Definition: ald_dma.h:323
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_DMA_CHANNEL
#define IS_DMA_CHANNEL(x)
Definition: ald_dma.h:351
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
dma_descriptor_t
Channel control data structure.
Definition: ald_dma.h:206
dma_ctrl_t::cycle_ctrl
uint32_t cycle_ctrl
Definition: ald_dma.h:189
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dma_ctrl_t::R_power
uint32_t R_power
Definition: ald_dma.h:192
dma_ctrl_t::n_minus_1
uint32_t n_minus_1
Definition: ald_dma.h:191
IS_DMA
#define IS_DMA(x)
Definition: ald_dma.h:350

◆ ald_dma_restart_auto()

void ald_dma_restart_auto | ( | dma_handle_t * | hperh,
 |  | void * | src,
 |  | void * | dst,
 |  | uint16_t | size
 | ) |  |

Restart DMA transmitted. The DMA mode is automatic. The other parameters have not changed except 'size' and 'addr'.

Parameters
hperh | Pointer to DMA_handle_t structure that contains configuration information for specified DMA channel.
src | Source data begin pointer
dst | Destination data begin pointer
size | Size.
Return values
None

Definition at line 417 of file ald_dma.c.

418 {
419 dma_descriptor_t *descr;
420
421 if (hperh->config.primary)
422 descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel;
423 else
424 descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel;
425
426 if (src) {
427 if (hperh->config.src_inc == DMA_DATA_INC_NONE)
428 descr->src = src;
429 else
430 descr->src = (void *)((uint32_t)src + ((size - 1) << (uint32_t)hperh->config.data_width));
431 }
432
433 if (dst) {
434 if (hperh->config.dst_inc == DMA_DATA_INC_NONE)
435 descr->dst = dst;
436 else
437 descr->dst = (void *)((uint32_t)dst + ((size - 1) << (uint32_t)hperh->config.data_width));
438 }
439
440 ald_dma_clear_flag_status(hperh->perh, hperh->config.channel);
441 descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO;
442 descr->ctrl.n_minus_1 = size - 1;
443 WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel));
444 SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel));
445 return;
446 }
dma_descriptor_t::dst
void * dst
Definition: ald_dma.h:208
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::primary
type_func_t primary
Definition: ald_dma.h:285
dma_descriptor_t::ctrl
dma_ctrl_t ctrl
Definition: ald_dma.h:209
ald_dma_clear_flag_status
void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel)
Clear the specified channel pending flag.
Definition: ald_dma.c:952
dma_descriptor_t::src
void * src
Definition: ald_dma.h:207
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
dma_descriptor_t
Channel control data structure.
Definition: ald_dma.h:206
dma_ctrl_t::cycle_ctrl
uint32_t cycle_ctrl
Definition: ald_dma.h:189
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
DMA_CYCLE_CTRL_AUTO
Definition: ald_dma.h:238
dma_ctrl_t::n_minus_1
uint32_t n_minus_1
Definition: ald_dma.h:191
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291

◆ ald_dma_restart_basic()

void ald_dma_restart_basic | ( | dma_handle_t * | hperh,
 |  | void * | src,
 |  | void * | dst,
 |  | uint16_t | size
 | ) |  |

Restart DMA transmitted. The DMA mode is basic. The other parameters have not changed except 'size' and 'addr'.

Parameters
hperh | Pointer to DMA_handle_t structure that contains configuration information for specified DMA channel.
src | Source data begin pointer
dst | Destination data begin pointer
size | Size.
Return values
None

Definition at line 523 of file ald_dma.c.

524 {
525 dma_descriptor_t *descr;
526
527 if (hperh->config.primary)
528 descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel;
529 else
530 descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel;
531
532 if (src) {
533 if (hperh->config.src_inc == DMA_DATA_INC_NONE)
534 descr->src = src;
535 else
536 descr->src = (void *)((uint32_t)src + ((size - 1) << (uint32_t)hperh->config.data_width));
537 }
538
539 if (dst) {
540 if (hperh->config.dst_inc == DMA_DATA_INC_NONE)
541 descr->dst = dst;
542 else
543 descr->dst = (void *)((uint32_t)dst + ((size - 1) << (uint32_t)hperh->config.data_width));
544 }
545
546 ald_dma_clear_flag_status(hperh->perh, hperh->config.channel);
547 descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC;
548 descr->ctrl.n_minus_1 = size - 1;
549 WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel));
550
551 return;
552 }
dma_descriptor_t::dst
void * dst
Definition: ald_dma.h:208
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::primary
type_func_t primary
Definition: ald_dma.h:285
dma_descriptor_t::ctrl
dma_ctrl_t ctrl
Definition: ald_dma.h:209
ald_dma_clear_flag_status
void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel)
Clear the specified channel pending flag.
Definition: ald_dma.c:952
DMA_CYCLE_CTRL_BASIC
Definition: ald_dma.h:237
dma_descriptor_t::src
void * src
Definition: ald_dma.h:207
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
dma_descriptor_t
Channel control data structure.
Definition: ald_dma.h:206
dma_ctrl_t::cycle_ctrl
uint32_t cycle_ctrl
Definition: ald_dma.h:189
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
dma_ctrl_t::n_minus_1
uint32_t n_minus_1
Definition: ald_dma.h:191
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291


ALD User Manual: DMA Control functions

Functions
DMA Control functions
EASTSOFT ES32F3xx ALD » DMA » DMA Public Functions

DMA control functions. More...

Collaboration diagram for DMA Control functions:

Functions

void | ald_dma_channel_config (DMA_TypeDef *DMAx, uint8_t channel, type_func_t state)
Configure channel enable or disable. It will unbind descriptor with channel, when channel has been disable. More...
void | ald_dma_interrupt_config (DMA_TypeDef *DMAx, uint8_t channel, type_func_t state)
Configure the interrupt enable or disable. More...
it_status_t | ald_dma_get_it_status (DMA_TypeDef *DMAx, uint8_t channel)
Check whether the specified channel interrupt is set or reset. More...
flag_status_t | ald_dma_get_flag_status (DMA_TypeDef *DMAx, uint8_t channel)
Check whether the specified channel flag is set or reset. More...
void | ald_dma_clear_flag_status (DMA_TypeDef *DMAx, uint8_t channel)
Clear the specified channel pending flag. More...
dma_descrp_cplt_t | ald_dma_descriptor_cplt_get (DMA_TypeDef *DMAx, uint8_t channel)
Get the completion status of the descriptor. More...
void | ald_dma_irq_handler (void)
Handle DMA interrupt. More...

Detailed Description

DMA control functions.

===================================================================

                #### DMA control functions ####

===================================================================
[..]
This subsection provides some functions allowing to control DMA:
(+) ald_dma_channel_config(): Control DMA channel ENABLE/DISABLE.
(+) ald_dma_interrupt_config(): Control DMA channel interrupt ENABLE or
    DISABLE.
(+) ald_dma_get_it_status(): Check whether the specified channel
    interrupt is SET or RESET.
(+) ald_dma_get_flag_status(): Check whether the specified channel
    flag is SET or RESET.
(+) ald_dma_clear_flag_status(): Clear the specified channel
    pending flag

Function Documentation

◆ ald_dma_channel_config()

void ald_dma_channel_config | ( | DMA_TypeDef * | DMAx,
 |  | uint8_t | channel,
 |  | type_func_t | state
 | ) |  |

Configure channel enable or disable. It will unbind descriptor with channel, when channel has been disable.

Parameters
DMAx | Pointer to DMA peripheral
channel | channel index
state status of channel:
  • ENABLE: Enable the channel
  • DISABLE: Disable the channel
Return values
None

Definition at line 850 of file ald_dma.c.

851 {
852 dma_descriptor_t *descr, *alt_descr;
853
854 assert_param(IS_DMA(DMAx));
855 assert_param(IS_DMA_CHANNEL(channel));
856 assert_param(IS_FUNC_STATE(state));
857
858 descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel;
859 alt_descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel;
860
861 if (state) {
862 WRITE_REG(DMAx->CHENSET, (1 << channel));
863 }
864 else {
865 memset(descr, 0x00, sizeof(dma_descriptor_t));
866 memset(alt_descr, 0x00, sizeof(dma_descriptor_t));
867 WRITE_REG(DMAx->CH_SELCON[channel], 0x0);
868 WRITE_REG(DMAx->CHENCLR, (1 << channel));
869 }
870
871 return;
872 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_DMA_CHANNEL
#define IS_DMA_CHANNEL(x)
Definition: ald_dma.h:351
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
dma_descriptor_t
Channel control data structure.
Definition: ald_dma.h:206
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
IS_DMA
#define IS_DMA(x)
Definition: ald_dma.h:350

◆ ald_dma_clear_flag_status()

void ald_dma_clear_flag_status | ( | DMA_TypeDef * | DMAx,
 |  | uint8_t | channel
 | ) |  |

Clear the specified channel pending flag.

Parameters
DMAx Pointer to DMA peripheral
channel Channel index or DMA_ERR
  • 0~11: Channel index
  • DMA_ERR: DMA bus error
Return values
None

Definition at line 952 of file ald_dma.c.

953 {
954 assert_param(IS_DMA(DMAx));
955 assert_param(IS_DMA_IT_TYPE(channel));
956
957 WRITE_REG(DMAx->ICFR, (1 << channel));
958 return;
959 }
assert_param
#define assert_param(x)
Definition: type.h:88
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
IS_DMA_IT_TYPE
#define IS_DMA_IT_TYPE(x)
Definition: ald_dma.h:353
IS_DMA
#define IS_DMA(x)
Definition: ald_dma.h:350

◆ ald_dma_descriptor_cplt_get()

dma_descrp_cplt_t ald_dma_descriptor_cplt_get | ( | DMA_TypeDef * | DMAx,
 |  | uint8_t | channel
 | ) |  |

Get the completion status of the descriptor.

Parameters
DMAx | Pointer to DMA peripheral
channel | Channel index
Return values
Completion status:
  • DMA_DESCP_CPLT_PRI: Primary descriptor has been completed
  • DMA_DESCP_CPLT_ALT: Alternate descriptor has been completed
  • DMA_DESCP_CPLT_ALL: Both primary and alternate descriptors have been completed

Definition at line 970 of file ald_dma.c.

971 {
972 uint8_t pri, alt;
973 dma_descriptor_t *desc;
974
975 assert_param(IS_DMA(DMAx));
976 assert_param(IS_DMA_IT_TYPE(channel));
977
978 desc = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel;
979 pri = desc->ctrl.cycle_ctrl;
980 desc = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel;
981 alt = desc->ctrl.cycle_ctrl;
982
983 if ((pri == 0) && (alt == 0))
984 return DMA_DESCP_CPLT_ALL;
985
986 if (pri == 0)
987 return DMA_DESCP_CPLT_PRI;
988 else
989 return DMA_DESCP_CPLT_ALT;
990 }
assert_param
#define assert_param(x)
Definition: type.h:88
DMA_DESCP_CPLT_PRI
Definition: ald_dma.h:310
DMA_DESCP_CPLT_ALL
Definition: ald_dma.h:312
dma_descriptor_t::ctrl
dma_ctrl_t ctrl
Definition: ald_dma.h:209
DMA_DESCP_CPLT_ALT
Definition: ald_dma.h:311
dma_descriptor_t
Channel control data structure.
Definition: ald_dma.h:206
dma_ctrl_t::cycle_ctrl
uint32_t cycle_ctrl
Definition: ald_dma.h:189
IS_DMA_IT_TYPE
#define IS_DMA_IT_TYPE(x)
Definition: ald_dma.h:353
IS_DMA
#define IS_DMA(x)
Definition: ald_dma.h:350

◆ ald_dma_get_flag_status()

flag_status_t ald_dma_get_flag_status | ( | DMA_TypeDef * | DMAx,
 |  | uint8_t | channel
 | ) |  |

Check whether the specified channel flag is set or reset.

Parameters
DMAx Pointer to DMA peripheral
channel Channel index or DMA_ERR
  • 0~11: Channel index
  • DMA_ERR: DMA bus error
Return values
Status
  • SET: Channel flag is set
  • RESET: Channel flag is reset

Definition at line 933 of file ald_dma.c.

934 {
935 assert_param(IS_DMA(DMAx));
936 assert_param(IS_DMA_IT_TYPE(channel));
937
938 if (READ_BIT(DMAx->IFLAG, (1 << channel)))
939 return SET;
940
941 return RESET;
942 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
RESET
Definition: type.h:38
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
IS_DMA_IT_TYPE
#define IS_DMA_IT_TYPE(x)
Definition: ald_dma.h:353
IS_DMA
#define IS_DMA(x)
Definition: ald_dma.h:350

◆ ald_dma_get_it_status()

it_status_t ald_dma_get_it_status | ( | DMA_TypeDef * | DMAx,
 |  | uint8_t | channel
 | ) |  |

Check whether the specified channel interrupt is set or reset.

Parameters
DMAx Pointer to DMA peripheral
channel Channel index or DMA_ERR
  • 0~11: Channel index
  • DMA_ERR: DMA bus error
Return values
Status
  • SET: Channel interrupt is set
  • RESET: Channel interrupt is reset

Definition at line 911 of file ald_dma.c.

912 {
913 assert_param(IS_DMA(DMAx));
914 assert_param(IS_DMA_IT_TYPE(channel));
915
916 if (READ_BIT(DMAx->IER, (1 << channel)))
917 return SET;
918
919 return RESET;
920 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
RESET
Definition: type.h:38
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
IS_DMA_IT_TYPE
#define IS_DMA_IT_TYPE(x)
Definition: ald_dma.h:353
IS_DMA
#define IS_DMA(x)
Definition: ald_dma.h:350

◆ ald_dma_interrupt_config()

void ald_dma_interrupt_config | ( | DMA_TypeDef * | DMAx,
 |  | uint8_t | channel,
 |  | type_func_t | state
 | ) |  |

Configure the interrupt enable or disable.

Parameters
DMAx Pointer to DMA peripheral
channel Channel index or DMA_ERR.
  • 0~11: Channel index
  • DMA_ERR: DMA bus error
state status of channel:
  • ENABLE: Enable the channel
  • DISABLE: Disable the channel
Return values
None

Definition at line 886 of file ald_dma.c.

887 {
888 assert_param(IS_DMA(DMAx));
889 assert_param(IS_DMA_IT_TYPE(channel));
890 assert_param(IS_FUNC_STATE(state));
891
892 if (state)
893 SET_BIT(DMAx->IER, (1 << channel));
894 else
895 CLEAR_BIT(DMAx->IER, (1 << channel));
896
897 return;
898 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
IS_DMA_IT_TYPE
#define IS_DMA_IT_TYPE(x)
Definition: ald_dma.h:353
IS_DMA
#define IS_DMA(x)
Definition: ald_dma.h:350

◆ ald_dma_irq_handler()

void ald_dma_irq_handler ( void )

Handle DMA interrupt.

Return values
None

Definition at line 170 of file ald_dma.c.

171 {
172 uint32_t i, reg = DMA0->IFLAG;
173
174 for (i = 0; i < DMA_CH_COUNT; ++i) {
175 if (READ_BIT(reg, (1 << i))) {
176 if (dma0_cbk[i].cplt_cbk != NULL)
177 dma0_cbk[i].cplt_cbk(dma0_cbk[i].cplt_arg);
178
179 ald_dma_clear_flag_status(DMA0, i);
180 }
181 }
182
183 if (READ_BIT(reg, (1U << DMA_ERR))) {
184 ald_dma_clear_flag_status(DMA0, DMA_ERR);
185
186 for (i = 0; i < DMA_CH_COUNT; ++i) {
187 if (((DMA0->CHENSET >> i) & 0x1) && (dma0_cbk[i].err_cbk != NULL))
188 dma0_cbk[i].err_cbk(dma0_cbk[i].err_arg);
189 }
190 }
191
192 return;
193 }
dma_call_back_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:269
dma_call_back_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:268
dma0_cbk
dma_call_back_t dma0_cbk[12]
Definition: ald_dma.c:77
ald_dma_clear_flag_status
void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel)
Clear the specified channel pending flag.
Definition: ald_dma.c:952
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
DMA_ERR
#define DMA_ERR
Definition: ald_dma.h:40
DMA_CH_COUNT
#define DMA_CH_COUNT
Definition: ald_dma.h:39


ALD User Manual: DMA Public Macros

Macros
DMA Public Macros
EASTSOFT ES32F3xx ALD » DMA
Collaboration diagram for DMA Public Macros:

Macros

#define | DMA_CH_COUNT 12U
#define | DMA_ERR 31U

Detailed Description

Macro Definition Documentation

◆ DMA_CH_COUNT

#define DMA_CH_COUNT 12U

Definition at line 39 of file ald_dma.h.

◆ DMA_ERR

#define DMA_ERR 31U

Definition at line 40 of file ald_dma.h.


ALD User Manual: DMA Public Types

Data Structures | Enumerations
DMA Public Types
EASTSOFT ES32F3xx ALD » DMA
Collaboration diagram for DMA Public Types:

Data Structures

union | dma_ctrl_t
DMA Descriptor control type. More...
struct | dma_descriptor_t
Channel control data structure. More...
struct | dma_call_back_t
Callback function pointer and param. More...
struct | dma_config_t
DMA channal configure structure. More...
struct | dma_handle_t
DMA handle structure definition. More...

Enumerations

enum dma_msel_t {
DMA_MSEL_NONE = 0x0U, DMA_MSEL_GPIO = 0x1U, DMA_MSEL_CRYPT = 0x2U, DMA_MSEL_DAC0 = 0x4U,
DMA_MSEL_ADC0 = 0x6U, DMA_MSEL_CRC = 0x7U, DMA_MSEL_UART0 = 0x8U, DMA_MSEL_UART1 = 0x9U,
DMA_MSEL_UART2 = 0xAU, DMA_MSEL_UART3 = 0xBU, DMA_MSEL_UART4 = 0xCU, DMA_MSEL_UART5 = 0xDU,
DMA_MSEL_SPI0 = 0xEU, DMA_MSEL_SPI1 = 0xFU, DMA_MSEL_I2C0 = 0x10U, DMA_MSEL_I2C1 = 0x11U,
DMA_MSEL_TIMER0 = 0x12U, DMA_MSEL_TIMER1 = 0x13U, DMA_MSEL_TIMER2 = 0x14U, DMA_MSEL_TIMER3 = 0x15U,
DMA_MSEL_LPUART0 = 0x18U, DMA_MSEL_SPI2 = 0x1AU, DMA_MSEL_TIMER4 = 0x1BU, DMA_MSEL_TIMER5 = 0x1CU,
DMA_MSEL_TIMER6 = 0x1DU, DMA_MSEL_TIMER7 = 0x1EU, DMA_MSEL_ADC1 = 0x1FU, DMA_MSEL_PIS = 0x20U,
DMA_MSEL_TRNG = 0x21U, DMA_MSEL_QSPI = 0x22U, DMA_MSEL_USB = 0x23U
}
Input source to DMA channel. More...
enum dma_msigsel_t {
DMA_MSIGSEL_NONE = 0x0U, DMA_MSIGSEL_EXTI_0 = 0x0U, DMA_MSIGSEL_EXTI_1 = 0x1U, DMA_MSIGSEL_EXTI_2 = 0x2U,
DMA_MSIGSEL_EXTI_3 = 0x3U, DMA_MSIGSEL_EXTI_4 = 0x4U, DMA_MSIGSEL_EXTI_5 = 0x5U, DMA_MSIGSEL_EXTI_6 = 0x6U,
DMA_MSIGSEL_EXTI_7 = 0x7U, DMA_MSIGSEL_EXTI_8 = 0x8U, DMA_MSIGSEL_EXTI_9 = 0x9U, DMA_MSIGSEL_EXTI_10 = 0xAU,
DMA_MSIGSEL_EXTI_11 = 0xBU, DMA_MSIGSEL_EXTI_12 = 0xCU, DMA_MSIGSEL_EXTI_13 = 0xDU, DMA_MSIGSEL_EXTI_14 = 0xEU,
DMA_MSIGSEL_EXTI_15 = 0xFU, DMA_MSIGSEL_CRYPT_WRITE = 0x0U, DMA_MSIGSEL_CRYPT_READ = 0x1U, DMA_MSIGSEL_DAC0_CH0 = 0x0U,
DMA_MSIGSEL_DAC0_CH1 = 0x1U, DMA_MSIGSEL_ADC = 0x0U, DMA_MSIGSEL_UART_TXEMPTY = 0x0U, DMA_MSIGSEL_UART_RNR = 0x1U,
DMA_MSIGSEL_UART45_RNR = 0x0U, DMA_MSIGSEL_UART45_TXEMPTY = 0x1U, DMA_MSIGSEL_SPI_RNR = 0x0U, DMA_MSIGSEL_SPI_TXEMPTY = 0x1U,
DMA_MSIGSEL_I2C_RNR = 0x0U, DMA_MSIGSEL_I2C_TXEMPTY = 0x1U, DMA_MSIGSEL_TIMER_CH1 = 0x0U, DMA_MSIGSEL_TIMER_CH2 = 0x1U,
DMA_MSIGSEL_TIMER_CH3 = 0x2U, DMA_MSIGSEL_TIMER_CH4 = 0x3U, DMA_MSIGSEL_TIMER_TRI = 0x4U, DMA_MSIGSEL_TIMER_COMP = 0x5U,
DMA_MSIGSEL_TIMER_UPDATE = 0x6U, DMA_MSIGSEL_LPUART_RNR = 0x0U, DMA_MSIGSEL_LPUART_TXEMPTY = 0x1U, DMA_MSIGSEL_PIS_CH0 = 0x0U,
DMA_MSIGSEL_PIS_CH1 = 0x1U, DMA_MSIGSEL_PIS_CH2 = 0x2U, DMA_MSIGSEL_PIS_CH3 = 0x3U, DMA_MSIGSEL_PIS_CH4 = 0x4U,
DMA_MSIGSEL_PIS_CH5 = 0x5U, DMA_MSIGSEL_PIS_CH6 = 0x6U, DMA_MSIGSEL_PIS_CH7 = 0x7U, DMA_MSIGSEL_PIS_CH8 = 0x8U,
DMA_MSIGSEL_PIS_CH9 = 0x9U, DMA_MSIGSEL_PIS_CH10 = 0xAU, DMA_MSIGSEL_PIS_CH11 = 0xBU, DMA_MSIGSEL_PIS_CH12 = 0xCU,
DMA_MSIGSEL_PIS_CH13 = 0xDU, DMA_MSIGSEL_PIS_CH14 = 0xEU, DMA_MSIGSEL_PIS_CH15 = 0xFU, DMA_MSIGSEL_QSPI_WRITE = 0x0U,
DMA_MSIGSEL_QSPI_READ = 0x1U, DMA_MSIGSEL_EP_TX1 = 0x0U, DMA_MSIGSEL_EP_TX2 = 0x1U, DMA_MSIGSEL_EP_TX3 = 0x2U,
DMA_MSIGSEL_EP_TX4 = 0x3U, DMA_MSIGSEL_EP_TX5 = 0x4U, DMA_MSIGSEL_EP_RX1 = 0x8U, DMA_MSIGSEL_EP_RX2 = 0x9U,
DMA_MSIGSEL_EP_RX3 = 0xAU, DMA_MSIGSEL_EP_RX4 = 0xBU, DMA_MSIGSEL_EP_RX5 = 0xCU
}
Input signal to DMA channel. More...
enum | dma_data_inc_t { DMA_DATA_INC_BYTE = 0x0U, DMA_DATA_INC_HALFWORD = 0x1U, DMA_DATA_INC_WORD = 0x2U, DMA_DATA_INC_NONE = 0x3U }
data increment More...
enum | dma_data_size_t { DMA_DATA_SIZE_BYTE = 0x0U, DMA_DATA_SIZE_HALFWORD = 0x1U, DMA_DATA_SIZE_WORD = 0x2U }
Data size. More...
enum dma_cycle_ctrl_t {
DMA_CYCLE_CTRL_NONE = 0x0U, DMA_CYCLE_CTRL_BASIC = 0x1U, DMA_CYCLE_CTRL_AUTO = 0x2U, DMA_CYCLE_CTRL_PINGPONG = 0x3U,
DMA_CYCLE_CTRL_MEM_SG_PRIMARY = 0x4U, DMA_CYCLE_CTRL_MEM_SG_ALTERNATE = 0x5U, DMA_CYCLE_CTRL_PER_SG_PRIMARY = 0x6U, DMA_CYCLE_CTRL_PER_SG_ALTERNATE = 0x7U
}
The operating mode of the DMA cycle. More...
enum dma_arbiter_config_t {
DMA_R_POWER_1 = 0x0U, DMA_R_POWER_2 = 0x1U, DMA_R_POWER_4 = 0x2U, DMA_R_POWER_8 = 0x3U,
DMA_R_POWER_16 = 0x4U, DMA_R_POWER_32 = 0x5U, DMA_R_POWER_64 = 0x6U, DMA_R_POWER_128 = 0x7U,
DMA_R_POWER_256 = 0x8U, DMA_R_POWER_512 = 0x9U, DMA_R_POWER_1024 = 0xAU
}
Control how many DMA transfers can occur before the controller re-arbitrates. More...
enum | dma_descrp_cplt_t { DMA_DESCP_CPLT_PRI = 0x0U, DMA_DESCP_CPLT_ALT = 0x1U, DMA_DESCP_CPLT_ALL = 0x2U }
Descriptor complete state. More...

Detailed Description

Enumeration Type Documentation

◆ dma_arbiter_config_t

enum dma_arbiter_config_t

Control how many DMA transfers can occur before the controller re-arbitrates.

Enumerator
DMA_R_POWER_1 | Arbitrates after each DMA transfer
DMA_R_POWER_2 | Arbitrates after 2 DMA transfer
DMA_R_POWER_4 | Arbitrates after 4 DMA transfer
DMA_R_POWER_8 | Arbitrates after 8 DMA transfer
DMA_R_POWER_16 | Arbitrates after 16 DMA transfer
DMA_R_POWER_32 | Arbitrates after 32 DMA transfer
DMA_R_POWER_64 | Arbitrates after 64 DMA transfer
DMA_R_POWER_128 | Arbitrates after 128 DMA transfer
DMA_R_POWER_256 | Arbitrates after 256 DMA transfer
DMA_R_POWER_512 | Arbitrates after 512 DMA transfer
DMA_R_POWER_1024 | Arbitrates after 1024 DMA transfer

Definition at line 250 of file ald_dma.h.

250 {
251 DMA_R_POWER_1 = 0x0U,
252 DMA_R_POWER_2 = 0x1U,
253 DMA_R_POWER_4 = 0x2U,
254 DMA_R_POWER_8 = 0x3U,
255 DMA_R_POWER_16 = 0x4U,
256 DMA_R_POWER_32 = 0x5U,
257 DMA_R_POWER_64 = 0x6U,
258 DMA_R_POWER_128 = 0x7U,
259 DMA_R_POWER_256 = 0x8U,
260 DMA_R_POWER_512 = 0x9U,
261 DMA_R_POWER_1024 = 0xAU,
262 } dma_arbiter_config_t;
DMA_R_POWER_4
Definition: ald_dma.h:253
DMA_R_POWER_128
Definition: ald_dma.h:258
DMA_R_POWER_256
Definition: ald_dma.h:259
DMA_R_POWER_512
Definition: ald_dma.h:260
DMA_R_POWER_64
Definition: ald_dma.h:257
DMA_R_POWER_1024
Definition: ald_dma.h:261
DMA_R_POWER_16
Definition: ald_dma.h:255
dma_arbiter_config_t
dma_arbiter_config_t
Control how many DMA transfers can occur before the controller re-arbitrates.
Definition: ald_dma.h:250
DMA_R_POWER_2
Definition: ald_dma.h:252
DMA_R_POWER_8
Definition: ald_dma.h:254
DMA_R_POWER_1
Definition: ald_dma.h:251
DMA_R_POWER_32
Definition: ald_dma.h:256

◆ dma_cycle_ctrl_t

enum dma_cycle_ctrl_t

The operating mode of the DMA cycle.

Enumerator
DMA_CYCLE_CTRL_NONE | Stop
DMA_CYCLE_CTRL_BASIC | Basic
DMA_CYCLE_CTRL_AUTO | Auto-request
DMA_CYCLE_CTRL_PINGPONG | Ping-pong
DMA_CYCLE_CTRL_MEM_SG_PRIMARY | Memory scatter-gather using the primary structure
DMA_CYCLE_CTRL_MEM_SG_ALTERNATE | Memory scatter-gather using the alternate structure
DMA_CYCLE_CTRL_PER_SG_PRIMARY | Peripheral scatter-gather using the primary structure
DMA_CYCLE_CTRL_PER_SG_ALTERNATE | Peripheral scatter-gather using the alternate structure

Definition at line 235 of file ald_dma.h.

235 {
236 DMA_CYCLE_CTRL_NONE = 0x0U,
237 DMA_CYCLE_CTRL_BASIC = 0x1U,
238 DMA_CYCLE_CTRL_AUTO = 0x2U,
239 DMA_CYCLE_CTRL_PINGPONG = 0x3U,
240 DMA_CYCLE_CTRL_MEM_SG_PRIMARY = 0x4U,
241 DMA_CYCLE_CTRL_MEM_SG_ALTERNATE = 0x5U,
242 DMA_CYCLE_CTRL_PER_SG_PRIMARY = 0x6U,
243 DMA_CYCLE_CTRL_PER_SG_ALTERNATE = 0x7U,
244 } dma_cycle_ctrl_t;
DMA_CYCLE_CTRL_MEM_SG_PRIMARY
Definition: ald_dma.h:240
DMA_CYCLE_CTRL_PER_SG_PRIMARY
Definition: ald_dma.h:242
DMA_CYCLE_CTRL_BASIC
Definition: ald_dma.h:237
dma_cycle_ctrl_t
dma_cycle_ctrl_t
The operating mode of the DMA cycle.
Definition: ald_dma.h:235
DMA_CYCLE_CTRL_PER_SG_ALTERNATE
Definition: ald_dma.h:243
DMA_CYCLE_CTRL_PINGPONG
Definition: ald_dma.h:239
DMA_CYCLE_CTRL_NONE
Definition: ald_dma.h:236
DMA_CYCLE_CTRL_AUTO
Definition: ald_dma.h:238
DMA_CYCLE_CTRL_MEM_SG_ALTERNATE
Definition: ald_dma.h:241

◆ dma_data_inc_t

enum dma_data_inc_t

data increment

Enumerator
DMA_DATA_INC_BYTE | Address increment by byte
DMA_DATA_INC_HALFWORD | Address increment by halfword
DMA_DATA_INC_WORD | Address increment by word
DMA_DATA_INC_NONE | No increment

Definition at line 216 of file ald_dma.h.

216 {
217 DMA_DATA_INC_BYTE = 0x0U,
218 DMA_DATA_INC_HALFWORD = 0x1U,
219 DMA_DATA_INC_WORD = 0x2U,
220 DMA_DATA_INC_NONE = 0x3U,
221 } dma_data_inc_t;
dma_data_inc_t
dma_data_inc_t
data increment
Definition: ald_dma.h:216
DMA_DATA_INC_WORD
Definition: ald_dma.h:219
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
DMA_DATA_INC_BYTE
Definition: ald_dma.h:217
DMA_DATA_INC_NONE
Definition: ald_dma.h:220

◆ dma_data_size_t

enum dma_data_size_t

Data size.

Enumerator
DMA_DATA_SIZE_BYTE | Byte
DMA_DATA_SIZE_HALFWORD | Halfword
DMA_DATA_SIZE_WORD | Word

Definition at line 226 of file ald_dma.h.

226 {
227 DMA_DATA_SIZE_BYTE = 0x0U,
228 DMA_DATA_SIZE_HALFWORD = 0x1U,
229 DMA_DATA_SIZE_WORD = 0x2U,
230 } dma_data_size_t;
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
dma_data_size_t
dma_data_size_t
Data size.
Definition: ald_dma.h:226
DMA_DATA_SIZE_WORD
Definition: ald_dma.h:229
DMA_DATA_SIZE_BYTE
Definition: ald_dma.h:227

◆ dma_descrp_cplt_t

enum dma_descrp_cplt_t

Descriptor complete state.

Enumerator
DMA_DESCP_CPLT_PRI | Primary descriptor has been completed
DMA_DESCP_CPLT_ALT | Alternate descriptor has been completed
DMA_DESCP_CPLT_ALL | Both primary and alternate descriptors have been completed

Definition at line 309 of file ald_dma.h.

309 {
310 DMA_DESCP_CPLT_PRI = 0x0U,
311 DMA_DESCP_CPLT_ALT = 0x1U,
312 DMA_DESCP_CPLT_ALL = 0x2U,
313 } dma_descrp_cplt_t;
DMA_DESCP_CPLT_PRI
Definition: ald_dma.h:310
DMA_DESCP_CPLT_ALL
Definition: ald_dma.h:312
DMA_DESCP_CPLT_ALT
Definition: ald_dma.h:311
dma_descrp_cplt_t
dma_descrp_cplt_t
Descriptor complete state.
Definition: ald_dma.h:309

◆ dma_msel_t

enum dma_msel_t

Input source to DMA channel.

  In this module, for the convenience of code maintenance,
  TIMERx is used to indicate the sequence of the timer peripheral.
  Different product series TIMERx represent different meanings:
  1. For ES32F36xx series:
  TIMER0 ----> AD16C4T0
  TIMER1 ----> AD16C4T1
  TIMER2 ----> GP32C4T0
  TIMER3 ----> GP32C4T1
  TIMER4 ----> BS16T0
  TIMER5 ----> BS16T1
  TIMER6 ----> GP16C4T0
  TIMER7 ----> GP16C4T1

  2. For ES32F393x/ES32F336x/ES32F392x series:
  TIMER0 ----> GP16C4T0
  TIMER1 ----> GP16C4T1
  TIMER2 ----> GP32C4T0
  TIMER3 ----> GP32C4T1
  TIMER4 ----> BS16T0
  TIMER5 ----> BS16T1
  TIMER6 ----> GP16C4T2
  TIMER7 ----> GP16C4T3

Enumerator
DMA_MSEL_NONE | NONE
DMA_MSEL_GPIO | GPIO
DMA_MSEL_CRYPT | CRYPT
DMA_MSEL_DAC0 | DAC0
DMA_MSEL_ADC0 | ADC0
DMA_MSEL_CRC | CRC
DMA_MSEL_UART0 | UART0
DMA_MSEL_UART1 | UART1
DMA_MSEL_UART2 | UART2
DMA_MSEL_UART3 | UART3
DMA_MSEL_UART4 | UART4
DMA_MSEL_UART5 | UART5
DMA_MSEL_SPI0 | SPI0
DMA_MSEL_SPI1 | SPI1
DMA_MSEL_I2C0 | I2C0
DMA_MSEL_I2C1 | I2C1
DMA_MSEL_TIMER0 | TIMER0
DMA_MSEL_TIMER1 | TIMER1
DMA_MSEL_TIMER2 | TIMER2
DMA_MSEL_TIMER3 | TIMER3
DMA_MSEL_LPUART0 | LPUART0
DMA_MSEL_SPI2 | SPI2
DMA_MSEL_TIMER4 | TIMER4
DMA_MSEL_TIMER5 | TIMER5
DMA_MSEL_TIMER6 | TIMER6
DMA_MSEL_TIMER7 | TIMER7
DMA_MSEL_ADC1 | ADC1
DMA_MSEL_PIS | PIS
DMA_MSEL_TRNG | TRNG
DMA_MSEL_QSPI | QSPI
DMA_MSEL_USB | USB

Definition at line 77 of file ald_dma.h.

77 {
78 DMA_MSEL_NONE = 0x0U,
79 DMA_MSEL_GPIO = 0x1U,
80 DMA_MSEL_CRYPT = 0x2U,
81 DMA_MSEL_DAC0 = 0x4U,
82 DMA_MSEL_ADC0 = 0x6U,
83 DMA_MSEL_CRC = 0x7U,
84 DMA_MSEL_UART0 = 0x8U,
85 DMA_MSEL_UART1 = 0x9U,
86 DMA_MSEL_UART2 = 0xAU,
87 DMA_MSEL_UART3 = 0xBU,
88 DMA_MSEL_UART4 = 0xCU,
89 DMA_MSEL_UART5 = 0xDU,
90 DMA_MSEL_SPI0 = 0xEU,
91 DMA_MSEL_SPI1 = 0xFU,
92 DMA_MSEL_I2C0 = 0x10U,
93 DMA_MSEL_I2C1 = 0x11U,
94 DMA_MSEL_TIMER0 = 0x12U,
95 DMA_MSEL_TIMER1 = 0x13U,
96 DMA_MSEL_TIMER2 = 0x14U,
97 DMA_MSEL_TIMER3 = 0x15U,
98 DMA_MSEL_LPUART0 = 0x18U,
99 DMA_MSEL_SPI2 = 0x1AU,
100 DMA_MSEL_TIMER4 = 0x1BU,
101 DMA_MSEL_TIMER5 = 0x1CU,
102 DMA_MSEL_TIMER6 = 0x1DU,
103 DMA_MSEL_TIMER7 = 0x1EU,
104 DMA_MSEL_ADC1 = 0x1FU,
105 DMA_MSEL_PIS = 0x20U,
106 DMA_MSEL_TRNG = 0x21U,
107 DMA_MSEL_QSPI = 0x22U,
108 DMA_MSEL_USB = 0x23U,
109 } dma_msel_t;
DMA_MSEL_SPI1
Definition: ald_dma.h:91
DMA_MSEL_TIMER2
Definition: ald_dma.h:96
DMA_MSEL_UART4
Definition: ald_dma.h:88
DMA_MSEL_USB
Definition: ald_dma.h:108
DMA_MSEL_UART5
Definition: ald_dma.h:89
DMA_MSEL_NONE
Definition: ald_dma.h:78
DMA_MSEL_TIMER4
Definition: ald_dma.h:100
DMA_MSEL_SPI2
Definition: ald_dma.h:99
DMA_MSEL_UART1
Definition: ald_dma.h:85
DMA_MSEL_UART0
Definition: ald_dma.h:84
DMA_MSEL_QSPI
Definition: ald_dma.h:107
DMA_MSEL_PIS
Definition: ald_dma.h:105
DMA_MSEL_TIMER6
Definition: ald_dma.h:102
DMA_MSEL_LPUART0
Definition: ald_dma.h:98
DMA_MSEL_TIMER7
Definition: ald_dma.h:103
DMA_MSEL_I2C0
Definition: ald_dma.h:92
DMA_MSEL_DAC0
Definition: ald_dma.h:81
DMA_MSEL_ADC1
Definition: ald_dma.h:104
DMA_MSEL_TRNG
Definition: ald_dma.h:106
DMA_MSEL_TIMER0
Definition: ald_dma.h:94
DMA_MSEL_TIMER3
Definition: ald_dma.h:97
DMA_MSEL_UART3
Definition: ald_dma.h:87
DMA_MSEL_GPIO
Definition: ald_dma.h:79
DMA_MSEL_TIMER1
Definition: ald_dma.h:95
DMA_MSEL_CRYPT
Definition: ald_dma.h:80
DMA_MSEL_ADC0
Definition: ald_dma.h:82
DMA_MSEL_CRC
Definition: ald_dma.h:83
DMA_MSEL_I2C1
Definition: ald_dma.h:93
dma_msel_t
dma_msel_t
Input source to DMA channel.
Definition: ald_dma.h:77
DMA_MSEL_TIMER5
Definition: ald_dma.h:101
DMA_MSEL_SPI0
Definition: ald_dma.h:90
DMA_MSEL_UART2
Definition: ald_dma.h:86

◆ dma_msigsel_t

enum dma_msigsel_t

Input signal to DMA channel.

Enumerator
DMA_MSIGSEL_NONE | NONE
DMA_MSIGSEL_EXTI_0 | External interrupt 0
DMA_MSIGSEL_EXTI_1 | External interrupt 1
DMA_MSIGSEL_EXTI_2 | External interrupt 2
DMA_MSIGSEL_EXTI_3 | External interrupt 3
DMA_MSIGSEL_EXTI_4 | External interrupt 4
DMA_MSIGSEL_EXTI_5 | External interrupt 5
DMA_MSIGSEL_EXTI_6 | External interrupt 6
DMA_MSIGSEL_EXTI_7 | External interrupt 7
DMA_MSIGSEL_EXTI_8 | External interrupt 8
DMA_MSIGSEL_EXTI_9 | External interrupt 9
DMA_MSIGSEL_EXTI_10 | External interrupt 10
DMA_MSIGSEL_EXTI_11 | External interrupt 11
DMA_MSIGSEL_EXTI_12 | External interrupt 12
DMA_MSIGSEL_EXTI_13 | External interrupt 13
DMA_MSIGSEL_EXTI_14 | External interrupt 14
DMA_MSIGSEL_EXTI_15 | External interrupt 15
DMA_MSIGSEL_CRYPT_WRITE | CRYPT write mode
DMA_MSIGSEL_CRYPT_READ | CRYPT read mode
DMA_MSIGSEL_DAC0_CH0 | DAC0 channel 0 complete
DMA_MSIGSEL_DAC0_CH1 | DAC0 channel 1 complete
DMA_MSIGSEL_ADC | ADC mode
DMA_MSIGSEL_UART_TXEMPTY | UART0/UART1/UART2/UART3 transmit
DMA_MSIGSEL_UART_RNR | UART0/UART1/UART2/UART3 receive
DMA_MSIGSEL_UART45_RNR | UART4/UART5 reveive
DMA_MSIGSEL_UART45_TXEMPTY | UART4/UART5 transmit
DMA_MSIGSEL_SPI_RNR | SPI receive
DMA_MSIGSEL_SPI_TXEMPTY | SPI transmit
DMA_MSIGSEL_I2C_RNR | I2C receive
DMA_MSIGSEL_I2C_TXEMPTY | I2C transmit
DMA_MSIGSEL_TIMER_CH1 | TIM channal 1
DMA_MSIGSEL_TIMER_CH2 | TIM channal 2
DMA_MSIGSEL_TIMER_CH3 | TIM channal 3
DMA_MSIGSEL_TIMER_CH4 | TIM channal 4
DMA_MSIGSEL_TIMER_TRI | TIM trigger
DMA_MSIGSEL_TIMER_COMP | TIM compare
DMA_MSIGSEL_TIMER_UPDATE | TIM update
DMA_MSIGSEL_LPUART_RNR | LPUART receive
DMA_MSIGSEL_LPUART_TXEMPTY | LPUART transmit
DMA_MSIGSEL_PIS_CH0 | PIS channal 0
DMA_MSIGSEL_PIS_CH1 | PIS channal 1
DMA_MSIGSEL_PIS_CH2 | PIS channal 2
DMA_MSIGSEL_PIS_CH3 | PIS channal 3
DMA_MSIGSEL_PIS_CH4 | PIS channal 4
DMA_MSIGSEL_PIS_CH5 | PIS channal 5
DMA_MSIGSEL_PIS_CH6 | PIS channal 6
DMA_MSIGSEL_PIS_CH7 | PIS channal 7
DMA_MSIGSEL_PIS_CH8 | PIS channal 8
DMA_MSIGSEL_PIS_CH9 | PIS channal 9
DMA_MSIGSEL_PIS_CH10 | PIS channal 10
DMA_MSIGSEL_PIS_CH11 | PIS channal 11
DMA_MSIGSEL_PIS_CH12 | PIS channal 12
DMA_MSIGSEL_PIS_CH13 | PIS channal 13
DMA_MSIGSEL_PIS_CH14 | PIS channal 14
DMA_MSIGSEL_PIS_CH15 | PIS channal 15
DMA_MSIGSEL_QSPI_WRITE | QSPI Write
DMA_MSIGSEL_QSPI_READ | QSPI Read
DMA_MSIGSEL_EP_TX1 | USB TX Endport 0
DMA_MSIGSEL_EP_TX2 | USB TX Endport 1
DMA_MSIGSEL_EP_TX3 | USB TX Endport 2
DMA_MSIGSEL_EP_TX4 | USB TX Endport 3
DMA_MSIGSEL_EP_TX5 | USB TX Endport 4
DMA_MSIGSEL_EP_RX1 | USB RX Endport 0
DMA_MSIGSEL_EP_RX2 | USB RX Endport 1
DMA_MSIGSEL_EP_RX3 | USB RX Endport 2
DMA_MSIGSEL_EP_RX4 | USB RX Endport 3
DMA_MSIGSEL_EP_RX5 | USB RX Endport 4

Definition at line 114 of file ald_dma.h.

114 {
115 DMA_MSIGSEL_NONE = 0x0U,
116 DMA_MSIGSEL_EXTI_0 = 0x0U,
117 DMA_MSIGSEL_EXTI_1 = 0x1U,
118 DMA_MSIGSEL_EXTI_2 = 0x2U,
119 DMA_MSIGSEL_EXTI_3 = 0x3U,
120 DMA_MSIGSEL_EXTI_4 = 0x4U,
121 DMA_MSIGSEL_EXTI_5 = 0x5U,
122 DMA_MSIGSEL_EXTI_6 = 0x6U,
123 DMA_MSIGSEL_EXTI_7 = 0x7U,
124 DMA_MSIGSEL_EXTI_8 = 0x8U,
125 DMA_MSIGSEL_EXTI_9 = 0x9U,
126 DMA_MSIGSEL_EXTI_10 = 0xAU,
127 DMA_MSIGSEL_EXTI_11 = 0xBU,
128 DMA_MSIGSEL_EXTI_12 = 0xCU,
129 DMA_MSIGSEL_EXTI_13 = 0xDU,
130 DMA_MSIGSEL_EXTI_14 = 0xEU,
131 DMA_MSIGSEL_EXTI_15 = 0xFU,
132 DMA_MSIGSEL_CRYPT_WRITE = 0x0U,
133 DMA_MSIGSEL_CRYPT_READ = 0x1U,
134 DMA_MSIGSEL_DAC0_CH0 = 0x0U,
135 DMA_MSIGSEL_DAC0_CH1 = 0x1U,
136 DMA_MSIGSEL_ADC = 0x0U,
137 DMA_MSIGSEL_UART_TXEMPTY = 0x0U,
138 DMA_MSIGSEL_UART_RNR = 0x1U,
139 DMA_MSIGSEL_UART45_RNR = 0x0U,
140 DMA_MSIGSEL_UART45_TXEMPTY = 0x1U,
141 DMA_MSIGSEL_SPI_RNR = 0x0U,
142 DMA_MSIGSEL_SPI_TXEMPTY = 0x1U,
143 DMA_MSIGSEL_I2C_RNR = 0x0U,
144 DMA_MSIGSEL_I2C_TXEMPTY = 0x1U,
145 DMA_MSIGSEL_TIMER_CH1 = 0x0U,
146 DMA_MSIGSEL_TIMER_CH2 = 0x1U,
147 DMA_MSIGSEL_TIMER_CH3 = 0x2U,
148 DMA_MSIGSEL_TIMER_CH4 = 0x3U,
149 DMA_MSIGSEL_TIMER_TRI = 0x4U,
150 DMA_MSIGSEL_TIMER_COMP = 0x5U,
151 DMA_MSIGSEL_TIMER_UPDATE = 0x6U,
152 DMA_MSIGSEL_LPUART_RNR = 0x0U,
153 DMA_MSIGSEL_LPUART_TXEMPTY = 0x1U,
154 DMA_MSIGSEL_PIS_CH0 = 0x0U,
155 DMA_MSIGSEL_PIS_CH1 = 0x1U,
156 DMA_MSIGSEL_PIS_CH2 = 0x2U,
157 DMA_MSIGSEL_PIS_CH3 = 0x3U,
158 DMA_MSIGSEL_PIS_CH4 = 0x4U,
159 DMA_MSIGSEL_PIS_CH5 = 0x5U,
160 DMA_MSIGSEL_PIS_CH6 = 0x6U,
161 DMA_MSIGSEL_PIS_CH7 = 0x7U,
162 DMA_MSIGSEL_PIS_CH8 = 0x8U,
163 DMA_MSIGSEL_PIS_CH9 = 0x9U,
164 DMA_MSIGSEL_PIS_CH10 = 0xAU,
165 DMA_MSIGSEL_PIS_CH11 = 0xBU,
166 DMA_MSIGSEL_PIS_CH12 = 0xCU,
167 DMA_MSIGSEL_PIS_CH13 = 0xDU,
168 DMA_MSIGSEL_PIS_CH14 = 0xEU,
169 DMA_MSIGSEL_PIS_CH15 = 0xFU,
170 DMA_MSIGSEL_QSPI_WRITE = 0x0U,
171 DMA_MSIGSEL_QSPI_READ = 0x1U,
172 DMA_MSIGSEL_EP_TX1 = 0x0U,
173 DMA_MSIGSEL_EP_TX2 = 0x1U,
174 DMA_MSIGSEL_EP_TX3 = 0x2U,
175 DMA_MSIGSEL_EP_TX4 = 0x3U,
176 DMA_MSIGSEL_EP_TX5 = 0x4U,
177 DMA_MSIGSEL_EP_RX1 = 0x8U,
178 DMA_MSIGSEL_EP_RX2 = 0x9U,
179 DMA_MSIGSEL_EP_RX3 = 0xAU,
180 DMA_MSIGSEL_EP_RX4 = 0xBU,
181 DMA_MSIGSEL_EP_RX5 = 0xCU,
182 } dma_msigsel_t;
DMA_MSIGSEL_TIMER_CH1
Definition: ald_dma.h:145
DMA_MSIGSEL_PIS_CH11
Definition: ald_dma.h:165
DMA_MSIGSEL_EP_TX1
Definition: ald_dma.h:172
DMA_MSIGSEL_EP_TX2
Definition: ald_dma.h:173
DMA_MSIGSEL_EP_RX5
Definition: ald_dma.h:181
DMA_MSIGSEL_EXTI_5
Definition: ald_dma.h:121
DMA_MSIGSEL_EP_TX3
Definition: ald_dma.h:174
DMA_MSIGSEL_TIMER_COMP
Definition: ald_dma.h:150
DMA_MSIGSEL_EXTI_9
Definition: ald_dma.h:125
DMA_MSIGSEL_PIS_CH8
Definition: ald_dma.h:162
DMA_MSIGSEL_TIMER_UPDATE
Definition: ald_dma.h:151
DMA_MSIGSEL_EP_TX4
Definition: ald_dma.h:175
DMA_MSIGSEL_I2C_TXEMPTY
Definition: ald_dma.h:144
DMA_MSIGSEL_PIS_CH4
Definition: ald_dma.h:158
DMA_MSIGSEL_EXTI_1
Definition: ald_dma.h:117
DMA_MSIGSEL_UART45_RNR
Definition: ald_dma.h:139
DMA_MSIGSEL_I2C_RNR
Definition: ald_dma.h:143
DMA_MSIGSEL_EXTI_11
Definition: ald_dma.h:127
DMA_MSIGSEL_EP_RX2
Definition: ald_dma.h:178
DMA_MSIGSEL_PIS_CH3
Definition: ald_dma.h:157
DMA_MSIGSEL_UART_TXEMPTY
Definition: ald_dma.h:137
DMA_MSIGSEL_EP_RX3
Definition: ald_dma.h:179
DMA_MSIGSEL_EXTI_10
Definition: ald_dma.h:126
DMA_MSIGSEL_DAC0_CH0
Definition: ald_dma.h:134
DMA_MSIGSEL_EXTI_13
Definition: ald_dma.h:129
dma_msigsel_t
dma_msigsel_t
Input signal to DMA channel.
Definition: ald_dma.h:114
DMA_MSIGSEL_TIMER_CH4
Definition: ald_dma.h:148
DMA_MSIGSEL_EXTI_12
Definition: ald_dma.h:128
DMA_MSIGSEL_PIS_CH13
Definition: ald_dma.h:167
DMA_MSIGSEL_PIS_CH2
Definition: ald_dma.h:156
DMA_MSIGSEL_PIS_CH6
Definition: ald_dma.h:160
DMA_MSIGSEL_PIS_CH1
Definition: ald_dma.h:155
DMA_MSIGSEL_PIS_CH0
Definition: ald_dma.h:154
DMA_MSIGSEL_UART_RNR
Definition: ald_dma.h:138
DMA_MSIGSEL_TIMER_CH2
Definition: ald_dma.h:146
DMA_MSIGSEL_PIS_CH7
Definition: ald_dma.h:161
DMA_MSIGSEL_EP_RX1
Definition: ald_dma.h:177
DMA_MSIGSEL_EXTI_6
Definition: ald_dma.h:122
DMA_MSIGSEL_EXTI_15
Definition: ald_dma.h:131
DMA_MSIGSEL_PIS_CH10
Definition: ald_dma.h:164
DMA_MSIGSEL_UART45_TXEMPTY
Definition: ald_dma.h:140
DMA_MSIGSEL_EXTI_0
Definition: ald_dma.h:116
DMA_MSIGSEL_EXTI_3
Definition: ald_dma.h:119
DMA_MSIGSEL_CRYPT_WRITE
Definition: ald_dma.h:132
DMA_MSIGSEL_SPI_RNR
Definition: ald_dma.h:141
DMA_MSIGSEL_EXTI_8
Definition: ald_dma.h:124
DMA_MSIGSEL_TIMER_CH3
Definition: ald_dma.h:147
DMA_MSIGSEL_EXTI_4
Definition: ald_dma.h:120
DMA_MSIGSEL_QSPI_READ
Definition: ald_dma.h:171
DMA_MSIGSEL_PIS_CH9
Definition: ald_dma.h:163
DMA_MSIGSEL_EXTI_14
Definition: ald_dma.h:130
DMA_MSIGSEL_ADC
Definition: ald_dma.h:136
DMA_MSIGSEL_NONE
Definition: ald_dma.h:115
DMA_MSIGSEL_SPI_TXEMPTY
Definition: ald_dma.h:142
DMA_MSIGSEL_EP_RX4
Definition: ald_dma.h:180
DMA_MSIGSEL_PIS_CH5
Definition: ald_dma.h:159
DMA_MSIGSEL_PIS_CH14
Definition: ald_dma.h:168
DMA_MSIGSEL_DAC0_CH1
Definition: ald_dma.h:135
DMA_MSIGSEL_TIMER_TRI
Definition: ald_dma.h:149
DMA_MSIGSEL_PIS_CH15
Definition: ald_dma.h:169
DMA_MSIGSEL_EXTI_2
Definition: ald_dma.h:118
DMA_MSIGSEL_EP_TX5
Definition: ald_dma.h:176
DMA_MSIGSEL_CRYPT_READ
Definition: ald_dma.h:133
DMA_MSIGSEL_LPUART_RNR
Definition: ald_dma.h:152
DMA_MSIGSEL_QSPI_WRITE
Definition: ald_dma.h:170
DMA_MSIGSEL_EXTI_7
Definition: ald_dma.h:123
DMA_MSIGSEL_PIS_CH12
Definition: ald_dma.h:166
DMA_MSIGSEL_LPUART_TXEMPTY
Definition: ald_dma.h:153


ALD User Manual: dma_ctrl_t Union Reference

Data Fields
dma_ctrl_t Union Reference
EASTSOFT ES32F3xx ALD » DMA » DMA Public Types

DMA Descriptor control type. More...

#include <ald_dma.h>

Data Fields

struct {
uint32_t cycle_ctrl:3
uint32_t next_useburst:1
uint32_t n_minus_1:10
uint32_t R_power:4
uint32_t src_prot_ctrl:3
uint32_t dst_prot_ctrl:3
uint32_t src_size:2
uint32_t src_inc:2
uint32_t dst_size:2
uint32_t dst_inc:2
};
uint32_t word

Detailed Description

DMA Descriptor control type.

Definition at line 187 of file ald_dma.h.

Field Documentation

◆ @1

struct { ... }

◆ cycle_ctrl

uint32_t cycle_ctrl

DMA operating mode dma_cycle_ctrl_t

Definition at line 189 of file ald_dma.h.

◆ dst_inc

uint32_t dst_inc

Destination address increment. dma_data_inc_t

Definition at line 198 of file ald_dma.h.

◆ dst_prot_ctrl

uint32_t dst_prot_ctrl

Control the state of HPROT when writes the destination data

Definition at line 194 of file ald_dma.h.

◆ dst_size

uint32_t dst_size

Destination data size. dma_data_size_t

Definition at line 197 of file ald_dma.h.

◆ n_minus_1

uint32_t n_minus_1

Represent the total number of DMA transfers that DMA cycle contains.

Definition at line 191 of file ald_dma.h.

◆ next_useburst

uint32_t next_useburst

Uses the alternate data structure when complete a DMA cycle

Definition at line 190 of file ald_dma.h.

◆ R_power

uint32_t R_power

Control how many DMA transfers can occur before re-arbitrates. dma_arbiter_config_t

Definition at line 192 of file ald_dma.h.

◆ src_inc

uint32_t src_inc

Control the source address increment. dma_data_inc_t

Definition at line 196 of file ald_dma.h.

◆ src_prot_ctrl

uint32_t src_prot_ctrl

Control the state of HPROT when reads the source data.

Definition at line 193 of file ald_dma.h.

◆ src_size

uint32_t src_size

Source data size dma_data_size_t

Definition at line 195 of file ald_dma.h.

◆ word

uint32_t word

Definition at line 200 of file ald_dma.h.

The documentation for this union was generated from the following file:
  • D:/svn/src/ald_dma.h


ALD User Manual: dma_descriptor_t Struct Reference

Data Fields
dma_descriptor_t Struct Reference
EASTSOFT ES32F3xx ALD » DMA » DMA Public Types

Channel control data structure. More...

#include <ald_dma.h>

Collaboration diagram for dma_descriptor_t:
[legend]

Data Fields

void * | src
void * | dst
dma_ctrl_t ctrl
uint32_t | use

Detailed Description

Channel control data structure.

Definition at line 206 of file ald_dma.h.

Field Documentation

◆ ctrl

dma_ctrl_t ctrl

Control data configuration dma_ctrl_t

Definition at line 209 of file ald_dma.h.

◆ dst

void* dst

Destination data end pointer

Definition at line 208 of file ald_dma.h.

◆ src

void* src

Source data end pointer

Definition at line 207 of file ald_dma.h.

◆ use

uint32_t use

Reserve for user

Definition at line 210 of file ald_dma.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_dma.h


ALD User Manual: dma_call_back_t Struct Reference

Data Fields
dma_call_back_t Struct Reference
EASTSOFT ES32F3xx ALD » DMA » DMA Public Types

Callback function pointer and param. More...

#include <ald_dma.h>

Data Fields

void(* | cplt_cbk )(void *arg)
void(* | err_cbk )(void *arg)
void * | cplt_arg
void * | err_arg

Detailed Description

Callback function pointer and param.

Definition at line 267 of file ald_dma.h.

Field Documentation

◆ cplt_arg

void* cplt_arg

The parameter of cplt_cbk()

Definition at line 270 of file ald_dma.h.

◆ cplt_cbk

void(* cplt_cbk) (void *arg)

DMA transfers complete callback

Definition at line 268 of file ald_dma.h.

◆ err_arg

void* err_arg

The parameter of err_cbk()

Definition at line 271 of file ald_dma.h.

◆ err_cbk

void(* err_cbk) (void *arg)

DMA occurs error callback

Definition at line 269 of file ald_dma.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_dma.h


ALD User Manual: dma_config_t Struct Reference

Data Fields
dma_config_t Struct Reference
EASTSOFT ES32F3xx ALD » DMA » DMA Public Types

DMA channal configure structure. More...

#include <ald_dma.h>

Data Fields

void * | src
void * | dst
uint16_t | size
dma_data_size_t data_width
dma_data_inc_t src_inc
dma_data_inc_t dst_inc
dma_arbiter_config_t R_power
type_func_t primary
type_func_t burst
type_func_t high_prio
type_func_t interrupt
dma_msel_t msel
dma_msigsel_t msigsel
uint8_t | channel

Detailed Description

DMA channal configure structure.

Definition at line 277 of file ald_dma.h.

Field Documentation

◆ burst

type_func_t burst

Enable/Disable the useburst setting for this channel

Definition at line 286 of file ald_dma.h.

◆ channel

uint8_t channel

Channel index

Definition at line 291 of file ald_dma.h.

◆ data_width

dma_data_size_t data_width

Data width, dma_data_size_t

Definition at line 281 of file ald_dma.h.

◆ dst

void* dst

Destination data begin pointer

Definition at line 279 of file ald_dma.h.

◆ dst_inc

dma_data_inc_t dst_inc

Destination increment type. dma_data_inc_t

Definition at line 283 of file ald_dma.h.

◆ high_prio

type_func_t high_prio

High priority or default priority

Definition at line 287 of file ald_dma.h.

◆ interrupt

type_func_t interrupt

Enable/disable interrupt

Definition at line 288 of file ald_dma.h.

◆ msel

dma_msel_t msel

Input source to DMA channel dma_msel_t

Definition at line 289 of file ald_dma.h.

◆ msigsel

dma_msigsel_t msigsel

Input signal to DMA channel dma_msigsel_t

Definition at line 290 of file ald_dma.h.

◆ primary

type_func_t primary

Use primary descriptor or alternate descriptor

Definition at line 285 of file ald_dma.h.

◆ R_power

dma_arbiter_config_t R_power

Control how many DMA transfers can occur before re-arbitrates. dma_arbiter_config_t

Definition at line 284 of file ald_dma.h.

◆ size

uint16_t size

The total number of DMA transfers that DMA cycle contains

Definition at line 280 of file ald_dma.h.

◆ src

void* src

Source data begin pointer

Definition at line 278 of file ald_dma.h.

◆ src_inc

dma_data_inc_t src_inc

Source increment type. dma_data_inc_t

Definition at line 282 of file ald_dma.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_dma.h


ALD User Manual: dma_handle_t Struct Reference

Data Fields
dma_handle_t Struct Reference
EASTSOFT ES32F3xx ALD » DMA » DMA Public Types

DMA handle structure definition. More...

#include <ald_dma.h>

Collaboration diagram for dma_handle_t:
[legend]

Data Fields

DMA_TypeDef * | perh
dma_config_t config
void(* | cplt_cbk )(void *arg)
void(* | err_cbk )(void *arg)
void * | cplt_arg
void * | err_arg

Detailed Description

DMA handle structure definition.

Definition at line 297 of file ald_dma.h.

Field Documentation

◆ config

dma_config_t config

Channel configure structure. dma_config_t

Definition at line 299 of file ald_dma.h.

◆ cplt_arg

void* cplt_arg

The parameter of cplt_cbk()

Definition at line 302 of file ald_dma.h.

◆ cplt_cbk

void(* cplt_cbk) (void *arg)

DMA transfers complete callback

Definition at line 300 of file ald_dma.h.

◆ err_arg

void* err_arg

The parameter of err_cbk()

Definition at line 303 of file ald_dma.h.

◆ err_cbk

void(* err_cbk) (void *arg)

DMA bus occurs error callback

Definition at line 301 of file ald_dma.h.

◆ perh

DMA_TypeDef* perh

DMA registers base address

Definition at line 298 of file ald_dma.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_dma.h


ALD User Manual: DMA Private Macros

Macros
DMA Private Macros
EASTSOFT ES32F3xx ALD » DMA
Collaboration diagram for DMA Private Macros:

Macros

#define | IS_DMA_MSEL_TYPE(x) ((x) <= DMA_MSEL_USB)
#define | IS_DMA_MSIGSEL_TYPE(x) ((x) <= 0xF)
#define | IS_DMA_DATAINC_TYPE(x)
#define | IS_DMA_DATASIZE_TYPE(x)
#define | IS_CYCLECTRL_TYPE(x)
#define | IS_DMA_ARBITERCONFIG_TYPE(x)
#define | IS_DMA(x) ((x) == DMA0)
#define | IS_DMA_CHANNEL(x) ((x) <= 11)
#define | IS_DMA_DATA_SIZE(x) ((x) <= 1024)
#define | IS_DMA_IT_TYPE(x) (((x) <= 11) || ((x) == 31))

Detailed Description

Macro Definition Documentation

◆ IS_CYCLECTRL_TYPE

#define IS_CYCLECTRL_TYPE ( x )
Value:
(((x) == DMA_CYCLE_CTRL_NONE) || \
((x) == DMA_CYCLE_CTRL_BASIC) || \
((x) == DMA_CYCLE_CTRL_AUTO) || \
((x) == DMA_CYCLE_CTRL_PINGPONG) || \
((x) == DMA_CYCLE_CTRL_MEM_SG_PRIMARY) || \
((x) == DMA_CYCLE_CTRL_MEM_SG_ALTERNATE) || \
((x) == DMA_CYCLE_CTRL_PER_SG_PRIMARY) || \
((x) == DMA_CYCLE_CTRL_PER_SG_ALTERNATE))
DMA_CYCLE_CTRL_MEM_SG_PRIMARY
Definition: ald_dma.h:240
DMA_CYCLE_CTRL_PER_SG_PRIMARY
Definition: ald_dma.h:242
DMA_CYCLE_CTRL_BASIC
Definition: ald_dma.h:237
DMA_CYCLE_CTRL_PER_SG_ALTERNATE
Definition: ald_dma.h:243
DMA_CYCLE_CTRL_PINGPONG
Definition: ald_dma.h:239
DMA_CYCLE_CTRL_NONE
Definition: ald_dma.h:236
DMA_CYCLE_CTRL_AUTO
Definition: ald_dma.h:238
DMA_CYCLE_CTRL_MEM_SG_ALTERNATE
Definition: ald_dma.h:241

Definition at line 331 of file ald_dma.h.

◆ IS_DMA

#define IS_DMA ( x ) ((x) == DMA0)

Definition at line 350 of file ald_dma.h.

◆ IS_DMA_ARBITERCONFIG_TYPE

#define IS_DMA_ARBITERCONFIG_TYPE ( x )
Value:
(((x) == DMA_R_POWER_1) || \
((x) == DMA_R_POWER_2) || \
((x) == DMA_R_POWER_4) || \
((x) == DMA_R_POWER_8) || \
((x) == DMA_R_POWER_16) || \
((x) == DMA_R_POWER_32) || \
((x) == DMA_R_POWER_64) || \
((x) == DMA_R_POWER_128) || \
((x) == DMA_R_POWER_256) || \
((x) == DMA_R_POWER_512) || \
((x) == DMA_R_POWER_1024))
DMA_R_POWER_4
Definition: ald_dma.h:253
DMA_R_POWER_128
Definition: ald_dma.h:258
DMA_R_POWER_256
Definition: ald_dma.h:259
DMA_R_POWER_512
Definition: ald_dma.h:260
DMA_R_POWER_64
Definition: ald_dma.h:257
DMA_R_POWER_1024
Definition: ald_dma.h:261
DMA_R_POWER_16
Definition: ald_dma.h:255
DMA_R_POWER_2
Definition: ald_dma.h:252
DMA_R_POWER_8
Definition: ald_dma.h:254
DMA_R_POWER_1
Definition: ald_dma.h:251
DMA_R_POWER_32
Definition: ald_dma.h:256

Definition at line 339 of file ald_dma.h.

◆ IS_DMA_CHANNEL

#define IS_DMA_CHANNEL ( x ) ((x) <= 11)

Definition at line 351 of file ald_dma.h.

◆ IS_DMA_DATA_SIZE

#define IS_DMA_DATA_SIZE ( x ) ((x) <= 1024)

Definition at line 352 of file ald_dma.h.

◆ IS_DMA_DATAINC_TYPE

#define IS_DMA_DATAINC_TYPE ( x )
Value:
(((x) == DMA_DATA_INC_BYTE) || \
((x) == DMA_DATA_INC_HALFWORD) || \
((x) == DMA_DATA_INC_WORD) || \
((x) == DMA_DATA_INC_NONE))
DMA_DATA_INC_WORD
Definition: ald_dma.h:219
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
DMA_DATA_INC_BYTE
Definition: ald_dma.h:217
DMA_DATA_INC_NONE
Definition: ald_dma.h:220

Definition at line 324 of file ald_dma.h.

◆ IS_DMA_DATASIZE_TYPE

#define IS_DMA_DATASIZE_TYPE ( x )
Value:
(((x) == DMA_DATA_SIZE_BYTE) || \
((x) == DMA_DATA_SIZE_HALFWORD) || \
((x) == DMA_DATA_SIZE_WORD))
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
DMA_DATA_SIZE_WORD
Definition: ald_dma.h:229
DMA_DATA_SIZE_BYTE
Definition: ald_dma.h:227

Definition at line 328 of file ald_dma.h.

◆ IS_DMA_IT_TYPE

#define IS_DMA_IT_TYPE ( x ) (((x) <= 11) || ((x) == 31))

Definition at line 353 of file ald_dma.h.

◆ IS_DMA_MSEL_TYPE

#define IS_DMA_MSEL_TYPE ( x ) ((x) <= DMA_MSEL_USB)

Definition at line 322 of file ald_dma.h.

◆ IS_DMA_MSIGSEL_TYPE

#define IS_DMA_MSIGSEL_TYPE ( x ) ((x) <= 0xF)

Definition at line 323 of file ald_dma.h.


ALD User Manual: EBI

Modules
EBI
EASTSOFT ES32F3xx ALD

EBI module driver. More...

Collaboration diagram for EBI:

Modules

EBI Public Functions
EBI Public Macros
EBI Public Types
EBI Private Macros

Detailed Description

EBI module driver.


ALD User Manual: EBI Public Functions

Modules
EBI Public Functions
EASTSOFT ES32F3xx ALD » EBI
Collaboration diagram for EBI Public Functions:

Modules

NOR-FLASH SRAM initialize functions
NOR-FLASH SRAM initialize functions.
NOR-FLASH SRAM control functions
NOR-FLASH SRAM control functions.
NAND-FLASH initialize functions
NAND-FLASH initialize functions.
NAND-FLASH control functions
NAND-FLASH control functions.
LCD initialize functions
LCD initialize functions.

Detailed Description


ALD User Manual: NOR-FLASH SRAM initialize functions

Functions
NOR-FLASH SRAM initialize functions
EASTSOFT ES32F3xx ALD » EBI » EBI Public Functions

NOR-FLASH SRAM initialize functions. More...

Collaboration diagram for NOR-FLASH SRAM initialize functions:

Functions

void | ald_ebi_nor_sram_init (EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_init_t *init)
Initialize the EBI_NOR_SRAM device according to the specified control parameters in the EBI_NOR_SRAM_InitTypeDef. More...
void | ald_ebi_nor_sram_timing_init (EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank)
Initialize the EBI_NOR_SRAM Timing according to the specified parameters in the EBI_NOR_SRAM_TimingTypeDef. More...
void | ald_ebi_nor_sram_ext_timing_init (EBI_NOR_SRAM_EXTENDED_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank, uint32_t mode)
Initialize the EBI_NOR_SRAM Extended mode Timing according to the specified parameters in the EBI_NOR_SRAM_TimingTypeDef. More...
ald_status_t | ald_ebi_nor_sram_deinit (EBI_NOR_SRAM_TypeDef *dev, EBI_NOR_SRAM_EXTENDED_TypeDef *e_dev, uint32_t bank)
DeInitialize the EBI_NOR_SRAM peripheral. More...

Detailed Description

NOR-FLASH SRAM initialize functions.

Function Documentation

◆ ald_ebi_nor_sram_deinit()

ald_status_t ald_ebi_nor_sram_deinit | ( | EBI_NOR_SRAM_TypeDef * | dev,
 |  | EBI_NOR_SRAM_EXTENDED_TypeDef * | e_dev,
 |  | uint32_t | bank
 | ) |  |

DeInitialize the EBI_NOR_SRAM peripheral.

Parameters
dev | Pointer to NOR_SRAM device instance
e_dev | Pointer to NOR_SRAM extended mode device instance
bank | NOR_SRAM bank number
Return values
ald status

Definition at line 172 of file ald_ebi.c.

173 {
174 assert_param(IS_EBI_NORSRAM_DEVICE(dev));
175 assert_param(IS_EBI_NORSRAM_EXTENDED_DEVICE(e_dev));
176 assert_param(IS_EBI_NORSRAM_BANK(bank));
177
178 /* Disable the EBI_NOR/SRAM device */
179 ald_ebi_nor_sram_disable(dev, bank);
180
181 /* De-initialize the EBI_NOR/SRAM device */
182 if (bank == EBI_NORSRAM_BANK1)
183 dev->BTCR[bank] = 0x000030DBU;
184 else
185 dev->BTCR[bank] = 0x000030D2U;
186
187 dev->BTCR[bank + 1U] = 0x0FFFFFFFU;
188 e_dev->BWTR[bank] = 0x0FFFFFFFU;
189
190 return OK;
191 }
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
IS_EBI_NORSRAM_BANK
#define IS_EBI_NORSRAM_BANK(x)
Definition: ald_ebi.h:421
IS_EBI_NORSRAM_EXTENDED_DEVICE
#define IS_EBI_NORSRAM_EXTENDED_DEVICE(x)
Definition: ald_ebi.h:479
ald_ebi_nor_sram_disable
void ald_ebi_nor_sram_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Disable the NORSRAM device access.
Definition: ald_ebi.c:220
IS_EBI_NORSRAM_DEVICE
#define IS_EBI_NORSRAM_DEVICE(x)
Definition: ald_ebi.h:478
EBI_NORSRAM_BANK1
Definition: ald_ebi.h:190

◆ ald_ebi_nor_sram_ext_timing_init()

void ald_ebi_nor_sram_ext_timing_init | ( | EBI_NOR_SRAM_EXTENDED_TypeDef * | dev,
 |  | ald_ebi_nor_sram_timing_t * | timing,
 |  | uint32_t | bank,
 |  | uint32_t | mode
 | ) |  |

Initialize the EBI_NOR_SRAM Extended mode Timing according to the specified parameters in the EBI_NOR_SRAM_TimingTypeDef.

Parameters
dev | Pointer to NOR_SRAM device instance
timing | Pointer to NOR_SRAM Timing structure
bank | NOR_SRAM bank number
mode EBI Extended Mode This parameter can be one of the following values:
  • EBI_EXTENDED_MODE_DISABLE
  • EBI_EXTENDED_MODE_ENABLE
Return values
None

Definition at line 138 of file ald_ebi.c.

139 {
140 assert_param(IS_EBI_EXTENDED_MODE(mode));
141
142 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
143 if (mode == EBI_EXTENDED_MODE_ENABLE) {
144 assert_param(IS_EBI_NORSRAM_EXTENDED_DEVICE(dev));
145 assert_param(IS_EBI_ADDRESS_SETUP_TIME(timing->addr_setup));
146 assert_param(IS_EBI_ADDRESS_HOLD_TIME(timing->addr_hold));
147 assert_param(IS_EBI_DATASETUP_TIME(timing->data_setup));
148 assert_param(IS_EBI_TURNAROUND_TIME(timing->bus_dur));
149 assert_param(IS_EBI_ACCESS_MODE(timing->mode));
150 assert_param(IS_EBI_NORSRAM_BANK(bank));
151
152 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
153 MODIFY_REG(dev->BWTR[bank], BWTR_CLEAR_MASK, \
154 (uint32_t)(timing->addr_setup | \
155 ((timing->addr_hold) << EBI_BWRTRx_ADDHOLD_POSS) | \
156 ((timing->data_setup) << EBI_BWRTRx_DATAHOLD_POSS) | \
157 timing->mode | \
158 ((timing->bus_dur) << EBI_BWRTRx_BUSTURN_POSS)));
159 }
160 else {
161 dev->BWTR[bank] = 0x0FFFFFFFU;
162 }
163 }
IS_EBI_EXTENDED_MODE
#define IS_EBI_EXTENDED_MODE(x)
Definition: ald_ebi.h:493
assert_param
#define assert_param(x)
Definition: type.h:88
IS_EBI_DATASETUP_TIME
#define IS_EBI_DATASETUP_TIME(x)
Definition: ald_ebi.h:501
BWTR_CLEAR_MASK
#define BWTR_CLEAR_MASK
Definition: ald_ebi.h:80
EBI_EXTENDED_MODE_ENABLE
Definition: ald_ebi.h:275
ald_ebi_nor_sram_timing_t::addr_hold
uint32_t addr_hold
Definition: ald_ebi.h:111
ald_ebi_nor_sram_timing_t::mode
ebi_access_mode_t mode
Definition: ald_ebi.h:116
ald_ebi_nor_sram_timing_t::data_setup
uint32_t data_setup
Definition: ald_ebi.h:112
IS_EBI_ADDRESS_HOLD_TIME
#define IS_EBI_ADDRESS_HOLD_TIME(x)
Definition: ald_ebi.h:500
ald_ebi_nor_sram_timing_t::bus_dur
uint32_t bus_dur
Definition: ald_ebi.h:113
IS_EBI_ACCESS_MODE
#define IS_EBI_ACCESS_MODE(x)
Definition: ald_ebi.h:435
IS_EBI_NORSRAM_BANK
#define IS_EBI_NORSRAM_BANK(x)
Definition: ald_ebi.h:421
IS_EBI_NORSRAM_EXTENDED_DEVICE
#define IS_EBI_NORSRAM_EXTENDED_DEVICE(x)
Definition: ald_ebi.h:479
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
ald_ebi_nor_sram_timing_t::addr_setup
uint32_t addr_setup
Definition: ald_ebi.h:110
IS_EBI_ADDRESS_SETUP_TIME
#define IS_EBI_ADDRESS_SETUP_TIME(x)
Definition: ald_ebi.h:499
IS_EBI_TURNAROUND_TIME
#define IS_EBI_TURNAROUND_TIME(x)
Definition: ald_ebi.h:502

◆ ald_ebi_nor_sram_init()

void ald_ebi_nor_sram_init | ( | EBI_NOR_SRAM_TypeDef * | dev,
 |  | ald_ebi_nor_sram_init_t * | init
 | ) |  |

Initialize the EBI_NOR_SRAM device according to the specified control parameters in the EBI_NOR_SRAM_InitTypeDef.

Parameters
dev | Pointer to NOR_SRAM device instance
init | Pointer to NOR_SRAM Initialization structure
Return values
None

Definition at line 43 of file ald_ebi.c.

44 {
45 assert_param(IS_EBI_NORSRAM_DEVICE(dev));
46 assert_param(IS_EBI_NORSRAM_BANK(init->bank));
47 assert_param(IS_EBI_MUX(init->mux));
48 assert_param(IS_EBI_MEMORY(init->type));
49 assert_param(IS_EBI_NORSRAM_MEMORY_WIDTH(init->width));
50 assert_param(IS_EBI_BURSTMODE(init->acc_mode));
51 assert_param(IS_EBI_WAIT_POLARITY(init->polarity));
52 assert_param(IS_EBI_WRAP_MODE(init->wrap_mode));
53 assert_param(IS_EBI_WAIT_SIGNAL_ACTIVE(init->active));
54 assert_param(IS_EBI_WRITE_OPERATION(init->write));
55 assert_param(IS_EBI_WAITE_SIGNAL(init->signal));
56 assert_param(IS_EBI_EXTENDED_MODE(init->ext_mode));
57 assert_param(IS_EBI_ASYNWAIT(init->wait));
58 assert_param(IS_EBI_WRITE_BURST(init->burst));
59
60 /* Disable NORSRAM device */
61 ald_ebi_nor_sram_disable(dev, init->bank);
62
63 /* Set NORSRAM device control parameters */
64 if (init->type == EBI_MEMORY_TYPE_NOR) {
65 MODIFY_REG(dev->BTCR[init->bank], BCTRLR_CLEAR_MASK, (uint32_t)((uint32_t)EBI_NORSRAM_FLASH_ACCESS_ENABLE
66 | (uint32_t)init->mux
67 | (uint32_t)init->type
68 | (uint32_t)init->width
69 | (uint32_t)init->acc_mode
70 | (uint32_t)init->polarity
71 | (uint32_t)init->wrap_mode
72 | (uint32_t)init->active
73 | (uint32_t)init->write
74 | (uint32_t)init->signal
75 | (uint32_t)init->ext_mode
76 | (uint32_t)init->wait
77 | (uint32_t)init->burst));
78 }
79 else {
80 MODIFY_REG(dev->BTCR[init->bank], BCTRLR_CLEAR_MASK, (uint32_t)(EBI_NORSRAM_FLASH_ACCESS_DISABLE
81 | (uint32_t)init->mux
82 | (uint32_t)init->type
83 | (uint32_t)init->width
84 | (uint32_t)init->acc_mode
85 | (uint32_t)init->polarity
86 | (uint32_t)init->wrap_mode
87 | (uint32_t)init->active
88 | (uint32_t)init->write
89 | (uint32_t)init->signal
90 | (uint32_t)init->ext_mode
91 | (uint32_t)init->wait
92 | (uint32_t)init->burst));
93 }
94 }
IS_EBI_MUX
#define IS_EBI_MUX(x)
Definition: ald_ebi.h:425
ald_ebi_nor_sram_init_t::mux
ebi_data_address_mux_t mux
Definition: ald_ebi.h:400
IS_EBI_WAIT_SIGNAL_ACTIVE
#define IS_EBI_WAIT_SIGNAL_ACTIVE(x)
Definition: ald_ebi.h:487
IS_EBI_EXTENDED_MODE
#define IS_EBI_EXTENDED_MODE(x)
Definition: ald_ebi.h:493
EBI_NORSRAM_FLASH_ACCESS_ENABLE
Definition: ald_ebi.h:219
assert_param
#define assert_param(x)
Definition: type.h:88
IS_EBI_WAIT_POLARITY
#define IS_EBI_WAIT_POLARITY(x)
Definition: ald_ebi.h:483
IS_EBI_ASYNWAIT
#define IS_EBI_ASYNWAIT(x)
Definition: ald_ebi.h:495
IS_EBI_NORSRAM_MEMORY_WIDTH
#define IS_EBI_NORSRAM_MEMORY_WIDTH(x)
Definition: ald_ebi.h:430
IS_EBI_WAITE_SIGNAL
#define IS_EBI_WAITE_SIGNAL(x)
Definition: ald_ebi.h:491
ald_ebi_nor_sram_init_t::signal
ebi_wait_signal_t signal
Definition: ald_ebi.h:408
BCTRLR_CLEAR_MASK
#define BCTRLR_CLEAR_MASK
Definition: ald_ebi.h:66
IS_EBI_WRITE_OPERATION
#define IS_EBI_WRITE_OPERATION(x)
Definition: ald_ebi.h:489
ald_ebi_nor_sram_init_t::ext_mode
ebi_extended_mode_t ext_mode
Definition: ald_ebi.h:409
EBI_NORSRAM_FLASH_ACCESS_DISABLE
Definition: ald_ebi.h:218
ald_ebi_nor_sram_init_t::burst
ebi_write_burst_t burst
Definition: ald_ebi.h:411
ald_ebi_nor_sram_init_t::polarity
ebi_wait_signal_polarity_t polarity
Definition: ald_ebi.h:404
ald_ebi_nor_sram_init_t::wait
ebi_asynchronous_wait_t wait
Definition: ald_ebi.h:410
ald_ebi_nor_sram_init_t::active
ebi_wait_timing_t active
Definition: ald_ebi.h:406
ald_ebi_nor_sram_init_t::wrap_mode
ebi_wrap_mode_t wrap_mode
Definition: ald_ebi.h:405
EBI_MEMORY_TYPE_NOR
Definition: ald_ebi.h:202
IS_EBI_MEMORY
#define IS_EBI_MEMORY(x)
Definition: ald_ebi.h:427
IS_EBI_NORSRAM_BANK
#define IS_EBI_NORSRAM_BANK(x)
Definition: ald_ebi.h:421
ald_ebi_nor_sram_init_t::write
ebi_write_operation_t write
Definition: ald_ebi.h:407
IS_EBI_WRAP_MODE
#define IS_EBI_WRAP_MODE(x)
Definition: ald_ebi.h:485
ald_ebi_nor_sram_init_t::acc_mode
ebi_burst_access_mode_t acc_mode
Definition: ald_ebi.h:403
ald_ebi_nor_sram_init_t::width
ebi_norsram_mem_bus_width_t width
Definition: ald_ebi.h:402
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_EBI_BURSTMODE
#define IS_EBI_BURSTMODE(x)
Definition: ald_ebi.h:481
IS_EBI_WRITE_BURST
#define IS_EBI_WRITE_BURST(x)
Definition: ald_ebi.h:433
ald_ebi_nor_sram_init_t::type
ebi_memory_type_t type
Definition: ald_ebi.h:401
ald_ebi_nor_sram_disable
void ald_ebi_nor_sram_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Disable the NORSRAM device access.
Definition: ald_ebi.c:220
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399
IS_EBI_NORSRAM_DEVICE
#define IS_EBI_NORSRAM_DEVICE(x)
Definition: ald_ebi.h:478

◆ ald_ebi_nor_sram_timing_init()

void ald_ebi_nor_sram_timing_init | ( | EBI_NOR_SRAM_TypeDef * | dev,
 |  | ald_ebi_nor_sram_timing_t * | timing,
 |  | uint32_t | bank
 | ) |  |

Initialize the EBI_NOR_SRAM Timing according to the specified parameters in the EBI_NOR_SRAM_TimingTypeDef.

Parameters
dev | Pointer to NOR_SRAM device instance
timing | Pointer to NOR_SRAM Timing structure
bank | NOR_SRAM bank number
Return values
None

Definition at line 104 of file ald_ebi.c.

105 {
106 assert_param(IS_EBI_NORSRAM_DEVICE(dev));
107 assert_param(IS_EBI_ADDRESS_SETUP_TIME(timing->addr_setup));
108 assert_param(IS_EBI_ADDRESS_HOLD_TIME(timing->addr_hold));
109 assert_param(IS_EBI_DATASETUP_TIME(timing->data_setup));
110 assert_param(IS_EBI_TURNAROUND_TIME(timing->bus_dur));
111 assert_param(IS_EBI_DATA_LATENCY(timing->latency));
112 assert_param(IS_EBI_ACCESS_MODE(timing->mode));
113 assert_param(IS_EBI_NORSRAM_BANK(bank));
114
115 /* Set EBI_NORSRAM device timing parameters */
116 MODIFY_REG(dev->BTCR[bank + 1U], BTR_CLEAR_MASK, \
117 (uint32_t)(timing->addr_setup | \
118 ((timing->addr_hold) << EBI_BTRx_ADDHOLD_POSS) | \
119 ((timing->data_setup) << EBI_BTRx_DATAHOLD_POSS) | \
120 ((timing->bus_dur) << EBI_BTRx_BUSTURN_POSS) | \
121 (((timing->div) - 1U) << EBI_BTRx_CLKDIV_POSS) | \
122 (((timing->latency) - 1U) << EBI_BTRx_DATALAT_POSS) | \
123 (timing->mode)));
124 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_EBI_DATASETUP_TIME
#define IS_EBI_DATASETUP_TIME(x)
Definition: ald_ebi.h:501
ald_ebi_nor_sram_timing_t::addr_hold
uint32_t addr_hold
Definition: ald_ebi.h:111
ald_ebi_nor_sram_timing_t::mode
ebi_access_mode_t mode
Definition: ald_ebi.h:116
ald_ebi_nor_sram_timing_t::data_setup
uint32_t data_setup
Definition: ald_ebi.h:112
ald_ebi_nor_sram_timing_t::div
uint32_t div
Definition: ald_ebi.h:114
IS_EBI_DATA_LATENCY
#define IS_EBI_DATA_LATENCY(x)
Definition: ald_ebi.h:498
BTR_CLEAR_MASK
#define BTR_CLEAR_MASK
Definition: ald_ebi.h:74
IS_EBI_ADDRESS_HOLD_TIME
#define IS_EBI_ADDRESS_HOLD_TIME(x)
Definition: ald_ebi.h:500
ald_ebi_nor_sram_timing_t::bus_dur
uint32_t bus_dur
Definition: ald_ebi.h:113
ald_ebi_nor_sram_timing_t::latency
uint32_t latency
Definition: ald_ebi.h:115
IS_EBI_ACCESS_MODE
#define IS_EBI_ACCESS_MODE(x)
Definition: ald_ebi.h:435
IS_EBI_NORSRAM_BANK
#define IS_EBI_NORSRAM_BANK(x)
Definition: ald_ebi.h:421
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
ald_ebi_nor_sram_timing_t::addr_setup
uint32_t addr_setup
Definition: ald_ebi.h:110
IS_EBI_NORSRAM_DEVICE
#define IS_EBI_NORSRAM_DEVICE(x)
Definition: ald_ebi.h:478
IS_EBI_ADDRESS_SETUP_TIME
#define IS_EBI_ADDRESS_SETUP_TIME(x)
Definition: ald_ebi.h:499
IS_EBI_TURNAROUND_TIME
#define IS_EBI_TURNAROUND_TIME(x)
Definition: ald_ebi.h:502


ALD User Manual: NOR-FLASH SRAM control functions

Functions
NOR-FLASH SRAM control functions
EASTSOFT ES32F3xx ALD » EBI » EBI Public Functions

NOR-FLASH SRAM control functions. More...

Collaboration diagram for NOR-FLASH SRAM control functions:

Functions

void | ald_ebi_nor_sram_enable (EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Enable the NOR/SRAM device access. More...
void | ald_ebi_nor_sram_disable (EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Disable the NORSRAM device access. More...
void | ald_ebi_nor_sram_write_enable (EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Enables dynamically NOR-FLASH/SRAM write operation. More...
void | ald_ebi_nor_sram_write_disable (EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Disables dynamically EBI_NORSRAM write operation. More...

Detailed Description

NOR-FLASH SRAM control functions.

Function Documentation

◆ ald_ebi_nor_sram_disable()

void ald_ebi_nor_sram_disable | ( | EBI_NOR_SRAM_TypeDef * | dev,
 |  | uint32_t | bank
 | ) |  |

Disable the NORSRAM device access.

Parameters
dev | EBI_NORSRAM Instance
bank | EBI_NORSRAM Bank
Return values
none

Definition at line 220 of file ald_ebi.c.

221 {
222 assert_param(IS_EBI_NORSRAM_DEVICE(dev));
223 assert_param(IS_EBI_NORSRAM_BANK(bank));
224
225 CLEAR_BIT(dev->BTCR[bank], EBI_BCTRLRx_MEMBKEN_MSK);
226 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_EBI_NORSRAM_BANK
#define IS_EBI_NORSRAM_BANK(x)
Definition: ald_ebi.h:421
IS_EBI_NORSRAM_DEVICE
#define IS_EBI_NORSRAM_DEVICE(x)
Definition: ald_ebi.h:478

◆ ald_ebi_nor_sram_enable()

void ald_ebi_nor_sram_enable | ( | EBI_NOR_SRAM_TypeDef * | dev,
 |  | uint32_t | bank
 | ) |  |

Enable the NOR/SRAM device access.

Parameters
dev | NOR/SRAM Instance
bank | NOR/SRAM Bank
Return values
none

Definition at line 206 of file ald_ebi.c.

207 {
208 assert_param(IS_EBI_NORSRAM_DEVICE(dev));
209 assert_param(IS_EBI_NORSRAM_BANK(bank));
210
211 SET_BIT(dev->BTCR[bank], EBI_BCTRLRx_MEMBKEN_MSK);
212 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_EBI_NORSRAM_BANK
#define IS_EBI_NORSRAM_BANK(x)
Definition: ald_ebi.h:421
IS_EBI_NORSRAM_DEVICE
#define IS_EBI_NORSRAM_DEVICE(x)
Definition: ald_ebi.h:478

◆ ald_ebi_nor_sram_write_disable()

void ald_ebi_nor_sram_write_disable | ( | EBI_NOR_SRAM_TypeDef * | dev,
 |  | uint32_t | bank
 | ) |  |

Disables dynamically EBI_NORSRAM write operation.

Parameters
dev | Pointer to NORSRAM device instance
bank | NORSRAM bank number
Return values
None

Definition at line 249 of file ald_ebi.c.

250 {
251 assert_param(IS_EBI_NORSRAM_DEVICE(dev));
252 assert_param(IS_EBI_NORSRAM_BANK(bank));
253
254 /* Disable write operation */
255 CLEAR_BIT(dev->BTCR[bank], EBI_WRITE_OPERATION_ENABLE);
256 }
EBI_WRITE_OPERATION_ENABLE
Definition: ald_ebi.h:259
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_EBI_NORSRAM_BANK
#define IS_EBI_NORSRAM_BANK(x)
Definition: ald_ebi.h:421
IS_EBI_NORSRAM_DEVICE
#define IS_EBI_NORSRAM_DEVICE(x)
Definition: ald_ebi.h:478

◆ ald_ebi_nor_sram_write_enable()

void ald_ebi_nor_sram_write_enable | ( | EBI_NOR_SRAM_TypeDef * | dev,
 |  | uint32_t | bank
 | ) |  |

Enables dynamically NOR-FLASH/SRAM write operation.

Parameters
dev | Pointer to NOR/SRAM device instance
bank | NOR/SRAM bank number
Return values
void

Definition at line 234 of file ald_ebi.c.

235 {
236 assert_param(IS_EBI_NORSRAM_DEVICE(dev));
237 assert_param(IS_EBI_NORSRAM_BANK(bank));
238
239 /* Enable write operation */
240 SET_BIT(dev->BTCR[bank], EBI_WRITE_OPERATION_ENABLE);
241 }
EBI_WRITE_OPERATION_ENABLE
Definition: ald_ebi.h:259
assert_param
#define assert_param(x)
Definition: type.h:88
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_EBI_NORSRAM_BANK
#define IS_EBI_NORSRAM_BANK(x)
Definition: ald_ebi.h:421
IS_EBI_NORSRAM_DEVICE
#define IS_EBI_NORSRAM_DEVICE(x)
Definition: ald_ebi.h:478


ALD User Manual: NAND-FLASH initialize functions

Functions
NAND-FLASH initialize functions
EASTSOFT ES32F3xx ALD » EBI » EBI Public Functions

NAND-FLASH initialize functions. More...

Collaboration diagram for NAND-FLASH initialize functions:

Functions

void | ald_ebi_nand_init (EBI_NAND_TypeDef *dev, ald_ebi_nand_init_t *init)
Initializes the EBI_NAND device according to the specified control parameters in the EBI_NAND_HandleTypeDef. More...
void | ald_ebi_nand_comm_timing_init (EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
Initializes the EBI_NAND Common space Timing according to the specified parameters in the EBI_NAND_TimingTypeDef. More...
void | ald_ebi_nand_attr_timing_init (EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
Initializes the EBI_NAND Attribute space Timing according to the specified parameters in the EBI_NAND_TimingTypeDef. More...
void | ald_ebi_nand_deinit (EBI_NAND_TypeDef *dev, uint32_t bank)
DeInitializes the EBI_NAND device. More...

Detailed Description

NAND-FLASH initialize functions.

Function Documentation

◆ ald_ebi_nand_attr_timing_init()

void ald_ebi_nand_attr_timing_init | ( | EBI_NAND_TypeDef * | dev,
 |  | ald_ebi_nand_timing_t * | timing,
 |  | uint32_t | bank
 | ) |  |

Initializes the EBI_NAND Attribute space Timing according to the specified parameters in the EBI_NAND_TimingTypeDef.

Parameters
dev | Pointer to NAND device instance
timing | Pointer to NAND timing structure
bank | NAND bank number
Return values
None

Definition at line 344 of file ald_ebi.c.

345 {
346 assert_param(IS_EBI_NAND_DEVICE(dev));
347 assert_param(IS_EBI_SETUP_TIME(timing->time));
348 assert_param(IS_EBI_WAIT_TIME(timing->wait_time));
349 assert_param(IS_EBI_HOLD_TIME(timing->hold_time));
350 assert_param(IS_EBI_HIZ_TIME(timing->hiz_time));
351 assert_param(IS_EBI_NAND_BANK(bank));
352
353 /* Set FMC_NAND device timing parameters */
354 if (bank == EBI_NAND_BANK2) {
355 MODIFY_REG(dev->PATTR2, PATTR_CLEAR_MASK, (timing->time | \
356 ((timing->wait_time) << EBI_PATTRx_ATTWAIT_POSS) | \
357 ((timing->hold_time) << EBI_PATTRx_ATTHOLD_POSS) | \
358 ((timing->hiz_time) << EBI_PATTRx_ATTHIZT_POSS)));
359 }
360 else {
361 MODIFY_REG(dev->PATTR3, PATTR_CLEAR_MASK, (timing->time | \
362 ((timing->wait_time) << EBI_PATTRx_ATTWAIT_POSS) | \
363 ((timing->hold_time) << EBI_PATTRx_ATTHOLD_POSS) | \
364 ((timing->hiz_time) << EBI_PATTRx_ATTHIZT_POSS)));
365 }
366 }
assert_param
#define assert_param(x)
Definition: type.h:88
ald_ebi_nand_timing_t::hiz_time
uint32_t hiz_time
Definition: ald_ebi.h:175
ald_ebi_nand_timing_t::time
uint32_t time
Definition: ald_ebi.h:172
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
IS_EBI_WAIT_TIME
#define IS_EBI_WAIT_TIME(x)
Definition: ald_ebi.h:475
IS_EBI_SETUP_TIME
#define IS_EBI_SETUP_TIME(x)
Definition: ald_ebi.h:474
ald_ebi_nand_timing_t::hold_time
uint32_t hold_time
Definition: ald_ebi.h:174
IS_EBI_NAND_DEVICE
#define IS_EBI_NAND_DEVICE(x)
Definition: ald_ebi.h:480
PATTR_CLEAR_MASK
#define PATTR_CLEAR_MASK
Definition: ald_ebi.h:62
IS_EBI_HOLD_TIME
#define IS_EBI_HOLD_TIME(x)
Definition: ald_ebi.h:476
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_EBI_NAND_BANK
#define IS_EBI_NAND_BANK(x)
Definition: ald_ebi.h:439
IS_EBI_HIZ_TIME
#define IS_EBI_HIZ_TIME(x)
Definition: ald_ebi.h:477
ald_ebi_nand_timing_t::wait_time
uint32_t wait_time
Definition: ald_ebi.h:173

◆ ald_ebi_nand_comm_timing_init()

void ald_ebi_nand_comm_timing_init | ( | EBI_NAND_TypeDef * | dev,
 |  | ald_ebi_nand_timing_t * | timing,
 |  | uint32_t | bank
 | ) |  |

Initializes the EBI_NAND Common space Timing according to the specified parameters in the EBI_NAND_TimingTypeDef.

Parameters
dev | Pointer to NAND device instance
timing | Pointer to NAND timing structure
bank | NAND bank number
Return values
None

Definition at line 312 of file ald_ebi.c.

313 {
314 assert_param(IS_EBI_NAND_DEVICE(dev));
315 assert_param(IS_EBI_SETUP_TIME(timing->time));
316 assert_param(IS_EBI_WAIT_TIME(timing->wait_time));
317 assert_param(IS_EBI_HOLD_TIME(timing->hold_time));
318 assert_param(IS_EBI_HIZ_TIME(timing->hiz_time));
319 assert_param(IS_EBI_NAND_BANK(bank));
320
321 /* Set EBI_NAND device timing parameters */
322 if (bank == EBI_NAND_BANK2) {
323 MODIFY_REG(dev->PMEMR2, PMEMR_CLEAR_MASK, (timing->time | \
324 ((timing->wait_time) << EBI_PMEMRx_MEMWAIT_POSS) | \
325 ((timing->hold_time) << EBI_PMEMRx_MEMHOLD_POSS) | \
326 ((timing->hiz_time) << EBI_PMEMRx_MEMHIZT_POSS)));
327 }
328 else {
329 MODIFY_REG(dev->PMEMR3, PMEMR_CLEAR_MASK, (timing->time | \
330 ((timing->wait_time) << EBI_PMEMRx_MEMWAIT_POSS) | \
331 ((timing->hold_time) << EBI_PMEMRx_MEMHOLD_POSS) | \
332 ((timing->hiz_time) << EBI_PMEMRx_MEMHIZT_POSS)));
333 }
334 }
assert_param
#define assert_param(x)
Definition: type.h:88
ald_ebi_nand_timing_t::hiz_time
uint32_t hiz_time
Definition: ald_ebi.h:175
ald_ebi_nand_timing_t::time
uint32_t time
Definition: ald_ebi.h:172
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
IS_EBI_WAIT_TIME
#define IS_EBI_WAIT_TIME(x)
Definition: ald_ebi.h:475
IS_EBI_SETUP_TIME
#define IS_EBI_SETUP_TIME(x)
Definition: ald_ebi.h:474
ald_ebi_nand_timing_t::hold_time
uint32_t hold_time
Definition: ald_ebi.h:174
IS_EBI_NAND_DEVICE
#define IS_EBI_NAND_DEVICE(x)
Definition: ald_ebi.h:480
PMEMR_CLEAR_MASK
#define PMEMR_CLEAR_MASK
Definition: ald_ebi.h:58
IS_EBI_HOLD_TIME
#define IS_EBI_HOLD_TIME(x)
Definition: ald_ebi.h:476
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_EBI_NAND_BANK
#define IS_EBI_NAND_BANK(x)
Definition: ald_ebi.h:439
IS_EBI_HIZ_TIME
#define IS_EBI_HIZ_TIME(x)
Definition: ald_ebi.h:477
ald_ebi_nand_timing_t::wait_time
uint32_t wait_time
Definition: ald_ebi.h:173

◆ ald_ebi_nand_deinit()

void ald_ebi_nand_deinit | ( | EBI_NAND_TypeDef * | dev,
 |  | uint32_t | bank
 | ) |  |

DeInitializes the EBI_NAND device.

Parameters
dev | Pointer to NAND device instance
bank | NAND bank number
Return values
None

Definition at line 374 of file ald_ebi.c.

375 {
376 assert_param(IS_EBI_NAND_DEVICE(dev));
377 assert_param(IS_EBI_NAND_BANK(bank));
378
379 /* Disable the NAND Bank */
380 ald_ebi_nand_disable(dev, bank);
381
382 /* De-initialize the NAND Bank */
383 if (bank == EBI_NAND_BANK2) {
384 /* Set the EBI_NAND_BANK2 registers to their reset values */
385 WRITE_REG(dev->PCTRLR2, 0x00000018U);
386 WRITE_REG(dev->STAR2, 0x00000040U);
387 WRITE_REG(dev->PMEMR2, 0xFCFCFCFCU);
388 WRITE_REG(dev->PATTR2, 0xFCFCFCFCU);
389 }
390 /* EBI_Bank3_NAND */
391 else {
392 /* Set the EBI_NAND_BANK3 registers to their reset values */
393 WRITE_REG(dev->PCTRLR3, 0x00000018U);
394 WRITE_REG(dev->STAR3, 0x00000040U);
395 WRITE_REG(dev->PMEMR3, 0xFCFCFCFCU);
396 WRITE_REG(dev->PATTR3, 0xFCFCFCFCU);
397 }
398 }
assert_param
#define assert_param(x)
Definition: type.h:88
ald_ebi_nand_disable
void ald_ebi_nand_disable(EBI_NAND_TypeDef *dev, uint32_t bank)
Disable the NAND device access.
Definition: ald_ebi.c:430
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
IS_EBI_NAND_DEVICE
#define IS_EBI_NAND_DEVICE(x)
Definition: ald_ebi.h:480
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
IS_EBI_NAND_BANK
#define IS_EBI_NAND_BANK(x)
Definition: ald_ebi.h:439

◆ ald_ebi_nand_init()

void ald_ebi_nand_init | ( | EBI_NAND_TypeDef * | dev,
 |  | ald_ebi_nand_init_t * | init
 | ) |  |

Initializes the EBI_NAND device according to the specified control parameters in the EBI_NAND_HandleTypeDef.

Parameters
dev | Pointer to NAND device instance
init | Pointer to NAND Initialization structure
Return values
None

Definition at line 272 of file ald_ebi.c.

273 {
274 assert_param(IS_EBI_NAND_DEVICE(dev));
275 assert_param(IS_EBI_NAND_BANK(init->bank));
276 assert_param(IS_EBI_WAIT_FEATURE(init->wait));
277 assert_param(IS_EBI_NAND_MEMORY_WIDTH(init->width));
278 assert_param(IS_EBI_ECC_STATE(init->ecc));
279 assert_param(IS_EBI_ECCPAGE_SIZE(init->size));
280 assert_param(IS_EBI_TCLR_TIME(init->cle_time));
281 assert_param(IS_EBI_TAR_TIME(init->ale_time));
282
283 /* Set NAND device control parameters */
284 if (init->bank == EBI_NAND_BANK2) {
285 MODIFY_REG(dev->PCTRLR2, PCTRLR_CLEAR_MASK, ((uint32_t)init->wait |
286 (uint32_t)EBI_PCTRLR_MEMORY_TYPE_NAND |
287 (uint32_t)init->width |
288 (uint32_t)init->ecc |
289 (uint32_t)init->size |
290 (uint32_t)((init->cle_time) << EBI_PCTRLRx_CRDLY_POSS) |
291 (uint32_t)((init->ale_time) << EBI_PCTRLRx_ARDLY_POSS)));
292 }
293 else {
294 MODIFY_REG(dev->PCTRLR3, PCTRLR_CLEAR_MASK, ((uint32_t)init->wait |
295 (uint32_t)EBI_PCTRLR_MEMORY_TYPE_NAND |
296 (uint32_t)init->width |
297 (uint32_t)init->ecc |
298 (uint32_t)init->size |
299 (uint32_t)((init->cle_time) << EBI_PCTRLRx_CRDLY_POSS) |
300 (uint32_t)((init->ale_time) << EBI_PCTRLRx_ARDLY_POSS)));
301 }
302 }
IS_EBI_TAR_TIME
#define IS_EBI_TAR_TIME(x)
Definition: ald_ebi.h:473
ald_ebi_nand_init_t::size
ebi_md_ecc_page_size_t size
Definition: ald_ebi.h:163
IS_EBI_WAIT_FEATURE
#define IS_EBI_WAIT_FEATURE(x)
Definition: ald_ebi.h:441
assert_param
#define assert_param(x)
Definition: type.h:88
IS_EBI_ECCPAGE_SIZE
#define IS_EBI_ECCPAGE_SIZE(x)
Definition: ald_ebi.h:447
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
ald_ebi_nand_init_t::ale_time
uint32_t ale_time
Definition: ald_ebi.h:165
ald_ebi_nand_init_t::width
ebi_nand_mem_bus_width_t width
Definition: ald_ebi.h:161
IS_EBI_ECC_STATE
#define IS_EBI_ECC_STATE(x)
Definition: ald_ebi.h:445
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159
IS_EBI_NAND_DEVICE
#define IS_EBI_NAND_DEVICE(x)
Definition: ald_ebi.h:480
ald_ebi_nand_init_t::cle_time
uint32_t cle_time
Definition: ald_ebi.h:164
IS_EBI_TCLR_TIME
#define IS_EBI_TCLR_TIME(x)
Definition: ald_ebi.h:472
IS_EBI_NAND_MEMORY_WIDTH
#define IS_EBI_NAND_MEMORY_WIDTH(x)
Definition: ald_ebi.h:443
EBI_PCTRLR_MEMORY_TYPE_NAND
Definition: ald_ebi.h:299
ald_ebi_nand_init_t::ecc
ebi_nand_ecc_t ecc
Definition: ald_ebi.h:162
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_EBI_NAND_BANK
#define IS_EBI_NAND_BANK(x)
Definition: ald_ebi.h:439
ald_ebi_nand_init_t::wait
ebi_nand_wait_feature_t wait
Definition: ald_ebi.h:160
PCTRLR_CLEAR_MASK
#define PCTRLR_CLEAR_MASK
Definition: ald_ebi.h:52


ALD User Manual: NAND-FLASH control functions

Functions
NAND-FLASH control functions
EASTSOFT ES32F3xx ALD » EBI » EBI Public Functions

NAND-FLASH control functions. More...

Collaboration diagram for NAND-FLASH control functions:

Functions

void | ald_ebi_nand_enable (EBI_NAND_TypeDef *dev, uint32_t bank)
Enable the NAND device access. More...
void | ald_ebi_nand_disable (EBI_NAND_TypeDef *dev, uint32_t bank)
Disable the NAND device access. More...
void | ald_ebi_nand_enable_it (EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it)
Enable the NAND device interrupt. More...
void | ald_ebi_nand_disable_it (EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it)
Disable the NAND device interrupt. More...
void | ald_ebi_nand_ecc_enable (EBI_NAND_TypeDef *dev, uint32_t bank)
Enables dynamically EBI_NAND ECC feature. More...
void | ald_ebi_nand_ecc_disable (EBI_NAND_TypeDef *dev, uint32_t bank)
Disables dynamically EBI_NAND ECC feature. More...
ald_status_t | ald_ebi_nand_get_ecc (EBI_NAND_TypeDef *dev, uint32_t *val, uint32_t bank, uint32_t timeout)
Disables dynamically EBI_NAND ECC feature. More...
flag_status_t | ald_ebi_nand_get_flag (EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
Get flag status of the NAND device. More...
void | ald_ebi_nand_clear_flag (EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
Clear flag status of the NAND device. More...

Detailed Description

NAND-FLASH control functions.

Function Documentation

◆ ald_ebi_nand_clear_flag()

void ald_ebi_nand_clear_flag | ( | EBI_NAND_TypeDef * | dev,
 |  | uint32_t | bank,
 |  | ebi_flag_t | flag
 | ) |  |

Clear flag status of the NAND device.

Parameters
dev | EBI_NAND Instance
bank | EBI_NAND Bank
flag EBI_NAND flag This parameter can be any combination of the following values:
  • EBI_FLAG_RISING_EDGE: Interrupt rising edge flag.
  • EBI_FLAG_LEVEL: Interrupt level edge flag.
  • EBI_FLAG_FALLING_EDGE: Interrupt falling edge flag.
  • EBI_FLAG_FEMPT: FIFO empty flag.
Return values
None

Definition at line 596 of file ald_ebi.c.

597 {
598 assert_param(IS_EBI_NAND_DEVICE(dev));
599 assert_param(IS_EBI_NAND_BANK(bank));
600
601 /* Enable ECC feature */
602 if (bank == EBI_NAND_BANK2)
603 CLEAR_BIT(dev->STAR2, flag);
604 else
605 CLEAR_BIT(dev->STAR3, flag);
606 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
IS_EBI_NAND_DEVICE
#define IS_EBI_NAND_DEVICE(x)
Definition: ald_ebi.h:480
IS_EBI_NAND_BANK
#define IS_EBI_NAND_BANK(x)
Definition: ald_ebi.h:439

◆ ald_ebi_nand_disable()

void ald_ebi_nand_disable | ( | EBI_NAND_TypeDef * | dev,
 |  | uint32_t | bank
 | ) |  |

Disable the NAND device access.

Parameters
dev | EBI_NAND Instance
bank | EBI_NAND Bank
Return values
None

Definition at line 430 of file ald_ebi.c.

431 {
432 assert_param(IS_EBI_NAND_DEVICE(dev));
433 assert_param(IS_EBI_NAND_BANK(bank));
434
435 if (bank == EBI_NAND_BANK2)
436 CLEAR_BIT(dev->PCTRLR2, EBI_PCTRLRx_MEMBKEN_MSK);
437 else
438 CLEAR_BIT(dev->PCTRLR3, EBI_PCTRLRx_MEMBKEN_MSK);
439 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
IS_EBI_NAND_DEVICE
#define IS_EBI_NAND_DEVICE(x)
Definition: ald_ebi.h:480
IS_EBI_NAND_BANK
#define IS_EBI_NAND_BANK(x)
Definition: ald_ebi.h:439

◆ ald_ebi_nand_disable_it()

void ald_ebi_nand_disable_it | ( | EBI_NAND_TypeDef * | dev,
 |  | uint32_t | bank,
 |  | ebi_it_t | it
 | ) |  |

Disable the NAND device interrupt.

Parameters
dev | EBI_NAND Instance
bank | EBI_NAND Bank
it EBI_NAND interrupt This parameter can be any combination of the following values:
  • EBI_IT_RISING_EDGE: Interrupt rising edge.
  • EBI_IT_LEVEL: Interrupt level.
  • EBI_IT_FALLING_EDGE: Interrupt falling edge.
Return values
None

Definition at line 474 of file ald_ebi.c.

475 {
476 assert_param(IS_EBI_NAND_DEVICE(dev));
477 assert_param(IS_EBI_NAND_BANK(bank));
478
479 if (bank == EBI_NAND_BANK2)
480 CLEAR_BIT(dev->STAR2, it);
481 else
482 CLEAR_BIT(dev->STAR3, it);
483 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
IS_EBI_NAND_DEVICE
#define IS_EBI_NAND_DEVICE(x)
Definition: ald_ebi.h:480
IS_EBI_NAND_BANK
#define IS_EBI_NAND_BANK(x)
Definition: ald_ebi.h:439

◆ ald_ebi_nand_ecc_disable()

void ald_ebi_nand_ecc_disable | ( | EBI_NAND_TypeDef * | dev,
 |  | uint32_t | bank
 | ) |  |

Disables dynamically EBI_NAND ECC feature.

Parameters
dev | Pointer to NAND device instance
bank | NAND bank number
Return values
None

Definition at line 509 of file ald_ebi.c.

510 {
511 assert_param(IS_EBI_NAND_DEVICE(dev));
512 assert_param(IS_EBI_NAND_BANK(bank));
513
514 /* Disable ECC feature */
515 if (bank == EBI_NAND_BANK2)
516 CLEAR_BIT(dev->PCTRLR2, EBI_PCTRLRx_ECCEN_MSK);
517 else
518 CLEAR_BIT(dev->PCTRLR3, EBI_PCTRLRx_ECCEN_MSK);
519 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
IS_EBI_NAND_DEVICE
#define IS_EBI_NAND_DEVICE(x)
Definition: ald_ebi.h:480
IS_EBI_NAND_BANK
#define IS_EBI_NAND_BANK(x)
Definition: ald_ebi.h:439

◆ ald_ebi_nand_ecc_enable()

void ald_ebi_nand_ecc_enable | ( | EBI_NAND_TypeDef * | dev,
 |  | uint32_t | bank
 | ) |  |

Enables dynamically EBI_NAND ECC feature.

Parameters
dev | Pointer to NAND device instance
bank | NAND bank number
Return values
None

Definition at line 491 of file ald_ebi.c.

492 {
493 assert_param(IS_EBI_NAND_DEVICE(dev));
494 assert_param(IS_EBI_NAND_BANK(bank));
495
496 /* Enable ECC feature */
497 if (bank == EBI_NAND_BANK2)
498 SET_BIT(dev->PCTRLR2, EBI_PCTRLRx_ECCEN_MSK);
499 else
500 SET_BIT(dev->PCTRLR3, EBI_PCTRLRx_ECCEN_MSK);
501 }
assert_param
#define assert_param(x)
Definition: type.h:88
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
IS_EBI_NAND_DEVICE
#define IS_EBI_NAND_DEVICE(x)
Definition: ald_ebi.h:480
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_EBI_NAND_BANK
#define IS_EBI_NAND_BANK(x)
Definition: ald_ebi.h:439

◆ ald_ebi_nand_enable()

void ald_ebi_nand_enable | ( | EBI_NAND_TypeDef * | dev,
 |  | uint32_t | bank
 | ) |  |

Enable the NAND device access.

Parameters
dev | EBI_NAND Instance
bank | EBI_NAND Bank
Return values
None

Definition at line 413 of file ald_ebi.c.

414 {
415 assert_param(IS_EBI_NAND_DEVICE(dev));
416 assert_param(IS_EBI_NAND_BANK(bank));
417
418 if (bank == EBI_NAND_BANK2)
419 SET_BIT(dev->PCTRLR2, EBI_PCTRLRx_MEMBKEN_MSK);
420 else
421 SET_BIT(dev->PCTRLR3, EBI_PCTRLRx_MEMBKEN_MSK);
422 }
assert_param
#define assert_param(x)
Definition: type.h:88
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
IS_EBI_NAND_DEVICE
#define IS_EBI_NAND_DEVICE(x)
Definition: ald_ebi.h:480
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_EBI_NAND_BANK
#define IS_EBI_NAND_BANK(x)
Definition: ald_ebi.h:439

◆ ald_ebi_nand_enable_it()

void ald_ebi_nand_enable_it | ( | EBI_NAND_TypeDef * | dev,
 |  | uint32_t | bank,
 |  | ebi_it_t | it
 | ) |  |

Enable the NAND device interrupt.

Parameters
dev | EBI_NAND Instance
bank | EBI_NAND Bank
it EBI_NAND interrupt This parameter can be any combination of the following values:
  • EBI_IT_RISING_EDGE: Interrupt rising edge.
  • EBI_IT_LEVEL: Interrupt level.
  • EBI_IT_FALLING_EDGE: Interrupt falling edge.
Return values
None

Definition at line 452 of file ald_ebi.c.

453 {
454 assert_param(IS_EBI_NAND_DEVICE(dev));
455 assert_param(IS_EBI_NAND_BANK(bank));
456
457 if (bank == EBI_NAND_BANK2)
458 SET_BIT(dev->STAR2, it);
459 else
460 SET_BIT(dev->STAR3, it);
461 }
assert_param
#define assert_param(x)
Definition: type.h:88
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
IS_EBI_NAND_DEVICE
#define IS_EBI_NAND_DEVICE(x)
Definition: ald_ebi.h:480
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_EBI_NAND_BANK
#define IS_EBI_NAND_BANK(x)
Definition: ald_ebi.h:439

◆ ald_ebi_nand_get_ecc()

ald_status_t ald_ebi_nand_get_ecc | ( | EBI_NAND_TypeDef * | dev,
 |  | uint32_t * | val,
 |  | uint32_t | bank,
 |  | uint32_t | timeout
 | ) |  |

Disables dynamically EBI_NAND ECC feature.

Parameters
dev | Pointer to NAND device instance
val | Pointer to ECC value
bank | NAND bank number
timeout | Timeout wait value
Return values
ALD status

Definition at line 529 of file ald_ebi.c.

530 {
531 uint32_t tick;
532
533 assert_param(IS_EBI_NAND_DEVICE(dev));
534 assert_param(IS_EBI_NAND_BANK(bank));
535
536 tick = ald_get_tick();
537
538 /* Wait until FIFO is empty */
539 while (ald_ebi_nand_get_flag(dev, bank, EBI_FLAG_FEMPT) == RESET) {
540 if (timeout != ALD_MAX_DELAY) {
541 if ((timeout == 0U) || ((ald_get_tick() - tick) > timeout))
542 return TIMEOUT;
543 }
544 }
545
546 if (bank == EBI_NAND_BANK2)
547 *val = (uint32_t)dev->ECCRESULT2;
548 else
549 *val = (uint32_t)dev->ECCRESULT3;
550
551 return OK;
552 }
EBI_FLAG_FEMPT
Definition: ald_ebi.h:318
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
ALD_MAX_DELAY
#define ALD_MAX_DELAY
Definition: utils.h:88
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
RESET
Definition: type.h:38
IS_EBI_NAND_DEVICE
#define IS_EBI_NAND_DEVICE(x)
Definition: ald_ebi.h:480
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
ald_ebi_nand_get_flag
flag_status_t ald_ebi_nand_get_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
Get flag status of the NAND device.
Definition: ald_ebi.c:568
IS_EBI_NAND_BANK
#define IS_EBI_NAND_BANK(x)
Definition: ald_ebi.h:439

◆ ald_ebi_nand_get_flag()

flag_status_t ald_ebi_nand_get_flag | ( | EBI_NAND_TypeDef * | dev,
 |  | uint32_t | bank,
 |  | ebi_flag_t | flag
 | ) |  |

Get flag status of the NAND device.

Parameters
dev | EBI_NAND Instance
bank | : EBI_NAND Bank
flag : EBI_NAND flag This parameter can be any combination of the following values:
  • EBI_FLAG_RISING_EDGE: Interrupt rising edge flag.
  • EBI_FLAG_LEVEL: Interrupt level edge flag.
  • EBI_FLAG_FALLING_EDGE: Interrupt falling edge flag.
  • EBI_FLAG_FEMPT: FIFO empty flag.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 568 of file ald_ebi.c.

569 {
570 assert_param(IS_EBI_NAND_DEVICE(dev));
571 assert_param(IS_EBI_NAND_BANK(bank));
572
573 if (bank == EBI_NAND_BANK2) {
574 if (dev->STAR2 & flag)
575 return SET;
576 } else {
577 if (dev->STAR3 & flag)
578 return SET;
579 }
580
581 return RESET;
582 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
RESET
Definition: type.h:38
IS_EBI_NAND_DEVICE
#define IS_EBI_NAND_DEVICE(x)
Definition: ald_ebi.h:480
IS_EBI_NAND_BANK
#define IS_EBI_NAND_BANK(x)
Definition: ald_ebi.h:439


ALD User Manual: LCD initialize functions

Functions
LCD initialize functions
EASTSOFT ES32F3xx ALD » EBI » EBI Public Functions

LCD initialize functions. More...

Collaboration diagram for LCD initialize functions:

Functions

void | ald_ebi_lcd_init (ebi_lcd_handle_t *hlcd)
Initializes the EBI_LCD device according to the specified control parameters in the nor_lcd_handle_t. More...
void | ald_ebi_lcd_reset (ebi_lcd_handle_t *hlcd)
Reset the EBI_LCD. More...

Detailed Description

LCD initialize functions.

Function Documentation

◆ ald_ebi_lcd_init()

void ald_ebi_lcd_init ( ebi_lcd_handle_t * hlcd )

Initializes the EBI_LCD device according to the specified control parameters in the nor_lcd_handle_t.

Parameters
hlcd Pointer to LCD device instance
Return values
None

Definition at line 621 of file ald_ebi.c.

622 {
623 assert_param(IS_EBI_LCD_DEVICE(hlcd->inst));
624 assert_param(IS_EBI_BANK_NUMBER(hlcd->init.bank));
625 assert_param(IS_EBI_HORIZONTAL_SYNCH(hlcd->init.h_polarity));
626 assert_param(IS_EBI_VERTICAL_SYNCH(hlcd->init.v_polarity));
627 assert_param(IS_EBI_DATA_ENABLE(hlcd->init.data_polarity));
628 assert_param(IS_EBI_LCD_ENABLE(hlcd->init.enable));
629 assert_param(IS_EBI_DATA_CLOCK(hlcd->init.clk_polarity));
630 assert_param(IS_EBI_LCD_DATASETUP_TIME(hlcd->init.setup));
631 assert_param(IS_EBI_HYSNC_PULSE_WIDTH(hlcd->init.h_width));
632 assert_param(IS_EBI_VSYNC_PULSE_WIDTH(hlcd->init.v_width));
633 assert_param(IS_EBI_FRAME_LINE_NUMBER(hlcd->init.nr_line));
634 assert_param(IS_EBI_FRAME_PIXEL_NUMBER(hlcd->init.nr_pixel));
635
636 MODIFY_REG(hlcd->inst->LCDCRCFGS[(hlcd->init.bank - 1)*4], LCDCTRL_CLEAR_MASK,
637 ((uint32_t)hlcd->init.h_polarity |
638 (uint32_t)hlcd->init.v_polarity |
639 hlcd->init.data_polarity |
640 hlcd->init.enable |
641 hlcd->init.clk_polarity |
642 hlcd->init.setup << EBI_LCDCTRLx_DATASETUP_POSS |
643 hlcd->init.h_width << EBI_LCDCTRLx_VSYNCWID_POSS |
644 hlcd->init.v_width << EBI_LCDCTRLx_HSYNCWID_POSS));
645
646 WRITE_REG(hlcd->inst->LCDCRCFGS[(hlcd->init.bank - 1)*4 + 1],
647 (hlcd->init.nr_line << EBI_LCDSTx_LINECNT_POSS |
648 hlcd->init.nr_pixel << EBI_LCDSTx_PXLCNT_POSS));
649 }
ebi_lcd_init_t::v_width
uint8_t v_width
Definition: ald_ebi.h:381
IS_EBI_HYSNC_PULSE_WIDTH
#define IS_EBI_HYSNC_PULSE_WIDTH(x)
Definition: ald_ebi.h:467
assert_param
#define assert_param(x)
Definition: type.h:88
IS_EBI_DATA_CLOCK
#define IS_EBI_DATA_CLOCK(x)
Definition: ald_ebi.h:464
ebi_lcd_handle_t::init
ebi_lcd_init_t init
Definition: ald_ebi.h:392
ebi_lcd_init_t::nr_line
uint16_t nr_line
Definition: ald_ebi.h:383
IS_EBI_LCD_ENABLE
#define IS_EBI_LCD_ENABLE(x)
Definition: ald_ebi.h:460
ebi_lcd_init_t::nr_pixel
uint16_t nr_pixel
Definition: ald_ebi.h:384
IS_EBI_VSYNC_PULSE_WIDTH
#define IS_EBI_VSYNC_PULSE_WIDTH(x)
Definition: ald_ebi.h:468
IS_EBI_FRAME_PIXEL_NUMBER
#define IS_EBI_FRAME_PIXEL_NUMBER(x)
Definition: ald_ebi.h:470
ebi_lcd_init_t::h_polarity
ebi_lcd_hsyncpol_t h_polarity
Definition: ald_ebi.h:374
IS_EBI_BANK_NUMBER
#define IS_EBI_BANK_NUMBER(x)
Definition: ald_ebi.h:503
IS_EBI_DATA_ENABLE
#define IS_EBI_DATA_ENABLE(x)
Definition: ald_ebi.h:458
ebi_lcd_init_t::bank
uint8_t bank
Definition: ald_ebi.h:373
IS_EBI_VERTICAL_SYNCH
#define IS_EBI_VERTICAL_SYNCH(x)
Definition: ald_ebi.h:456
ebi_lcd_init_t::enable
ebi_lcd_lcden_t enable
Definition: ald_ebi.h:377
IS_EBI_HORIZONTAL_SYNCH
#define IS_EBI_HORIZONTAL_SYNCH(x)
Definition: ald_ebi.h:454
IS_EBI_LCD_DEVICE
#define IS_EBI_LCD_DEVICE(x)
Definition: ald_ebi.h:453
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
ebi_lcd_init_t::data_polarity
ebi_lcd_denpol_t data_polarity
Definition: ald_ebi.h:376
IS_EBI_LCD_DATASETUP_TIME
#define IS_EBI_LCD_DATASETUP_TIME(x)
Definition: ald_ebi.h:466
ebi_lcd_init_t::v_polarity
ebi_lcd_vsyncpol_t v_polarity
Definition: ald_ebi.h:375
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
ebi_lcd_init_t::h_width
uint8_t h_width
Definition: ald_ebi.h:382
LCDCTRL_CLEAR_MASK
#define LCDCTRL_CLEAR_MASK
Definition: ald_ebi.h:84
ebi_lcd_init_t::setup
uint8_t setup
Definition: ald_ebi.h:380
ebi_lcd_handle_t::inst
EBI_LCD_TypeDef * inst
Definition: ald_ebi.h:391
IS_EBI_FRAME_LINE_NUMBER
#define IS_EBI_FRAME_LINE_NUMBER(x)
Definition: ald_ebi.h:469
ebi_lcd_init_t::clk_polarity
ebi_lcd_dclkpol_t clk_polarity
Definition: ald_ebi.h:378

◆ ald_ebi_lcd_reset()

void ald_ebi_lcd_reset ( ebi_lcd_handle_t * hlcd )

Reset the EBI_LCD.

Parameters
hlcd Pointer to LCD device instance
Return values
None

Definition at line 656 of file ald_ebi.c.

657 {
658 assert_param(IS_EBI_LCD_RESET(hlcd->init.reset));
659 assert_param(IS_EBI_BANK_NUMBER(hlcd->init.bank));
660
661 SET_BIT(hlcd->inst->LCDCRCFGS[(hlcd->init.bank - 1)*4], hlcd->init.reset);
662 }
assert_param
#define assert_param(x)
Definition: type.h:88
ebi_lcd_handle_t::init
ebi_lcd_init_t init
Definition: ald_ebi.h:392
ebi_lcd_init_t::reset
ebi_lcd_lcdint_t reset
Definition: ald_ebi.h:379
IS_EBI_LCD_RESET
#define IS_EBI_LCD_RESET(x)
Definition: ald_ebi.h:462
IS_EBI_BANK_NUMBER
#define IS_EBI_BANK_NUMBER(x)
Definition: ald_ebi.h:503
ebi_lcd_init_t::bank
uint8_t bank
Definition: ald_ebi.h:373
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
ebi_lcd_handle_t::inst
EBI_LCD_TypeDef * inst
Definition: ald_ebi.h:391


ALD User Manual: EBI Public Macros

Macros
EBI Public Macros
EASTSOFT ES32F3xx ALD » EBI
Collaboration diagram for EBI Public Macros:

Macros

#define | EBI_NOR_SRAM_TypeDef EBI_Bank1_TypeDef
#define | EBI_NOR_SRAM_EXTENDED_TypeDef EBI_Bank1E_TypeDef
#define | EBI_NAND_TypeDef EBI_Bank2_3_TypeDef
#define | EBI_LCD_TypeDef EBI_Bank1_LCD_TypeDef
#define | EBI_NOR_SRAM_DEVICE EBI_Bank1
#define | EBI_NOR_SRAM_EXTENDED_DEVICE EBI_Bank1E
#define | EBI_NAND_DEVICE EBI_Bank2_3
#define | EBI_LCD_DEVICE EBI_Bank1_LCD
#define | EBI_NAND_BANK2 0x00000010U
#define | EBI_NAND_BANK3 0x00000100U
#define | PCTRLR_CLEAR_MASK
#define | PMEMR_CLEAR_MASK
#define | PATTR_CLEAR_MASK
#define | BCTRLR_CLEAR_MASK
#define | BTR_CLEAR_MASK
#define | BWTR_CLEAR_MASK
#define | LCDCTRL_CLEAR_MASK

Detailed Description

Macro Definition Documentation

◆ BCTRLR_CLEAR_MASK

#define BCTRLR_CLEAR_MASK
Value:
((uint32_t)(EBI_BCTRLRx_FLASHACCEN_MSK | EBI_BCTRLRx_MUXEN_MSK | \
EBI_BCTRLRx_MEMTYP_MSK | EBI_BCTRLRx_MEMWID_MSK | \
EBI_BCTRLRx_BURSTEN_MSK | EBI_BCTRLRx_WAITPOL_MSK | \
EBI_BCTRLRx_WRAPMODE_MSK | EBI_BCTRLRx_WAITCFG_MSK | \
EBI_BCTRLRx_WREN_MSK | EBI_BCTRLRx_WAITEN_MSK | \
EBI_BCTRLRx_EXTMODEN_MSK | EBI_BCTRLRx_ASYNCWAIT_MSK | \
EBI_BCTRLRx_RWCBURSTEN_MSK))

Definition at line 66 of file ald_ebi.h.

◆ BTR_CLEAR_MASK

#define BTR_CLEAR_MASK
Value:
((uint32_t)(EBI_BTRx_ADDATASETUP_MSK | EBI_BTRx_ADDHOLD_MSK | \
EBI_BTRx_DATAHOLD_MSK | EBI_BTRx_BUSTURN_MSK | \
EBI_BTRx_CLKDIV_MSK | EBI_BTRx_DATALAT_MSK | \
EBI_BTRx_ACCMODE_MSK))

Definition at line 74 of file ald_ebi.h.

◆ BWTR_CLEAR_MASK

#define BWTR_CLEAR_MASK
Value:
((uint32_t)(EBI_BWRTRx_ADDATASETUP_MSK | EBI_BWRTRx_ADDHOLD_MSK | \
EBI_BWRTRx_DATAHOLD_MSK | EBI_BWRTRx_BUSTURN_MSK | \
EBI_BWRTRx_ACCMODE_MSK))

Definition at line 80 of file ald_ebi.h.

◆ EBI_LCD_DEVICE

#define EBI_LCD_DEVICE EBI_Bank1_LCD

Definition at line 47 of file ald_ebi.h.

◆ EBI_LCD_TypeDef

#define EBI_LCD_TypeDef EBI_Bank1_LCD_TypeDef

Definition at line 43 of file ald_ebi.h.

◆ EBI_NAND_BANK2

#define EBI_NAND_BANK2 0x00000010U

Definition at line 48 of file ald_ebi.h.

◆ EBI_NAND_BANK3

#define EBI_NAND_BANK3 0x00000100U

Definition at line 49 of file ald_ebi.h.

◆ EBI_NAND_DEVICE

#define EBI_NAND_DEVICE EBI_Bank2_3

Definition at line 46 of file ald_ebi.h.

◆ EBI_NAND_TypeDef

#define EBI_NAND_TypeDef EBI_Bank2_3_TypeDef

Definition at line 42 of file ald_ebi.h.

◆ EBI_NOR_SRAM_DEVICE

#define EBI_NOR_SRAM_DEVICE EBI_Bank1

Definition at line 44 of file ald_ebi.h.

◆ EBI_NOR_SRAM_EXTENDED_DEVICE

#define EBI_NOR_SRAM_EXTENDED_DEVICE EBI_Bank1E

Definition at line 45 of file ald_ebi.h.

◆ EBI_NOR_SRAM_EXTENDED_TypeDef

#define EBI_NOR_SRAM_EXTENDED_TypeDef EBI_Bank1E_TypeDef

Definition at line 41 of file ald_ebi.h.

◆ EBI_NOR_SRAM_TypeDef

#define EBI_NOR_SRAM_TypeDef EBI_Bank1_TypeDef

Definition at line 40 of file ald_ebi.h.

◆ LCDCTRL_CLEAR_MASK

#define LCDCTRL_CLEAR_MASK
Value:
((uint32_t)(EBI_LCDCTRLx_HSYNCPOL_POS | EBI_LCDCTRLx_VSYNCPOL_MSK | \
EBI_LCDCTRLx_DENPOL_MSK | EBI_LCDCTRLx_LCDEN_MSK | \
EBI_LCDCTRLx_LCDINT_MSK | EBI_LCDCTRLx_DCLKPOL_MSK | \
EBI_LCDCTRLx_DATASETUP_MSK))

Definition at line 84 of file ald_ebi.h.

◆ PATTR_CLEAR_MASK

#define PATTR_CLEAR_MASK
Value:
((uint32_t)(EBI_PATTRx_ATTSETUP_MSK | EBI_PATTRx_ATTWAIT_MSK | \
EBI_PATTRx_ATTHOLD_MSK | EBI_PATTRx_ATTHIZT_MSK))

Definition at line 62 of file ald_ebi.h.

◆ PCTRLR_CLEAR_MASK

#define PCTRLR_CLEAR_MASK
Value:
((uint32_t)(EBI_PCTRLRx_WAITEN_MSK | EBI_PCTRLRx_MEMBKEN_MSK | \
EBI_PCTRLRx_MEMTYP_MSK | EBI_PCTRLRx_DATBUSWID_MSK | \
EBI_PCTRLRx_ECCEN_MSK | EBI_PCTRLRx_CRDLY_MSK | \
EBI_PCTRLRx_ARDLY_MSK | EBI_PCTRLRx_ECCPSIZE_MSK))

Definition at line 52 of file ald_ebi.h.

◆ PMEMR_CLEAR_MASK

#define PMEMR_CLEAR_MASK
Value:
((uint32_t)(EBI_PMEMRx_MEMSETUP_MSK | EBI_PMEMRx_MEMWAIT_MSK | \
EBI_PMEMRx_MEMHOLD_MSK | EBI_PMEMRx_MEMHIZT_MSK))

Definition at line 58 of file ald_ebi.h.


ALD User Manual: EBI Public Types

Data Structures | Enumerations
EBI Public Types
EASTSOFT ES32F3xx ALD » EBI
Collaboration diagram for EBI Public Types:

Data Structures

struct | ald_ebi_nor_sram_timing_t
EBI NORSRAM Timing parameters structure definition. More...
struct | ald_ebi_nand_init_t
EBI NAND Configuration Structure definition. More...
struct | ald_ebi_nand_timing_t
EBI NAND Timing parameters structure definition. More...
struct | ebi_lcd_init_t
EBI LCD parameters structure definition. More...
struct | ebi_lcd_handle_t
NOR LCD handle Structure definition. More...
struct | ald_ebi_nor_sram_init_t
EBI NORSRAM Configuration Structure definition. More...

Enumerations

enum | ebi_access_mode_t { EBI_ACCESS_MODE_A = 0x0U, EBI_ACCESS_MODE_B = (0x1U << 28), EBI_ACCESS_MODE_C = (0x2U << 28), EBI_ACCESS_MODE_D = (0x3U << 28) }
EBI Access Mode. More...
enum | ebi_nand_wait_feature_t { EBI_NAND_WAIT_FEATURE_DISABLE = 0x0U, EBI_NAND_WAIT_FEATURE_ENABLE = (0x1U << 1) }
EBI_Wait_feature EBI Wait feature. More...
enum | ebi_nand_mem_bus_width_t { EBI_NAND_MEM_BUS_WIDTH_8 = 0x0U, EBI_NAND_MEM_BUS_WIDTH_16 = (0x3U << 4) }
EBI NAND Data Width. More...
enum | ebi_nand_ecc_t { EBI_NAND_ECC_DISABLE = 0U, EBI_NAND_ECC_ENABLE = (0x1U << 6) }
EBI NAND ECC STATE. More...
enum ebi_md_ecc_page_size_t {
EBI_NAND_ECC_PAGE_SIZE_256BYTE = 0U, EBI_NAND_ECC_PAGE_SIZE_512BYTE = (0x1U << 17), EBI_NAND_ECC_PAGE_SIZE_1024BYTE = (0x2U << 17), EBI_NAND_ECC_PAGE_SIZE_2048BYTE = (0x3U << 17),
EBI_NAND_ECC_PAGE_SIZE_4096BYTE = (0x4U << 17), EBI_NAND_ECC_PAGE_SIZE_8192BYTE = (0x5U << 17)
}
EBI ECC Page Size. More...
enum | ebi_data_address_mux_t { EBI_DATA_ADDRESS_MUX_DISABLE = 0x0U, EBI_DATA_ADDRESS_MUX_ENABLE = (0x1U << 1) }
EBI Data Address Bus Multiplexing. More...
enum | ebi_norsram_bank_t { EBI_NORSRAM_BANK1 = 0x0U, EBI_NORSRAM_BANK2 = 0x2U, EBI_NORSRAM_BANK3 = 0x4U, EBI_NORSRAM_BANK4 = 0x6U }
EBI NOR/SRAM Bank. More...
enum | ebi_memory_type_t { EBI_MEMORY_TYPE_SRAM = 0x0U, EBI_MEMORY_TYPE_PSRAM = (0x1U << 2), EBI_MEMORY_TYPE_NOR = (0x2U << 2) }
EBI Memory Type. More...
enum | ebi_norsram_mem_bus_width_t { EBI_NORSRAM_MEM_BUS_WIDTH_8 = 0x0U, EBI_NORSRAM_MEM_BUS_WIDTH_16 = (0x1U << 4), EBI_NORSRAM_MEM_BUS_WIDTH_32 = (0x2U << 4) }
EBI NOR/SRAM Data Width. More...
enum | ebi_norsram_flash_access_t { EBI_NORSRAM_FLASH_ACCESS_DISABLE = 0x0U, EBI_NORSRAM_FLASH_ACCESS_ENABLE = (0x1U << 6) }
EBI NOR/SRAM Flash Access. More...
enum | ebi_burst_access_mode_t { EBI_BURST_ACCESS_MODE_DISABLE = 0x0U, EBI_BURST_ACCESS_MODE_ENABLE = (0x1U << 8) }
EBI Burst Access Mode. More...
enum | ebi_wait_signal_polarity_t { EBI_WAIT_SIGNAL_POLARITY_LOW = 0x0U, EBI_WAIT_SIGNAL_POLARITY_HIGH = (0x1U << 9) }
EBI Wait Signal Polarity. More...
enum | ebi_wrap_mode_t { EBI_WRAP_MODE_DISABLE = 0x0U, EBI_WRAP_MODE_ENABLE = (0x1U << 10) }
EBI Wrap Mode. More...
enum | ebi_wait_timing_t { EBI_WAIT_TIMING_BEFORE_WS = 0x0U, EBI_WAIT_TIMING_DURING_WS = (0x1U << 11) }
EBI Wait Timing. More...
enum | ebi_write_operation_t { EBI_WRITE_OPERATION_DISABLE = 0x0U, EBI_WRITE_OPERATION_ENABLE = (0x1U << 12) }
EBI Write Operation State. More...
enum | ebi_wait_signal_t { EBI_WAIT_SIGNAL_DISABLE = 0x0U, EBI_WAIT_SIGNAL_ENABLE = (0x1U << 13) }
EBI Wait Signal. More...
enum | ebi_extended_mode_t { EBI_EXTENDED_MODE_DISABLE = 0x0U, EBI_EXTENDED_MODE_ENABLE = (0x1U << 14) }
EBI Extended Mode. More...
enum | ebi_asynchronous_wait_t { EBI_ASYNCHRONOUS_WAIT_DISABLE = 0x0U, EBI_ASYNCHRONOUS_WAIT_ENABLE = (0x1U << 15) }
EBI Asynchronous Wait. More...
enum | ebi_write_burst_t { EBI_WRITE_BURST_DISABLE = 0x0U, EBI_WRITE_BURST_ENABLE = (0x1U << 19) }
EBI Write Burst. More...
enum | ebi_pctrlr_memory_type_t { EBI_PCTRLR_MEMORY_TYPE_None = 0x0U, EBI_PCTRLR_MEMORY_TYPE_NAND = (0x1U << 3) }
EBI PCR Memory Type. More...
enum | ebi_it_t { EBI_IT_RISING_EDGE = (1U << 3), EBI_IT_LEVEL = (1U << 4), EBI_IT_FALLING_EDGE = (1U << 5) }
EBI Interrupt definition. More...
enum | ebi_flag_t { EBI_FLAG_RISING_EDGE = (1U << 0), EBI_FLAG_LEVEL = (1U << 1), EBI_FLAG_FALLING_EDGE = (1U << 2), EBI_FLAG_FEMPT = (1U << 6) }
EBI Flag definition. More...
enum | ebi_lcd_hsyncpol_t { EBI_LCD_HSYNCPOL_LOW = 0x0U, EBI_LCD_HSYNCPOL_HIGH = (0x1U << 29) }
EBI LCD_Horizontal Synch Polarity definition. More...
enum | ebi_lcd_vsyncpol_t { EBI_LCD_VSYNCPOL_LOW = 0x0U, EBI_LCD_VSYNCPOL_HIGH = (0x1U << 28) }
EBI LCD Vertical Synch Polarity definition. More...
enum | ebi_lcd_denpol_t { EBI_LCD_DENPOL_LOW = 0x0U, EBI_LCD_DENPOL_HIGH = (0x1U << 27) }
EBI LCD Data Enable Polarity definition. More...
enum | ebi_lcd_lcden_t { EBI_LCD_LCDEN_DISABLE = 0x0U, EBI_LCD_LCDEN_ENABLE = (0x1U << 26) }
EBI LCD Enable definition. More...
enum | ebi_lcd_lcdint_t { EBI_LCD_LCDINT_DISABLE = 0x0U, EBI_LCD_LCDINT_ENABLE = (0x1 << 25) }
EBI LCD Init Enable definition. More...
enum | ebi_lcd_dclkpol_t { EBI_LCD_DCLKPOL_FALLING = 0x0U, EBI_LCD_DCLKPOL_RISING = (0x1U << 24) }
EBI LCD Data Clock definition. More...

Detailed Description

Enumeration Type Documentation

◆ ebi_access_mode_t

enum ebi_access_mode_t

EBI Access Mode.

Enumerator
EBI_ACCESS_MODE_A | EBI access mode A
EBI_ACCESS_MODE_B | EBI access mode B
EBI_ACCESS_MODE_C | EBI access mode C
EBI_ACCESS_MODE_D | EBI access mode D

Definition at line 99 of file ald_ebi.h.

99 {
100 EBI_ACCESS_MODE_A = 0x0U,
101 EBI_ACCESS_MODE_B = (0x1U << 28),
102 EBI_ACCESS_MODE_C = (0x2U << 28),
103 EBI_ACCESS_MODE_D = (0x3U << 28),
104 } ebi_access_mode_t;
EBI_ACCESS_MODE_D
Definition: ald_ebi.h:103
ebi_access_mode_t
ebi_access_mode_t
EBI Access Mode.
Definition: ald_ebi.h:99
EBI_ACCESS_MODE_A
Definition: ald_ebi.h:100
EBI_ACCESS_MODE_B
Definition: ald_ebi.h:101
EBI_ACCESS_MODE_C
Definition: ald_ebi.h:102

◆ ebi_asynchronous_wait_t

enum ebi_asynchronous_wait_t

EBI Asynchronous Wait.

Enumerator
EBI_ASYNCHRONOUS_WAIT_DISABLE | Asynchronous wait disable
EBI_ASYNCHRONOUS_WAIT_ENABLE | Asynchronous wait enable

Definition at line 281 of file ald_ebi.h.

281 {
282 EBI_ASYNCHRONOUS_WAIT_DISABLE = 0x0U,
283 EBI_ASYNCHRONOUS_WAIT_ENABLE = (0x1U << 15),
284 } ebi_asynchronous_wait_t;
EBI_ASYNCHRONOUS_WAIT_ENABLE
Definition: ald_ebi.h:283
ebi_asynchronous_wait_t
ebi_asynchronous_wait_t
EBI Asynchronous Wait.
Definition: ald_ebi.h:281
EBI_ASYNCHRONOUS_WAIT_DISABLE
Definition: ald_ebi.h:282

◆ ebi_burst_access_mode_t

enum ebi_burst_access_mode_t

EBI Burst Access Mode.

Enumerator
EBI_BURST_ACCESS_MODE_DISABLE | Burst access disable
EBI_BURST_ACCESS_MODE_ENABLE | Burst access enable

Definition at line 225 of file ald_ebi.h.

225 {
226 EBI_BURST_ACCESS_MODE_DISABLE = 0x0U,
227 EBI_BURST_ACCESS_MODE_ENABLE = (0x1U << 8),
228 } ebi_burst_access_mode_t;
ebi_burst_access_mode_t
ebi_burst_access_mode_t
EBI Burst Access Mode.
Definition: ald_ebi.h:225
EBI_BURST_ACCESS_MODE_DISABLE
Definition: ald_ebi.h:226
EBI_BURST_ACCESS_MODE_ENABLE
Definition: ald_ebi.h:227

◆ ebi_data_address_mux_t

enum ebi_data_address_mux_t

EBI Data Address Bus Multiplexing.

Enumerator
EBI_DATA_ADDRESS_MUX_DISABLE | Data address mux disable
EBI_DATA_ADDRESS_MUX_ENABLE | Data address mux enable

Definition at line 181 of file ald_ebi.h.

181 {
182 EBI_DATA_ADDRESS_MUX_DISABLE = 0x0U,
183 EBI_DATA_ADDRESS_MUX_ENABLE = (0x1U << 1),
184 } ebi_data_address_mux_t;
EBI_DATA_ADDRESS_MUX_ENABLE
Definition: ald_ebi.h:183
ebi_data_address_mux_t
ebi_data_address_mux_t
EBI Data Address Bus Multiplexing.
Definition: ald_ebi.h:181
EBI_DATA_ADDRESS_MUX_DISABLE
Definition: ald_ebi.h:182

◆ ebi_extended_mode_t

enum ebi_extended_mode_t

EBI Extended Mode.

Enumerator
EBI_EXTENDED_MODE_DISABLE | EBI extended mode disable
EBI_EXTENDED_MODE_ENABLE | EBI extended mode enable

Definition at line 273 of file ald_ebi.h.

273 {
274 EBI_EXTENDED_MODE_DISABLE = 0x0U,
275 EBI_EXTENDED_MODE_ENABLE = (0x1U << 14),
276 } ebi_extended_mode_t;
EBI_EXTENDED_MODE_ENABLE
Definition: ald_ebi.h:275
EBI_EXTENDED_MODE_DISABLE
Definition: ald_ebi.h:274
ebi_extended_mode_t
ebi_extended_mode_t
EBI Extended Mode.
Definition: ald_ebi.h:273

◆ ebi_flag_t

enum ebi_flag_t

EBI Flag definition.

Enumerator
EBI_FLAG_RISING_EDGE | Rising edge flag
EBI_FLAG_LEVEL | Level flag
EBI_FLAG_FALLING_EDGE | Falling edge flag
EBI_FLAG_FEMPT | Rising edge trigger interrupt

Definition at line 314 of file ald_ebi.h.

314 {
315 EBI_FLAG_RISING_EDGE = (1U << 0),
316 EBI_FLAG_LEVEL = (1U << 1),
317 EBI_FLAG_FALLING_EDGE = (1U << 2),
318 EBI_FLAG_FEMPT = (1U << 6),
319 } ebi_flag_t;
EBI_FLAG_FEMPT
Definition: ald_ebi.h:318
EBI_FLAG_FALLING_EDGE
Definition: ald_ebi.h:317
EBI_FLAG_LEVEL
Definition: ald_ebi.h:316
EBI_FLAG_RISING_EDGE
Definition: ald_ebi.h:315
ebi_flag_t
ebi_flag_t
EBI Flag definition.
Definition: ald_ebi.h:314

◆ ebi_it_t

enum ebi_it_t

EBI Interrupt definition.

Enumerator
EBI_IT_RISING_EDGE | Rising edge trigger interrupt
EBI_IT_LEVEL | Level trigger interrupt
EBI_IT_FALLING_EDGE | Falling edge trigger interrupt

Definition at line 305 of file ald_ebi.h.

305 {
306 EBI_IT_RISING_EDGE = (1U << 3),
307 EBI_IT_LEVEL = (1U << 4),
308 EBI_IT_FALLING_EDGE = (1U << 5),
309 } ebi_it_t;
EBI_IT_RISING_EDGE
Definition: ald_ebi.h:306
ebi_it_t
ebi_it_t
EBI Interrupt definition.
Definition: ald_ebi.h:305
EBI_IT_FALLING_EDGE
Definition: ald_ebi.h:308
EBI_IT_LEVEL
Definition: ald_ebi.h:307

◆ ebi_lcd_dclkpol_t

enum ebi_lcd_dclkpol_t

EBI LCD Data Clock definition.

Enumerator
EBI_LCD_DCLKPOL_FALLING | LCD data clock falling edge
EBI_LCD_DCLKPOL_RISING | LCD data clock rising edge

Definition at line 364 of file ald_ebi.h.

364 {
365 EBI_LCD_DCLKPOL_FALLING = 0x0U,
366 EBI_LCD_DCLKPOL_RISING = (0x1U << 24),
367 } ebi_lcd_dclkpol_t;
ebi_lcd_dclkpol_t
ebi_lcd_dclkpol_t
EBI LCD Data Clock definition.
Definition: ald_ebi.h:364
EBI_LCD_DCLKPOL_RISING
Definition: ald_ebi.h:366
EBI_LCD_DCLKPOL_FALLING
Definition: ald_ebi.h:365

◆ ebi_lcd_denpol_t

enum ebi_lcd_denpol_t

EBI LCD Data Enable Polarity definition.

Enumerator
EBI_LCD_DENPOL_LOW | LCD data enable polarity low
EBI_LCD_DENPOL_HIGH | LCD data enable polarity high

Definition at line 340 of file ald_ebi.h.

340 {
341 EBI_LCD_DENPOL_LOW = 0x0U,
342 EBI_LCD_DENPOL_HIGH = (0x1U << 27),
343 } ebi_lcd_denpol_t;
ebi_lcd_denpol_t
ebi_lcd_denpol_t
EBI LCD Data Enable Polarity definition.
Definition: ald_ebi.h:340
EBI_LCD_DENPOL_LOW
Definition: ald_ebi.h:341
EBI_LCD_DENPOL_HIGH
Definition: ald_ebi.h:342

◆ ebi_lcd_hsyncpol_t

enum ebi_lcd_hsyncpol_t

EBI LCD_Horizontal Synch Polarity definition.

Enumerator
EBI_LCD_HSYNCPOL_LOW | Horizontal synch polarity low
EBI_LCD_HSYNCPOL_HIGH | Horizontal synch polarity high

Definition at line 324 of file ald_ebi.h.

324 {
325 EBI_LCD_HSYNCPOL_LOW = 0x0U,
326 EBI_LCD_HSYNCPOL_HIGH = (0x1U << 29),
327 } ebi_lcd_hsyncpol_t;
EBI_LCD_HSYNCPOL_HIGH
Definition: ald_ebi.h:326
EBI_LCD_HSYNCPOL_LOW
Definition: ald_ebi.h:325
ebi_lcd_hsyncpol_t
ebi_lcd_hsyncpol_t
EBI LCD_Horizontal Synch Polarity definition.
Definition: ald_ebi.h:324

◆ ebi_lcd_lcden_t

enum ebi_lcd_lcden_t

EBI LCD Enable definition.

Enumerator
EBI_LCD_LCDEN_DISABLE | LCD disable
EBI_LCD_LCDEN_ENABLE | LCD data enable polarity low

Definition at line 348 of file ald_ebi.h.

348 {
349 EBI_LCD_LCDEN_DISABLE = 0x0U,
350 EBI_LCD_LCDEN_ENABLE = (0x1U << 26),
351 } ebi_lcd_lcden_t;
ebi_lcd_lcden_t
ebi_lcd_lcden_t
EBI LCD Enable definition.
Definition: ald_ebi.h:348
EBI_LCD_LCDEN_DISABLE
Definition: ald_ebi.h:349
EBI_LCD_LCDEN_ENABLE
Definition: ald_ebi.h:350

◆ ebi_lcd_lcdint_t

enum ebi_lcd_lcdint_t

EBI LCD Init Enable definition.

Enumerator
EBI_LCD_LCDINT_DISABLE | LCD init disable
EBI_LCD_LCDINT_ENABLE | LCD init enable

Definition at line 356 of file ald_ebi.h.

356 {
357 EBI_LCD_LCDINT_DISABLE = 0x0U,
358 EBI_LCD_LCDINT_ENABLE = (0x1 << 25),
359 } ebi_lcd_lcdint_t;
ebi_lcd_lcdint_t
ebi_lcd_lcdint_t
EBI LCD Init Enable definition.
Definition: ald_ebi.h:356
EBI_LCD_LCDINT_DISABLE
Definition: ald_ebi.h:357
EBI_LCD_LCDINT_ENABLE
Definition: ald_ebi.h:358

◆ ebi_lcd_vsyncpol_t

enum ebi_lcd_vsyncpol_t

EBI LCD Vertical Synch Polarity definition.

Enumerator
EBI_LCD_VSYNCPOL_LOW | Vertical synch polarity low
EBI_LCD_VSYNCPOL_HIGH | Vertical synch polarity high

Definition at line 332 of file ald_ebi.h.

332 {
333 EBI_LCD_VSYNCPOL_LOW = 0x0U,
334 EBI_LCD_VSYNCPOL_HIGH = (0x1U << 28),
335 } ebi_lcd_vsyncpol_t;
EBI_LCD_VSYNCPOL_HIGH
Definition: ald_ebi.h:334
ebi_lcd_vsyncpol_t
ebi_lcd_vsyncpol_t
EBI LCD Vertical Synch Polarity definition.
Definition: ald_ebi.h:332
EBI_LCD_VSYNCPOL_LOW
Definition: ald_ebi.h:333

◆ ebi_md_ecc_page_size_t

enum ebi_md_ecc_page_size_t

EBI ECC Page Size.

Enumerator
EBI_NAND_ECC_PAGE_SIZE_256BYTE | NAND ecc page size 256 bytes
EBI_NAND_ECC_PAGE_SIZE_512BYTE | NAND ecc page size 512 bytes
EBI_NAND_ECC_PAGE_SIZE_1024BYTE | NAND ecc page size 1024 bytes
EBI_NAND_ECC_PAGE_SIZE_2048BYTE | NAND ecc page size 2048 bytes
EBI_NAND_ECC_PAGE_SIZE_4096BYTE | NAND ecc page size 4096 bytes
EBI_NAND_ECC_PAGE_SIZE_8192BYTE | NAND ecc page size 8192 bytes

Definition at line 146 of file ald_ebi.h.

146 {
147 EBI_NAND_ECC_PAGE_SIZE_256BYTE = 0U,
148 EBI_NAND_ECC_PAGE_SIZE_512BYTE = (0x1U << 17),
149 EBI_NAND_ECC_PAGE_SIZE_1024BYTE = (0x2U << 17),
150 EBI_NAND_ECC_PAGE_SIZE_2048BYTE = (0x3U << 17),
151 EBI_NAND_ECC_PAGE_SIZE_4096BYTE = (0x4U << 17),
152 EBI_NAND_ECC_PAGE_SIZE_8192BYTE = (0x5U << 17),
153 } ebi_md_ecc_page_size_t;
EBI_NAND_ECC_PAGE_SIZE_8192BYTE
Definition: ald_ebi.h:152
EBI_NAND_ECC_PAGE_SIZE_2048BYTE
Definition: ald_ebi.h:150
ebi_md_ecc_page_size_t
ebi_md_ecc_page_size_t
EBI ECC Page Size.
Definition: ald_ebi.h:146
EBI_NAND_ECC_PAGE_SIZE_512BYTE
Definition: ald_ebi.h:148
EBI_NAND_ECC_PAGE_SIZE_256BYTE
Definition: ald_ebi.h:147
EBI_NAND_ECC_PAGE_SIZE_1024BYTE
Definition: ald_ebi.h:149
EBI_NAND_ECC_PAGE_SIZE_4096BYTE
Definition: ald_ebi.h:151

◆ ebi_memory_type_t

enum ebi_memory_type_t

EBI Memory Type.

Enumerator
EBI_MEMORY_TYPE_SRAM | Memory tyepe SRAM
EBI_MEMORY_TYPE_PSRAM | Memory tyepe PSRAM
EBI_MEMORY_TYPE_NOR | Memory tyepe NOR

Definition at line 199 of file ald_ebi.h.

199 {
200 EBI_MEMORY_TYPE_SRAM = 0x0U,
201 EBI_MEMORY_TYPE_PSRAM = (0x1U << 2),
202 EBI_MEMORY_TYPE_NOR = (0x2U << 2),
203 } ebi_memory_type_t;
EBI_MEMORY_TYPE_PSRAM
Definition: ald_ebi.h:201
EBI_MEMORY_TYPE_SRAM
Definition: ald_ebi.h:200
EBI_MEMORY_TYPE_NOR
Definition: ald_ebi.h:202
ebi_memory_type_t
ebi_memory_type_t
EBI Memory Type.
Definition: ald_ebi.h:199

◆ ebi_nand_ecc_t

enum ebi_nand_ecc_t

EBI NAND ECC STATE.

Enumerator
EBI_NAND_ECC_DISABLE | NAND ecc disable
EBI_NAND_ECC_ENABLE | NAND ecc enable

Definition at line 138 of file ald_ebi.h.

138 {
139 EBI_NAND_ECC_DISABLE = 0U,
140 EBI_NAND_ECC_ENABLE = (0x1U << 6),
141 } ebi_nand_ecc_t;
EBI_NAND_ECC_DISABLE
Definition: ald_ebi.h:139
EBI_NAND_ECC_ENABLE
Definition: ald_ebi.h:140
ebi_nand_ecc_t
ebi_nand_ecc_t
EBI NAND ECC STATE.
Definition: ald_ebi.h:138

◆ ebi_nand_mem_bus_width_t

enum ebi_nand_mem_bus_width_t

EBI NAND Data Width.

Enumerator
EBI_NAND_MEM_BUS_WIDTH_8 | NAND mem bus width 8-bits
EBI_NAND_MEM_BUS_WIDTH_16 | NAND mem bus width 16-bits

Definition at line 130 of file ald_ebi.h.

130 {
131 EBI_NAND_MEM_BUS_WIDTH_8 = 0x0U,
132 EBI_NAND_MEM_BUS_WIDTH_16 = (0x3U << 4),
133 } ebi_nand_mem_bus_width_t;
ebi_nand_mem_bus_width_t
ebi_nand_mem_bus_width_t
EBI NAND Data Width.
Definition: ald_ebi.h:130
EBI_NAND_MEM_BUS_WIDTH_16
Definition: ald_ebi.h:132
EBI_NAND_MEM_BUS_WIDTH_8
Definition: ald_ebi.h:131

◆ ebi_nand_wait_feature_t

enum ebi_nand_wait_feature_t

EBI_Wait_feature EBI Wait feature.

Enumerator
EBI_NAND_WAIT_FEATURE_DISABLE | NAND wait feature disable
EBI_NAND_WAIT_FEATURE_ENABLE | NAND wait feature enable

Definition at line 122 of file ald_ebi.h.

122 {
123 EBI_NAND_WAIT_FEATURE_DISABLE = 0x0U,
124 EBI_NAND_WAIT_FEATURE_ENABLE = (0x1U << 1),
125 } ebi_nand_wait_feature_t;
EBI_NAND_WAIT_FEATURE_ENABLE
Definition: ald_ebi.h:124
EBI_NAND_WAIT_FEATURE_DISABLE
Definition: ald_ebi.h:123
ebi_nand_wait_feature_t
ebi_nand_wait_feature_t
EBI_Wait_feature EBI Wait feature.
Definition: ald_ebi.h:122

◆ ebi_norsram_bank_t

enum ebi_norsram_bank_t

EBI NOR/SRAM Bank.

Enumerator
EBI_NORSRAM_BANK1 | Norsram bank 1
EBI_NORSRAM_BANK2 | Norsram bank 2
EBI_NORSRAM_BANK3 | Norsram bank 3
EBI_NORSRAM_BANK4 | Norsram bank 4

Definition at line 189 of file ald_ebi.h.

189 {
190 EBI_NORSRAM_BANK1 = 0x0U,
191 EBI_NORSRAM_BANK2 = 0x2U,
192 EBI_NORSRAM_BANK3 = 0x4U,
193 EBI_NORSRAM_BANK4 = 0x6U,
194 } ebi_norsram_bank_t;
EBI_NORSRAM_BANK2
Definition: ald_ebi.h:191
EBI_NORSRAM_BANK3
Definition: ald_ebi.h:192
EBI_NORSRAM_BANK4
Definition: ald_ebi.h:193
ebi_norsram_bank_t
ebi_norsram_bank_t
EBI NOR/SRAM Bank.
Definition: ald_ebi.h:189
EBI_NORSRAM_BANK1
Definition: ald_ebi.h:190

◆ ebi_norsram_flash_access_t

enum ebi_norsram_flash_access_t

EBI NOR/SRAM Flash Access.

Enumerator
EBI_NORSRAM_FLASH_ACCESS_DISABLE | Norsram flash access disable
EBI_NORSRAM_FLASH_ACCESS_ENABLE | Norsram flash access enable

Definition at line 217 of file ald_ebi.h.

217 {
218 EBI_NORSRAM_FLASH_ACCESS_DISABLE = 0x0U,
219 EBI_NORSRAM_FLASH_ACCESS_ENABLE = (0x1U << 6),
220 } ebi_norsram_flash_access_t;
EBI_NORSRAM_FLASH_ACCESS_ENABLE
Definition: ald_ebi.h:219
EBI_NORSRAM_FLASH_ACCESS_DISABLE
Definition: ald_ebi.h:218
ebi_norsram_flash_access_t
ebi_norsram_flash_access_t
EBI NOR/SRAM Flash Access.
Definition: ald_ebi.h:217

◆ ebi_norsram_mem_bus_width_t

enum ebi_norsram_mem_bus_width_t

EBI NOR/SRAM Data Width.

Enumerator
EBI_NORSRAM_MEM_BUS_WIDTH_8 | Norsram Memory width 8-bits
EBI_NORSRAM_MEM_BUS_WIDTH_16 | Norsram Memory width 16-bits
EBI_NORSRAM_MEM_BUS_WIDTH_32 | Norsram Memory width 32-bits

Definition at line 208 of file ald_ebi.h.

208 {
209 EBI_NORSRAM_MEM_BUS_WIDTH_8 = 0x0U,
210 EBI_NORSRAM_MEM_BUS_WIDTH_16 = (0x1U << 4),
211 EBI_NORSRAM_MEM_BUS_WIDTH_32 = (0x2U << 4),
212 } ebi_norsram_mem_bus_width_t;
ebi_norsram_mem_bus_width_t
ebi_norsram_mem_bus_width_t
EBI NOR/SRAM Data Width.
Definition: ald_ebi.h:208
EBI_NORSRAM_MEM_BUS_WIDTH_8
Definition: ald_ebi.h:209
EBI_NORSRAM_MEM_BUS_WIDTH_32
Definition: ald_ebi.h:211
EBI_NORSRAM_MEM_BUS_WIDTH_16
Definition: ald_ebi.h:210

◆ ebi_pctrlr_memory_type_t

enum ebi_pctrlr_memory_type_t

EBI PCR Memory Type.

Enumerator
EBI_PCTRLR_MEMORY_TYPE_None | PCR memory type none
EBI_PCTRLR_MEMORY_TYPE_NAND | PCR memory type nand

Definition at line 297 of file ald_ebi.h.

297 {
298 EBI_PCTRLR_MEMORY_TYPE_None = 0x0U,
299 EBI_PCTRLR_MEMORY_TYPE_NAND = (0x1U << 3),
300 } ebi_pctrlr_memory_type_t;
EBI_PCTRLR_MEMORY_TYPE_None
Definition: ald_ebi.h:298
ebi_pctrlr_memory_type_t
ebi_pctrlr_memory_type_t
EBI PCR Memory Type.
Definition: ald_ebi.h:297
EBI_PCTRLR_MEMORY_TYPE_NAND
Definition: ald_ebi.h:299

◆ ebi_wait_signal_polarity_t

enum ebi_wait_signal_polarity_t

EBI Wait Signal Polarity.

Enumerator
EBI_WAIT_SIGNAL_POLARITY_LOW | Wait signal polarity low
EBI_WAIT_SIGNAL_POLARITY_HIGH | Wait signal polarity high

Definition at line 233 of file ald_ebi.h.

233 {
234 EBI_WAIT_SIGNAL_POLARITY_LOW = 0x0U,
235 EBI_WAIT_SIGNAL_POLARITY_HIGH = (0x1U << 9),
236 } ebi_wait_signal_polarity_t;
ebi_wait_signal_polarity_t
ebi_wait_signal_polarity_t
EBI Wait Signal Polarity.
Definition: ald_ebi.h:233
EBI_WAIT_SIGNAL_POLARITY_HIGH
Definition: ald_ebi.h:235
EBI_WAIT_SIGNAL_POLARITY_LOW
Definition: ald_ebi.h:234

◆ ebi_wait_signal_t

enum ebi_wait_signal_t

EBI Wait Signal.

Enumerator
EBI_WAIT_SIGNAL_DISABLE | Wait signal disable
EBI_WAIT_SIGNAL_ENABLE | Wait signal enable

Definition at line 265 of file ald_ebi.h.

265 {
266 EBI_WAIT_SIGNAL_DISABLE = 0x0U,
267 EBI_WAIT_SIGNAL_ENABLE = (0x1U << 13),
268 } ebi_wait_signal_t;
EBI_WAIT_SIGNAL_ENABLE
Definition: ald_ebi.h:267
EBI_WAIT_SIGNAL_DISABLE
Definition: ald_ebi.h:266
ebi_wait_signal_t
ebi_wait_signal_t
EBI Wait Signal.
Definition: ald_ebi.h:265

◆ ebi_wait_timing_t

enum ebi_wait_timing_t

EBI Wait Timing.

Enumerator
EBI_WAIT_TIMING_BEFORE_WS | Wait timing before ws
EBI_WAIT_TIMING_DURING_WS | Wait timing during ws

Definition at line 249 of file ald_ebi.h.

249 {
250 EBI_WAIT_TIMING_BEFORE_WS = 0x0U,
251 EBI_WAIT_TIMING_DURING_WS = (0x1U << 11),
252 } ebi_wait_timing_t;
EBI_WAIT_TIMING_DURING_WS
Definition: ald_ebi.h:251
EBI_WAIT_TIMING_BEFORE_WS
Definition: ald_ebi.h:250
ebi_wait_timing_t
ebi_wait_timing_t
EBI Wait Timing.
Definition: ald_ebi.h:249

◆ ebi_wrap_mode_t

enum ebi_wrap_mode_t

EBI Wrap Mode.

Enumerator
EBI_WRAP_MODE_DISABLE | Wrap mode disable
EBI_WRAP_MODE_ENABLE | Wrap mode enable

Definition at line 241 of file ald_ebi.h.

241 {
242 EBI_WRAP_MODE_DISABLE = 0x0U,
243 EBI_WRAP_MODE_ENABLE = (0x1U << 10),
244 } ebi_wrap_mode_t;
ebi_wrap_mode_t
ebi_wrap_mode_t
EBI Wrap Mode.
Definition: ald_ebi.h:241
EBI_WRAP_MODE_ENABLE
Definition: ald_ebi.h:243
EBI_WRAP_MODE_DISABLE
Definition: ald_ebi.h:242

◆ ebi_write_burst_t

enum ebi_write_burst_t

EBI Write Burst.

Enumerator
EBI_WRITE_BURST_DISABLE | Write burst disable
EBI_WRITE_BURST_ENABLE | Write burst enable

Definition at line 289 of file ald_ebi.h.

289 {
290 EBI_WRITE_BURST_DISABLE = 0x0U,
291 EBI_WRITE_BURST_ENABLE = (0x1U << 19),
292 } ebi_write_burst_t;
EBI_WRITE_BURST_DISABLE
Definition: ald_ebi.h:290
ebi_write_burst_t
ebi_write_burst_t
EBI Write Burst.
Definition: ald_ebi.h:289
EBI_WRITE_BURST_ENABLE
Definition: ald_ebi.h:291

◆ ebi_write_operation_t

enum ebi_write_operation_t

EBI Write Operation State.

Enumerator
EBI_WRITE_OPERATION_DISABLE | Write operation disable
EBI_WRITE_OPERATION_ENABLE | Write operation enable

Definition at line 257 of file ald_ebi.h.

257 {
258 EBI_WRITE_OPERATION_DISABLE = 0x0U,
259 EBI_WRITE_OPERATION_ENABLE = (0x1U << 12),
260 } ebi_write_operation_t;
EBI_WRITE_OPERATION_ENABLE
Definition: ald_ebi.h:259
ebi_write_operation_t
ebi_write_operation_t
EBI Write Operation State.
Definition: ald_ebi.h:257
EBI_WRITE_OPERATION_DISABLE
Definition: ald_ebi.h:258


ALD User Manual: ald_ebi_nor_sram_timing_t Struct Reference

Data Fields
ald_ebi_nor_sram_timing_t Struct Reference
EASTSOFT ES32F3xx ALD » EBI » EBI Public Types

EBI NORSRAM Timing parameters structure definition. More...

#include <ald_ebi.h>

Data Fields

uint32_t | addr_setup
uint32_t | addr_hold
uint32_t | data_setup
uint32_t | bus_dur
uint32_t | div
uint32_t | latency
ebi_access_mode_t mode

Detailed Description

EBI NORSRAM Timing parameters structure definition.

Definition at line 109 of file ald_ebi.h.

Field Documentation

◆ addr_hold

uint32_t addr_hold

Address hold HCLK cycles number, the value between 0 and 15

Definition at line 111 of file ald_ebi.h.

◆ addr_setup

uint32_t addr_setup

Address setup HCLK cycles number, the value between 0 and 15

Definition at line 110 of file ald_ebi.h.

◆ bus_dur

uint32_t bus_dur

Bus turnaround duration HCLK cycles, the value between 0 and 15

Definition at line 113 of file ald_ebi.h.

◆ data_setup

uint32_t data_setup

Data setup HCLK cycles number, the value between 1 and 255

Definition at line 112 of file ald_ebi.h.

◆ div

uint32_t div

Defines the period of CLK clock signal, the value between 2 and 16

Definition at line 114 of file ald_ebi.h.

◆ latency

uint32_t latency

Issue clock cycles before getting the first data, the value between 2 and 17

Definition at line 115 of file ald_ebi.h.

◆ mode

ebi_access_mode_t mode

Specifies the asynchronous access mode

Definition at line 116 of file ald_ebi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_ebi.h


ALD User Manual: ald_ebi_nand_init_t Struct Reference

Data Fields
ald_ebi_nand_init_t Struct Reference
EASTSOFT ES32F3xx ALD » EBI » EBI Public Types

EBI NAND Configuration Structure definition. More...

#include <ald_ebi.h>

Data Fields

uint32_t | bank
ebi_nand_wait_feature_t wait
ebi_nand_mem_bus_width_t width
ebi_nand_ecc_t ecc
ebi_md_ecc_page_size_t size
uint32_t | cle_time
uint32_t | ale_time

Detailed Description

EBI NAND Configuration Structure definition.

Definition at line 158 of file ald_ebi.h.

Field Documentation

◆ ale_time

uint32_t ale_time

Number of HCLK cycles between ALE low and RE low

Definition at line 165 of file ald_ebi.h.

◆ bank

uint32_t bank

Specifies the NAND memory device that will be used

Definition at line 159 of file ald_ebi.h.

◆ cle_time

uint32_t cle_time

Number of HCLK cycles between CLE low and RE low, the value between 0 and 255

Definition at line 164 of file ald_ebi.h.

◆ ecc

ebi_nand_ecc_t ecc

Enables or disables the ECC computation

Definition at line 162 of file ald_ebi.h.

◆ size

ebi_md_ecc_page_size_t size

Defines the page size for the extended ECC

Definition at line 163 of file ald_ebi.h.

◆ wait

ebi_nand_wait_feature_t wait

Enables or disables the Wait feature for the NAND Memory device

Definition at line 160 of file ald_ebi.h.

◆ width

ebi_nand_mem_bus_width_t width

Specifies the external memory device width

Definition at line 161 of file ald_ebi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_ebi.h


ALD User Manual: ald_ebi_nand_timing_t Struct Reference

Data Fields
ald_ebi_nand_timing_t Struct Reference
EASTSOFT ES32F3xx ALD » EBI » EBI Public Types

EBI NAND Timing parameters structure definition. More...

#include <ald_ebi.h>

Data Fields

uint32_t | time
uint32_t | wait_time
uint32_t | hold_time
uint32_t | hiz_time

Detailed Description

EBI NAND Timing parameters structure definition.

Definition at line 171 of file ald_ebi.h.

Field Documentation

◆ hiz_time

uint32_t hiz_time

Number of HCLK cycles data bus is kept in HiZ, the value between 0 and 255

Definition at line 175 of file ald_ebi.h.

◆ hold_time

uint32_t hold_time

Number of HCLK cycles to hold address or data, the value between 0 and 255

Definition at line 174 of file ald_ebi.h.

◆ time

uint32_t time

Number of cycles to setup address, the value between 0 and 255

Definition at line 172 of file ald_ebi.h.

◆ wait_time

uint32_t wait_time

Number of HCLK cycles to assert the command ,the value between 0 and 255

Definition at line 173 of file ald_ebi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_ebi.h


ALD User Manual: ebi_lcd_init_t Struct Reference

Data Fields
ebi_lcd_init_t Struct Reference
EASTSOFT ES32F3xx ALD » EBI » EBI Public Types

EBI LCD parameters structure definition. More...

#include <ald_ebi.h>

Data Fields

uint8_t | bank
ebi_lcd_hsyncpol_t h_polarity
ebi_lcd_vsyncpol_t v_polarity
ebi_lcd_denpol_t data_polarity
ebi_lcd_lcden_t enable
ebi_lcd_dclkpol_t clk_polarity
ebi_lcd_lcdint_t reset
uint8_t | setup
uint8_t | v_width
uint8_t | h_width
uint16_t | nr_line
uint16_t | nr_pixel

Detailed Description

EBI LCD parameters structure definition.

Definition at line 372 of file ald_ebi.h.

Field Documentation

◆ bank

uint8_t bank

Specifies the NORSRAM memory device

Definition at line 373 of file ald_ebi.h.

◆ clk_polarity

ebi_lcd_dclkpol_t clk_polarity

Data clock polarity

Definition at line 378 of file ald_ebi.h.

◆ data_polarity

ebi_lcd_denpol_t data_polarity

Data enable polarity

Definition at line 376 of file ald_ebi.h.

◆ enable

ebi_lcd_lcden_t enable

LCD enable

Definition at line 377 of file ald_ebi.h.

◆ h_polarity

ebi_lcd_hsyncpol_t h_polarity

Horizontal sync polarity

Definition at line 374 of file ald_ebi.h.

◆ h_width

uint8_t h_width

Hsync puluse width

Definition at line 382 of file ald_ebi.h.

◆ nr_line

uint16_t nr_line

Frame line number

Definition at line 383 of file ald_ebi.h.

◆ nr_pixel

uint16_t nr_pixel

Frame pixel number

Definition at line 384 of file ald_ebi.h.

◆ reset

ebi_lcd_lcdint_t reset

LCD Reset

Definition at line 379 of file ald_ebi.h.

◆ setup

uint8_t setup

Data setup time

Definition at line 380 of file ald_ebi.h.

◆ v_polarity

ebi_lcd_vsyncpol_t v_polarity

Vertical sync polarity

Definition at line 375 of file ald_ebi.h.

◆ v_width

uint8_t v_width

Vsync pulse width

Definition at line 381 of file ald_ebi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_ebi.h


ALD User Manual: ebi_lcd_handle_t Struct Reference

Data Fields
ebi_lcd_handle_t Struct Reference
EASTSOFT ES32F3xx ALD » EBI » EBI Public Types

NOR LCD handle Structure definition. More...

#include <ald_ebi.h>

Collaboration diagram for ebi_lcd_handle_t:
[legend]

Data Fields

EBI_LCD_TypeDef * inst
ebi_lcd_init_t init

Detailed Description

NOR LCD handle Structure definition.

Definition at line 390 of file ald_ebi.h.

Field Documentation

◆ init

ebi_lcd_init_t init

Definition at line 392 of file ald_ebi.h.

◆ inst

EBI_LCD_TypeDef* inst

Definition at line 391 of file ald_ebi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_ebi.h


ALD User Manual: ald_ebi_nor_sram_init_t Struct Reference

Data Fields
ald_ebi_nor_sram_init_t Struct Reference
EASTSOFT ES32F3xx ALD » EBI » EBI Public Types

EBI NORSRAM Configuration Structure definition. More...

#include <ald_ebi.h>

Data Fields

uint32_t bank
ebi_data_address_mux_t mux
ebi_memory_type_t type
ebi_norsram_mem_bus_width_t width
ebi_burst_access_mode_t acc_mode
ebi_wait_signal_polarity_t polarity
ebi_wrap_mode_t wrap_mode
ebi_wait_timing_t active
ebi_write_operation_t write
ebi_wait_signal_t signal
ebi_extended_mode_t ext_mode
ebi_asynchronous_wait_t wait
ebi_write_burst_t burst

Detailed Description

EBI NORSRAM Configuration Structure definition.

Definition at line 398 of file ald_ebi.h.

Field Documentation

◆ acc_mode

ebi_burst_access_mode_t acc_mode

Enables or disables the burst access mode for Flash memory

Definition at line 403 of file ald_ebi.h.

◆ active

ebi_wait_timing_t active

Specifies if the wait signal is asserted, only in burst mode

Definition at line 406 of file ald_ebi.h.

◆ bank

uint32_t bank

Specifies the NORSRAM memory device, the value can be one of 0 ~ 3

Definition at line 399 of file ald_ebi.h.

◆ burst

ebi_write_burst_t burst

Enables or disables the write burst operation

Definition at line 411 of file ald_ebi.h.

◆ ext_mode

ebi_extended_mode_t ext_mode

Enables or disables the extended mode

Definition at line 409 of file ald_ebi.h.

◆ mux

ebi_data_address_mux_t mux

Address and data values are multiplexed or not

Definition at line 400 of file ald_ebi.h.

◆ polarity

ebi_wait_signal_polarity_t polarity

Wait signal polarity, valid only in burst mode

Definition at line 404 of file ald_ebi.h.

◆ signal

ebi_wait_signal_t signal

Enables or disables the wait state insertion, only in burst mode

Definition at line 408 of file ald_ebi.h.

◆ type

ebi_memory_type_t type

Specifies the type of external memory

Definition at line 401 of file ald_ebi.h.

◆ wait

ebi_asynchronous_wait_t wait

Enables or disables wait signal during asynchronous transfers

Definition at line 410 of file ald_ebi.h.

◆ width

ebi_norsram_mem_bus_width_t width

Specifies the external memory device width

Definition at line 402 of file ald_ebi.h.

◆ wrap_mode

ebi_wrap_mode_t wrap_mode

Enables or disables the Wrapped burst access mode, only in burst mode

Definition at line 405 of file ald_ebi.h.

◆ write

ebi_write_operation_t write

Enables or disables the write operation

Definition at line 407 of file ald_ebi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_ebi.h


ALD User Manual: EBI Private Macros

Macros
EBI Private Macros
EASTSOFT ES32F3xx ALD » EBI
Collaboration diagram for EBI Private Macros:

Macros

#define | IS_EBI_NORSRAM_BANK(x)
#define | IS_EBI_MUX(x)
#define | IS_EBI_MEMORY(x)
#define | IS_EBI_NORSRAM_MEMORY_WIDTH(x)
#define | IS_EBI_WRITE_BURST(x)
#define | IS_EBI_ACCESS_MODE(x)
#define | IS_EBI_NAND_BANK(x)
#define | IS_EBI_WAIT_FEATURE(x)
#define | IS_EBI_NAND_MEMORY_WIDTH(x)
#define | IS_EBI_ECC_STATE(x)
#define | IS_EBI_ECCPAGE_SIZE(x)
#define | IS_EBI_LCD_DEVICE(x) ((x) == EBI_LCD_DEVICE)
#define | IS_EBI_HORIZONTAL_SYNCH(x)
#define | IS_EBI_VERTICAL_SYNCH(x)
#define | IS_EBI_DATA_ENABLE(x)
#define | IS_EBI_LCD_ENABLE(x)
#define | IS_EBI_LCD_RESET(x)
#define | IS_EBI_DATA_CLOCK(x)
#define | IS_EBI_LCD_DATASETUP_TIME(x) ((x) < 255U)
#define | IS_EBI_HYSNC_PULSE_WIDTH(x) ((x) < 255U)
#define | IS_EBI_VSYNC_PULSE_WIDTH(x) ((x) < 255U)
#define | IS_EBI_FRAME_LINE_NUMBER(x) (((x) >= 1U) && ((x) < 65535))
#define | IS_EBI_FRAME_PIXEL_NUMBER(x) (((x) >= 1U) && ((x) < 65535))
#define | IS_EBI_TCLR_TIME(x) ((x) <= 255U)
#define | IS_EBI_TAR_TIME(x) ((x) <= 255U)
#define | IS_EBI_SETUP_TIME(x) ((x) <= 255U)
#define | IS_EBI_WAIT_TIME(x) ((x) <= 255U)
#define | IS_EBI_HOLD_TIME(x) ((x) <= 255U)
#define | IS_EBI_HIZ_TIME(x) ((x) <= 255U)
#define | IS_EBI_NORSRAM_DEVICE(x) ((x) == EBI_NOR_SRAM_DEVICE)
#define | IS_EBI_NORSRAM_EXTENDED_DEVICE(x) ((x) == EBI_NOR_SRAM_EXTENDED_DEVICE)
#define | IS_EBI_NAND_DEVICE(x) ((x) == EBI_NAND_DEVICE)
#define | IS_EBI_BURSTMODE(x)
#define | IS_EBI_WAIT_POLARITY(x)
#define | IS_EBI_WRAP_MODE(x)
#define | IS_EBI_WAIT_SIGNAL_ACTIVE(x)
#define | IS_EBI_WRITE_OPERATION(x)
#define | IS_EBI_WAITE_SIGNAL(x)
#define | IS_EBI_EXTENDED_MODE(x)
#define | IS_EBI_ASYNWAIT(x)
#define | IS_EBI_CLK_DIV(x) (((x) >= 1U) && ((x) <= 16U))
#define | IS_EBI_DATA_LATENCY(x) (((x) >= 1U) && ((x) <= 17U))
#define | IS_EBI_ADDRESS_SETUP_TIME(x) ((x) <= 15U)
#define | IS_EBI_ADDRESS_HOLD_TIME(x) (((x) > 0U) && ((x) <= 15U))
#define | IS_EBI_DATASETUP_TIME(x) (((x) > 0U) && ((x) <= 255U))
#define | IS_EBI_TURNAROUND_TIME(x) ((x) <= 15U)
#define | IS_EBI_BANK_NUMBER(x) (((x) > 0U) && ((x) <= 4U))

Detailed Description

Macro Definition Documentation

◆ IS_EBI_ACCESS_MODE

#define IS_EBI_ACCESS_MODE ( x )
Value:
(((x) == EBI_ACCESS_MODE_A) || \
((x) == EBI_ACCESS_MODE_B) || \
((x) == EBI_ACCESS_MODE_C) || \
((x) == EBI_ACCESS_MODE_D))
EBI_ACCESS_MODE_D
Definition: ald_ebi.h:103
EBI_ACCESS_MODE_A
Definition: ald_ebi.h:100
EBI_ACCESS_MODE_B
Definition: ald_ebi.h:101
EBI_ACCESS_MODE_C
Definition: ald_ebi.h:102

Definition at line 435 of file ald_ebi.h.

◆ IS_EBI_ADDRESS_HOLD_TIME

#define IS_EBI_ADDRESS_HOLD_TIME ( x ) (((x) > 0U) && ((x) <= 15U))

Definition at line 500 of file ald_ebi.h.

◆ IS_EBI_ADDRESS_SETUP_TIME

#define IS_EBI_ADDRESS_SETUP_TIME ( x ) ((x) <= 15U)

Definition at line 499 of file ald_ebi.h.

◆ IS_EBI_ASYNWAIT

#define IS_EBI_ASYNWAIT ( x )
Value:
(((x) == EBI_ASYNCHRONOUS_WAIT_DISABLE) || \
((x) == EBI_ASYNCHRONOUS_WAIT_ENABLE))
EBI_ASYNCHRONOUS_WAIT_ENABLE
Definition: ald_ebi.h:283
EBI_ASYNCHRONOUS_WAIT_DISABLE
Definition: ald_ebi.h:282

Definition at line 495 of file ald_ebi.h.

◆ IS_EBI_BANK_NUMBER

#define IS_EBI_BANK_NUMBER ( x ) (((x) > 0U) && ((x) <= 4U))

Definition at line 503 of file ald_ebi.h.

◆ IS_EBI_BURSTMODE

#define IS_EBI_BURSTMODE ( x )
Value:
(((x) == EBI_BURST_ACCESS_MODE_DISABLE) || \
((x) == EBI_BURST_ACCESS_MODE_ENABLE))
EBI_BURST_ACCESS_MODE_DISABLE
Definition: ald_ebi.h:226
EBI_BURST_ACCESS_MODE_ENABLE
Definition: ald_ebi.h:227

Definition at line 481 of file ald_ebi.h.

◆ IS_EBI_CLK_DIV

#define IS_EBI_CLK_DIV ( x ) (((x) >= 1U) && ((x) <= 16U))

Definition at line 497 of file ald_ebi.h.

◆ IS_EBI_DATA_CLOCK

#define IS_EBI_DATA_CLOCK ( x )
Value:
(((x) == EBI_LCD_DCLKPOL_FALLING) || \
((x) == EBI_LCD_DCLKPOL_RISING))
EBI_LCD_DCLKPOL_RISING
Definition: ald_ebi.h:366
EBI_LCD_DCLKPOL_FALLING
Definition: ald_ebi.h:365

Definition at line 464 of file ald_ebi.h.

◆ IS_EBI_DATA_ENABLE

#define IS_EBI_DATA_ENABLE ( x )
Value:
(((x) == EBI_LCD_DENPOL_LOW) || \
((x) == EBI_LCD_DENPOL_HIGH))
EBI_LCD_DENPOL_LOW
Definition: ald_ebi.h:341
EBI_LCD_DENPOL_HIGH
Definition: ald_ebi.h:342

Definition at line 458 of file ald_ebi.h.

◆ IS_EBI_DATA_LATENCY

#define IS_EBI_DATA_LATENCY ( x ) (((x) >= 1U) && ((x) <= 17U))

Definition at line 498 of file ald_ebi.h.

◆ IS_EBI_DATASETUP_TIME

#define IS_EBI_DATASETUP_TIME ( x ) (((x) > 0U) && ((x) <= 255U))

Definition at line 501 of file ald_ebi.h.

◆ IS_EBI_ECC_STATE

#define IS_EBI_ECC_STATE ( x )
Value:
(((x) == EBI_NAND_ECC_DISABLE) || \
((x) == EBI_NAND_ECC_ENABLE))
EBI_NAND_ECC_DISABLE
Definition: ald_ebi.h:139
EBI_NAND_ECC_ENABLE
Definition: ald_ebi.h:140

Definition at line 445 of file ald_ebi.h.

◆ IS_EBI_ECCPAGE_SIZE

#define IS_EBI_ECCPAGE_SIZE ( x )
Value:
(((x) == EBI_NAND_ECC_PAGE_SIZE_256BYTE) || \
((x) == EBI_NAND_ECC_PAGE_SIZE_512BYTE) || \
((x) == EBI_NAND_ECC_PAGE_SIZE_1024BYTE) || \
((x) == EBI_NAND_ECC_PAGE_SIZE_2048BYTE) || \
((x) == EBI_NAND_ECC_PAGE_SIZE_4096BYTE) || \
((x) == EBI_NAND_ECC_PAGE_SIZE_8192BYTE))
EBI_NAND_ECC_PAGE_SIZE_8192BYTE
Definition: ald_ebi.h:152
EBI_NAND_ECC_PAGE_SIZE_2048BYTE
Definition: ald_ebi.h:150
EBI_NAND_ECC_PAGE_SIZE_512BYTE
Definition: ald_ebi.h:148
EBI_NAND_ECC_PAGE_SIZE_256BYTE
Definition: ald_ebi.h:147
EBI_NAND_ECC_PAGE_SIZE_1024BYTE
Definition: ald_ebi.h:149
EBI_NAND_ECC_PAGE_SIZE_4096BYTE
Definition: ald_ebi.h:151

Definition at line 447 of file ald_ebi.h.

◆ IS_EBI_EXTENDED_MODE

#define IS_EBI_EXTENDED_MODE ( x )
Value:
(((x) == EBI_EXTENDED_MODE_DISABLE) || \
((x) == EBI_EXTENDED_MODE_ENABLE))
EBI_EXTENDED_MODE_ENABLE
Definition: ald_ebi.h:275
EBI_EXTENDED_MODE_DISABLE
Definition: ald_ebi.h:274

Definition at line 493 of file ald_ebi.h.

◆ IS_EBI_FRAME_LINE_NUMBER

#define IS_EBI_FRAME_LINE_NUMBER ( x ) (((x) >= 1U) && ((x) < 65535))

Definition at line 469 of file ald_ebi.h.

◆ IS_EBI_FRAME_PIXEL_NUMBER

#define IS_EBI_FRAME_PIXEL_NUMBER ( x ) (((x) >= 1U) && ((x) < 65535))

Definition at line 470 of file ald_ebi.h.

◆ IS_EBI_HIZ_TIME

#define IS_EBI_HIZ_TIME ( x ) ((x) <= 255U)

Definition at line 477 of file ald_ebi.h.

◆ IS_EBI_HOLD_TIME

#define IS_EBI_HOLD_TIME ( x ) ((x) <= 255U)

Definition at line 476 of file ald_ebi.h.

◆ IS_EBI_HORIZONTAL_SYNCH

#define IS_EBI_HORIZONTAL_SYNCH ( x )
Value:
(((x) == EBI_LCD_HSYNCPOL_LOW) || \
((x) == EBI_LCD_HSYNCPOL_HIGH))
EBI_LCD_HSYNCPOL_HIGH
Definition: ald_ebi.h:326
EBI_LCD_HSYNCPOL_LOW
Definition: ald_ebi.h:325

Definition at line 454 of file ald_ebi.h.

◆ IS_EBI_HYSNC_PULSE_WIDTH

#define IS_EBI_HYSNC_PULSE_WIDTH ( x ) ((x) < 255U)

Definition at line 467 of file ald_ebi.h.

◆ IS_EBI_LCD_DATASETUP_TIME

#define IS_EBI_LCD_DATASETUP_TIME ( x ) ((x) < 255U)

Definition at line 466 of file ald_ebi.h.

◆ IS_EBI_LCD_DEVICE

#define IS_EBI_LCD_DEVICE ( x ) ((x) == EBI_LCD_DEVICE)

Definition at line 453 of file ald_ebi.h.

◆ IS_EBI_LCD_ENABLE

#define IS_EBI_LCD_ENABLE ( x )
Value:
(((x) == EBI_LCD_LCDEN_DISABLE) || \
((x) == EBI_LCD_LCDEN_ENABLE))
EBI_LCD_LCDEN_DISABLE
Definition: ald_ebi.h:349
EBI_LCD_LCDEN_ENABLE
Definition: ald_ebi.h:350

Definition at line 460 of file ald_ebi.h.

◆ IS_EBI_LCD_RESET

#define IS_EBI_LCD_RESET ( x )
Value:
(((x) == EBI_LCD_LCDINT_DISABLE) || \
((x) == EBI_LCD_LCDINT_ENABLE))
EBI_LCD_LCDINT_DISABLE
Definition: ald_ebi.h:357
EBI_LCD_LCDINT_ENABLE
Definition: ald_ebi.h:358

Definition at line 462 of file ald_ebi.h.

◆ IS_EBI_MEMORY

#define IS_EBI_MEMORY ( x )
Value:
(((x) == EBI_MEMORY_TYPE_SRAM) || \
((x) == EBI_MEMORY_TYPE_PSRAM) || \
((x) == EBI_MEMORY_TYPE_NOR))
EBI_MEMORY_TYPE_PSRAM
Definition: ald_ebi.h:201
EBI_MEMORY_TYPE_SRAM
Definition: ald_ebi.h:200
EBI_MEMORY_TYPE_NOR
Definition: ald_ebi.h:202

Definition at line 427 of file ald_ebi.h.

◆ IS_EBI_MUX

#define IS_EBI_MUX ( x )
Value:
(((x) == EBI_DATA_ADDRESS_MUX_DISABLE) || \
((x) == EBI_DATA_ADDRESS_MUX_ENABLE))
EBI_DATA_ADDRESS_MUX_ENABLE
Definition: ald_ebi.h:183
EBI_DATA_ADDRESS_MUX_DISABLE
Definition: ald_ebi.h:182

Definition at line 425 of file ald_ebi.h.

◆ IS_EBI_NAND_BANK

#define IS_EBI_NAND_BANK ( x )
Value:
(((x) == EBI_NAND_BANK2) || \
((x) == EBI_NAND_BANK3))
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
EBI_NAND_BANK3
#define EBI_NAND_BANK3
Definition: ald_ebi.h:49

Definition at line 439 of file ald_ebi.h.

◆ IS_EBI_NAND_DEVICE

#define IS_EBI_NAND_DEVICE ( x ) ((x) == EBI_NAND_DEVICE)

Definition at line 480 of file ald_ebi.h.

◆ IS_EBI_NAND_MEMORY_WIDTH

#define IS_EBI_NAND_MEMORY_WIDTH ( x )
Value:
(((x) == EBI_NAND_MEM_BUS_WIDTH_8) || \
((x) == EBI_NAND_MEM_BUS_WIDTH_16))
EBI_NAND_MEM_BUS_WIDTH_16
Definition: ald_ebi.h:132
EBI_NAND_MEM_BUS_WIDTH_8
Definition: ald_ebi.h:131

Definition at line 443 of file ald_ebi.h.

◆ IS_EBI_NORSRAM_BANK

#define IS_EBI_NORSRAM_BANK ( x )
Value:
(((x) == EBI_NORSRAM_BANK1) || \
((x) == EBI_NORSRAM_BANK2) || \
((x) == EBI_NORSRAM_BANK3) || \
((x) == EBI_NORSRAM_BANK4))
EBI_NORSRAM_BANK2
Definition: ald_ebi.h:191
EBI_NORSRAM_BANK3
Definition: ald_ebi.h:192
EBI_NORSRAM_BANK4
Definition: ald_ebi.h:193
EBI_NORSRAM_BANK1
Definition: ald_ebi.h:190

Definition at line 421 of file ald_ebi.h.

◆ IS_EBI_NORSRAM_DEVICE

#define IS_EBI_NORSRAM_DEVICE ( x ) ((x) == EBI_NOR_SRAM_DEVICE)

Definition at line 478 of file ald_ebi.h.

◆ IS_EBI_NORSRAM_EXTENDED_DEVICE

#define IS_EBI_NORSRAM_EXTENDED_DEVICE ( x ) ((x) == EBI_NOR_SRAM_EXTENDED_DEVICE)

Definition at line 479 of file ald_ebi.h.

◆ IS_EBI_NORSRAM_MEMORY_WIDTH

#define IS_EBI_NORSRAM_MEMORY_WIDTH ( x )
Value:
(((x) == EBI_NORSRAM_MEM_BUS_WIDTH_8) || \
((x) == EBI_NORSRAM_MEM_BUS_WIDTH_16) || \
((x) == EBI_NORSRAM_MEM_BUS_WIDTH_32))
EBI_NORSRAM_MEM_BUS_WIDTH_8
Definition: ald_ebi.h:209
EBI_NORSRAM_MEM_BUS_WIDTH_32
Definition: ald_ebi.h:211
EBI_NORSRAM_MEM_BUS_WIDTH_16
Definition: ald_ebi.h:210

Definition at line 430 of file ald_ebi.h.

◆ IS_EBI_SETUP_TIME

#define IS_EBI_SETUP_TIME ( x ) ((x) <= 255U)

Definition at line 474 of file ald_ebi.h.

◆ IS_EBI_TAR_TIME

#define IS_EBI_TAR_TIME ( x ) ((x) <= 255U)

Definition at line 473 of file ald_ebi.h.

◆ IS_EBI_TCLR_TIME

#define IS_EBI_TCLR_TIME ( x ) ((x) <= 255U)

Definition at line 472 of file ald_ebi.h.

◆ IS_EBI_TURNAROUND_TIME

#define IS_EBI_TURNAROUND_TIME ( x ) ((x) <= 15U)

Definition at line 502 of file ald_ebi.h.

◆ IS_EBI_VERTICAL_SYNCH

#define IS_EBI_VERTICAL_SYNCH ( x )
Value:
(((x) == EBI_LCD_VSYNCPOL_LOW) || \
((x) == EBI_LCD_VSYNCPOL_HIGH))
EBI_LCD_VSYNCPOL_HIGH
Definition: ald_ebi.h:334
EBI_LCD_VSYNCPOL_LOW
Definition: ald_ebi.h:333

Definition at line 456 of file ald_ebi.h.

◆ IS_EBI_VSYNC_PULSE_WIDTH

#define IS_EBI_VSYNC_PULSE_WIDTH ( x ) ((x) < 255U)

Definition at line 468 of file ald_ebi.h.

◆ IS_EBI_WAIT_FEATURE

#define IS_EBI_WAIT_FEATURE ( x )
Value:
(((x) == EBI_NAND_WAIT_FEATURE_DISABLE) || \
((x) == EBI_NAND_WAIT_FEATURE_ENABLE))
EBI_NAND_WAIT_FEATURE_ENABLE
Definition: ald_ebi.h:124
EBI_NAND_WAIT_FEATURE_DISABLE
Definition: ald_ebi.h:123

Definition at line 441 of file ald_ebi.h.

◆ IS_EBI_WAIT_POLARITY

#define IS_EBI_WAIT_POLARITY ( x )
Value:
(((x) == EBI_WAIT_SIGNAL_POLARITY_LOW) || \
((x) == EBI_WAIT_SIGNAL_POLARITY_HIGH))
EBI_WAIT_SIGNAL_POLARITY_HIGH
Definition: ald_ebi.h:235
EBI_WAIT_SIGNAL_POLARITY_LOW
Definition: ald_ebi.h:234

Definition at line 483 of file ald_ebi.h.

◆ IS_EBI_WAIT_SIGNAL_ACTIVE

#define IS_EBI_WAIT_SIGNAL_ACTIVE ( x )
Value:
(((x) == EBI_WAIT_TIMING_BEFORE_WS) || \
((x) == EBI_WAIT_TIMING_DURING_WS))
EBI_WAIT_TIMING_DURING_WS
Definition: ald_ebi.h:251
EBI_WAIT_TIMING_BEFORE_WS
Definition: ald_ebi.h:250

Definition at line 487 of file ald_ebi.h.

◆ IS_EBI_WAIT_TIME

#define IS_EBI_WAIT_TIME ( x ) ((x) <= 255U)

Definition at line 475 of file ald_ebi.h.

◆ IS_EBI_WAITE_SIGNAL

#define IS_EBI_WAITE_SIGNAL ( x )
Value:
(((x) == EBI_WAIT_SIGNAL_DISABLE) || \
((x) == EBI_WAIT_SIGNAL_ENABLE))
EBI_WAIT_SIGNAL_ENABLE
Definition: ald_ebi.h:267
EBI_WAIT_SIGNAL_DISABLE
Definition: ald_ebi.h:266

Definition at line 491 of file ald_ebi.h.

◆ IS_EBI_WRAP_MODE

#define IS_EBI_WRAP_MODE ( x )
Value:
(((x) == EBI_WRAP_MODE_DISABLE) || \
((x) == EBI_WRAP_MODE_ENABLE))
EBI_WRAP_MODE_ENABLE
Definition: ald_ebi.h:243
EBI_WRAP_MODE_DISABLE
Definition: ald_ebi.h:242

Definition at line 485 of file ald_ebi.h.

◆ IS_EBI_WRITE_BURST

#define IS_EBI_WRITE_BURST ( x )
Value:
(((x) == EBI_WRITE_BURST_DISABLE) || \
((x) == EBI_WRITE_BURST_ENABLE))
EBI_WRITE_BURST_DISABLE
Definition: ald_ebi.h:290
EBI_WRITE_BURST_ENABLE
Definition: ald_ebi.h:291

Definition at line 433 of file ald_ebi.h.

◆ IS_EBI_WRITE_OPERATION

#define IS_EBI_WRITE_OPERATION ( x )
Value:
(((x) == EBI_WRITE_OPERATION_DISABLE) || \
((x) == EBI_WRITE_OPERATION_ENABLE))
EBI_WRITE_OPERATION_ENABLE
Definition: ald_ebi.h:259
EBI_WRITE_OPERATION_DISABLE
Definition: ald_ebi.h:258

Definition at line 489 of file ald_ebi.h.


ALD User Manual: FLASH

Modules | Macros
FLASH
EASTSOFT ES32F3xx ALD

FLASH module driver. More...

Collaboration diagram for FLASH:

Modules

Flash Private Variables
Flash Private Functions
Flash Private functions.
FLASH Private Macros
FLASH Private Types
Flash Public Functions

Macros

#define __RAMFUNC

Detailed Description

FLASH module driver.

Macro Definition Documentation

◆ __RAMFUNC

#define __RAMFUNC

Definition at line 53 of file ald_flash.c.


ALD User Manual: Flash Private Variables

Variables
Flash Private Variables
EASTSOFT ES32F3xx ALD » FLASH
Collaboration diagram for Flash Private Variables:

Variables

static op_cmd_type | OP_CMD = OP_FLASH
static uint8_t | write_buf [FLASH_PAGE_SIZE]

Detailed Description

Variable Documentation

◆ OP_CMD

op_cmd_type OP_CMD = OP_FLASH
static

Definition at line 60 of file ald_flash.c.

◆ write_buf

uint8_t write_buf[FLASH_PAGE_SIZE]
static

Definition at line 66 of file ald_flash_ext.c.


ALD User Manual: Flash Private Functions

Functions
Flash Private Functions
EASTSOFT ES32F3xx ALD » FLASH

Flash Private functions. More...

Collaboration diagram for Flash Private Functions:

Functions

static __RAMFUNC ald_status_t | flash_unlock (void)
Unlock the flash. More...
static __RAMFUNC ald_status_t | flash_lock (void)
Lock the flash. More...
__RAMFUNC ald_status_t | flash_page_erase (uint32_t addr)
Erase one page. More...
__RAMFUNC ald_status_t | flash_word_program (uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo)
Programme a word. More...
static type_bool_t | page_have_writen (uint32_t begin_addr, uint32_t end_addr)
Check whether the flash between the given address section have been writen, if it have been writen, return TRUE, else return FALSE. More...

Detailed Description

Flash Private functions.

Function Documentation

◆ flash_lock()

static __RAMFUNC ald_status_t flash_lock ( void )
static

Lock the flash.

Return values
Status,see ald_status_t.

Definition at line 97 of file ald_flash.c.

98 {
99 uint16_t i;
100 uint16_t op_cmd = OP_CMD;
101
102 FLASH_REG_UNLOCK();
103 WRITE_REG(MSC->FLASHCR, 0x0);
104
105 for (i = 0; i < 0xFFFF; i++) {
106 if (!(READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK)))
107 break;
108 }
109
110 return i == 0xFFFF ? ERROR : OK;
111 }
OK
Definition: utils.h:55
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
ERROR
Definition: utils.h:56
OP_CMD
static op_cmd_type OP_CMD
Definition: ald_flash.c:60
FLASH_REG_UNLOCK
#define FLASH_REG_UNLOCK()
Definition: ald_flash.h:38

◆ flash_page_erase()

ald_status_t flash_page_erase ( uint32_t addr )

Erase one page.

Parameters
addr The erased page's address
Return values
Status,see ald_status_t.

Definition at line 118 of file ald_flash.c.

119 {
120 uint32_t i;
121 uint16_t op_cmd = OP_CMD;
122
123 if (flash_unlock() != OK)
124 goto end;
125
126 if (op_cmd == OP_FLASH) {
127 CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
128 MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, FLASH_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS);
129 }
130 else {
131 SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
132 MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, INFO_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS);
133 }
134
135 WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE);
136
137 for (i = 0; i < 0xFFFF; i++) {
138 if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
139 continue;
140 if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_ADDR_OV_MSK))
141 goto end;
142 if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_WRP_FLAG_MSK))
143 goto end;
144 if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_SERA_MSK))
145 break;
146 }
147
148 if (i == 0xFFFF)
149 goto end;
150
151 if (flash_lock() == ERROR)
152 goto end;
153
154 return OK;
155 end:
156 flash_lock();
157 return ERROR;
158 }
OK
Definition: utils.h:55
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
OP_FLASH
Definition: ald_flash.h:93
FLASH_PAGE_ADDR
#define FLASH_PAGE_ADDR(ADDR)
Definition: ald_flash.h:61
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
flash_unlock
static __RAMFUNC ald_status_t flash_unlock(void)
Unlock the flash.
Definition: ald_flash.c:73
flash_lock
static __RAMFUNC ald_status_t flash_lock(void)
Lock the flash.
Definition: ald_flash.c:97
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
FLASH_CMD_PE
Definition: ald_flash.h:83
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
INFO_PAGE_ADDR
#define INFO_PAGE_ADDR(ADDR)
Definition: ald_flash.h:67
ERROR
Definition: utils.h:56
OP_CMD
static op_cmd_type OP_CMD
Definition: ald_flash.c:60

◆ flash_unlock()

static __RAMFUNC ald_status_t flash_unlock ( void )
static

Unlock the flash.

Return values
Status,see ald_status_t.

Definition at line 73 of file ald_flash.c.

74 {
75 uint16_t i;
76 uint16_t op_cmd = OP_CMD;
77
78 if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
79 return ERROR;
80
81 FLASH_REG_UNLOCK();
82 FLASH_IAP_ENABLE();
83 FLASH_REQ();
84
85 for (i = 0; i < 0xFFFF; i++) {
86 if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK))
87 break;
88 }
89
90 return i == 0xFFFF ? ERROR : OK;
91 }
OK
Definition: utils.h:55
FLASH_REQ
#define FLASH_REQ()
Definition: ald_flash.h:49
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
ERROR
Definition: utils.h:56
FLASH_IAP_ENABLE
#define FLASH_IAP_ENABLE()
Definition: ald_flash.h:51
OP_CMD
static op_cmd_type OP_CMD
Definition: ald_flash.c:60
FLASH_REG_UNLOCK
#define FLASH_REG_UNLOCK()
Definition: ald_flash.h:38

◆ flash_word_program()

ald_status_t flash_word_program | ( | uint32_t | addr,
 |  | uint32_t * | data,
 |  | uint32_t | len,
 |  | uint32_t | fifo
 | ) |  |

Programme a word.

Parameters
addr | The word's address, it is must word align.
data | The 8 bytes data be write.
len | The number of data be write.
fifo | Choose if use fifo.
Return values
Status,see ald_status_t.

Definition at line 168 of file ald_flash.c.

169 {
170 uint16_t i = 0;
171 uint16_t prog_len;
172 uint32_t *p_data = data;
173 uint16_t op_cmd = OP_CMD;
174
175 if (flash_unlock() != OK)
176 goto end;
177
178 if (op_cmd == OP_FLASH)
179 CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
180 else
181 SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
182
183 MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, addr << MSC_FLASHADDR_ADDR_POSS);
184 MODIFY_REG(MSC->FLASHCR, MSC_FLASHCR_FIFOEN_MSK, fifo << MSC_FLASHCR_FIFOEN_POS);
185
186 for (prog_len = 0; prog_len < len; prog_len++) {
187 if (fifo) {
188 WRITE_REG(MSC->FLASHFIFO, p_data[0]);
189 WRITE_REG(MSC->FLASHFIFO, p_data[1]);
190 }
191 else {
192 WRITE_REG(MSC->FLASHDL, p_data[0]);
193 WRITE_REG(MSC->FLASHDH, p_data[1]);
194 WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP);
195 }
196
197 p_data += 2;
198
199 for (i = 0; i < 0xFFFF; i++) {
200 if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
201 continue;
202 if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_PROG_MSK))
203 break;
204 }
205 }
206 if (i == 0xFFFF)
207 goto end;
208
209 if (flash_lock() == ERROR)
210 goto end;
211
212 return OK;
213 end:
214 flash_lock();
215 return ERROR;
216 }
OK
Definition: utils.h:55
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
OP_FLASH
Definition: ald_flash.h:93
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
flash_unlock
static __RAMFUNC ald_status_t flash_unlock(void)
Unlock the flash.
Definition: ald_flash.c:73
FLASH_CMD_WP
Definition: ald_flash.h:84
flash_lock
static __RAMFUNC ald_status_t flash_lock(void)
Lock the flash.
Definition: ald_flash.c:97
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
ERROR
Definition: utils.h:56
OP_CMD
static op_cmd_type OP_CMD
Definition: ald_flash.c:60

◆ page_have_writen()

static type_bool_t page_have_writen | ( | uint32_t | begin_addr,
 |  | uint32_t | end_addr
 | ) |  |
static

Check whether the flash between the given address section have been writen, if it have been writen, return TRUE, else return FALSE.

Parameters
begin_addr | The begin address.
end_addr | The end address.
Return values
The check result
  • TRUE
  • FALSE

Definition at line 85 of file ald_flash_ext.c.

86 {
87 uint8_t* addr_to_read;
88 uint8_t value;
89 uint32_t index;
90
91 /* Check the parameters */
92 assert_param(IS_FLASH_ADDRESS(begin_addr));
93 assert_param(IS_FLASH_ADDRESS(end_addr));
94
95 addr_to_read = (uint8_t *)begin_addr;
96 index = begin_addr;
97 value = 0xFF;
98
99 if (begin_addr > end_addr)
100 return FALSE;
101
102 while (index++ <= end_addr) {
103 value = *addr_to_read++;
104
105 if (value != 0xFF)
106 break;
107 }
108
109 return value == 0xFF ? FALSE : TRUE;
110 }
assert_param
#define assert_param(x)
Definition: type.h:88
FALSE
Definition: type.h:54
TRUE
Definition: type.h:55
IS_FLASH_ADDRESS
#define IS_FLASH_ADDRESS(ADDR)
Definition: ald_flash.h:59


ALD User Manual: FLASH Private Macros

Macros
FLASH Private Macros
EASTSOFT ES32F3xx ALD » FLASH
Collaboration diagram for FLASH Private Macros:

Macros

#define | FLASH_REG_UNLOCK()
#define | FLASH_REQ() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
#define | FLASH_REQ_FIN() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
#define | FLASH_IAP_ENABLE() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
#define | FLASH_IAP_DISABLE() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
#define | FLASH_BASE_ADDR 0x00000000
#define | FLASH_PAGE_SIZE 1024UL
#define | FLASH_WORD_SIZE 8UL
#define | FLASH_TOTAL_SIZE 512UL
#define | FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1)
#define | FLASH_WORD_MASK (FLASH_WORD_SIZE - 1)
#define | IS_FLASH_ADDRESS(ADDR) ((ADDR) < (FLASH_BASE_ADDR + FLASH_PAGE_SIZE * FLASH_TOTAL_SIZE))
#define | IS_4BYTES_ALIGN(ADDR) (((uint32_t)(ADDR) & 0x3) == 0 ? 1 : 0)
#define | FLASH_PAGE_ADDR(ADDR) ((ADDR) & (~FLASH_PAGE_MASK))
#define | FLASH_PAGEEND_ADDR(ADDR) ((ADDR) | FLASH_PAGE_MASK)
#define | FLASH_WORD_ADDR(ADDR) ((ADDR) & (~FLASH_WORD_MASK))
#define | FLASH_WORDEND_ADDR(ADDR) ((ADDR) | FLASH_WORD_MASK)
#define | INFO_PAGE_SIZE 1024UL
#define | INFO_PAGE_MASK (INFO_PAGE_SIZE - 1)
#define | INFO_PAGE_ADDR(ADDR) ((ADDR) & (~INFO_PAGE_MASK))
#define | FLASH_FIFO 0

Detailed Description

Macro Definition Documentation

◆ FLASH_BASE_ADDR

#define FLASH_BASE_ADDR 0x00000000

Definition at line 53 of file ald_flash.h.

◆ FLASH_FIFO

#define FLASH_FIFO 0

Definition at line 72 of file ald_flash.h.

◆ FLASH_IAP_DISABLE

#define FLASH_IAP_DISABLE ( ) (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))

Definition at line 52 of file ald_flash.h.

◆ FLASH_IAP_ENABLE

#define FLASH_IAP_ENABLE ( ) (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))

Definition at line 51 of file ald_flash.h.

◆ FLASH_PAGE_ADDR

#define FLASH_PAGE_ADDR ( ADDR ) ((ADDR) & (~FLASH_PAGE_MASK))

Definition at line 61 of file ald_flash.h.

◆ FLASH_PAGE_MASK

#define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1)

Definition at line 57 of file ald_flash.h.

◆ FLASH_PAGE_SIZE

#define FLASH_PAGE_SIZE 1024UL

Definition at line 54 of file ald_flash.h.

◆ FLASH_PAGEEND_ADDR

#define FLASH_PAGEEND_ADDR ( ADDR ) ((ADDR) | FLASH_PAGE_MASK)

Definition at line 62 of file ald_flash.h.

◆ FLASH_REG_UNLOCK

#define FLASH_REG_UNLOCK ( )
Value:
do { \
if (op_cmd == OP_FLASH) { \
WRITE_REG(MSC->FLASHKEY, 0x8ACE0246); \
WRITE_REG(MSC->FLASHKEY, 0x9BDF1357); \
} \
else { \
WRITE_REG(MSC->INFOKEY, 0x7153BFD9); \
WRITE_REG(MSC->INFOKEY, 0x0642CEA8); \
} \
} while (0)
OP_FLASH
Definition: ald_flash.h:93

Definition at line 38 of file ald_flash.h.

◆ FLASH_REQ

#define FLASH_REQ ( ) (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))

Definition at line 49 of file ald_flash.h.

◆ FLASH_REQ_FIN

#define FLASH_REQ_FIN ( ) (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))

Definition at line 50 of file ald_flash.h.

◆ FLASH_TOTAL_SIZE

#define FLASH_TOTAL_SIZE 512UL

Definition at line 56 of file ald_flash.h.

◆ FLASH_WORD_ADDR

#define FLASH_WORD_ADDR ( ADDR ) ((ADDR) & (~FLASH_WORD_MASK))

Definition at line 63 of file ald_flash.h.

◆ FLASH_WORD_MASK

#define FLASH_WORD_MASK (FLASH_WORD_SIZE - 1)

Definition at line 58 of file ald_flash.h.

◆ FLASH_WORD_SIZE

#define FLASH_WORD_SIZE 8UL

Definition at line 55 of file ald_flash.h.

◆ FLASH_WORDEND_ADDR

#define FLASH_WORDEND_ADDR ( ADDR ) ((ADDR) | FLASH_WORD_MASK)

Definition at line 64 of file ald_flash.h.

◆ INFO_PAGE_ADDR

#define INFO_PAGE_ADDR ( ADDR ) ((ADDR) & (~INFO_PAGE_MASK))

Definition at line 67 of file ald_flash.h.

◆ INFO_PAGE_MASK

#define INFO_PAGE_MASK (INFO_PAGE_SIZE - 1)

Definition at line 66 of file ald_flash.h.

◆ INFO_PAGE_SIZE

#define INFO_PAGE_SIZE 1024UL

Definition at line 65 of file ald_flash.h.

◆ IS_4BYTES_ALIGN

#define IS_4BYTES_ALIGN ( ADDR ) (((uint32_t)(ADDR) & 0x3) == 0 ? 1 : 0)

Definition at line 60 of file ald_flash.h.

◆ IS_FLASH_ADDRESS

#define IS_FLASH_ADDRESS ( ADDR ) ((ADDR) < (FLASH_BASE_ADDR + FLASH_PAGE_SIZE * FLASH_TOTAL_SIZE))

Definition at line 59 of file ald_flash.h.


ALD User Manual: FLASH Private Types

Enumerations
FLASH Private Types
EASTSOFT ES32F3xx ALD » FLASH
Collaboration diagram for FLASH Private Types:

Enumerations

enum flash_cmd_type {
FLASH_CMD_AE = 0x000051AEU, FLASH_CMD_PE = 0x00005EA1U, FLASH_CMD_WP = 0x00005DA2U, FLASH_CMD_WP_FAST = 0x00005CA3U,
FLASH_CMD_DATAPE = 0x00005BA4U, FLASH_CMD_DATAWP = 0x00005AA5U, FLASH_CMD_DATAWP_FAST = 0x000059A6U, FLASH_CMD_NP_AE = 0x000050AFU
}
enum op_cmd_type { OP_FLASH = 0U, OP_INFO = 1U }

Detailed Description

Enumeration Type Documentation

◆ flash_cmd_type

enum flash_cmd_type
Enumerator
FLASH_CMD_AE | Program area erase all
FLASH_CMD_PE | Page erase
FLASH_CMD_WP | Word program
FLASH_CMD_WP_FAST | Flash quickly program
FLASH_CMD_DATAPE | Data flash page page erase
FLASH_CMD_DATAWP | Data flash word program
FLASH_CMD_DATAWP_FAST | Data flash quickly program
FLASH_CMD_NP_AE | No-private area erase all

Definition at line 81 of file ald_flash.h.

81 {
82 FLASH_CMD_AE = 0x000051AEU,
83 FLASH_CMD_PE = 0x00005EA1U,
84 FLASH_CMD_WP = 0x00005DA2U,
85 FLASH_CMD_WP_FAST = 0x00005CA3U,
86 FLASH_CMD_DATAPE = 0x00005BA4U,
87 FLASH_CMD_DATAWP = 0x00005AA5U,
88 FLASH_CMD_DATAWP_FAST = 0x000059A6U,
89 FLASH_CMD_NP_AE = 0x000050AFU,
90 } flash_cmd_type;
FLASH_CMD_WP_FAST
Definition: ald_flash.h:85
FLASH_CMD_NP_AE
Definition: ald_flash.h:89
FLASH_CMD_AE
Definition: ald_flash.h:82
flash_cmd_type
flash_cmd_type
Definition: ald_flash.h:81
FLASH_CMD_DATAWP_FAST
Definition: ald_flash.h:88
FLASH_CMD_WP
Definition: ald_flash.h:84
FLASH_CMD_PE
Definition: ald_flash.h:83
FLASH_CMD_DATAWP
Definition: ald_flash.h:87
FLASH_CMD_DATAPE
Definition: ald_flash.h:86

◆ op_cmd_type

enum op_cmd_type
Enumerator
OP_FLASH | Operate Pragram area
OP_INFO | Operate info area

Definition at line 92 of file ald_flash.h.

92 {
93 OP_FLASH = 0U,
94 OP_INFO = 1U,
95 } op_cmd_type;
op_cmd_type
op_cmd_type
Definition: ald_flash.h:92
OP_FLASH
Definition: ald_flash.h:93
OP_INFO
Definition: ald_flash.h:94


ALD User Manual: Flash Public Functions

Functions
Flash Public Functions
EASTSOFT ES32F3xx ALD » FLASH
Collaboration diagram for Flash Public Functions:

Functions

ald_status_t | ald_flash_read (uint32_t *ram_addr, uint32_t addr, uint16_t len)
read the specified length bytes from flash, and store to the specified area. More...
ald_status_t | ald_flash_write (uint32_t addr, uint8_t *buf, uint16_t len)
Write the give bytes to the given address section. More...
ald_status_t | ald_flash_erase (uint32_t addr, uint16_t len)
erase The flash between the given address section. More...

Detailed Description

===============================================================================
             ##### Flash operation functions #####
===============================================================================
 [..]
   This section provides functions allowing to operate flash, such as read and write.

Function Documentation

◆ ald_flash_erase()

ald_status_t ald_flash_erase | ( | uint32_t | addr,
 |  | uint16_t | len
 | ) |  |

erase The flash between the given address section.

Parameters
addr | The start address to erase.
len | The length to erase.
Return values
Status,see ald_status_t.

Definition at line 250 of file ald_flash_ext.c.

251 {
252 uint32_t index;
253 int32_t para;
254 int32_t start_erase_addr;
255 int32_t end_erase_addr;
256 uint16_t len_not_erase;
257 uint32_t len_index;
258 type_bool_t page_need_save;
259
260 assert_param(IS_FLASH_ADDRESS(addr));
261 assert_param(IS_FLASH_ADDRESS(addr + len - 1));
262
263 len_not_erase = len;
264
265 __disable_irq();
266 while (len_not_erase > 0) {
267 page_need_save = FALSE;
268
269 start_erase_addr = addr + len - len_not_erase;
270 end_erase_addr = addr + len - 1;
271 end_erase_addr = (FLASH_PAGE_ADDR(start_erase_addr) == FLASH_PAGE_ADDR(end_erase_addr))
272 ? end_erase_addr : FLASH_PAGEEND_ADDR(start_erase_addr);
273
274 if (start_erase_addr != FLASH_PAGE_ADDR(start_erase_addr)) {
275 if (page_have_writen(FLASH_PAGE_ADDR(start_erase_addr), (start_erase_addr - 1)))
276 page_need_save = TRUE;
277 }
278 if (end_erase_addr != FLASH_PAGEEND_ADDR(end_erase_addr)) {
279 if (page_have_writen((end_erase_addr + 1), FLASH_PAGEEND_ADDR(end_erase_addr)))
280 page_need_save = TRUE;
281 }
282
283 if (page_need_save) {
284 if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_erase_addr),
285 FLASH_PAGE_SIZE >> 2)) {
286 __enable_irq();
287 return ERROR;
288 }
289 }
290
291 if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_erase_addr))) {
292 __enable_irq();
293 return ERROR;
294 }
295
296 if (page_need_save) {
297 para = end_erase_addr & (FLASH_PAGE_SIZE - 1);
298 index = start_erase_addr & (FLASH_PAGE_SIZE - 1);
299
300 while (index <= para)
301 write_buf[index++] = 0xFF;
302
303 index = FLASH_PAGE_ADDR(start_erase_addr);
304 len_index = FLASH_PAGE_SIZE;
305 if (ERROR == flash_word_program(index, (uint32_t *)write_buf, (len_index >> 3), FLASH_FIFO)) {
306 __enable_irq();
307 return ERROR;
308 }
309 }
310 len_not_erase = len_not_erase - (end_erase_addr - start_erase_addr + 1);
311 }
312
313 __enable_irq();
314 return OK;
315 }
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
FALSE
Definition: type.h:54
ald_flash_read
ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len)
read the specified length bytes from flash, and store to the specified area.
Definition: ald_flash_ext.c:134
type_bool_t
type_bool_t
Definition: type.h:53
FLASH_PAGE_ADDR
#define FLASH_PAGE_ADDR(ADDR)
Definition: ald_flash.h:61
flash_page_erase
__RAMFUNC ald_status_t flash_page_erase(uint32_t addr)
Erase one page.
Definition: ald_flash.c:118
TRUE
Definition: type.h:55
IS_FLASH_ADDRESS
#define IS_FLASH_ADDRESS(ADDR)
Definition: ald_flash.h:59
flash_word_program
__RAMFUNC ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo)
Programme a word.
Definition: ald_flash.c:168
FLASH_FIFO
#define FLASH_FIFO
Definition: ald_flash.h:72
FLASH_PAGE_SIZE
#define FLASH_PAGE_SIZE
Definition: ald_flash.h:54
write_buf
static uint8_t write_buf[FLASH_PAGE_SIZE]
Definition: ald_flash_ext.c:66
ERROR
Definition: utils.h:56
FLASH_PAGEEND_ADDR
#define FLASH_PAGEEND_ADDR(ADDR)
Definition: ald_flash.h:62
page_have_writen
static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr)
Check whether the flash between the given address section have been writen, if it have been writen...
Definition: ald_flash_ext.c:85

◆ ald_flash_read()

ald_status_t ald_flash_read | ( | uint32_t * | ram_addr,
 |  | uint32_t | addr,
 |  | uint16_t | len
 | ) |  |

read the specified length bytes from flash, and store to the specified area.

Parameters
ram_addr | the specified area to store the reading bytes.
addr | the start address.
len | the length to read.
Return values
Status,see ald_status_t.

Definition at line 134 of file ald_flash_ext.c.

135 {
136 uint32_t i;
137 uint32_t temp;
138
139 assert_param(IS_4BYTES_ALIGN(ram_addr));
140 assert_param(IS_FLASH_ADDRESS(addr));
141 assert_param(IS_FLASH_ADDRESS(addr + len - 1));
142
143 temp = (uint32_t)ram_addr;
144
145 if (((temp & 0x3) != 0) || (((addr) & 0x3) != 0))
146 return ERROR;
147
148 for (i = 0; i < len; i++)
149 ram_addr[i] = ((uint32_t *)addr)[i];
150
151 return OK;
152 }
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
IS_FLASH_ADDRESS
#define IS_FLASH_ADDRESS(ADDR)
Definition: ald_flash.h:59
ERROR
Definition: utils.h:56
IS_4BYTES_ALIGN
#define IS_4BYTES_ALIGN(ADDR)
Definition: ald_flash.h:60

◆ ald_flash_write()

ald_status_t ald_flash_write | ( | uint32_t | addr,
 |  | uint8_t * | buf,
 |  | uint16_t | len
 | ) |  |

Write the give bytes to the given address section.

Parameters
addr | The start address to write.
buf | The bytes' address.
len | The length to write,and multiple of 2.
Return values
Status,see ald_status_t.

Definition at line 162 of file ald_flash_ext.c.

163 {
164 uint32_t index = 0;
165 uint32_t para = 0;
166 uint32_t index2 = 0;
167 uint32_t start_write_addr;
168 uint32_t end_write_addr;
169 uint32_t start_word_addr;
170 uint32_t end_word_addr;
171 uint16_t len_to_write;
172 uint32_t len_index;
173 type_bool_t need_erase_page;
174
175 assert_param(IS_FLASH_ADDRESS(addr));
176 assert_param(IS_FLASH_ADDRESS(addr + len - 1));
177
178 len_to_write = len;
179
180 __disable_irq();
181 while (len_to_write > 0) {
182 need_erase_page = FALSE;
183
184 for (index = 0; index < FLASH_PAGE_SIZE; index++)
185 write_buf[index] = 0xFF;
186
187 start_write_addr = addr + (len - len_to_write);
188 end_write_addr = addr + len - 1;
189 end_write_addr = FLASH_PAGE_ADDR(start_write_addr) == FLASH_PAGE_ADDR(end_write_addr)
190 ? end_write_addr : FLASH_PAGEEND_ADDR(start_write_addr);
191 need_erase_page = page_have_writen(FLASH_WORD_ADDR(start_write_addr),
192 FLASH_WORDEND_ADDR(end_write_addr));
193
194 if (need_erase_page) {
195 if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_write_addr),
196 FLASH_PAGE_SIZE >> 2)) {
197 __enable_irq();
198 return ERROR;
199 }
200
201 if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_write_addr))) {
202 __enable_irq();
203 return ERROR;
204 }
205
206 para = end_write_addr & (FLASH_PAGE_SIZE - 1);
207 index = start_write_addr & (FLASH_PAGE_SIZE - 1);
208 index2 = len - len_to_write;
209
210 while (index <= para)
211 write_buf[index++] = buf[index2++];
212
213 index2 = 0;
214 index = FLASH_PAGE_ADDR(start_write_addr);
215 len_index = FLASH_PAGE_SIZE;
216 }
217 else {
218 para = end_write_addr & (FLASH_PAGE_SIZE - 1);
219 index = start_write_addr & (FLASH_PAGE_SIZE - 1);
220 index2 = len - len_to_write;
221
222 while (index <= para)
223 write_buf[index++] = buf[index2++];
224
225 start_word_addr = FLASH_WORD_ADDR(start_write_addr);
226 end_word_addr = FLASH_WORDEND_ADDR(end_write_addr);
227 index2 = (FLASH_WORD_ADDR(start_word_addr) - FLASH_PAGE_ADDR(start_word_addr));
228 index = start_word_addr;
229 len_index = end_word_addr - start_word_addr + 1;
230 }
231
232 if (ERROR == flash_word_program(index, (uint32_t *)(write_buf + index2), (len_index >> 3), FLASH_FIFO)) {
233 __enable_irq();
234 return ERROR;
235 }
236
237 len_to_write = len_to_write - (end_write_addr - start_write_addr + 1);
238 }
239
240 __enable_irq();
241 return OK;
242 }
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
FALSE
Definition: type.h:54
ald_flash_read
ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len)
read the specified length bytes from flash, and store to the specified area.
Definition: ald_flash_ext.c:134
type_bool_t
type_bool_t
Definition: type.h:53
FLASH_PAGE_ADDR
#define FLASH_PAGE_ADDR(ADDR)
Definition: ald_flash.h:61
flash_page_erase
__RAMFUNC ald_status_t flash_page_erase(uint32_t addr)
Erase one page.
Definition: ald_flash.c:118
FLASH_WORD_ADDR
#define FLASH_WORD_ADDR(ADDR)
Definition: ald_flash.h:63
IS_FLASH_ADDRESS
#define IS_FLASH_ADDRESS(ADDR)
Definition: ald_flash.h:59
flash_word_program
__RAMFUNC ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo)
Programme a word.
Definition: ald_flash.c:168
FLASH_FIFO
#define FLASH_FIFO
Definition: ald_flash.h:72
FLASH_PAGE_SIZE
#define FLASH_PAGE_SIZE
Definition: ald_flash.h:54
FLASH_WORDEND_ADDR
#define FLASH_WORDEND_ADDR(ADDR)
Definition: ald_flash.h:64
write_buf
static uint8_t write_buf[FLASH_PAGE_SIZE]
Definition: ald_flash_ext.c:66
ERROR
Definition: utils.h:56
FLASH_PAGEEND_ADDR
#define FLASH_PAGEEND_ADDR(ADDR)
Definition: ald_flash.h:62
page_have_writen
static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr)
Check whether the flash between the given address section have been writen, if it have been writen...
Definition: ald_flash_ext.c:85


ALD User Manual: GPIO

Modules
GPIO
EASTSOFT ES32F3xx ALD

GPIO module driver. More...

Collaboration diagram for GPIO:

Modules

GPIO Public Functions
GPIO Public Macros
GPIO Public Types
GPIO Private Macros

Detailed Description

GPIO module driver.


ALD User Manual: GPIO Public Functions

Modules
GPIO Public Functions
EASTSOFT ES32F3xx ALD » GPIO
Collaboration diagram for GPIO Public Functions:

Modules

Initialization functions
Initialization and Configuration functions.
IO operation functions
GPIO Read and Write.
Control functions
EXTI Control functions.

Detailed Description


ALD User Manual: Initialization functions

Functions
Initialization functions
EASTSOFT ES32F3xx ALD » GPIO » GPIO Public Functions

Initialization and Configuration functions. More...

Collaboration diagram for Initialization functions:

Functions

void | ald_gpio_init (GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init)
Initialize the GPIOx peripheral according to the specified parameters in the gpio_init_t. More...
void | ald_gpio_init_default (GPIO_TypeDef *GPIOx, uint16_t pin)
Initialize the GPIOx peripheral using the default parameters. More...
void | ald_gpio_func_default (GPIO_TypeDef *GPIOx)
Sets GPIO function to default(func0). More...
void | ald_gpio_exti_init (GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init)
Initialize the external interrupt according to the specified parameters in the exti_init_t. More...

Detailed Description

Initialization and Configuration functions.

===============================================================================
             ##### Initialization functions #####
===============================================================================
 [..]
   This section provides functions allowing to initialize the GPIOs or external
   interrupt to be ready for use.

Function Documentation

◆ ald_gpio_exti_init()

void ald_gpio_exti_init | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | pin,
 |  | exti_init_t * | init
 | ) |  |

Initialize the external interrupt according to the specified parameters in the exti_init_t.

Parameters
GPIOx | Where x can be (A–H) to select the GPIO peripheral.
pin | The pin which need to initialize.
init | Pointer to a exti_init_t structure that can contains the configuration information for the specified parameters.
Return values
None

Definition at line 297 of file ald_gpio.c.

298 {
299 uint8_t i;
300 uint8_t port;
301
302 assert_param(IS_GPIO_PORT(GPIOx));
303 assert_param(IS_GPIO_PIN(pin));
304 assert_param(IS_FUNC_STATE(init->filter));
305 assert_param(IS_EXTI_FLTCKS_TYPE(init->cks));
306
307 /* Get GPIO port */
308 if (GPIOx == GPIOA)
309 port = 0x0;
310 else if (GPIOx == GPIOB)
311 port = 0x1;
312 else if (GPIOx == GPIOC)
313 port = 2;
314 else if (GPIOx == GPIOD)
315 port = 3;
316 else if (GPIOx == GPIOE)
317 port = 4;
318 else if (GPIOx == GPIOF)
319 port = 5;
320 else if (GPIOx == GPIOG)
321 port = 6;
322 else if (GPIOx == GPIOH)
323 port = 7;
324 else
325 port = 0;
326
327 /* Get Pin index */
328 for (i = 0; i < 16; ++i) {
329 if (((pin >> i) & 0x1) == 0x1)
330 break;
331 }
332
333 /* Select external interrupt line */
334 if (i <= 7) {
335 EXTI->EXTIPSR0 &= ~(0x7U << (i * 4));
336 EXTI->EXTIPSR0 |= (port << (i * 4));
337 }
338 else {
339 i -= 8;
340 EXTI->EXTIPSR1 &= ~(0x7U << (i * 4));
341 EXTI->EXTIPSR1 |= (port << (i * 4));
342 }
343
344 /* Configure filter parameter */
345 if (init->filter == ENABLE) {
346 SET_BIT(EXTI->EXTIFLTCR, pin);
347 MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTCKS_MSK, init->cks << GPIO_EXTIFLTCR_FLTCKS_POSS);
348 MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTSEL_MSK, init->filter_time << GPIO_EXTIFLTCR_FLTSEL_POSS);
349 }
350 else {
351 CLEAR_BIT(EXTI->EXTIFLTCR, pin);
352 }
353
354 return;
355 }
ENABLE
Definition: type.h:49
exti_init_t::cks
exti_filter_clock_t cks
Definition: ald_gpio.h:178
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
exti_init_t::filter
type_func_t filter
Definition: ald_gpio.h:177
IS_EXTI_FLTCKS_TYPE
#define IS_EXTI_FLTCKS_TYPE(x)
Definition: ald_gpio.h:222
exti_init_t::filter_time
uint8_t filter_time
Definition: ald_gpio.h:179
IS_GPIO_PIN
#define IS_GPIO_PIN(x)
Definition: ald_gpio.h:192
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
IS_GPIO_PORT
#define IS_GPIO_PORT(GPIOx)
Definition: ald_gpio.h:193

◆ ald_gpio_func_default()

void ald_gpio_func_default ( GPIO_TypeDef * GPIOx )

Sets GPIO function to default(func0).

Parameters
GPIOx Where x can be (A–H) to select the GPIO peripheral.
Return values
None

Definition at line 280 of file ald_gpio.c.

281 {
282 WRITE_REG(GPIOx->FUNC0, 0x00);
283 WRITE_REG(GPIOx->FUNC1, 0x00);
284
285 return;
286 }
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72

◆ ald_gpio_init()

void ald_gpio_init | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | pin,
 |  | gpio_init_t * | init
 | ) |  |

Initialize the GPIOx peripheral according to the specified parameters in the gpio_init_t.

Parameters
GPIOx | Where x can be (A–H) to select the GPIO peripheral.
pin | The pin which need to initialize.
init | Pointer to a gpio_init_t structure that can contains the configuration information for the specified parameters.
Return values
None

Definition at line 170 of file ald_gpio.c.

171 {
172 uint32_t i, pos, mask, tmp;
173
174 assert_param(IS_GPIO_PORT(GPIOx));
175 assert_param(IS_GPIO_PIN(pin));
176 assert_param(IS_GPIO_MODE(init->mode));
177 assert_param(IS_GPIO_ODOS(init->odos));
178 assert_param(IS_GPIO_PUPD(init->pupd));
179 assert_param(IS_GPIO_ODRV(init->podrv));
180 assert_param(IS_GPIO_ODRV(init->nodrv));
181 assert_param(IS_GPIO_FLT(init->flt));
182 assert_param(IS_GPIO_TYPE(init->type));
183 assert_param(IS_GPIO_FUNC(init->func));
184
185 for (i = 0; i < 16; ++i) {
186 if (((pin >> i) & 0x1) == 0)
187 continue;
188
189 /* Get position and 2-bits mask */
190 pos = i << 1;
191 mask = 0x3 << pos;
192
193 /* Set PIN mode */
194 tmp = READ_REG(GPIOx->MODE);
195 tmp &= ~mask;
196 tmp |= (init->mode << pos);
197 WRITE_REG(GPIOx->MODE, tmp);
198
199 /* Set PIN open-drain or push-pull */
200 tmp = READ_REG(GPIOx->ODOS);
201 tmp &= ~mask;
202 tmp |= (init->odos << pos);
203 WRITE_REG(GPIOx->ODOS, tmp);
204
205 /* Set PIN push-up or/and push-down */
206 tmp = READ_REG(GPIOx->PUPD);
207 tmp &= ~mask;
208 tmp |= (init->pupd << pos);
209 WRITE_REG(GPIOx->PUPD, tmp);
210
211 /* Set PIN output P-MOS driver */
212 tmp = READ_REG(GPIOx->PODRV);
213 tmp &= ~mask;
214 tmp |= (init->podrv << pos);
215 WRITE_REG(GPIOx->PODRV, tmp);
216
217 /* Set PIN output N-MOS driver */
218 tmp = READ_REG(GPIOx->NODRV);
219 tmp &= ~mask;
220 tmp |= (init->nodrv << pos);
221 WRITE_REG(GPIOx->NODRV, tmp);
222
223 /* Get position and 1-bit mask */
224 pos = i;
225 mask = 0x1 << pos;
226
227 /* Set PIN filter enable or disable */
228 tmp = READ_REG(GPIOx->FLT);
229 tmp &= ~mask;
230 tmp |= (init->flt << pos);
231 WRITE_REG(GPIOx->FLT, tmp);
232
233 /* Set PIN type ttl or smit */
234 tmp = READ_REG(GPIOx->TYPE);
235 tmp &= ~mask;
236 tmp |= (init->type << pos);
237 WRITE_REG(GPIOx->TYPE, tmp);
238
239 /* Configure PIN function */
240 pos = i < 8 ? (i << 2) : ((i - 8) << 2);
241 mask = 0xF << pos;
242 tmp = i < 8 ? READ_REG(GPIOx->FUNC0) : READ_REG(GPIOx->FUNC1);
243 tmp &= ~mask;
244 tmp |= (init->func << pos);
245 i < 8 ? WRITE_REG(GPIOx->FUNC0, tmp) : WRITE_REG(GPIOx->FUNC1, tmp);
246 }
247
248 return;
249 }
gpio_init_t::nodrv
gpio_out_drive_t nodrv
Definition: ald_gpio.h:146
assert_param
#define assert_param(x)
Definition: type.h:88
READ_REG
#define READ_REG(reg)
Definition: type.h:73
IS_GPIO_FLT
#define IS_GPIO_FLT(x)
Definition: ald_gpio.h:215
IS_GPIO_FUNC
#define IS_GPIO_FUNC(x)
Definition: ald_gpio.h:224
gpio_init_t::func
gpio_func_t func
Definition: ald_gpio.h:152
gpio_init_t::flt
gpio_filter_t flt
Definition: ald_gpio.h:148
IS_GPIO_TYPE
#define IS_GPIO_TYPE(x)
Definition: ald_gpio.h:217
gpio_init_t::type
gpio_type_t type
Definition: ald_gpio.h:150
IS_GPIO_ODOS
#define IS_GPIO_ODOS(x)
Definition: ald_gpio.h:204
IS_GPIO_PIN
#define IS_GPIO_PIN(x)
Definition: ald_gpio.h:192
gpio_init_t::mode
gpio_mode_t mode
Definition: ald_gpio.h:138
gpio_init_t::pupd
gpio_push_t pupd
Definition: ald_gpio.h:142
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
gpio_init_t::podrv
gpio_out_drive_t podrv
Definition: ald_gpio.h:144
IS_GPIO_ODRV
#define IS_GPIO_ODRV(x)
Definition: ald_gpio.h:211
IS_GPIO_PUPD
#define IS_GPIO_PUPD(x)
Definition: ald_gpio.h:207
IS_GPIO_MODE
#define IS_GPIO_MODE(x)
Definition: ald_gpio.h:201
gpio_init_t::odos
gpio_odos_t odos
Definition: ald_gpio.h:140
IS_GPIO_PORT
#define IS_GPIO_PORT(GPIOx)
Definition: ald_gpio.h:193

◆ ald_gpio_init_default()

void ald_gpio_init_default | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | pin
 | ) |  |

Initialize the GPIOx peripheral using the default parameters.

Parameters
GPIOx | Where x can be (A–H) to select the GPIO peripheral.
pin | The pin which need to initialize.
Return values
None

Definition at line 257 of file ald_gpio.c.

258 {
259 gpio_init_t init;
260
261 /* Fill GPIO_init_t structure with default parameter */
262 init.mode = GPIO_MODE_OUTPUT;
263 init.odos = GPIO_PUSH_PULL;
264 init.pupd = GPIO_PUSH_UP;
265 init.podrv = GPIO_OUT_DRIVE_6;
266 init.nodrv = GPIO_OUT_DRIVE_6;
267 init.flt = GPIO_FILTER_DISABLE;
268 init.type = GPIO_TYPE_CMOS;
269 init.func = GPIO_FUNC_1;
270
271 ald_gpio_init(GPIOx, pin, &init);
272 return;
273 }
gpio_init_t::nodrv
gpio_out_drive_t nodrv
Definition: ald_gpio.h:146
GPIO_FUNC_1
Definition: ald_gpio.h:124
gpio_init_t::func
gpio_func_t func
Definition: ald_gpio.h:152
gpio_init_t::flt
gpio_filter_t flt
Definition: ald_gpio.h:148
GPIO_FILTER_DISABLE
Definition: ald_gpio.h:107
GPIO_PUSH_PULL
Definition: ald_gpio.h:78
gpio_init_t::type
gpio_type_t type
Definition: ald_gpio.h:150
gpio_init_t
GPIO Init Structure definition.
Definition: ald_gpio.h:137
gpio_init_t::mode
gpio_mode_t mode
Definition: ald_gpio.h:138
gpio_init_t::pupd
gpio_push_t pupd
Definition: ald_gpio.h:142
GPIO_MODE_OUTPUT
Definition: ald_gpio.h:71
GPIO_TYPE_CMOS
Definition: ald_gpio.h:115
gpio_init_t::podrv
gpio_out_drive_t podrv
Definition: ald_gpio.h:144
gpio_init_t::odos
gpio_odos_t odos
Definition: ald_gpio.h:140
ald_gpio_init
void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init)
Initialize the GPIOx peripheral according to the specified parameters in the gpio_init_t.
Definition: ald_gpio.c:170
GPIO_OUT_DRIVE_6
Definition: ald_gpio.h:99
GPIO_PUSH_UP
Definition: ald_gpio.h:88


ALD User Manual: IO operation functions

Functions
IO operation functions
EASTSOFT ES32F3xx ALD » GPIO » GPIO Public Functions

GPIO Read and Write. More...

Collaboration diagram for IO operation functions:

Functions

uint8_t | ald_gpio_read_pin (GPIO_TypeDef *GPIOx, uint16_t pin)
Read the specified input port pin. More...
void | ald_gpio_write_pin (GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val)
Set or clear the select Pin data. More...
void | ald_gpio_toggle_pin (GPIO_TypeDef *GPIOx, uint16_t pin)
Turn over the select data. More...
void | ald_gpio_toggle_dir (GPIO_TypeDef *GPIOx, uint16_t pin)
Turn over the direction. More...
void | ald_gpio_lock_pin (GPIO_TypeDef *GPIOx, uint16_t pin)
Lock the GPIO prot. Once locked, can only change the output data. Only when the CPU reset to unlock the GPIO port. More...
uint16_t | ald_gpio_read_port (GPIO_TypeDef *GPIOx)
Read the specified input port pin. More...
void | ald_gpio_write_port (GPIO_TypeDef *GPIOx, uint16_t val)
Set or clear the select Pin data. More...

Detailed Description

GPIO Read and Write.

===============================================================================
                      ##### IO operation functions #####
===============================================================================
 [..]
   This subsection provides a set of functions allowing to manage the GPIOs.

Function Documentation

◆ ald_gpio_lock_pin()

void ald_gpio_lock_pin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | pin
 | ) |  |

Lock the GPIO prot. Once locked, can only change the output data. Only when the CPU reset to unlock the GPIO port.

Parameters
GPIOx | Where x can be (A–H) to select the GPIO peripheral.
pin | The specified Pin to be written.
Return values
None

Definition at line 477 of file ald_gpio.c.

478 {
479 assert_param(IS_GPIO_PORT(GPIOx));
480 assert_param(IS_GPIO_PIN(pin));
481
482 MODIFY_REG(GPIOx->LOCK, GPIO_LOCK_KEY_MSK, UNLOCK_KEY << GPIO_LOCK_KEY_POSS);
483 WRITE_REG(GPIOx->LOCK, pin);
484
485 return;
486 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_GPIO_PIN
#define IS_GPIO_PIN(x)
Definition: ald_gpio.h:192
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
UNLOCK_KEY
#define UNLOCK_KEY
Definition: ald_gpio.h:190
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_GPIO_PORT
#define IS_GPIO_PORT(GPIOx)
Definition: ald_gpio.h:193

◆ ald_gpio_read_pin()

uint8_t ald_gpio_read_pin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | pin
 | ) |  |

Read the specified input port pin.

Parameters
GPIOx | Where x can be (A–H) to select the GPIO peripheral.
pin | Specifies the pin to read.
Return values
The input pin value

Definition at line 380 of file ald_gpio.c.

381 {
382 assert_param(IS_GPIO_PORT(GPIOx));
383 assert_param(IS_GPIO_PIN(pin));
384
385 if (READ_BIT(GPIOx->DIN, pin))
386 return 1;
387 else
388 return 0;
389 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_GPIO_PIN
#define IS_GPIO_PIN(x)
Definition: ald_gpio.h:192
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
IS_GPIO_PORT
#define IS_GPIO_PORT(GPIOx)
Definition: ald_gpio.h:193

◆ ald_gpio_read_port()

uint16_t ald_gpio_read_port ( GPIO_TypeDef * GPIOx )

Read the specified input port pin.

Parameters
GPIOx Where x can be (A–H) to select the GPIO peripheral.
Return values
The value;

Definition at line 493 of file ald_gpio.c.

494 {
495 assert_param(IS_GPIO_PORT(GPIOx));
496
497 return READ_REG(GPIOx->DIN);
498 }
assert_param
#define assert_param(x)
Definition: type.h:88
READ_REG
#define READ_REG(reg)
Definition: type.h:73
IS_GPIO_PORT
#define IS_GPIO_PORT(GPIOx)
Definition: ald_gpio.h:193

◆ ald_gpio_toggle_dir()

void ald_gpio_toggle_dir | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | pin
 | ) |  |

Turn over the direction.

Parameters
GPIOx | Where x can be (A–H) to select the GPIO peripheral.
pin | Specifies the pin to turn over.
Return values
None

Definition at line 432 of file ald_gpio.c.

433 {
434 uint32_t i, pos, mask, tmp, value;
435
436 assert_param(IS_GPIO_PORT(GPIOx));
437 assert_param(IS_GPIO_PIN(pin));
438
439 for (i = 0; i < 16; ++i) {
440 if (((pin >> i) & 0x1) == 0)
441 continue;
442
443 /* Get position and 2-bits mask */
444 pos = i << 1;
445 mask = 0x3 << pos;
446
447 /* Get the new direction */
448 tmp = READ_REG(GPIOx->MODE);
449 value = (tmp >> pos) & 0x3;
450
451 if ((value == 2) || (value == 3))
452 value = 1;
453 else if (value == 1) {
454 value = 2;
455 }
456 else {
457 continue; /* do nothing */
458 }
459
460 /* Set PIN mode */
461 tmp &= ~mask;
462 tmp |= (value << pos);
463 WRITE_REG(GPIOx->MODE, tmp);
464 }
465
466 return;
467 }
assert_param
#define assert_param(x)
Definition: type.h:88
READ_REG
#define READ_REG(reg)
Definition: type.h:73
IS_GPIO_PIN
#define IS_GPIO_PIN(x)
Definition: ald_gpio.h:192
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
IS_GPIO_PORT
#define IS_GPIO_PORT(GPIOx)
Definition: ald_gpio.h:193

◆ ald_gpio_toggle_pin()

void ald_gpio_toggle_pin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | pin
 | ) |  |

Turn over the select data.

Parameters
GPIOx | Where x can be (A–H) to select the GPIO peripheral.
pin | Specifies the pin to turn over.
Return values
None

Definition at line 417 of file ald_gpio.c.

418 {
419 assert_param(IS_GPIO_PORT(GPIOx));
420 assert_param(IS_GPIO_PIN(pin));
421
422 WRITE_REG(GPIOx->BIR, pin);
423 return;
424 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_GPIO_PIN
#define IS_GPIO_PIN(x)
Definition: ald_gpio.h:192
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
IS_GPIO_PORT
#define IS_GPIO_PORT(GPIOx)
Definition: ald_gpio.h:193

◆ ald_gpio_write_pin()

void ald_gpio_write_pin | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | pin,
 |  | uint8_t | val
 | ) |  |

Set or clear the select Pin data.

Parameters
GPIOx | Where x can be (A–H) to select the GPIO peripheral.
pin | The specified pin to be written.
val | The specifies value to be written.
Return values
None

Definition at line 398 of file ald_gpio.c.

399 {
400 assert_param(IS_GPIO_PORT(GPIOx));
401 assert_param(IS_GPIO_PIN(pin));
402
403 if ((val & (0x01)) == 0x00)
404 CLEAR_BIT(GPIOx->DOUT, pin);
405 else
406 SET_BIT(GPIOx->DOUT, pin);
407
408 return;
409 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_GPIO_PIN
#define IS_GPIO_PIN(x)
Definition: ald_gpio.h:192
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_GPIO_PORT
#define IS_GPIO_PORT(GPIOx)
Definition: ald_gpio.h:193

◆ ald_gpio_write_port()

void ald_gpio_write_port | ( | GPIO_TypeDef * | GPIOx,
 |  | uint16_t | val
 | ) |  |

Set or clear the select Pin data.

Parameters
GPIOx | Where x can be (A–H) to select the GPIO peripheral.
val | The specifies value to be written.
Return values
None

Definition at line 506 of file ald_gpio.c.

507 {
508 assert_param(IS_GPIO_PORT(GPIOx));
509
510 WRITE_REG(GPIOx->DOUT, val);
511 return;
512 }
assert_param
#define assert_param(x)
Definition: type.h:88
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
IS_GPIO_PORT
#define IS_GPIO_PORT(GPIOx)
Definition: ald_gpio.h:193


ALD User Manual: Control functions

Functions
Control functions
EASTSOFT ES32F3xx ALD » GPIO » GPIO Public Functions

EXTI Control functions. More...

Collaboration diagram for Control functions:

Functions

void | ald_gpio_exti_interrupt_config (uint16_t pin, exti_trigger_style_t style, type_func_t status)
Configure the interrupt according to the specified parameter. More...
flag_status_t | ald_gpio_exti_get_flag_status (uint16_t pin)
Get the Flag about external interrupt. More...
void | ald_gpio_exti_clear_flag_status (uint16_t pin)
Clear the external interrupt flag. More...

Detailed Description

EXTI Control functions.

===============================================================================
                      ##### Control functions #####
===============================================================================
 [..]
   This subsection provides a set of functions allowing to
   control external interrupt.

Function Documentation

◆ ald_gpio_exti_clear_flag_status()

void ald_gpio_exti_clear_flag_status ( uint16_t pin )

Clear the external interrupt flag.

Parameters
pin The pin which belong to external interrupt.
Return values
None

Definition at line 608 of file ald_gpio.c.

609 {
610 assert_param(IS_GPIO_PIN(pin));
611
612 WRITE_REG(EXTI->EXTICFR, pin);
613 return;
614 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_GPIO_PIN
#define IS_GPIO_PIN(x)
Definition: ald_gpio.h:192
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72

◆ ald_gpio_exti_get_flag_status()

flag_status_t ald_gpio_exti_get_flag_status ( uint16_t pin )

Get the Flag about external interrupt.

Parameters
pin The pin which belong to external interrupt.
Return values
Flag status
  • SET
  • RESET

Definition at line 593 of file ald_gpio.c.

594 {
595 assert_param(IS_GPIO_PIN(pin));
596
597 if (READ_BIT(EXTI->EXTIFLAG, pin))
598 return SET;
599
600 return RESET;
601 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
RESET
Definition: type.h:38
IS_GPIO_PIN
#define IS_GPIO_PIN(x)
Definition: ald_gpio.h:192
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69

◆ ald_gpio_exti_interrupt_config()

void ald_gpio_exti_interrupt_config | ( | uint16_t | pin,
 |  | exti_trigger_style_t | style,
 |  | type_func_t | status
 | ) |  |

Configure the interrupt according to the specified parameter.

Parameters
pin | The Pin which need to configure.
style | External interrupt trigger style.
status
  • ENABLE
  • DISABLE
Return values
None

Definition at line 541 of file ald_gpio.c.

542 {
543 assert_param(IS_GPIO_PIN(pin));
544 assert_param(IS_TRIGGER_STYLE(style));
545 assert_param(IS_FUNC_STATE(status));
546
547 if (status == ENABLE) {
548 if (style == EXTI_TRIGGER_RISING_EDGE) {
549 SET_BIT(EXTI->EXTIRER, pin);
550 }
551 else if (style == EXTI_TRIGGER_TRAILING_EDGE) {
552 SET_BIT(EXTI->EXTIFER, pin);
553 }
554 else if (style == EXTI_TRIGGER_BOTH_EDGE) {
555 SET_BIT(EXTI->EXTIRER, pin);
556 SET_BIT(EXTI->EXTIFER, pin);
557 }
558 else {
559 ; /* do nothing */
560 }
561
562 WRITE_REG(EXTI->EXTICFR, 0xffff);
563 SET_BIT(EXTI->EXTIEN, pin);
564 }
565 else {
566 if (style == EXTI_TRIGGER_RISING_EDGE) {
567 CLEAR_BIT(EXTI->EXTIRER, pin);
568 }
569 else if (style == EXTI_TRIGGER_TRAILING_EDGE) {
570 CLEAR_BIT(EXTI->EXTIFER, pin);
571 }
572 else if (style == EXTI_TRIGGER_BOTH_EDGE) {
573 CLEAR_BIT(EXTI->EXTIRER, pin);
574 CLEAR_BIT(EXTI->EXTIFER, pin);
575 }
576 else {
577 ; /* do nothing */
578 }
579
580 CLEAR_BIT(EXTI->EXTIEN, pin);
581 }
582
583 return;
584 }
ENABLE
Definition: type.h:49
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_TRIGGER_STYLE
#define IS_TRIGGER_STYLE(x)
Definition: ald_gpio.h:219
EXTI_TRIGGER_RISING_EDGE
Definition: ald_gpio.h:160
EXTI_TRIGGER_TRAILING_EDGE
Definition: ald_gpio.h:161
EXTI_TRIGGER_BOTH_EDGE
Definition: ald_gpio.h:162
IS_GPIO_PIN
#define IS_GPIO_PIN(x)
Definition: ald_gpio.h:192
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73


ALD User Manual: GPIO Public Macros

Macros
GPIO Public Macros
EASTSOFT ES32F3xx ALD » GPIO
Collaboration diagram for GPIO Public Macros:

Macros

#define | GPIO_PIN_0 (1U << 0)
#define | GPIO_PIN_1 (1U << 1)
#define | GPIO_PIN_2 (1U << 2)
#define | GPIO_PIN_3 (1U << 3)
#define | GPIO_PIN_4 (1U << 4)
#define | GPIO_PIN_5 (1U << 5)
#define | GPIO_PIN_6 (1U << 6)
#define | GPIO_PIN_7 (1U << 7)
#define | GPIO_PIN_8 (1U << 8)
#define | GPIO_PIN_9 (1U << 9)
#define | GPIO_PIN_10 (1U << 10)
#define | GPIO_PIN_11 (1U << 11)
#define | GPIO_PIN_12 (1U << 12)
#define | GPIO_PIN_13 (1U << 13)
#define | GPIO_PIN_14 (1U << 14)
#define | GPIO_PIN_15 (1U << 15)
#define | GPIO_PIN_ALL (0xFFFF)

Detailed Description

Macro Definition Documentation

◆ GPIO_PIN_0

#define GPIO_PIN_0 (1U << 0)

Definition at line 39 of file ald_gpio.h.

◆ GPIO_PIN_1

#define GPIO_PIN_1 (1U << 1)

Definition at line 40 of file ald_gpio.h.

◆ GPIO_PIN_10

#define GPIO_PIN_10 (1U << 10)

Definition at line 49 of file ald_gpio.h.

◆ GPIO_PIN_11

#define GPIO_PIN_11 (1U << 11)

Definition at line 50 of file ald_gpio.h.

◆ GPIO_PIN_12

#define GPIO_PIN_12 (1U << 12)

Definition at line 51 of file ald_gpio.h.

◆ GPIO_PIN_13

#define GPIO_PIN_13 (1U << 13)

Definition at line 52 of file ald_gpio.h.

◆ GPIO_PIN_14

#define GPIO_PIN_14 (1U << 14)

Definition at line 53 of file ald_gpio.h.

◆ GPIO_PIN_15

#define GPIO_PIN_15 (1U << 15)

Definition at line 54 of file ald_gpio.h.

◆ GPIO_PIN_2

#define GPIO_PIN_2 (1U << 2)

Definition at line 41 of file ald_gpio.h.

◆ GPIO_PIN_3

#define GPIO_PIN_3 (1U << 3)

Definition at line 42 of file ald_gpio.h.

◆ GPIO_PIN_4

#define GPIO_PIN_4 (1U << 4)

Definition at line 43 of file ald_gpio.h.

◆ GPIO_PIN_5

#define GPIO_PIN_5 (1U << 5)

Definition at line 44 of file ald_gpio.h.

◆ GPIO_PIN_6

#define GPIO_PIN_6 (1U << 6)

Definition at line 45 of file ald_gpio.h.

◆ GPIO_PIN_7

#define GPIO_PIN_7 (1U << 7)

Definition at line 46 of file ald_gpio.h.

◆ GPIO_PIN_8

#define GPIO_PIN_8 (1U << 8)

Definition at line 47 of file ald_gpio.h.

◆ GPIO_PIN_9

#define GPIO_PIN_9 (1U << 9)

Definition at line 48 of file ald_gpio.h.

◆ GPIO_PIN_ALL

#define GPIO_PIN_ALL (0xFFFF)

Definition at line 55 of file ald_gpio.h.


ALD User Manual: GPIO Public Types

Data Structures | Enumerations
GPIO Public Types
EASTSOFT ES32F3xx ALD » GPIO
Collaboration diagram for GPIO Public Types:

Data Structures

struct | gpio_init_t
GPIO Init Structure definition. More...
struct | exti_init_t
EXTI Init Structure definition. More...

Enumerations

enum | gpio_mode_t { GPIO_MODE_CLOSE = 0x0U, GPIO_MODE_INPUT = 0x1U, GPIO_MODE_OUTPUT = 0x2U }
GPIO mode. More...
enum | gpio_odos_t { GPIO_PUSH_PULL = 0x0U, GPIO_OPEN_DRAIN = 0x2U, GPIO_OPEN_SOURCE = 0x3U }
GPIO open-drain or push-pull. More...
enum | gpio_push_t { GPIO_FLOATING = 0x0U, GPIO_PUSH_UP = 0x1U, GPIO_PUSH_DOWN = 0x2U, GPIO_PUSH_UP_DOWN = 0x3U }
GPIO push-up or push-down. More...
enum | gpio_out_drive_t { GPIO_OUT_DRIVE_0_1 = 0x0U, GPIO_OUT_DRIVE_1 = 0x1U, GPIO_OUT_DRIVE_6 = 0x2U, GPIO_OUT_DRIVE_20 = 0x3U }
GPIO output drive. More...
enum | gpio_filter_t { GPIO_FILTER_DISABLE = 0x0U, GPIO_FILTER_ENABLE = 0x1U }
GPIO filter. More...
enum | gpio_type_t { GPIO_TYPE_CMOS = 0x0U, GPIO_TYPE_TTL = 0x1U }
GPIO type. More...
enum gpio_func_t {
GPIO_FUNC_0 = 0U, GPIO_FUNC_1 = 1U, GPIO_FUNC_2 = 2U, GPIO_FUNC_3 = 3U,
GPIO_FUNC_4 = 4U, GPIO_FUNC_5 = 5U, GPIO_FUNC_6 = 6U, GPIO_FUNC_7 = 7U
}
GPIO functions. More...
enum | exti_trigger_style_t { EXTI_TRIGGER_RISING_EDGE = 0U, EXTI_TRIGGER_TRAILING_EDGE = 1U, EXTI_TRIGGER_BOTH_EDGE = 2U }
EXTI trigger style. More...
enum | exti_filter_clock_t { EXTI_FILTER_CLOCK_10K = 0U, EXTI_FILTER_CLOCK_32K = 1U }
EXTI filter clock select. More...

Detailed Description

Enumeration Type Documentation

◆ exti_filter_clock_t

enum exti_filter_clock_t

EXTI filter clock select.

Enumerator
EXTI_FILTER_CLOCK_10K | cks = 10KHz
EXTI_FILTER_CLOCK_32K | cks = 32KHz

Definition at line 168 of file ald_gpio.h.

168 {
169 EXTI_FILTER_CLOCK_10K = 0U,
170 EXTI_FILTER_CLOCK_32K = 1U,
171 } exti_filter_clock_t;
EXTI_FILTER_CLOCK_32K
Definition: ald_gpio.h:170
EXTI_FILTER_CLOCK_10K
Definition: ald_gpio.h:169
exti_filter_clock_t
exti_filter_clock_t
EXTI filter clock select.
Definition: ald_gpio.h:168

◆ exti_trigger_style_t

enum exti_trigger_style_t

EXTI trigger style.

Enumerator
EXTI_TRIGGER_RISING_EDGE | Rising edge trigger
EXTI_TRIGGER_TRAILING_EDGE | Trailing edge trigger
EXTI_TRIGGER_BOTH_EDGE | Rising and trailing edge trigger

Definition at line 159 of file ald_gpio.h.

159 {
160 EXTI_TRIGGER_RISING_EDGE = 0U,
161 EXTI_TRIGGER_TRAILING_EDGE = 1U,
162 EXTI_TRIGGER_BOTH_EDGE = 2U,
163 } exti_trigger_style_t;
EXTI_TRIGGER_RISING_EDGE
Definition: ald_gpio.h:160
exti_trigger_style_t
exti_trigger_style_t
EXTI trigger style.
Definition: ald_gpio.h:159
EXTI_TRIGGER_TRAILING_EDGE
Definition: ald_gpio.h:161
EXTI_TRIGGER_BOTH_EDGE
Definition: ald_gpio.h:162

◆ gpio_filter_t

enum gpio_filter_t

GPIO filter.

Enumerator
GPIO_FILTER_DISABLE | Disable filter
GPIO_FILTER_ENABLE | Enable filter

Definition at line 106 of file ald_gpio.h.

106 {
107 GPIO_FILTER_DISABLE = 0x0U,
108 GPIO_FILTER_ENABLE = 0x1U,
109 } gpio_filter_t;
GPIO_FILTER_DISABLE
Definition: ald_gpio.h:107
gpio_filter_t
gpio_filter_t
GPIO filter.
Definition: ald_gpio.h:106
GPIO_FILTER_ENABLE
Definition: ald_gpio.h:108

◆ gpio_func_t

enum gpio_func_t

GPIO functions.

Enumerator
GPIO_FUNC_0 | function #0
GPIO_FUNC_1 | function #1
GPIO_FUNC_2 | function #2
GPIO_FUNC_3 | function #3
GPIO_FUNC_4 | function #4
GPIO_FUNC_5 | function #5
GPIO_FUNC_6 | function #6
GPIO_FUNC_7 | function #7

Definition at line 122 of file ald_gpio.h.

122 {
123 GPIO_FUNC_0 = 0U,
124 GPIO_FUNC_1 = 1U,
125 GPIO_FUNC_2 = 2U,
126 GPIO_FUNC_3 = 3U,
127 GPIO_FUNC_4 = 4U,
128 GPIO_FUNC_5 = 5U,
129 GPIO_FUNC_6 = 6U,
130 GPIO_FUNC_7 = 7U,
131 } gpio_func_t;
gpio_func_t
gpio_func_t
GPIO functions.
Definition: ald_gpio.h:122
GPIO_FUNC_3
Definition: ald_gpio.h:126
GPIO_FUNC_2
Definition: ald_gpio.h:125
GPIO_FUNC_1
Definition: ald_gpio.h:124
GPIO_FUNC_0
Definition: ald_gpio.h:123
GPIO_FUNC_7
Definition: ald_gpio.h:130
GPIO_FUNC_6
Definition: ald_gpio.h:129
GPIO_FUNC_5
Definition: ald_gpio.h:128
GPIO_FUNC_4
Definition: ald_gpio.h:127

◆ gpio_mode_t

enum gpio_mode_t

GPIO mode.

Enumerator
GPIO_MODE_CLOSE | Digital close Analog open
GPIO_MODE_INPUT | Input
GPIO_MODE_OUTPUT | Output

Definition at line 68 of file ald_gpio.h.

68 {
69 GPIO_MODE_CLOSE = 0x0U,
70 GPIO_MODE_INPUT = 0x1U,
71 GPIO_MODE_OUTPUT = 0x2U,
72 } gpio_mode_t;
gpio_mode_t
gpio_mode_t
GPIO mode.
Definition: ald_gpio.h:68
GPIO_MODE_CLOSE
Definition: ald_gpio.h:69
GPIO_MODE_OUTPUT
Definition: ald_gpio.h:71
GPIO_MODE_INPUT
Definition: ald_gpio.h:70

◆ gpio_odos_t

enum gpio_odos_t

GPIO open-drain or push-pull.

Enumerator
GPIO_PUSH_PULL | Push-Pull
GPIO_OPEN_DRAIN | Open-Drain. Can't output high level
GPIO_OPEN_SOURCE | Open-Source. Can't output low level

Definition at line 77 of file ald_gpio.h.

77 {
78 GPIO_PUSH_PULL = 0x0U,
79 GPIO_OPEN_DRAIN = 0x2U,
80 GPIO_OPEN_SOURCE = 0x3U,
81 } gpio_odos_t;
gpio_odos_t
gpio_odos_t
GPIO open-drain or push-pull.
Definition: ald_gpio.h:77
GPIO_OPEN_DRAIN
Definition: ald_gpio.h:79
GPIO_PUSH_PULL
Definition: ald_gpio.h:78
GPIO_OPEN_SOURCE
Definition: ald_gpio.h:80

◆ gpio_out_drive_t

enum gpio_out_drive_t

GPIO output drive.

Enumerator
GPIO_OUT_DRIVE_0_1 | 0.1mA
GPIO_OUT_DRIVE_1 | 1mA
GPIO_OUT_DRIVE_6 | 6mA
GPIO_OUT_DRIVE_20 | 20mA

Definition at line 96 of file ald_gpio.h.

96 {
97 GPIO_OUT_DRIVE_0_1 = 0x0U,
98 GPIO_OUT_DRIVE_1 = 0x1U,
99 GPIO_OUT_DRIVE_6 = 0x2U,
100 GPIO_OUT_DRIVE_20 = 0x3U,
101 } gpio_out_drive_t;
GPIO_OUT_DRIVE_20
Definition: ald_gpio.h:100
GPIO_OUT_DRIVE_0_1
Definition: ald_gpio.h:97
gpio_out_drive_t
gpio_out_drive_t
GPIO output drive.
Definition: ald_gpio.h:96
GPIO_OUT_DRIVE_1
Definition: ald_gpio.h:98
GPIO_OUT_DRIVE_6
Definition: ald_gpio.h:99

◆ gpio_push_t

enum gpio_push_t

GPIO push-up or push-down.

Enumerator
GPIO_FLOATING | Floating
GPIO_PUSH_UP | Push-Up
GPIO_PUSH_DOWN | Push-Down
GPIO_PUSH_UP_DOWN | Push-Up and Push-Down

Definition at line 86 of file ald_gpio.h.

86 {
87 GPIO_FLOATING = 0x0U,
88 GPIO_PUSH_UP = 0x1U,
89 GPIO_PUSH_DOWN = 0x2U,
90 GPIO_PUSH_UP_DOWN = 0x3U,
91 } gpio_push_t;
gpio_push_t
gpio_push_t
GPIO push-up or push-down.
Definition: ald_gpio.h:86
GPIO_PUSH_DOWN
Definition: ald_gpio.h:89
GPIO_PUSH_UP_DOWN
Definition: ald_gpio.h:90
GPIO_FLOATING
Definition: ald_gpio.h:87
GPIO_PUSH_UP
Definition: ald_gpio.h:88

◆ gpio_type_t

enum gpio_type_t

GPIO type.

Enumerator
GPIO_TYPE_CMOS | CMOS Type
GPIO_TYPE_TTL | TTL Type

Definition at line 114 of file ald_gpio.h.

114 {
115 GPIO_TYPE_CMOS = 0x0U,
116 GPIO_TYPE_TTL = 0x1U,
117 } gpio_type_t;
gpio_type_t
gpio_type_t
GPIO type.
Definition: ald_gpio.h:114
GPIO_TYPE_TTL
Definition: ald_gpio.h:116
GPIO_TYPE_CMOS
Definition: ald_gpio.h:115


ALD User Manual: gpio_init_t Struct Reference

Data Fields
gpio_init_t Struct Reference
EASTSOFT ES32F3xx ALD » GPIO » GPIO Public Types

GPIO Init Structure definition. More...

#include <ald_gpio.h>

Data Fields

gpio_mode_t mode
gpio_odos_t odos
gpio_push_t pupd
gpio_out_drive_t podrv
gpio_out_drive_t nodrv
gpio_filter_t flt
gpio_type_t type
gpio_func_t func

Detailed Description

GPIO Init Structure definition.

Definition at line 137 of file ald_gpio.h.

Field Documentation

◆ flt

gpio_filter_t flt

Specifies the input filter for the selected pins. This parameter can be a value of gpio_filter_t

Definition at line 148 of file ald_gpio.h.

◆ func

gpio_func_t func

Specifies the function for the selected pins. This parameter can be a value of gpio_func_t

Definition at line 152 of file ald_gpio.h.

◆ mode

gpio_mode_t mode

Specifies the operating mode for the selected pins. This parameter can be any value of gpio_mode_t

Definition at line 138 of file ald_gpio.h.

◆ nodrv

gpio_out_drive_t nodrv

Specifies the output N-MOS driver for the selected pins. This parameter can be a value of gpio_out_drive_t

Definition at line 146 of file ald_gpio.h.

◆ odos

gpio_odos_t odos

Specifies the Open-Drain or Push-Pull for the selected pins. This parameter can be a value of gpio_odos_t

Definition at line 140 of file ald_gpio.h.

◆ podrv

gpio_out_drive_t podrv

Specifies the output P-MOS driver for the selected pins. This parameter can be a value of gpio_out_drive_t

Definition at line 144 of file ald_gpio.h.

◆ pupd

gpio_push_t pupd

Specifies the Pull-up or Pull-Down for the selected pins. This parameter can be a value of gpio_push_t

Definition at line 142 of file ald_gpio.h.

◆ type

gpio_type_t type

Specifies the type for the selected pins. This parameter can be a value of gpio_type_t

Definition at line 150 of file ald_gpio.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_gpio.h


ALD User Manual: exti_init_t Struct Reference

Data Fields
exti_init_t Struct Reference
EASTSOFT ES32F3xx ALD » GPIO » GPIO Public Types

EXTI Init Structure definition. More...

#include <ald_gpio.h>

Data Fields

type_func_t filter
exti_filter_clock_t cks
uint8_t filter_time

Detailed Description

EXTI Init Structure definition.

Definition at line 176 of file ald_gpio.h.

Field Documentation

◆ cks

exti_filter_clock_t cks

Filter clock select.

Definition at line 178 of file ald_gpio.h.

◆ filter

type_func_t filter

Enable filter.

Definition at line 177 of file ald_gpio.h.

◆ filter_time

uint8_t filter_time

Filter duration

Definition at line 179 of file ald_gpio.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_gpio.h


ALD User Manual: GPIO Private Macros

Macros
GPIO Private Macros
EASTSOFT ES32F3xx ALD » GPIO
Collaboration diagram for GPIO Private Macros:

Macros

#define | PIN_MASK 0xFFFFU
#define | UNLOCK_KEY 0x55AAU
#define | IS_GPIO_PIN(x) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0))
#define | IS_GPIO_PORT(GPIOx)
#define | IS_GPIO_MODE(x)
#define | IS_GPIO_ODOS(x)
#define | IS_GPIO_PUPD(x)
#define | IS_GPIO_ODRV(x)
#define | IS_GPIO_FLT(x)
#define | IS_GPIO_TYPE(x)
#define | IS_TRIGGER_STYLE(x)
#define | IS_EXTI_FLTCKS_TYPE(x)
#define | IS_GPIO_FUNC(x) ((x) <= 7)

Detailed Description

Macro Definition Documentation

◆ IS_EXTI_FLTCKS_TYPE

#define IS_EXTI_FLTCKS_TYPE ( x )
Value:
(((x) == EXTI_FILTER_CLOCK_10K) || \
((x) == EXTI_FILTER_CLOCK_32K))
EXTI_FILTER_CLOCK_32K
Definition: ald_gpio.h:170
EXTI_FILTER_CLOCK_10K
Definition: ald_gpio.h:169

Definition at line 222 of file ald_gpio.h.

◆ IS_GPIO_FLT

#define IS_GPIO_FLT ( x )
Value:
(((x) == GPIO_FILTER_DISABLE) || \
((x) == GPIO_FILTER_ENABLE))
GPIO_FILTER_DISABLE
Definition: ald_gpio.h:107
GPIO_FILTER_ENABLE
Definition: ald_gpio.h:108

Definition at line 215 of file ald_gpio.h.

◆ IS_GPIO_FUNC

#define IS_GPIO_FUNC ( x ) ((x) <= 7)

Definition at line 224 of file ald_gpio.h.

◆ IS_GPIO_MODE

#define IS_GPIO_MODE ( x )
Value:
(((x) == GPIO_MODE_CLOSE) || \
((x) == GPIO_MODE_INPUT) || \
((x) == GPIO_MODE_OUTPUT))
GPIO_MODE_CLOSE
Definition: ald_gpio.h:69
GPIO_MODE_OUTPUT
Definition: ald_gpio.h:71
GPIO_MODE_INPUT
Definition: ald_gpio.h:70

Definition at line 201 of file ald_gpio.h.

◆ IS_GPIO_ODOS

#define IS_GPIO_ODOS ( x )
Value:
(((x) == GPIO_PUSH_PULL) || \
((x) == GPIO_OPEN_DRAIN) || \
((x) == GPIO_OPEN_SOURCE))
GPIO_OPEN_DRAIN
Definition: ald_gpio.h:79
GPIO_PUSH_PULL
Definition: ald_gpio.h:78
GPIO_OPEN_SOURCE
Definition: ald_gpio.h:80

Definition at line 204 of file ald_gpio.h.

◆ IS_GPIO_ODRV

#define IS_GPIO_ODRV ( x )
Value:
(((x) == GPIO_OUT_DRIVE_0_1) || \
((x) == GPIO_OUT_DRIVE_1) || \
((x) == GPIO_OUT_DRIVE_6) || \
((x) == GPIO_OUT_DRIVE_20))
GPIO_OUT_DRIVE_20
Definition: ald_gpio.h:100
GPIO_OUT_DRIVE_0_1
Definition: ald_gpio.h:97
GPIO_OUT_DRIVE_1
Definition: ald_gpio.h:98
GPIO_OUT_DRIVE_6
Definition: ald_gpio.h:99

Definition at line 211 of file ald_gpio.h.

◆ IS_GPIO_PIN

#define IS_GPIO_PIN ( x ) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0))

Definition at line 192 of file ald_gpio.h.

◆ IS_GPIO_PORT

#define IS_GPIO_PORT ( GPIOx )
Value:
((GPIOx == GPIOA) || \
(GPIOx == GPIOB) || \
(GPIOx == GPIOC) || \
(GPIOx == GPIOD) || \
(GPIOx == GPIOE) || \
(GPIOx == GPIOF) || \
(GPIOx == GPIOG) || \
(GPIOx == GPIOH))

Definition at line 193 of file ald_gpio.h.

◆ IS_GPIO_PUPD

#define IS_GPIO_PUPD ( x )
Value:
(((x) == GPIO_FLOATING) || \
((x) == GPIO_PUSH_UP) || \
((x) == GPIO_PUSH_DOWN) || \
((x) == GPIO_PUSH_UP_DOWN))
GPIO_PUSH_DOWN
Definition: ald_gpio.h:89
GPIO_PUSH_UP_DOWN
Definition: ald_gpio.h:90
GPIO_FLOATING
Definition: ald_gpio.h:87
GPIO_PUSH_UP
Definition: ald_gpio.h:88

Definition at line 207 of file ald_gpio.h.

◆ IS_GPIO_TYPE

#define IS_GPIO_TYPE ( x )
Value:
(((x) == GPIO_TYPE_TTL) || \
((x) == GPIO_TYPE_CMOS))
GPIO_TYPE_TTL
Definition: ald_gpio.h:116
GPIO_TYPE_CMOS
Definition: ald_gpio.h:115

Definition at line 217 of file ald_gpio.h.

◆ IS_TRIGGER_STYLE

#define IS_TRIGGER_STYLE ( x )
Value:
(((x) == EXTI_TRIGGER_RISING_EDGE) || \
((x) == EXTI_TRIGGER_TRAILING_EDGE) || \
((x) == EXTI_TRIGGER_BOTH_EDGE))
EXTI_TRIGGER_RISING_EDGE
Definition: ald_gpio.h:160
EXTI_TRIGGER_TRAILING_EDGE
Definition: ald_gpio.h:161
EXTI_TRIGGER_BOTH_EDGE
Definition: ald_gpio.h:162

Definition at line 219 of file ald_gpio.h.

◆ PIN_MASK

#define PIN_MASK 0xFFFFU

Definition at line 189 of file ald_gpio.h.

◆ UNLOCK_KEY

#define UNLOCK_KEY 0x55AAU

Definition at line 190 of file ald_gpio.h.


ALD User Manual: I2C

Modules
I2C
EASTSOFT ES32F3xx ALD

I2C module driver. More...

Collaboration diagram for I2C:

Modules

I2C Public functions
I2C Public Types
I2C Public Macros
I2C Private Macros
I2C Private Constants
I2C Private Functions

Detailed Description

I2C module driver.


ALD User Manual: I2C Public functions

Modules
I2C Public functions
EASTSOFT ES32F3xx ALD » I2C
Collaboration diagram for I2C Public functions:

Modules

Initialization and de-initialization functions
Initialization and Configuration functions.
Input and Output operation functions
Data transfers functions.
Peripheral state and Errors functions
Peripheral state and Errors functions.
IRQ Handler and Callbacks
I2C Private Functions

Detailed Description


ALD User Manual: Initialization and de-initialization functions

Functions
Initialization and de-initialization functions
EASTSOFT ES32F3xx ALD » I2C » I2C Public functions

Initialization and Configuration functions. More...

Collaboration diagram for Initialization and de-initialization functions:

Functions

ald_status_t | i2c_speed_init (i2c_handle_t *hperh, uint32_t freqrange)
I2C Configuration Speed function. More...
ald_status_t | ald_i2c_init (i2c_handle_t *hperh)
Initializes the I2C according to the specified parameters in the i2c_init_t and initialize the associated handle. More...
ald_status_t | ald_i2c_reset (i2c_handle_t *hperh)
DeInitialize the I2C peripheral. More...

Detailed Description

Initialization and Configuration functions.

 ===============================================================================
              ##### Initialization and de-initialization functions #####
 ===============================================================================
    [..]  This subsection provides a set of functions allowing to initialize and
          de-initialiaze the I2Cx peripheral:

      (+) Call the function ald_i2c_init() to configure the selected device with
          the selected configuration:
        (++) Communication Speed
        (++) Addressing mode
        (++) Own Address 1
        (++) Dual Addressing mode
        (++) Own Address 2
        (++) General call mode
        (++) Nostretch mode

      (+) Call the function ald_i2c_reset() to restore the default configuration
          of the selected I2Cx periperal.

Function Documentation

◆ ald_i2c_init()

ald_status_t ald_i2c_init ( i2c_handle_t * hperh )

Initializes the I2C according to the specified parameters in the i2c_init_t and initialize the associated handle.

Parameters
hperh Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
Return values
Status,see ald_status_t.

Definition at line 319 of file ald_i2c.c.

320 {
321 uint32_t freqrange = ald_cmu_get_pclk1_clock();
322
323 if (hperh == NULL)
324 return ERROR;
325
326 /* Check the parameters */
327 assert_param(IS_I2C_CLOCK_SPEED(hperh->init.clk_speed));
328 assert_param(IS_I2C_ADDRESSING_MODE(hperh->init.addr_mode));
329 assert_param(IS_I2C_GENERAL_CALL(hperh->init.general_call));
330 assert_param(IS_I2C_NO_STRETCH(hperh->init.no_stretch));
331 assert_param(IS_I2C_MODULE(hperh->init.module));
332
333 if (hperh->state == I2C_STATE_RESET)
334 hperh->lock = UNLOCK;
335
336 hperh->state = I2C_STATE_BUSY;
337
338 I2C_DISABLE(hperh);
339
340 i2c_speed_init(hperh, freqrange);
341 MODIFY_REG(hperh->perh->CON1, I2C_CON1_NOSTRETCH_MSK, (hperh->init.no_stretch) << I2C_CON1_NOSTRETCH_POS);
342 MODIFY_REG(hperh->perh->CON1, I2C_CON1_GCEN_MSK, (hperh->init.general_call) << I2C_CON1_GCEN_POS);
343
344 if (hperh->init.dual_addr == I2C_DUALADDR_ENABLE) {
345 CLEAR_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK);
346 MODIFY_REG(hperh->perh->ADDR1, I2C_ADDR1_OA1_MSK, (hperh->init.own_addr1 & 0x3FF) << I2C_ADDR1_OA1_POSS);
347 SET_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK);
348
349 CLEAR_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK);
350 MODIFY_REG(hperh->perh->ADDR2, I2C_ADDR2_OA2_MSK, (hperh->init.own_addr2 & 0x7F) << I2C_ADDR2_OA2_POSS);
351 SET_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK);
352 } else {
353 if (hperh->init.addr_mode == I2C_ADDR_10BIT) {
354 CLEAR_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK);
355 SET_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1MODE_MSK);
356 MODIFY_REG(hperh->perh->ADDR1, I2C_ADDR1_OA1_MSK, (hperh->init.own_addr1 & 0x3FF) << I2C_ADDR1_OA1_POSS);
357 SET_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK);
358 }
359 else {
360 CLEAR_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK);
361 MODIFY_REG(hperh->perh->ADDR2, I2C_ADDR2_OA2_MSK, (hperh->init.own_addr2 & 0x7F) << I2C_ADDR2_OA2_POSS);
362 SET_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK);
363 }
364 }
365
366 I2C_ENABLE(hperh);
367
368 hperh->error_code = I2C_ERROR_NONE;
369 hperh->state = I2C_STATE_READY;
370 hperh->mode = I2C_MODE_NONE;
371
372 return OK;
373 }
i2c_init_t::clk_speed
uint32_t clk_speed
Definition: ald_i2c.h:257
OK
Definition: utils.h:55
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_I2C_NO_STRETCH
#define IS_I2C_NO_STRETCH(STRETCH)
Definition: ald_i2c.h:329
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
i2c_init_t::module
i2c_module_t module
Definition: ald_i2c.h:256
I2C_DISABLE
#define I2C_DISABLE(x)
Definition: ald_i2c.h:311
i2c_init_t::no_stretch
i2c_nostretch_t no_stretch
Definition: ald_i2c.h:263
i2c_handle_s::init
i2c_init_t init
Definition: ald_i2c.h:271
I2C_ENABLE
#define I2C_ENABLE(x)
Definition: ald_i2c.h:310
i2c_init_t::dual_addr
i2c_dual_addr_t dual_addr
Definition: ald_i2c.h:260
i2c_handle_s::lock
lock_state_t lock
Definition: ald_i2c.h:279
UNLOCK
Definition: type.h:59
I2C_STATE_BUSY
Definition: ald_i2c.h:64
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_init_t::general_call
i2c_general_addr_t general_call
Definition: ald_i2c.h:262
I2C_ADDR_10BIT
Definition: ald_i2c.h:76
IS_I2C_ADDRESSING_MODE
#define IS_I2C_ADDRESSING_MODE(ADDRESS)
Definition: ald_i2c.h:321
I2C_STATE_RESET
Definition: ald_i2c.h:62
IS_I2C_CLOCK_SPEED
#define IS_I2C_CLOCK_SPEED(SPEED)
Definition: ald_i2c.h:331
I2C_DUALADDR_ENABLE
Definition: ald_i2c.h:84
IS_I2C_GENERAL_CALL
#define IS_I2C_GENERAL_CALL(CALL)
Definition: ald_i2c.h:325
i2c_speed_init
ald_status_t i2c_speed_init(i2c_handle_t *hperh, uint32_t freqrange)
I2C Configuration Speed function.
Definition: ald_i2c.c:254
ald_cmu_get_pclk1_clock
uint32_t ald_cmu_get_pclk1_clock(void)
Get APB1 clock.
Definition: ald_cmu.c:627
i2c_init_t::addr_mode
i2c_addr_t addr_mode
Definition: ald_i2c.h:259
i2c_init_t::own_addr2
uint32_t own_addr2
Definition: ald_i2c.h:261
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_I2C_MODULE
#define IS_I2C_MODULE(x)
Definition: ald_i2c.h:320
I2C_MODE_NONE
Definition: ald_i2c.h:115
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
i2c_init_t::own_addr1
uint32_t own_addr1
Definition: ald_i2c.h:258
ERROR
Definition: utils.h:56
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ ald_i2c_reset()

ald_status_t ald_i2c_reset ( i2c_handle_t * hperh )

DeInitialize the I2C peripheral.

Parameters
hperh Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
Return values
Status,see ald_status_t.

Definition at line 381 of file ald_i2c.c.

382 {
383 if (hperh == NULL)
384 return ERROR;
385
386 I2C_DISABLE(hperh);
387
388 hperh->error_code = I2C_ERROR_NONE;
389 hperh->state = I2C_STATE_READY;
390 hperh->mode = I2C_MODE_NONE;
391
392 __UNLOCK(hperh);
393
394 WRITE_REG(hperh->perh->CON1, 0);
395 WRITE_REG(hperh->perh->CON2, 0);
396 WRITE_REG(hperh->perh->ADDR1, 0);
397 WRITE_REG(hperh->perh->ADDR2, 0);
398 WRITE_REG(hperh->perh->TIMINGR, 0);
399 WRITE_REG(hperh->perh->TIMEOUTR, 0);
400 WRITE_REG(hperh->perh->FCON, 0);
401 WRITE_REG(hperh->perh->TXDATA, 0);
402 WRITE_REG(hperh->perh->IDR, I2C_FLAG_MASK);
403 WRITE_REG(hperh->perh->ICR, I2C_FLAG_MASK);
404
405 I2C_ENABLE(hperh);
406
407 return OK;
408 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
I2C_DISABLE
#define I2C_DISABLE(x)
Definition: ald_i2c.h:311
I2C_ENABLE
#define I2C_ENABLE(x)
Definition: ald_i2c.h:310
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
I2C_FLAG_MASK
#define I2C_FLAG_MASK
Definition: ald_i2c.h:300
I2C_MODE_NONE
Definition: ald_i2c.h:115
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
ERROR
Definition: utils.h:56
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ i2c_speed_init()

ald_status_t i2c_speed_init | ( | i2c_handle_t * | hperh,
 |  | uint32_t | freqrange
 | ) |  |

I2C Configuration Speed function.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains. the configuration information for the I2C speed.
freqrange | I2C Peripheral bus clock
Return values
Status,see ald_status_t.

Definition at line 254 of file ald_i2c.c.

255 {
256 float Tsync = 0;
257 float Tscl = 0;
258 float Tfre = 0;
259 uint32_t Tper = 0;
260 uint32_t presc = 0;
261 uint32_t tmp = 0;
262
263 if (hperh->init.module == I2C_MODULE_SLAVE) {
264 hperh->init.clk_speed = 450000;
265 }
266
267 if (hperh->init.clk_speed <= 100000) {
268 tmp = freqrange / 4000000;
269 freqrange = 4000000;
270 } else {
271 tmp = freqrange / 8000000;
272 freqrange = 8000000;
273 }
274
275 Tscl = 1000.0 / (hperh->init.clk_speed / 1000000.0);
276 Tfre = 1000.0 / I2C_FREQ_RANGE(freqrange);
277
278 Tsync = (READ_BITS(hperh->perh->CON2, I2C_CON1_DNF_MSK, I2C_CON1_DNF_POSS) + 2) * 2 * Tfre;
279
280 Tper = (uint32_t)((Tscl - Tsync) / Tfre);
281
282 while (Tper > 512) {
283 Tper = Tper - 512;
284 presc++;
285 }
286
287 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_PRESC_MSK, (presc + tmp ) << I2C_TIMINGR_PRESC_POSS);
288
289 if (hperh->init.clk_speed <= I2C_STANDARD_MODE_MAX_CLK) {
290 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SDADEL_MSK, 2 << I2C_TIMINGR_SDADEL_POSS);
291 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, 4 << I2C_TIMINGR_SCLDEL_POSS);
292 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLH_MSK, (((Tper - 2) / 2) - 4) << I2C_TIMINGR_SCLH_POSS);
293 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLL_MSK, (((Tper - 2) / 2) + 4) << I2C_TIMINGR_SCLL_POSS);
294 }
295 else {
296 if (hperh->init.clk_speed <= I2C_FAST_MODE_MAX_CLK) {
297 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SDADEL_MSK, 2 << I2C_TIMINGR_SDADEL_POSS);
298 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, 3 << I2C_TIMINGR_SCLDEL_POSS);
299 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLH_MSK, (((Tper - 2) / 2) - 6) << I2C_TIMINGR_SCLH_POSS);
300 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLL_MSK, (((Tper - 2) / 2) + 6) << I2C_TIMINGR_SCLL_POSS);
301 }
302 else {
303 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SDADEL_MSK, 0 << I2C_TIMINGR_SDADEL_POSS);
304 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, 1 << I2C_TIMINGR_SCLDEL_POSS);
305 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLH_MSK, (((Tper - 2) / 2) - 3) << I2C_TIMINGR_SCLH_POSS);
306 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLL_MSK, (((Tper - 2) / 2) + 3) << I2C_TIMINGR_SCLL_POSS);
307 }
308 }
309
310 return OK;
311 }
i2c_init_t::clk_speed
uint32_t clk_speed
Definition: ald_i2c.h:257
OK
Definition: utils.h:55
I2C_FREQ_RANGE
#define I2C_FREQ_RANGE(__PCLK__)
Definition: ald_i2c.h:332
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
i2c_init_t::module
i2c_module_t module
Definition: ald_i2c.h:256
i2c_handle_s::init
i2c_init_t init
Definition: ald_i2c.h:271
I2C_MODULE_SLAVE
Definition: ald_i2c.h:198
I2C_FAST_MODE_MAX_CLK
Definition: ald_i2c.h:126
I2C_STANDARD_MODE_MAX_CLK
Definition: ald_i2c.h:125
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270


ALD User Manual: Input and Output operation functions

Functions
Input and Output operation functions
EASTSOFT ES32F3xx ALD » I2C » I2C Public functions

Data transfers functions. More...

Collaboration diagram for Input and Output operation functions:

Functions

ald_status_t | ald_i2c_master_send (i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size, uint32_t timeout)
Transmits in master mode an amount of data in blocking mode. More...
ald_status_t | ald_i2c_master_recv (i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size, uint32_t timeout)
Receives in master mode an amount of data in blocking mode. More...
ald_status_t | ald_i2c_slave_send (i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Transmits in slave mode an amount of data in blocking mode. More...
ald_status_t | ald_i2c_slave_recv (i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Receive in slave mode an amount of data in blocking mode. More...
ald_status_t | ald_i2c_master_send_by_it (i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt. More...
ald_status_t | ald_i2c_master_recv_by_it (i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size)
Receive in master mode an amount of data in non-blocking mode with Interrupt. More...
ald_status_t | ald_i2c_slave_send_by_it (i2c_handle_t *hperh, uint8_t *buf, uint32_t size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt. More...
ald_status_t | ald_i2c_slave_recv_by_it (i2c_handle_t *hperh, uint8_t *buf, uint32_t size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt. More...
ald_status_t | ald_i2c_master_send_by_dma (i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint8_t size, uint8_t channel)
Transmit in master mode an amount of data in non-blocking mode with DMA. More...
ald_status_t | ald_i2c_master_recv_by_dma (i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint8_t size, uint8_t channel)
Receive in master mode an amount of data in non-blocking mode with DMA. More...
ald_status_t | ald_i2c_slave_send_by_dma (i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel)
Transmit in slave mode an amount of data in non-blocking mode with DMA. More...
ald_status_t | ald_i2c_slave_recv_by_dma (i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel)
Receive in slave mode an amount of data in non-blocking mode with DMA. More...
ald_status_t | ald_i2c_mem_write (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout)
Write an amount of data in blocking mode to a specific memory address. More...
ald_status_t | ald_i2c_mem_read (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout)
Read an amount of data in blocking mode from a specific memory address. More...
ald_status_t | ald_i2c_mem_write_by_it (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint32_t size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address. More...
ald_status_t | ald_i2c_mem_read_by_it (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint32_t size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address. More...
ald_status_t | ald_i2c_mem_write_by_dma (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint8_t size, uint8_t channel)
Write an amount of data in non-blocking mode with DMA to a specific memory address. More...
ald_status_t | ald_i2c_mem_read_by_dma (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint8_t size, uint8_t channel)
Reads an amount of data in non-blocking mode with DMA from a specific memory address. More...

Detailed Description

Data transfers functions.

 ===============================================================================
                      ##### IO operation functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to manage the I2C data
    transfers.

    (#) There are two modes of transfer:
       (++) Blocking mode : The communication is performed in the polling mode.
            The status of all data processing is returned by the same function
            after finishing transfer.
       (++) No-Blocking mode : The communication is performed using Interrupts
            or DMA. These functions return the status of the transfer startup.
            The end of the data processing will be indicated through the
            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
            using DMA mode.

    (#) Blocking mode functions are :
        (++) ald_i2c_master_send()
        (++) ald_i2c_master_recv()
        (++) ald_i2c_slave_send()
        (++) ald_i2c_slave_recv()
        (++) ald_i2c_mem_write()
        (++) ald_i2c_mem_read()

    (#) No-Blocking mode functions with Interrupt are :
        (++) ald_i2c_master_send_by_it()
        (++) ald_i2c_master_recv_by_it()
        (++) ald_i2c_slave_send_by_it()
        (++) ald_i2c_slave_recv_by_it()
        (++) ald_i2c_mem_write_by_it()
        (++) ald_i2c_mem_read_by_it()

    (#) No-Blocking mode functions with DMA are :
        (++) ald_i2c_master_send_by_dma()
        (++) ald_i2c_master_recv_by_dma()
        (++) ald_i2c_slave_send_by_dma()
        (++) ald_i2c_slave_recv_by_dma()
        (++) ald_i2c_mem_write_by_dma()
        (++) ald_i2c_mem_read_by_dma()

    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
        (++) hperh->mem_tx_cplt_cbk()
        (++) hperh->mem_rx_cplt_cbk()
        (++) hperh->master_tx_cplt_cbk()
        (++) hperh->master_rx_cplt_cbk()
        (++) hperh->slave_tx_cplt_cbk()
        (++) hperh->slave_rx_cplt_cbk()
        (++) hperh->error_callback()

Function Documentation

◆ ald_i2c_master_recv()

ald_status_t ald_i2c_master_recv | ( | i2c_handle_t * | hperh,
 |  | uint16_t | dev_addr,
 |  | uint8_t * | buf,
 |  | uint32_t | size,
 |  | uint32_t | timeout
 | ) |  |

Receives in master mode an amount of data in blocking mode.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
dev_addr | Target device address
buf | Pointer to data buffer
size | Amount of data to be sent
timeout | Timeout duration
Return values
Status,see ald_status_t

Definition at line 576 of file ald_i2c.c.

578 {
579 if (hperh->state != I2C_STATE_READY)
580 return BUSY;
581
582 if ((buf == NULL) || (size == 0))
583 return ERROR;
584
585 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
586 return BUSY;
587
588 assert_param(IS_I2C_TYPE(hperh->perh));
589 __LOCK(hperh);
590
591 hperh->state = I2C_STATE_BUSY_RX;
592 hperh->mode = I2C_MODE_MASTER;
593 hperh->error_code = I2C_ERROR_NONE;
594 hperh->p_buff = buf;
595 hperh->xfer_size = size;
596 hperh->xfer_count = 0;
597
598 i2c_master_req_read(hperh, dev_addr, timeout);
599
600 if (size <= 0xFF) {
601 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
602 }
603 else {
604 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
605 SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
606 }
607
608 SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK);
609 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
610
611 while (size > 0) {
612 if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK)
613 goto ERROR;
614
615 (*buf++) = hperh->perh->RXDATA;
616 size--;
617 hperh->xfer_count++;
618
619 if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) {
620 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TCR, RESET, I2C_TIMEOUT_FLAG) == OK) {
621 if (size > 0xFF) {
622 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
623 }
624 else {
625 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
626 CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
627 }
628 }
629 else {
630 goto ERROR;
631 }
632 }
633 }
634
635 if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK))
636 goto SUCCESS;
637
638 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
639 goto SUCCESS;
640
641 ERROR:
642 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
643 hperh->state = I2C_STATE_READY;
644 hperh->mode = I2C_MODE_NONE;
645 __UNLOCK(hperh);
646
647 return ERROR;
648
649 SUCCESS:
650 hperh->state = I2C_STATE_READY;
651 hperh->mode = I2C_MODE_NONE;
652 __UNLOCK(hperh);
653
654 return OK;
655 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
SET
Definition: type.h:39
i2c_wait_rxne_to_timeout
static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeout)
This function handles I2C Communication timeout for specific usage of RXNE flag.
Definition: ald_i2c.c:2683
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
I2C_TIMEOUT_FLAG
#define I2C_TIMEOUT_FLAG
Definition: ald_i2c.c:171
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
I2C_STAT_BUSY
Definition: ald_i2c.h:217
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_TIMEOUT_BUSY_FLAG
#define I2C_TIMEOUT_BUSY_FLAG
Definition: ald_i2c.c:173
RESET
Definition: type.h:38
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
I2C_STAT_TCR
Definition: ald_i2c.h:216
I2C_MODE_MASTER
Definition: ald_i2c.h:116
I2C_STATE_BUSY_RX
Definition: ald_i2c.h:66
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
I2C_MODE_NONE
Definition: ald_i2c.h:115
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63
i2c_master_req_read
static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout)
Master sends target device address followed by internal memory address for read request.
Definition: ald_i2c.c:2298

◆ ald_i2c_master_recv_by_dma()

ald_status_t ald_i2c_master_recv_by_dma | ( | i2c_handle_t * | hperh,
 |  | uint16_t | dev_addr,
 |  | uint8_t * | buf,
 |  | uint8_t | size,
 |  | uint8_t | channel
 | ) |  |

Receive in master mode an amount of data in non-blocking mode with DMA.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
dev_addr | Target device address
buf | Pointer to data buffer
size | Amount of data to be sent
channel | DMA channel as I2C receive
Return values
Status,see ald_status_t.

Definition at line 1070 of file ald_i2c.c.

1072 {
1073 if (hperh->state != I2C_STATE_READY)
1074 return BUSY;
1075
1076 if ((buf == NULL) || (size == 0))
1077 return ERROR;
1078
1079 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
1080 return BUSY;
1081
1082 assert_param(IS_I2C_TYPE(hperh->perh));
1083 __LOCK(hperh);
1084
1085 if (size >= 0xFF)
1086 size = 0xFF;
1087
1088 hperh->state = I2C_STATE_BUSY_RX;
1089 hperh->mode = I2C_MODE_MASTER;
1090 hperh->error_code = I2C_ERROR_NONE;
1091 hperh->p_buff = buf;
1092 hperh->xfer_size = size;
1093 hperh->xfer_count = 0;
1094
1095 if (hperh->hdmarx.perh == NULL)
1096 hperh->hdmarx.perh = DMA0;
1097
1098 hperh->hdmarx.cplt_cbk = i2c_dma_master_recv_cplt;
1099 hperh->hdmarx.cplt_arg = (void *)hperh;
1100 hperh->hdmarx.err_cbk = i2c_dma_error;
1101 hperh->hdmarx.err_arg = (void *)hperh;
1102
1103 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
1104 hperh->hdmarx.config.size = size;
1105
1106 ald_dma_config_struct(&hperh->hdmarx.config);
1107 hperh->hdmarx.config.src = (void *)&hperh->perh->RXDATA;
1108 hperh->hdmarx.config.dst = (void *)buf;
1109 hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE;
1110 hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE;
1111 hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE;
1112 hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1;
1113 hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR;
1114 hperh->hdmarx.config.channel = channel;
1115 ald_dma_config_basic(&hperh->hdmarx);
1116
1117 i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG);
1118
1119 SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK);
1120 SET_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK);
1121 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
1122
1123 return OK;
1124 }
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
i2c_handle_s::hdmatx
dma_handle_t hdmatx
Definition: ald_i2c.h:276
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
SET
Definition: type.h:39
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
DMA_MSIGSEL_I2C_RNR
Definition: ald_dma.h:143
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
I2C_TIMEOUT_FLAG
#define I2C_TIMEOUT_FLAG
Definition: ald_i2c.c:171
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
dma_config_t::src
void * src
Definition: ald_dma.h:278
I2C_STAT_BUSY
Definition: ald_i2c.h:217
i2c_dma_error
static void i2c_dma_error(void *argv)
DMA I2C communication error callback.
Definition: ald_i2c.c:2573
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_TIMEOUT_BUSY_FLAG
#define I2C_TIMEOUT_BUSY_FLAG
Definition: ald_i2c.c:173
DMA_DATA_SIZE_BYTE
Definition: ald_dma.h:227
I2C_ERROR_NONE
Definition: ald_i2c.h:44
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
DMA_MSEL_I2C0
Definition: ald_dma.h:92
I2C_MODE_MASTER
Definition: ald_i2c.h:116
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
I2C_STATE_BUSY_RX
Definition: ald_i2c.h:66
i2c_dma_master_recv_cplt
static void i2c_dma_master_recv_cplt(void *argv)
DMA I2C master receive process complete callback.
Definition: ald_i2c.c:2457
DMA_DATA_INC_BYTE
Definition: ald_dma.h:217
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
DMA_MSEL_I2C1
Definition: ald_dma.h:93
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
i2c_handle_s::hdmarx
dma_handle_t hdmarx
Definition: ald_i2c.h:277
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
I2C_STATE_READY
Definition: ald_i2c.h:63
i2c_master_req_read
static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout)
Master sends target device address followed by internal memory address for read request.
Definition: ald_i2c.c:2298

◆ ald_i2c_master_recv_by_it()

ald_status_t ald_i2c_master_recv_by_it | ( | i2c_handle_t * | hperh,
 |  | uint16_t | dev_addr,
 |  | uint8_t * | buf,
 |  | uint32_t | size
 | ) |  |

Receive in master mode an amount of data in non-blocking mode with Interrupt.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
dev_addr | Target device address
buf | Pointer to data buffer
size | Amount of data to be sent
Return values
Status,see ald_status_t.

Definition at line 861 of file ald_i2c.c.

862 {
863 if (hperh->state != I2C_STATE_READY)
864 return BUSY;
865
866 if ((buf == NULL) || (size == 0))
867 return ERROR;
868
869 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
870 return BUSY;
871
872 assert_param(IS_I2C_TYPE(hperh->perh));
873 __LOCK(hperh);
874
875 hperh->state = I2C_STATE_BUSY_RX;
876 hperh->mode = I2C_MODE_MASTER;
877 hperh->error_code = I2C_ERROR_NONE;
878 hperh->p_buff = buf;
879 hperh->xfer_size = size;
880 hperh->xfer_count = 0;
881
882 i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) ;
883
884 if (size <= 0xFF) {
885 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
886 }
887 else {
888 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
889 SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
890 }
891
892 SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK);
893
894 I2C_CLEAR_IT(hperh , I2C_IT_RXTH);
895 I2C_CLEAR_IT(hperh , I2C_IT_TCR);
896 I2C_CLEAR_IT(hperh , I2C_IT_TC);
897
898 I2C_DISABLE_IT(hperh, I2C_FLAG_MASK);
899 I2C_ENABLE_IT(hperh, I2C_IT_RXTH | I2C_IT_TCR | I2C_IT_TC);
900
901 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
902
903 return OK;
904 }
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
SET
Definition: type.h:39
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
I2C_TIMEOUT_FLAG
#define I2C_TIMEOUT_FLAG
Definition: ald_i2c.c:171
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
I2C_STAT_BUSY
Definition: ald_i2c.h:217
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_TIMEOUT_BUSY_FLAG
#define I2C_TIMEOUT_BUSY_FLAG
Definition: ald_i2c.c:173
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
I2C_FLAG_MASK
#define I2C_FLAG_MASK
Definition: ald_i2c.h:300
I2C_MODE_MASTER
Definition: ald_i2c.h:116
I2C_STATE_BUSY_RX
Definition: ald_i2c.h:66
I2C_DISABLE_IT
#define I2C_DISABLE_IT(x, y)
Definition: ald_i2c.h:303
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
I2C_CLEAR_IT
#define I2C_CLEAR_IT(x, y)
Definition: ald_i2c.h:304
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
I2C_ENABLE_IT
#define I2C_ENABLE_IT(x, y)
Definition: ald_i2c.h:302
I2C_IT_TC
Definition: ald_i2c.h:233
I2C_IT_TCR
Definition: ald_i2c.h:234
I2C_IT_RXTH
Definition: ald_i2c.h:232
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63
i2c_master_req_read
static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout)
Master sends target device address followed by internal memory address for read request.
Definition: ald_i2c.c:2298

◆ ald_i2c_master_send()

ald_status_t ald_i2c_master_send | ( | i2c_handle_t * | hperh,
 |  | uint16_t | dev_addr,
 |  | uint8_t * | buf,
 |  | uint32_t | size,
 |  | uint32_t | timeout
 | ) |  |

Transmits in master mode an amount of data in blocking mode.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
dev_addr | Target device address
buf | Pointer to data buffer
size | Amount of data to be sent
timeout | Timeout duration
Return values
Status,see ald_status_t.

Blocking mode: Polling

Definition at line 480 of file ald_i2c.c.

482 {
483 if (hperh->state != I2C_STATE_READY)
484 return BUSY;
485
486 if ((buf == NULL) || (size == 0))
487 return ERROR;
488
489 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
490 return BUSY;
491
492 assert_param(IS_I2C_TYPE(hperh->perh));
493 __LOCK(hperh);
494
495 hperh->state = I2C_STATE_BUSY_TX;
496 hperh->mode = I2C_MODE_MASTER;
497 hperh->error_code = I2C_ERROR_NONE;
498 hperh->p_buff = buf;
499 hperh->xfer_size = size;
500 hperh->xfer_count = 0;
501
502 i2c_master_req_write(hperh, dev_addr, timeout);
503
504 if (size <= 0xFF) {
505 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
506 }
507 else {
508 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
509 SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
510 }
511
512 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
513 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
514
515 while (size > 0) {
516 hperh->perh->TXDATA = (*buf++);
517 size--;
518 hperh->xfer_count++;
519
520 if (i2c_wait_txe_to_timeout(hperh, timeout) != OK)
521 goto ERROR;
522
523 if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) {
524 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TCR, RESET, I2C_TIMEOUT_FLAG) == OK) {
525 if (size > 0xFF) {
526 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
527 }
528 else {
529 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
530 CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
531 }
532 }
533 else {
534 goto ERROR;
535 }
536 }
537 }
538
539 if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK) == SET)
540 goto SUCCESS;
541
542 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == OK) {
543 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
544 goto SUCCESS;
545 }
546 else {
547 goto ERROR;
548 }
549
550 ERROR:
551 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
552 hperh->state = I2C_STATE_READY;
553 hperh->mode = I2C_MODE_NONE;
554 __UNLOCK(hperh);
555
556 return ERROR;
557
558 SUCCESS:
559 hperh->state = I2C_STATE_READY;
560 hperh->mode = I2C_MODE_NONE;
561 __UNLOCK(hperh);
562
563 return OK;
564 }
I2C_STATE_BUSY_TX
Definition: ald_i2c.h:65
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
SET
Definition: type.h:39
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
i2c_wait_txe_to_timeout
static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout)
This function handles I2C Communication timeout for specific usage of TXE flag.
Definition: ald_i2c.c:2652
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
I2C_TIMEOUT_FLAG
#define I2C_TIMEOUT_FLAG
Definition: ald_i2c.c:171
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
I2C_STAT_BUSY
Definition: ald_i2c.h:217
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_TIMEOUT_BUSY_FLAG
#define I2C_TIMEOUT_BUSY_FLAG
Definition: ald_i2c.c:173
RESET
Definition: type.h:38
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
I2C_STAT_TCR
Definition: ald_i2c.h:216
i2c_master_req_write
static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout)
Master sends target device address followed by internal memory address for write request.
Definition: ald_i2c.c:2275
I2C_MODE_MASTER
Definition: ald_i2c.h:116
I2C_STAT_TC
Definition: ald_i2c.h:215
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
I2C_MODE_NONE
Definition: ald_i2c.h:115
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ ald_i2c_master_send_by_dma()

ald_status_t ald_i2c_master_send_by_dma | ( | i2c_handle_t * | hperh,
 |  | uint16_t | dev_addr,
 |  | uint8_t * | buf,
 |  | uint8_t | size,
 |  | uint8_t | channel
 | ) |  |

Transmit in master mode an amount of data in non-blocking mode with DMA.

Note
The maximum amount of data to be sent is 0xFF.
Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
dev_addr | Target device address
buf | Pointer to data buffer
size | Amount of data to be sent (maximum is 0xFF)
channel | DMA channel as I2C transmit
Return values
Status,see ald_status_t.

Non-Blocking mode: DMA

Definition at line 1001 of file ald_i2c.c.

1003 {
1004 if (hperh->state != I2C_STATE_READY)
1005 return BUSY;
1006
1007 if ((buf == NULL) || (size == 0))
1008 return ERROR;
1009
1010 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
1011 return BUSY;
1012
1013 assert_param(IS_I2C_TYPE(hperh->perh));
1014 __LOCK(hperh);
1015
1016 if (size >= 0xFF)
1017 size = 0xFF;
1018
1019 hperh->state = I2C_STATE_BUSY_TX;
1020 hperh->mode = I2C_MODE_MASTER;
1021 hperh->error_code = I2C_ERROR_NONE;
1022 hperh->p_buff = buf;
1023 hperh->xfer_size = size;
1024 hperh->xfer_count = 0;
1025
1026 if (hperh->hdmatx.perh == NULL)
1027 hperh->hdmatx.perh = DMA0;
1028
1029 hperh->hdmatx.cplt_cbk = i2c_dma_master_send_cplt;
1030 hperh->hdmatx.cplt_arg = hperh;
1031 hperh->hdmatx.err_cbk = i2c_dma_error;
1032 hperh->hdmatx.err_arg = hperh;
1033
1034 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
1035 hperh->hdmatx.config.size = size;
1036
1037 ald_dma_config_struct(&hperh->hdmatx.config);
1038 hperh->hdmatx.config.burst = ENABLE;
1039 hperh->hdmatx.config.src = (void *)hperh->p_buff;
1040 hperh->hdmatx.config.dst = (void *)&hperh->perh->TXDATA;
1041 hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE;
1042 hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE;
1043 hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
1044 hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1;
1045 hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY;
1046 hperh->hdmatx.config.channel = channel;
1047 ald_dma_config_basic(&hperh->hdmatx);
1048
1049 i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG);
1050
1051 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
1052 SET_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK);
1053 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
1054
1055 __UNLOCK(hperh);
1056
1057 return OK;
1058 }
I2C_STATE_BUSY_TX
Definition: ald_i2c.h:65
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
i2c_handle_s::hdmatx
dma_handle_t hdmatx
Definition: ald_i2c.h:276
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
SET
Definition: type.h:39
DMA_MSIGSEL_I2C_TXEMPTY
Definition: ald_dma.h:144
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
I2C_TIMEOUT_FLAG
#define I2C_TIMEOUT_FLAG
Definition: ald_i2c.c:171
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
dma_config_t::src
void * src
Definition: ald_dma.h:278
I2C_STAT_BUSY
Definition: ald_i2c.h:217
i2c_dma_error
static void i2c_dma_error(void *argv)
DMA I2C communication error callback.
Definition: ald_i2c.c:2573
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_TIMEOUT_BUSY_FLAG
#define I2C_TIMEOUT_BUSY_FLAG
Definition: ald_i2c.c:173
DMA_DATA_SIZE_BYTE
Definition: ald_dma.h:227
I2C_ERROR_NONE
Definition: ald_i2c.h:44
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
DMA_MSEL_I2C0
Definition: ald_dma.h:92
i2c_master_req_write
static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout)
Master sends target device address followed by internal memory address for write request.
Definition: ald_i2c.c:2275
I2C_MODE_MASTER
Definition: ald_i2c.h:116
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
DMA_DATA_INC_BYTE
Definition: ald_dma.h:217
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
i2c_dma_master_send_cplt
static void i2c_dma_master_send_cplt(void *argv)
DMA I2C master transmit process complete callback.
Definition: ald_i2c.c:2401
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
DMA_MSEL_I2C1
Definition: ald_dma.h:93
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ ald_i2c_master_send_by_it()

ald_status_t ald_i2c_master_send_by_it | ( | i2c_handle_t * | hperh,
 |  | uint16_t | dev_addr,
 |  | uint8_t * | buf,
 |  | uint32_t | size
 | ) |  |

Transmit in master mode an amount of data in non-blocking mode with Interrupt.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
dev_addr | Target device address
buf | Pointer to data buffer
size | Amount of data to be sent
Return values
Status,see ald_status_t.

Non-Blocking mode: Interrupt

Definition at line 806 of file ald_i2c.c.

807 {
808 if (hperh->state != I2C_STATE_READY)
809 return BUSY;
810
811 if ((buf == NULL) || (size == 0))
812 return ERROR;
813
814 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
815 return BUSY;
816
817 assert_param(IS_I2C_TYPE(hperh->perh));
818 __LOCK(hperh);
819
820 hperh->state = I2C_STATE_BUSY_TX;
821 hperh->mode = I2C_MODE_MASTER;
822 hperh->error_code = I2C_ERROR_NONE;
823 hperh->p_buff = buf;
824 hperh->xfer_size = size;
825 hperh->xfer_count = 0;
826
827 i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG);
828
829 if (size <= 0xff) {
830 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
831 }
832 else {
833 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
834 SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
835 }
836
837 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
838
839 I2C_CLEAR_IT(hperh , I2C_IT_TXTH);
840 I2C_CLEAR_IT(hperh , I2C_IT_NACK);
841 I2C_CLEAR_IT(hperh , I2C_IT_TC);
842 I2C_CLEAR_IT(hperh , I2C_IT_TCR);
843
844 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
845
846 I2C_DISABLE_IT(hperh, I2C_FLAG_MASK);
847 I2C_ENABLE_IT(hperh, I2C_IT_TXTH | I2C_IT_NACK | I2C_IT_TC | I2C_IT_TCR);
848
849 return OK;
850 }
I2C_STATE_BUSY_TX
Definition: ald_i2c.h:65
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
SET
Definition: type.h:39
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
I2C_TIMEOUT_FLAG
#define I2C_TIMEOUT_FLAG
Definition: ald_i2c.c:171
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
I2C_STAT_BUSY
Definition: ald_i2c.h:217
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_TIMEOUT_BUSY_FLAG
#define I2C_TIMEOUT_BUSY_FLAG
Definition: ald_i2c.c:173
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
I2C_FLAG_MASK
#define I2C_FLAG_MASK
Definition: ald_i2c.h:300
i2c_master_req_write
static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout)
Master sends target device address followed by internal memory address for write request.
Definition: ald_i2c.c:2275
I2C_MODE_MASTER
Definition: ald_i2c.h:116
I2C_IT_TXTH
Definition: ald_i2c.h:228
I2C_DISABLE_IT
#define I2C_DISABLE_IT(x, y)
Definition: ald_i2c.h:303
I2C_IT_NACK
Definition: ald_i2c.h:236
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
I2C_CLEAR_IT
#define I2C_CLEAR_IT(x, y)
Definition: ald_i2c.h:304
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
I2C_ENABLE_IT
#define I2C_ENABLE_IT(x, y)
Definition: ald_i2c.h:302
I2C_IT_TC
Definition: ald_i2c.h:233
I2C_IT_TCR
Definition: ald_i2c.h:234
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ ald_i2c_mem_read()

ald_status_t ald_i2c_mem_read | ( | i2c_handle_t * | hperh,
 |  | uint16_t | dev_addr,
 |  | uint16_t | mem_addr,
 |  | i2c_addr_size_t | add_size,
 |  | uint8_t * | buf,
 |  | uint32_t | size,
 |  | uint32_t | timeout
 | ) |  |

Read an amount of data in blocking mode from a specific memory address.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
dev_addr | Target device address
mem_addr | Internal memory address
add_size | size of internal memory address
buf | Pointer to data buffer
size | Amount of data to be sent
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 1378 of file ald_i2c.c.

1380 {
1381 uint32_t nbyte = 0;
1382
1383 assert_param(IS_I2C_MEMADD_size(add_size));
1384
1385 if (hperh->state != I2C_STATE_READY)
1386 return BUSY;
1387
1388 if ((buf == NULL) || (size == 0))
1389 return ERROR;
1390
1391 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
1392 return BUSY;
1393
1394 assert_param(IS_I2C_TYPE(hperh->perh));
1395 __LOCK(hperh);
1396
1397 hperh->state = I2C_STATE_BUSY_RX;
1398 hperh->mode = I2C_MODE_MEM;
1399 hperh->error_code = I2C_ERROR_NONE;
1400 hperh->xfer_count = 0;
1401 hperh->xfer_size = size;
1402
1403 i2c_master_req_write(hperh, dev_addr, timeout);
1404
1405 nbyte = (add_size == I2C_MEMADD_SIZE_8BIT) ? 1 : 2;
1406 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS);
1407
1408 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
1409 SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK);
1410
1411 if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) {
1412 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
1413 hperh->state = I2C_STATE_READY;
1414 hperh->mode = I2C_MODE_NONE;
1415 __UNLOCK(hperh);
1416
1417 return ERROR;
1418 }
1419
1420 if (size <= 0xFF) {
1421 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
1422 }
1423 else {
1424 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
1425 SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
1426 }
1427
1428 SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK);
1429 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
1430
1431 while (size > 0) {
1432 if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK)
1433 goto ERROR;
1434
1435 (*buf++) = hperh->perh->RXDATA;
1436 size--;
1437 hperh->xfer_count++;
1438
1439 if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) {
1440 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TCR, RESET, I2C_TIMEOUT_FLAG) == OK) {
1441 if (size > 0xFF) {
1442 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
1443 }
1444 else {
1445 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
1446 CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
1447 }
1448 }
1449 else {
1450 goto ERROR;
1451 }
1452 }
1453 }
1454
1455 if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK))
1456 goto SUCCESS;
1457
1458 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
1459 goto SUCCESS;
1460
1461 ERROR:
1462 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
1463 hperh->state = I2C_STATE_READY;
1464 hperh->mode = I2C_MODE_NONE;
1465 __UNLOCK(hperh);
1466
1467 return ERROR;
1468
1469 SUCCESS:
1470 hperh->state = I2C_STATE_READY;
1471 hperh->mode = I2C_MODE_NONE;
1472 __UNLOCK(hperh);
1473
1474 return OK;
1475 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
SET
Definition: type.h:39
I2C_MODE_MEM
Definition: ald_i2c.h:118
i2c_wait_rxne_to_timeout
static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeout)
This function handles I2C Communication timeout for specific usage of RXNE flag.
Definition: ald_i2c.c:2683
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
I2C_TIMEOUT_FLAG
#define I2C_TIMEOUT_FLAG
Definition: ald_i2c.c:171
I2C_STAT_BUSY
Definition: ald_i2c.h:217
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_TIMEOUT_BUSY_FLAG
#define I2C_TIMEOUT_BUSY_FLAG
Definition: ald_i2c.c:173
RESET
Definition: type.h:38
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
I2C_STAT_TCR
Definition: ald_i2c.h:216
IS_I2C_MEMADD_size
#define IS_I2C_MEMADD_size(size)
Definition: ald_i2c.h:327
i2c_master_req_write
static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout)
Master sends target device address followed by internal memory address for write request.
Definition: ald_i2c.c:2275
I2C_STATE_BUSY_RX
Definition: ald_i2c.h:66
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
I2C_MEMADD_SIZE_8BIT
Definition: ald_i2c.h:107
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
I2C_MODE_NONE
Definition: ald_i2c.h:115
i2c_req_mem_write
static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout)
Master sends target device address followed by internal memory address for write request.
Definition: ald_i2c.c:2323
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ ald_i2c_mem_read_by_dma()

ald_status_t ald_i2c_mem_read_by_dma | ( | i2c_handle_t * | hperh,
 |  | uint16_t | dev_addr,
 |  | uint16_t | mem_addr,
 |  | i2c_addr_size_t | add_size,
 |  | uint8_t * | buf,
 |  | uint8_t | size,
 |  | uint8_t | channel
 | ) |  |

Reads an amount of data in non-blocking mode with DMA from a specific memory address.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
dev_addr | Target device address
mem_addr | Internal memory address
add_size | size of internal memory address
buf | Pointer to data buffer
size | Amount of data to be read
channel | DMA channel
Return values
Status,see ald_status_t.

Definition at line 1721 of file ald_i2c.c.

1723 {
1724 if (hperh->state != I2C_STATE_READY)
1725 return BUSY;
1726
1727 if ((buf == NULL) || (size == 0))
1728 return ERROR;
1729
1730 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
1731 return BUSY;
1732
1733 assert_param(IS_I2C_MEMADD_size(add_size));
1734 __LOCK(hperh);
1735
1736 hperh->state = I2C_STATE_BUSY_RX;
1737 hperh->mode = I2C_MODE_MEM;
1738 hperh->error_code = I2C_ERROR_NONE;
1739 hperh->p_buff = buf;
1740 hperh->xfer_size = size;
1741 hperh->xfer_count = size;
1742
1743 if (hperh->hdmarx.perh == NULL)
1744 hperh->hdmarx.perh = DMA0;
1745
1746 hperh->hdmarx.cplt_cbk = i2c_dma_mem_recv_cplt;
1747 hperh->hdmarx.cplt_arg = (void *)hperh;
1748 hperh->hdmarx.err_cbk = i2c_dma_error;
1749 hperh->hdmarx.err_arg = (void *)hperh;
1750
1751 if (add_size == I2C_MEMADD_SIZE_16BIT) {
1752 hperh->hdmatx.config.size = size + 2;
1753 }
1754 else {
1755 hperh->hdmatx.config.size = size + 1;
1756 }
1757
1758 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
1759 hperh->hdmatx.config.size = size;
1760
1761 ald_dma_config_struct(&hperh->hdmarx.config);
1762 hperh->hdmatx.config.burst = ENABLE;
1763 hperh->hdmarx.config.src = (void *)&hperh->perh->RXDATA;
1764 hperh->hdmarx.config.dst = (void *)buf;
1765 hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE;
1766 hperh->hdmarx.config.size = size;
1767 hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE;
1768 hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE;
1769 hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1;
1770 hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR;
1771 hperh->hdmarx.config.channel = channel;
1772 ald_dma_config_basic(&hperh->hdmarx);
1773
1774 if (!I2C_GET_FLAG(hperh, I2C_STAT_TXE)) {
1775 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
1776 }
1777
1778 if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) {
1779 if (hperh->error_code == I2C_ERROR_AF) {
1780 __UNLOCK(hperh);
1781 return ERROR;
1782 }
1783 else {
1784 __UNLOCK(hperh);
1785 return TIMEOUT;
1786 }
1787 }
1788
1789 SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK);
1790 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
1791 SET_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK);
1792
1793 __UNLOCK(hperh);
1794
1795 return OK;
1796 }
I2C_ERROR_AF
Definition: ald_i2c.h:48
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
i2c_handle_s::hdmatx
dma_handle_t hdmatx
Definition: ald_i2c.h:276
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
I2C_STAT_TXE
Definition: ald_i2c.h:205
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
SET
Definition: type.h:39
I2C_MODE_MEM
Definition: ald_i2c.h:118
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
DMA_MSIGSEL_I2C_RNR
Definition: ald_dma.h:143
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
I2C_TIMEOUT_FLAG
#define I2C_TIMEOUT_FLAG
Definition: ald_i2c.c:171
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
dma_config_t::src
void * src
Definition: ald_dma.h:278
I2C_STAT_BUSY
Definition: ald_i2c.h:217
i2c_dma_error
static void i2c_dma_error(void *argv)
DMA I2C communication error callback.
Definition: ald_i2c.c:2573
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_TIMEOUT_BUSY_FLAG
#define I2C_TIMEOUT_BUSY_FLAG
Definition: ald_i2c.c:173
DMA_DATA_SIZE_BYTE
Definition: ald_dma.h:227
I2C_ERROR_NONE
Definition: ald_i2c.h:44
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
IS_I2C_MEMADD_size
#define IS_I2C_MEMADD_size(size)
Definition: ald_i2c.h:327
DMA_MSEL_I2C0
Definition: ald_dma.h:92
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
I2C_STATE_BUSY_RX
Definition: ald_i2c.h:66
i2c_req_mem_read
static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout)
Master sends target device address followed by internal memory address for read request.
Definition: ald_i2c.c:2356
I2C_GET_FLAG
#define I2C_GET_FLAG(x, y)
Definition: ald_i2c.h:307
DMA_DATA_INC_BYTE
Definition: ald_dma.h:217
TIMEOUT
Definition: utils.h:58
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
I2C_MEMADD_SIZE_16BIT
Definition: ald_i2c.h:108
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
DMA_MSEL_I2C1
Definition: ald_dma.h:93
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
i2c_dma_mem_recv_cplt
static void i2c_dma_mem_recv_cplt(void *argv)
DMA I2C Memory Read process complete callback.
Definition: ald_i2c.c:2543
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
i2c_handle_s::hdmarx
dma_handle_t hdmarx
Definition: ald_i2c.h:277
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ ald_i2c_mem_read_by_it()

ald_status_t ald_i2c_mem_read_by_it | ( | i2c_handle_t * | hperh,
 |  | uint16_t | dev_addr,
 |  | uint16_t | mem_addr,
 |  | i2c_addr_size_t | add_size,
 |  | uint8_t * | buf,
 |  | uint32_t | size
 | ) |  |

Read an amount of data in non-blocking mode with Interrupt from a specific memory address.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
dev_addr | Target device address
mem_addr | Internal memory address
add_size | size of internal memory address
buf | Pointer to data buffer
size | Amount of data to be sent
Return values
Status,see ald_status_t.

Definition at line 1566 of file ald_i2c.c.

1568 {
1569 uint32_t nbyte = 0;
1570
1571 assert_param(IS_I2C_MEMADD_size(add_size));
1572
1573 if (hperh->state != I2C_STATE_READY)
1574 return BUSY;
1575
1576 if ((buf == NULL) || (size == 0))
1577 return ERROR;
1578
1579 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
1580 return BUSY;
1581
1582 assert_param(IS_I2C_TYPE(hperh->perh));
1583 __LOCK(hperh);
1584
1585 hperh->state = I2C_STATE_BUSY_RX;
1586 hperh->mode = I2C_MODE_MEM;
1587 hperh->error_code = I2C_ERROR_NONE;
1588 hperh->p_buff = buf;
1589 hperh->xfer_size = size;
1590 hperh->xfer_count = 0;
1591
1592 nbyte = (add_size == I2C_MEMADD_SIZE_8BIT) ? 1 : 2;
1593 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS);
1594
1595 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
1596 SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK);
1597
1598 if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) {
1599 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
1600 hperh->state = I2C_STATE_READY;
1601 hperh->mode = I2C_MODE_NONE;
1602 __UNLOCK(hperh);
1603
1604 return ERROR;
1605 }
1606
1607 if (size <= 0xFF) {
1608 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
1609 }
1610 else {
1611 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
1612 SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
1613 }
1614
1615 I2C_CLEAR_IT(hperh , I2C_IT_RXTH);
1616 I2C_CLEAR_IT(hperh , I2C_IT_TC);
1617 I2C_CLEAR_IT(hperh , I2C_IT_TCR);
1618
1619 I2C_ENABLE_IT(hperh, I2C_IT_RXTH | I2C_IT_TC | I2C_IT_TCR);
1620
1621 SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK);
1622 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
1623
1624 return OK;
1625 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
SET
Definition: type.h:39
I2C_MODE_MEM
Definition: ald_i2c.h:118
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
I2C_TIMEOUT_FLAG
#define I2C_TIMEOUT_FLAG
Definition: ald_i2c.c:171
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
I2C_STAT_BUSY
Definition: ald_i2c.h:217
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_TIMEOUT_BUSY_FLAG
#define I2C_TIMEOUT_BUSY_FLAG
Definition: ald_i2c.c:173
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
IS_I2C_MEMADD_size
#define IS_I2C_MEMADD_size(size)
Definition: ald_i2c.h:327
I2C_STATE_BUSY_RX
Definition: ald_i2c.h:66
I2C_MEMADD_SIZE_8BIT
Definition: ald_i2c.h:107
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
I2C_CLEAR_IT
#define I2C_CLEAR_IT(x, y)
Definition: ald_i2c.h:304
I2C_MODE_NONE
Definition: ald_i2c.h:115
i2c_req_mem_write
static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout)
Master sends target device address followed by internal memory address for write request.
Definition: ald_i2c.c:2323
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
I2C_ENABLE_IT
#define I2C_ENABLE_IT(x, y)
Definition: ald_i2c.h:302
I2C_IT_TC
Definition: ald_i2c.h:233
I2C_IT_TCR
Definition: ald_i2c.h:234
I2C_IT_RXTH
Definition: ald_i2c.h:232
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ ald_i2c_mem_write()

ald_status_t ald_i2c_mem_write | ( | i2c_handle_t * | hperh,
 |  | uint16_t | dev_addr,
 |  | uint16_t | mem_addr,
 |  | i2c_addr_size_t | add_size,
 |  | uint8_t * | buf,
 |  | uint32_t | size,
 |  | uint32_t | timeout
 | ) |  |

Write an amount of data in blocking mode to a specific memory address.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
dev_addr | Target device address
mem_addr | Internal memory address
add_size | size of internal memory address
buf | Pointer to data buffer
size | Amount of data to be sent
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 1272 of file ald_i2c.c.

1274 {
1275 uint32_t nbyte = 0;
1276
1277 assert_param(IS_I2C_MEMADD_size(add_size));
1278
1279 if (hperh->state != I2C_STATE_READY)
1280 return BUSY;
1281
1282 if ((buf == NULL) || (size == 0))
1283 return ERROR;
1284
1285 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
1286 return BUSY;
1287
1288 assert_param(IS_I2C_TYPE(hperh->perh));
1289 __LOCK(hperh);
1290
1291 hperh->state = I2C_STATE_BUSY_TX;
1292 hperh->mode = I2C_MODE_MEM;
1293 hperh->error_code = I2C_ERROR_NONE;
1294 hperh->xfer_size = size;
1295 hperh->xfer_count = 0;
1296
1297 i2c_master_req_write(hperh, dev_addr, timeout);
1298
1299 if (add_size == I2C_MEMADD_SIZE_8BIT) {
1300 nbyte = size + 1;
1301 }
1302 else {
1303 nbyte = size + 2;
1304 }
1305
1306 if (nbyte <= 0xFF) {
1307 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS);
1308 }
1309 else {
1310 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
1311 SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
1312 }
1313
1314 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
1315
1316 if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK)
1317 goto ERROR;
1318
1319 hperh->xfer_count += 2;
1320 while (size > 0) {
1321 hperh->perh->TXDATA = (*buf++);
1322 --size;
1323 hperh->xfer_count++;
1324
1325 if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) {
1326 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TCR, RESET, I2C_TIMEOUT_FLAG) == OK) {
1327 if (size > 0xFF) {
1328 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
1329 }
1330 else {
1331 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
1332 CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
1333 }
1334 }
1335 else {
1336 goto ERROR;
1337 }
1338 }
1339
1340 if (i2c_wait_txe_to_timeout(hperh, timeout) != OK)
1341 goto ERROR;
1342 }
1343
1344 if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK))
1345 goto SUCCESS;
1346
1347 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
1348 goto SUCCESS;
1349
1350 ERROR:
1351 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
1352 hperh->state = I2C_STATE_READY;
1353 hperh->mode = I2C_MODE_NONE;
1354 __UNLOCK(hperh);
1355
1356 return ERROR;
1357
1358 SUCCESS:
1359 hperh->state = I2C_STATE_READY;
1360 hperh->mode = I2C_MODE_NONE;
1361 __UNLOCK(hperh);
1362
1363 return OK;
1364 }
I2C_STATE_BUSY_TX
Definition: ald_i2c.h:65
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
SET
Definition: type.h:39
I2C_MODE_MEM
Definition: ald_i2c.h:118
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
i2c_wait_txe_to_timeout
static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout)
This function handles I2C Communication timeout for specific usage of TXE flag.
Definition: ald_i2c.c:2652
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
I2C_TIMEOUT_FLAG
#define I2C_TIMEOUT_FLAG
Definition: ald_i2c.c:171
I2C_STAT_BUSY
Definition: ald_i2c.h:217
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_TIMEOUT_BUSY_FLAG
#define I2C_TIMEOUT_BUSY_FLAG
Definition: ald_i2c.c:173
RESET
Definition: type.h:38
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
I2C_STAT_TCR
Definition: ald_i2c.h:216
IS_I2C_MEMADD_size
#define IS_I2C_MEMADD_size(size)
Definition: ald_i2c.h:327
i2c_master_req_write
static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout)
Master sends target device address followed by internal memory address for write request.
Definition: ald_i2c.c:2275
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
I2C_MEMADD_SIZE_8BIT
Definition: ald_i2c.h:107
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
I2C_MODE_NONE
Definition: ald_i2c.h:115
i2c_req_mem_write
static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout)
Master sends target device address followed by internal memory address for write request.
Definition: ald_i2c.c:2323
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ ald_i2c_mem_write_by_dma()

ald_status_t ald_i2c_mem_write_by_dma | ( | i2c_handle_t * | hperh,
 |  | uint16_t | dev_addr,
 |  | uint16_t | mem_addr,
 |  | i2c_addr_size_t | add_size,
 |  | uint8_t * | buf,
 |  | uint8_t | size,
 |  | uint8_t | channel
 | ) |  |

Write an amount of data in non-blocking mode with DMA to a specific memory address.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
dev_addr | Target device address
mem_addr | Internal memory address
add_size | size of internal memory address(Maxsiz 0xFF)
buf | Pointer to data buffer
size | Amount of data to be sent
channel | DMA channel
Return values
Status,see ald_status_t.

Definition at line 1641 of file ald_i2c.c.

1643 {
1644 uint32_t nbyte = 0;
1645
1646 if (hperh->state != I2C_STATE_READY)
1647 return BUSY;
1648
1649 if ((buf == NULL) || (size == 0))
1650 return ERROR;
1651
1652 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
1653 return BUSY;
1654
1655 assert_param(IS_I2C_MEMADD_size(add_size));
1656 __LOCK(hperh);
1657
1658 hperh->state = I2C_STATE_BUSY_TX;
1659 hperh->mode = I2C_MODE_MASTER;
1660 hperh->error_code = I2C_ERROR_NONE;
1661 hperh->p_buff = buf;
1662 hperh->xfer_size = size;
1663 hperh->xfer_count = 0;
1664
1665 if (hperh->hdmatx.perh == NULL)
1666 hperh->hdmatx.perh = DMA0;
1667
1668 hperh->hdmatx.cplt_cbk = i2c_dma_mem_send_cplt;
1669 hperh->hdmatx.cplt_arg = hperh;
1670 hperh->hdmatx.err_cbk = i2c_dma_error;
1671 hperh->hdmatx.err_arg = hperh;
1672
1673 nbyte = (add_size == I2C_MEMADD_SIZE_8BIT) ? 1 : 2;
1674 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS);
1675 SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
1676
1677 ald_dma_config_struct(&hperh->hdmatx.config);
1678 hperh->hdmatx.config.burst = ENABLE;
1679 hperh->hdmatx.config.src = (void *)hperh->p_buff;
1680 hperh->hdmatx.config.dst = (void *)&hperh->perh->TXDATA;
1681 hperh->hdmatx.config.size = size;
1682 hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE;
1683 hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE;
1684 hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
1685 hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1;
1686 hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY;
1687 hperh->hdmatx.config.channel = channel;
1688 ald_dma_config_basic(&hperh->hdmatx);
1689
1690 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
1691
1692 if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) {
1693 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
1694 hperh->state = I2C_STATE_READY;
1695 hperh->mode = I2C_MODE_NONE;
1696 __UNLOCK(hperh);
1697
1698 return ERROR;
1699 }
1700
1701 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
1702 CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
1703
1704 SET_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK);
1705
1706 return OK;
1707 }
I2C_STATE_BUSY_TX
Definition: ald_i2c.h:65
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
i2c_dma_mem_send_cplt
static void i2c_dma_mem_send_cplt(void *argv)
DMA I2C Memory Write process complete callback.
Definition: ald_i2c.c:2513
i2c_handle_s::hdmatx
dma_handle_t hdmatx
Definition: ald_i2c.h:276
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
SET
Definition: type.h:39
DMA_MSIGSEL_I2C_TXEMPTY
Definition: ald_dma.h:144
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
I2C_TIMEOUT_FLAG
#define I2C_TIMEOUT_FLAG
Definition: ald_i2c.c:171
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
dma_config_t::src
void * src
Definition: ald_dma.h:278
I2C_STAT_BUSY
Definition: ald_i2c.h:217
i2c_dma_error
static void i2c_dma_error(void *argv)
DMA I2C communication error callback.
Definition: ald_i2c.c:2573
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_TIMEOUT_BUSY_FLAG
#define I2C_TIMEOUT_BUSY_FLAG
Definition: ald_i2c.c:173
DMA_DATA_SIZE_BYTE
Definition: ald_dma.h:227
I2C_ERROR_NONE
Definition: ald_i2c.h:44
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
IS_I2C_MEMADD_size
#define IS_I2C_MEMADD_size(size)
Definition: ald_i2c.h:327
DMA_MSEL_I2C0
Definition: ald_dma.h:92
I2C_MODE_MASTER
Definition: ald_i2c.h:116
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
DMA_DATA_INC_BYTE
Definition: ald_dma.h:217
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
I2C_MEMADD_SIZE_8BIT
Definition: ald_i2c.h:107
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
I2C_MODE_NONE
Definition: ald_i2c.h:115
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
i2c_req_mem_write
static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout)
Master sends target device address followed by internal memory address for write request.
Definition: ald_i2c.c:2323
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
DMA_MSEL_I2C1
Definition: ald_dma.h:93
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ ald_i2c_mem_write_by_it()

ald_status_t ald_i2c_mem_write_by_it | ( | i2c_handle_t * | hperh,
 |  | uint16_t | dev_addr,
 |  | uint16_t | mem_addr,
 |  | i2c_addr_size_t | add_size,
 |  | uint8_t * | buf,
 |  | uint32_t | size
 | ) |  |

Write an amount of data in non-blocking mode with Interrupt to a specific memory address.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
dev_addr | Target device address
mem_addr | Internal memory address
add_size | size of internal memory address
buf | Pointer to data buffer
size | Amount of data to be sent
Return values
Status,see ald_status_t.

Definition at line 1488 of file ald_i2c.c.

1490 {
1491 uint32_t nbyte = 0;
1492
1493 assert_param(IS_I2C_MEMADD_size(add_size));
1494
1495 if (hperh->state != I2C_STATE_READY)
1496 return BUSY;
1497
1498 if ((buf == NULL) || (size == 0))
1499 return ERROR;
1500
1501 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
1502 return BUSY;
1503
1504 assert_param(IS_I2C_TYPE(hperh->perh));
1505 __LOCK(hperh);
1506
1507 hperh->state = I2C_STATE_BUSY_TX;
1508 hperh->mode = I2C_MODE_MEM;
1509 hperh->error_code = I2C_ERROR_NONE;
1510 hperh->p_buff = buf;
1511 hperh->xfer_size = size;
1512 hperh->xfer_count = 0;
1513
1514 if (add_size == I2C_MEMADD_SIZE_8BIT) {
1515 nbyte = size + 1;
1516 }
1517 else {
1518 nbyte = size + 2;
1519 }
1520
1521 if (nbyte <= 0xFF) {
1522 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS);
1523 }
1524 else {
1525 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
1526 SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
1527 }
1528
1529 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
1530 SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK);
1531
1532 if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) {
1533 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
1534 hperh->state = I2C_STATE_READY;
1535 hperh->mode = I2C_MODE_NONE;
1536 __UNLOCK(hperh);
1537
1538 return ERROR;
1539 }
1540
1541 I2C_CLEAR_IT(hperh , I2C_IT_TXTH);
1542 I2C_CLEAR_IT(hperh , I2C_IT_NACK);
1543 I2C_CLEAR_IT(hperh , I2C_IT_TC);
1544 I2C_CLEAR_IT(hperh , I2C_IT_TCR);
1545
1546 hperh->perh->TXDATA = (*hperh->p_buff++);
1547 hperh->xfer_count++;
1548
1549 I2C_DISABLE_IT(hperh, I2C_FLAG_MASK);
1550 I2C_ENABLE_IT(hperh, I2C_IT_TXTH | I2C_IT_NACK | I2C_IT_TC | I2C_IT_TCR);
1551
1552 return OK;
1553 }
I2C_STATE_BUSY_TX
Definition: ald_i2c.h:65
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
SET
Definition: type.h:39
I2C_MODE_MEM
Definition: ald_i2c.h:118
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
I2C_TIMEOUT_FLAG
#define I2C_TIMEOUT_FLAG
Definition: ald_i2c.c:171
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
I2C_STAT_BUSY
Definition: ald_i2c.h:217
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_TIMEOUT_BUSY_FLAG
#define I2C_TIMEOUT_BUSY_FLAG
Definition: ald_i2c.c:173
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
I2C_FLAG_MASK
#define I2C_FLAG_MASK
Definition: ald_i2c.h:300
IS_I2C_MEMADD_size
#define IS_I2C_MEMADD_size(size)
Definition: ald_i2c.h:327
I2C_IT_TXTH
Definition: ald_i2c.h:228
I2C_DISABLE_IT
#define I2C_DISABLE_IT(x, y)
Definition: ald_i2c.h:303
I2C_IT_NACK
Definition: ald_i2c.h:236
I2C_MEMADD_SIZE_8BIT
Definition: ald_i2c.h:107
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
I2C_CLEAR_IT
#define I2C_CLEAR_IT(x, y)
Definition: ald_i2c.h:304
I2C_MODE_NONE
Definition: ald_i2c.h:115
i2c_req_mem_write
static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout)
Master sends target device address followed by internal memory address for write request.
Definition: ald_i2c.c:2323
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
I2C_ENABLE_IT
#define I2C_ENABLE_IT(x, y)
Definition: ald_i2c.h:302
I2C_IT_TC
Definition: ald_i2c.h:233
I2C_IT_TCR
Definition: ald_i2c.h:234
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ ald_i2c_slave_recv()

ald_status_t ald_i2c_slave_recv | ( | i2c_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint32_t | size,
 |  | uint32_t | timeout
 | ) |  |

Receive in slave mode an amount of data in blocking mode.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
buf | Pointer to data buffer
size | Amount of data to be sent
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 744 of file ald_i2c.c.

745 {
746 if (hperh->state != I2C_STATE_READY)
747 return BUSY;
748
749 if ((buf == NULL) || (size == 0))
750 return ERROR;
751
752 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
753 return BUSY;
754
755 assert_param(IS_I2C_TYPE(hperh->perh));
756 __LOCK(hperh);
757
758 hperh->state = I2C_STATE_BUSY_RX;
759 hperh->mode = I2C_MODE_SLAVE;
760 hperh->error_code = I2C_ERROR_NONE;
761 hperh->p_buff = buf;
762 hperh->xfer_count = 0;
763 hperh->xfer_size = size;
764
765 SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK);
766
767 if (i2c_wait_master_addr_to_timeout(hperh, I2C_IT_ADDR, timeout) == ERROR)
768 goto ERROR;
769
770 while (size > 0) {
771 if (i2c_wait_rxne_to_timeout(hperh, timeout) == ERROR)
772 goto ERROR;
773
774 SET_BIT(hperh->perh->CON2, I2C_CON2_ACK_UPD_MSK);
775 (*buf++) = hperh->perh->RXDATA;
776 --size;
777 hperh->xfer_count++;
778 }
779
780 goto SUCCESS;
781
782 ERROR:
783 hperh->state = I2C_STATE_READY;
784 hperh->mode = I2C_MODE_NONE;
785 __UNLOCK(hperh);
786
787 return ERROR;
788
789 SUCCESS:
790 hperh->state = I2C_STATE_READY;
791 hperh->mode = I2C_MODE_NONE;
792 __UNLOCK(hperh);
793
794 return OK;
795 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
SET
Definition: type.h:39
i2c_wait_rxne_to_timeout
static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeout)
This function handles I2C Communication timeout for specific usage of RXNE flag.
Definition: ald_i2c.c:2683
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
I2C_STAT_BUSY
Definition: ald_i2c.h:217
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_TIMEOUT_BUSY_FLAG
#define I2C_TIMEOUT_BUSY_FLAG
Definition: ald_i2c.c:173
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
I2C_MODE_SLAVE
Definition: ald_i2c.h:117
I2C_STATE_BUSY_RX
Definition: ald_i2c.h:66
I2C_IT_ADDR
Definition: ald_i2c.h:235
i2c_wait_master_addr_to_timeout
static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, uint32_t flag, uint32_t timeout)
This function handles I2C Communication timeout for Master addressing phase.
Definition: ald_i2c.c:2630
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
I2C_MODE_NONE
Definition: ald_i2c.h:115
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ ald_i2c_slave_recv_by_dma()

ald_status_t ald_i2c_slave_recv_by_dma | ( | i2c_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint8_t | size,
 |  | uint8_t | channel
 | ) |  |

Receive in slave mode an amount of data in non-blocking mode with DMA.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
buf | Pointer to data buffer
size | Amount of data to be sent
channel | DMA channel as I2C receive
Return values
Status,see ald_status_t.

Definition at line 1202 of file ald_i2c.c.

1203 {
1204 if (hperh->state != I2C_STATE_READY)
1205 return BUSY;
1206
1207 if ((buf == NULL) || (size == 0))
1208 return ERROR;
1209
1210 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
1211 return BUSY;
1212
1213 assert_param(IS_I2C_TYPE(hperh->perh));
1214 __LOCK(hperh);
1215
1216 hperh->state = I2C_STATE_BUSY_RX;
1217 hperh->mode = I2C_MODE_SLAVE;
1218 hperh->error_code = I2C_ERROR_NONE;
1219 hperh->p_buff = buf;
1220 hperh->xfer_size = size;
1221 hperh->xfer_count = 0;
1222
1223 if (size >= 0xFF)
1224 size = 0xFF;
1225
1226 if (hperh->hdmarx.perh == NULL)
1227 hperh->hdmarx.perh = DMA0;
1228
1229 hperh->hdmarx.cplt_cbk = i2c_dma_slave_recv_cplt;
1230 hperh->hdmarx.cplt_arg = (void *)hperh;
1231 hperh->hdmarx.err_cbk = i2c_dma_error;
1232 hperh->hdmarx.err_arg = (void *)hperh;
1233
1234 ald_dma_config_struct(&hperh->hdmarx.config);
1235 hperh->hdmarx.config.src = (void *)&hperh->perh->RXDATA;
1236 hperh->hdmarx.config.dst = (void *)buf;
1237 hperh->hdmarx.config.size = size;
1238 hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE;
1239 hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE;
1240 hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE;
1241 hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1;
1242 hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR;
1243 hperh->hdmarx.config.channel = channel;
1244 ald_dma_config_basic(&hperh->hdmarx);
1245
1246 if (i2c_wait_master_addr_to_timeout(hperh, I2C_IT_ADDR, I2C_TIMEOUT_ADDR_SLAVE) == ERROR) {
1247 hperh->state = I2C_STATE_READY;
1248 hperh->mode = I2C_MODE_NONE;
1249 __UNLOCK(hperh);
1250
1251 return ERROR;
1252 }
1253
1254 SET_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK);
1255
1256 return OK;
1257 }
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
i2c_handle_s::hdmatx
dma_handle_t hdmatx
Definition: ald_i2c.h:276
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
SET
Definition: type.h:39
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
DMA_MSIGSEL_I2C_RNR
Definition: ald_dma.h:143
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
i2c_dma_slave_recv_cplt
static void i2c_dma_slave_recv_cplt(void *argv)
DMA I2C slave receive process complete callback.
Definition: ald_i2c.c:2487
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
dma_config_t::src
void * src
Definition: ald_dma.h:278
I2C_STAT_BUSY
Definition: ald_i2c.h:217
i2c_dma_error
static void i2c_dma_error(void *argv)
DMA I2C communication error callback.
Definition: ald_i2c.c:2573
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_TIMEOUT_BUSY_FLAG
#define I2C_TIMEOUT_BUSY_FLAG
Definition: ald_i2c.c:173
DMA_DATA_SIZE_BYTE
Definition: ald_dma.h:227
I2C_ERROR_NONE
Definition: ald_i2c.h:44
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
I2C_MODE_SLAVE
Definition: ald_i2c.h:117
DMA_MSEL_I2C0
Definition: ald_dma.h:92
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
I2C_STATE_BUSY_RX
Definition: ald_i2c.h:66
I2C_IT_ADDR
Definition: ald_i2c.h:235
DMA_DATA_INC_BYTE
Definition: ald_dma.h:217
i2c_wait_master_addr_to_timeout
static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, uint32_t flag, uint32_t timeout)
This function handles I2C Communication timeout for Master addressing phase.
Definition: ald_i2c.c:2630
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
I2C_TIMEOUT_ADDR_SLAVE
#define I2C_TIMEOUT_ADDR_SLAVE
Definition: ald_i2c.c:172
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
I2C_MODE_NONE
Definition: ald_i2c.h:115
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
DMA_MSEL_I2C1
Definition: ald_dma.h:93
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
i2c_handle_s::hdmarx
dma_handle_t hdmarx
Definition: ald_i2c.h:277
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ ald_i2c_slave_recv_by_it()

ald_status_t ald_i2c_slave_recv_by_it | ( | i2c_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint32_t | size
 | ) |  |

Receive in slave mode an amount of data in non-blocking mode with Interrupt.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
buf | Pointer to data buffer
size | Amount of data to be sent
Return values
Status,see ald_status_t.

Definition at line 956 of file ald_i2c.c.

957 {
958 if (hperh->state != I2C_STATE_READY)
959 return BUSY;
960
961 if ((buf == NULL) || (size == 0))
962 return ERROR;
963
964 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
965 return BUSY;
966
967 assert_param(IS_I2C_TYPE(hperh->perh));
968 __LOCK(hperh);
969
970 hperh->state = I2C_STATE_BUSY_RX;
971 hperh->mode = I2C_MODE_SLAVE;
972 hperh->error_code = I2C_ERROR_NONE;
973 hperh->p_buff = buf;
974 hperh->xfer_size = size;
975 hperh->xfer_count = 0;
976
977 SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK);
978
979 I2C_CLEAR_IT(hperh , I2C_IT_RXTH);
980 I2C_CLEAR_IT(hperh , I2C_IT_ADDR);
981 I2C_CLEAR_IT(hperh , I2C_IT_STOP);
982
983 I2C_DISABLE_IT(hperh, I2C_FLAG_MASK);
984 I2C_ENABLE_IT(hperh, I2C_IT_RXTH | I2C_IT_ADDR | I2C_IT_STOP);
985
986 return OK;
987 }
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
SET
Definition: type.h:39
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
I2C_STAT_BUSY
Definition: ald_i2c.h:217
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_TIMEOUT_BUSY_FLAG
#define I2C_TIMEOUT_BUSY_FLAG
Definition: ald_i2c.c:173
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
I2C_FLAG_MASK
#define I2C_FLAG_MASK
Definition: ald_i2c.h:300
I2C_MODE_SLAVE
Definition: ald_i2c.h:117
I2C_STATE_BUSY_RX
Definition: ald_i2c.h:66
I2C_IT_ADDR
Definition: ald_i2c.h:235
I2C_DISABLE_IT
#define I2C_DISABLE_IT(x, y)
Definition: ald_i2c.h:303
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
I2C_CLEAR_IT
#define I2C_CLEAR_IT(x, y)
Definition: ald_i2c.h:304
I2C_ENABLE_IT
#define I2C_ENABLE_IT(x, y)
Definition: ald_i2c.h:302
I2C_IT_STOP
Definition: ald_i2c.h:237
I2C_IT_RXTH
Definition: ald_i2c.h:232
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ ald_i2c_slave_send()

ald_status_t ald_i2c_slave_send | ( | i2c_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint32_t | size,
 |  | uint32_t | timeout
 | ) |  |

Transmits in slave mode an amount of data in blocking mode.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
buf | Pointer to data buffer
size | Amount of data to be sent
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 666 of file ald_i2c.c.

667 {
668 uint8_t i = 0;
669
670 if (hperh->state != I2C_STATE_READY)
671 return BUSY;
672
673 if ((buf == NULL) || (size == 0))
674 return ERROR;
675
676 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
677 return BUSY;
678
679 assert_param(IS_I2C_TYPE(hperh->perh));
680 __LOCK(hperh);
681
682 hperh->state = I2C_STATE_BUSY_TX;
683 hperh->mode = I2C_MODE_SLAVE;
684 hperh->error_code = I2C_ERROR_NONE;
685 hperh->p_buff = buf;
686 hperh->xfer_size = size;
687 hperh->xfer_count = 0;
688
689 MODIFY_REG(hperh->perh->FCON, I2C_FCON_TXFTH_MSK, 0x03 << I2C_FCON_TXFTH_POSS);
690 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
691
692 for (i = 0; i < 16; i++) {
693 hperh->perh->TXDATA = (*buf++);
694 --size;
695 hperh->xfer_count++;
696
697 if (size == 0)
698 break;
699 }
700
701 if (i2c_wait_master_addr_to_timeout(hperh, I2C_IT_ADDR, timeout) == ERROR)
702 goto ERROR;
703
704 while (size > 0) {
705 if (i2c_wait_txe_to_timeout(hperh, timeout) == ERROR)
706 goto ERROR;
707
708 for (i = 0; i < 8; i++) {
709 hperh->perh->TXDATA = (*buf++);
710 --size;
711 hperh->xfer_count++;
712
713 if (size == 0)
714 break;
715 }
716 }
717
718 goto SUCCESS;
719
720 ERROR:
721 hperh->state = I2C_STATE_READY;
722 hperh->mode = I2C_MODE_NONE;
723 __UNLOCK(hperh);
724
725 return ERROR;
726
727 SUCCESS:
728 hperh->state = I2C_STATE_READY;
729 hperh->mode = I2C_MODE_NONE;
730 __UNLOCK(hperh);
731
732 return OK;
733 }
I2C_STATE_BUSY_TX
Definition: ald_i2c.h:65
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
SET
Definition: type.h:39
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
i2c_wait_txe_to_timeout
static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout)
This function handles I2C Communication timeout for specific usage of TXE flag.
Definition: ald_i2c.c:2652
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
I2C_STAT_BUSY
Definition: ald_i2c.h:217
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_TIMEOUT_BUSY_FLAG
#define I2C_TIMEOUT_BUSY_FLAG
Definition: ald_i2c.c:173
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
I2C_MODE_SLAVE
Definition: ald_i2c.h:117
I2C_IT_ADDR
Definition: ald_i2c.h:235
i2c_wait_master_addr_to_timeout
static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, uint32_t flag, uint32_t timeout)
This function handles I2C Communication timeout for Master addressing phase.
Definition: ald_i2c.c:2630
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
I2C_MODE_NONE
Definition: ald_i2c.h:115
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ ald_i2c_slave_send_by_dma()

ald_status_t ald_i2c_slave_send_by_dma | ( | i2c_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint8_t | size,
 |  | uint8_t | channel
 | ) |  |

Transmit in slave mode an amount of data in non-blocking mode with DMA.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
buf | Pointer to data buffer
size | Amount of data to be sent
channel | DMA channel as I2C Transmit
Return values
Status,see ald_status_t.

Definition at line 1135 of file ald_i2c.c.

1136 {
1137 if (hperh->state != I2C_STATE_READY)
1138 return BUSY;
1139
1140 if ((buf == NULL) || (size == 0))
1141 return ERROR;
1142
1143 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
1144 return BUSY;
1145
1146 assert_param(IS_I2C_TYPE(hperh->perh));
1147 __LOCK(hperh);
1148
1149 hperh->state = I2C_STATE_BUSY_TX;
1150 hperh->mode = I2C_MODE_SLAVE;
1151 hperh->error_code = I2C_ERROR_NONE;
1152 hperh->p_buff = buf;
1153 hperh->xfer_size = size;
1154 hperh->xfer_count = 0;
1155
1156 if (size >= 0xFF)
1157 size = 0xFF;
1158
1159 if (hperh->hdmatx.perh == NULL)
1160 hperh->hdmatx.perh = DMA0;
1161
1162 hperh->hdmatx.cplt_cbk = i2c_dma_slave_send_cplt;
1163 hperh->hdmatx.cplt_arg = hperh;
1164 hperh->hdmatx.err_cbk = i2c_dma_error;
1165 hperh->hdmatx.err_arg = hperh;
1166
1167 ald_dma_config_struct(&hperh->hdmatx.config);
1168 hperh->hdmatx.config.burst = ENABLE;
1169 hperh->hdmatx.config.src = (void *)buf;
1170 hperh->hdmatx.config.dst = (void *)&hperh->perh->TXDATA;
1171 hperh->hdmatx.config.size = size;
1172 hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE;
1173 hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE;
1174 hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
1175 hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1;
1176 hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY;
1177 hperh->hdmatx.config.channel = channel;
1178 ald_dma_config_basic(&hperh->hdmatx);
1179
1180 if (i2c_wait_master_addr_to_timeout(hperh, I2C_IT_ADDR, I2C_TIMEOUT_ADDR_SLAVE) == ERROR) {
1181 hperh->state = I2C_STATE_READY;
1182 hperh->mode = I2C_MODE_NONE;
1183 __UNLOCK(hperh);
1184
1185 return ERROR;
1186 }
1187
1188 SET_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK);
1189
1190 return OK;
1191 }
I2C_STATE_BUSY_TX
Definition: ald_i2c.h:65
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
i2c_handle_s::hdmatx
dma_handle_t hdmatx
Definition: ald_i2c.h:276
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
i2c_dma_slave_send_cplt
static void i2c_dma_slave_send_cplt(void *argv)
DMA I2C slave transmit process complete callback.
Definition: ald_i2c.c:2431
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
SET
Definition: type.h:39
DMA_MSIGSEL_I2C_TXEMPTY
Definition: ald_dma.h:144
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
dma_config_t::src
void * src
Definition: ald_dma.h:278
I2C_STAT_BUSY
Definition: ald_i2c.h:217
i2c_dma_error
static void i2c_dma_error(void *argv)
DMA I2C communication error callback.
Definition: ald_i2c.c:2573
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_TIMEOUT_BUSY_FLAG
#define I2C_TIMEOUT_BUSY_FLAG
Definition: ald_i2c.c:173
DMA_DATA_SIZE_BYTE
Definition: ald_dma.h:227
I2C_ERROR_NONE
Definition: ald_i2c.h:44
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
I2C_MODE_SLAVE
Definition: ald_i2c.h:117
DMA_MSEL_I2C0
Definition: ald_dma.h:92
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
I2C_IT_ADDR
Definition: ald_i2c.h:235
DMA_DATA_INC_BYTE
Definition: ald_dma.h:217
i2c_wait_master_addr_to_timeout
static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, uint32_t flag, uint32_t timeout)
This function handles I2C Communication timeout for Master addressing phase.
Definition: ald_i2c.c:2630
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
I2C_TIMEOUT_ADDR_SLAVE
#define I2C_TIMEOUT_ADDR_SLAVE
Definition: ald_i2c.c:172
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
I2C_MODE_NONE
Definition: ald_i2c.h:115
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
DMA_MSEL_I2C1
Definition: ald_dma.h:93
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ ald_i2c_slave_send_by_it()

ald_status_t ald_i2c_slave_send_by_it | ( | i2c_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint32_t | size
 | ) |  |

Transmit in slave mode an amount of data in non-blocking mode with Interrupt.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
buf | Pointer to data buffer
size | Amount of data to be sent
Return values
Status,see ald_status_t.

Definition at line 914 of file ald_i2c.c.

915 {
916 if (hperh->state != I2C_STATE_READY)
917 return BUSY;
918
919 if ((buf == NULL) || (size == 0))
920 return ERROR;
921
922 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
923 return BUSY;
924
925 assert_param(IS_I2C_TYPE(hperh->perh));
926 __LOCK(hperh);
927
928 hperh->state = I2C_STATE_BUSY_TX;
929 hperh->mode = I2C_MODE_SLAVE;
930 hperh->error_code = I2C_ERROR_NONE;
931 hperh->p_buff = buf;
932 hperh->xfer_size = size;
933 hperh->xfer_count = 0;
934
935 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
936
937 I2C_CLEAR_IT(hperh , I2C_IT_TXTH);
938 I2C_CLEAR_IT(hperh , I2C_IT_ADDR);
939 I2C_CLEAR_IT(hperh , I2C_IT_NACK);
940 I2C_CLEAR_IT(hperh , I2C_IT_STOP);
941
942 I2C_DISABLE_IT(hperh, I2C_FLAG_MASK);
943 I2C_ENABLE_IT(hperh, I2C_IT_ADDR | I2C_IT_NACK | I2C_IT_STOP | I2C_IT_TXTH);
944
945 return OK;
946 }
I2C_STATE_BUSY_TX
Definition: ald_i2c.h:65
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
SET
Definition: type.h:39
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
I2C_STAT_BUSY
Definition: ald_i2c.h:217
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_TIMEOUT_BUSY_FLAG
#define I2C_TIMEOUT_BUSY_FLAG
Definition: ald_i2c.c:173
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
I2C_FLAG_MASK
#define I2C_FLAG_MASK
Definition: ald_i2c.h:300
I2C_MODE_SLAVE
Definition: ald_i2c.h:117
I2C_IT_ADDR
Definition: ald_i2c.h:235
I2C_IT_TXTH
Definition: ald_i2c.h:228
I2C_DISABLE_IT
#define I2C_DISABLE_IT(x, y)
Definition: ald_i2c.h:303
I2C_IT_NACK
Definition: ald_i2c.h:236
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
I2C_CLEAR_IT
#define I2C_CLEAR_IT(x, y)
Definition: ald_i2c.h:304
I2C_ENABLE_IT
#define I2C_ENABLE_IT(x, y)
Definition: ald_i2c.h:302
I2C_IT_STOP
Definition: ald_i2c.h:237
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63


ALD User Manual: Peripheral state and Errors functions

Functions
Peripheral state and Errors functions
EASTSOFT ES32F3xx ALD » I2C » I2C Public functions

Peripheral state and Errors functions. More...

Collaboration diagram for Peripheral state and Errors functions:

Functions

i2c_state_t | ald_i2c_get_state (i2c_handle_t *hperh)
Return the I2C handle state. More...
uint32_t | ald_i2c_get_error (i2c_handle_t *hperh)
Return the I2C error code. More...
void | ald_i2c_clear_flag_status (i2c_handle_t *hperh, i2c_interrupt_t flag)
Clear the I2C interrupt flag. More...
flag_status_t | ald_i2c_get_mask_flag_status (i2c_handle_t *hperh, i2c_interrupt_t flag)
Get the status of interrupt flag and interupt source. More...
flag_status_t | ald_i2c_get_flag_status (i2c_handle_t *hperh, i2c_interrupt_t flag)
Get the status of I2C interrupt flag. More...
it_status_t | ald_i2c_get_it_status (i2c_handle_t *hperh, i2c_interrupt_t it)
Get the status of I2C interrupt source. More...

Detailed Description

Peripheral state and Errors functions.

 ===============================================================================
            ##### Peripheral state and Errors functions #####
 ===============================================================================
    [..]
    This subsection permits to get in run-time the status of the peripheral
    and the data flow.

Function Documentation

◆ ald_i2c_clear_flag_status()

void ald_i2c_clear_flag_status | ( | i2c_handle_t * | hperh,
 |  | i2c_interrupt_t | flag
 | ) |  |

Clear the I2C interrupt flag.

Parameters
hperh | Pointer to a i2c_handle_t structure.
flag | Specifies the I2C interrupt flag.
Return values
None

Definition at line 2101 of file ald_i2c.c.

2102 {
2103 assert_param(IS_I2C_TYPE(hperh->perh));
2104 assert_param(IS_I2C_IT(flag));
2105
2106 hperh->perh->ICR = flag;
2107 return;
2108 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
IS_I2C_IT
#define IS_I2C_IT(x)
Definition: ald_i2c.h:336
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270

◆ ald_i2c_get_error()

uint32_t ald_i2c_get_error ( i2c_handle_t * hperh )

Return the I2C error code.

Parameters
hperh Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
Return values
I2C Error Code

Definition at line 1836 of file ald_i2c.c.

1837 {
1838 return hperh->error_code;
1839 }
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282

◆ ald_i2c_get_flag_status()

flag_status_t ald_i2c_get_flag_status | ( | i2c_handle_t * | hperh,
 |  | i2c_interrupt_t | flag
 | ) |  |

Get the status of I2C interrupt flag.

Parameters
hperh | Pointer to a i2c_handle_t structure.
flag | Specifies the I2C interrupt flag. This parameter can be one of the i2c_interrupt_t.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 2063 of file ald_i2c.c.

2064 {
2065 assert_param(IS_I2C_TYPE(hperh->perh));
2066 assert_param(IS_I2C_IT(flag));
2067
2068 if (hperh->perh->RIF & flag)
2069 return SET;
2070
2071 return RESET;
2072 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
IS_I2C_IT
#define IS_I2C_IT(x)
Definition: ald_i2c.h:336
RESET
Definition: type.h:38
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270

◆ ald_i2c_get_it_status()

it_status_t ald_i2c_get_it_status | ( | i2c_handle_t * | hperh,
 |  | i2c_interrupt_t | it
 | ) |  |

Get the status of I2C interrupt source.

Parameters
hperh | Pointer to a i2c_handle_t structure.
it | Specifies the I2C interrupt source. This parameter can be one of the i2c_interrupt_t.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 2041 of file ald_i2c.c.

2042 {
2043 it_status_t status = RESET;
2044
2045 assert_param(IS_I2C_TYPE(hperh->perh));
2046 assert_param(IS_I2C_IT(it));
2047
2048 if (hperh->perh->IVS & it)
2049 status = SET;
2050
2051 return status;
2052 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
IS_I2C_IT
#define IS_I2C_IT(x)
Definition: ald_i2c.h:336
RESET
Definition: type.h:38
it_status_t
enum flag_status_t it_status_t
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270

◆ ald_i2c_get_mask_flag_status()

flag_status_t ald_i2c_get_mask_flag_status | ( | i2c_handle_t * | hperh,
 |  | i2c_interrupt_t | flag
 | ) |  |

Get the status of interrupt flag and interupt source.

Parameters
hperh | Pointer to a i2c_handle_t structure.
flag | Specifies the I2C interrupt flag. This parameter can be one of the i2c_interrupt_t.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 2084 of file ald_i2c.c.

2085 {
2086 assert_param(IS_I2C_TYPE(hperh->perh));
2087 assert_param(IS_I2C_IT(flag));
2088
2089 if (hperh->perh->IFM & flag)
2090 return SET;
2091
2092 return RESET;
2093 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
IS_I2C_IT
#define IS_I2C_IT(x)
Definition: ald_i2c.h:336
RESET
Definition: type.h:38
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270

◆ ald_i2c_get_state()

i2c_state_t ald_i2c_get_state ( i2c_handle_t * hperh )

Return the I2C handle state.

Parameters
hperh Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
Return values
ald_status_t state

Definition at line 1825 of file ald_i2c.c.

1826 {
1827 return hperh->state;
1828 }
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280


ALD User Manual: IRQ Handler and Callbacks

Functions
IRQ Handler and Callbacks
EASTSOFT ES32F3xx ALD » I2C » I2C Public functions
Collaboration diagram for IRQ Handler and Callbacks:

Functions

void | ald_i2c_ev_irq_handler (i2c_handle_t *hperh)
This function handles I2C event interrupt request. More...
void | ald_i2c_er_irq_handler (i2c_handle_t *hperh)
This function handles I2C error interrupt request. More...
void | ald_i2c_interrupt_config (i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state)
Enable/disable the specified I2C interrupts. More...
it_status_t | ald_i2c_get_it_status (i2c_handle_t *hperh, i2c_interrupt_t it)
Get the status of I2C interrupt source. More...
flag_status_t | ald_i2c_get_flag_status (i2c_handle_t *hperh, i2c_interrupt_t flag)
Get the status of I2C interrupt flag. More...
flag_status_t | ald_i2c_get_mask_flag_status (i2c_handle_t *hperh, i2c_interrupt_t flag)
Get the status of interrupt flag and interupt source. More...
void | ald_i2c_clear_flag_status (i2c_handle_t *hperh, i2c_interrupt_t flag)
Clear the I2C interrupt flag. More...

Detailed Description

Function Documentation

◆ ald_i2c_clear_flag_status()

void ald_i2c_clear_flag_status | ( | i2c_handle_t * | hperh,
 |  | i2c_interrupt_t | flag
 | ) |  |

Clear the I2C interrupt flag.

Parameters
hperh | Pointer to a i2c_handle_t structure.
flag | Specifies the I2C interrupt flag.
Return values
None

Definition at line 2101 of file ald_i2c.c.

2102 {
2103 assert_param(IS_I2C_TYPE(hperh->perh));
2104 assert_param(IS_I2C_IT(flag));
2105
2106 hperh->perh->ICR = flag;
2107 return;
2108 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
IS_I2C_IT
#define IS_I2C_IT(x)
Definition: ald_i2c.h:336
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270

◆ ald_i2c_er_irq_handler()

void ald_i2c_er_irq_handler ( i2c_handle_t * hperh )

This function handles I2C error interrupt request.

Parameters
hperh pointer to a i2c_handle_t structure that contains the configuration information for I2C module
Return values
NONE

< Transmit FIFO overrun interrupt

Definition at line 1935 of file ald_i2c.c.

1936 {
1938 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TXOV) == SET) {
1939 ald_i2c_clear_flag_status(hperh, I2C_IT_TXOV);
1940 hperh->error_code |= I2C_ERROR_TOV;
1941 }
1943 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TXUD) == SET) {
1944 ald_i2c_clear_flag_status(hperh, I2C_IT_TXUD);
1945 hperh->error_code |= I2C_ERROR_TUD;
1946 }
1947
1949 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_RXOV) == SET) {
1950 ald_i2c_clear_flag_status(hperh, I2C_IT_RXOV);
1951 hperh->error_code |= I2C_ERROR_ROV;
1952 }
1953
1955 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_RXUD) == SET) {
1956 ald_i2c_clear_flag_status(hperh, I2C_IT_RXUD);
1957 hperh->error_code |= I2C_ERROR_RUD;
1958 }
1959
1961 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_NACK) == SET) {
1962 if (hperh->xfer_count != hperh->xfer_size)
1963 hperh->state |= I2C_ERROR_AF;
1964
1965 if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM))
1966 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
1967
1968 I2C_DISABLE_IT(hperh, I2C_IT_TXTH | I2C_IT_NACK);
1969 ald_i2c_clear_flag_status(hperh, I2C_IT_NACK);
1970 }
1971
1973 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_BERR) == SET) {
1974 ald_i2c_clear_flag_status(hperh, I2C_IT_BERR);
1975 hperh->state |= I2C_ERROR_BERR;
1976 }
1977
1979 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_ARLO) == SET) {
1980 ald_i2c_clear_flag_status(hperh, I2C_IT_ARLO);
1981 hperh->state |= I2C_ERROR_ARLO;
1982 }
1983
1985 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_PECE) == SET) {
1986 ald_i2c_clear_flag_status(hperh, I2C_IT_PECE);
1987 }
1988
1990 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TOUT) == SET) {
1991 ald_i2c_clear_flag_status(hperh, I2C_IT_TOUT);
1992 hperh->state |= I2C_ERROR_TIMEOUT;
1993 }
1994
1996 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_ALERT) == SET) {
1997 ald_i2c_clear_flag_status(hperh, I2C_IT_ALERT);
1998 }
1999
2000 hperh->state = I2C_STATE_READY;
2001 hperh->mode = I2C_MODE_NONE;
2002 __UNLOCK(hperh);
2003
2004 if (hperh->error_callback)
2005 hperh->error_callback(hperh);
2006 }
I2C_ERROR_AF
Definition: ald_i2c.h:48
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
I2C_ERROR_RUD
Definition: ald_i2c.h:47
SET
Definition: type.h:39
I2C_MODE_MEM
Definition: ald_i2c.h:118
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_ERROR_TUD
Definition: ald_i2c.h:51
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
I2C_IT_ALERT
Definition: ald_i2c.h:242
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
I2C_ERROR_BERR
Definition: ald_i2c.h:45
I2C_IT_BERR
Definition: ald_i2c.h:238
I2C_MODE_MASTER
Definition: ald_i2c.h:116
ald_i2c_clear_flag_status
void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag)
Clear the I2C interrupt flag.
Definition: ald_i2c.c:2101
i2c_handle_s::error_callback
void(* error_callback)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:290
I2C_ERROR_TIMEOUT
Definition: ald_i2c.h:55
I2C_ERROR_ARLO
Definition: ald_i2c.h:46
I2C_IT_ARLO
Definition: ald_i2c.h:239
I2C_ERROR_TOV
Definition: ald_i2c.h:52
I2C_IT_TOUT
Definition: ald_i2c.h:241
I2C_IT_TXTH
Definition: ald_i2c.h:228
I2C_DISABLE_IT
#define I2C_DISABLE_IT(x, y)
Definition: ald_i2c.h:303
I2C_IT_NACK
Definition: ald_i2c.h:236
I2C_ERROR_ROV
Definition: ald_i2c.h:49
I2C_IT_RXUD
Definition: ald_i2c.h:231
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
I2C_IT_TXUD
Definition: ald_i2c.h:227
I2C_MODE_NONE
Definition: ald_i2c.h:115
I2C_IT_TXOV
Definition: ald_i2c.h:226
I2C_IT_PECE
Definition: ald_i2c.h:240
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
ald_i2c_get_mask_flag_status
flag_status_t ald_i2c_get_mask_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag)
Get the status of interrupt flag and interupt source.
Definition: ald_i2c.c:2084
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63
I2C_IT_RXOV
Definition: ald_i2c.h:230

◆ ald_i2c_ev_irq_handler()

void ald_i2c_ev_irq_handler ( i2c_handle_t * hperh )

This function handles I2C event interrupt request.

Parameters
hperh Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
Return values
None

< Transmit FIFO threshold interrupt

Definition at line 1854 of file ald_i2c.c.

1855 {
1856 uint32_t size = hperh->xfer_size - hperh->xfer_count;
1857
1859 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TXTH) == SET) {
1860 ald_i2c_clear_flag_status(hperh, I2C_IT_TXTH);
1861 if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) {
1862 i2c_master_send_txe(hperh);
1863 }
1864 else if (hperh->mode == I2C_MODE_SLAVE) {
1865 i2c_slave_send_txe(hperh);
1866 }
1867 }
1868
1870 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_RXTH) == SET) {
1871 ald_i2c_clear_flag_status(hperh, I2C_IT_RXTH);
1872 if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) {
1873 i2c_master_recv_rxne(hperh);
1874 }
1875 else if (hperh->mode == I2C_MODE_SLAVE) {
1876 i2c_slave_recv_rxne(hperh);
1877 }
1878 }
1879
1881 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TC) == SET) {
1882 if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) {
1883 if (I2C_MASTER_GET_DIR(hperh) == RESET) {
1884 i2c_master_send_tc(hperh);
1885 }
1886 else {
1887 i2c_master_recv_tc(hperh);
1888 }
1889 }
1890
1891 ald_i2c_clear_flag_status(hperh, I2C_IT_TC);
1892 }
1893
1895 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TCR) == SET) {
1896 if (size > 0xFF) {
1897 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
1898 }
1899 else {
1900 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
1901 CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
1902 }
1903
1904 ald_i2c_clear_flag_status(hperh, I2C_IT_TCR);
1905 }
1906
1908 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TXE) == SET) {
1909 ald_i2c_clear_flag_status(hperh, I2C_IT_TXE);
1910 }
1911
1913 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_RXF) == SET) {
1914 ald_i2c_clear_flag_status(hperh, I2C_IT_RXF);
1915 }
1916
1918 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_ADDR) == SET) {
1919 ald_i2c_clear_flag_status(hperh, I2C_IT_ADDR);
1920 }
1921
1923 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_STOP) == SET) {
1924 i2c_slave_stopf(hperh);
1925 ald_i2c_clear_flag_status(hperh, I2C_IT_STOP);
1926 }
1927 }
i2c_slave_send_txe
static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh)
Handle TXE flag for Slave Transmit mode.
Definition: ald_i2c.c:2212
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
SET
Definition: type.h:39
I2C_MODE_MEM
Definition: ald_i2c.h:118
I2C_IT_TXE
Definition: ald_i2c.h:225
I2C_IT_RXF
Definition: ald_i2c.h:229
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
RESET
Definition: type.h:38
i2c_master_send_tc
static ald_status_t i2c_master_send_tc(i2c_handle_t *hperh)
Handle transmit complete flag for Master Transmit mode.
Definition: ald_i2c.c:2124
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_slave_stopf
static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh)
Handle STOPF flag for Slave mode.
Definition: ald_i2c.c:2244
i2c_master_recv_tc
static ald_status_t i2c_master_recv_tc(i2c_handle_t *hperh)
Handle receive complete for Master Receive mode.
Definition: ald_i2c.c:2169
I2C_MODE_SLAVE
Definition: ald_i2c.h:117
i2c_master_recv_rxne
static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh)
Handle receive not empty for Master Receive mode.
Definition: ald_i2c.c:2196
I2C_MODE_MASTER
Definition: ald_i2c.h:116
ald_i2c_clear_flag_status
void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag)
Clear the I2C interrupt flag.
Definition: ald_i2c.c:2101
i2c_master_send_txe
static ald_status_t i2c_master_send_txe(i2c_handle_t *hperh)
Handle transmit empty flag for Master Transmit mode.
Definition: ald_i2c.c:2153
I2C_IT_ADDR
Definition: ald_i2c.h:235
I2C_MASTER_GET_DIR
#define I2C_MASTER_GET_DIR(x)
Definition: ald_i2c.h:308
I2C_IT_TXTH
Definition: ald_i2c.h:228
i2c_slave_recv_rxne
static ald_status_t i2c_slave_recv_rxne(i2c_handle_t *hperh)
Handle RXNE flag for Slave Receive mode.
Definition: ald_i2c.c:2228
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
I2C_IT_STOP
Definition: ald_i2c.h:237
I2C_IT_TC
Definition: ald_i2c.h:233
I2C_IT_TCR
Definition: ald_i2c.h:234
I2C_IT_RXTH
Definition: ald_i2c.h:232
ald_i2c_get_mask_flag_status
flag_status_t ald_i2c_get_mask_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag)
Get the status of interrupt flag and interupt source.
Definition: ald_i2c.c:2084
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270

◆ ald_i2c_get_flag_status()

flag_status_t ald_i2c_get_flag_status | ( | i2c_handle_t * | hperh,
 |  | i2c_interrupt_t | flag
 | ) |  |

Get the status of I2C interrupt flag.

Parameters
hperh | Pointer to a i2c_handle_t structure.
flag | Specifies the I2C interrupt flag. This parameter can be one of the i2c_interrupt_t.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 2063 of file ald_i2c.c.

2064 {
2065 assert_param(IS_I2C_TYPE(hperh->perh));
2066 assert_param(IS_I2C_IT(flag));
2067
2068 if (hperh->perh->RIF & flag)
2069 return SET;
2070
2071 return RESET;
2072 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
IS_I2C_IT
#define IS_I2C_IT(x)
Definition: ald_i2c.h:336
RESET
Definition: type.h:38
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270

◆ ald_i2c_get_it_status()

it_status_t ald_i2c_get_it_status | ( | i2c_handle_t * | hperh,
 |  | i2c_interrupt_t | it
 | ) |  |

Get the status of I2C interrupt source.

Parameters
hperh | Pointer to a i2c_handle_t structure.
it | Specifies the I2C interrupt source. This parameter can be one of the i2c_interrupt_t.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 2041 of file ald_i2c.c.

2042 {
2043 it_status_t status = RESET;
2044
2045 assert_param(IS_I2C_TYPE(hperh->perh));
2046 assert_param(IS_I2C_IT(it));
2047
2048 if (hperh->perh->IVS & it)
2049 status = SET;
2050
2051 return status;
2052 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
IS_I2C_IT
#define IS_I2C_IT(x)
Definition: ald_i2c.h:336
RESET
Definition: type.h:38
it_status_t
enum flag_status_t it_status_t
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270

◆ ald_i2c_get_mask_flag_status()

flag_status_t ald_i2c_get_mask_flag_status | ( | i2c_handle_t * | hperh,
 |  | i2c_interrupt_t | flag
 | ) |  |

Get the status of interrupt flag and interupt source.

Parameters
hperh | Pointer to a i2c_handle_t structure.
flag | Specifies the I2C interrupt flag. This parameter can be one of the i2c_interrupt_t.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 2084 of file ald_i2c.c.

2085 {
2086 assert_param(IS_I2C_TYPE(hperh->perh));
2087 assert_param(IS_I2C_IT(flag));
2088
2089 if (hperh->perh->IFM & flag)
2090 return SET;
2091
2092 return RESET;
2093 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
IS_I2C_IT
#define IS_I2C_IT(x)
Definition: ald_i2c.h:336
RESET
Definition: type.h:38
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270

◆ ald_i2c_interrupt_config()

void ald_i2c_interrupt_config | ( | i2c_handle_t * | hperh,
 |  | i2c_interrupt_t | it,
 |  | type_func_t | state
 | ) |  |

Enable/disable the specified I2C interrupts.

Parameters
hperh | Pointer to a i2c_handle_t structure.
it | Specifies the i2c interrupt sources to be enabled or disabled.
state New state of the specified I2C interrupts. This parameter can be:
  • ENABLE
  • DISABLE
Return values
None

Definition at line 2018 of file ald_i2c.c.

2019 {
2020 assert_param(IS_I2C_TYPE(hperh->perh));
2021 assert_param(IS_I2C_IT(it));
2022 assert_param(IS_FUNC_STATE(state));
2023
2024 if (state == ENABLE)
2025 hperh->perh->IER = it;
2026 else
2027 hperh->perh->IDR = it;
2028
2029 return;
2030 }
ENABLE
Definition: type.h:49
assert_param
#define assert_param(x)
Definition: type.h:88
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
IS_I2C_IT
#define IS_I2C_IT(x)
Definition: ald_i2c.h:336
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270


ALD User Manual: I2C Private Functions

Functions
I2C Private Functions
EASTSOFT ES32F3xx ALD » I2C EASTSOFT ES32F3xx ALD » I2C » | I2C Public functions
Collaboration diagram for I2C Private Functions:

Functions

static void | i2c_dma_master_send_cplt (void *argv)
DMA I2C master transmit process complete callback. More...
static void | i2c_dma_master_recv_cplt (void *argv)
DMA I2C master receive process complete callback. More...
static void | i2c_dma_slave_send_cplt (void *argv)
DMA I2C slave transmit process complete callback. More...
static void | i2c_dma_slave_recv_cplt (void *argv)
DMA I2C slave receive process complete callback. More...
static void | i2c_dma_mem_send_cplt (void *argv)
DMA I2C Memory Write process complete callback. More...
static void | i2c_dma_mem_recv_cplt (void *argv)
DMA I2C Memory Read process complete callback. More...
static void | i2c_dma_error (void *argv)
DMA I2C communication error callback. More...
static ald_status_t | i2c_req_mem_read (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout)
Master sends target device address followed by internal memory address for read request. More...
static ald_status_t | i2c_master_req_write (i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout)
Master sends target device address followed by internal memory address for write request. More...
static ald_status_t | i2c_master_req_read (i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout)
Master sends target device address followed by internal memory address for read request. More...
static ald_status_t | i2c_req_mem_write (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout)
Master sends target device address followed by internal memory address for write request. More...
static ald_status_t | i2c_wait_flag_change_to_timeout (i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout. More...
static ald_status_t | i2c_wait_master_addr_to_timeout (i2c_handle_t *hperh, uint32_t flag, uint32_t timeout)
This function handles I2C Communication timeout for Master addressing phase. More...
static ald_status_t | i2c_wait_txe_to_timeout (i2c_handle_t *hperh, uint32_t timeout)
This function handles I2C Communication timeout for specific usage of TXE flag. More...
static ald_status_t | i2c_wait_rxne_to_timeout (i2c_handle_t *hperh, uint32_t timeout)
This function handles I2C Communication timeout for specific usage of RXNE flag. More...
static ald_status_t | i2c_master_send_tc (i2c_handle_t *hperh)
Handle transmit complete flag for Master Transmit mode. More...
static ald_status_t | i2c_master_send_txe (i2c_handle_t *hperh)
Handle transmit empty flag for Master Transmit mode. More...
static ald_status_t | i2c_master_recv_tc (i2c_handle_t *hperh)
Handle receive complete for Master Receive mode. More...
static ald_status_t | i2c_master_recv_rxne (i2c_handle_t *hperh)
Handle receive not empty for Master Receive mode. More...
static ald_status_t | i2c_slave_send_txe (i2c_handle_t *hperh)
Handle TXE flag for Slave Transmit mode. More...
static ald_status_t | i2c_slave_recv_rxne (i2c_handle_t *hperh)
Handle RXNE flag for Slave Receive mode. More...
static ald_status_t | i2c_slave_stopf (i2c_handle_t *hperh)
Handle STOPF flag for Slave mode. More...

Detailed Description

Function Documentation

◆ i2c_dma_error()

static void i2c_dma_error ( void * argv )
static

DMA I2C communication error callback.

Parameters
argv I2C handle
Return values
None

Definition at line 2573 of file ald_i2c.c.

2574 {
2575 i2c_handle_t* hperh = (i2c_handle_t*)argv;
2576
2577 hperh->xfer_count = 0;
2578 hperh->state = I2C_STATE_READY;
2579 hperh->mode = I2C_MODE_NONE;
2580 hperh->error_code |= I2C_ERROR_DMA;
2581 __UNLOCK(hperh);
2582
2583 if (hperh->error_callback)
2584 hperh->error_callback(hperh);
2585 }
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::error_callback
void(* error_callback)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:290
i2c_handle_s
I2C handle Structure definition.
Definition: ald_i2c.h:269
I2C_ERROR_DMA
Definition: ald_i2c.h:54
I2C_MODE_NONE
Definition: ald_i2c.h:115
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ i2c_dma_master_recv_cplt()

static void i2c_dma_master_recv_cplt ( void * argv )
static

DMA I2C master receive process complete callback.

Parameters
argv I2C handle
Return values
None

Definition at line 2457 of file ald_i2c.c.

2458 {
2459 i2c_handle_t* hperh = (i2c_handle_t*)argv;
2460
2461 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == ERROR)
2462 hperh->error_code |= I2C_ERROR_TIMEOUT;
2463
2464 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
2465 CLEAR_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK);
2466
2467 hperh->xfer_count = 0;
2468 hperh->state = I2C_STATE_READY;
2469 hperh->mode = I2C_MODE_NONE;
2470 __UNLOCK(hperh);
2471
2472 if (hperh->error_code != I2C_ERROR_NONE) {
2473 if (hperh->error_callback)
2474 hperh->error_callback(hperh);
2475 }
2476 else {
2477 if (hperh->master_rx_cplt_cbk)
2478 hperh->master_rx_cplt_cbk(hperh);
2479 }
2480 }
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
I2C_TIMEOUT_FLAG
#define I2C_TIMEOUT_FLAG
Definition: ald_i2c.c:171
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
RESET
Definition: type.h:38
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
i2c_handle_s::error_callback
void(* error_callback)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:290
I2C_STAT_TC
Definition: ald_i2c.h:215
I2C_ERROR_TIMEOUT
Definition: ald_i2c.h:55
i2c_handle_s
I2C handle Structure definition.
Definition: ald_i2c.h:269
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
I2C_MODE_NONE
Definition: ald_i2c.h:115
i2c_handle_s::master_rx_cplt_cbk
void(* master_rx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:285
ERROR
Definition: utils.h:56
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ i2c_dma_master_send_cplt()

static void i2c_dma_master_send_cplt ( void * argv )
static

DMA I2C master transmit process complete callback.

Parameters
argv I2C handle
Return values
None

Definition at line 2401 of file ald_i2c.c.

2402 {
2403 i2c_handle_t* hperh = (i2c_handle_t*)argv;
2404
2405 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == ERROR)
2406 hperh->error_code |= I2C_ERROR_TIMEOUT;
2407
2408 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
2409 CLEAR_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK);
2410
2411 hperh->xfer_count = 0;
2412 hperh->state = I2C_STATE_READY;
2413 hperh->mode = I2C_MODE_NONE;
2414 __UNLOCK(hperh);
2415
2416 if (hperh->error_code != I2C_ERROR_NONE) {
2417 if (hperh->error_callback)
2418 hperh->error_callback(hperh);
2419 }
2420 else {
2421 if (hperh->master_tx_cplt_cbk)
2422 hperh->master_tx_cplt_cbk(hperh);
2423 }
2424 }
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
I2C_TIMEOUT_FLAG
#define I2C_TIMEOUT_FLAG
Definition: ald_i2c.c:171
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
RESET
Definition: type.h:38
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
i2c_handle_s::error_callback
void(* error_callback)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:290
I2C_STAT_TC
Definition: ald_i2c.h:215
I2C_ERROR_TIMEOUT
Definition: ald_i2c.h:55
i2c_handle_s
I2C handle Structure definition.
Definition: ald_i2c.h:269
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
i2c_handle_s::master_tx_cplt_cbk
void(* master_tx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:284
I2C_MODE_NONE
Definition: ald_i2c.h:115
ERROR
Definition: utils.h:56
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ i2c_dma_mem_recv_cplt()

static void i2c_dma_mem_recv_cplt ( void * argv )
static

DMA I2C Memory Read process complete callback.

Parameters
argv I2C handle
Return values
None

Definition at line 2543 of file ald_i2c.c.

2544 {
2545 i2c_handle_t* hperh = (i2c_handle_t*)argv;
2546
2547 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == OK)
2548 hperh->error_code |= I2C_ERROR_TIMEOUT;
2549
2550 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
2551 CLEAR_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK);
2552
2553 hperh->xfer_count = 0;
2554 hperh->state = I2C_STATE_READY;
2555 hperh->mode = I2C_MODE_NONE;
2556 __UNLOCK(hperh);
2557
2558 if (hperh->error_code != I2C_ERROR_NONE) {
2559 if (hperh->error_callback)
2560 hperh->error_callback(hperh);
2561 }
2562 else {
2563 if (hperh->mem_rx_cplt_cbk)
2564 hperh->mem_rx_cplt_cbk(hperh);
2565 }
2566 }
i2c_handle_s::mem_rx_cplt_cbk
void(* mem_rx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:289
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
I2C_TIMEOUT_FLAG
#define I2C_TIMEOUT_FLAG
Definition: ald_i2c.c:171
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
RESET
Definition: type.h:38
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
i2c_handle_s::error_callback
void(* error_callback)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:290
I2C_STAT_TC
Definition: ald_i2c.h:215
I2C_ERROR_TIMEOUT
Definition: ald_i2c.h:55
i2c_handle_s
I2C handle Structure definition.
Definition: ald_i2c.h:269
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
I2C_MODE_NONE
Definition: ald_i2c.h:115
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ i2c_dma_mem_send_cplt()

static void i2c_dma_mem_send_cplt ( void * argv )
static

DMA I2C Memory Write process complete callback.

Parameters
argv I2C handle
Return values
None

Definition at line 2513 of file ald_i2c.c.

2514 {
2515 i2c_handle_t* hperh = (i2c_handle_t*)argv;
2516
2517 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == ERROR)
2518 hperh->error_code |= I2C_ERROR_TIMEOUT;
2519
2520 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
2521 CLEAR_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK);
2522
2523 hperh->xfer_count = 0;
2524 hperh->state = I2C_STATE_READY;
2525 hperh->mode = I2C_MODE_NONE;
2526 __UNLOCK(hperh);
2527
2528 if (hperh->error_code != I2C_ERROR_NONE) {
2529 if (hperh->error_callback)
2530 hperh->error_callback(hperh);
2531 }
2532 else {
2533 if (hperh->mem_tx_cplt_cbk)
2534 hperh->mem_tx_cplt_cbk(hperh);
2535 }
2536 }
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
I2C_TIMEOUT_FLAG
#define I2C_TIMEOUT_FLAG
Definition: ald_i2c.c:171
i2c_handle_s::mem_tx_cplt_cbk
void(* mem_tx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:288
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
RESET
Definition: type.h:38
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
i2c_handle_s::error_callback
void(* error_callback)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:290
I2C_STAT_TC
Definition: ald_i2c.h:215
I2C_ERROR_TIMEOUT
Definition: ald_i2c.h:55
i2c_handle_s
I2C handle Structure definition.
Definition: ald_i2c.h:269
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
I2C_MODE_NONE
Definition: ald_i2c.h:115
ERROR
Definition: utils.h:56
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ i2c_dma_slave_recv_cplt()

static void i2c_dma_slave_recv_cplt ( void * argv )
static

DMA I2C slave receive process complete callback.

Parameters
argv I2C handle
Return values
None

Definition at line 2487 of file ald_i2c.c.

2488 {
2489 i2c_handle_t* hperh = (i2c_handle_t*)argv;
2490
2491 CLEAR_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK);
2492
2493 hperh->xfer_count = 0;
2494 hperh->state = I2C_STATE_READY;
2495 hperh->mode = I2C_MODE_NONE;
2496 __UNLOCK(hperh);
2497
2498 if (hperh->error_code != I2C_ERROR_NONE) {
2499 if (hperh->error_callback)
2500 hperh->error_callback(hperh);
2501 }
2502 else {
2503 if (hperh->slave_rx_cplt_cbk)
2504 hperh->slave_rx_cplt_cbk(hperh);
2505 }
2506 }
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::error_callback
void(* error_callback)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:290
i2c_handle_s::slave_rx_cplt_cbk
void(* slave_rx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:287
i2c_handle_s
I2C handle Structure definition.
Definition: ald_i2c.h:269
I2C_MODE_NONE
Definition: ald_i2c.h:115
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ i2c_dma_slave_send_cplt()

static void i2c_dma_slave_send_cplt ( void * argv )
static

DMA I2C slave transmit process complete callback.

Parameters
argv I2C handle
Return values
None

Definition at line 2431 of file ald_i2c.c.

2432 {
2433 i2c_handle_t* hperh = (i2c_handle_t*)argv;
2434
2435 CLEAR_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK);
2436
2437 hperh->xfer_count = 0;
2438 hperh->state = I2C_STATE_READY;
2439 hperh->mode = I2C_MODE_NONE;
2440 __UNLOCK(hperh);
2441
2442 if (hperh->error_code != I2C_ERROR_NONE) {
2443 if (hperh->error_callback)
2444 hperh->error_callback(hperh);
2445 }
2446 else {
2447 if (hperh->slave_tx_cplt_cbk)
2448 hperh->slave_tx_cplt_cbk(hperh);
2449 }
2450 }
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
i2c_handle_s::error_callback
void(* error_callback)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:290
i2c_handle_s::slave_tx_cplt_cbk
void(* slave_tx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:286
i2c_handle_s
I2C handle Structure definition.
Definition: ald_i2c.h:269
I2C_MODE_NONE
Definition: ald_i2c.h:115
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ i2c_master_recv_rxne()

static ald_status_t i2c_master_recv_rxne ( i2c_handle_t * hperh )
static

Handle receive not empty for Master Receive mode.

Parameters
hperh Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
Return values
Status,see ald_status_t.

Definition at line 2196 of file ald_i2c.c.

2197 {
2198 if (hperh->xfer_size - hperh->xfer_count > 0) {
2199 (*hperh->p_buff++) = hperh->perh->RXDATA;
2200 hperh->xfer_count++;
2201 }
2202
2203 return OK;
2204 }
OK
Definition: utils.h:55
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270

◆ i2c_master_recv_tc()

static ald_status_t i2c_master_recv_tc ( i2c_handle_t * hperh )
static

Handle receive complete for Master Receive mode.

Parameters
hperh Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
Return values
Status,see ald_status_t.

Definition at line 2169 of file ald_i2c.c.

2170 {
2171 I2C_DISABLE_IT(hperh, I2C_IT_RXTH | I2C_IT_TCR | I2C_IT_TC);
2172
2173 if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK) == RESET)
2174 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
2175
2176 __UNLOCK(hperh);
2177 hperh->state = I2C_STATE_READY;
2178
2179 if (hperh->mode == I2C_MODE_MEM) {
2180 if (hperh->mem_rx_cplt_cbk)
2181 hperh->mem_rx_cplt_cbk(hperh);
2182 }
2183 else {
2184 if (hperh->master_rx_cplt_cbk)
2185 hperh->master_rx_cplt_cbk(hperh);
2186 }
2187
2188 return OK;
2189 }
i2c_handle_s::mem_rx_cplt_cbk
void(* mem_rx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:289
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
I2C_MODE_MEM
Definition: ald_i2c.h:118
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
RESET
Definition: type.h:38
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
I2C_DISABLE_IT
#define I2C_DISABLE_IT(x, y)
Definition: ald_i2c.h:303
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
i2c_handle_s::master_rx_cplt_cbk
void(* master_rx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:285
I2C_IT_TC
Definition: ald_i2c.h:233
I2C_IT_TCR
Definition: ald_i2c.h:234
I2C_IT_RXTH
Definition: ald_i2c.h:232
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ i2c_master_req_read()

static ald_status_t i2c_master_req_read | ( | i2c_handle_t * | hperh,
 |  | uint16_t | dev_addr,
 |  | uint32_t | timeout
 | ) |  |
static

Master sends target device address followed by internal memory address for read request.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
dev_addr | Target device address
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 2298 of file ald_i2c.c.

2299 {
2300 if (hperh->init.addr_mode == I2C_ADDR_7BIT) {
2301 CLEAR_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK);
2302 }
2303 else {
2304 SET_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK);
2305 }
2306
2307 MODIFY_REG(hperh->perh->CON2, I2C_CON2_SADD_MSK, dev_addr << I2C_CON2_SADD_POSS);
2308 SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK);
2309
2310 return OK;
2311 }
OK
Definition: utils.h:55
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
i2c_handle_s::init
i2c_init_t init
Definition: ald_i2c.h:271
i2c_init_t::addr_mode
i2c_addr_t addr_mode
Definition: ald_i2c.h:259
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
I2C_ADDR_7BIT
Definition: ald_i2c.h:75
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270

◆ i2c_master_req_write()

static ald_status_t i2c_master_req_write | ( | i2c_handle_t * | hperh,
 |  | uint16_t | dev_addr,
 |  | uint32_t | timeout
 | ) |  |
static

Master sends target device address followed by internal memory address for write request.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
dev_addr | Target device address
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 2275 of file ald_i2c.c.

2276 {
2277 if (hperh->init.addr_mode == I2C_ADDR_7BIT) {
2278 CLEAR_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK);
2279 }
2280 else {
2281 SET_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK);
2282 }
2283
2284 MODIFY_REG(hperh->perh->CON2, I2C_CON2_SADD_MSK, dev_addr << I2C_CON2_SADD_POSS);
2285 CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK);
2286
2287 return OK;
2288 }
OK
Definition: utils.h:55
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
i2c_handle_s::init
i2c_init_t init
Definition: ald_i2c.h:271
i2c_init_t::addr_mode
i2c_addr_t addr_mode
Definition: ald_i2c.h:259
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
I2C_ADDR_7BIT
Definition: ald_i2c.h:75
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270

◆ i2c_master_send_tc()

static ald_status_t i2c_master_send_tc ( i2c_handle_t * hperh )
static

Handle transmit complete flag for Master Transmit mode.

Parameters
hperh Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
Return values
Status,see ald_status_t.

Definition at line 2124 of file ald_i2c.c.

2125 {
2126 I2C_DISABLE_IT(hperh, I2C_IT_TXTH | I2C_IT_NACK | I2C_IT_TC | I2C_IT_TCR);
2127
2128 if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK) == RESET)
2129 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
2130
2131 __UNLOCK(hperh);
2132 hperh->state = I2C_STATE_READY;
2133
2134 if (hperh->mode == I2C_MODE_MEM) {
2135 if (hperh->mem_tx_cplt_cbk)
2136 hperh->mem_tx_cplt_cbk(hperh);
2137 }
2138 else {
2139 if (hperh->master_tx_cplt_cbk)
2140 hperh->master_tx_cplt_cbk(hperh);
2141 }
2142
2143 return OK;
2144 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
I2C_MODE_MEM
Definition: ald_i2c.h:118
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
i2c_handle_s::mem_tx_cplt_cbk
void(* mem_tx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:288
RESET
Definition: type.h:38
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
I2C_IT_TXTH
Definition: ald_i2c.h:228
I2C_DISABLE_IT
#define I2C_DISABLE_IT(x, y)
Definition: ald_i2c.h:303
I2C_IT_NACK
Definition: ald_i2c.h:236
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
i2c_handle_s::master_tx_cplt_cbk
void(* master_tx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:284
I2C_IT_TC
Definition: ald_i2c.h:233
I2C_IT_TCR
Definition: ald_i2c.h:234
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ i2c_master_send_txe()

static ald_status_t i2c_master_send_txe ( i2c_handle_t * hperh )
static

Handle transmit empty flag for Master Transmit mode.

Parameters
hperh Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
Return values
Status,see ald_status_t.

Definition at line 2153 of file ald_i2c.c.

2154 {
2155 if (hperh->xfer_count != hperh->xfer_size) {
2156 hperh->perh->TXDATA = (*hperh->p_buff++);
2157 hperh->xfer_count++;
2158 }
2159
2160 return OK;
2161 }
OK
Definition: utils.h:55
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270

◆ i2c_req_mem_read()

static ald_status_t i2c_req_mem_read | ( | i2c_handle_t * | hperh,
 |  | uint16_t | dev_addr,
 |  | uint16_t | mem_addr,
 |  | uint16_t | add_size,
 |  | uint32_t | timeout
 | ) |  |
static

Master sends target device address followed by internal memory address for read request.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
dev_addr | Target device address
mem_addr | Internal memory address
add_size | size of internal memory address
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 2356 of file ald_i2c.c.

2357 {
2358 uint32_t tim_count = 0;
2359
2360 if (i2c_master_req_write(hperh, dev_addr, timeout) != OK) {
2361 __UNLOCK(hperh);
2362 return ERROR;
2363 }
2364
2365 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
2366
2367 if (add_size == I2C_MEMADD_SIZE_8BIT) {
2368 hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr);
2369 }
2370 else {
2371 hperh->perh->TXDATA = I2C_MEM_ADD_MSB(mem_addr);
2372
2373 if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) {
2374 if (hperh->error_code == I2C_ERROR_AF) {
2375 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
2376 return ERROR;
2377 }
2378 else {
2379 return TIMEOUT;
2380 }
2381 }
2382
2383 hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr);
2384 }
2385
2386 while (!I2C_GET_FLAG(hperh, I2C_STAT_TXE)) {
2387 tim_count++;
2388
2389 if (tim_count > 0xFFFF)
2390 return TIMEOUT;
2391 }
2392 return OK;
2393 }
I2C_ERROR_AF
Definition: ald_i2c.h:48
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
I2C_STAT_TXE
Definition: ald_i2c.h:205
i2c_wait_txe_to_timeout
static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout)
This function handles I2C Communication timeout for specific usage of TXE flag.
Definition: ald_i2c.c:2652
I2C_MEM_ADD_LSB
#define I2C_MEM_ADD_LSB(__ADDRESS__)
Definition: ald_i2c.h:335
I2C_MEM_ADD_MSB
#define I2C_MEM_ADD_MSB(__ADDRESS__)
Definition: ald_i2c.h:333
i2c_master_req_write
static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout)
Master sends target device address followed by internal memory address for write request.
Definition: ald_i2c.c:2275
I2C_GET_FLAG
#define I2C_GET_FLAG(x, y)
Definition: ald_i2c.h:307
TIMEOUT
Definition: utils.h:58
I2C_MEMADD_SIZE_8BIT
Definition: ald_i2c.h:107
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
ERROR
Definition: utils.h:56
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270

◆ i2c_req_mem_write()

static ald_status_t i2c_req_mem_write | ( | i2c_handle_t * | hperh,
 |  | uint16_t | dev_addr,
 |  | uint16_t | mem_addr,
 |  | uint16_t | add_size,
 |  | uint32_t | timeout
 | ) |  |
static

Master sends target device address followed by internal memory address for write request.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
dev_addr | Target device address
mem_addr | Internal memory address
add_size | size of internal memory address
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 2323 of file ald_i2c.c.

2324 {
2325 i2c_master_req_write(hperh, dev_addr, timeout);
2326 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
2327
2328 if (add_size == I2C_MEMADD_SIZE_8BIT) {
2329 hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr);
2330 }
2331 else {
2332 hperh->perh->TXDATA = I2C_MEM_ADD_MSB(mem_addr);
2333
2334 if (i2c_wait_txe_to_timeout(hperh, timeout) != OK)
2335 return ERROR;
2336
2337 hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr);
2338 }
2339
2340 if (i2c_wait_txe_to_timeout(hperh, timeout) != OK)
2341 return ERROR;
2342
2343 return OK;
2344 }
OK
Definition: utils.h:55
i2c_wait_txe_to_timeout
static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout)
This function handles I2C Communication timeout for specific usage of TXE flag.
Definition: ald_i2c.c:2652
I2C_MEM_ADD_LSB
#define I2C_MEM_ADD_LSB(__ADDRESS__)
Definition: ald_i2c.h:335
I2C_MEM_ADD_MSB
#define I2C_MEM_ADD_MSB(__ADDRESS__)
Definition: ald_i2c.h:333
i2c_master_req_write
static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout)
Master sends target device address followed by internal memory address for write request.
Definition: ald_i2c.c:2275
I2C_MEMADD_SIZE_8BIT
Definition: ald_i2c.h:107
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
ERROR
Definition: utils.h:56
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270

◆ i2c_slave_recv_rxne()

static ald_status_t i2c_slave_recv_rxne ( i2c_handle_t * hperh )
static

Handle RXNE flag for Slave Receive mode.

Parameters
hperh Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
Return values
Status,see ald_status_t.

Definition at line 2228 of file ald_i2c.c.

2229 {
2230 if (hperh->xfer_size > hperh->xfer_count) {
2231 (*hperh->p_buff++) = hperh->perh->RXDATA;
2232 hperh->xfer_count++;
2233 }
2234
2235 return OK;
2236 }
OK
Definition: utils.h:55
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270

◆ i2c_slave_send_txe()

static ald_status_t i2c_slave_send_txe ( i2c_handle_t * hperh )
static

Handle TXE flag for Slave Transmit mode.

Parameters
hperh Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
Return values
Status,see ald_status_t.

Definition at line 2212 of file ald_i2c.c.

2213 {
2214 if (hperh->xfer_size > hperh->xfer_count) {
2215 hperh->perh->TXDATA = (*hperh->p_buff++);
2216 hperh->xfer_count++;
2217 }
2218
2219 return OK;
2220 }
OK
Definition: utils.h:55
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270

◆ i2c_slave_stopf()

static ald_status_t i2c_slave_stopf ( i2c_handle_t * hperh )
static

Handle STOPF flag for Slave mode.

Parameters
hperh Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
Return values
Status,see ald_status_t.

Definition at line 2244 of file ald_i2c.c.

2245 {
2246 I2C_DISABLE_IT(hperh, I2C_IT_ADDR | I2C_IT_NACK | I2C_IT_RXTH | I2C_IT_TXTH | I2C_IT_STOP);
2247
2248 hperh->mode = I2C_MODE_NONE;
2249 hperh->error_code = I2C_ERROR_NONE;
2250 __UNLOCK(hperh);
2251
2252 if (hperh->state == I2C_STATE_BUSY_TX) {
2253 hperh->state = I2C_STATE_READY;
2254 if ((hperh->slave_tx_cplt_cbk) && (hperh->xfer_count != 0))
2255 hperh->slave_tx_cplt_cbk(hperh);
2256 }
2257 else if (hperh->state == I2C_STATE_BUSY_RX) {
2258 hperh->state = I2C_STATE_READY;
2259 if ((hperh->slave_rx_cplt_cbk) && (hperh->xfer_count != 0))
2260 hperh->slave_rx_cplt_cbk(hperh);
2261 }
2262
2263 return OK;
2264 }
I2C_STATE_BUSY_TX
Definition: ald_i2c.h:65
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
I2C_STATE_BUSY_RX
Definition: ald_i2c.h:66
I2C_IT_ADDR
Definition: ald_i2c.h:235
i2c_handle_s::slave_rx_cplt_cbk
void(* slave_rx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:287
i2c_handle_s::slave_tx_cplt_cbk
void(* slave_tx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:286
I2C_IT_TXTH
Definition: ald_i2c.h:228
I2C_DISABLE_IT
#define I2C_DISABLE_IT(x, y)
Definition: ald_i2c.h:303
I2C_IT_NACK
Definition: ald_i2c.h:236
I2C_MODE_NONE
Definition: ald_i2c.h:115
I2C_IT_STOP
Definition: ald_i2c.h:237
I2C_IT_RXTH
Definition: ald_i2c.h:232
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ i2c_wait_flag_change_to_timeout()

static ald_status_t i2c_wait_flag_change_to_timeout | ( | i2c_handle_t * | hperh,
 |  | uint32_t | flag,
 |  | flag_status_t | status,
 |  | uint32_t | timeout
 | ) |  |
static

This function handles I2C Communication timeout.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
flag | specifies the I2C flag to check.
status | The checked flag status (SET or RESET).
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 2597 of file ald_i2c.c.

2598 {
2599 uint32_t tickstart = 0;
2600
2601 tickstart = ald_get_tick();
2602 if (status == RESET) {
2603 while (I2C_GET_FLAG(hperh, flag) == RESET) {
2604 if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) {
2605 hperh->error_code |= I2C_ERROR_TIMEOUT;
2606 return TIMEOUT;
2607 }
2608 }
2609 }
2610 else {
2611 while (I2C_GET_FLAG(hperh, flag) != RESET) {
2612 if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) {
2613 hperh->error_code |= I2C_ERROR_TIMEOUT;
2614 return TIMEOUT;
2615 }
2616 }
2617 }
2618
2619 return OK;
2620 }
OK
Definition: utils.h:55
RESET
Definition: type.h:38
I2C_ERROR_TIMEOUT
Definition: ald_i2c.h:55
I2C_GET_FLAG
#define I2C_GET_FLAG(x, y)
Definition: ald_i2c.h:307
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282

◆ i2c_wait_master_addr_to_timeout()

static ald_status_t i2c_wait_master_addr_to_timeout | ( | i2c_handle_t * | hperh,
 |  | uint32_t | flag,
 |  | uint32_t | timeout
 | ) |  |
static

This function handles I2C Communication timeout for Master addressing phase.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
flag | specifies the I2C flag to check.
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 2630 of file ald_i2c.c.

2631 {
2632 uint32_t tickstart = ald_get_tick();
2633
2634 while (I2C_GET_IT_FLAG(hperh, flag) == RESET) {
2635 if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) {
2636 hperh->error_code = I2C_ERROR_TIMEOUT;
2637
2638 return ERROR;
2639 }
2640 }
2641
2642 return OK;
2643 }
OK
Definition: utils.h:55
RESET
Definition: type.h:38
I2C_GET_IT_FLAG
#define I2C_GET_IT_FLAG(x, y)
Definition: ald_i2c.h:305
I2C_ERROR_TIMEOUT
Definition: ald_i2c.h:55
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
ERROR
Definition: utils.h:56
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282

◆ i2c_wait_rxne_to_timeout()

static ald_status_t i2c_wait_rxne_to_timeout | ( | i2c_handle_t * | hperh,
 |  | uint32_t | timeout
 | ) |  |
static

This function handles I2C Communication timeout for specific usage of RXNE flag.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 2683 of file ald_i2c.c.

2684 {
2685 uint32_t tickstart = ald_get_tick();
2686
2687 while (I2C_GET_FLAG(hperh, I2C_STAT_RXTH) == RESET) {
2688 if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) {
2689 hperh->error_code |= I2C_ERROR_TIMEOUT;
2690 return ERROR;
2691 }
2692 }
2693
2694 return OK;
2695 }
OK
Definition: utils.h:55
I2C_STAT_RXTH
Definition: ald_i2c.h:214
RESET
Definition: type.h:38
I2C_ERROR_TIMEOUT
Definition: ald_i2c.h:55
I2C_GET_FLAG
#define I2C_GET_FLAG(x, y)
Definition: ald_i2c.h:307
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
ERROR
Definition: utils.h:56
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282

◆ i2c_wait_txe_to_timeout()

static ald_status_t i2c_wait_txe_to_timeout | ( | i2c_handle_t * | hperh,
 |  | uint32_t | timeout
 | ) |  |
static

This function handles I2C Communication timeout for specific usage of TXE flag.

Parameters
hperh | Pointer to a i2c_handle_t structure that contains the configuration information for the specified I2C.
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 2652 of file ald_i2c.c.

2653 {
2654 uint32_t tickstart = ald_get_tick();
2655
2656 while (I2C_GET_FLAG(hperh, I2C_STAT_THTH) == RESET) {
2657 if (I2C_GET_IT_FLAG(hperh, I2C_IT_ARLO)) {
2658 hperh->error_code |= I2C_ERROR_ARLO;
2659 return ERROR;
2660 }
2661
2662 if (I2C_GET_IT_FLAG(hperh, I2C_IT_NACK) == SET) {
2663 hperh->error_code |= I2C_ERROR_AF;
2664 return ERROR;
2665 }
2666
2667 if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) {
2668 hperh->error_code |= I2C_ERROR_TIMEOUT;
2669 return ERROR;
2670 }
2671 }
2672
2673 return OK;
2674 }
I2C_ERROR_AF
Definition: ald_i2c.h:48
OK
Definition: utils.h:55
SET
Definition: type.h:39
RESET
Definition: type.h:38
I2C_GET_IT_FLAG
#define I2C_GET_IT_FLAG(x, y)
Definition: ald_i2c.h:305
I2C_ERROR_TIMEOUT
Definition: ald_i2c.h:55
I2C_STAT_THTH
Definition: ald_i2c.h:209
I2C_ERROR_ARLO
Definition: ald_i2c.h:46
I2C_IT_ARLO
Definition: ald_i2c.h:239
I2C_GET_FLAG
#define I2C_GET_FLAG(x, y)
Definition: ald_i2c.h:307
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
I2C_IT_NACK
Definition: ald_i2c.h:236
ERROR
Definition: utils.h:56
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282


ALD User Manual: I2C Public Types

Data Structures | Typedefs | Enumerations
I2C Public Types
EASTSOFT ES32F3xx ALD » I2C
Collaboration diagram for I2C Public Types:

Data Structures

struct | i2c_init_t
I2C Configuration Structure definition. More...
struct | i2c_handle_s
I2C handle Structure definition. More...

Typedefs

typedef struct i2c_handle_s i2c_handle_t
I2C handle Structure definition. More...

Enumerations

enum i2c_error_t {
I2C_ERROR_NONE = 0x0U, I2C_ERROR_BERR = 0x1U, I2C_ERROR_ARLO = 0x2U, I2C_ERROR_RUD = 0x4U,
I2C_ERROR_AF = 0x8U, I2C_ERROR_ROV = 0x10U, I2C_ERROR_RF = 0x20U, I2C_ERROR_TUD = 0x40U,
I2C_ERROR_TOV = 0x80U, I2C_ERROR_TE = 0x100U, I2C_ERROR_DMA = 0x200U, I2C_ERROR_TIMEOUT = 0x400U
}
I2C Error Code. More...
enum i2c_state_t {
I2C_STATE_RESET = 0x0U, I2C_STATE_READY = 0x20U, I2C_STATE_BUSY = 0x24U, I2C_STATE_BUSY_TX = 0x21U,
I2C_STATE_BUSY_RX = 0x22U, I2C_STATE_TIMEOUT = 0xA0U, I2C_STATE_ERROR = 0xE0U
}
I2C state structure definition. More...
enum | i2c_addr_t { I2C_ADDR_7BIT = 0x0U, I2C_ADDR_10BIT = 0x1U }
I2C Addressing Mode. More...
enum | i2c_dual_addr_t { I2C_DUALADDR_DISABLE = 0x0U, I2C_DUALADDR_ENABLE = 0x1U }
I2C Dual Addressing Mode. More...
enum | i2c_general_addr_t { I2C_GENERALCALL_DISABLE = 0x0U, I2C_GENERALCALL_ENABLE = 0x1U }
I2C General Call Addressing mode. More...
enum | i2c_nostretch_t { I2C_NOSTRETCH_DISABLE = 0x0U, I2C_NOSTRETCH_ENABLE = 0x1U }
I2C Nostretch Mode. More...
enum | i2c_addr_size_t { I2C_MEMADD_SIZE_8BIT = 0x8U, I2C_MEMADD_SIZE_16BIT = 0x10U }
I2C Memory Address Size. More...
enum | i2c_mode_t { I2C_MODE_NONE = 0x0U, I2C_MODE_MASTER = 0x10U, I2C_MODE_SLAVE = 0x20U, I2C_MODE_MEM = 0x40U }
I2C mode structure definition. More...
enum | i2c_clock_t { I2C_STANDARD_MODE_MAX_CLK = 100000U, I2C_FAST_MODE_MAX_CLK = 400000U, I2C_EXTREME_FAST_MODE_MAX_CLK = 1000000U }
I2C Clock. More...
enum | i2c_oar2_t { I2C_OAR2_ENDUAL = (1U << 0), I2C_OAR2_ADD2 = (1U << 1) }
I2C OAR2 Register. More...
enum i2c_con1_t {
I2C_CON1_PE = (1U << 0), I2C_CON1_TXDMA = (1U << 14), I2C_CON1_RXDMA = (1U << 15), I2C_CON1_SBC = (1U << 16),
I2C_CON1_NOSTRETCH = (1U << 17), I2C_CON1_GCEN = (1U << 19), I2C_CON1_SMBHEN = (1U << 20), I2C_CON1_SMBDEN = (1U << 21),
I2C_CON1_ALERTEN = (1U << 22), I2C_CON1_PECEN = (1U << 23)
}
I2C CON1 Register. More...
enum i2c_con2_t {
I2C_CON2_RD_WRN = (1U << 10), I2C_CON2_ADD10 = (1U << 11), I2C_CON2_HEAD10R = (1U << 12), I2C_CON2_START = (1U << 13),
I2C_CON2_STOP = (1U << 14), I2C_CON2_NACK = (1U << 15), I2C_CON2_RELOAD = (1U << 24), I2C_CON2_AUTOEND = (1U << 25),
I2C_CON2_PECBYTE = (1U << 26), I2C_CON2_HOLDACK = (1U << 28)
}
I2C CON2 Register. More...
enum | i2c_addr1_t { I2C_OA1MODE = (1U << 10), I2C_OA1EN = (1U << 15) }
I2C ADDR1 Register. More...
enum | i2c_addr2_t { I2C_OA2EN = (1U << 15) }
I2C ADDR2 Register. More...
enum | i2c_timoutr_t { I2C_TIMEOUTR_TIDLE = (1U << 12), I2C_TIMEOUTR_TIMEOUTEN = (1U << 15) }
I2C TIMEOUTR Register. More...
enum | i2c_module_t { I2C_MODULE_MASTER = (1U << 0), I2C_MODULE_SLAVE = (1U << 1) }
I2C peripherals module. More...
enum i2c_stat_t {
I2C_STAT_TXE = (1U << 0), I2C_STAT_TXF = (1U << 1), I2C_STAT_TXOV = (1U << 2), I2C_STAT_TXUD = (1U << 3),
I2C_STAT_THTH = (1U << 4), I2C_STAT_RXE = (1U << 5), I2C_STAT_RXF = (1U << 6), I2C_STAT_RXOV = (1U << 7),
I2C_STAT_RXUD = (1U << 8), I2C_STAT_RXTH = (1U << 9), I2C_STAT_TC = (1U << 10), I2C_STAT_TCR = (1U << 11),
I2C_STAT_BUSY = (1U << 15), I2C_STAT_DIR = (1U << 16)
}
I2C STAT Register. More...
enum i2c_interrupt_t {
I2C_IT_TXE = (1U << 0), I2C_IT_TXOV = (1U << 2), I2C_IT_TXUD = (1U << 3), I2C_IT_TXTH = (1U << 4),
I2C_IT_RXF = (1U << 6), I2C_IT_RXOV = (1U << 7), I2C_IT_RXUD = (1U << 8), I2C_IT_RXTH = (1U << 9),
I2C_IT_TC = (1U << 10), I2C_IT_TCR = (1U << 11), I2C_IT_ADDR = (1U << 12), I2C_IT_NACK = (1U << 13),
I2C_IT_STOP = (1U << 14), I2C_IT_BERR = (1U << 16), I2C_IT_ARLO = (1U << 17), I2C_IT_PECE = (1U << 18),
I2C_IT_TOUT = (1U << 19), I2C_IT_ALERT = (1U << 20)
}
Interrupt Configuration Definition. More...
enum | i2c_trise_t { I2C_TRISE_TRISE = 0x3FU }
I2C TRISE Register. More...

Detailed Description

Typedef Documentation

◆ i2c_handle_t

typedef struct i2c_handle_s i2c_handle_t

I2C handle Structure definition.

Enumeration Type Documentation

◆ i2c_addr1_t

enum i2c_addr1_t

I2C ADDR1 Register.

Enumerator
I2C_OA1MODE | Addr1 bits choose BIT
I2C_OA1EN | Addr1 enable BIT

Definition at line 173 of file ald_i2c.h.

173 {
174 I2C_OA1MODE = (1U << 10),
175 I2C_OA1EN = (1U << 15),
176 } i2c_addr1_t;
I2C_OA1MODE
Definition: ald_i2c.h:174
I2C_OA1EN
Definition: ald_i2c.h:175
i2c_addr1_t
i2c_addr1_t
I2C ADDR1 Register.
Definition: ald_i2c.h:173

◆ i2c_addr2_t

enum i2c_addr2_t

I2C ADDR2 Register.

Enumerator
I2C_OA2EN

Addr2 enable BIT

Definition at line 181 of file ald_i2c.h.

181 {
182 I2C_OA2EN = (1U << 15),
183 } i2c_addr2_t;
I2C_OA2EN
Definition: ald_i2c.h:182
i2c_addr2_t
i2c_addr2_t
I2C ADDR2 Register.
Definition: ald_i2c.h:181

◆ i2c_addr_size_t

enum i2c_addr_size_t

I2C Memory Address Size.

Enumerator
I2C_MEMADD_SIZE_8BIT | 8 bit memory address size
I2C_MEMADD_SIZE_16BIT | 10 bit memory address size

Definition at line 106 of file ald_i2c.h.

106 {
107 I2C_MEMADD_SIZE_8BIT = 0x8U,
108 I2C_MEMADD_SIZE_16BIT = 0x10U,
109 } i2c_addr_size_t;
i2c_addr_size_t
i2c_addr_size_t
I2C Memory Address Size.
Definition: ald_i2c.h:106
I2C_MEMADD_SIZE_8BIT
Definition: ald_i2c.h:107
I2C_MEMADD_SIZE_16BIT
Definition: ald_i2c.h:108

◆ i2c_addr_t

enum i2c_addr_t

I2C Addressing Mode.

Enumerator
I2C_ADDR_7BIT | 7 bit address
I2C_ADDR_10BIT | 10 bit address

Definition at line 74 of file ald_i2c.h.

74 {
75 I2C_ADDR_7BIT = 0x0U,
76 I2C_ADDR_10BIT = 0x1U,
77 } i2c_addr_t;
i2c_addr_t
i2c_addr_t
I2C Addressing Mode.
Definition: ald_i2c.h:74
I2C_ADDR_10BIT
Definition: ald_i2c.h:76
I2C_ADDR_7BIT
Definition: ald_i2c.h:75

◆ i2c_clock_t

enum i2c_clock_t

I2C Clock.

Enumerator
I2C_STANDARD_MODE_MAX_CLK | Standard mode clock
I2C_FAST_MODE_MAX_CLK | Fast mode clock
I2C_EXTREME_FAST_MODE_MAX_CLK | Extreme mode clock

Definition at line 124 of file ald_i2c.h.

124 {
125 I2C_STANDARD_MODE_MAX_CLK = 100000U,
126 I2C_FAST_MODE_MAX_CLK = 400000U,
127 I2C_EXTREME_FAST_MODE_MAX_CLK = 1000000U,
128 } i2c_clock_t;
I2C_FAST_MODE_MAX_CLK
Definition: ald_i2c.h:126
I2C_EXTREME_FAST_MODE_MAX_CLK
Definition: ald_i2c.h:127
I2C_STANDARD_MODE_MAX_CLK
Definition: ald_i2c.h:125
i2c_clock_t
i2c_clock_t
I2C Clock.
Definition: ald_i2c.h:124

◆ i2c_con1_t

enum i2c_con1_t

I2C CON1 Register.

Enumerator
I2C_CON1_PE | Peripheral enable BIT
I2C_CON1_TXDMA | Transmit DMA BIT
I2C_CON1_RXDMA | Receive DMA BIT
I2C_CON1_SBC | Receive DMA BIT
I2C_CON1_NOSTRETCH | Slave bytes control BIT
I2C_CON1_GCEN | General call BIT
I2C_CON1_SMBHEN | SMBus slave device enable BIT
I2C_CON1_SMBDEN | SMBus master device enable BIT
I2C_CON1_ALERTEN | SMBus alert device enable BIT
I2C_CON1_PECEN | PEC enable BIT

Definition at line 141 of file ald_i2c.h.

141 {
142 I2C_CON1_PE = (1U << 0),
143 I2C_CON1_TXDMA = (1U << 14),
144 I2C_CON1_RXDMA = (1U << 15),
145 I2C_CON1_SBC = (1U << 16),
146 I2C_CON1_NOSTRETCH = (1U << 17),
147 I2C_CON1_GCEN = (1U << 19),
148 I2C_CON1_SMBHEN = (1U << 20),
149 I2C_CON1_SMBDEN = (1U << 21),
150 I2C_CON1_ALERTEN = (1U << 22),
151 I2C_CON1_PECEN = (1U << 23),
152 } i2c_con1_t;
I2C_CON1_PECEN
Definition: ald_i2c.h:151
I2C_CON1_SMBHEN
Definition: ald_i2c.h:148
I2C_CON1_TXDMA
Definition: ald_i2c.h:143
I2C_CON1_PE
Definition: ald_i2c.h:142
I2C_CON1_RXDMA
Definition: ald_i2c.h:144
I2C_CON1_NOSTRETCH
Definition: ald_i2c.h:146
I2C_CON1_SMBDEN
Definition: ald_i2c.h:149
i2c_con1_t
i2c_con1_t
I2C CON1 Register.
Definition: ald_i2c.h:141
I2C_CON1_GCEN
Definition: ald_i2c.h:147
I2C_CON1_SBC
Definition: ald_i2c.h:145
I2C_CON1_ALERTEN
Definition: ald_i2c.h:150

◆ i2c_con2_t

enum i2c_con2_t

I2C CON2 Register.

Enumerator
I2C_CON2_RD_WRN | Master R/W control BIT
I2C_CON2_ADD10 | 10bit address control BIT
I2C_CON2_HEAD10R | 10bit address master Receive control BIT
I2C_CON2_START | Master start singal control BIT
I2C_CON2_STOP | Master stop singal control BIT
I2C_CON2_NACK | Master Nack control BIT
I2C_CON2_RELOAD | Master communication reload control BIT
I2C_CON2_AUTOEND | Master Autoend control BIT
I2C_CON2_PECBYTE | PEC control BIT
I2C_CON2_HOLDACK | Hold ack control BIT

Definition at line 157 of file ald_i2c.h.

157 {
158 I2C_CON2_RD_WRN = (1U << 10),
159 I2C_CON2_ADD10 = (1U << 11),
160 I2C_CON2_HEAD10R = (1U << 12),
161 I2C_CON2_START = (1U << 13),
162 I2C_CON2_STOP = (1U << 14),
163 I2C_CON2_NACK = (1U << 15),
164 I2C_CON2_RELOAD = (1U << 24),
165 I2C_CON2_AUTOEND = (1U << 25),
166 I2C_CON2_PECBYTE = (1U << 26),
167 I2C_CON2_HOLDACK = (1U << 28),
168 } i2c_con2_t;
i2c_con2_t
i2c_con2_t
I2C CON2 Register.
Definition: ald_i2c.h:157
I2C_CON2_PECBYTE
Definition: ald_i2c.h:166
I2C_CON2_AUTOEND
Definition: ald_i2c.h:165
I2C_CON2_STOP
Definition: ald_i2c.h:162
I2C_CON2_NACK
Definition: ald_i2c.h:163
I2C_CON2_RELOAD
Definition: ald_i2c.h:164
I2C_CON2_START
Definition: ald_i2c.h:161
I2C_CON2_HOLDACK
Definition: ald_i2c.h:167
I2C_CON2_ADD10
Definition: ald_i2c.h:159
I2C_CON2_RD_WRN
Definition: ald_i2c.h:158
I2C_CON2_HEAD10R
Definition: ald_i2c.h:160

◆ i2c_dual_addr_t

enum i2c_dual_addr_t

I2C Dual Addressing Mode.

Enumerator
I2C_DUALADDR_DISABLE | dual address is disable
I2C_DUALADDR_ENABLE | dual address is enable

Definition at line 82 of file ald_i2c.h.

82 {
83 I2C_DUALADDR_DISABLE = 0x0U,
84 I2C_DUALADDR_ENABLE = 0x1U,
85 } i2c_dual_addr_t;
i2c_dual_addr_t
i2c_dual_addr_t
I2C Dual Addressing Mode.
Definition: ald_i2c.h:82
I2C_DUALADDR_DISABLE
Definition: ald_i2c.h:83
I2C_DUALADDR_ENABLE
Definition: ald_i2c.h:84

◆ i2c_error_t

enum i2c_error_t

I2C Error Code.

Enumerator
I2C_ERROR_NONE | No error
I2C_ERROR_BERR | Berr error
I2C_ERROR_ARLO | Arlo error
I2C_ERROR_RUD | Rx underflow error
I2C_ERROR_AF | Af error
I2C_ERROR_ROV | Rx overflow error
I2C_ERROR_RF | Rx full error
I2C_ERROR_TUD | Tx underflow error
I2C_ERROR_TOV | Tx overflow error
I2C_ERROR_TE | Tx empty error
I2C_ERROR_DMA | Dma error
I2C_ERROR_TIMEOUT | Timeout error

Definition at line 43 of file ald_i2c.h.

43 {
44 I2C_ERROR_NONE = 0x0U,
45 I2C_ERROR_BERR = 0x1U,
46 I2C_ERROR_ARLO = 0x2U,
47 I2C_ERROR_RUD = 0x4U,
48 I2C_ERROR_AF = 0x8U,
49 I2C_ERROR_ROV = 0x10U,
50 I2C_ERROR_RF = 0x20U,
51 I2C_ERROR_TUD = 0x40U,
52 I2C_ERROR_TOV = 0x80U,
53 I2C_ERROR_TE = 0x100U,
54 I2C_ERROR_DMA = 0x200U,
55 I2C_ERROR_TIMEOUT = 0x400U,
56 } i2c_error_t;
I2C_ERROR_TE
Definition: ald_i2c.h:53
I2C_ERROR_AF
Definition: ald_i2c.h:48
I2C_ERROR_RF
Definition: ald_i2c.h:50
I2C_ERROR_RUD
Definition: ald_i2c.h:47
I2C_ERROR_TUD
Definition: ald_i2c.h:51
I2C_ERROR_NONE
Definition: ald_i2c.h:44
I2C_ERROR_BERR
Definition: ald_i2c.h:45
I2C_ERROR_TIMEOUT
Definition: ald_i2c.h:55
I2C_ERROR_ARLO
Definition: ald_i2c.h:46
I2C_ERROR_TOV
Definition: ald_i2c.h:52
I2C_ERROR_ROV
Definition: ald_i2c.h:49
I2C_ERROR_DMA
Definition: ald_i2c.h:54
i2c_error_t
i2c_error_t
I2C Error Code.
Definition: ald_i2c.h:43

◆ i2c_general_addr_t

enum i2c_general_addr_t

I2C General Call Addressing mode.

Enumerator
I2C_GENERALCALL_DISABLE | general call address is disable
I2C_GENERALCALL_ENABLE | general call address is enable

Definition at line 90 of file ald_i2c.h.

90 {
91 I2C_GENERALCALL_DISABLE = 0x0U,
92 I2C_GENERALCALL_ENABLE = 0x1U,
93 } i2c_general_addr_t;
I2C_GENERALCALL_ENABLE
Definition: ald_i2c.h:92
I2C_GENERALCALL_DISABLE
Definition: ald_i2c.h:91
i2c_general_addr_t
i2c_general_addr_t
I2C General Call Addressing mode.
Definition: ald_i2c.h:90

◆ i2c_interrupt_t

enum i2c_interrupt_t

Interrupt Configuration Definition.

Enumerator
I2C_IT_TXE | Transmit FIFO empty interrupt
I2C_IT_TXOV | Transmit FIFO overrun interrupt
I2C_IT_TXUD | Transmit FIFO underrun interrupt
I2C_IT_TXTH | Transmit FIFO threshold interrupt
I2C_IT_RXF | Receive FIFO full interrupt
I2C_IT_RXOV | Receive FIFO overrun interrupt
I2C_IT_RXUD | Receive FIFO underrun interrupt
I2C_IT_RXTH | Receive FIFO threshold interrupt
I2C_IT_TC | Transmit completed interrupt
I2C_IT_TCR | Transmit and reload completed interrupt
I2C_IT_ADDR | Address matching interrupt
I2C_IT_NACK | NACK interrupt
I2C_IT_STOP | Stop detection interrupt
I2C_IT_BERR | Bus error interrupt
I2C_IT_ARLO | Arbitration loss interrupt
I2C_IT_PECE | PEC error interrupt
I2C_IT_TOUT | Timeout interrupt
I2C_IT_ALERT | SMBus Alert interrupt

Definition at line 224 of file ald_i2c.h.

224 {
225 I2C_IT_TXE = (1U << 0),
226 I2C_IT_TXOV = (1U << 2),
227 I2C_IT_TXUD = (1U << 3),
228 I2C_IT_TXTH = (1U << 4),
229 I2C_IT_RXF = (1U << 6),
230 I2C_IT_RXOV = (1U << 7),
231 I2C_IT_RXUD = (1U << 8),
232 I2C_IT_RXTH = (1U << 9),
233 I2C_IT_TC = (1U << 10),
234 I2C_IT_TCR = (1U << 11),
235 I2C_IT_ADDR = (1U << 12),
236 I2C_IT_NACK = (1U << 13),
237 I2C_IT_STOP = (1U << 14),
238 I2C_IT_BERR = (1U << 16),
239 I2C_IT_ARLO = (1U << 17),
240 I2C_IT_PECE = (1U << 18),
241 I2C_IT_TOUT = (1U << 19),
242 I2C_IT_ALERT = (1U << 20),
243 } i2c_interrupt_t;
I2C_IT_TXE
Definition: ald_i2c.h:225
I2C_IT_RXF
Definition: ald_i2c.h:229
i2c_interrupt_t
i2c_interrupt_t
Interrupt Configuration Definition.
Definition: ald_i2c.h:224
I2C_IT_ALERT
Definition: ald_i2c.h:242
I2C_IT_BERR
Definition: ald_i2c.h:238
I2C_IT_ADDR
Definition: ald_i2c.h:235
I2C_IT_ARLO
Definition: ald_i2c.h:239
I2C_IT_TOUT
Definition: ald_i2c.h:241
I2C_IT_TXTH
Definition: ald_i2c.h:228
I2C_IT_NACK
Definition: ald_i2c.h:236
I2C_IT_RXUD
Definition: ald_i2c.h:231
I2C_IT_TXUD
Definition: ald_i2c.h:227
I2C_IT_TXOV
Definition: ald_i2c.h:226
I2C_IT_STOP
Definition: ald_i2c.h:237
I2C_IT_TC
Definition: ald_i2c.h:233
I2C_IT_TCR
Definition: ald_i2c.h:234
I2C_IT_RXTH
Definition: ald_i2c.h:232
I2C_IT_PECE
Definition: ald_i2c.h:240
I2C_IT_RXOV
Definition: ald_i2c.h:230

◆ i2c_mode_t

enum i2c_mode_t

I2C mode structure definition.

Enumerator
I2C_MODE_NONE | No I2C communication on going
I2C_MODE_MASTER | I2C communication is in Master mode
I2C_MODE_SLAVE | I2C communication is in Slave mode
I2C_MODE_MEM | I2C communication is in Memory mode

Definition at line 114 of file ald_i2c.h.

114 {
115 I2C_MODE_NONE = 0x0U,
116 I2C_MODE_MASTER = 0x10U,
117 I2C_MODE_SLAVE = 0x20U,
118 I2C_MODE_MEM = 0x40U,
119 } i2c_mode_t;
I2C_MODE_MEM
Definition: ald_i2c.h:118
I2C_MODE_SLAVE
Definition: ald_i2c.h:117
I2C_MODE_MASTER
Definition: ald_i2c.h:116
i2c_mode_t
i2c_mode_t
I2C mode structure definition.
Definition: ald_i2c.h:114
I2C_MODE_NONE
Definition: ald_i2c.h:115

◆ i2c_module_t

enum i2c_module_t

I2C peripherals module.

Enumerator
I2C_MODULE_MASTER | Master module
I2C_MODULE_SLAVE | Slave module

Definition at line 196 of file ald_i2c.h.

196 {
197 I2C_MODULE_MASTER = (1U << 0),
198 I2C_MODULE_SLAVE = (1U << 1)
199 } i2c_module_t;
I2C_MODULE_MASTER
Definition: ald_i2c.h:197
i2c_module_t
i2c_module_t
I2C peripherals module.
Definition: ald_i2c.h:196
I2C_MODULE_SLAVE
Definition: ald_i2c.h:198

◆ i2c_nostretch_t

enum i2c_nostretch_t

I2C Nostretch Mode.

Enumerator
I2C_NOSTRETCH_DISABLE | Nostretch disable
I2C_NOSTRETCH_ENABLE | Nostretch enable

Definition at line 98 of file ald_i2c.h.

98 {
99 I2C_NOSTRETCH_DISABLE = 0x0U,
100 I2C_NOSTRETCH_ENABLE = 0x1U,
101 } i2c_nostretch_t;
I2C_NOSTRETCH_ENABLE
Definition: ald_i2c.h:100
I2C_NOSTRETCH_DISABLE
Definition: ald_i2c.h:99
i2c_nostretch_t
i2c_nostretch_t
I2C Nostretch Mode.
Definition: ald_i2c.h:98

◆ i2c_oar2_t

enum i2c_oar2_t

I2C OAR2 Register.

Enumerator
I2C_OAR2_ENDUAL | ENDUAL BIT
I2C_OAR2_ADD2 | ADD2 BIT

Definition at line 133 of file ald_i2c.h.

133 {
134 I2C_OAR2_ENDUAL = (1U << 0),
135 I2C_OAR2_ADD2 = (1U << 1)
136 } i2c_oar2_t;
i2c_oar2_t
i2c_oar2_t
I2C OAR2 Register.
Definition: ald_i2c.h:133
I2C_OAR2_ADD2
Definition: ald_i2c.h:135
I2C_OAR2_ENDUAL
Definition: ald_i2c.h:134

◆ i2c_stat_t

enum i2c_stat_t

I2C STAT Register.

Enumerator
I2C_STAT_TXE | Transmit FIFO empty flag
I2C_STAT_TXF | Transmit FIFO full flag
I2C_STAT_TXOV | Transmit FIFO overrun flag
I2C_STAT_TXUD | Transmit FIFO underrun flag
I2C_STAT_THTH | Transmit FIFO threshold flag
I2C_STAT_RXE | Receive FIFO empty flag
I2C_STAT_RXF | Receive FIFO full flag
I2C_STAT_RXOV | Receive FIFO overrun flag
I2C_STAT_RXUD | Receive FIFO underrun flag
I2C_STAT_RXTH | Receive FIFO threshold flag
I2C_STAT_TC | Transmit completed flag
I2C_STAT_TCR | Transmit and reload completed flag
I2C_STAT_BUSY | Bus status busy flag
I2C_STAT_DIR | Slave R/W flag

Definition at line 204 of file ald_i2c.h.

204 {
205 I2C_STAT_TXE = (1U << 0),
206 I2C_STAT_TXF = (1U << 1),
207 I2C_STAT_TXOV = (1U << 2),
208 I2C_STAT_TXUD = (1U << 3),
209 I2C_STAT_THTH = (1U << 4),
210 I2C_STAT_RXE = (1U << 5),
211 I2C_STAT_RXF = (1U << 6),
212 I2C_STAT_RXOV = (1U << 7),
213 I2C_STAT_RXUD = (1U << 8),
214 I2C_STAT_RXTH = (1U << 9),
215 I2C_STAT_TC = (1U << 10),
216 I2C_STAT_TCR = (1U << 11),
217 I2C_STAT_BUSY = (1U << 15),
218 I2C_STAT_DIR = (1U << 16),
219 } i2c_stat_t;
I2C_STAT_TXF
Definition: ald_i2c.h:206
I2C_STAT_RXF
Definition: ald_i2c.h:211
I2C_STAT_TXE
Definition: ald_i2c.h:205
I2C_STAT_RXE
Definition: ald_i2c.h:210
I2C_STAT_RXTH
Definition: ald_i2c.h:214
i2c_stat_t
i2c_stat_t
I2C STAT Register.
Definition: ald_i2c.h:204
I2C_STAT_BUSY
Definition: ald_i2c.h:217
I2C_STAT_TCR
Definition: ald_i2c.h:216
I2C_STAT_TC
Definition: ald_i2c.h:215
I2C_STAT_THTH
Definition: ald_i2c.h:209
I2C_STAT_TXUD
Definition: ald_i2c.h:208
I2C_STAT_RXOV
Definition: ald_i2c.h:212
I2C_STAT_TXOV
Definition: ald_i2c.h:207
I2C_STAT_RXUD
Definition: ald_i2c.h:213
I2C_STAT_DIR
Definition: ald_i2c.h:218

◆ i2c_state_t

enum i2c_state_t

I2C state structure definition.

Enumerator
I2C_STATE_RESET | Peripheral is not yet Initialized
I2C_STATE_READY | Peripheral Initialized and ready for use
I2C_STATE_BUSY | An internal process is ongoing
I2C_STATE_BUSY_TX | Data Transmission process is ongoing
I2C_STATE_BUSY_RX | Data Reception process is ongoing
I2C_STATE_TIMEOUT | timeout state
I2C_STATE_ERROR | Error

Definition at line 61 of file ald_i2c.h.

61 {
62 I2C_STATE_RESET = 0x0U,
63 I2C_STATE_READY = 0x20U,
64 I2C_STATE_BUSY = 0x24U,
65 I2C_STATE_BUSY_TX = 0x21U,
66 I2C_STATE_BUSY_RX = 0x22U,
67 I2C_STATE_TIMEOUT = 0xA0U,
68 I2C_STATE_ERROR = 0xE0U,
69 } i2c_state_t;
I2C_STATE_BUSY_TX
Definition: ald_i2c.h:65
I2C_STATE_BUSY
Definition: ald_i2c.h:64
I2C_STATE_TIMEOUT
Definition: ald_i2c.h:67
I2C_STATE_ERROR
Definition: ald_i2c.h:68
I2C_STATE_RESET
Definition: ald_i2c.h:62
I2C_STATE_BUSY_RX
Definition: ald_i2c.h:66
i2c_state_t
i2c_state_t
I2C state structure definition.
Definition: ald_i2c.h:61
I2C_STATE_READY
Definition: ald_i2c.h:63

◆ i2c_timoutr_t

enum i2c_timoutr_t

I2C TIMEOUTR Register.

Enumerator
I2C_TIMEOUTR_TIDLE | SCL idle check enable BIT
I2C_TIMEOUTR_TIMEOUTEN | Timeout enable BIT

Definition at line 188 of file ald_i2c.h.

188 {
189 I2C_TIMEOUTR_TIDLE = (1U << 12),
190 I2C_TIMEOUTR_TIMEOUTEN = (1U << 15),
191 } i2c_timoutr_t;
i2c_timoutr_t
i2c_timoutr_t
I2C TIMEOUTR Register.
Definition: ald_i2c.h:188
I2C_TIMEOUTR_TIDLE
Definition: ald_i2c.h:189
I2C_TIMEOUTR_TIMEOUTEN
Definition: ald_i2c.h:190

◆ i2c_trise_t

enum i2c_trise_t

I2C TRISE Register.

Enumerator
I2C_TRISE_TRISE

TRISE BITS

Definition at line 248 of file ald_i2c.h.

248 {
249 I2C_TRISE_TRISE = 0x3FU,
250 } i2c_trise_t;
I2C_TRISE_TRISE
Definition: ald_i2c.h:249
i2c_trise_t
i2c_trise_t
I2C TRISE Register.
Definition: ald_i2c.h:248


ALD User Manual: i2c_init_t Struct Reference

Data Fields
i2c_init_t Struct Reference
EASTSOFT ES32F3xx ALD » I2C » I2C Public Types

I2C Configuration Structure definition. More...

#include <ald_i2c.h>

Data Fields

i2c_module_t module
uint32_t | clk_speed
uint32_t | own_addr1
i2c_addr_t addr_mode
i2c_dual_addr_t dual_addr
uint32_t | own_addr2
i2c_general_addr_t general_call
i2c_nostretch_t no_stretch

Detailed Description

I2C Configuration Structure definition.

Definition at line 255 of file ald_i2c.h.

Field Documentation

◆ addr_mode

i2c_addr_t addr_mode

Specifies addressing mode

Definition at line 259 of file ald_i2c.h.

◆ clk_speed

uint32_t clk_speed

Specifies the clock frequency

Definition at line 257 of file ald_i2c.h.

◆ dual_addr

i2c_dual_addr_t dual_addr

Specifies if dual addressing mode is selected

Definition at line 260 of file ald_i2c.h.

◆ general_call

i2c_general_addr_t general_call

Specifies if general call mode is selected

Definition at line 262 of file ald_i2c.h.

◆ module

i2c_module_t module

Specifies the communication module

Definition at line 256 of file ald_i2c.h.

◆ no_stretch

i2c_nostretch_t no_stretch

Specifies if nostretch mode is selected

Definition at line 263 of file ald_i2c.h.

◆ own_addr1

uint32_t own_addr1

Specifies the first device own address

Definition at line 258 of file ald_i2c.h.

◆ own_addr2

uint32_t own_addr2

Specifies the second device own address

Definition at line 261 of file ald_i2c.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_i2c.h


ALD User Manual: i2c_handle_s Struct Reference

Data Fields
i2c_handle_s Struct Reference
EASTSOFT ES32F3xx ALD » I2C » I2C Public Types

I2C handle Structure definition. More...

#include <ald_i2c.h>

Collaboration diagram for i2c_handle_s:
[legend]

Data Fields

I2C_TypeDef * | perh
i2c_init_t init
uint8_t * | p_buff
uint16_t | xfer_size
__IO uint16_t | xfer_count
dma_handle_t hdmatx
dma_handle_t hdmarx
lock_state_t lock
__IO i2c_state_t | state
__IO i2c_mode_t | mode
__IO uint32_t | error_code
void(* | master_tx_cplt_cbk )(struct i2c_handle_s *arg)
void(* | master_rx_cplt_cbk )(struct i2c_handle_s *arg)
void(* | slave_tx_cplt_cbk )(struct i2c_handle_s *arg)
void(* | slave_rx_cplt_cbk )(struct i2c_handle_s *arg)
void(* | mem_tx_cplt_cbk )(struct i2c_handle_s *arg)
void(* | mem_rx_cplt_cbk )(struct i2c_handle_s *arg)
void(* | error_callback )(struct i2c_handle_s *arg)

Detailed Description

I2C handle Structure definition.

Definition at line 269 of file ald_i2c.h.

Field Documentation

◆ error_callback

void(* error_callback) (struct i2c_handle_s *arg)

Error callback

Definition at line 290 of file ald_i2c.h.

◆ error_code

__IO uint32_t error_code

I2C Error code

Definition at line 282 of file ald_i2c.h.

◆ hdmarx

dma_handle_t hdmarx

I2C Rx DMA handle parameters

Definition at line 277 of file ald_i2c.h.

◆ hdmatx

dma_handle_t hdmatx

I2C Tx DMA handle parameters

Definition at line 276 of file ald_i2c.h.

◆ init

i2c_init_t init

I2C communication parameters

Definition at line 271 of file ald_i2c.h.

◆ lock

lock_state_t lock

I2C locking object

Definition at line 279 of file ald_i2c.h.

◆ master_rx_cplt_cbk

void(* master_rx_cplt_cbk) (struct i2c_handle_s *arg)

Master Rx completed callback

Definition at line 285 of file ald_i2c.h.

◆ master_tx_cplt_cbk

void(* master_tx_cplt_cbk) (struct i2c_handle_s *arg)

Master Tx completed callback

Definition at line 284 of file ald_i2c.h.

◆ mem_rx_cplt_cbk

void(* mem_rx_cplt_cbk) (struct i2c_handle_s *arg)

Rx from Memory completed callback

Definition at line 289 of file ald_i2c.h.

◆ mem_tx_cplt_cbk

void(* mem_tx_cplt_cbk) (struct i2c_handle_s *arg)

Tx to Memory completed callback

Definition at line 288 of file ald_i2c.h.

◆ mode

__IO i2c_mode_t mode

I2C communication mode

Definition at line 281 of file ald_i2c.h.

◆ p_buff

uint8_t* p_buff

Pointer to I2C transfer buffer

Definition at line 272 of file ald_i2c.h.

◆ perh

I2C_TypeDef* perh

I2C registers base address

Definition at line 270 of file ald_i2c.h.

◆ slave_rx_cplt_cbk

void(* slave_rx_cplt_cbk) (struct i2c_handle_s *arg)

Slave Rx completed callback

Definition at line 287 of file ald_i2c.h.

◆ slave_tx_cplt_cbk

void(* slave_tx_cplt_cbk) (struct i2c_handle_s *arg)

Slave Tx completed callback

Definition at line 286 of file ald_i2c.h.

◆ state

__IO i2c_state_t state

I2C communication state

Definition at line 280 of file ald_i2c.h.

◆ xfer_count

__IO uint16_t xfer_count

I2C transfer counter

Definition at line 274 of file ald_i2c.h.

◆ xfer_size

uint16_t xfer_size

I2C transfer size

Definition at line 273 of file ald_i2c.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_i2c.h


ALD User Manual: I2C Public Macros

Macros
I2C Public Macros
EASTSOFT ES32F3xx ALD » I2C
Collaboration diagram for I2C Public Macros:

Macros

#define | I2C_FLAG_MASK (0xFFFFFFFFU)
#define | I2C_RESET_HANDLE_STATE(x) ((x)->state = I2C_STATE_RESET)
#define | I2C_ENABLE_IT(x, y) (SET_BIT((x)->perh->IER, (y)))
#define | I2C_DISABLE_IT(x, y) (SET_BIT((x)->perh->IDR, (y)))
#define | I2C_CLEAR_IT(x, y) (SET_BIT((x)->perh->ICR, (y)))
#define | I2C_GET_IT_FLAG(x, y) (READ_BIT((x)->perh->RIF, (y)))
#define | I2C_GET_IT_SOURCE(x, y) ((((x)->perh->IFM & (y)) == (y)) ? SET : RESET)
#define | I2C_GET_FLAG(x, y) ((((x)->perh->STAT) & ((y) & I2C_FLAG_MASK)) != RESET)
#define | I2C_MASTER_GET_DIR(x) (READ_BIT(((x)->perh->CON2), I2C_CON2_RD_WRN_MSK))
#define | I2C_SLAVE_GET_DIR(x) (READ_BIT(hperh->perh->STAT, I2C_STAT_DIR_MSK))
#define | I2C_ENABLE(x) (SET_BIT((x)->perh->CON1, I2C_CON1_PE_MSK))
#define | I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PE_MSK))

Detailed Description

Macro Definition Documentation

◆ I2C_CLEAR_IT

#define I2C_CLEAR_IT | ( | x,
 |  | y
 | ) | (SET_BIT((x)->perh->ICR, (y)))

Definition at line 304 of file ald_i2c.h.

◆ I2C_DISABLE

#define I2C_DISABLE ( x ) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PE_MSK))

Definition at line 311 of file ald_i2c.h.

◆ I2C_DISABLE_IT

#define I2C_DISABLE_IT | ( | x,
 |  | y
 | ) | (SET_BIT((x)->perh->IDR, (y)))

Definition at line 303 of file ald_i2c.h.

◆ I2C_ENABLE

#define I2C_ENABLE ( x ) (SET_BIT((x)->perh->CON1, I2C_CON1_PE_MSK))

Definition at line 310 of file ald_i2c.h.

◆ I2C_ENABLE_IT

#define I2C_ENABLE_IT | ( | x,
 |  | y
 | ) | (SET_BIT((x)->perh->IER, (y)))

Definition at line 302 of file ald_i2c.h.

◆ I2C_FLAG_MASK

#define I2C_FLAG_MASK (0xFFFFFFFFU)

Definition at line 300 of file ald_i2c.h.

◆ I2C_GET_FLAG

#define I2C_GET_FLAG | ( | x,
 |  | y
 | ) | ((((x)->perh->STAT) & ((y) & I2C_FLAG_MASK)) != RESET)

Definition at line 307 of file ald_i2c.h.

◆ I2C_GET_IT_FLAG

#define I2C_GET_IT_FLAG | ( | x,
 |  | y
 | ) | (READ_BIT((x)->perh->RIF, (y)))

Definition at line 305 of file ald_i2c.h.

◆ I2C_GET_IT_SOURCE

#define I2C_GET_IT_SOURCE | ( | x,
 |  | y
 | ) | ((((x)->perh->IFM & (y)) == (y)) ? SET : RESET)

Definition at line 306 of file ald_i2c.h.

◆ I2C_MASTER_GET_DIR

#define I2C_MASTER_GET_DIR ( x ) (READ_BIT(((x)->perh->CON2), I2C_CON2_RD_WRN_MSK))

Definition at line 308 of file ald_i2c.h.

◆ I2C_RESET_HANDLE_STATE

#define I2C_RESET_HANDLE_STATE ( x ) ((x)->state = I2C_STATE_RESET)

Definition at line 301 of file ald_i2c.h.

◆ I2C_SLAVE_GET_DIR

#define I2C_SLAVE_GET_DIR ( x ) (READ_BIT(hperh->perh->STAT, I2C_STAT_DIR_MSK))

Definition at line 309 of file ald_i2c.h.


ALD User Manual: I2C Private Macros

Macros
I2C Private Macros
EASTSOFT ES32F3xx ALD » I2C
Collaboration diagram for I2C Private Macros:

Macros

#define | IS_I2C_TYPE(x) (((x) == I2C0) || ((x) == I2C1))
#define | IS_I2C_MODULE(x) (((x) == I2C_MODULE_MASTER) || ((x) == I2C_MODULE_SLAVE))
#define | IS_I2C_ADDRESSING_MODE(ADDRESS)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_MEMADD_size(size)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= I2C_EXTREME_FAST_MODE_MAX_CLK) )
#define | I2C_FREQ_RANGE(__PCLK__) ((__PCLK__) / 1000000)
#define | I2C_MEM_ADD_MSB(__ADDRESS__)
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
#define | IS_I2C_IT(x)

Detailed Description

Macro Definition Documentation

◆ I2C_FREQ_RANGE

#define I2C_FREQ_RANGE ( __PCLK__ ) ((__PCLK__) / 1000000)

Definition at line 332 of file ald_i2c.h.

◆ I2C_MEM_ADD_LSB

#define I2C_MEM_ADD_LSB ( __ADDRESS__ ) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))

Definition at line 335 of file ald_i2c.h.

◆ I2C_MEM_ADD_MSB

#define I2C_MEM_ADD_MSB ( __ADDRESS__ )
Value:
((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) &\
(uint16_t)(0xFF00))) >> 8)))

Definition at line 333 of file ald_i2c.h.

◆ IS_I2C_ADDRESSING_MODE

#define IS_I2C_ADDRESSING_MODE ( ADDRESS )
Value:
(((ADDRESS) == I2C_ADDR_7BIT) || \
((ADDRESS) == I2C_ADDR_10BIT))
I2C_ADDR_10BIT
Definition: ald_i2c.h:76
I2C_ADDR_7BIT
Definition: ald_i2c.h:75

Definition at line 321 of file ald_i2c.h.

◆ IS_I2C_CLOCK_SPEED

#define IS_I2C_CLOCK_SPEED ( SPEED ) (((SPEED) > 0) && ((SPEED) <= I2C_EXTREME_FAST_MODE_MAX_CLK) )

Definition at line 331 of file ald_i2c.h.

◆ IS_I2C_DUAL_ADDRESS

#define IS_I2C_DUAL_ADDRESS ( ADDRESS )
Value:
(((ADDRESS) == I2C_DUALADDR_DISABLE) || \
((ADDRESS) == I2C_DUALADDR_ENABLE))
I2C_DUALADDR_DISABLE
Definition: ald_i2c.h:83
I2C_DUALADDR_ENABLE
Definition: ald_i2c.h:84

Definition at line 323 of file ald_i2c.h.

◆ IS_I2C_GENERAL_CALL

#define IS_I2C_GENERAL_CALL ( CALL )
Value:
(((CALL) == I2C_GENERALCALL_DISABLE) || \
((CALL) == I2C_GENERALCALL_ENABLE))
I2C_GENERALCALL_ENABLE
Definition: ald_i2c.h:92
I2C_GENERALCALL_DISABLE
Definition: ald_i2c.h:91

Definition at line 325 of file ald_i2c.h.

◆ IS_I2C_IT

#define IS_I2C_IT ( x )
Value:
(((x) == I2C_IT_TXE) || \
((x) == I2C_IT_TXOV) || \
((x) == I2C_IT_TXUD) || \
((x) == I2C_IT_TXTH) || \
((x) == I2C_IT_RXF) || \
((x) == I2C_IT_RXOV) || \
((x) == I2C_IT_RXUD) || \
((x) == I2C_IT_RXTH) || \
((x) == I2C_IT_TC) || \
((x) == I2C_IT_TCR) || \
((x) == I2C_IT_ADDR) || \
((x) == I2C_IT_NACK) || \
((x) == I2C_IT_STOP) || \
((x) == I2C_IT_BERR) || \
((x) == I2C_IT_ARLO) || \
((x) == I2C_IT_PECE) || \
((x) == I2C_IT_TOUT) || \
((x) == I2C_IT_ALERT))
I2C_IT_TXE
Definition: ald_i2c.h:225
I2C_IT_RXF
Definition: ald_i2c.h:229
I2C_IT_ALERT
Definition: ald_i2c.h:242
I2C_IT_BERR
Definition: ald_i2c.h:238
I2C_IT_ADDR
Definition: ald_i2c.h:235
I2C_IT_ARLO
Definition: ald_i2c.h:239
I2C_IT_TOUT
Definition: ald_i2c.h:241
I2C_IT_TXTH
Definition: ald_i2c.h:228
I2C_IT_NACK
Definition: ald_i2c.h:236
I2C_IT_RXUD
Definition: ald_i2c.h:231
I2C_IT_TXUD
Definition: ald_i2c.h:227
I2C_IT_TXOV
Definition: ald_i2c.h:226
I2C_IT_STOP
Definition: ald_i2c.h:237
I2C_IT_TC
Definition: ald_i2c.h:233
I2C_IT_TCR
Definition: ald_i2c.h:234
I2C_IT_RXTH
Definition: ald_i2c.h:232
I2C_IT_PECE
Definition: ald_i2c.h:240
I2C_IT_RXOV
Definition: ald_i2c.h:230

Definition at line 336 of file ald_i2c.h.

◆ IS_I2C_MEMADD_size

#define IS_I2C_MEMADD_size ( size )
Value:
(((size) == I2C_MEMADD_SIZE_8BIT) || \
((size) == I2C_MEMADD_SIZE_16BIT))
I2C_MEMADD_SIZE_8BIT
Definition: ald_i2c.h:107
I2C_MEMADD_SIZE_16BIT
Definition: ald_i2c.h:108

Definition at line 327 of file ald_i2c.h.

◆ IS_I2C_MODULE

#define IS_I2C_MODULE ( x ) (((x) == I2C_MODULE_MASTER) || ((x) == I2C_MODULE_SLAVE))

Definition at line 320 of file ald_i2c.h.

◆ IS_I2C_NO_STRETCH

#define IS_I2C_NO_STRETCH ( STRETCH )
Value:
(((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
((STRETCH) == I2C_NOSTRETCH_ENABLE))
I2C_NOSTRETCH_ENABLE
Definition: ald_i2c.h:100
I2C_NOSTRETCH_DISABLE
Definition: ald_i2c.h:99

Definition at line 329 of file ald_i2c.h.

◆ IS_I2C_TYPE

#define IS_I2C_TYPE ( x ) (((x) == I2C0) || ((x) == I2C1))

Definition at line 319 of file ald_i2c.h.


ALD User Manual: I2C Private Constants

Macros
I2C Private Constants
EASTSOFT ES32F3xx ALD » I2C
Collaboration diagram for I2C Private Constants:

Macros

#define | I2C_TIMEOUT_FLAG (__systick_interval / 20 + 1)
#define | I2C_TIMEOUT_ADDR_SLAVE (__systick_interval * 10)
#define | I2C_TIMEOUT_BUSY_FLAG (__systick_interval * 10)
#define | I2C_MAX_DELAY 0xFFFFFFFF

Detailed Description

Macro Definition Documentation

◆ I2C_MAX_DELAY

#define I2C_MAX_DELAY 0xFFFFFFFF

Definition at line 174 of file ald_i2c.c.

◆ I2C_TIMEOUT_ADDR_SLAVE

#define I2C_TIMEOUT_ADDR_SLAVE (__systick_interval * 10)

Definition at line 172 of file ald_i2c.c.

◆ I2C_TIMEOUT_BUSY_FLAG

#define I2C_TIMEOUT_BUSY_FLAG (__systick_interval * 10)

Definition at line 173 of file ald_i2c.c.

◆ I2C_TIMEOUT_FLAG

#define I2C_TIMEOUT_FLAG (__systick_interval / 20 + 1)

Definition at line 171 of file ald_i2c.c.


ALD User Manual: I2S

Modules
I2S
EASTSOFT ES32F3xx ALD

I2S module driver. More...

Collaboration diagram for I2S:

Modules

I2S Public Functions
I2S Private Functions
I2S Private functions.
I2S Public Types
I2S Public Macros
I2S Private Macros

Detailed Description

I2S module driver.


ALD User Manual: I2S Public Functions

Modules
I2S Public Functions
EASTSOFT ES32F3xx ALD » I2S
Collaboration diagram for I2S Public Functions:

Modules

Initialization functions
Initialization and Configuration functions.
IO operation functions
I2S Transmit and Receive functions.
Control functions
I2S Control functions.
Peripheral State and Errors functions
I2S State and Errors functions.

Detailed Description


ALD User Manual: Initialization functions

Functions
Initialization functions
EASTSOFT ES32F3xx ALD » I2S » I2S Public Functions

Initialization and Configuration functions. More...

Collaboration diagram for Initialization functions:

Functions

void | ald_i2s_reset (i2s_handle_t *hperh)
Reset the I2S peripheral. More...
ald_status_t | ald_i2s_init (i2s_handle_t *hperh)
Initializes the I2S mode according to the specified parameters in the i2s_init_t and create the associated handle. More...

Detailed Description

Initialization and Configuration functions.

===============================================================================
             ##### Initialization and de-initialization functions #####
===============================================================================
   [..]  This subsection provides a set of functions allowing to initialize and
         reset the I2Sx peripheral:

     (+) User must configure all related peripherals resources
         (CLOCK, GPIO, DMA, NVIC).

     (+) Call the function ald_i2s_init() to configure the selected device with
         the selected configuration:
       (++) Channel length
       (++) Data length
       (++) Polarity
       (++) Standard
       (++) Pcm frame
       (++) External clock
       (++) Main clock output function
       (++) Odd factor
       (++) Divide clock

     (+) Call the function ald_i2s_reset() to reset the selected I2Sx periperal.

Function Documentation

◆ ald_i2s_init()

ald_status_t ald_i2s_init ( i2s_handle_t * hperh )

Initializes the I2S mode according to the specified parameters in the i2s_init_t and create the associated handle.

Parameters
hperh Pointer to a i2s_handle_t structure that contains the configuration information for the specified SPI module.
Return values
Status,see ald_status_t.

Definition at line 146 of file ald_i2s.c.

147 {
148 uint32_t tmp = 0, clk, _div;
149
150 if (hperh == NULL)
151 return ERROR;
152
153 assert_param(IS_I2S(hperh->perh));
154 assert_param(IS_I2S_CH_LEN(hperh->init.ch_len));
155 assert_param(IS_I2S_DATE_LEN(hperh->init.data_len));
156 assert_param(IS_I2S_CPOL(hperh->init.polarity));
157 assert_param(IS_I2S_STANDARD(hperh->init.standard));
158 assert_param(IS_FUNC_STATE(hperh->init.ext_clk_en));
159 assert_param(IS_FUNC_STATE(hperh->init.mck_en));
160 assert_param(IS_I2S_PCMS(hperh->init.pcm_frame));
161
162 ald_i2s_reset(hperh);
163
164 tmp |= (hperh->init.ext_clk_en << SPI_I2SPR_EXTCKEN_POS);
165
166 /* Get I2S clock */
167 if (hperh->init.ext_clk_en)
168 clk = hperh->init.ext_clk;
169 else
170 clk = ald_cmu_get_pclk1_clock();
171
172 if (hperh->init.mck_en) {
173 _div = ((clk / hperh->init.sampling) >> 8);
174 }
175 else {
176 if (hperh->init.ch_len == I2S_WIDE_16)
177 _div = ((clk / hperh->init.sampling) >> 5);
178 else
179 _div = ((clk / hperh->init.sampling) >> 6);
180 }
181
182 if (_div & 0x1) {
183 SET_BIT(tmp, SPI_I2SPR_ODD_MSK);
184 --_div;
185 }
186 else {
187 CLEAR_BIT(tmp, SPI_I2SPR_ODD_MSK);
188 }
189
190 if (hperh->init.standard != I2S_STD_PCM)
191 MODIFY_REG(tmp, SPI_I2SPR_I2SDIV_MSK, (_div >> 1) << SPI_I2SPR_I2SDIV_POSS);
192 else
193 MODIFY_REG(tmp, SPI_I2SPR_I2SDIV_MSK, _div << SPI_I2SPR_I2SDIV_POSS);
194
195 hperh->perh->I2SPR = tmp;
196
197 tmp = hperh->perh->I2SCFG;
198 tmp |= ((hperh->init.ch_len << SPI_I2SCFG_CHLEN_POS) | (hperh->init.data_len << SPI_I2SCFG_DATLEN_POSS) |
199 (hperh->init.polarity << SPI_I2SCFG_CKPOL_POS) | (hperh->init.standard << SPI_I2SCFG_I2SSTD_POSS) |
200 (1 << SPI_I2SCFG_I2SMOD_POS));
201 hperh->perh->I2SCFG = tmp;
202
203 if (hperh->init.standard == I2S_STD_PCM)
204 hperh->perh->I2SCFG |= (hperh->init.pcm_frame << SPI_I2SCFG_PCMSYNC_POS);
205
206 hperh->err_code = I2S_ERROR_NONE;
207 hperh->state = I2S_STATE_READY;
208
209 return OK;
210 }
i2s_init_t::data_len
i2s_datalen_t data_len
Definition: ald_i2s.h:193
OK
Definition: utils.h:55
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
i2s_init_t::ext_clk_en
type_func_t ext_clk_en
Definition: ald_i2s.h:197
i2s_init_t::sampling
uint32_t sampling
Definition: ald_i2s.h:200
I2S_STD_PCM
Definition: ald_i2s.h:71
IS_I2S
#define IS_I2S(x)
Definition: ald_i2s.h:245
IS_I2S_CPOL
#define IS_I2S_CPOL(x)
Definition: ald_i2s.h:253
i2s_init_t::ext_clk
uint32_t ext_clk
Definition: ald_i2s.h:198
IS_I2S_STANDARD
#define IS_I2S_STANDARD(x)
Definition: ald_i2s.h:255
i2s_handle_s::state
i2s_state_t state
Definition: ald_i2s.h:220
i2s_init_t::ch_len
i2s_chlen_t ch_len
Definition: ald_i2s.h:192
i2s_handle_s::err_code
uint32_t err_code
Definition: ald_i2s.h:222
IS_I2S_DATE_LEN
#define IS_I2S_DATE_LEN(x)
Definition: ald_i2s.h:250
i2s_init_t::standard
i2s_standard_t standard
Definition: ald_i2s.h:195
i2s_init_t::mck_en
type_func_t mck_en
Definition: ald_i2s.h:199
IS_I2S_PCMS
#define IS_I2S_PCMS(x)
Definition: ald_i2s.h:259
I2S_ERROR_NONE
Definition: ald_i2s.h:94
ald_cmu_get_pclk1_clock
uint32_t ald_cmu_get_pclk1_clock(void)
Get APB1 clock.
Definition: ald_cmu.c:627
I2S_WIDE_16
Definition: ald_i2s.h:43
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
i2s_init_t::polarity
i2s_cpol_t polarity
Definition: ald_i2s.h:194
I2S_STATE_READY
Definition: ald_i2s.h:146
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_I2S_CH_LEN
#define IS_I2S_CH_LEN(x)
Definition: ald_i2s.h:248
ald_i2s_reset
void ald_i2s_reset(i2s_handle_t *hperh)
Reset the I2S peripheral.
Definition: ald_i2s.c:128
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
ERROR
Definition: utils.h:56
i2s_handle_s::init
i2s_init_t init
Definition: ald_i2s.h:208
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207
i2s_init_t::pcm_frame
i2s_pcms_t pcm_frame
Definition: ald_i2s.h:196

◆ ald_i2s_reset()

void ald_i2s_reset ( i2s_handle_t * hperh )

Reset the I2S peripheral.

Parameters
hperh Pointer to a i2s_handle_t structure that contains the configuration information for the specified I2S module.
Return values
None

Definition at line 128 of file ald_i2s.c.

129 {
130 hperh->perh->I2SCFG = 0x0;
131 hperh->perh->I2SPR = 0x0;
132
133 I2S_RESET_HANDLE_STATE(hperh);
134 __UNLOCK(hperh);
135
136 return;
137 }
I2S_RESET_HANDLE_STATE
#define I2S_RESET_HANDLE_STATE(x)
Definition: ald_i2s.h:235
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207


ALD User Manual: IO operation functions

Functions
IO operation functions
EASTSOFT ES32F3xx ALD » I2S » I2S Public Functions

I2S Transmit and Receive functions. More...

Collaboration diagram for IO operation functions:

Functions

ald_status_t | ald_i2s_master_send (i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout)
Master mode transmit an amount of data in blocking mode. More...
ald_status_t | ald_i2s_master_recv (i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout)
Master mode receive an amount of data in blocking mode. More...
ald_status_t | ald_i2s_master_send_by_it (i2s_handle_t *hperh, uint16_t *buf, uint32_t size)
Wraps up master mode transmission in non blocking mode. More...
ald_status_t | ald_i2s_master_recv_by_it (i2s_handle_t *hperh, uint16_t *buf, uint32_t size)
Master mode receives an amount of data in non blocking mode. More...
ald_status_t | ald_i2s_master_send_by_dma (i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t channel)
Master mode transmit an amount of data used dma channel. More...
ald_status_t | ald_i2s_master_recv_by_dma (i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t dma_ch, uint8_t _dma_ch)
Master mode receive an amount of data used dma channel. More...
ald_status_t | ald_i2s_dma_pause (i2s_handle_t *hperh)
Pauses the DMA Transfer. More...
ald_status_t | ald_i2s_dma_resume (i2s_handle_t *hperh)
Resumes the DMA Transfer. More...
ald_status_t | ald_i2s_dma_stop (i2s_handle_t *hperh)
Stops the DMA Transfer. More...

Detailed Description

I2S Transmit and Receive functions.

 ==============================================================================
                     ##### IO operation functions #####
===============================================================================
   This subsection provides a set of functions allowing to manage the I2S
   data transfers.

   [..] The I2S supports master or slave mode:

   (#) There are two modes of transfer:
      (++) Blocking mode: The communication is performed in polling mode.
           The ALD status of all data processing is returned by the same function
           after finishing transfer.
      (++) No-Blocking mode: The communication is performed using Interrupts
           or DMA, These APIs return the ALD status.
           The end of the data processing will be indicated through the
           dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.
           The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() user callbacks
           will be executed respectivelly at the end of the transmit or Receive process
           The hperh->err_cbk() user callback will be executed when a communication error is detected

   (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA).

 *

Function Documentation

◆ ald_i2s_dma_pause()

ald_status_t ald_i2s_dma_pause ( i2s_handle_t * hperh )

Pauses the DMA Transfer.

Parameters
hperh Pointer to a i2s_handle_t structure.
Return values
Status

Definition at line 575 of file ald_i2s.c.

576 {
577 assert_param(IS_I2S(hperh->perh));
578
579 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, DISABLE);
580 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, DISABLE);
581
582 return OK;
583 }
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
ald_i2s_dma_req_config
void ald_i2s_dma_req_config(i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t state)
Enables or disables the dma request.
Definition: ald_i2s.c:709
DISABLE
Definition: type.h:48
IS_I2S
#define IS_I2S(x)
Definition: ald_i2s.h:245
I2S_DMA_REQ_TX
Definition: ald_i2s.h:123
I2S_DMA_REQ_RX
Definition: ald_i2s.h:124
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207

◆ ald_i2s_dma_resume()

ald_status_t ald_i2s_dma_resume ( i2s_handle_t * hperh )

Resumes the DMA Transfer.

Parameters
hperh Pointer to a i2s_handle_t structure.
Return values
Status

Definition at line 590 of file ald_i2s.c.

591 {
592 assert_param(IS_I2S(hperh->perh));
593
594 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, ENABLE);
595 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, ENABLE);
596
597 return OK;
598 }
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
ald_i2s_dma_req_config
void ald_i2s_dma_req_config(i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t state)
Enables or disables the dma request.
Definition: ald_i2s.c:709
IS_I2S
#define IS_I2S(x)
Definition: ald_i2s.h:245
I2S_DMA_REQ_TX
Definition: ald_i2s.h:123
I2S_DMA_REQ_RX
Definition: ald_i2s.h:124
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207

◆ ald_i2s_dma_stop()

ald_status_t ald_i2s_dma_stop ( i2s_handle_t * hperh )

Stops the DMA Transfer.

Parameters
hperh Pointer to a i2s_handle_t structure.
Return values
Status

Definition at line 605 of file ald_i2s.c.

606 {
607 assert_param(IS_I2S(hperh->perh));
608
609 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, DISABLE);
610 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, DISABLE);
611
612 hperh->state = I2S_STATE_READY;
613 return OK;
614 }
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
ald_i2s_dma_req_config
void ald_i2s_dma_req_config(i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t state)
Enables or disables the dma request.
Definition: ald_i2s.c:709
DISABLE
Definition: type.h:48
IS_I2S
#define IS_I2S(x)
Definition: ald_i2s.h:245
i2s_handle_s::state
i2s_state_t state
Definition: ald_i2s.h:220
I2S_DMA_REQ_TX
Definition: ald_i2s.h:123
I2S_STATE_READY
Definition: ald_i2s.h:146
I2S_DMA_REQ_RX
Definition: ald_i2s.h:124
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207

◆ ald_i2s_master_recv()

ald_status_t ald_i2s_master_recv | ( | i2s_handle_t * | hperh,
 |  | uint16_t * | buf,
 |  | uint32_t | size,
 |  | uint32_t | timeout
 | ) |  |

Master mode receive an amount of data in blocking mode.

Parameters
hperh | Pointer to a i2s_handle_t structure.
buf | Pointer to data buffer
size | Amount of data to be received
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 307 of file ald_i2s.c.

308 {
309 assert_param(IS_I2S(hperh->perh));
310
311 if (hperh->state != I2S_STATE_READY)
312 return BUSY;
313 if (buf == NULL || size == 0)
314 return ERROR;
315
316 hperh->state = I2S_STATE_BUSY_RX;
317 hperh->err_code = I2S_ERROR_NONE;
318
319 MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_RECEIVE << SPI_I2SCFG_I2SCFG_POSS);
320
321 if (hperh->init.mck_en)
322 MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS);
323 if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0)
324 I2S_ENABLE(hperh);
325
326 while (size > 0) {
327 hperh->perh->DATA = 0xffff;
328 if (i2s_wait_status(hperh, I2S_STATUS_RXE, RESET, timeout) != OK) {
329 I2S_DISABLE(hperh);
330 hperh->state = I2S_STATE_READY;
331 return TIMEOUT;
332 }
333
334 *buf++ = hperh->perh->DATA;
335 --size;
336 }
337
338 hperh->state = I2S_STATE_READY;
339 return OK;
340 }
I2S_ENABLE
#define I2S_ENABLE(x)
Definition: ald_i2s.h:236
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
I2S_MASTER_RECEIVE
Definition: ald_i2s.h:79
IS_I2S
#define IS_I2S(x)
Definition: ald_i2s.h:245
RESET
Definition: type.h:38
i2s_handle_s::state
i2s_state_t state
Definition: ald_i2s.h:220
i2s_wait_status
static ald_status_t i2s_wait_status(i2s_handle_t *hperh, i2s_status_t state, flag_status_t status, uint32_t timeout)
This function wait I2S status until timeout.
Definition: ald_i2s.c:882
i2s_handle_s::err_code
uint32_t err_code
Definition: ald_i2s.h:222
i2s_init_t::mck_en
type_func_t mck_en
Definition: ald_i2s.h:199
I2S_STATE_BUSY_RX
Definition: ald_i2s.h:149
I2S_ERROR_NONE
Definition: ald_i2s.h:94
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
TIMEOUT
Definition: utils.h:58
I2S_STATUS_RXE
Definition: ald_i2s.h:163
I2S_STATE_READY
Definition: ald_i2s.h:146
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
ERROR
Definition: utils.h:56
i2s_handle_s::init
i2s_init_t init
Definition: ald_i2s.h:208
I2S_DISABLE
#define I2S_DISABLE(x)
Definition: ald_i2s.h:237
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207

◆ ald_i2s_master_recv_by_dma()

ald_status_t ald_i2s_master_recv_by_dma | ( | i2s_handle_t * | hperh,
 |  | uint16_t * | buf,
 |  | uint32_t | size,
 |  | uint8_t | dma_ch,
 |  | uint8_t | _dma_ch
 | ) |  |

Master mode receive an amount of data used dma channel.

Parameters
hperh | Pointer to a i2s_handle_t structure.
buf | Pointer to data buffer
size | Amount of data to be sent
dma_ch | DMA channel for I2S receive
_dma_ch | DMA channel for sending clock
Return values
Status,see ald_status_t.

Definition at line 495 of file ald_i2s.c.

496 {
497 assert_param(IS_I2S(hperh->perh));
498
499 if (hperh->state != I2S_STATE_READY)
500 return BUSY;
501 if (buf == NULL || size == 0)
502 return ERROR;
503
504 hperh->state = I2S_STATE_BUSY_RX;
505 hperh->err_code = I2S_ERROR_NONE;
506 hperh->rx_buf = buf;
507 hperh->rx_size = size;
508 hperh->rx_count = size;
509 hperh->tx_buf = NULL;
510 hperh->tx_size = 0;
511 hperh->tx_count = 0;
512 buf[size - 1] = 0xFFFF;
513
514 WRITE_REG(hperh->perh->ICR, 0xffffffff);
515
516 I2S_DISABLE(hperh);
517
518 MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_RECEIVE << SPI_I2SCFG_I2SCFG_POSS);
519
520 if (hperh->init.mck_en)
521 MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS);
522
523 hperh->hdmatx.cplt_arg = (void *)hperh;
524 hperh->hdmatx.cplt_cbk = i2s_dma_send_cplt;
525 hperh->hdmatx.err_arg = (void *)hperh;
526 hperh->hdmatx.err_cbk = i2s_dma_error;
527
528 ald_dma_config_struct(&(hperh->hdmatx.config));
529 hperh->hdmatx.perh = DMA0;
530 hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD;
531 hperh->hdmatx.config.src = (void *)&buf[size - 1];
532 hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA;
533 hperh->hdmatx.config.size = size;
534 hperh->hdmatx.config.src_inc = DMA_DATA_INC_NONE;
535 hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
536 hperh->hdmatx.config.msel = hperh->perh == I2S0 ? DMA_MSEL_SPI0 : (hperh->perh == I2S1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2);
537 hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY;
538 hperh->hdmatx.config.burst = ENABLE;
539 hperh->hdmatx.config.channel = _dma_ch;
540 ald_dma_config_basic(&(hperh->hdmatx));
541 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, ENABLE);
542
543 hperh->hdmarx.cplt_arg = (void *)hperh;
544 hperh->hdmarx.cplt_cbk = i2s_dma_recv_cplt;
545 hperh->hdmarx.err_arg = (void *)hperh;
546 hperh->hdmarx.err_cbk = i2s_dma_error;
547
548 /* Configure DMA Receive */
549 ald_dma_config_struct(&(hperh->hdmarx.config));
550 hperh->hdmarx.perh = DMA0;
551 hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD;
552 hperh->hdmarx.config.src = (void *)&hperh->perh->DATA;
553 hperh->hdmarx.config.dst = (void *)buf;
554 hperh->hdmarx.config.size = size;
555 hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE;
556 hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD;
557 hperh->hdmarx.config.msel = hperh->perh == I2S0 ? DMA_MSEL_SPI0 : (hperh->perh == I2S1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2);
558 hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR;
559 hperh->hdmarx.config.channel = dma_ch;
560 hperh->hdmarx.config.burst = ENABLE;
561 ald_dma_config_basic(&(hperh->hdmarx));
562 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, ENABLE);
563
564 if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0)
565 I2S_ENABLE(hperh);
566
567 return OK;
568 }
DMA_MSEL_SPI1
Definition: ald_dma.h:91
I2S_ENABLE
#define I2S_ENABLE(x)
Definition: ald_i2s.h:236
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
i2s_dma_error
static void i2s_dma_error(void *arg)
DMA I2S communication error callback.
Definition: ald_i2s.c:1033
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
ald_i2s_dma_req_config
void ald_i2s_dma_req_config(i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t state)
Enables or disables the dma request.
Definition: ald_i2s.c:709
DMA_MSEL_SPI2
Definition: ald_dma.h:99
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
I2S_MASTER_RECEIVE
Definition: ald_i2s.h:79
i2s_handle_s::rx_buf
uint16_t * rx_buf
Definition: ald_i2s.h:212
i2s_dma_recv_cplt
static void i2s_dma_recv_cplt(void *arg)
DMA I2S receive process complete callback.
Definition: ald_i2s.c:1008
IS_I2S
#define IS_I2S(x)
Definition: ald_i2s.h:245
i2s_handle_s::hdmarx
dma_handle_t hdmarx
Definition: ald_i2s.h:217
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
i2s_handle_s::state
i2s_state_t state
Definition: ald_i2s.h:220
i2s_handle_s::err_code
uint32_t err_code
Definition: ald_i2s.h:222
i2s_handle_s::tx_size
uint32_t tx_size
Definition: ald_i2s.h:210
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
i2s_init_t::mck_en
type_func_t mck_en
Definition: ald_i2s.h:199
I2S_STATE_BUSY_RX
Definition: ald_i2s.h:149
I2S_ERROR_NONE
Definition: ald_i2s.h:94
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
DMA_MSIGSEL_SPI_RNR
Definition: ald_dma.h:141
I2S_DMA_REQ_TX
Definition: ald_i2s.h:123
i2s_handle_s::tx_buf
uint16_t * tx_buf
Definition: ald_i2s.h:209
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
i2s_handle_s::rx_count
uint32_t rx_count
Definition: ald_i2s.h:214
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
i2s_handle_s::hdmatx
dma_handle_t hdmatx
Definition: ald_i2s.h:216
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
I2S_STATE_READY
Definition: ald_i2s.h:146
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
DMA_MSIGSEL_SPI_TXEMPTY
Definition: ald_dma.h:142
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
I2S_DMA_REQ_RX
Definition: ald_i2s.h:124
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
DMA_MSEL_SPI0
Definition: ald_dma.h:90
i2s_handle_s::tx_count
uint32_t tx_count
Definition: ald_i2s.h:211
ERROR
Definition: utils.h:56
i2s_handle_s::init
i2s_init_t init
Definition: ald_i2s.h:208
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
i2s_dma_send_cplt
static void i2s_dma_send_cplt(void *arg)
DMA I2S transmit process complete callback.
Definition: ald_i2s.c:978
I2S_DISABLE
#define I2S_DISABLE(x)
Definition: ald_i2s.h:237
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207
i2s_handle_s::rx_size
uint32_t rx_size
Definition: ald_i2s.h:213

◆ ald_i2s_master_recv_by_it()

ald_status_t ald_i2s_master_recv_by_it | ( | i2s_handle_t * | hperh,
 |  | uint16_t * | buf,
 |  | uint32_t | size
 | ) |  |

Master mode receives an amount of data in non blocking mode.

Parameters
hperh | Pointer to a i2s_handle_t structure.
buf | Pointer to data received buffer
size | Amount of data to be sent
Return values
Status,see ald_status_t.

Definition at line 388 of file ald_i2s.c.

389 {
390 assert_param(IS_I2S(hperh->perh));
391
392 if (hperh->state != I2S_STATE_READY)
393 return BUSY;
394 if (buf == NULL || size == 0)
395 return ERROR;
396
397 hperh->state = I2S_STATE_BUSY_TX_RX;
398 hperh->err_code = I2S_ERROR_NONE;
399 hperh->rx_buf = buf;
400 hperh->rx_size = size;
401 hperh->rx_count = size;
402 hperh->tx_buf = 0;
403 hperh->tx_size = size;
404 hperh->tx_count = size;
405
406 WRITE_REG(hperh->perh->ICR, 0xffffffff);
407
408 I2S_DISABLE(hperh);
409 MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_RECEIVE << SPI_I2SCFG_I2SCFG_POSS);
410
411 if (hperh->init.mck_en)
412 MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS);
413
414 if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0)
415 I2S_ENABLE(hperh);
416
417 ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, ENABLE);
418 ald_i2s_interrupt_config(hperh, I2S_IT_TXE, ENABLE);
419
420 return OK;
421 }
I2S_ENABLE
#define I2S_ENABLE(x)
Definition: ald_i2s.h:236
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
I2S_IT_RXTH
Definition: ald_i2s.h:113
I2S_IT_TXE
Definition: ald_i2s.h:107
I2S_MASTER_RECEIVE
Definition: ald_i2s.h:79
i2s_handle_s::rx_buf
uint16_t * rx_buf
Definition: ald_i2s.h:212
IS_I2S
#define IS_I2S(x)
Definition: ald_i2s.h:245
I2S_STATE_BUSY_TX_RX
Definition: ald_i2s.h:150
i2s_handle_s::state
i2s_state_t state
Definition: ald_i2s.h:220
i2s_handle_s::err_code
uint32_t err_code
Definition: ald_i2s.h:222
ald_i2s_interrupt_config
void ald_i2s_interrupt_config(i2s_handle_t *hperh, i2s_it_t it, type_func_t state)
Enables or disables the specified I2S interrupts.
Definition: ald_i2s.c:685
i2s_handle_s::tx_size
uint32_t tx_size
Definition: ald_i2s.h:210
i2s_init_t::mck_en
type_func_t mck_en
Definition: ald_i2s.h:199
I2S_ERROR_NONE
Definition: ald_i2s.h:94
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
i2s_handle_s::tx_buf
uint16_t * tx_buf
Definition: ald_i2s.h:209
i2s_handle_s::rx_count
uint32_t rx_count
Definition: ald_i2s.h:214
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
I2S_STATE_READY
Definition: ald_i2s.h:146
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
i2s_handle_s::tx_count
uint32_t tx_count
Definition: ald_i2s.h:211
ERROR
Definition: utils.h:56
i2s_handle_s::init
i2s_init_t init
Definition: ald_i2s.h:208
I2S_DISABLE
#define I2S_DISABLE(x)
Definition: ald_i2s.h:237
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207
i2s_handle_s::rx_size
uint32_t rx_size
Definition: ald_i2s.h:213

◆ ald_i2s_master_send()

ald_status_t ald_i2s_master_send | ( | i2s_handle_t * | hperh,
 |  | uint16_t * | buf,
 |  | uint32_t | size,
 |  | uint32_t | timeout
 | ) |  |

Master mode transmit an amount of data in blocking mode.

Parameters
hperh | Pointer to a i2s_handle_t structure.
buf | Pointer to data buffer
size | Amount of data to be sent
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 254 of file ald_i2s.c.

255 {
256 assert_param(IS_I2S(hperh->perh));
257
258 if (hperh->state != I2S_STATE_READY)
259 return BUSY;
260 if (buf == NULL || size == 0)
261 return ERROR;
262
263 hperh->state = I2S_STATE_BUSY_TX;
264 hperh->err_code = I2S_ERROR_NONE;
265
266 MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS);
267
268 if (hperh->init.mck_en)
269 MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS);
270 if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0)
271 I2S_ENABLE(hperh);
272
273 while (size > 0) {
274 if (i2s_wait_status(hperh, I2S_STATUS_TXE, SET, timeout) != OK) {
275 I2S_DISABLE(hperh);
276
277 hperh->state = I2S_STATE_READY;
278 return TIMEOUT;
279 }
280
281 hperh->side = READ_BITS(hperh->perh->STAT, SPI_STAT_CHSIDE_MSK, SPI_STAT_CHSIDE_POS);
282 hperh->perh->DATA = *buf++;
283 --size;
284 }
285
286 if ((i2s_wait_status(hperh, I2S_STATUS_TXE, SET, timeout) != OK)
287 || (i2s_wait_status(hperh, I2S_STATUS_BUSY, RESET, timeout) != OK)) {
288 I2S_DISABLE(hperh);
289 hperh->state = I2S_STATE_READY;
290 return TIMEOUT;
291 }
292
293 I2S_DISABLE(hperh);
294 hperh->state = I2S_STATE_READY;
295
296 return OK;
297 }
I2S_MASTER_TRANSMIT
Definition: ald_i2s.h:78
I2S_ENABLE
#define I2S_ENABLE(x)
Definition: ald_i2s.h:236
OK
Definition: utils.h:55
i2s_handle_s::side
uint8_t side
Definition: ald_i2s.h:221
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
SET
Definition: type.h:39
I2S_STATUS_BUSY
Definition: ald_i2s.h:168
IS_I2S
#define IS_I2S(x)
Definition: ald_i2s.h:245
I2S_STATUS_TXE
Definition: ald_i2s.h:159
RESET
Definition: type.h:38
i2s_handle_s::state
i2s_state_t state
Definition: ald_i2s.h:220
i2s_wait_status
static ald_status_t i2s_wait_status(i2s_handle_t *hperh, i2s_status_t state, flag_status_t status, uint32_t timeout)
This function wait I2S status until timeout.
Definition: ald_i2s.c:882
i2s_handle_s::err_code
uint32_t err_code
Definition: ald_i2s.h:222
i2s_init_t::mck_en
type_func_t mck_en
Definition: ald_i2s.h:199
I2S_STATE_BUSY_TX
Definition: ald_i2s.h:148
I2S_ERROR_NONE
Definition: ald_i2s.h:94
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
TIMEOUT
Definition: utils.h:58
I2S_STATE_READY
Definition: ald_i2s.h:146
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
ERROR
Definition: utils.h:56
i2s_handle_s::init
i2s_init_t init
Definition: ald_i2s.h:208
I2S_DISABLE
#define I2S_DISABLE(x)
Definition: ald_i2s.h:237
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207

◆ ald_i2s_master_send_by_dma()

ald_status_t ald_i2s_master_send_by_dma | ( | i2s_handle_t * | hperh,
 |  | uint16_t * | buf,
 |  | uint32_t | size,
 |  | uint8_t | channel
 | ) |  |

Master mode transmit an amount of data used dma channel.

Parameters
hperh | Pointer to a i2s_handle_t structure.
buf | Pointer to data buffer
size | Amount of data to be sent
channel | DMA channel as I2S transmit
Return values
Status,see ald_status_t.

Definition at line 432 of file ald_i2s.c.

433 {
434 assert_param(IS_I2S(hperh->perh));
435
436 if (hperh->state != I2S_STATE_READY)
437 return BUSY;
438 if (buf == NULL || size == 0)
439 return ERROR;
440
441 hperh->state = I2S_STATE_BUSY_TX;
442 hperh->err_code = I2S_ERROR_NONE;
443 hperh->tx_buf = buf;
444 hperh->tx_size = size;
445 hperh->tx_count = size;
446 hperh->rx_buf = NULL;
447 hperh->rx_size = 0;
448 hperh->rx_count = 0;
449
450 WRITE_REG(hperh->perh->ICR, 0xffffffff);
451
452 I2S_DISABLE(hperh);
453
454 MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS);
455
456 if (hperh->init.mck_en)
457 MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS);
458
459 hperh->hdmatx.cplt_arg = (void *)hperh;
460 hperh->hdmatx.cplt_cbk = i2s_dma_send_cplt;
461 hperh->hdmatx.err_arg = (void *)hperh;
462 hperh->hdmatx.err_cbk = i2s_dma_error;
463
464 /* Configure I2S DMA transmit */
465 ald_dma_config_struct(&(hperh->hdmatx.config));
466 hperh->hdmatx.perh = DMA0;
467 hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD;
468 hperh->hdmatx.config.src = (void *)buf;
469 hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA;
470 hperh->hdmatx.config.size = size;
471 hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD;
472 hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
473 hperh->hdmatx.config.msel = hperh->perh == I2S0 ? DMA_MSEL_SPI0 : (hperh->perh == I2S1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2);
474 hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY;
475 hperh->hdmatx.config.channel = channel;
476 hperh->hdmatx.config.burst = ENABLE;
477 ald_dma_config_basic(&(hperh->hdmatx));
478 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, ENABLE);
479
480 if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0)
481 I2S_ENABLE(hperh);
482
483 return OK;
484 }
I2S_MASTER_TRANSMIT
Definition: ald_i2s.h:78
DMA_MSEL_SPI1
Definition: ald_dma.h:91
I2S_ENABLE
#define I2S_ENABLE(x)
Definition: ald_i2s.h:236
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
i2s_dma_error
static void i2s_dma_error(void *arg)
DMA I2S communication error callback.
Definition: ald_i2s.c:1033
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
ald_i2s_dma_req_config
void ald_i2s_dma_req_config(i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t state)
Enables or disables the dma request.
Definition: ald_i2s.c:709
DMA_MSEL_SPI2
Definition: ald_dma.h:99
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
i2s_handle_s::rx_buf
uint16_t * rx_buf
Definition: ald_i2s.h:212
IS_I2S
#define IS_I2S(x)
Definition: ald_i2s.h:245
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
i2s_handle_s::state
i2s_state_t state
Definition: ald_i2s.h:220
i2s_handle_s::err_code
uint32_t err_code
Definition: ald_i2s.h:222
i2s_handle_s::tx_size
uint32_t tx_size
Definition: ald_i2s.h:210
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
i2s_init_t::mck_en
type_func_t mck_en
Definition: ald_i2s.h:199
I2S_STATE_BUSY_TX
Definition: ald_i2s.h:148
I2S_ERROR_NONE
Definition: ald_i2s.h:94
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
I2S_DMA_REQ_TX
Definition: ald_i2s.h:123
i2s_handle_s::tx_buf
uint16_t * tx_buf
Definition: ald_i2s.h:209
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
i2s_handle_s::rx_count
uint32_t rx_count
Definition: ald_i2s.h:214
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
i2s_handle_s::hdmatx
dma_handle_t hdmatx
Definition: ald_i2s.h:216
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
I2S_STATE_READY
Definition: ald_i2s.h:146
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
DMA_MSIGSEL_SPI_TXEMPTY
Definition: ald_dma.h:142
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
DMA_MSEL_SPI0
Definition: ald_dma.h:90
i2s_handle_s::tx_count
uint32_t tx_count
Definition: ald_i2s.h:211
ERROR
Definition: utils.h:56
i2s_handle_s::init
i2s_init_t init
Definition: ald_i2s.h:208
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
i2s_dma_send_cplt
static void i2s_dma_send_cplt(void *arg)
DMA I2S transmit process complete callback.
Definition: ald_i2s.c:978
I2S_DISABLE
#define I2S_DISABLE(x)
Definition: ald_i2s.h:237
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207
i2s_handle_s::rx_size
uint32_t rx_size
Definition: ald_i2s.h:213

◆ ald_i2s_master_send_by_it()

ald_status_t ald_i2s_master_send_by_it | ( | i2s_handle_t * | hperh,
 |  | uint16_t * | buf,
 |  | uint32_t | size
 | ) |  |

Wraps up master mode transmission in non blocking mode.

Parameters
hperh | pointer to a i2s_handle_t structure.
buf | Pointer to data transmitted buffer
size | Amount of data to be sent
Return values
Status,see ald_status_t.

Definition at line 349 of file ald_i2s.c.

350 {
351 assert_param(IS_I2S(hperh->perh));
352
353 if (hperh->state != I2S_STATE_READY)
354 return BUSY;
355 if (buf == NULL || size == 0)
356 return ERROR;
357
358 hperh->state = I2S_STATE_BUSY_TX;
359 hperh->err_code = I2S_ERROR_NONE;
360 hperh->tx_buf = buf;
361 hperh->tx_size = size;
362 hperh->tx_count = size;
363 hperh->rx_buf = NULL;
364 hperh->rx_size = 0;
365 hperh->rx_count = 0;
366
367 WRITE_REG(hperh->perh->ICR, 0xffffffff);
368
369 I2S_DISABLE(hperh);
370 MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS);
371
372 if (hperh->init.mck_en)
373 MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS);
374 if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0)
375 I2S_ENABLE(hperh);
376
377 ald_i2s_interrupt_config(hperh, I2S_IT_TXE, ENABLE);
378 return OK;
379 }
I2S_MASTER_TRANSMIT
Definition: ald_i2s.h:78
I2S_ENABLE
#define I2S_ENABLE(x)
Definition: ald_i2s.h:236
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
I2S_IT_TXE
Definition: ald_i2s.h:107
i2s_handle_s::rx_buf
uint16_t * rx_buf
Definition: ald_i2s.h:212
IS_I2S
#define IS_I2S(x)
Definition: ald_i2s.h:245
i2s_handle_s::state
i2s_state_t state
Definition: ald_i2s.h:220
i2s_handle_s::err_code
uint32_t err_code
Definition: ald_i2s.h:222
ald_i2s_interrupt_config
void ald_i2s_interrupt_config(i2s_handle_t *hperh, i2s_it_t it, type_func_t state)
Enables or disables the specified I2S interrupts.
Definition: ald_i2s.c:685
i2s_handle_s::tx_size
uint32_t tx_size
Definition: ald_i2s.h:210
i2s_init_t::mck_en
type_func_t mck_en
Definition: ald_i2s.h:199
I2S_STATE_BUSY_TX
Definition: ald_i2s.h:148
I2S_ERROR_NONE
Definition: ald_i2s.h:94
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
i2s_handle_s::tx_buf
uint16_t * tx_buf
Definition: ald_i2s.h:209
i2s_handle_s::rx_count
uint32_t rx_count
Definition: ald_i2s.h:214
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
I2S_STATE_READY
Definition: ald_i2s.h:146
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
i2s_handle_s::tx_count
uint32_t tx_count
Definition: ald_i2s.h:211
ERROR
Definition: utils.h:56
i2s_handle_s::init
i2s_init_t init
Definition: ald_i2s.h:208
I2S_DISABLE
#define I2S_DISABLE(x)
Definition: ald_i2s.h:237
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207
i2s_handle_s::rx_size
uint32_t rx_size
Definition: ald_i2s.h:213


ALD User Manual: Control functions

Functions
Control functions
EASTSOFT ES32F3xx ALD » I2S » I2S Public Functions

I2S Control functions. More...

Collaboration diagram for Control functions:

Functions

void | ald_i2s_irq_handler (i2s_handle_t *hperh)
This function handles I2S interrupt request. More...
void | ald_i2s_interrupt_config (i2s_handle_t *hperh, i2s_it_t it, type_func_t state)
Enables or disables the specified I2S interrupts. More...
void | ald_i2s_dma_req_config (i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t state)
Enables or disables the dma request. More...
flag_status_t | ald_i2s_get_status (i2s_handle_t *hperh, i2s_status_t status)
Check whether the specified I2S flag is set or not. More...
it_status_t | ald_i2s_get_it_status (i2s_handle_t *hperh, i2s_it_t it)
Checks whether the specified I2S interrupt has occurred or not. More...
flag_status_t | ald_i2s_get_flag_status (i2s_handle_t *hperh, i2s_flag_t flag)
Check whether the specified I2S interrupt flag is set or not. More...
flag_status_t | ald_i2s_get_mask_flag_status (i2s_handle_t *hperh, i2s_flag_t flag)
Check whether the specified I2S interrupt flag is set or not. More...
void | ald_i2s_clear_flag_status (i2s_handle_t *hperh, i2s_flag_t flag)
Clear the specified I2S interrupt flags. More...

Detailed Description

I2S Control functions.

===============================================================================
                   ##### Peripheral Control functions #####
===============================================================================
 [..]
 This subsection provides a set of functions allowing to control the I2S.
  (+) Handle interrupt about I2S module. The ald_i2s_irq_handler() function must
      be invoked by I2S-IRQ function.
  (+) Configure the interrupt DISABLE/ENABLE.
  (+) Configure the DMA request.
  (+) Get interrupt source status.
  (+) Get interrupt flag status.
  (+) Clear interrupt flag

Function Documentation

◆ ald_i2s_clear_flag_status()

void ald_i2s_clear_flag_status | ( | i2s_handle_t * | hperh,
 |  | i2s_flag_t | flag
 | ) |  |

Clear the specified I2S interrupt flags.

Parameters
hperh | Pointer to a i2s_handle_t structure.
flag | specifies the flag to check. This parameter can be one of the i2s_flag_t.
Return values
None

Definition at line 814 of file ald_i2s.c.

815 {
816 assert_param(IS_I2S(hperh->perh));
817 assert_param(IS_I2S_IF(flag));
818
819 hperh->perh->ICR = flag;
820 return;
821 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_I2S_IF
#define IS_I2S_IF(x)
Definition: ald_i2s.h:271
IS_I2S
#define IS_I2S(x)
Definition: ald_i2s.h:245
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207

◆ ald_i2s_dma_req_config()

void ald_i2s_dma_req_config | ( | i2s_handle_t * | hperh,
 |  | i2s_dma_req_t | req,
 |  | type_func_t | state
 | ) |  |

Enables or disables the dma request.

Parameters
hperh | Pointer to a i2s_handle_t structure.
req | Specifies the I2S dma request sources to be enabled or disabled. This parameter can be one of the i2s_dma_req_t.
state New status
  • ENABLE
  • DISABLE
Return values
None

Definition at line 709 of file ald_i2s.c.

710 {
711 assert_param(IS_I2S(hperh->perh));
712 assert_param(IS_I2S_DMA_REQ(req));
713 assert_param(IS_FUNC_STATE(state));
714
715 if (state == ENABLE) {
716 if (req == I2S_DMA_REQ_TX)
717 SET_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK);
718 else
719 SET_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK);
720 }
721 else {
722 if (req == I2S_DMA_REQ_TX)
723 CLEAR_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK);
724 else
725 CLEAR_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK);
726 }
727
728 return;
729 }
ENABLE
Definition: type.h:49
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_I2S
#define IS_I2S(x)
Definition: ald_i2s.h:245
IS_I2S_DMA_REQ
#define IS_I2S_DMA_REQ(x)
Definition: ald_i2s.h:299
I2S_DMA_REQ_TX
Definition: ald_i2s.h:123
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207

◆ ald_i2s_get_flag_status()

flag_status_t ald_i2s_get_flag_status | ( | i2s_handle_t * | hperh,
 |  | i2s_flag_t | flag
 | ) |  |

Check whether the specified I2S interrupt flag is set or not.

Parameters
hperh | Pointer to a i2s_handle_t structure.
flag | specifies the flag to check. This parameter can be one of the i2s_flag_t.
Return values
Status
  • SET
  • RESET

Definition at line 778 of file ald_i2s.c.

779 {
780 assert_param(IS_I2S(hperh->perh));
781 assert_param(IS_I2S_IF(flag));
782
783 if (hperh->perh->RIF & flag)
784 return SET;
785
786 return RESET;
787 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
IS_I2S_IF
#define IS_I2S_IF(x)
Definition: ald_i2s.h:271
IS_I2S
#define IS_I2S(x)
Definition: ald_i2s.h:245
RESET
Definition: type.h:38
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207

◆ ald_i2s_get_it_status()

it_status_t ald_i2s_get_it_status | ( | i2s_handle_t * | hperh,
 |  | i2s_it_t | it
 | ) |  |

Checks whether the specified I2S interrupt has occurred or not.

Parameters
hperh | Pointer to a i2s_handle_t structure.
it | Specifies the I2S interrupt source to check. This parameter can be one of the i2s_it_t.
Return values
Status
  • SET
  • RESET

Definition at line 759 of file ald_i2s.c.

760 {
761 assert_param(IS_I2S(hperh->perh));
762 assert_param(IS_I2S_IT(it));
763
764 if (hperh->perh->IVS & it)
765 return SET;
766
767 return RESET;
768 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
IS_I2S_IT
#define IS_I2S_IT(x)
Definition: ald_i2s.h:261
IS_I2S
#define IS_I2S(x)
Definition: ald_i2s.h:245
RESET
Definition: type.h:38
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207

◆ ald_i2s_get_mask_flag_status()

flag_status_t ald_i2s_get_mask_flag_status | ( | i2s_handle_t * | hperh,
 |  | i2s_flag_t | flag
 | ) |  |

Check whether the specified I2S interrupt flag is set or not.

Parameters
hperh | Pointer to a i2s_handle_t structure.
flag | specifies the flag to check. This parameter can be one of the i2s_flag_t.
Return values
Status
  • SET
  • RESET

Definition at line 797 of file ald_i2s.c.

798 {
799 assert_param(IS_I2S(hperh->perh));
800 assert_param(IS_I2S_IF(flag));
801
802 if (hperh->perh->IFM & flag)
803 return SET;
804
805 return RESET;
806 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
IS_I2S_IF
#define IS_I2S_IF(x)
Definition: ald_i2s.h:271
IS_I2S
#define IS_I2S(x)
Definition: ald_i2s.h:245
RESET
Definition: type.h:38
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207

◆ ald_i2s_get_status()

flag_status_t ald_i2s_get_status | ( | i2s_handle_t * | hperh,
 |  | i2s_status_t | status
 | ) |  |

Check whether the specified I2S flag is set or not.

Parameters
hperh | Pointer to a i2s_handle_t structure.
status | specifies the flag to check. This parameter can be one of the i2s_status_t.
Return values
Status
  • SET
  • RESET

Definition at line 739 of file ald_i2s.c.

740 {
741 assert_param(IS_I2S(hperh->perh));
742 assert_param(IS_I2S_STATUS(status));
743
744 if (hperh->perh->STAT & status)
745 return SET;
746
747 return RESET;
748 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
IS_I2S
#define IS_I2S(x)
Definition: ald_i2s.h:245
RESET
Definition: type.h:38
IS_I2S_STATUS
#define IS_I2S_STATUS(x)
Definition: ald_i2s.h:289
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207

◆ ald_i2s_interrupt_config()

void ald_i2s_interrupt_config | ( | i2s_handle_t * | hperh,
 |  | i2s_it_t | it,
 |  | type_func_t | state
 | ) |  |

Enables or disables the specified I2S interrupts.

Parameters
hperh | Pointer to a i2s_handle_t structure.
it | Specifies the I2S interrupt sources to be enabled or disabled. This parameter can be one of the i2s_it_t.
state New status
  • ENABLE
  • DISABLE
Return values
None

Definition at line 685 of file ald_i2s.c.

686 {
687 assert_param(IS_I2S(hperh->perh));
688 assert_param(IS_I2S_IT(it));
689 assert_param(IS_FUNC_STATE(state));
690
691 if (state == ENABLE)
692 hperh->perh->IER = (uint32_t)it;
693 else
694 hperh->perh->IDR = (uint32_t)it;
695
696 return;
697 }
ENABLE
Definition: type.h:49
assert_param
#define assert_param(x)
Definition: type.h:88
IS_I2S_IT
#define IS_I2S_IT(x)
Definition: ald_i2s.h:261
IS_I2S
#define IS_I2S(x)
Definition: ald_i2s.h:245
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207

◆ ald_i2s_irq_handler()

void ald_i2s_irq_handler ( i2s_handle_t * hperh )

This function handles I2S interrupt request.

Parameters
hperh Pointer to a i2s_handle_t structure.
Return values
None

Definition at line 646 of file ald_i2s.c.

647 {
648 if (ald_i2s_get_mask_flag_status(hperh, I2S_IF_RXTH) == SET) {
649 ald_i2s_clear_flag_status(hperh, I2S_IF_RXTH);
650 if ((hperh->state == I2S_STATE_BUSY_TX_RX) || (hperh->state == I2S_STATE_BUSY_RX))
651 __i2s_recv_by_it(hperh);
652 }
653
654 if (ald_i2s_get_mask_flag_status(hperh, I2S_IF_TXE) == SET) {
655 ald_i2s_clear_flag_status(hperh, I2S_IF_TXE);
656 if (hperh->state == I2S_STATE_BUSY_TX)
657 __i2s_send_by_it(hperh);
658 else if (hperh->state == I2S_STATE_BUSY_TX_RX)
659 __i2s_tx_recv_by_it(hperh);
660
661 }
662
663 if (hperh->err_code != I2S_ERROR_NONE) {
664 ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, DISABLE);
665 ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE);
666 hperh->state = I2S_STATE_READY;
667
668 if (hperh->err_cbk)
669 hperh->err_cbk(hperh);
670 }
671
672 return;
673 }
__i2s_send_by_it
static void __i2s_send_by_it(i2s_handle_t *hperh)
handle program when an tx empty interrupt flag arrived in non block mode
Definition: ald_i2s.c:904
SET
Definition: type.h:39
I2S_IT_RXTH
Definition: ald_i2s.h:113
DISABLE
Definition: type.h:48
I2S_IT_TXE
Definition: ald_i2s.h:107
__i2s_tx_recv_by_it
static void __i2s_tx_recv_by_it(i2s_handle_t *hperh)
handle program when an rx no empty interrupt flag arrived in non block mode
Definition: ald_i2s.c:960
I2S_STATE_BUSY_TX_RX
Definition: ald_i2s.h:150
i2s_handle_s::state
i2s_state_t state
Definition: ald_i2s.h:220
i2s_handle_s::err_cbk
void(* err_cbk)(struct i2s_handle_s *arg)
Definition: ald_i2s.h:226
I2S_IF_RXTH
Definition: ald_i2s.h:137
i2s_handle_s::err_code
uint32_t err_code
Definition: ald_i2s.h:222
ald_i2s_interrupt_config
void ald_i2s_interrupt_config(i2s_handle_t *hperh, i2s_it_t it, type_func_t state)
Enables or disables the specified I2S interrupts.
Definition: ald_i2s.c:685
__i2s_recv_by_it
static void __i2s_recv_by_it(i2s_handle_t *hperh)
handle program when an rx no empty interrupt flag arrived in non block mode
Definition: ald_i2s.c:939
I2S_STATE_BUSY_TX
Definition: ald_i2s.h:148
I2S_STATE_BUSY_RX
Definition: ald_i2s.h:149
I2S_ERROR_NONE
Definition: ald_i2s.h:94
I2S_IF_TXE
Definition: ald_i2s.h:131
ald_i2s_clear_flag_status
void ald_i2s_clear_flag_status(i2s_handle_t *hperh, i2s_flag_t flag)
Clear the specified I2S interrupt flags.
Definition: ald_i2s.c:814
ald_i2s_get_mask_flag_status
flag_status_t ald_i2s_get_mask_flag_status(i2s_handle_t *hperh, i2s_flag_t flag)
Check whether the specified I2S interrupt flag is set or not.
Definition: ald_i2s.c:797
I2S_STATE_READY
Definition: ald_i2s.h:146


ALD User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
EASTSOFT ES32F3xx ALD » I2S » I2S Public Functions

I2S State and Errors functions. More...

Collaboration diagram for Peripheral State and Errors functions:

Functions

i2s_state_t | ald_i2s_get_state (i2s_handle_t *hperh)
Returns the I2S state. More...
uint32_t | ald_i2s_get_error (i2s_handle_t *hperh)
Return the I2S error code. More...

Detailed Description

I2S State and Errors functions.

===============================================================================
                     ##### Peripheral State and Errors functions #####
===============================================================================
   [..]
   This subsection provides a set of functions allowing to control the I2S.
    (+) ald_i2s_get_state() API can check in run-time the state of the I2S peripheral
    (+) ald_i2s_get_error() check in run-time Errors occurring during communication

Function Documentation

◆ ald_i2s_get_error()

uint32_t ald_i2s_get_error ( i2s_handle_t * hperh )

Return the I2S error code.

Parameters
hperh Pointer to a i2s_handle_t structure.
Return values
I2S Error Code

Definition at line 858 of file ald_i2s.c.

859 {
860 assert_param(IS_I2S(hperh->perh));
861 return hperh->err_code;
862 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_I2S
#define IS_I2S(x)
Definition: ald_i2s.h:245
i2s_handle_s::err_code
uint32_t err_code
Definition: ald_i2s.h:222
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207

◆ ald_i2s_get_state()

i2s_state_t ald_i2s_get_state ( i2s_handle_t * hperh )

Returns the I2S state.

Parameters
hperh Pointer to a i2s_handle_t structure.
Return values
Status,see i2s_state_t.

Definition at line 847 of file ald_i2s.c.

848 {
849 assert_param(IS_I2S(hperh->perh));
850 return hperh->state;
851 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_I2S
#define IS_I2S(x)
Definition: ald_i2s.h:245
i2s_handle_s::state
i2s_state_t state
Definition: ald_i2s.h:220
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207


ALD User Manual: I2S Private Functions

Functions
I2S Private Functions
EASTSOFT ES32F3xx ALD » I2S

I2S Private functions. More...

Collaboration diagram for I2S Private Functions:

Functions

static ald_status_t | i2s_wait_status (i2s_handle_t *hperh, i2s_status_t flag, flag_status_t status, uint32_t timeout)
This function wait I2S status until timeout. More...
static void | __i2s_send_by_it (i2s_handle_t *hperh)
handle program when an tx empty interrupt flag arrived in non block mode More...
static void | __i2s_recv_by_it (i2s_handle_t *hperh)
handle program when an rx no empty interrupt flag arrived in non block mode More...
static void | __i2s_tx_recv_by_it (i2s_handle_t *hperh)
handle program when an rx no empty interrupt flag arrived in non block mode More...
static void | i2s_dma_send_cplt (void *arg)
DMA I2S transmit process complete callback. More...
static void | i2s_dma_recv_cplt (void *arg)
DMA I2S receive process complete callback. More...
static void | i2s_dma_error (void *arg)
DMA I2S communication error callback. More...

Detailed Description

I2S Private functions.

Function Documentation

◆ __i2s_recv_by_it()

static void __i2s_recv_by_it ( i2s_handle_t * hperh )
static

handle program when an rx no empty interrupt flag arrived in non block mode

Parameters
hperh Pointer to a i2s_handle_t structure.
Return values
None.

Definition at line 939 of file ald_i2s.c.

940 {
941 *(hperh->rx_buf++) = hperh->perh->DATA;
942 --hperh->rx_count;
943
944 if (hperh->rx_count == 0) {
945 ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, DISABLE);
946 hperh->state = I2S_STATE_READY;
947
948 if (hperh->rx_cplt_cbk)
949 hperh->rx_cplt_cbk(hperh);
950 }
951
952 return;
953 }
I2S_IT_RXTH
Definition: ald_i2s.h:113
DISABLE
Definition: type.h:48
i2s_handle_s::rx_buf
uint16_t * rx_buf
Definition: ald_i2s.h:212
i2s_handle_s::rx_cplt_cbk
void(* rx_cplt_cbk)(struct i2s_handle_s *arg)
Definition: ald_i2s.h:225
i2s_handle_s::state
i2s_state_t state
Definition: ald_i2s.h:220
ald_i2s_interrupt_config
void ald_i2s_interrupt_config(i2s_handle_t *hperh, i2s_it_t it, type_func_t state)
Enables or disables the specified I2S interrupts.
Definition: ald_i2s.c:685
i2s_handle_s::rx_count
uint32_t rx_count
Definition: ald_i2s.h:214
I2S_STATE_READY
Definition: ald_i2s.h:146
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207

◆ __i2s_send_by_it()

static void __i2s_send_by_it ( i2s_handle_t * hperh )
static

handle program when an tx empty interrupt flag arrived in non block mode

Parameters
hperh Pointer to a i2s_handle_t structure.
Return values
None.

Definition at line 904 of file ald_i2s.c.

905 {
906 int cnt = 8000;
907
908 if (hperh->tx_count == 0) {
909 ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE);
910 hperh->state = I2S_STATE_READY;
911
912 while ((hperh->perh->STAT & SPI_STAT_BUSY_MSK) && (--cnt));
913 if (cnt == 0) {
914 if (hperh->err_cbk)
915 hperh->err_cbk(hperh);
916
917 ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, DISABLE);
918 return;
919 }
920
921 if (hperh->tx_cplt_cbk)
922 hperh->tx_cplt_cbk(hperh);
923
924 return;
925 }
926
927 hperh->side = READ_BITS(hperh->perh->STAT, SPI_STAT_CHSIDE_MSK, SPI_STAT_CHSIDE_POS);
928 hperh->perh->DATA = *hperh->tx_buf++;
929 --hperh->tx_count;
930
931 return;
932 }
i2s_handle_s::side
uint8_t side
Definition: ald_i2s.h:221
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
I2S_IT_RXTH
Definition: ald_i2s.h:113
DISABLE
Definition: type.h:48
I2S_IT_TXE
Definition: ald_i2s.h:107
i2s_handle_s::state
i2s_state_t state
Definition: ald_i2s.h:220
i2s_handle_s::err_cbk
void(* err_cbk)(struct i2s_handle_s *arg)
Definition: ald_i2s.h:226
ald_i2s_interrupt_config
void ald_i2s_interrupt_config(i2s_handle_t *hperh, i2s_it_t it, type_func_t state)
Enables or disables the specified I2S interrupts.
Definition: ald_i2s.c:685
i2s_handle_s::tx_cplt_cbk
void(* tx_cplt_cbk)(struct i2s_handle_s *arg)
Definition: ald_i2s.h:224
i2s_handle_s::tx_buf
uint16_t * tx_buf
Definition: ald_i2s.h:209
I2S_STATE_READY
Definition: ald_i2s.h:146
i2s_handle_s::tx_count
uint32_t tx_count
Definition: ald_i2s.h:211
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207

◆ __i2s_tx_recv_by_it()

static void __i2s_tx_recv_by_it ( i2s_handle_t * hperh )
static

handle program when an rx no empty interrupt flag arrived in non block mode

Parameters
hperh Pointer to a i2s_handle_t structure.
Return values
None.

Definition at line 960 of file ald_i2s.c.

961 {
962 if (hperh->tx_count != 0) {
963 ald_i2s_clear_flag_status(hperh, I2S_IF_TXE);
964 hperh->perh->DATA = 0xffff;
965 // while(ald_i2s_get_status(hperh, I2S_STATUS_RXE) == SET);
966 --hperh->tx_count;
967 if (hperh->tx_count == 0)
968 ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE);
969 }
970 }
DISABLE
Definition: type.h:48
I2S_IT_TXE
Definition: ald_i2s.h:107
ald_i2s_interrupt_config
void ald_i2s_interrupt_config(i2s_handle_t *hperh, i2s_it_t it, type_func_t state)
Enables or disables the specified I2S interrupts.
Definition: ald_i2s.c:685
I2S_IF_TXE
Definition: ald_i2s.h:131
ald_i2s_clear_flag_status
void ald_i2s_clear_flag_status(i2s_handle_t *hperh, i2s_flag_t flag)
Clear the specified I2S interrupt flags.
Definition: ald_i2s.c:814
i2s_handle_s::tx_count
uint32_t tx_count
Definition: ald_i2s.h:211
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207

◆ i2s_dma_error()

static void i2s_dma_error ( void * arg )
static

DMA I2S communication error callback.

Parameters
arg Pointer to a void structure.
Return values
None

Definition at line 1033 of file ald_i2s.c.

1034 {
1035 i2s_handle_t *hperh = (i2s_handle_t *)arg;
1036
1037 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, DISABLE);
1038 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, DISABLE);
1039 SET_BIT(hperh->err_code, I2S_ERROR_DMA);
1040
1041 hperh->tx_count = 0;
1042 hperh->rx_count = 0;
1043 hperh->state = I2S_STATE_READY;
1044
1045 if (hperh->err_cbk)
1046 hperh->err_cbk(hperh);
1047
1048 return;
1049 }
ald_i2s_dma_req_config
void ald_i2s_dma_req_config(i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t state)
Enables or disables the dma request.
Definition: ald_i2s.c:709
DISABLE
Definition: type.h:48
i2s_handle_s::state
i2s_state_t state
Definition: ald_i2s.h:220
i2s_handle_s::err_cbk
void(* err_cbk)(struct i2s_handle_s *arg)
Definition: ald_i2s.h:226
i2s_handle_s::err_code
uint32_t err_code
Definition: ald_i2s.h:222
I2S_ERROR_DMA
Definition: ald_i2s.h:96
I2S_DMA_REQ_TX
Definition: ald_i2s.h:123
i2s_handle_s::rx_count
uint32_t rx_count
Definition: ald_i2s.h:214
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
I2S_STATE_READY
Definition: ald_i2s.h:146
i2s_handle_s
I2S handle structure definition.
Definition: ald_i2s.h:206
I2S_DMA_REQ_RX
Definition: ald_i2s.h:124
i2s_handle_s::tx_count
uint32_t tx_count
Definition: ald_i2s.h:211

◆ i2s_dma_recv_cplt()

static void i2s_dma_recv_cplt ( void * arg )
static

DMA I2S receive process complete callback.

Parameters
arg Pointer to a void structure.
Return values
None

Definition at line 1008 of file ald_i2s.c.

1009 {
1010 i2s_handle_t *hperh = (i2s_handle_t *)arg;
1011
1012 hperh->rx_count = 0;
1013 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, DISABLE);
1014 hperh->state = I2S_STATE_READY;
1015
1016 if (hperh->err_code == I2S_ERROR_NONE) {
1017 if (hperh->rx_cplt_cbk)
1018 hperh->rx_cplt_cbk(hperh);
1019 }
1020 else {
1021 if (hperh->err_cbk)
1022 hperh->err_cbk(hperh);
1023 }
1024
1025 return;
1026 }
ald_i2s_dma_req_config
void ald_i2s_dma_req_config(i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t state)
Enables or disables the dma request.
Definition: ald_i2s.c:709
DISABLE
Definition: type.h:48
i2s_handle_s::rx_cplt_cbk
void(* rx_cplt_cbk)(struct i2s_handle_s *arg)
Definition: ald_i2s.h:225
i2s_handle_s::state
i2s_state_t state
Definition: ald_i2s.h:220
i2s_handle_s::err_cbk
void(* err_cbk)(struct i2s_handle_s *arg)
Definition: ald_i2s.h:226
i2s_handle_s::err_code
uint32_t err_code
Definition: ald_i2s.h:222
I2S_ERROR_NONE
Definition: ald_i2s.h:94
i2s_handle_s::rx_count
uint32_t rx_count
Definition: ald_i2s.h:214
I2S_STATE_READY
Definition: ald_i2s.h:146
i2s_handle_s
I2S handle structure definition.
Definition: ald_i2s.h:206
I2S_DMA_REQ_RX
Definition: ald_i2s.h:124

◆ i2s_dma_send_cplt()

static void i2s_dma_send_cplt ( void * arg )
static

DMA I2S transmit process complete callback.

Parameters
arg Pointer to a void structure.
Return values
None

Definition at line 978 of file ald_i2s.c.

979 {
980 int cnt = 8000;
981 i2s_handle_t *hperh = (i2s_handle_t *)arg;
982
983 hperh->tx_count = 0;
984 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, DISABLE);
985 hperh->state = I2S_STATE_READY;
986
987 while ((hperh->perh->STAT & SPI_STAT_BUSY_MSK) && (--cnt));
988 if (cnt == 0)
989 hperh->err_code |= I2S_ERROR_FLAG;
990
991 if (hperh->err_code == I2S_ERROR_NONE) {
992 if (hperh->tx_cplt_cbk)
993 hperh->tx_cplt_cbk(hperh);
994 }
995 else {
996 if (hperh->err_cbk)
997 hperh->err_cbk(hperh);
998 }
999
1000 return;
1001 }
ald_i2s_dma_req_config
void ald_i2s_dma_req_config(i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t state)
Enables or disables the dma request.
Definition: ald_i2s.c:709
DISABLE
Definition: type.h:48
i2s_handle_s::state
i2s_state_t state
Definition: ald_i2s.h:220
i2s_handle_s::err_cbk
void(* err_cbk)(struct i2s_handle_s *arg)
Definition: ald_i2s.h:226
i2s_handle_s::err_code
uint32_t err_code
Definition: ald_i2s.h:222
i2s_handle_s::tx_cplt_cbk
void(* tx_cplt_cbk)(struct i2s_handle_s *arg)
Definition: ald_i2s.h:224
I2S_ERROR_NONE
Definition: ald_i2s.h:94
I2S_ERROR_FLAG
Definition: ald_i2s.h:100
I2S_DMA_REQ_TX
Definition: ald_i2s.h:123
I2S_STATE_READY
Definition: ald_i2s.h:146
i2s_handle_s
I2S handle structure definition.
Definition: ald_i2s.h:206
i2s_handle_s::tx_count
uint32_t tx_count
Definition: ald_i2s.h:211
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207

◆ i2s_wait_status()

static ald_status_t i2s_wait_status | ( | i2s_handle_t * | hperh,
 |  | i2s_status_t | flag,
 |  | flag_status_t | status,
 |  | uint32_t | timeout
 | ) |  |
static

This function wait I2S status until timeout.

Parameters
hperh | Pointer to a i2s_handle_t structure.
flag | specifies the I2S flag to check.
status | The new Flag status (SET or RESET).
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 882 of file ald_i2s.c.

883 {
884 uint32_t tick = ald_get_tick();
885
886 assert_param(timeout > 0);
887
888 while ((ald_i2s_get_status(hperh, flag)) != status) {
889 if (((ald_get_tick()) - tick) > timeout) {
890 ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE);
891 ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, DISABLE);
892 return TIMEOUT;
893 }
894 }
895
896 return OK;
897 }
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
I2S_IT_RXTH
Definition: ald_i2s.h:113
DISABLE
Definition: type.h:48
I2S_IT_TXE
Definition: ald_i2s.h:107
ald_i2s_interrupt_config
void ald_i2s_interrupt_config(i2s_handle_t *hperh, i2s_it_t it, type_func_t state)
Enables or disables the specified I2S interrupts.
Definition: ald_i2s.c:685
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
ald_i2s_get_status
flag_status_t ald_i2s_get_status(i2s_handle_t *hperh, i2s_status_t status)
Check whether the specified I2S flag is set or not.
Definition: ald_i2s.c:739


ALD User Manual: I2S Public Types

Data Structures | Typedefs | Enumerations
I2S Public Types
EASTSOFT ES32F3xx ALD » I2S
Collaboration diagram for I2S Public Types:

Data Structures

struct | i2s_init_t
I2S init structure definition. More...
struct | i2s_handle_s
I2S handle structure definition. More...

Typedefs

typedef struct i2s_handle_s i2s_handle_t
I2S handle structure definition. More...

Enumerations

enum | i2s_chlen_t { I2S_WIDE_16 = 0x0U, I2S_WIDE_32 = 0x1U }
Channel length. More...
enum | i2s_datalen_t { I2S_LEN_16 = 0x0U, I2S_LEN_24 = 0x1U, I2S_LEN_32 = 0x2U }
Data length. More...
enum | i2s_cpol_t { I2S_INACTIVE_LOW = 0x0U, I2S_INACTIVE_HIGH = 0x1U }
Inactive state clock polarity. More...
enum | i2s_standard_t { I2S_STD_PHI = 0x0U, I2S_STD_MSB = 0x1U, I2S_STD_LSB = 0x2U, I2S_STD_PCM = 0x3U }
I2s standard. More...
enum | i2s_cfg_t { I2S_MASTER_TRANSMIT = 0x2U, I2S_MASTER_RECEIVE = 0x3U }
I2s configuration mode. More...
enum | i2s_pcms_t { I2S_FRAME_SHORT = 0x0U, I2S_FRAME_LONG = 0x1U }
Pcm frame synchronization. More...
enum i2s_error_t {
I2S_ERROR_NONE = 0x0U, I2S_ERROR_MODF = 0x1U, I2S_ERROR_DMA = 0x2U, I2S_ERROR_FRE = 0x4U,
I2S_ERROR_RXOV = 0x8U, I2S_ERROR_TXOV = 0x10U, I2S_ERROR_FLAG = 0x20U
}
I2S error status. More...
enum i2s_it_t {
I2S_IT_TXE = (1U << 0), I2S_IT_TXOV = (1U << 2), I2S_IT_TXUD = (1U << 3), I2S_IT_RXF = (1U << 9),
I2S_IT_RXOV = (1U << 10), I2S_IT_RXUD = (1U << 11), I2S_IT_RXTH = (1U << 12), I2S_IT_CRCERR = (1U << 16),
I2S_IT_MODF = (1U << 17), I2S_IT_FRE = (1U << 18)
}
interrupt control More...
enum | i2s_dma_req_t { I2S_DMA_REQ_TX = 0U, I2S_DMA_REQ_RX = 1U }
I2S dma request definition. More...
enum i2s_flag_t {
I2S_IF_TXE = (1U << 0), I2S_IF_TXOV = (1U << 2), I2S_IF_TXUD = (1U << 3), I2S_IF_RXF = (1U << 9),
I2S_IF_RXOV = (1U << 10), I2S_IF_RXUD = (1U << 11), I2S_IF_RXTH = (1U << 12), I2S_IF_FRE = (1U << 18)
}
interrupt flag More...
enum i2s_state_t {
I2S_STATE_RESET = 0x00U, I2S_STATE_READY = 0x01U, I2S_STATE_BUSY = 0x02U, I2S_STATE_BUSY_TX = 0x11U,
I2S_STATE_BUSY_RX = 0x21U, I2S_STATE_BUSY_TX_RX = 0x31U, I2S_STATE_TIMEOUT = 0x03U, I2S_STATE_ERROR = 0x04U
}
I2S state structures definition. More...
enum i2s_status_t {
I2S_STATUS_TXE = (1U << 0), I2S_STATUS_TXF = (1U << 1), I2S_STATUS_TXOV = (1U << 2), I2S_STATUS_TXUD = (1U << 3),
I2S_STATUS_RXE = (1U << 8), I2S_STATUS_RXF = (1U << 9), I2S_STATUS_RXOV = (1U << 10), I2S_STATUS_RXUD = (1U << 11),
I2S_STATUS_CHSIDE = (1U << 14), I2S_STATUS_BUSY = (1U << 15)
}
I2S status definition. More...
enum | i2s_ch_side_t { I2S_SIDE_LEFT = 0U, I2S_SIDE_RIGHT = 1U }
Channel side. More...
enum | i2s_sr_status_t { I2S_SR_TXE = 0U, I2S_SR_RXNE = 1U, I2S_SR_TXE_RXNE = 2U }
I2S TXE/RXNE status definition. More...

Detailed Description

Typedef Documentation

◆ i2s_handle_t

typedef struct i2s_handle_s i2s_handle_t

I2S handle structure definition.

Enumeration Type Documentation

◆ i2s_cfg_t

enum i2s_cfg_t

I2s configuration mode.

Enumerator
I2S_MASTER_TRANSMIT | I2S master transmit mode
I2S_MASTER_RECEIVE | I2S master receive mode

Definition at line 77 of file ald_i2s.h.

77 {
78 I2S_MASTER_TRANSMIT = 0x2U,
79 I2S_MASTER_RECEIVE = 0x3U,
80 } i2s_cfg_t;
I2S_MASTER_TRANSMIT
Definition: ald_i2s.h:78
i2s_cfg_t
i2s_cfg_t
I2s configuration mode.
Definition: ald_i2s.h:77
I2S_MASTER_RECEIVE
Definition: ald_i2s.h:79

◆ i2s_ch_side_t

enum i2s_ch_side_t

Channel side.

Enumerator
I2S_SIDE_LEFT | Sound channel is left
I2S_SIDE_RIGHT | Sound channel is right

Definition at line 174 of file ald_i2s.h.

174 {
175 I2S_SIDE_LEFT = 0U,
176 I2S_SIDE_RIGHT = 1U,
177 } i2s_ch_side_t;
i2s_ch_side_t
i2s_ch_side_t
Channel side.
Definition: ald_i2s.h:174
I2S_SIDE_LEFT
Definition: ald_i2s.h:175
I2S_SIDE_RIGHT
Definition: ald_i2s.h:176

◆ i2s_chlen_t

enum i2s_chlen_t

Channel length.

Enumerator
I2S_WIDE_16 | Channel length is 16
I2S_WIDE_32 | Channel length is 32

Definition at line 42 of file ald_i2s.h.

42 {
43 I2S_WIDE_16 = 0x0U,
44 I2S_WIDE_32 = 0x1U,
45 } i2s_chlen_t;
i2s_chlen_t
i2s_chlen_t
Channel length.
Definition: ald_i2s.h:42
I2S_WIDE_16
Definition: ald_i2s.h:43
I2S_WIDE_32
Definition: ald_i2s.h:44

◆ i2s_cpol_t

enum i2s_cpol_t

Inactive state clock polarity.

Enumerator
I2S_INACTIVE_LOW | Inactive state is low
I2S_INACTIVE_HIGH | Inactive state is high

Definition at line 59 of file ald_i2s.h.

59 {
60 I2S_INACTIVE_LOW = 0x0U,
61 I2S_INACTIVE_HIGH = 0x1U,
62 } i2s_cpol_t;
I2S_INACTIVE_LOW
Definition: ald_i2s.h:60
I2S_INACTIVE_HIGH
Definition: ald_i2s.h:61
i2s_cpol_t
i2s_cpol_t
Inactive state clock polarity.
Definition: ald_i2s.h:59

◆ i2s_datalen_t

enum i2s_datalen_t

Data length.

Enumerator
I2S_LEN_16 | Data length is 16
I2S_LEN_24 | Data length is 24
I2S_LEN_32 | Data length is 32

Definition at line 50 of file ald_i2s.h.

50 {
51 I2S_LEN_16 = 0x0U,
52 I2S_LEN_24 = 0x1U,
53 I2S_LEN_32 = 0x2U,
54 } i2s_datalen_t;
I2S_LEN_16
Definition: ald_i2s.h:51
I2S_LEN_24
Definition: ald_i2s.h:52
i2s_datalen_t
i2s_datalen_t
Data length.
Definition: ald_i2s.h:50
I2S_LEN_32
Definition: ald_i2s.h:53

◆ i2s_dma_req_t

enum i2s_dma_req_t

I2S dma request definition.

Enumerator
I2S_DMA_REQ_TX | TX dma request
I2S_DMA_REQ_RX | RX dma request

Definition at line 122 of file ald_i2s.h.

122 {
123 I2S_DMA_REQ_TX = 0U,
124 I2S_DMA_REQ_RX = 1U,
125 } i2s_dma_req_t;
I2S_DMA_REQ_TX
Definition: ald_i2s.h:123
I2S_DMA_REQ_RX
Definition: ald_i2s.h:124
i2s_dma_req_t
i2s_dma_req_t
I2S dma request definition.
Definition: ald_i2s.h:122

◆ i2s_error_t

enum i2s_error_t

I2S error status.

Enumerator
I2S_ERROR_NONE | none
I2S_ERROR_MODF | mode fault
I2S_ERROR_DMA | crc error
I2S_ERROR_FRE | frame error
I2S_ERROR_RXOV | receive over error
I2S_ERROR_TXOV | dma error
I2S_ERROR_FLAG | interrupt flag error

Definition at line 93 of file ald_i2s.h.

93 {
94 I2S_ERROR_NONE = 0x0U,
95 I2S_ERROR_MODF = 0x1U,
96 I2S_ERROR_DMA = 0x2U,
97 I2S_ERROR_FRE = 0x4U,
98 I2S_ERROR_RXOV = 0x8U,
99 I2S_ERROR_TXOV = 0x10U,
100 I2S_ERROR_FLAG = 0x20U,
101 } i2s_error_t;
i2s_error_t
i2s_error_t
I2S error status.
Definition: ald_i2s.h:93
I2S_ERROR_RXOV
Definition: ald_i2s.h:98
I2S_ERROR_TXOV
Definition: ald_i2s.h:99
I2S_ERROR_DMA
Definition: ald_i2s.h:96
I2S_ERROR_NONE
Definition: ald_i2s.h:94
I2S_ERROR_FRE
Definition: ald_i2s.h:97
I2S_ERROR_FLAG
Definition: ald_i2s.h:100
I2S_ERROR_MODF
Definition: ald_i2s.h:95

◆ i2s_flag_t

enum i2s_flag_t

interrupt flag

Enumerator
I2S_IF_TXE | Transmit fifo empty interrupt flag
I2S_IF_TXOV | Transmit fifo overflow interrupt flag
I2S_IF_TXUD | Transmit fifo underflow interrupt flag
I2S_IF_RXF | Receive fifo full interrupt flag
I2S_IF_RXOV | Receive fifo overflow interrupt flag
I2S_IF_RXUD | Receive fifo underflow interrupt flag
I2S_IF_RXTH | Receive fifo over threshold interrupt flag
I2S_IF_FRE | Frame error interrupt flag

Definition at line 130 of file ald_i2s.h.

130 {
131 I2S_IF_TXE = (1U << 0),
132 I2S_IF_TXOV = (1U << 2),
133 I2S_IF_TXUD = (1U << 3),
134 I2S_IF_RXF = (1U << 9),
135 I2S_IF_RXOV = (1U << 10),
136 I2S_IF_RXUD = (1U << 11),
137 I2S_IF_RXTH = (1U << 12),
138 I2S_IF_FRE = (1U << 18),
139 } i2s_flag_t;
I2S_IF_RXF
Definition: ald_i2s.h:134
I2S_IF_RXTH
Definition: ald_i2s.h:137
I2S_IF_TXUD
Definition: ald_i2s.h:133
I2S_IF_FRE
Definition: ald_i2s.h:138
I2S_IF_TXE
Definition: ald_i2s.h:131
I2S_IF_RXUD
Definition: ald_i2s.h:136
I2S_IF_RXOV
Definition: ald_i2s.h:135
I2S_IF_TXOV
Definition: ald_i2s.h:132
i2s_flag_t
i2s_flag_t
interrupt flag
Definition: ald_i2s.h:130

◆ i2s_it_t

enum i2s_it_t

interrupt control

Enumerator
I2S_IT_TXE | Transmit fifo empty interrupt
I2S_IT_TXOV | Transmit fifo overflow interrupt
I2S_IT_TXUD | Transmit fifo underflow interrupt
I2S_IT_RXF | Receive fifo full interrupt
I2S_IT_RXOV | Receive fifo overflow interrupt
I2S_IT_RXUD | Receive fifo underflow interrupt
I2S_IT_RXTH | Receive fifo over threshold interrupt
I2S_IT_CRCERR | Crc error interrupt
I2S_IT_MODF | Mode error interrupt
I2S_IT_FRE | Frame error interrupt

Definition at line 106 of file ald_i2s.h.

106 {
107 I2S_IT_TXE = (1U << 0),
108 I2S_IT_TXOV = (1U << 2),
109 I2S_IT_TXUD = (1U << 3),
110 I2S_IT_RXF = (1U << 9),
111 I2S_IT_RXOV = (1U << 10),
112 I2S_IT_RXUD = (1U << 11),
113 I2S_IT_RXTH = (1U << 12),
114 I2S_IT_CRCERR = (1U << 16),
115 I2S_IT_MODF = (1U << 17),
116 I2S_IT_FRE = (1U << 18),
117 } i2s_it_t;
I2S_IT_CRCERR
Definition: ald_i2s.h:114
I2S_IT_RXTH
Definition: ald_i2s.h:113
I2S_IT_RXUD
Definition: ald_i2s.h:112
I2S_IT_TXE
Definition: ald_i2s.h:107
i2s_it_t
i2s_it_t
interrupt control
Definition: ald_i2s.h:106
I2S_IT_RXOV
Definition: ald_i2s.h:111
I2S_IT_MODF
Definition: ald_i2s.h:115
I2S_IT_TXOV
Definition: ald_i2s.h:108
I2S_IT_RXF
Definition: ald_i2s.h:110
I2S_IT_TXUD
Definition: ald_i2s.h:109
I2S_IT_FRE
Definition: ald_i2s.h:116

◆ i2s_pcms_t

enum i2s_pcms_t

Pcm frame synchronization.

Enumerator
I2S_FRAME_SHORT | I2S PCM short frame
I2S_FRAME_LONG | I2S PCM long frame

Definition at line 85 of file ald_i2s.h.

85 {
86 I2S_FRAME_SHORT = 0x0U,
87 I2S_FRAME_LONG = 0x1U,
88 } i2s_pcms_t;
I2S_FRAME_SHORT
Definition: ald_i2s.h:86
i2s_pcms_t
i2s_pcms_t
Pcm frame synchronization.
Definition: ald_i2s.h:85
I2S_FRAME_LONG
Definition: ald_i2s.h:87

◆ i2s_sr_status_t

enum i2s_sr_status_t

I2S TXE/RXNE status definition.

Enumerator
I2S_SR_TXE | STAT TXE set
I2S_SR_RXNE | STAT RXTH set
I2S_SR_TXE_RXNE | STAT TXE and RXTH set

Definition at line 182 of file ald_i2s.h.

182 {
183 I2S_SR_TXE = 0U,
184 I2S_SR_RXNE = 1U,
185 I2S_SR_TXE_RXNE = 2U,
186 } i2s_sr_status_t;
i2s_sr_status_t
i2s_sr_status_t
I2S TXE/RXNE status definition.
Definition: ald_i2s.h:182
I2S_SR_TXE
Definition: ald_i2s.h:183
I2S_SR_RXNE
Definition: ald_i2s.h:184
I2S_SR_TXE_RXNE
Definition: ald_i2s.h:185

◆ i2s_standard_t

enum i2s_standard_t

I2s standard.

Enumerator
I2S_STD_PHI | Philips standard
I2S_STD_MSB | MSB standard
I2S_STD_LSB | LSB standard
I2S_STD_PCM | PCM standard

Definition at line 67 of file ald_i2s.h.

67 {
68 I2S_STD_PHI = 0x0U,
69 I2S_STD_MSB = 0x1U,
70 I2S_STD_LSB = 0x2U,
71 I2S_STD_PCM = 0x3U,
72 } i2s_standard_t;
I2S_STD_PHI
Definition: ald_i2s.h:68
i2s_standard_t
i2s_standard_t
I2s standard.
Definition: ald_i2s.h:67
I2S_STD_PCM
Definition: ald_i2s.h:71
I2S_STD_MSB
Definition: ald_i2s.h:69
I2S_STD_LSB
Definition: ald_i2s.h:70

◆ i2s_state_t

enum i2s_state_t

I2S state structures definition.

Enumerator
I2S_STATE_RESET | Peripheral is not initialized
I2S_STATE_READY | Peripheral Initialized and ready for use
I2S_STATE_BUSY | an internal process is ongoing
I2S_STATE_BUSY_TX | transmit is ongoing
I2S_STATE_BUSY_RX | receive is ongoing
I2S_STATE_BUSY_TX_RX | transmit and receive are ongoing
I2S_STATE_TIMEOUT | Timeout state
I2S_STATE_ERROR | Error

Definition at line 144 of file ald_i2s.h.

144 {
145 I2S_STATE_RESET = 0x00U,
146 I2S_STATE_READY = 0x01U,
147 I2S_STATE_BUSY = 0x02U,
148 I2S_STATE_BUSY_TX = 0x11U,
149 I2S_STATE_BUSY_RX = 0x21U,
150 I2S_STATE_BUSY_TX_RX = 0x31U,
151 I2S_STATE_TIMEOUT = 0x03U,
152 I2S_STATE_ERROR = 0x04U,
153 } i2s_state_t;
I2S_STATE_BUSY
Definition: ald_i2s.h:147
I2S_STATE_ERROR
Definition: ald_i2s.h:152
I2S_STATE_BUSY_TX_RX
Definition: ald_i2s.h:150
I2S_STATE_BUSY_TX
Definition: ald_i2s.h:148
i2s_state_t
i2s_state_t
I2S state structures definition.
Definition: ald_i2s.h:144
I2S_STATE_BUSY_RX
Definition: ald_i2s.h:149
I2S_STATE_RESET
Definition: ald_i2s.h:145
I2S_STATE_TIMEOUT
Definition: ald_i2s.h:151
I2S_STATE_READY
Definition: ald_i2s.h:146

◆ i2s_status_t

enum i2s_status_t

I2S status definition.

Enumerator
I2S_STATUS_TXE | Transmit fifo empty status
I2S_STATUS_TXF | Transmit fifo full status
I2S_STATUS_TXOV | Transmit fifo overflow status
I2S_STATUS_TXUD | Transmit fifo underflow status
I2S_STATUS_RXE | Receive fifo empty status
I2S_STATUS_RXF | Receive fifo full status
I2S_STATUS_RXOV | Receive fifo overflow status
I2S_STATUS_RXUD | Receive fifo underflow status
I2S_STATUS_CHSIDE | Sound channel status
I2S_STATUS_BUSY | BUSY status

Definition at line 158 of file ald_i2s.h.

158 {
159 I2S_STATUS_TXE = (1U << 0),
160 I2S_STATUS_TXF = (1U << 1),
161 I2S_STATUS_TXOV = (1U << 2),
162 I2S_STATUS_TXUD = (1U << 3),
163 I2S_STATUS_RXE = (1U << 8),
164 I2S_STATUS_RXF = (1U << 9),
165 I2S_STATUS_RXOV = (1U << 10),
166 I2S_STATUS_RXUD = (1U << 11),
167 I2S_STATUS_CHSIDE = (1U << 14),
168 I2S_STATUS_BUSY = (1U << 15),
169 } i2s_status_t;
I2S_STATUS_RXOV
Definition: ald_i2s.h:165
I2S_STATUS_BUSY
Definition: ald_i2s.h:168
I2S_STATUS_TXE
Definition: ald_i2s.h:159
I2S_STATUS_TXF
Definition: ald_i2s.h:160
I2S_STATUS_RXUD
Definition: ald_i2s.h:166
I2S_STATUS_TXUD
Definition: ald_i2s.h:162
I2S_STATUS_RXE
Definition: ald_i2s.h:163
I2S_STATUS_CHSIDE
Definition: ald_i2s.h:167
I2S_STATUS_RXF
Definition: ald_i2s.h:164
i2s_status_t
i2s_status_t
I2S status definition.
Definition: ald_i2s.h:158
I2S_STATUS_TXOV
Definition: ald_i2s.h:161


ALD User Manual: i2s_init_t Struct Reference

Data Fields
i2s_init_t Struct Reference
EASTSOFT ES32F3xx ALD » I2S » I2S Public Types

I2S init structure definition. More...

#include <ald_i2s.h>

Data Fields

i2s_chlen_t ch_len
i2s_datalen_t data_len
i2s_cpol_t polarity
i2s_standard_t standard
i2s_pcms_t pcm_frame
type_func_t ext_clk_en
uint32_t | ext_clk
type_func_t mck_en
uint32_t | sampling

Detailed Description

I2S init structure definition.

Definition at line 191 of file ald_i2s.h.

Field Documentation

◆ ch_len

i2s_chlen_t ch_len

Channel length choose

Definition at line 192 of file ald_i2s.h.

◆ data_len

i2s_datalen_t data_len

Data length choose

Definition at line 193 of file ald_i2s.h.

◆ ext_clk

uint32_t ext_clk

External clock, unit is Hz

Definition at line 198 of file ald_i2s.h.

◆ ext_clk_en

type_func_t ext_clk_en

Choose external clock or APB1 clock

Definition at line 197 of file ald_i2s.h.

◆ mck_en

type_func_t mck_en

Main clock output function

Definition at line 199 of file ald_i2s.h.

◆ pcm_frame

i2s_pcms_t pcm_frame

PCM frame synchronization

Definition at line 196 of file ald_i2s.h.

◆ polarity

i2s_cpol_t polarity

Inactive clock polarity

Definition at line 194 of file ald_i2s.h.

◆ sampling

uint32_t sampling

Sampling rate. eg. 192*1024-192KHz, 96*1024-96KHz

Definition at line 200 of file ald_i2s.h.

◆ standard

i2s_standard_t standard

Standard choose

Definition at line 195 of file ald_i2s.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_i2s.h


ALD User Manual: i2s_handle_s Struct Reference

Data Fields
i2s_handle_s Struct Reference
EASTSOFT ES32F3xx ALD » I2S » I2S Public Types

I2S handle structure definition. More...

#include <ald_i2s.h>

Collaboration diagram for i2s_handle_s:
[legend]

Data Fields

SPI_I2S_TypeDef * | perh
i2s_init_t init
uint16_t * | tx_buf
uint32_t | tx_size
uint32_t | tx_count
uint16_t * | rx_buf
uint32_t | rx_size
uint32_t | rx_count
dma_handle_t hdmatx
dma_handle_t hdmarx
lock_state_t lock
i2s_state_t state
uint8_t | side
uint32_t | err_code
void(* | tx_cplt_cbk )(struct i2s_handle_s *arg)
void(* | rx_cplt_cbk )(struct i2s_handle_s *arg)
void(* | err_cbk )(struct i2s_handle_s *arg)

Detailed Description

I2S handle structure definition.

Definition at line 206 of file ald_i2s.h.

Field Documentation

◆ err_cbk

void(* err_cbk) (struct i2s_handle_s *arg)

error callback

Definition at line 226 of file ald_i2s.h.

◆ err_code

uint32_t err_code

I2S error code

Definition at line 222 of file ald_i2s.h.

◆ hdmarx

dma_handle_t hdmarx

I2S DMA handle parameters

Definition at line 217 of file ald_i2s.h.

◆ hdmatx

dma_handle_t hdmatx

I2S DMA handle parameters

Definition at line 216 of file ald_i2s.h.

◆ init

i2s_init_t init

I2S communication parameters

Definition at line 208 of file ald_i2s.h.

◆ lock

lock_state_t lock

Locking object

Definition at line 219 of file ald_i2s.h.

◆ perh

SPI_I2S_TypeDef* perh

I2S registers base address

Definition at line 207 of file ald_i2s.h.

◆ rx_buf

uint16_t* rx_buf

Pointer to I2S Rx transfer buffer

Definition at line 212 of file ald_i2s.h.

◆ rx_count

uint32_t rx_count

I2S Rx Transfer Counter

Definition at line 214 of file ald_i2s.h.

◆ rx_cplt_cbk

void(* rx_cplt_cbk) (struct i2s_handle_s *arg)

Rx completed callback

Definition at line 225 of file ald_i2s.h.

◆ rx_size

uint32_t rx_size

I2S Rx Transfer size

Definition at line 213 of file ald_i2s.h.

◆ side

uint8_t side

I2S channel side

Definition at line 221 of file ald_i2s.h.

◆ state

i2s_state_t state

I2S communication state

Definition at line 220 of file ald_i2s.h.

◆ tx_buf

uint16_t* tx_buf

Pointer to I2S Tx transfer buffer

Definition at line 209 of file ald_i2s.h.

◆ tx_count

uint32_t tx_count

I2S Tx transfer counter

Definition at line 211 of file ald_i2s.h.

◆ tx_cplt_cbk

void(* tx_cplt_cbk) (struct i2s_handle_s *arg)

Tx completed callback

Definition at line 224 of file ald_i2s.h.

◆ tx_size

uint32_t tx_size

I2S Tx transfer size

Definition at line 210 of file ald_i2s.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_i2s.h


ALD User Manual: I2S Public Macros

Macros
I2S Public Macros
EASTSOFT ES32F3xx ALD » I2S
Collaboration diagram for I2S Public Macros:

Macros

#define | I2S_RESET_HANDLE_STATE(x) ((x)->state = I2S_STATE_RESET)
#define | I2S_ENABLE(x) (SET_BIT((x)->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK))
#define | I2S_DISABLE(x) (CLEAR_BIT((x)->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK))

Detailed Description

Macro Definition Documentation

◆ I2S_DISABLE

#define I2S_DISABLE ( x ) (CLEAR_BIT((x)->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK))

Definition at line 237 of file ald_i2s.h.

◆ I2S_ENABLE

#define I2S_ENABLE ( x ) (SET_BIT((x)->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK))

Definition at line 236 of file ald_i2s.h.

◆ I2S_RESET_HANDLE_STATE

#define I2S_RESET_HANDLE_STATE ( x ) ((x)->state = I2S_STATE_RESET)

Definition at line 235 of file ald_i2s.h.


ALD User Manual: I2S Private Macros

Macros
I2S Private Macros
EASTSOFT ES32F3xx ALD » I2S
Collaboration diagram for I2S Private Macros:

Macros

#define | IS_I2S(x)
#define | IS_I2S_CH_LEN(x)
#define | IS_I2S_DATE_LEN(x)
#define | IS_I2S_CPOL(x)
#define | IS_I2S_STANDARD(x)
#define | IS_I2S_PCMS(x)
#define | IS_I2S_IT(x)
#define | IS_I2S_IF(x)
#define | IS_I2S_FLAG(x)
#define | IS_I2S_STATUS(x)
#define | IS_I2S_DMA_REQ(x)

Detailed Description

Macro Definition Documentation

◆ IS_I2S

#define IS_I2S ( x )
Value:
(((x) == I2S0) || \
((x) == I2S1) || \
((x) == I2S2))

Definition at line 245 of file ald_i2s.h.

◆ IS_I2S_CH_LEN

#define IS_I2S_CH_LEN ( x )
Value:
(((x) == I2S_WIDE_16) || \
((x) == I2S_WIDE_32))
I2S_WIDE_16
Definition: ald_i2s.h:43
I2S_WIDE_32
Definition: ald_i2s.h:44

Definition at line 248 of file ald_i2s.h.

◆ IS_I2S_CPOL

#define IS_I2S_CPOL ( x )
Value:
(((x) == I2S_INACTIVE_LOW) || \
((x) == I2S_INACTIVE_HIGH))
I2S_INACTIVE_LOW
Definition: ald_i2s.h:60
I2S_INACTIVE_HIGH
Definition: ald_i2s.h:61

Definition at line 253 of file ald_i2s.h.

◆ IS_I2S_DATE_LEN

#define IS_I2S_DATE_LEN ( x )
Value:
(((x) == I2S_LEN_16) || \
((x) == I2S_LEN_24) || \
((x) == I2S_LEN_32))
I2S_LEN_16
Definition: ald_i2s.h:51
I2S_LEN_24
Definition: ald_i2s.h:52
I2S_LEN_32
Definition: ald_i2s.h:53

Definition at line 250 of file ald_i2s.h.

◆ IS_I2S_DMA_REQ

#define IS_I2S_DMA_REQ ( x )
Value:
(((x) == I2S_DMA_REQ_TX) || \
((x) == I2S_DMA_REQ_RX))
I2S_DMA_REQ_TX
Definition: ald_i2s.h:123
I2S_DMA_REQ_RX
Definition: ald_i2s.h:124

Definition at line 299 of file ald_i2s.h.

◆ IS_I2S_FLAG

#define IS_I2S_FLAG ( x )
Value:
(((x) == I2S_FLAG_TXE) || \
((x) == I2S_FLAG_TXF) || \
((x) == I2S_FLAG_TXOV) || \
((x) == I2S_FLAG_TXUD) || \
((x) == I2S_FLAG_RXE) || \
((x) == I2S_FLAG_RXF) || \
((x) == I2S_FLAG_RXOV) || \
((x) == I2S_FLAG_RXUD) || \
((x) == I2S_FLAG_CHSIDE) || \
((x) == I2S_FLAG_BSY))

Definition at line 279 of file ald_i2s.h.

◆ IS_I2S_IF

#define IS_I2S_IF ( x )
Value:
(((x) == I2S_IF_TXE) || \
((x) == I2S_IF_TXOV) || \
((x) == I2S_IF_TXUD) || \
((x) == I2S_IF_RXF) || \
((x) == I2S_IF_RXOV) || \
((x) == I2S_IF_RXUD) || \
((x) == I2S_IF_RXTH) || \
((x) == I2S_IF_FRE))
I2S_IF_RXF
Definition: ald_i2s.h:134
I2S_IF_RXTH
Definition: ald_i2s.h:137
I2S_IF_TXUD
Definition: ald_i2s.h:133
I2S_IF_FRE
Definition: ald_i2s.h:138
I2S_IF_TXE
Definition: ald_i2s.h:131
I2S_IF_RXUD
Definition: ald_i2s.h:136
I2S_IF_RXOV
Definition: ald_i2s.h:135
I2S_IF_TXOV
Definition: ald_i2s.h:132

Definition at line 271 of file ald_i2s.h.

◆ IS_I2S_IT

#define IS_I2S_IT ( x )
Value:
(((x) == I2S_IT_TXE) || \
((x) == I2S_IT_TXOV) || \
((x) == I2S_IT_TXUD) || \
((x) == I2S_IT_RXF) || \
((x) == I2S_IT_RXOV) || \
((x) == I2S_IT_RXUD) || \
((x) == I2S_IT_RXTH) || \
((x) == I2S_IT_CRCERR) || \
((x) == I2S_IT_MODF) || \
((x) == I2S_IT_FRE))
I2S_IT_CRCERR
Definition: ald_i2s.h:114
I2S_IT_RXTH
Definition: ald_i2s.h:113
I2S_IT_RXUD
Definition: ald_i2s.h:112
I2S_IT_TXE
Definition: ald_i2s.h:107
I2S_IT_RXOV
Definition: ald_i2s.h:111
I2S_IT_MODF
Definition: ald_i2s.h:115
I2S_IT_TXOV
Definition: ald_i2s.h:108
I2S_IT_RXF
Definition: ald_i2s.h:110
I2S_IT_TXUD
Definition: ald_i2s.h:109
I2S_IT_FRE
Definition: ald_i2s.h:116

Definition at line 261 of file ald_i2s.h.

◆ IS_I2S_PCMS

#define IS_I2S_PCMS ( x )
Value:
(((x) == I2S_FRAME_SHORT) || \
((x) == I2S_FRAME_LONG))
I2S_FRAME_SHORT
Definition: ald_i2s.h:86
I2S_FRAME_LONG
Definition: ald_i2s.h:87

Definition at line 259 of file ald_i2s.h.

◆ IS_I2S_STANDARD

#define IS_I2S_STANDARD ( x )
Value:
(((x) == I2S_STD_PHI) || \
((x) == I2S_STD_MSB) || \
((x) == I2S_STD_LSB) || \
((x) == I2S_STD_PCM))
I2S_STD_PHI
Definition: ald_i2s.h:68
I2S_STD_PCM
Definition: ald_i2s.h:71
I2S_STD_MSB
Definition: ald_i2s.h:69
I2S_STD_LSB
Definition: ald_i2s.h:70

Definition at line 255 of file ald_i2s.h.

◆ IS_I2S_STATUS

#define IS_I2S_STATUS ( x )
Value:
(((x) == I2S_STATUS_TXE) || \
((x) == I2S_STATUS_TXF) || \
((x) == I2S_STATUS_TXOV) || \
((x) == I2S_STATUS_TXUD) || \
((x) == I2S_STATUS_RXE) || \
((x) == I2S_STATUS_RXF) || \
((x) == I2S_STATUS_RXOV) || \
((x) == I2S_STATUS_RXUD) || \
((x) == I2S_STATUS_CHSIDE) || \
((x) == I2S_STATUS_BUSY))
I2S_STATUS_RXOV
Definition: ald_i2s.h:165
I2S_STATUS_BUSY
Definition: ald_i2s.h:168
I2S_STATUS_TXE
Definition: ald_i2s.h:159
I2S_STATUS_TXF
Definition: ald_i2s.h:160
I2S_STATUS_RXUD
Definition: ald_i2s.h:166
I2S_STATUS_TXUD
Definition: ald_i2s.h:162
I2S_STATUS_RXE
Definition: ald_i2s.h:163
I2S_STATUS_CHSIDE
Definition: ald_i2s.h:167
I2S_STATUS_RXF
Definition: ald_i2s.h:164
I2S_STATUS_TXOV
Definition: ald_i2s.h:161

Definition at line 289 of file ald_i2s.h.


ALD User Manual: IAP

Modules
IAP
EASTSOFT ES32F3xx ALD

IAP module driver. More...

Collaboration diagram for IAP:

Modules

IAP Public Functions
IAP Private Macros
IAP Private Types

Detailed Description

IAP module driver.


ALD User Manual: IAP Public Functions

Functions
IAP Public Functions
EASTSOFT ES32F3xx ALD » IAP
Collaboration diagram for IAP Public Functions:

Functions

uint32_t | ald_iap_erase_page (uint32_t addr)
Erases a specified page. More...
uint32_t | ald_iap_program_word (uint32_t addr, uint32_t data)
Programs a word at a specified address. More...
uint32_t | ald_iap_program_dword (uint32_t addr, uint32_t data_l, uint32_t data_h)
Programs double words at a specified address. More...
uint32_t | ald_iap_program_words (uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase)
Programs datas at a specified address. More...

Detailed Description

==============================================================================
            #####  Erase and Program flash functions #####
==============================================================================
  [..]  This section provides functions allowing to:
    (+) Erase flash.
    (+) Program flash.

Function Documentation

◆ ald_iap_erase_page()

uint32_t ald_iap_erase_page ( uint32_t addr )

Erases a specified page.

Parameters
addr The beginning address of the page to be erased.
Return values
The result:
  • 0: SUCCESS
  • 1: ERROR

Definition at line 52 of file ald_iap.c.

53 {
54 uint32_t status;
55 IAP_PE iap_pe = (IAP_PE)(*(uint32_t *)IAP_PE_ADDR);
56
57 __disable_irq();
58 status = (*iap_pe)(addr);
59 __enable_irq();
60
61 return !status;
62 }
IAP_PE
uint32_t(* IAP_PE)(uint32_t addr)
Definition: ald_iap.h:50
IAP_PE_ADDR
#define IAP_PE_ADDR
Definition: ald_iap.h:40

◆ ald_iap_program_dword()

uint32_t ald_iap_program_dword | ( | uint32_t | addr,
 |  | uint32_t | data_l,
 |  | uint32_t | data_h
 | ) |  |

Programs double words at a specified address.

Parameters
addr | Specifies the address to be programmed. Bit0-1 must be zero.
data_l | Specifies the LSB data to be programmed.
data_h | Specifies the MSB data to be programmed.
Return values
The result:
  • 0: SUCCESS
  • 1: ERROR

Definition at line 98 of file ald_iap.c.

99 {
100 uint32_t status;
101 IAP_DWP iap_dwp = (IAP_DWP)(*(uint32_t *)IAP_DWP_ADDR);
102
103 if (addr & 0x3)
104 return 1;
105
106 __disable_irq();
107 status = (*iap_dwp)(addr, data_l, data_h);
108 __enable_irq();
109
110 return !status;
111 }
IAP_DWP_ADDR
#define IAP_DWP_ADDR
Definition: ald_iap.h:42
IAP_DWP
uint32_t(* IAP_DWP)(uint32_t addr, uint32_t data_l, uint32_t data_h)
Definition: ald_iap.h:52

◆ ald_iap_program_word()

uint32_t ald_iap_program_word | ( | uint32_t | addr,
 |  | uint32_t | data
 | ) |  |

Programs a word at a specified address.

Parameters
addr | Specifies the address to be programmed. Bit0-1 must be zero.
data | Specifies the data to be programmed.
Return values
The result:
  • 0: SUCCESS
  • 1: ERROR

Definition at line 73 of file ald_iap.c.

74 {
75 uint32_t status;
76 IAP_WP iap_wp = (IAP_WP)(*(uint32_t *)IAP_WP_ADDR);
77
78 if (addr & 0x3)
79 return 1;
80
81 __disable_irq();
82 status = (*iap_wp)(addr, data);
83 __enable_irq();
84
85 return !status;
86 }
IAP_WP
uint32_t(* IAP_WP)(uint32_t addr, uint32_t data)
Definition: ald_iap.h:51
IAP_WP_ADDR
#define IAP_WP_ADDR
Definition: ald_iap.h:41

◆ ald_iap_program_words()

uint32_t ald_iap_program_words | ( | uint32_t | addr,
 |  | uint8_t * | data,
 |  | uint32_t | len,
 |  | uint32_t | erase
 | ) |  |

Programs datas at a specified address.

Parameters
addr | Specifies the address to be programmed. Bit0-1 must be zero.
data | Specifies the data to be programmed.
len | Specifies the data length to be programmed. Bit0-1 must be zero.
erase | Erase page flag before programming.
Return values
The result:
  • 0: SUCCESS
  • 1: ERROR

Definition at line 125 of file ald_iap.c.

126 {
127 uint32_t status;
128 IAP_WSP iap_wsp = (IAP_WSP)(*(uint32_t *)IAP_WSP_ADDR);
129
130 if ((addr & 0x3) || (len & 0x3))
131 return 1;
132
133 __disable_irq();
134 status = (*iap_wsp)(addr, data, len, erase);
135 __enable_irq();
136
137 return !status;
138 }
IAP_WSP
uint32_t(* IAP_WSP)(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase)
Definition: ald_iap.h:53
IAP_WSP_ADDR
#define IAP_WSP_ADDR
Definition: ald_iap.h:39


ALD User Manual: IAP Private Macros

Macros
IAP Private Macros
EASTSOFT ES32F3xx ALD » IAP
Collaboration diagram for IAP Private Macros:

Macros

#define | IAP_WSP_ADDR 0x10000000U
#define | IAP_PE_ADDR 0x10000004U
#define | IAP_WP_ADDR 0x10000008U
#define | IAP_DWP_ADDR 0x1000000cU

Detailed Description

Macro Definition Documentation

◆ IAP_DWP_ADDR

#define IAP_DWP_ADDR 0x1000000cU

Definition at line 42 of file ald_iap.h.

◆ IAP_PE_ADDR

#define IAP_PE_ADDR 0x10000004U

Definition at line 40 of file ald_iap.h.

◆ IAP_WP_ADDR

#define IAP_WP_ADDR 0x10000008U

Definition at line 41 of file ald_iap.h.

◆ IAP_WSP_ADDR

#define IAP_WSP_ADDR 0x10000000U

Definition at line 39 of file ald_iap.h.


ALD User Manual: IAP Private Types

Typedefs
IAP Private Types
EASTSOFT ES32F3xx ALD » IAP
Collaboration diagram for IAP Private Types:

Typedefs

typedef uint32_t(* | IAP_PE) (uint32_t addr)
typedef uint32_t(* | IAP_WP) (uint32_t addr, uint32_t data)
typedef uint32_t(* | IAP_DWP) (uint32_t addr, uint32_t data_l, uint32_t data_h)
typedef uint32_t(* | IAP_WSP) (uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase)

Detailed Description

Typedef Documentation

◆ IAP_DWP

typedef uint32_t(* IAP_DWP) (uint32_t addr, uint32_t data_l, uint32_t data_h)

Definition at line 52 of file ald_iap.h.

◆ IAP_PE

typedef uint32_t(* IAP_PE) (uint32_t addr)

Definition at line 50 of file ald_iap.h.

◆ IAP_WP

typedef uint32_t(* IAP_WP) (uint32_t addr, uint32_t data)

Definition at line 51 of file ald_iap.h.

◆ IAP_WSP

typedef uint32_t(* IAP_WSP) (uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase)

Definition at line 53 of file ald_iap.h.


ALD User Manual: NAND

Modules
NAND
EASTSOFT ES32F3xx ALD

NAND driver modules. More...

Collaboration diagram for NAND:

Modules

NAND Public Functions
NAND Public functions.
NAND Public Types
Nand Private Constants
Nand Private Macros

Detailed Description

NAND driver modules.


ALD User Manual: NAND Public Functions

Modules
NAND Public Functions
EASTSOFT ES32F3xx ALD » NAND

NAND Public functions. More...

Collaboration diagram for NAND Public Functions:

Modules

Initialization functions
NAND Initialization functions.
IO operation functions
IO operation functions.
NAND Control functions
NAND Control functions.

Detailed Description

NAND Public functions.


ALD User Manual: Initialization functions

Functions
Initialization functions
EASTSOFT ES32F3xx ALD » NAND » NAND Public Functions

NAND Initialization functions. More...

Collaboration diagram for Initialization functions:

Functions

ald_status_t | ald_nand_init (nand_handle_t *hperh, ald_ebi_nand_timing_t *ctiming, ald_ebi_nand_timing_t *atiming)
Perform NAND memory initialization sequence. More...
ald_status_t | ald_nand_deinit (nand_handle_t *hperh)
Perform NAND memory De-Initialization sequence. More...
ald_status_t | ald_nand_reset (nand_handle_t *hperh)
NAND memory reset. More...
void | nand_config_device (nand_handle_t *hperh, nand_device_cfg_t *pdcfg)
configure the device: Enter the physical parameters of the device More...

Detailed Description

NAND Initialization functions.

Function Documentation

◆ ald_nand_deinit()

ald_status_t ald_nand_deinit ( nand_handle_t * hperh )

Perform NAND memory De-Initialization sequence.

Parameters
hperh pointer to a nand_handle_t structure
Return values
ald status

Definition at line 92 of file ald_nand.c.

93 {
94 ald_ebi_nand_deinit(hperh->instance, hperh->init.bank);
95 hperh->state = ALD_NAND_STATE_RESET;
96 __UNLOCK(hperh);
97
98 return OK;
99 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
nand_handle_t::init
ald_ebi_nand_init_t init
Definition: ald_nand.h:88
nand_handle_t::state
__IO ald_nand_state_t state
Definition: ald_nand.h:90
nand_handle_t::instance
EBI_NAND_TypeDef * instance
Definition: ald_nand.h:87
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159
ALD_NAND_STATE_RESET
Definition: ald_nand.h:42
ald_ebi_nand_deinit
void ald_ebi_nand_deinit(EBI_NAND_TypeDef *dev, uint32_t bank)
DeInitializes the EBI_NAND device.
Definition: ald_ebi.c:374

◆ ald_nand_init()

ald_status_t ald_nand_init | ( | nand_handle_t * | hperh,
 |  | ald_ebi_nand_timing_t * | ctiming,
 |  | ald_ebi_nand_timing_t * | atiming
 | ) |  |

Perform NAND memory initialization sequence.

Parameters
hperh | pointer to a nand_handle_t structure
ctiming | pointer to common space timing structure
atiming | pointer to attribute space timing structure
Return values
ald status

Definition at line 71 of file ald_nand.c.

72 {
73 if (hperh == NULL)
74 return ERROR;
75 if (hperh->state == ALD_NAND_STATE_RESET)
76 hperh->lock = UNLOCK;
77
78 ald_ebi_nand_init(hperh->instance, &(hperh->init));
79 ald_ebi_nand_comm_timing_init(hperh->instance, ctiming, hperh->init.bank);
80 ald_ebi_nand_attr_timing_init(hperh->instance, atiming, hperh->init.bank);
81 ald_ebi_nand_enable(hperh->instance, hperh->init.bank);
82 hperh->state = ALD_NAND_STATE_READY;
83
84 return OK;
85 }
OK
Definition: utils.h:55
nand_handle_t::init
ald_ebi_nand_init_t init
Definition: ald_nand.h:88
nand_handle_t::state
__IO ald_nand_state_t state
Definition: ald_nand.h:90
nand_handle_t::instance
EBI_NAND_TypeDef * instance
Definition: ald_nand.h:87
ALD_NAND_STATE_READY
Definition: ald_nand.h:43
ald_ebi_nand_enable
void ald_ebi_nand_enable(EBI_NAND_TypeDef *dev, uint32_t bank)
Enable the NAND device access.
Definition: ald_ebi.c:413
UNLOCK
Definition: type.h:59
ald_ebi_nand_comm_timing_init
void ald_ebi_nand_comm_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
Initializes the EBI_NAND Common space Timing according to the specified parameters in the EBI_NAND_Ti...
Definition: ald_ebi.c:312
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159
ald_ebi_nand_init
void ald_ebi_nand_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_init_t *init)
Initializes the EBI_NAND device according to the specified control parameters in the EBI_NAND_HandleT...
Definition: ald_ebi.c:272
ALD_NAND_STATE_RESET
Definition: ald_nand.h:42
ald_ebi_nand_attr_timing_init
void ald_ebi_nand_attr_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
Initializes the EBI_NAND Attribute space Timing according to the specified parameters in the EBI_NAND...
Definition: ald_ebi.c:344
nand_handle_t::lock
lock_state_t lock
Definition: ald_nand.h:89
ERROR
Definition: utils.h:56

◆ ald_nand_reset()

ald_status_t ald_nand_reset ( nand_handle_t * hperh )

NAND memory reset.

Parameters
hperh pointer to a nand_handle_t structure
Return values
ald status

Definition at line 106 of file ald_nand.c.

107 {
108 uint32_t deviceaddr = 0;
109
110 __LOCK(hperh);
111
112 if (hperh->state == ALD_NAND_STATE_BUSY)
113 return BUSY;
114
115 /* Identify the device address */
116 if (hperh->init.bank == EBI_NAND_BANK2)
117 deviceaddr = NAND_DEVICE1;
118 else
119 deviceaddr = NAND_DEVICE2;
120
121 hperh->state = ALD_NAND_STATE_BUSY;
122
123 /* Send NAND reset command */
124 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = 0xFF;
125
126 hperh->state = ALD_NAND_STATE_READY;
127 __UNLOCK(hperh);
128
129 return OK;
130 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
BUSY
Definition: utils.h:57
nand_handle_t::init
ald_ebi_nand_init_t init
Definition: ald_nand.h:88
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
nand_handle_t::state
__IO ald_nand_state_t state
Definition: ald_nand.h:90
ALD_NAND_STATE_READY
Definition: ald_nand.h:43
NAND_DEVICE2
#define NAND_DEVICE2
Definition: ald_nand.h:104
ALD_NAND_STATE_BUSY
Definition: ald_nand.h:44
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159
NAND_DEVICE1
#define NAND_DEVICE1
Definition: ald_nand.h:103
CMD_AREA
#define CMD_AREA
Definition: ald_nand.h:106
__LOCK
#define __LOCK(x)
Definition: utils.h:92

◆ nand_config_device()

void nand_config_device | ( | nand_handle_t * | hperh,
 |  | nand_device_cfg_t * | pdcfg
 | ) |  |

configure the device: Enter the physical parameters of the device

Parameters
hperh | pointer to a nand_handle_t structure
pdcfg | : pointer to nand_device_cfg_t structure
Return values
ald status

Definition at line 138 of file ald_nand.c.

139 {
140 hperh->config.page_size = pdcfg->page_size;
141 hperh->config.spare_size = pdcfg->spare_size;
142 hperh->config.block_size = pdcfg->block_size;
143 hperh->config.block_nbr = pdcfg->block_nbr;
144 hperh->config.plane_size = pdcfg->plane_size;
145 hperh->config.plane_nbr = pdcfg->plane_nbr;
146 hperh->config.extra_cmd = pdcfg->extra_cmd;
147 }
nand_device_cfg_t::plane_size
uint32_t plane_size
Definition: ald_nand.h:78
nand_device_cfg_t::extra_cmd
type_func_t extra_cmd
Definition: ald_nand.h:79
nand_device_cfg_t::block_size
uint32_t block_size
Definition: ald_nand.h:75
nand_handle_t::config
nand_device_cfg_t config
Definition: ald_nand.h:91
nand_device_cfg_t::spare_size
uint32_t spare_size
Definition: ald_nand.h:74
nand_device_cfg_t::page_size
uint32_t page_size
Definition: ald_nand.h:73
nand_device_cfg_t::plane_nbr
uint32_t plane_nbr
Definition: ald_nand.h:77
nand_device_cfg_t::block_nbr
uint32_t block_nbr
Definition: ald_nand.h:76


ALD User Manual: IO operation functions

Functions
IO operation functions
EASTSOFT ES32F3xx ALD » NAND » NAND Public Functions

IO operation functions. More...

Collaboration diagram for IO operation functions:

Functions

ald_status_t | ald_nand_read_id (nand_handle_t *hperh, nand_id_t *id)
Read the NAND memory electronic signature. More...
ald_status_t | ald_nand_read_page_8b (nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
Read page(s) from NAND memory block (8-bits addressing) More...
ald_status_t | ald_nand_write_page_8b (nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
Write page(s) to NAND memory block (8-bits addressing) More...
ald_status_t | ald_nand_read_sparearea_8b (nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
Read spare area(s) from NAND memory (8-bits addressing) More...
ald_status_t | ald_nand_write_sparearea_8b (nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
Write spare area(s) to NAND memory (8-bits addressing) More...
ald_status_t | ald_nand_read_page_16b (nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
Read page(s) from NAND memory block (16-bits addressing) More...
ald_status_t | ald_nand_write_page_16b (nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
Write page(s) to NAND memory block (16-bits addressing) More...
ald_status_t | ald_nand_read_sparearea_16b (nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
Read spare area(s) from NAND memory (16-bits addressing) More...
ald_status_t | ald_nand_write_sparearea_16b (nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
Write spare area(s) to NAND memory (16-bits addressing) More...
ald_status_t | ald_nand_erase_block (nand_handle_t *hperh, nand_address_t *addr)
NAND memory Block erase. More...

Detailed Description

IO operation functions.

Function Documentation

◆ ald_nand_erase_block()

ald_status_t ald_nand_erase_block | ( | nand_handle_t * | hperh,
 |  | nand_address_t * | addr
 | ) |  |

NAND memory Block erase.

Parameters
hperh | pointer to a nand_handle_t structure
addr | pointer to NAND address structure
Return values
ald status

Definition at line 1016 of file ald_nand.c.

1017 {
1018 uint32_t deviceaddr = 0;
1019 uint32_t tickstart = 0;
1020
1021 __LOCK(hperh);
1022
1023 if (hperh->state == ALD_NAND_STATE_BUSY)
1024 return BUSY;
1025
1026 /* Identify the device address */
1027 if (hperh->init.bank == EBI_NAND_BANK2)
1028 deviceaddr = NAND_DEVICE1;
1029 else
1030 deviceaddr = NAND_DEVICE2;
1031
1032 /* Update the NAND controller state */
1033 hperh->state = ALD_NAND_STATE_BUSY;
1034
1035 /* Send Erase block command sequence */
1036 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_ERASE0;
1037 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(addr, hperh));
1038 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(addr, hperh));
1039 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(addr, hperh));
1040 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_ERASE1;
1041
1042 /* Update the NAND controller state */
1043 hperh->state = ALD_NAND_STATE_READY;
1044 /* Get tick */
1045 tickstart = ald_get_tick();
1046
1047 /* Read status until NAND is ready */
1048 while (ald_nand_read_status(hperh) != NAND_READY) {
1049 if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT) {
1050 __UNLOCK(hperh);
1051
1052 return TIMEOUT;
1053 }
1054 }
1055
1056 __UNLOCK(hperh);
1057
1058 return OK;
1059 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
NAND_WRITE_TIMEOUT
#define NAND_WRITE_TIMEOUT
Definition: ald_nand.h:105
BUSY
Definition: utils.h:57
NAND_CMD_ERASE0
#define NAND_CMD_ERASE0
Definition: ald_nand.h:114
nand_handle_t::init
ald_ebi_nand_init_t init
Definition: ald_nand.h:88
ADDR_AREA
#define ADDR_AREA
Definition: ald_nand.h:107
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
nand_handle_t::state
__IO ald_nand_state_t state
Definition: ald_nand.h:90
ALD_NAND_STATE_READY
Definition: ald_nand.h:43
NAND_READY
#define NAND_READY
Definition: ald_nand.h:126
NAND_DEVICE2
#define NAND_DEVICE2
Definition: ald_nand.h:104
ALD_NAND_STATE_BUSY
Definition: ald_nand.h:44
ARRAY_ADDRESS
#define ARRAY_ADDRESS(x, y)
Definition: ald_nand.h:134
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159
ADDR_3RD_CYCLE
#define ADDR_3RD_CYCLE(x)
Definition: ald_nand.h:140
NAND_DEVICE1
#define NAND_DEVICE1
Definition: ald_nand.h:103
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
ADDR_2ND_CYCLE
#define ADDR_2ND_CYCLE(x)
Definition: ald_nand.h:139
ald_nand_read_status
uint32_t ald_nand_read_status(nand_handle_t *hperh)
NAND memory read status.
Definition: ald_nand.c:1147
CMD_AREA
#define CMD_AREA
Definition: ald_nand.h:106
NAND_CMD_ERASE1
#define NAND_CMD_ERASE1
Definition: ald_nand.h:115
ADDR_1ST_CYCLE
#define ADDR_1ST_CYCLE(x)
Definition: ald_nand.h:138
__LOCK
#define __LOCK(x)
Definition: utils.h:92

◆ ald_nand_read_id()

ald_status_t ald_nand_read_id | ( | nand_handle_t * | hperh,
 |  | nand_id_t * | id
 | ) |  |

Read the NAND memory electronic signature.

Parameters
hperh | pointer to a nand_handle_t structure
id | NAND ID structure
Return values
ald status

Definition at line 161 of file ald_nand.c.

162 {
163 __IO uint32_t data = 0;
164 __IO uint32_t data1 = 0;
165 uint32_t deviceaddr = 0;
166
167 __LOCK(hperh);
168
169 if (hperh->state == ALD_NAND_STATE_BUSY)
170 return BUSY;
171
172 /* Identify the device address */
173 if (hperh->init.bank == EBI_NAND_BANK2)
174 deviceaddr = NAND_DEVICE1;
175 else
176 deviceaddr = NAND_DEVICE2;
177
178 hperh->state = ALD_NAND_STATE_BUSY;
179
180 /* Send Read ID command sequence */
181 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_READID;
182 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
183
184 if (hperh->init.width == EBI_NAND_MEM_BUS_WIDTH_8) {
185 data = *(__IO uint32_t *)deviceaddr;
186
187 id->maker_id = ADDR_1ST_CYCLE(data);
188 id->device_id = ADDR_2ND_CYCLE(data);
189 id->third_id = ADDR_3RD_CYCLE(data);
190 id->fourth_id = ADDR_4TH_CYCLE(data);
191 }
192 else {
193 data = *(__IO uint32_t *)deviceaddr;
194 data1 = *((__IO uint32_t *)deviceaddr + 4);
195
196 /* Return the data read */
197 id->maker_id = ADDR_1ST_CYCLE(data);
198 id->device_id = ADDR_3RD_CYCLE(data);
199 id->third_id = ADDR_1ST_CYCLE(data1);
200 id->fourth_id = ADDR_3RD_CYCLE(data1);
201 }
202
203 hperh->state = ALD_NAND_STATE_READY;
204 __UNLOCK(hperh);
205
206 return OK;
207 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
BUSY
Definition: utils.h:57
nand_handle_t::init
ald_ebi_nand_init_t init
Definition: ald_nand.h:88
ADDR_AREA
#define ADDR_AREA
Definition: ald_nand.h:107
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
nand_handle_t::state
__IO ald_nand_state_t state
Definition: ald_nand.h:90
ALD_NAND_STATE_READY
Definition: ald_nand.h:43
NAND_CMD_READID
#define NAND_CMD_READID
Definition: ald_nand.h:116
NAND_DEVICE2
#define NAND_DEVICE2
Definition: ald_nand.h:104
ALD_NAND_STATE_BUSY
Definition: ald_nand.h:44
ald_ebi_nand_init_t::width
ebi_nand_mem_bus_width_t width
Definition: ald_ebi.h:161
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159
ADDR_3RD_CYCLE
#define ADDR_3RD_CYCLE(x)
Definition: ald_nand.h:140
NAND_DEVICE1
#define NAND_DEVICE1
Definition: ald_nand.h:103
ADDR_2ND_CYCLE
#define ADDR_2ND_CYCLE(x)
Definition: ald_nand.h:139
EBI_NAND_MEM_BUS_WIDTH_8
Definition: ald_ebi.h:131
CMD_AREA
#define CMD_AREA
Definition: ald_nand.h:106
ADDR_1ST_CYCLE
#define ADDR_1ST_CYCLE(x)
Definition: ald_nand.h:138
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ADDR_4TH_CYCLE
#define ADDR_4TH_CYCLE(x)
Definition: ald_nand.h:141

◆ ald_nand_read_page_16b()

ald_status_t ald_nand_read_page_16b | ( | nand_handle_t * | hperh,
 |  | nand_address_t * | addr,
 |  | uint16_t * | buf,
 |  | uint32_t | nr
 | ) |  |

Read page(s) from NAND memory block (16-bits addressing)

Parameters
hperh | pointer to a nand_handle_t structure
addr | pointer to NAND address structure
buf | pointer to destination read buffer
nr | number of pages to read from block
Return values
ald status

Definition at line 618 of file ald_nand.c.

619 {
620 __IO uint32_t index = 0;
621 uint32_t tickstart = 0;
622 uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0;
623
624 __LOCK(hperh);
625
626 if (hperh->state == ALD_NAND_STATE_BUSY)
627 return BUSY;
628
629 /* Identify the device address */
630 if (hperh->init.bank == EBI_NAND_BANK2)
631 deviceaddr = NAND_DEVICE1;
632 else
633 deviceaddr = NAND_DEVICE2;
634
635 hperh->state = ALD_NAND_STATE_BUSY;
636 nandaddr = ARRAY_ADDRESS(addr, hperh);
637
638 /* Page(s) read loop */
639 while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) {
640 /* update the buffer size */
641 size = (hperh->config.page_size) + ((hperh->config.page_size) * num);
642
643 /* Send read page command sequence */
644 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A;
645
646 /* Cards with page size <= 512 bytes */
647 if ((hperh->config.page_size) <= 512U) {
648 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
649 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
650 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
651 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
652 }
653 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
654 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
655 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
656 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
657 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
658 }
659 }
660 else {/* (hperh->config.page_size) > 512 */
661 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
662 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
663 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
664 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
665 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
666 }
667 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
668 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
669 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
670 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
671 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
672 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
673 }
674 }
675
676 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
677
678 if (hperh->config.extra_cmd == ENABLE) {
679 /* Get tick */
680 tickstart = ald_get_tick();
681
682 /* Read status until NAND is ready */
683 while (ald_nand_read_status(hperh) != NAND_READY) {
684 if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT)
685 return TIMEOUT;
686 }
687
688 /* Go back to read mode */
689 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = ((uint8_t)0x00);
690 }
691
692 /* Get Data into Buffer */
693 for (; index < size; index++)
694 *(uint16_t *)buf++ = *(uint16_t *)deviceaddr;
695
696 num++;
697 nr--;
698 nandaddr = (uint32_t)(nandaddr + 1U);
699 }
700
701 hperh->state = ALD_NAND_STATE_READY;
702 __UNLOCK(hperh);
703
704 return OK;
705 }
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
NAND_WRITE_TIMEOUT
#define NAND_WRITE_TIMEOUT
Definition: ald_nand.h:105
BUSY
Definition: utils.h:57
nand_handle_t::init
ald_ebi_nand_init_t init
Definition: ald_nand.h:88
ADDR_AREA
#define ADDR_AREA
Definition: ald_nand.h:107
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
nand_handle_t::state
__IO ald_nand_state_t state
Definition: ald_nand.h:90
ALD_NAND_STATE_READY
Definition: ald_nand.h:43
NAND_READY
#define NAND_READY
Definition: ald_nand.h:126
NAND_DEVICE2
#define NAND_DEVICE2
Definition: ald_nand.h:104
ALD_NAND_STATE_BUSY
Definition: ald_nand.h:44
nand_device_cfg_t::extra_cmd
type_func_t extra_cmd
Definition: ald_nand.h:79
ARRAY_ADDRESS
#define ARRAY_ADDRESS(x, y)
Definition: ald_nand.h:134
NAND_CMD_AREA_A
#define NAND_CMD_AREA_A
Definition: ald_nand.h:108
nand_device_cfg_t::block_size
uint32_t block_size
Definition: ald_nand.h:75
nand_handle_t::config
nand_device_cfg_t config
Definition: ald_nand.h:91
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159
ADDR_3RD_CYCLE
#define ADDR_3RD_CYCLE(x)
Definition: ald_nand.h:140
NAND_DEVICE1
#define NAND_DEVICE1
Definition: ald_nand.h:103
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
ADDR_2ND_CYCLE
#define ADDR_2ND_CYCLE(x)
Definition: ald_nand.h:139
nand_device_cfg_t::page_size
uint32_t page_size
Definition: ald_nand.h:73
ald_nand_read_status
uint32_t ald_nand_read_status(nand_handle_t *hperh)
NAND memory read status.
Definition: ald_nand.c:1147
CMD_AREA
#define CMD_AREA
Definition: ald_nand.h:106
ADDR_1ST_CYCLE
#define ADDR_1ST_CYCLE(x)
Definition: ald_nand.h:138
__LOCK
#define __LOCK(x)
Definition: utils.h:92
nand_device_cfg_t::block_nbr
uint32_t block_nbr
Definition: ald_nand.h:76
NAND_CMD_AREA_TRUE1
#define NAND_CMD_AREA_TRUE1
Definition: ald_nand.h:111

◆ ald_nand_read_page_8b()

ald_status_t ald_nand_read_page_8b | ( | nand_handle_t * | hperh,
 |  | nand_address_t * | addr,
 |  | uint8_t * | buf,
 |  | uint32_t | nr
 | ) |  |

Read page(s) from NAND memory block (8-bits addressing)

Parameters
hperh | pointer to a nand_handle_t structure
addr | pointer to NAND address structure
buf | pointer to destination read buffer
nr | number of pages to read from block
Return values
ald status

Definition at line 217 of file ald_nand.c.

218 {
219 __IO uint32_t index = 0;
220 uint32_t tickstart = 0;
221 uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0;
222
223 __LOCK(hperh);
224
225 if (hperh->state == ALD_NAND_STATE_BUSY)
226 return BUSY;
227
228 /* Identify the device address */
229 if (hperh->init.bank == EBI_NAND_BANK2)
230 deviceaddr = NAND_DEVICE1;
231 else
232 deviceaddr = NAND_DEVICE2;
233
234 hperh->state = ALD_NAND_STATE_BUSY;
235
236 /* NAND raw address calculation */
237 nandaddr = ARRAY_ADDRESS(addr, hperh);
238
239 /* Page(s) read loop */
240 while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) {
241 /* update the buffer size */
242 size = (hperh->config.page_size) + ((hperh->config.page_size) * num);
243
244 /* Send read page command sequence */
245 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A;
246
247 /* Cards with page size <= 512 bytes */
248 if ((hperh->config.page_size) <= 512U) {
249 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
250 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
251 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
252 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
253 }
254 else { /* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
255 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
256 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
257 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
258 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
259 }
260 }
261 else { /* (hperh->config.page_size) > 512 */
262 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
263 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
264 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
265 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
266 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
267 }
268 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
269 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
270 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
271 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
272 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
273 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
274 }
275 }
276
277 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
278
279 /* Check if an extra command is needed for reading pages */
280 if (hperh->config.extra_cmd == ENABLE) {
281 /* Get tick */
282 tickstart = ald_get_tick();
283
284 /* Read status until NAND is ready */
285 while (ald_nand_read_status(hperh) != NAND_READY) {
286 if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT)
287 return TIMEOUT;
288 }
289
290 /* Go back to read mode */
291 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = ((uint8_t)0x00);
292 }
293
294 /* Get Data into Buffer */
295 for (; index < size; index++) {
296 *(uint8_t *)buf++ = *(uint8_t *)deviceaddr;
297 }
298
299 num++;
300 nr--;
301 nandaddr = (uint32_t)(nandaddr + 1U);
302 }
303
304 hperh->state = ALD_NAND_STATE_READY;
305 __UNLOCK(hperh);
306
307 return OK;
308 }
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
NAND_WRITE_TIMEOUT
#define NAND_WRITE_TIMEOUT
Definition: ald_nand.h:105
BUSY
Definition: utils.h:57
nand_handle_t::init
ald_ebi_nand_init_t init
Definition: ald_nand.h:88
ADDR_AREA
#define ADDR_AREA
Definition: ald_nand.h:107
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
nand_handle_t::state
__IO ald_nand_state_t state
Definition: ald_nand.h:90
ALD_NAND_STATE_READY
Definition: ald_nand.h:43
NAND_READY
#define NAND_READY
Definition: ald_nand.h:126
NAND_DEVICE2
#define NAND_DEVICE2
Definition: ald_nand.h:104
ALD_NAND_STATE_BUSY
Definition: ald_nand.h:44
nand_device_cfg_t::extra_cmd
type_func_t extra_cmd
Definition: ald_nand.h:79
ARRAY_ADDRESS
#define ARRAY_ADDRESS(x, y)
Definition: ald_nand.h:134
NAND_CMD_AREA_A
#define NAND_CMD_AREA_A
Definition: ald_nand.h:108
nand_device_cfg_t::block_size
uint32_t block_size
Definition: ald_nand.h:75
nand_handle_t::config
nand_device_cfg_t config
Definition: ald_nand.h:91
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159
ADDR_3RD_CYCLE
#define ADDR_3RD_CYCLE(x)
Definition: ald_nand.h:140
NAND_DEVICE1
#define NAND_DEVICE1
Definition: ald_nand.h:103
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
ADDR_2ND_CYCLE
#define ADDR_2ND_CYCLE(x)
Definition: ald_nand.h:139
nand_device_cfg_t::page_size
uint32_t page_size
Definition: ald_nand.h:73
ald_nand_read_status
uint32_t ald_nand_read_status(nand_handle_t *hperh)
NAND memory read status.
Definition: ald_nand.c:1147
CMD_AREA
#define CMD_AREA
Definition: ald_nand.h:106
ADDR_1ST_CYCLE
#define ADDR_1ST_CYCLE(x)
Definition: ald_nand.h:138
__LOCK
#define __LOCK(x)
Definition: utils.h:92
nand_device_cfg_t::block_nbr
uint32_t block_nbr
Definition: ald_nand.h:76
NAND_CMD_AREA_TRUE1
#define NAND_CMD_AREA_TRUE1
Definition: ald_nand.h:111

◆ ald_nand_read_sparearea_16b()

ald_status_t ald_nand_read_sparearea_16b | ( | nand_handle_t * | hperh,
 |  | nand_address_t * | addr,
 |  | uint16_t * | buf,
 |  | uint32_t | nr
 | ) |  |

Read spare area(s) from NAND memory (16-bits addressing)

Parameters
hperh | pointer to a nand_handle_t structure
addr | pointer to NAND address structure
buf | pointer to source buffer to write. pbuffer should be 16bits aligned.
nr | Number of spare area to read
Return values
ald status

Definition at line 811 of file ald_nand.c.

812 {
813 __IO uint32_t index = 0;
814 uint32_t tickstart = 0;
815 uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0, columnaddr = 0;
816
817 __LOCK(hperh);
818
819 /* Check the NAND controller state */
820 if (hperh->state == ALD_NAND_STATE_BUSY)
821 return BUSY;
822
823 /* Identify the device address */
824 if (hperh->init.bank == EBI_NAND_BANK2)
825 deviceaddr = NAND_DEVICE1;
826 else
827 deviceaddr = NAND_DEVICE2;
828
829 /* Update the NAND controller state */
830 hperh->state = ALD_NAND_STATE_BUSY;
831 /* NAND raw address calculation */
832 nandaddr = ARRAY_ADDRESS(addr, hperh);
833 /* Column in page address */
834 columnaddr = (uint32_t)(COLUMN_ADDRESS(hperh) * 2U);
835
836 /* Spare area(s) read loop */
837 while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) {
838 /* update the buffer size */
839 size = (hperh->config.spare_size) + ((hperh->config.spare_size) * num);
840
841 /* Cards with page size <= 512 bytes */
842 if ((hperh->config.page_size) <= 512U) {
843 /* Send read spare area command sequence */
844 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_C;
845
846 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
847 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
848 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
849 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
850 }
851 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
852 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
853 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
854 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
855 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
856 }
857 }
858 else {/* (hperh->config.page_size) > 512 */
859 /* Send read spare area command sequence */
860 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A;
861
862 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
863 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr);
864 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr);
865 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
866 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
867 }
868 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
869 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr);
870 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr);
871 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
872 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
873 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
874 }
875 }
876
877 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
878
879 if (hperh->config.extra_cmd == ENABLE) {
880 /* Get tick */
881 tickstart = ald_get_tick();
882
883 /* Read status until NAND is ready */
884 while (ald_nand_read_status(hperh) != NAND_READY) {
885 if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT)
886 return TIMEOUT;
887 }
888
889 /* Go back to read mode */
890 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = ((uint8_t)0x00);
891 }
892
893 /* Get Data into Buffer */
894 for (; index < size; index++)
895 *(uint16_t *)buf++ = *(uint16_t *)deviceaddr;
896
897 num++;
898 nr--;
899 nandaddr = (uint32_t)(nandaddr + 1U);
900 }
901
902 hperh->state = ALD_NAND_STATE_READY;
903 __UNLOCK(hperh);
904
905 return OK;
906 }
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
NAND_WRITE_TIMEOUT
#define NAND_WRITE_TIMEOUT
Definition: ald_nand.h:105
BUSY
Definition: utils.h:57
nand_handle_t::init
ald_ebi_nand_init_t init
Definition: ald_nand.h:88
ADDR_AREA
#define ADDR_AREA
Definition: ald_nand.h:107
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
nand_handle_t::state
__IO ald_nand_state_t state
Definition: ald_nand.h:90
ALD_NAND_STATE_READY
Definition: ald_nand.h:43
NAND_READY
#define NAND_READY
Definition: ald_nand.h:126
NAND_DEVICE2
#define NAND_DEVICE2
Definition: ald_nand.h:104
ALD_NAND_STATE_BUSY
Definition: ald_nand.h:44
nand_device_cfg_t::extra_cmd
type_func_t extra_cmd
Definition: ald_nand.h:79
ARRAY_ADDRESS
#define ARRAY_ADDRESS(x, y)
Definition: ald_nand.h:134
NAND_CMD_AREA_A
#define NAND_CMD_AREA_A
Definition: ald_nand.h:108
nand_device_cfg_t::block_size
uint32_t block_size
Definition: ald_nand.h:75
nand_handle_t::config
nand_device_cfg_t config
Definition: ald_nand.h:91
COLUMN_2ND_CYCLE
#define COLUMN_2ND_CYCLE(x)
Definition: ald_nand.h:143
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159
ADDR_3RD_CYCLE
#define ADDR_3RD_CYCLE(x)
Definition: ald_nand.h:140
NAND_DEVICE1
#define NAND_DEVICE1
Definition: ald_nand.h:103
COLUMN_ADDRESS
#define COLUMN_ADDRESS(x)
Definition: ald_nand.h:137
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
NAND_CMD_AREA_C
#define NAND_CMD_AREA_C
Definition: ald_nand.h:110
nand_device_cfg_t::spare_size
uint32_t spare_size
Definition: ald_nand.h:74
ADDR_2ND_CYCLE
#define ADDR_2ND_CYCLE(x)
Definition: ald_nand.h:139
nand_device_cfg_t::page_size
uint32_t page_size
Definition: ald_nand.h:73
ald_nand_read_status
uint32_t ald_nand_read_status(nand_handle_t *hperh)
NAND memory read status.
Definition: ald_nand.c:1147
COLUMN_1ST_CYCLE
#define COLUMN_1ST_CYCLE(x)
Definition: ald_nand.h:142
CMD_AREA
#define CMD_AREA
Definition: ald_nand.h:106
ADDR_1ST_CYCLE
#define ADDR_1ST_CYCLE(x)
Definition: ald_nand.h:138
__LOCK
#define __LOCK(x)
Definition: utils.h:92
nand_device_cfg_t::block_nbr
uint32_t block_nbr
Definition: ald_nand.h:76
NAND_CMD_AREA_TRUE1
#define NAND_CMD_AREA_TRUE1
Definition: ald_nand.h:111

◆ ald_nand_read_sparearea_8b()

ald_status_t ald_nand_read_sparearea_8b | ( | nand_handle_t * | hperh,
 |  | nand_address_t * | addr,
 |  | uint8_t * | buf,
 |  | uint32_t | nr
 | ) |  |

Read spare area(s) from NAND memory (8-bits addressing)

Parameters
hperh | pointer to a nand_handle_t structure
addr | pointer to NAND address structure
buf | pointer to source buffer to write
nr | Number of spare area to read
Return values
ald status

Definition at line 414 of file ald_nand.c.

415 {
416 __IO uint32_t index = 0;
417 uint32_t tickstart = 0;
418 uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0, columnaddr = 0;
419
420 /* Process Locked */
421 __LOCK(hperh);
422
423 if (hperh->state == ALD_NAND_STATE_BUSY)
424 return BUSY;
425
426 /* Identify the device address */
427 if (hperh->init.bank == EBI_NAND_BANK2)
428 deviceaddr = NAND_DEVICE1;
429 else
430 deviceaddr = NAND_DEVICE2;
431
432 /* Update the NAND controller state */
433 hperh->state = ALD_NAND_STATE_BUSY;
434 /* NAND raw address calculation */
435 nandaddr = ARRAY_ADDRESS(addr, hperh);
436 /* Column in page address */
437 columnaddr = COLUMN_ADDRESS(hperh);
438
439 /* Spare area(s) read loop */
440 while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) {
441 /* update the buffer size */
442 size = (hperh->config.spare_size) + ((hperh->config.spare_size) * num);
443
444 /* Cards with page size <= 512 bytes */
445 if ((hperh->config.page_size) <= 512U) {
446 /* Send read spare area command sequence */
447 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_C;
448
449 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
450 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
451 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
452 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
453 }
454 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
455 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
456 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
457 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
458 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
459 }
460 }
461 else {/* (hperh->config.page_size) > 512 */
462 /* Send read spare area command sequence */
463 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A;
464
465 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
466 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr);
467 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr);
468 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
469 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
470 }
471 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
472 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr);
473 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr);
474 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
475 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
476 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
477 }
478 }
479
480 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
481
482 if (hperh->config.extra_cmd == ENABLE) {
483 /* Get tick */
484 tickstart = ald_get_tick();
485
486 /* Read status until NAND is ready */
487 while (ald_nand_read_status(hperh) != NAND_READY) {
488 if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT)
489 return TIMEOUT;
490 }
491
492 /* Go back to read mode */
493 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = ((uint8_t)0x00);
494 }
495
496 /* Get Data into Buffer */
497 for (; index < size; index++)
498 *(uint8_t *)buf++ = *(uint8_t *)deviceaddr;
499
500 num++;
501 nr--;
502 nandaddr = (uint32_t)(nandaddr + 1U);
503 }
504
505 hperh->state = ALD_NAND_STATE_READY;
506 __UNLOCK(hperh);
507
508 return OK;
509 }
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
NAND_WRITE_TIMEOUT
#define NAND_WRITE_TIMEOUT
Definition: ald_nand.h:105
BUSY
Definition: utils.h:57
nand_handle_t::init
ald_ebi_nand_init_t init
Definition: ald_nand.h:88
ADDR_AREA
#define ADDR_AREA
Definition: ald_nand.h:107
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
nand_handle_t::state
__IO ald_nand_state_t state
Definition: ald_nand.h:90
ALD_NAND_STATE_READY
Definition: ald_nand.h:43
NAND_READY
#define NAND_READY
Definition: ald_nand.h:126
NAND_DEVICE2
#define NAND_DEVICE2
Definition: ald_nand.h:104
ALD_NAND_STATE_BUSY
Definition: ald_nand.h:44
nand_device_cfg_t::extra_cmd
type_func_t extra_cmd
Definition: ald_nand.h:79
ARRAY_ADDRESS
#define ARRAY_ADDRESS(x, y)
Definition: ald_nand.h:134
NAND_CMD_AREA_A
#define NAND_CMD_AREA_A
Definition: ald_nand.h:108
nand_device_cfg_t::block_size
uint32_t block_size
Definition: ald_nand.h:75
nand_handle_t::config
nand_device_cfg_t config
Definition: ald_nand.h:91
COLUMN_2ND_CYCLE
#define COLUMN_2ND_CYCLE(x)
Definition: ald_nand.h:143
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159
ADDR_3RD_CYCLE
#define ADDR_3RD_CYCLE(x)
Definition: ald_nand.h:140
NAND_DEVICE1
#define NAND_DEVICE1
Definition: ald_nand.h:103
COLUMN_ADDRESS
#define COLUMN_ADDRESS(x)
Definition: ald_nand.h:137
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
NAND_CMD_AREA_C
#define NAND_CMD_AREA_C
Definition: ald_nand.h:110
nand_device_cfg_t::spare_size
uint32_t spare_size
Definition: ald_nand.h:74
ADDR_2ND_CYCLE
#define ADDR_2ND_CYCLE(x)
Definition: ald_nand.h:139
nand_device_cfg_t::page_size
uint32_t page_size
Definition: ald_nand.h:73
ald_nand_read_status
uint32_t ald_nand_read_status(nand_handle_t *hperh)
NAND memory read status.
Definition: ald_nand.c:1147
COLUMN_1ST_CYCLE
#define COLUMN_1ST_CYCLE(x)
Definition: ald_nand.h:142
CMD_AREA
#define CMD_AREA
Definition: ald_nand.h:106
ADDR_1ST_CYCLE
#define ADDR_1ST_CYCLE(x)
Definition: ald_nand.h:138
__LOCK
#define __LOCK(x)
Definition: utils.h:92
nand_device_cfg_t::block_nbr
uint32_t block_nbr
Definition: ald_nand.h:76
NAND_CMD_AREA_TRUE1
#define NAND_CMD_AREA_TRUE1
Definition: ald_nand.h:111

◆ ald_nand_write_page_16b()

ald_status_t ald_nand_write_page_16b | ( | nand_handle_t * | hperh,
 |  | nand_address_t * | addr,
 |  | uint16_t * | buf,
 |  | uint32_t | nr
 | ) |  |

Write page(s) to NAND memory block (16-bits addressing)

Parameters
hperh | pointer to a nand_handle_t structure
addr | : pointer to NAND address structure
buf | : pointer to source buffer to write. pbuffer should be 16bits aligned
nr | : number of pages to write to block
Return values
ald status

Definition at line 715 of file ald_nand.c.

716 {
717 __IO uint32_t index = 0;
718 uint32_t tickstart = 0;
719 uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0;
720
721 __LOCK(hperh);
722
723 if (hperh->state == ALD_NAND_STATE_BUSY)
724 return BUSY;
725
726 /* Identify the device address */
727 if (hperh->init.bank == EBI_NAND_BANK2)
728 deviceaddr = NAND_DEVICE1;
729 else
730 deviceaddr = NAND_DEVICE2;
731
732 hperh->state = ALD_NAND_STATE_BUSY;
733 /* NAND raw address calculation */
734 nandaddr = ARRAY_ADDRESS(addr, hperh);
735
736 /* Page(s) write loop */
737 while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) {
738 /* update the buffer size */
739 size = (hperh->config.page_size) + ((hperh->config.page_size) * num);
740
741 /* Send write page command sequence */
742 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A;
743 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0;
744
745 /* Cards with page size <= 512 bytes */
746 if ((hperh->config.page_size) <= 512U) {
747 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
748 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
749 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
750 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
751 }
752 else { /* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
753 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
754 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
755 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
756 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
757 }
758 }
759 else { /* (hperh->config.page_size) > 512 */
760 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
761 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
762 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
763 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
764 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
765 }
766 else { /* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
767 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
768 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
769 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
770 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
771 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
772 }
773 }
774
775 /* Write data to memory */
776 for (; index < size; index++)
777 *(__IO uint16_t *)deviceaddr = *(uint16_t *)buf++;
778
779 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
780
781 /* Read status until NAND is ready */
782 while (ald_nand_read_status(hperh) != NAND_READY) {
783 /* Get tick */
784 tickstart = ald_get_tick();
785
786 if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT)
787 return TIMEOUT;
788 }
789
790 num++;
791 nr--;
792 nandaddr = (uint32_t)(nandaddr + 1U);
793 }
794
795 hperh->state = ALD_NAND_STATE_READY;
796 __UNLOCK(hperh);
797
798 return OK;
799 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
NAND_CMD_WRITE_TRUE1
#define NAND_CMD_WRITE_TRUE1
Definition: ald_nand.h:113
NAND_WRITE_TIMEOUT
#define NAND_WRITE_TIMEOUT
Definition: ald_nand.h:105
BUSY
Definition: utils.h:57
nand_handle_t::init
ald_ebi_nand_init_t init
Definition: ald_nand.h:88
ADDR_AREA
#define ADDR_AREA
Definition: ald_nand.h:107
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
nand_handle_t::state
__IO ald_nand_state_t state
Definition: ald_nand.h:90
ALD_NAND_STATE_READY
Definition: ald_nand.h:43
NAND_READY
#define NAND_READY
Definition: ald_nand.h:126
NAND_DEVICE2
#define NAND_DEVICE2
Definition: ald_nand.h:104
ALD_NAND_STATE_BUSY
Definition: ald_nand.h:44
ARRAY_ADDRESS
#define ARRAY_ADDRESS(x, y)
Definition: ald_nand.h:134
NAND_CMD_AREA_A
#define NAND_CMD_AREA_A
Definition: ald_nand.h:108
nand_device_cfg_t::block_size
uint32_t block_size
Definition: ald_nand.h:75
nand_handle_t::config
nand_device_cfg_t config
Definition: ald_nand.h:91
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159
ADDR_3RD_CYCLE
#define ADDR_3RD_CYCLE(x)
Definition: ald_nand.h:140
NAND_DEVICE1
#define NAND_DEVICE1
Definition: ald_nand.h:103
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
ADDR_2ND_CYCLE
#define ADDR_2ND_CYCLE(x)
Definition: ald_nand.h:139
nand_device_cfg_t::page_size
uint32_t page_size
Definition: ald_nand.h:73
NAND_CMD_WRITE0
#define NAND_CMD_WRITE0
Definition: ald_nand.h:112
ald_nand_read_status
uint32_t ald_nand_read_status(nand_handle_t *hperh)
NAND memory read status.
Definition: ald_nand.c:1147
CMD_AREA
#define CMD_AREA
Definition: ald_nand.h:106
ADDR_1ST_CYCLE
#define ADDR_1ST_CYCLE(x)
Definition: ald_nand.h:138
__LOCK
#define __LOCK(x)
Definition: utils.h:92
nand_device_cfg_t::block_nbr
uint32_t block_nbr
Definition: ald_nand.h:76

◆ ald_nand_write_page_8b()

ald_status_t ald_nand_write_page_8b | ( | nand_handle_t * | hperh,
 |  | nand_address_t * | addr,
 |  | uint8_t * | buf,
 |  | uint32_t | nr
 | ) |  |

Write page(s) to NAND memory block (8-bits addressing)

Parameters
hperh | pointer to a nand_handle_t structure
addr | pointer to NAND address structure
buf | pointer to source buffer to write
nr | number of pages to write to block
Return values
ald status

Definition at line 318 of file ald_nand.c.

319 {
320 __IO uint32_t index = 0;
321 uint32_t tickstart = 0;
322 uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0;
323
324 __LOCK(hperh);
325
326 if (hperh->state == ALD_NAND_STATE_BUSY)
327 return BUSY;
328
329 /* Identify the device address */
330 if (hperh->init.bank == EBI_NAND_BANK2)
331 deviceaddr = NAND_DEVICE1;
332 else
333 deviceaddr = NAND_DEVICE2;
334
335 /* Update the NAND controller state */
336 hperh->state = ALD_NAND_STATE_BUSY;
337
338 /* NAND raw address calculation */
339 nandaddr = ARRAY_ADDRESS(addr, hperh);
340
341 /* Page(s) write loop */
342 while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) {
343 /* update the buffer size */
344 size = hperh->config.page_size + ((hperh->config.page_size) * num);
345
346 /* Send write page command sequence */
347 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A;
348 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0;
349
350 /* Cards with page size <= 512 bytes */
351 if ((hperh->config.page_size) <= 512U) {
352 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
353 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
354 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
355 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
356 }
357 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
358 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
359 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
360 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
361 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
362 }
363 }
364 else {/* (hperh->config.page_size) > 512 */
365 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
366 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
367 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
368 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
369 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
370 }
371 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
372 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
373 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
374 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
375 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
376 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
377 }
378 }
379
380 /* Write data to memory */
381 for (; index < size; index++)
382 *(__IO uint8_t *)deviceaddr = *(uint8_t *)buf++;
383
384 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
385
386 /* Read status until NAND is ready */
387 while (ald_nand_read_status(hperh) != NAND_READY) {
388 /* Get tick */
389 tickstart = ald_get_tick();
390
391 if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT)
392 return TIMEOUT;
393 }
394
395 num++;
396 nr--;
397 nandaddr = (uint32_t)(nandaddr + 1U);
398 }
399
400 hperh->state = ALD_NAND_STATE_READY;
401 __UNLOCK(hperh);
402
403 return OK;
404 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
NAND_CMD_WRITE_TRUE1
#define NAND_CMD_WRITE_TRUE1
Definition: ald_nand.h:113
NAND_WRITE_TIMEOUT
#define NAND_WRITE_TIMEOUT
Definition: ald_nand.h:105
BUSY
Definition: utils.h:57
nand_handle_t::init
ald_ebi_nand_init_t init
Definition: ald_nand.h:88
ADDR_AREA
#define ADDR_AREA
Definition: ald_nand.h:107
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
nand_handle_t::state
__IO ald_nand_state_t state
Definition: ald_nand.h:90
ALD_NAND_STATE_READY
Definition: ald_nand.h:43
NAND_READY
#define NAND_READY
Definition: ald_nand.h:126
NAND_DEVICE2
#define NAND_DEVICE2
Definition: ald_nand.h:104
ALD_NAND_STATE_BUSY
Definition: ald_nand.h:44
ARRAY_ADDRESS
#define ARRAY_ADDRESS(x, y)
Definition: ald_nand.h:134
NAND_CMD_AREA_A
#define NAND_CMD_AREA_A
Definition: ald_nand.h:108
nand_device_cfg_t::block_size
uint32_t block_size
Definition: ald_nand.h:75
nand_handle_t::config
nand_device_cfg_t config
Definition: ald_nand.h:91
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159
ADDR_3RD_CYCLE
#define ADDR_3RD_CYCLE(x)
Definition: ald_nand.h:140
NAND_DEVICE1
#define NAND_DEVICE1
Definition: ald_nand.h:103
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
ADDR_2ND_CYCLE
#define ADDR_2ND_CYCLE(x)
Definition: ald_nand.h:139
nand_device_cfg_t::page_size
uint32_t page_size
Definition: ald_nand.h:73
NAND_CMD_WRITE0
#define NAND_CMD_WRITE0
Definition: ald_nand.h:112
ald_nand_read_status
uint32_t ald_nand_read_status(nand_handle_t *hperh)
NAND memory read status.
Definition: ald_nand.c:1147
CMD_AREA
#define CMD_AREA
Definition: ald_nand.h:106
ADDR_1ST_CYCLE
#define ADDR_1ST_CYCLE(x)
Definition: ald_nand.h:138
__LOCK
#define __LOCK(x)
Definition: utils.h:92
nand_device_cfg_t::block_nbr
uint32_t block_nbr
Definition: ald_nand.h:76

◆ ald_nand_write_sparearea_16b()

ald_status_t ald_nand_write_sparearea_16b | ( | nand_handle_t * | hperh,
 |  | nand_address_t * | addr,
 |  | uint16_t * | buf,
 |  | uint32_t | nr
 | ) |  |

Write spare area(s) to NAND memory (16-bits addressing)

Parameters
hperh | pointer to a nand_handle_t structure
addr | pointer to NAND address structure
buf | pointer to source buffer to write. pbuffer should be 16bits aligned.
nr | number of spare areas to write to block
Return values
ald status

Definition at line 917 of file ald_nand.c.

918 {
919 __IO uint32_t index = 0;
920 uint32_t tickstart = 0;
921 uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0, columnaddr = 0;
922
923 __LOCK(hperh);
924
925 if (hperh->state == ALD_NAND_STATE_BUSY)
926 return BUSY;
927
928 /* Identify the device address */
929 if (hperh->init.bank == EBI_NAND_BANK2)
930 deviceaddr = NAND_DEVICE1;
931 else
932 deviceaddr = NAND_DEVICE2;
933
934 /* Update the FSMC_NAND controller state */
935 hperh->state = ALD_NAND_STATE_BUSY;
936 /* NAND raw address calculation */
937 nandaddr = ARRAY_ADDRESS(addr, hperh);
938 /* Column in page address */
939 columnaddr = (uint32_t)(COLUMN_ADDRESS(hperh) * 2);
940
941 /* Spare area(s) write loop */
942 while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) {
943 /* update the buffer size */
944 size = (hperh->config.spare_size) + ((hperh->config.spare_size) * num);
945
946 /* Cards with page size <= 512 bytes */
947 if ((hperh->config.page_size) <= 512U) {
948 /* Send write Spare area command sequence */
949 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_C;
950 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0;
951
952 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
953 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
954 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
955 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
956 }
957 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
958 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
959 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
960 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
961 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
962 }
963 }
964 else {/* (hperh->config.page_size) > 512 */
965 /* Send write Spare area command sequence */
966 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A;
967 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0;
968
969 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
970 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr);
971 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr);
972 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
973 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
974 }
975 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
976 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr);
977 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr);
978 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
979 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
980 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
981 }
982 }
983
984 /* Write data to memory */
985 for (; index < size; index++)
986 *(__IO uint16_t *)deviceaddr = *(uint16_t *)buf++;
987
988 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
989
990 /* Read status until NAND is ready */
991 while (ald_nand_read_status(hperh) != NAND_READY) {
992 /* Get tick */
993 tickstart = ald_get_tick();
994
995 if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT)
996 return TIMEOUT;
997 }
998
999 num++;
1000 nr--;
1001 nandaddr = (uint32_t)(nandaddr + 1U);
1002 }
1003
1004 hperh->state = ALD_NAND_STATE_READY;
1005 __UNLOCK(hperh);
1006
1007 return OK;
1008 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
NAND_CMD_WRITE_TRUE1
#define NAND_CMD_WRITE_TRUE1
Definition: ald_nand.h:113
NAND_WRITE_TIMEOUT
#define NAND_WRITE_TIMEOUT
Definition: ald_nand.h:105
BUSY
Definition: utils.h:57
nand_handle_t::init
ald_ebi_nand_init_t init
Definition: ald_nand.h:88
ADDR_AREA
#define ADDR_AREA
Definition: ald_nand.h:107
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
nand_handle_t::state
__IO ald_nand_state_t state
Definition: ald_nand.h:90
ALD_NAND_STATE_READY
Definition: ald_nand.h:43
NAND_READY
#define NAND_READY
Definition: ald_nand.h:126
NAND_DEVICE2
#define NAND_DEVICE2
Definition: ald_nand.h:104
ALD_NAND_STATE_BUSY
Definition: ald_nand.h:44
ARRAY_ADDRESS
#define ARRAY_ADDRESS(x, y)
Definition: ald_nand.h:134
NAND_CMD_AREA_A
#define NAND_CMD_AREA_A
Definition: ald_nand.h:108
nand_device_cfg_t::block_size
uint32_t block_size
Definition: ald_nand.h:75
nand_handle_t::config
nand_device_cfg_t config
Definition: ald_nand.h:91
COLUMN_2ND_CYCLE
#define COLUMN_2ND_CYCLE(x)
Definition: ald_nand.h:143
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159
ADDR_3RD_CYCLE
#define ADDR_3RD_CYCLE(x)
Definition: ald_nand.h:140
NAND_DEVICE1
#define NAND_DEVICE1
Definition: ald_nand.h:103
COLUMN_ADDRESS
#define COLUMN_ADDRESS(x)
Definition: ald_nand.h:137
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
NAND_CMD_AREA_C
#define NAND_CMD_AREA_C
Definition: ald_nand.h:110
nand_device_cfg_t::spare_size
uint32_t spare_size
Definition: ald_nand.h:74
ADDR_2ND_CYCLE
#define ADDR_2ND_CYCLE(x)
Definition: ald_nand.h:139
nand_device_cfg_t::page_size
uint32_t page_size
Definition: ald_nand.h:73
NAND_CMD_WRITE0
#define NAND_CMD_WRITE0
Definition: ald_nand.h:112
ald_nand_read_status
uint32_t ald_nand_read_status(nand_handle_t *hperh)
NAND memory read status.
Definition: ald_nand.c:1147
COLUMN_1ST_CYCLE
#define COLUMN_1ST_CYCLE(x)
Definition: ald_nand.h:142
CMD_AREA
#define CMD_AREA
Definition: ald_nand.h:106
ADDR_1ST_CYCLE
#define ADDR_1ST_CYCLE(x)
Definition: ald_nand.h:138
__LOCK
#define __LOCK(x)
Definition: utils.h:92
nand_device_cfg_t::block_nbr
uint32_t block_nbr
Definition: ald_nand.h:76

◆ ald_nand_write_sparearea_8b()

ald_status_t ald_nand_write_sparearea_8b | ( | nand_handle_t * | hperh,
 |  | nand_address_t * | addr,
 |  | uint8_t * | buf,
 |  | uint32_t | nr
 | ) |  |

Write spare area(s) to NAND memory (8-bits addressing)

Parameters
hperh | pointer to a nand_handle_t structure
addr | pointer to NAND address structure
buf | pointer to source buffer to write
nr | number of spare areas to write to block
Return values
ald status

Definition at line 519 of file ald_nand.c.

520 {
521 __IO uint32_t index = 0;
522 uint32_t tickstart = 0;
523 uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0, columnaddr = 0;
524
525 __LOCK(hperh);
526
527 if (hperh->state == ALD_NAND_STATE_BUSY)
528 return BUSY;
529
530 /* Identify the device address */
531 if (hperh->init.bank == EBI_NAND_BANK2)
532 deviceaddr = NAND_DEVICE1;
533 else
534 deviceaddr = NAND_DEVICE2;
535
536 /* Update the FSMC_NAND controller state */
537 hperh->state = ALD_NAND_STATE_BUSY;
538 /* Page address calculation */
539 nandaddr = ARRAY_ADDRESS(addr, hperh);
540 /* Column in page address */
541 columnaddr = COLUMN_ADDRESS(hperh);
542
543 /* Spare area(s) write loop */
544 while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) {
545 /* update the buffer size */
546 size = (hperh->config.spare_size) + ((hperh->config.spare_size) * num);
547
548 /* Cards with page size <= 512 bytes */
549 if ((hperh->config.page_size) <= 512U) {
550 /* Send write Spare area command sequence */
551 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_C;
552 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0;
553
554 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
555 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
556 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
557 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
558 }
559 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
560 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
561 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
562 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
563 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
564 }
565 }
566 else {/* (hperh->config.page_size) > 512 */
567 /* Send write Spare area command sequence */
568 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A;
569 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0;
570
571 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
572 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr);
573 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr);
574 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
575 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
576 }
577 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
578 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr);
579 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr);
580 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
581 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
582 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
583 }
584 }
585
586 /* Write data to memory */
587 for (; index < size; index++)
588 *(__IO uint8_t *)deviceaddr = *(uint8_t *)buf++;
589
590 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
591 tickstart = ald_get_tick();
592
593 /* Read status until NAND is ready */
594 while (ald_nand_read_status(hperh) != NAND_READY) {
595 if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT)
596 return TIMEOUT;
597 }
598
599 num++;
600 nr--;
601 nandaddr = (uint32_t)(nandaddr + 1U);
602 }
603
604 hperh->state = ALD_NAND_STATE_READY;
605 __UNLOCK(hperh);
606
607 return OK;
608 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
NAND_CMD_WRITE_TRUE1
#define NAND_CMD_WRITE_TRUE1
Definition: ald_nand.h:113
NAND_WRITE_TIMEOUT
#define NAND_WRITE_TIMEOUT
Definition: ald_nand.h:105
BUSY
Definition: utils.h:57
nand_handle_t::init
ald_ebi_nand_init_t init
Definition: ald_nand.h:88
ADDR_AREA
#define ADDR_AREA
Definition: ald_nand.h:107
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
nand_handle_t::state
__IO ald_nand_state_t state
Definition: ald_nand.h:90
ALD_NAND_STATE_READY
Definition: ald_nand.h:43
NAND_READY
#define NAND_READY
Definition: ald_nand.h:126
NAND_DEVICE2
#define NAND_DEVICE2
Definition: ald_nand.h:104
ALD_NAND_STATE_BUSY
Definition: ald_nand.h:44
ARRAY_ADDRESS
#define ARRAY_ADDRESS(x, y)
Definition: ald_nand.h:134
NAND_CMD_AREA_A
#define NAND_CMD_AREA_A
Definition: ald_nand.h:108
nand_device_cfg_t::block_size
uint32_t block_size
Definition: ald_nand.h:75
nand_handle_t::config
nand_device_cfg_t config
Definition: ald_nand.h:91
COLUMN_2ND_CYCLE
#define COLUMN_2ND_CYCLE(x)
Definition: ald_nand.h:143
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159
ADDR_3RD_CYCLE
#define ADDR_3RD_CYCLE(x)
Definition: ald_nand.h:140
NAND_DEVICE1
#define NAND_DEVICE1
Definition: ald_nand.h:103
COLUMN_ADDRESS
#define COLUMN_ADDRESS(x)
Definition: ald_nand.h:137
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
NAND_CMD_AREA_C
#define NAND_CMD_AREA_C
Definition: ald_nand.h:110
nand_device_cfg_t::spare_size
uint32_t spare_size
Definition: ald_nand.h:74
ADDR_2ND_CYCLE
#define ADDR_2ND_CYCLE(x)
Definition: ald_nand.h:139
nand_device_cfg_t::page_size
uint32_t page_size
Definition: ald_nand.h:73
NAND_CMD_WRITE0
#define NAND_CMD_WRITE0
Definition: ald_nand.h:112
ald_nand_read_status
uint32_t ald_nand_read_status(nand_handle_t *hperh)
NAND memory read status.
Definition: ald_nand.c:1147
COLUMN_1ST_CYCLE
#define COLUMN_1ST_CYCLE(x)
Definition: ald_nand.h:142
CMD_AREA
#define CMD_AREA
Definition: ald_nand.h:106
ADDR_1ST_CYCLE
#define ADDR_1ST_CYCLE(x)
Definition: ald_nand.h:138
__LOCK
#define __LOCK(x)
Definition: utils.h:92
nand_device_cfg_t::block_nbr
uint32_t block_nbr
Definition: ald_nand.h:76


ALD User Manual: NAND Control functions

Functions
NAND Control functions
EASTSOFT ES32F3xx ALD » NAND » NAND Public Functions

NAND Control functions. More...

Collaboration diagram for NAND Control functions:

Functions

void | ald_nand_irq_handler (nand_handle_t *hperh)
This function handles NAND device interrupt request. More...
__weak void | ald_nand_irq_cbk (nand_handle_t *hperh)
NAND interrupt feature callback. More...
uint32_t | ald_nand_address_inc (nand_handle_t *hperh, nand_address_t *addr)
Increment the NAND memory address. More...
uint32_t | ald_nand_read_status (nand_handle_t *hperh)
NAND memory read status. More...
ald_nand_state_t | ald_nand_get_state (nand_handle_t *hperh)
return the NAND state More...
ald_status_t | ald_nand_ecc_enable (nand_handle_t *hperh)
Enables dynamically NAND ECC feature. More...
ald_status_t | ald_nand_ecc_disable (nand_handle_t *hperh)
Disables dynamically FSMC_NAND ECC feature. More...
ald_status_t | ald_nand_get_ecc (nand_handle_t *hperh, uint32_t *val, uint32_t timeout)
Disables dynamically NAND ECC feature. More...

Detailed Description

NAND Control functions.

Function Documentation

◆ ald_nand_address_inc()

uint32_t ald_nand_address_inc | ( | nand_handle_t * | hperh,
 |  | nand_address_t * | addr
 | ) |  |

Increment the NAND memory address.

Parameters
hperh | pointer to a nand_handle_t structure
addr | pointer to NAND address structure
Return values
The new status of the increment address operation. It can be:
  • NAND_VALID_ADDRESS: When the new address is valid address
  • NAND_INVALID_ADDRESS: When the new address is invalid address

Definition at line 1119 of file ald_nand.c.

1120 {
1121 uint32_t status = NAND_VALID_ADDRESS;
1122
1123 addr->page++;
1124
1125 /* Check NAND address is valid */
1126 if (addr->page == hperh->config.block_size) {
1127 addr->page = 0;
1128 addr->block++;
1129
1130 if (addr->block == hperh->config.plane_size) {
1131 addr->block = 0;
1132 addr->plane++;
1133
1134 if (addr->plane == (hperh->config.plane_nbr))
1135 status = NAND_INVALID_ADDRESS;
1136 }
1137 }
1138
1139 return status;
1140 }
nand_device_cfg_t::plane_size
uint32_t plane_size
Definition: ald_nand.h:78
nand_address_t::block
uint16_t block
Definition: ald_nand.h:65
nand_address_t::page
uint16_t page
Definition: ald_nand.h:63
nand_address_t::plane
uint16_t plane
Definition: ald_nand.h:64
nand_device_cfg_t::block_size
uint32_t block_size
Definition: ald_nand.h:75
nand_handle_t::config
nand_device_cfg_t config
Definition: ald_nand.h:91
NAND_INVALID_ADDRESS
#define NAND_INVALID_ADDRESS
Definition: ald_nand.h:122
nand_device_cfg_t::plane_nbr
uint32_t plane_nbr
Definition: ald_nand.h:77
NAND_VALID_ADDRESS
#define NAND_VALID_ADDRESS
Definition: ald_nand.h:121

◆ ald_nand_ecc_disable()

ald_status_t ald_nand_ecc_disable ( nand_handle_t * hperh )

Disables dynamically FSMC_NAND ECC feature.

Parameters
hperh pointer to a nand_handle_t structure
Return values
ald status

Definition at line 1207 of file ald_nand.c.

1208 {
1209 if (hperh->state == ALD_NAND_STATE_BUSY)
1210 return BUSY;
1211
1212 /* Update the NAND state */
1213 hperh->state = ALD_NAND_STATE_BUSY;
1214 /* Disable ECC feature */
1215 ald_ebi_nand_ecc_disable(hperh->instance, hperh->init.bank);
1216 hperh->state = ALD_NAND_STATE_READY;
1217
1218 return OK;
1219 }
OK
Definition: utils.h:55
ald_ebi_nand_ecc_disable
void ald_ebi_nand_ecc_disable(EBI_NAND_TypeDef *dev, uint32_t bank)
Disables dynamically EBI_NAND ECC feature.
Definition: ald_ebi.c:509
BUSY
Definition: utils.h:57
nand_handle_t::init
ald_ebi_nand_init_t init
Definition: ald_nand.h:88
nand_handle_t::state
__IO ald_nand_state_t state
Definition: ald_nand.h:90
nand_handle_t::instance
EBI_NAND_TypeDef * instance
Definition: ald_nand.h:87
ALD_NAND_STATE_READY
Definition: ald_nand.h:43
ALD_NAND_STATE_BUSY
Definition: ald_nand.h:44
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159

◆ ald_nand_ecc_enable()

ald_status_t ald_nand_ecc_enable ( nand_handle_t * hperh )

Enables dynamically NAND ECC feature.

Parameters
hperh pointer to a nand_handle_t structure
Return values
ald status

Definition at line 1187 of file ald_nand.c.

1188 {
1189 if (hperh->state == ALD_NAND_STATE_BUSY)
1190 return BUSY;
1191
1192 /* Update the NAND state */
1193 hperh->state = ALD_NAND_STATE_BUSY;
1194 /* Enable ECC feature */
1195 ald_ebi_nand_ecc_enable(hperh->instance, hperh->init.bank);
1196 /* Update the NAND state */
1197 hperh->state = ALD_NAND_STATE_READY;
1198
1199 return OK;
1200 }
OK
Definition: utils.h:55
BUSY
Definition: utils.h:57
nand_handle_t::init
ald_ebi_nand_init_t init
Definition: ald_nand.h:88
nand_handle_t::state
__IO ald_nand_state_t state
Definition: ald_nand.h:90
nand_handle_t::instance
EBI_NAND_TypeDef * instance
Definition: ald_nand.h:87
ALD_NAND_STATE_READY
Definition: ald_nand.h:43
ALD_NAND_STATE_BUSY
Definition: ald_nand.h:44
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159
ald_ebi_nand_ecc_enable
void ald_ebi_nand_ecc_enable(EBI_NAND_TypeDef *dev, uint32_t bank)
Enables dynamically EBI_NAND ECC feature.
Definition: ald_ebi.c:491

◆ ald_nand_get_ecc()

ald_status_t ald_nand_get_ecc | ( | nand_handle_t * | hperh,
 |  | uint32_t * | val,
 |  | uint32_t | timeout
 | ) |  |

Disables dynamically NAND ECC feature.

Parameters
hperh | pointer to a nand_handle_t structure
val | pointer to ECC value
timeout | maximum timeout to wait
Return values
ald status

Definition at line 1228 of file ald_nand.c.

1229 {
1230 ald_status_t status = OK;
1231
1232 if (hperh->state == ALD_NAND_STATE_BUSY)
1233 return BUSY;
1234
1235 hperh->state = ALD_NAND_STATE_BUSY;
1236 status = ald_ebi_nand_get_ecc(hperh->instance, val, hperh->init.bank, timeout);
1237 hperh->state = ALD_NAND_STATE_READY;
1238
1239 return status;
1240 }
OK
Definition: utils.h:55
BUSY
Definition: utils.h:57
nand_handle_t::init
ald_ebi_nand_init_t init
Definition: ald_nand.h:88
nand_handle_t::state
__IO ald_nand_state_t state
Definition: ald_nand.h:90
nand_handle_t::instance
EBI_NAND_TypeDef * instance
Definition: ald_nand.h:87
ALD_NAND_STATE_READY
Definition: ald_nand.h:43
ALD_NAND_STATE_BUSY
Definition: ald_nand.h:44
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159
ald_ebi_nand_get_ecc
ald_status_t ald_ebi_nand_get_ecc(EBI_NAND_TypeDef *dev, uint32_t *val, uint32_t bank, uint32_t timeout)
Disables dynamically EBI_NAND ECC feature.
Definition: ald_ebi.c:529
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54

◆ ald_nand_get_state()

ald_nand_state_t ald_nand_get_state ( nand_handle_t * hperh )

return the NAND state

Parameters
hperh pointer to a nand_handle_t structure
Return values
ald state

Definition at line 1177 of file ald_nand.c.

1178 {
1179 return hperh->state;
1180 }
nand_handle_t::state
__IO ald_nand_state_t state
Definition: ald_nand.h:90

◆ ald_nand_irq_cbk()

void ald_nand_irq_cbk ( nand_handle_t * hperh )

NAND interrupt feature callback.

Parameters
hperh pointer to a nand_handle_t structure
Return values
None

Definition at line 1105 of file ald_nand.c.

1106 {
1107 /* Prevent unused argument(s) compilation warning */
1108 UNUSED(hperh);
1109 }
UNUSED
#define UNUSED(x)
Definition: type.h:76

◆ ald_nand_irq_handler()

void ald_nand_irq_handler ( nand_handle_t * hperh )

This function handles NAND device interrupt request.

Parameters
hperh pointer to a nand_handle_t structure
Return values
ald status

Definition at line 1073 of file ald_nand.c.

1074 {
1075 /* Check NAND interrupt Rising edge flag */
1076 if (ald_ebi_nand_get_flag(hperh->instance, hperh->init.bank, EBI_FLAG_RISING_EDGE)) {
1077 ald_nand_irq_cbk(hperh);
1078 ald_ebi_nand_clear_flag(hperh->instance, hperh->init.bank, EBI_FLAG_RISING_EDGE);
1079 }
1080
1081 /* Check NAND interrupt Level flag */
1082 if (ald_ebi_nand_get_flag(hperh->instance, hperh->init.bank, EBI_FLAG_LEVEL)) {
1083 ald_nand_irq_cbk(hperh);
1084 ald_ebi_nand_clear_flag(hperh->instance, hperh->init.bank, EBI_FLAG_LEVEL);
1085 }
1086
1087 if (ald_ebi_nand_get_flag(hperh->instance, hperh->init.bank, EBI_FLAG_FALLING_EDGE)) {
1088 /* NAND interrupt callback*/
1089 ald_nand_irq_cbk(hperh);
1090 ald_ebi_nand_clear_flag(hperh->instance, hperh->init.bank, EBI_FLAG_FALLING_EDGE);
1091 }
1092
1093 /* Check NAND interrupt FIFO empty flag */
1094 if (ald_ebi_nand_get_flag(hperh->instance, hperh->init.bank, EBI_FLAG_FEMPT)) {
1095 ald_nand_irq_cbk(hperh);
1096 ald_ebi_nand_clear_flag(hperh->instance, hperh->init.bank, EBI_FLAG_FEMPT);
1097 }
1098 }
EBI_FLAG_FEMPT
Definition: ald_ebi.h:318
nand_handle_t::init
ald_ebi_nand_init_t init
Definition: ald_nand.h:88
nand_handle_t::instance
EBI_NAND_TypeDef * instance
Definition: ald_nand.h:87
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159
EBI_FLAG_FALLING_EDGE
Definition: ald_ebi.h:317
ald_ebi_nand_get_flag
flag_status_t ald_ebi_nand_get_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
Get flag status of the NAND device.
Definition: ald_ebi.c:568
ald_ebi_nand_clear_flag
void ald_ebi_nand_clear_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
Clear flag status of the NAND device.
Definition: ald_ebi.c:596
ald_nand_irq_cbk
__weak void ald_nand_irq_cbk(nand_handle_t *hperh)
NAND interrupt feature callback.
Definition: ald_nand.c:1105
EBI_FLAG_LEVEL
Definition: ald_ebi.h:316
EBI_FLAG_RISING_EDGE
Definition: ald_ebi.h:315

◆ ald_nand_read_status()

uint32_t ald_nand_read_status ( nand_handle_t * hperh )

NAND memory read status.

Parameters
hperh pointer to a nand_handle_t structure
Return values
NAND status

Definition at line 1147 of file ald_nand.c.

1148 {
1149 uint32_t data = 0;
1150 uint32_t addr = 0;
1151
1152 /* Identify the device address */
1153 if (hperh->init.bank == EBI_NAND_BANK2)
1154 addr = NAND_DEVICE1;
1155 else
1156 addr = NAND_DEVICE2;
1157
1158 /* Send Read status operation command */
1159 *(__IO uint8_t *)((uint32_t)(addr | CMD_AREA)) = NAND_CMD_STATUS;
1160 /* Read status register data */
1161 data = *(__IO uint8_t *)addr;
1162
1163 /* Return the status */
1164 if ((data & NAND_ERROR) == NAND_ERROR)
1165 return NAND_ERROR;
1166 else if ((data & NAND_READY) == NAND_READY)
1167 return NAND_READY;
1168
1169 return NAND_BUSY;
1170 }
NAND_BUSY
#define NAND_BUSY
Definition: ald_nand.h:124
NAND_ERROR
#define NAND_ERROR
Definition: ald_nand.h:125
nand_handle_t::init
ald_ebi_nand_init_t init
Definition: ald_nand.h:88
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
NAND_READY
#define NAND_READY
Definition: ald_nand.h:126
NAND_DEVICE2
#define NAND_DEVICE2
Definition: ald_nand.h:104
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159
NAND_DEVICE1
#define NAND_DEVICE1
Definition: ald_nand.h:103
NAND_CMD_STATUS
#define NAND_CMD_STATUS
Definition: ald_nand.h:117
CMD_AREA
#define CMD_AREA
Definition: ald_nand.h:106


ALD User Manual: NAND Public Types

Data Structures | Enumerations
NAND Public Types
EASTSOFT ES32F3xx ALD » NAND
Collaboration diagram for NAND Public Types:

Data Structures

struct | nand_id_t
NAND Memory electronic signature Structure definition. More...
struct | nand_address_t
NAND Memory address Structure definition. More...
struct | nand_device_cfg_t
NAND Memory info Structure definition. More...
struct | nand_handle_t
NAND handle Structure definition. More...

Enumerations

enum ald_nand_state_t { ALD_NAND_STATE_RESET = 0x00U, ALD_NAND_STATE_READY = 0x01U, ALD_NAND_STATE_BUSY = 0x02U, ALD_NAND_STATE_ERROR = 0x03U }
NAND State structures definition. More...

Detailed Description

Enumeration Type Documentation

◆ ald_nand_state_t

enum ald_nand_state_t

NAND State structures definition.

Enumerator
ALD_NAND_STATE_RESET | NAND not yet initialized or disabled
ALD_NAND_STATE_READY | NAND initialized and ready for use
ALD_NAND_STATE_BUSY | NAND internal process is ongoing
ALD_NAND_STATE_ERROR | NAND error state

Definition at line 41 of file ald_nand.h.

41 {
42 ALD_NAND_STATE_RESET = 0x00U,
43 ALD_NAND_STATE_READY = 0x01U,
44 ALD_NAND_STATE_BUSY = 0x02U,
45 ALD_NAND_STATE_ERROR = 0x03U
46 } ald_nand_state_t;
ALD_NAND_STATE_READY
Definition: ald_nand.h:43
ALD_NAND_STATE_BUSY
Definition: ald_nand.h:44
ald_nand_state_t
ald_nand_state_t
NAND State structures definition.
Definition: ald_nand.h:41
ALD_NAND_STATE_ERROR
Definition: ald_nand.h:45
ALD_NAND_STATE_RESET
Definition: ald_nand.h:42


ALD User Manual: nand_id_t Struct Reference

Data Fields
nand_id_t Struct Reference
EASTSOFT ES32F3xx ALD » NAND » NAND Public Types

NAND Memory electronic signature Structure definition. More...

#include <ald_nand.h>

Data Fields

uint8_t | maker_id
uint8_t | device_id
uint8_t | third_id
uint8_t | fourth_id

Detailed Description

NAND Memory electronic signature Structure definition.

Definition at line 51 of file ald_nand.h.

Field Documentation

◆ device_id

uint8_t device_id

Device id

Definition at line 53 of file ald_nand.h.

◆ fourth_id

uint8_t fourth_id

Fourth id

Definition at line 55 of file ald_nand.h.

◆ maker_id

uint8_t maker_id

Maker id

Definition at line 52 of file ald_nand.h.

◆ third_id

uint8_t third_id

Third id

Definition at line 54 of file ald_nand.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_nand.h


ALD User Manual: nand_address_t Struct Reference

Data Fields
nand_address_t Struct Reference
EASTSOFT ES32F3xx ALD » NAND » NAND Public Types

NAND Memory address Structure definition. More...

#include <ald_nand.h>

Data Fields

uint16_t | page
uint16_t | plane
uint16_t | block

Detailed Description

NAND Memory address Structure definition.

Definition at line 61 of file ald_nand.h.

Field Documentation

◆ block

uint16_t block

NAND memory Block address

Definition at line 65 of file ald_nand.h.

◆ page

uint16_t page

NAND memory Page address

Definition at line 63 of file ald_nand.h.

◆ plane

uint16_t plane

NAND memory Plane address

Definition at line 64 of file ald_nand.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_nand.h


ALD User Manual: nand_device_cfg_t Struct Reference

Data Fields
nand_device_cfg_t Struct Reference
EASTSOFT ES32F3xx ALD » NAND » NAND Public Types

NAND Memory info Structure definition. More...

#include <ald_nand.h>

Data Fields

uint32_t | page_size
uint32_t | spare_size
uint32_t | block_size
uint32_t | block_nbr
uint32_t | plane_nbr
uint32_t | plane_size
type_func_t extra_cmd

Detailed Description

NAND Memory info Structure definition.

Definition at line 71 of file ald_nand.h.

Field Documentation

◆ block_nbr

uint32_t block_nbr

NAND memory number of total block

Definition at line 76 of file ald_nand.h.

◆ block_size

uint32_t block_size

NAND memory block size measured in number of pages

Definition at line 75 of file ald_nand.h.

◆ extra_cmd

type_func_t extra_cmd

NAND extra command needed for Page reading mode

Definition at line 79 of file ald_nand.h.

◆ page_size

uint32_t page_size

NAND memory page (without spare area) size measured in bytes

Definition at line 73 of file ald_nand.h.

◆ plane_nbr

uint32_t plane_nbr

NAND memory number of planes

Definition at line 77 of file ald_nand.h.

◆ plane_size

uint32_t plane_size

NAND memory plane size measured in number of blocks

Definition at line 78 of file ald_nand.h.

◆ spare_size

uint32_t spare_size

NAND memory spare area size measured in bytes

Definition at line 74 of file ald_nand.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_nand.h


ALD User Manual: nand_handle_t Struct Reference

Data Fields
nand_handle_t Struct Reference
EASTSOFT ES32F3xx ALD » NAND » NAND Public Types

NAND handle Structure definition. More...

#include <ald_nand.h>

Collaboration diagram for nand_handle_t:
[legend]

Data Fields

EBI_NAND_TypeDef * instance
ald_ebi_nand_init_t init
lock_state_t lock
__IO ald_nand_state_t state
nand_device_cfg_t config

Detailed Description

NAND handle Structure definition.

Definition at line 85 of file ald_nand.h.

Field Documentation

◆ config

nand_device_cfg_t config

NAND phusical characteristic information structure

Definition at line 91 of file ald_nand.h.

◆ init

ald_ebi_nand_init_t init

NAND device control configuration parameters

Definition at line 88 of file ald_nand.h.

◆ instance

EBI_NAND_TypeDef* instance

Register base address

Definition at line 87 of file ald_nand.h.

◆ lock

lock_state_t lock

NAND locking object

Definition at line 89 of file ald_nand.h.

◆ state

__IO ald_nand_state_t state

NAND device access state

Definition at line 90 of file ald_nand.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_nand.h


ALD User Manual: Nand Private Constants

Macros
Nand Private Constants
EASTSOFT ES32F3xx ALD » NAND
Collaboration diagram for Nand Private Constants:

Macros

#define | NAND_DEVICE1 EBI_BANK2
#define | NAND_DEVICE2 EBI_BANK3
#define | NAND_WRITE_TIMEOUT 1000U
#define | CMD_AREA (1U<<16U) /* A16 = CLE high */
#define | ADDR_AREA (1U<<17U) /* A17 = ALE high */
#define | NAND_CMD_AREA_A ((uint8_t)0x00U)
#define | NAND_CMD_AREA_B ((uint8_t)0x01U)
#define | NAND_CMD_AREA_C ((uint8_t)0x50U)
#define | NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
#define | NAND_CMD_WRITE0 ((uint8_t)0x80U)
#define | NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
#define | NAND_CMD_ERASE0 ((uint8_t)0x60U)
#define | NAND_CMD_ERASE1 ((uint8_t)0xD0U)
#define | NAND_CMD_READID ((uint8_t)0x90U)
#define | NAND_CMD_STATUS ((uint8_t)0x70U)
#define | NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
#define | NAND_CMD_RESET ((uint8_t)0xFFU)
#define | NAND_VALID_ADDRESS 0x00000100U
#define | NAND_INVALID_ADDRESS 0x00000200U
#define | NAND_TIMEOUT_ERROR 0x00000400U
#define | NAND_BUSY 0x00000000U
#define | NAND_ERROR 0x00000001U
#define | NAND_READY 0x00000040U

Detailed Description

Macro Definition Documentation

◆ ADDR_AREA

#define ADDR_AREA (1U<<17U) /* A17 = ALE high */

Definition at line 107 of file ald_nand.h.

◆ CMD_AREA

#define CMD_AREA (1U<<16U) /* A16 = CLE high */

Definition at line 106 of file ald_nand.h.

◆ NAND_BUSY

#define NAND_BUSY 0x00000000U

Definition at line 124 of file ald_nand.h.

◆ NAND_CMD_AREA_A

#define NAND_CMD_AREA_A ((uint8_t)0x00U)

Definition at line 108 of file ald_nand.h.

◆ NAND_CMD_AREA_B

#define NAND_CMD_AREA_B ((uint8_t)0x01U)

Definition at line 109 of file ald_nand.h.

◆ NAND_CMD_AREA_C

#define NAND_CMD_AREA_C ((uint8_t)0x50U)

Definition at line 110 of file ald_nand.h.

◆ NAND_CMD_AREA_TRUE1

#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)

Definition at line 111 of file ald_nand.h.

◆ NAND_CMD_ERASE0

#define NAND_CMD_ERASE0 ((uint8_t)0x60U)

Definition at line 114 of file ald_nand.h.

◆ NAND_CMD_ERASE1

#define NAND_CMD_ERASE1 ((uint8_t)0xD0U)

Definition at line 115 of file ald_nand.h.

◆ NAND_CMD_LOCK_STATUS

#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)

Definition at line 118 of file ald_nand.h.

◆ NAND_CMD_READID

#define NAND_CMD_READID ((uint8_t)0x90U)

Definition at line 116 of file ald_nand.h.

◆ NAND_CMD_RESET

#define NAND_CMD_RESET ((uint8_t)0xFFU)

Definition at line 119 of file ald_nand.h.

◆ NAND_CMD_STATUS

#define NAND_CMD_STATUS ((uint8_t)0x70U)

Definition at line 117 of file ald_nand.h.

◆ NAND_CMD_WRITE0

#define NAND_CMD_WRITE0 ((uint8_t)0x80U)

Definition at line 112 of file ald_nand.h.

◆ NAND_CMD_WRITE_TRUE1

#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)

Definition at line 113 of file ald_nand.h.

◆ NAND_DEVICE1

#define NAND_DEVICE1 EBI_BANK2

Definition at line 103 of file ald_nand.h.

◆ NAND_DEVICE2

#define NAND_DEVICE2 EBI_BANK3

Definition at line 104 of file ald_nand.h.

◆ NAND_ERROR

#define NAND_ERROR 0x00000001U

Definition at line 125 of file ald_nand.h.

◆ NAND_INVALID_ADDRESS

#define NAND_INVALID_ADDRESS 0x00000200U

Definition at line 122 of file ald_nand.h.

◆ NAND_READY

#define NAND_READY 0x00000040U

Definition at line 126 of file ald_nand.h.

◆ NAND_TIMEOUT_ERROR

#define NAND_TIMEOUT_ERROR 0x00000400U

Definition at line 123 of file ald_nand.h.

◆ NAND_VALID_ADDRESS

#define NAND_VALID_ADDRESS 0x00000100U

Definition at line 121 of file ald_nand.h.

◆ NAND_WRITE_TIMEOUT

#define NAND_WRITE_TIMEOUT 1000U

Definition at line 105 of file ald_nand.h.


ALD User Manual: Nand Private Macros

Macros
Nand Private Macros
EASTSOFT ES32F3xx ALD » NAND
Collaboration diagram for Nand Private Macros:

Macros

#define | ARRAY_ADDRESS(x, y)
#define | COLUMN_ADDRESS(x) ((x)->config.page_size)
#define | ADDR_1ST_CYCLE(x) (uint8_t)(x) /* 1st addressing cycle */
#define | ADDR_2ND_CYCLE(x) (uint8_t)((x) >> 8U) /* 2nd addressing cycle */
#define | ADDR_3RD_CYCLE(x) (uint8_t)((x) >> 16U) /* 3rd addressing cycle */
#define | ADDR_4TH_CYCLE(x) (uint8_t)((x) >> 24U) /* 4th addressing cycle */
#define | COLUMN_1ST_CYCLE(x) (uint8_t)(x) /* 1st Column addressing cycle */
#define | COLUMN_2ND_CYCLE(x) (uint8_t)((x) >> 8U) /* 2nd Column addressing cycle */

Detailed Description

Macro Definition Documentation

◆ ADDR_1ST_CYCLE

#define ADDR_1ST_CYCLE ( x ) (uint8_t)(x) /* 1st addressing cycle */

Definition at line 138 of file ald_nand.h.

◆ ADDR_2ND_CYCLE

#define ADDR_2ND_CYCLE ( x ) (uint8_t)((x) >> 8U) /* 2nd addressing cycle */

Definition at line 139 of file ald_nand.h.

◆ ADDR_3RD_CYCLE

#define ADDR_3RD_CYCLE ( x ) (uint8_t)((x) >> 16U) /* 3rd addressing cycle */

Definition at line 140 of file ald_nand.h.

◆ ADDR_4TH_CYCLE

#define ADDR_4TH_CYCLE ( x ) (uint8_t)((x) >> 24U) /* 4th addressing cycle */

Definition at line 141 of file ald_nand.h.

◆ ARRAY_ADDRESS

#define ARRAY_ADDRESS | ( | x,
 |  | y
 | ) |
Value:
((x)->page + \
(((x)->block + (((x)->plane) * \
((y)->config.plane_size))) * ((y)->config.block_size)))

Definition at line 134 of file ald_nand.h.

◆ COLUMN_1ST_CYCLE

#define COLUMN_1ST_CYCLE ( x ) (uint8_t)(x) /* 1st Column addressing cycle */

Definition at line 142 of file ald_nand.h.

◆ COLUMN_2ND_CYCLE

#define COLUMN_2ND_CYCLE ( x ) (uint8_t)((x) >> 8U) /* 2nd Column addressing cycle */

Definition at line 143 of file ald_nand.h.

◆ COLUMN_ADDRESS

#define COLUMN_ADDRESS ( x ) ((x)->config.page_size)

Definition at line 137 of file ald_nand.h.


ALD User Manual: NOR_LCD

Modules
NOR_LCD
EASTSOFT ES32F3xx ALD

NOR_LCD driver modules. More...

Collaboration diagram for NOR_LCD:

Modules

NOR_LCD Private Variables
NOR_LCD Public Functions
NOR_LCD public functions.
NOR LCD Private Constants
NOR_LCD Private Macros
NOR_LCD Public Types
NOR_Public_Functions

Detailed Description

NOR_LCD driver modules.


ALD User Manual: NOR_LCD Private Variables

Variables
NOR_LCD Private Variables
EASTSOFT ES32F3xx ALD » NOR_LCD
Collaboration diagram for NOR_LCD Private Variables:

Variables

static uint32_t NORMEMDATWIDTH = NOR_MEMORY_8B

Detailed Description

Variable Documentation

◆ NORMEMDATWIDTH

uint32_t NORMEMDATWIDTH = NOR_MEMORY_8B
static

Definition at line 33 of file ald_nor_lcd.c.


ALD User Manual: NOR_LCD Public Functions

Modules
NOR_LCD Public Functions
EASTSOFT ES32F3xx ALD » NOR_LCD

NOR_LCD public functions. More...

Collaboration diagram for NOR_LCD Public Functions:

Modules

Initialization functions
NOR_LCD Initialization functions.
I/O operation functions
NOR_LCD I/O operation functions.
Control functions
NOR_LCD Control functions.
State functions
NOR_LCD State functions.

Detailed Description

NOR_LCD public functions.


ALD User Manual: Initialization functions

Functions
Initialization functions
EASTSOFT ES32F3xx ALD » NOR_LCD » NOR_LCD Public Functions

NOR_LCD Initialization functions. More...

Collaboration diagram for Initialization functions:

Functions

ald_status_t | ald_nor_init (nor_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing)
Perform the NOR memory Initialization sequence. More...
ald_status_t | ald_nor_deinit (nor_handle_t *hperh)
Perform NOR memory De-Initialization sequence. More...

Detailed Description

NOR_LCD Initialization functions.

Function Documentation

◆ ald_nor_deinit()

ald_status_t ald_nor_deinit ( nor_handle_t * hperh )

Perform NOR memory De-Initialization sequence.

Parameters
hperh pointer to a nor_handle_t structure
Return values
ald status

Definition at line 84 of file ald_nor_lcd.c.

85 {
86 ald_ebi_nor_sram_deinit(hperh->instance, hperh->ext, hperh->init.bank);
87 hperh->state = ALD_NOR_STATE_RESET;
88 __UNLOCK(hperh);
89
90 return OK;
91 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
ald_ebi_nor_sram_deinit
ald_status_t ald_ebi_nor_sram_deinit(EBI_NOR_SRAM_TypeDef *dev, EBI_NOR_SRAM_EXTENDED_TypeDef *e_dev, uint32_t bank)
DeInitialize the EBI_NOR_SRAM peripheral.
Definition: ald_ebi.c:172
nor_handle_t::instance
EBI_NOR_SRAM_TypeDef * instance
Definition: ald_nor_lcd.h:151
nor_handle_t::state
__IO ald_nor_state_t state
Definition: ald_nor_lcd.h:155
nor_handle_t::ext
EBI_NOR_SRAM_EXTENDED_TypeDef * ext
Definition: ald_nor_lcd.h:152
ALD_NOR_STATE_RESET
Definition: ald_nor_lcd.h:110
nor_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_nor_lcd.h:153
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399

◆ ald_nor_init()

ald_status_t ald_nor_init | ( | nor_handle_t * | hperh,
 |  | ald_ebi_nor_sram_timing_t * | timing,
 |  | ald_ebi_nor_sram_timing_t * | ext_timing
 | ) |  |

Perform the NOR memory Initialization sequence.

Parameters
hperh | pointer to a nor_handle_t structure
timing | pointer to NOR control timing structure
ext_timing | pointer to NOR extended mode timing structure
Return values
ald status

Definition at line 53 of file ald_nor_lcd.c.

54 {
55 if (hperh == NULL)
56 return ERROR;
57 if (hperh->state == ALD_NOR_STATE_RESET)
58 hperh->lock = UNLOCK;
59
60 /* Initialize NOR control Interface */
61 ald_ebi_nor_sram_init(hperh->instance, &(hperh->init));
62 /* Initialize NOR timing Interface */
63 ald_ebi_nor_sram_timing_init(hperh->instance, timing, hperh->init.bank);
64 /* Initialize NOR extended mode timing Interface */
65 ald_ebi_nor_sram_ext_timing_init(hperh->ext, ext_timing, hperh->init.bank, hperh->init.ext_mode);
66 /* Enable the NORSRAM device */
67 ald_ebi_nor_sram_enable(hperh->instance, hperh->init.bank);
68
69 /* Initialize NOR Memory Data Width*/
70 if (hperh->init.width == EBI_NORSRAM_MEM_BUS_WIDTH_8)
71 NORMEMDATWIDTH = NOR_MEMORY_8B;
72 else
73 NORMEMDATWIDTH = NOR_MEMORY_16B;
74
75 hperh->state = ALD_NOR_STATE_READY;
76 return OK;
77 }
ALD_NOR_STATE_READY
Definition: ald_nor_lcd.h:111
OK
Definition: utils.h:55
UNLOCK
Definition: type.h:59
ald_ebi_nor_sram_init_t::ext_mode
ebi_extended_mode_t ext_mode
Definition: ald_ebi.h:409
ald_ebi_nor_sram_timing_init
void ald_ebi_nor_sram_timing_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank)
Initialize the EBI_NOR_SRAM Timing according to the specified parameters in the EBI_NOR_SRAM_TimingTy...
Definition: ald_ebi.c:104
NORMEMDATWIDTH
static uint32_t NORMEMDATWIDTH
Definition: ald_nor_lcd.c:33
nor_handle_t::lock
lock_state_t lock
Definition: ald_nor_lcd.h:154
nor_handle_t::instance
EBI_NOR_SRAM_TypeDef * instance
Definition: ald_nor_lcd.h:151
EBI_NORSRAM_MEM_BUS_WIDTH_8
Definition: ald_ebi.h:209
nor_handle_t::state
__IO ald_nor_state_t state
Definition: ald_nor_lcd.h:155
nor_handle_t::ext
EBI_NOR_SRAM_EXTENDED_TypeDef * ext
Definition: ald_nor_lcd.h:152
ALD_NOR_STATE_RESET
Definition: ald_nor_lcd.h:110
NOR_MEMORY_16B
#define NOR_MEMORY_16B
Definition: ald_nor_lcd.h:56
ald_ebi_nor_sram_init
void ald_ebi_nor_sram_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_init_t *init)
Initialize the EBI_NOR_SRAM device according to the specified control parameters in the EBI_NOR_SRAM_...
Definition: ald_ebi.c:43
ald_ebi_nor_sram_init_t::width
ebi_norsram_mem_bus_width_t width
Definition: ald_ebi.h:402
NOR_MEMORY_8B
#define NOR_MEMORY_8B
Definition: ald_nor_lcd.h:55
nor_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_nor_lcd.h:153
ERROR
Definition: utils.h:56
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399
ald_ebi_nor_sram_enable
void ald_ebi_nor_sram_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Enable the NOR/SRAM device access.
Definition: ald_ebi.c:206
ald_ebi_nor_sram_ext_timing_init
void ald_ebi_nor_sram_ext_timing_init(EBI_NOR_SRAM_EXTENDED_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank, uint32_t mode)
Initialize the EBI_NOR_SRAM Extended mode Timing according to the specified parameters in the EBI_NOR...
Definition: ald_ebi.c:138


ALD User Manual: I/O operation functions

Functions
I/O operation functions
EASTSOFT ES32F3xx ALD » NOR_LCD » NOR_LCD Public Functions EASTSOFT ES32F3xx ALD » NOR_LCD » | NOR_Public_Functions

NOR_LCD I/O operation functions. More...

Collaboration diagram for I/O operation functions:

Functions

ald_status_t | ald_nor_read_id (nor_handle_t *hperh, nor_id_t *id)
Read NOR flash IDs. More...
ald_status_t | ald_nor_return_readmode (nor_handle_t *hperh)
Returns the NOR memory to Read mode. More...
ald_status_t | ald_nor_read (nor_handle_t *hperh, uint32_t *addr, uint16_t *data)
Read data from NOR memory. More...
ald_status_t | ald_nor_program (nor_handle_t *hperh, uint32_t *addr, uint16_t *data)
Program data to NOR memory. More...
ald_status_t | ald_nor_read_buffer (nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size)
Reads a block of data from the EBI NOR memory. More...
ald_status_t | ald_nor_program_buffer (nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size)
Writes a half-word buffer to the EBI NOR memory. More...
ald_status_t | ald_nor_erase_block (nor_handle_t *hperh, uint32_t blkaddr, uint32_t addr)
Erase the specified block of the NOR memory. More...
ald_status_t | ald_nor_erase_chip (nor_handle_t *hperh)
Erase the entire NOR chip. More...
ald_status_t | ald_nor_read_cfi (nor_handle_t *hperh, nor_cfi_t *cfi)
Read NOR flash CFI IDs. More...

Detailed Description

NOR_LCD I/O operation functions.

Function Documentation

◆ ald_nor_erase_block()

ald_status_t ald_nor_erase_block | ( | nor_handle_t * | hperh,
 |  | uint32_t | blkaddr,
 |  | uint32_t | addr
 | ) |  |

Erase the specified block of the NOR memory.

Parameters
hperh | pointer to a nor_handle_t structure
blkaddr | : block to erase address
addr | device address
Return values
ald status

Definition at line 366 of file ald_nor_lcd.c.

367 {
368 uint32_t devaddr = 0;
369
370 __LOCK(hperh);
371
372 if (hperh->state == ALD_NOR_STATE_BUSY)
373 return BUSY;
374
375 if (hperh->init.bank == EBI_NORSRAM_BANK1)
376 devaddr = NOR_MEMORY_ADRESS1;
377 else if (hperh->init.bank == EBI_NORSRAM_BANK2)
378 devaddr = NOR_MEMORY_ADRESS2;
379 else if (hperh->init.bank == EBI_NORSRAM_BANK3)
380 devaddr = NOR_MEMORY_ADRESS3;
381 else
382 devaddr = NOR_MEMORY_ADRESS4;
383
384 hperh->state = ALD_NOR_STATE_BUSY;
385
386 /* Send block erase command sequence */
387 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
388 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
389 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
390 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
391 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
392 NOR_WRITE((uint32_t)(blkaddr + addr), NOR_CMD_DATA_BLOCK_ERASE);
393
394 hperh->state = ALD_NOR_STATE_READY;
395 __UNLOCK(hperh);
396
397 return OK;
398
399 }
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH
#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH
Definition: ald_nor_lcd.h:79
ALD_NOR_STATE_READY
Definition: ald_nor_lcd.h:111
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
NOR_MEMORY_ADRESS1
#define NOR_MEMORY_ADRESS1
Definition: ald_nor_lcd.h:59
BUSY
Definition: utils.h:57
ALD_NOR_STATE_BUSY
Definition: ald_nor_lcd.h:112
EBI_NORSRAM_BANK2
Definition: ald_ebi.h:191
NOR_CMD_ADDRESS_FIFTH
#define NOR_CMD_ADDRESS_FIFTH
Definition: ald_nor_lcd.h:69
NOR_MEMORY_ADRESS3
#define NOR_MEMORY_ADRESS3
Definition: ald_nor_lcd.h:61
NOR_CMD_ADDRESS_SECOND
#define NOR_CMD_ADDRESS_SECOND
Definition: ald_nor_lcd.h:66
EBI_NORSRAM_BANK3
Definition: ald_ebi.h:192
NOR_CMD_ADDRESS_FIRST
#define NOR_CMD_ADDRESS_FIRST
Definition: ald_nor_lcd.h:64
NORMEMDATWIDTH
static uint32_t NORMEMDATWIDTH
Definition: ald_nor_lcd.c:33
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD
#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD
Definition: ald_nor_lcd.h:77
NOR_CMD_DATA_FIRST
#define NOR_CMD_DATA_FIRST
Definition: ald_nor_lcd.h:73
NOR_MEMORY_ADRESS2
#define NOR_MEMORY_ADRESS2
Definition: ald_nor_lcd.h:60
NOR_WRITE
#define NOR_WRITE(ADDR, DATA)
Definition: ald_nor_lcd.h:98
NOR_ADDR_SHIFT
#define NOR_ADDR_SHIFT(NOR_ADDR, NOR_MEMORY_WIDTH_, ADDRESS)
Definition: ald_nor_lcd.h:94
NOR_MEMORY_ADRESS4
#define NOR_MEMORY_ADRESS4
Definition: ald_nor_lcd.h:62
NOR_CMD_ADDRESS_THIRD
#define NOR_CMD_ADDRESS_THIRD
Definition: ald_nor_lcd.h:67
nor_handle_t::state
__IO ald_nor_state_t state
Definition: ald_nor_lcd.h:155
NOR_CMD_ADDRESS_FOURTH
#define NOR_CMD_ADDRESS_FOURTH
Definition: ald_nor_lcd.h:68
NOR_CMD_DATA_SECOND
#define NOR_CMD_DATA_SECOND
Definition: ald_nor_lcd.h:74
NOR_CMD_DATA_BLOCK_ERASE
#define NOR_CMD_DATA_BLOCK_ERASE
Definition: ald_nor_lcd.h:84
nor_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_nor_lcd.h:153
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH
#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH
Definition: ald_nor_lcd.h:78
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399
EBI_NORSRAM_BANK1
Definition: ald_ebi.h:190

◆ ald_nor_erase_chip()

ald_status_t ald_nor_erase_chip ( nor_handle_t * hperh )

Erase the entire NOR chip.

Parameters
hperh pointer to a nor_handle_t structure
Return values
ald status

Definition at line 406 of file ald_nor_lcd.c.

407 {
408 uint32_t devaddr = 0;
409
410 __LOCK(hperh);
411
412 if (hperh->state == ALD_NOR_STATE_BUSY)
413 return BUSY;
414
415 /* Select the NOR device address */
416 if (hperh->init.bank == EBI_NORSRAM_BANK1)
417 devaddr = NOR_MEMORY_ADRESS1;
418 else if (hperh->init.bank == EBI_NORSRAM_BANK2)
419 devaddr = NOR_MEMORY_ADRESS2;
420 else if (hperh->init.bank == EBI_NORSRAM_BANK3)
421 devaddr = NOR_MEMORY_ADRESS3;
422 else
423 devaddr = NOR_MEMORY_ADRESS4;
424
425 hperh->state = ALD_NOR_STATE_BUSY;
426
427 /* Send NOR chip erase command sequence */
428 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
429 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
430 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
431 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
432 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
433 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
434
435 hperh->state = ALD_NOR_STATE_READY;
436 __UNLOCK(hperh);
437
438 return OK;
439 }
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH
#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH
Definition: ald_nor_lcd.h:79
NOR_CMD_ADDRESS_SIXTH
#define NOR_CMD_ADDRESS_SIXTH
Definition: ald_nor_lcd.h:70
ALD_NOR_STATE_READY
Definition: ald_nor_lcd.h:111
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
NOR_MEMORY_ADRESS1
#define NOR_MEMORY_ADRESS1
Definition: ald_nor_lcd.h:59
BUSY
Definition: utils.h:57
ALD_NOR_STATE_BUSY
Definition: ald_nor_lcd.h:112
EBI_NORSRAM_BANK2
Definition: ald_ebi.h:191
NOR_CMD_ADDRESS_FIFTH
#define NOR_CMD_ADDRESS_FIFTH
Definition: ald_nor_lcd.h:69
NOR_MEMORY_ADRESS3
#define NOR_MEMORY_ADRESS3
Definition: ald_nor_lcd.h:61
NOR_CMD_ADDRESS_SECOND
#define NOR_CMD_ADDRESS_SECOND
Definition: ald_nor_lcd.h:66
EBI_NORSRAM_BANK3
Definition: ald_ebi.h:192
NOR_CMD_ADDRESS_FIRST
#define NOR_CMD_ADDRESS_FIRST
Definition: ald_nor_lcd.h:64
NORMEMDATWIDTH
static uint32_t NORMEMDATWIDTH
Definition: ald_nor_lcd.c:33
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD
#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD
Definition: ald_nor_lcd.h:77
NOR_CMD_DATA_FIRST
#define NOR_CMD_DATA_FIRST
Definition: ald_nor_lcd.h:73
NOR_MEMORY_ADRESS2
#define NOR_MEMORY_ADRESS2
Definition: ald_nor_lcd.h:60
NOR_CMD_DATA_CHIP_ERASE
#define NOR_CMD_DATA_CHIP_ERASE
Definition: ald_nor_lcd.h:80
NOR_WRITE
#define NOR_WRITE(ADDR, DATA)
Definition: ald_nor_lcd.h:98
NOR_ADDR_SHIFT
#define NOR_ADDR_SHIFT(NOR_ADDR, NOR_MEMORY_WIDTH_, ADDRESS)
Definition: ald_nor_lcd.h:94
NOR_MEMORY_ADRESS4
#define NOR_MEMORY_ADRESS4
Definition: ald_nor_lcd.h:62
NOR_CMD_ADDRESS_THIRD
#define NOR_CMD_ADDRESS_THIRD
Definition: ald_nor_lcd.h:67
nor_handle_t::state
__IO ald_nor_state_t state
Definition: ald_nor_lcd.h:155
NOR_CMD_ADDRESS_FOURTH
#define NOR_CMD_ADDRESS_FOURTH
Definition: ald_nor_lcd.h:68
NOR_CMD_DATA_SECOND
#define NOR_CMD_DATA_SECOND
Definition: ald_nor_lcd.h:74
nor_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_nor_lcd.h:153
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH
#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH
Definition: ald_nor_lcd.h:78
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399
EBI_NORSRAM_BANK1
Definition: ald_ebi.h:190

◆ ald_nor_program()

ald_status_t ald_nor_program | ( | nor_handle_t * | hperh,
 |  | uint32_t * | addr,
 |  | uint16_t * | data
 | ) |  |

Program data to NOR memory.

Parameters
hperh | pointer to a nor_handle_t structure
addr | device address
data | pointer to the data to write
Return values
ald status

Definition at line 221 of file ald_nor_lcd.c.

222 {
223 uint32_t devaddr = 0;
224
225 __LOCK(hperh);
226
227 if (hperh->state == ALD_NOR_STATE_BUSY)
228 return BUSY;
229
230 /* Select the NOR device address */
231 if (hperh->init.bank == EBI_NORSRAM_BANK1)
232 devaddr = NOR_MEMORY_ADRESS1;
233 else if (hperh->init.bank == EBI_NORSRAM_BANK2)
234 devaddr = NOR_MEMORY_ADRESS2;
235 else if (hperh->init.bank == EBI_NORSRAM_BANK3)
236 devaddr = NOR_MEMORY_ADRESS3;
237 else /* EBI_NORSRAM_BANK4 */
238 devaddr = NOR_MEMORY_ADRESS4;
239
240 hperh->state = ALD_NOR_STATE_BUSY;
241
242 /* Send program data command */
243 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
244 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
245 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
246
247 /* Write the data */
248 NOR_WRITE(addr, *data);
249 hperh->state = ALD_NOR_STATE_READY;
250 __UNLOCK(hperh);
251
252 return OK;
253 }
ALD_NOR_STATE_READY
Definition: ald_nor_lcd.h:111
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
NOR_MEMORY_ADRESS1
#define NOR_MEMORY_ADRESS1
Definition: ald_nor_lcd.h:59
BUSY
Definition: utils.h:57
ALD_NOR_STATE_BUSY
Definition: ald_nor_lcd.h:112
EBI_NORSRAM_BANK2
Definition: ald_ebi.h:191
NOR_MEMORY_ADRESS3
#define NOR_MEMORY_ADRESS3
Definition: ald_nor_lcd.h:61
NOR_CMD_ADDRESS_SECOND
#define NOR_CMD_ADDRESS_SECOND
Definition: ald_nor_lcd.h:66
EBI_NORSRAM_BANK3
Definition: ald_ebi.h:192
NOR_CMD_ADDRESS_FIRST
#define NOR_CMD_ADDRESS_FIRST
Definition: ald_nor_lcd.h:64
NORMEMDATWIDTH
static uint32_t NORMEMDATWIDTH
Definition: ald_nor_lcd.c:33
NOR_CMD_DATA_FIRST
#define NOR_CMD_DATA_FIRST
Definition: ald_nor_lcd.h:73
NOR_MEMORY_ADRESS2
#define NOR_MEMORY_ADRESS2
Definition: ald_nor_lcd.h:60
NOR_CMD_DATA_PROGRAM
#define NOR_CMD_DATA_PROGRAM
Definition: ald_nor_lcd.h:76
NOR_WRITE
#define NOR_WRITE(ADDR, DATA)
Definition: ald_nor_lcd.h:98
NOR_ADDR_SHIFT
#define NOR_ADDR_SHIFT(NOR_ADDR, NOR_MEMORY_WIDTH_, ADDRESS)
Definition: ald_nor_lcd.h:94
NOR_MEMORY_ADRESS4
#define NOR_MEMORY_ADRESS4
Definition: ald_nor_lcd.h:62
NOR_CMD_ADDRESS_THIRD
#define NOR_CMD_ADDRESS_THIRD
Definition: ald_nor_lcd.h:67
nor_handle_t::state
__IO ald_nor_state_t state
Definition: ald_nor_lcd.h:155
NOR_CMD_DATA_SECOND
#define NOR_CMD_DATA_SECOND
Definition: ald_nor_lcd.h:74
nor_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_nor_lcd.h:153
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399
EBI_NORSRAM_BANK1
Definition: ald_ebi.h:190

◆ ald_nor_program_buffer()

ald_status_t ald_nor_program_buffer | ( | nor_handle_t * | hperh,
 |  | uint32_t | addr,
 |  | uint16_t * | data,
 |  | uint32_t | size
 | ) |  |

Writes a half-word buffer to the EBI NOR memory.

Parameters
hperh | pointer to a nor_handle_t structure
addr | nor memory internal address from which the data
data | pointer to source data buffer
size | number of Half words to write
Return values
ald status

Definition at line 311 of file ald_nor_lcd.c.

312 {
313 uint16_t * p_currentaddr = (uint16_t *)NULL;
314 uint16_t * p_endaddr = (uint16_t *)NULL;
315 uint32_t lastloadedaddr = 0, devaddr = 0;
316
317 __LOCK(hperh);
318
319 if (hperh->state == ALD_NOR_STATE_BUSY)
320 return BUSY;
321
322 if (hperh->init.bank == EBI_NORSRAM_BANK1)
323 devaddr = NOR_MEMORY_ADRESS1;
324 else if (hperh->init.bank == EBI_NORSRAM_BANK2)
325 devaddr = NOR_MEMORY_ADRESS2;
326 else if (hperh->init.bank == EBI_NORSRAM_BANK3)
327 devaddr = NOR_MEMORY_ADRESS3;
328 else
329 devaddr = NOR_MEMORY_ADRESS4;
330
331 hperh->state = ALD_NOR_STATE_BUSY;
332
333 /* Initialize variables */
334 p_currentaddr = (uint16_t*)((uint32_t)(addr));
335 p_endaddr = p_currentaddr + (size - 1U);
336 lastloadedaddr = (uint32_t)(addr);
337
338 /* Issue unlock command sequence */
339 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
340 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
341 /* Write Buffer Load Command */
342 NOR_WRITE((uint32_t)(p_currentaddr), NOR_CMD_DATA_BUFFER_AND_PROG);
343 NOR_WRITE((uint32_t)(p_currentaddr), (size - 1U));
344
345 /* Load Data into NOR Buffer */
346 while (p_currentaddr <= p_endaddr) {
347 lastloadedaddr = (uint32_t)p_currentaddr;
348 NOR_WRITE(p_currentaddr, *data++);
349 p_currentaddr++;
350 }
351
352 NOR_WRITE((uint32_t)(lastloadedaddr), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
353 hperh->state = ALD_NOR_STATE_READY;
354 __UNLOCK(hperh);
355
356 return OK;
357 }
ALD_NOR_STATE_READY
Definition: ald_nor_lcd.h:111
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
NOR_MEMORY_ADRESS1
#define NOR_MEMORY_ADRESS1
Definition: ald_nor_lcd.h:59
BUSY
Definition: utils.h:57
ALD_NOR_STATE_BUSY
Definition: ald_nor_lcd.h:112
EBI_NORSRAM_BANK2
Definition: ald_ebi.h:191
NOR_MEMORY_ADRESS3
#define NOR_MEMORY_ADRESS3
Definition: ald_nor_lcd.h:61
NOR_CMD_ADDRESS_SECOND
#define NOR_CMD_ADDRESS_SECOND
Definition: ald_nor_lcd.h:66
EBI_NORSRAM_BANK3
Definition: ald_ebi.h:192
NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM
#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM
Definition: ald_nor_lcd.h:83
NOR_CMD_ADDRESS_FIRST
#define NOR_CMD_ADDRESS_FIRST
Definition: ald_nor_lcd.h:64
NORMEMDATWIDTH
static uint32_t NORMEMDATWIDTH
Definition: ald_nor_lcd.c:33
NOR_CMD_DATA_FIRST
#define NOR_CMD_DATA_FIRST
Definition: ald_nor_lcd.h:73
NOR_MEMORY_ADRESS2
#define NOR_MEMORY_ADRESS2
Definition: ald_nor_lcd.h:60
NOR_CMD_DATA_BUFFER_AND_PROG
#define NOR_CMD_DATA_BUFFER_AND_PROG
Definition: ald_nor_lcd.h:82
NOR_WRITE
#define NOR_WRITE(ADDR, DATA)
Definition: ald_nor_lcd.h:98
NOR_ADDR_SHIFT
#define NOR_ADDR_SHIFT(NOR_ADDR, NOR_MEMORY_WIDTH_, ADDRESS)
Definition: ald_nor_lcd.h:94
NOR_MEMORY_ADRESS4
#define NOR_MEMORY_ADRESS4
Definition: ald_nor_lcd.h:62
nor_handle_t::state
__IO ald_nor_state_t state
Definition: ald_nor_lcd.h:155
NOR_CMD_DATA_SECOND
#define NOR_CMD_DATA_SECOND
Definition: ald_nor_lcd.h:74
nor_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_nor_lcd.h:153
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399
EBI_NORSRAM_BANK1
Definition: ald_ebi.h:190

◆ ald_nor_read()

ald_status_t ald_nor_read | ( | nor_handle_t * | hperh,
 |  | uint32_t * | addr,
 |  | uint16_t * | data
 | ) |  |

Read data from NOR memory.

Parameters
hperh | pointer to a nor_handle_t structure
addr | pointer to Device address
data | pointer to read data
Return values
ald status

Definition at line 182 of file ald_nor_lcd.c.

183 {
184 uint32_t devaddr = 0;
185
186 __LOCK(hperh);
187
188 if (hperh->state == ALD_NOR_STATE_BUSY)
189 return BUSY;
190
191 if (hperh->init.bank == EBI_NORSRAM_BANK1)
192 devaddr = NOR_MEMORY_ADRESS1;
193 else if (hperh->init.bank == EBI_NORSRAM_BANK2)
194 devaddr = NOR_MEMORY_ADRESS2;
195 else if (hperh->init.bank == EBI_NORSRAM_BANK3)
196 devaddr = NOR_MEMORY_ADRESS3;
197 else
198 devaddr = NOR_MEMORY_ADRESS4;
199
200 hperh->state = ALD_NOR_STATE_BUSY;
201
202 /* Send read data command */
203 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
204 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
205 NOR_WRITE((uint32_t)addr, NOR_CMD_DATA_READ_RESET);
206
207 *data = *(__IO uint32_t *)(uint32_t)addr;
208 hperh->state = ALD_NOR_STATE_READY;
209 __UNLOCK(hperh);
210
211 return OK;
212 }
ALD_NOR_STATE_READY
Definition: ald_nor_lcd.h:111
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
NOR_MEMORY_ADRESS1
#define NOR_MEMORY_ADRESS1
Definition: ald_nor_lcd.h:59
BUSY
Definition: utils.h:57
ALD_NOR_STATE_BUSY
Definition: ald_nor_lcd.h:112
EBI_NORSRAM_BANK2
Definition: ald_ebi.h:191
NOR_MEMORY_ADRESS3
#define NOR_MEMORY_ADRESS3
Definition: ald_nor_lcd.h:61
NOR_CMD_DATA_READ_RESET
#define NOR_CMD_DATA_READ_RESET
Definition: ald_nor_lcd.h:72
NOR_CMD_ADDRESS_SECOND
#define NOR_CMD_ADDRESS_SECOND
Definition: ald_nor_lcd.h:66
EBI_NORSRAM_BANK3
Definition: ald_ebi.h:192
NOR_CMD_ADDRESS_FIRST
#define NOR_CMD_ADDRESS_FIRST
Definition: ald_nor_lcd.h:64
NORMEMDATWIDTH
static uint32_t NORMEMDATWIDTH
Definition: ald_nor_lcd.c:33
NOR_CMD_DATA_FIRST
#define NOR_CMD_DATA_FIRST
Definition: ald_nor_lcd.h:73
NOR_MEMORY_ADRESS2
#define NOR_MEMORY_ADRESS2
Definition: ald_nor_lcd.h:60
NOR_WRITE
#define NOR_WRITE(ADDR, DATA)
Definition: ald_nor_lcd.h:98
NOR_ADDR_SHIFT
#define NOR_ADDR_SHIFT(NOR_ADDR, NOR_MEMORY_WIDTH_, ADDRESS)
Definition: ald_nor_lcd.h:94
NOR_MEMORY_ADRESS4
#define NOR_MEMORY_ADRESS4
Definition: ald_nor_lcd.h:62
nor_handle_t::state
__IO ald_nor_state_t state
Definition: ald_nor_lcd.h:155
NOR_CMD_DATA_SECOND
#define NOR_CMD_DATA_SECOND
Definition: ald_nor_lcd.h:74
nor_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_nor_lcd.h:153
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399
EBI_NORSRAM_BANK1
Definition: ald_ebi.h:190

◆ ald_nor_read_buffer()

ald_status_t ald_nor_read_buffer | ( | nor_handle_t * | hperh,
 |  | uint32_t | addr,
 |  | uint16_t * | data,
 |  | uint32_t | size
 | ) |  |

Reads a block of data from the EBI NOR memory.

Parameters
hperh | pointer to a nor_handle_t structure
addr | nor memory internal address to read from
data | pointer to the buffer that receives the data read from the NOR memory
size | : number of Half word to read
Return values
ald status

Definition at line 264 of file ald_nor_lcd.c.

265 {
266 uint32_t devaddr = 0;
267
268 /* Process Locked */
269 __LOCK(hperh);
270
271 if (hperh->state == ALD_NOR_STATE_BUSY)
272 return BUSY;
273
274 if (hperh->init.bank == EBI_NORSRAM_BANK1)
275 devaddr = NOR_MEMORY_ADRESS1;
276 else if (hperh->init.bank == EBI_NORSRAM_BANK2)
277 devaddr = NOR_MEMORY_ADRESS2;
278 else if (hperh->init.bank == EBI_NORSRAM_BANK3)
279 devaddr = NOR_MEMORY_ADRESS3;
280 else
281 devaddr = NOR_MEMORY_ADRESS4;
282
283 hperh->state = ALD_NOR_STATE_BUSY;
284
285 /* Send read data command */
286 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
287 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
288 NOR_WRITE(addr, NOR_CMD_DATA_READ_RESET);
289
290 /* Read buffer */
291 while (size > 0) {
292 *data++ = *(__IO uint16_t *)addr;
293 addr += 2U;
294 size--;
295 }
296
297 hperh->state = ALD_NOR_STATE_READY;
298 __UNLOCK(hperh);
299
300 return OK;
301 }
ALD_NOR_STATE_READY
Definition: ald_nor_lcd.h:111
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
NOR_MEMORY_ADRESS1
#define NOR_MEMORY_ADRESS1
Definition: ald_nor_lcd.h:59
BUSY
Definition: utils.h:57
ALD_NOR_STATE_BUSY
Definition: ald_nor_lcd.h:112
EBI_NORSRAM_BANK2
Definition: ald_ebi.h:191
NOR_MEMORY_ADRESS3
#define NOR_MEMORY_ADRESS3
Definition: ald_nor_lcd.h:61
NOR_CMD_DATA_READ_RESET
#define NOR_CMD_DATA_READ_RESET
Definition: ald_nor_lcd.h:72
NOR_CMD_ADDRESS_SECOND
#define NOR_CMD_ADDRESS_SECOND
Definition: ald_nor_lcd.h:66
EBI_NORSRAM_BANK3
Definition: ald_ebi.h:192
NOR_CMD_ADDRESS_FIRST
#define NOR_CMD_ADDRESS_FIRST
Definition: ald_nor_lcd.h:64
NORMEMDATWIDTH
static uint32_t NORMEMDATWIDTH
Definition: ald_nor_lcd.c:33
NOR_CMD_DATA_FIRST
#define NOR_CMD_DATA_FIRST
Definition: ald_nor_lcd.h:73
NOR_MEMORY_ADRESS2
#define NOR_MEMORY_ADRESS2
Definition: ald_nor_lcd.h:60
NOR_WRITE
#define NOR_WRITE(ADDR, DATA)
Definition: ald_nor_lcd.h:98
NOR_ADDR_SHIFT
#define NOR_ADDR_SHIFT(NOR_ADDR, NOR_MEMORY_WIDTH_, ADDRESS)
Definition: ald_nor_lcd.h:94
NOR_MEMORY_ADRESS4
#define NOR_MEMORY_ADRESS4
Definition: ald_nor_lcd.h:62
nor_handle_t::state
__IO ald_nor_state_t state
Definition: ald_nor_lcd.h:155
NOR_CMD_DATA_SECOND
#define NOR_CMD_DATA_SECOND
Definition: ald_nor_lcd.h:74
nor_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_nor_lcd.h:153
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399
EBI_NORSRAM_BANK1
Definition: ald_ebi.h:190

◆ ald_nor_read_cfi()

ald_status_t ald_nor_read_cfi | ( | nor_handle_t * | hperh,
 |  | nor_cfi_t * | cfi
 | ) |  |

Read NOR flash CFI IDs.

Parameters
hperh | pointer to a nor_handle_t structure
cfi | pointer to NOR CFI IDs structure
Return values
ald status

Definition at line 447 of file ald_nor_lcd.c.

448 {
449 uint32_t devaddr = 0;
450
451 __LOCK(hperh);
452
453 if (hperh->state == ALD_NOR_STATE_BUSY)
454 return BUSY;
455
456 /* Select the NOR device address */
457 if (hperh->init.bank == EBI_NORSRAM_BANK1)
458 devaddr = NOR_MEMORY_ADRESS1;
459 else if (hperh->init.bank == EBI_NORSRAM_BANK2)
460 devaddr = NOR_MEMORY_ADRESS2;
461 else if (hperh->init.bank == EBI_NORSRAM_BANK3)
462 devaddr = NOR_MEMORY_ADRESS3;
463 else
464 devaddr = NOR_MEMORY_ADRESS4;
465
466 hperh->state = ALD_NOR_STATE_BUSY;
467 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
468
469 cfi->cfi_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI1_ADDRESS);
470 cfi->cfi_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI2_ADDRESS);
471 cfi->cfi_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI3_ADDRESS);
472 cfi->cfi_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI4_ADDRESS);
473
474 hperh->state = ALD_NOR_STATE_READY;
475 __UNLOCK(hperh);
476
477 return OK;
478 }
ALD_NOR_STATE_READY
Definition: ald_nor_lcd.h:111
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
nor_cfi_t::cfi_2
uint16_t cfi_2
Definition: ald_nor_lcd.h:142
NOR_MEMORY_ADRESS1
#define NOR_MEMORY_ADRESS1
Definition: ald_nor_lcd.h:59
BUSY
Definition: utils.h:57
ALD_NOR_STATE_BUSY
Definition: ald_nor_lcd.h:112
EBI_NORSRAM_BANK2
Definition: ald_ebi.h:191
NOR_CMD_DATA_CFI
#define NOR_CMD_DATA_CFI
Definition: ald_nor_lcd.h:81
NOR_MEMORY_ADRESS3
#define NOR_MEMORY_ADRESS3
Definition: ald_nor_lcd.h:61
EBI_NORSRAM_BANK3
Definition: ald_ebi.h:192
NORMEMDATWIDTH
static uint32_t NORMEMDATWIDTH
Definition: ald_nor_lcd.c:33
CFI2_ADDRESS
#define CFI2_ADDRESS
Definition: ald_nor_lcd.h:47
NOR_MEMORY_ADRESS2
#define NOR_MEMORY_ADRESS2
Definition: ald_nor_lcd.h:60
NOR_WRITE
#define NOR_WRITE(ADDR, DATA)
Definition: ald_nor_lcd.h:98
NOR_CMD_ADDRESS_FIRST_CFI
#define NOR_CMD_ADDRESS_FIRST_CFI
Definition: ald_nor_lcd.h:65
nor_cfi_t::cfi_1
uint16_t cfi_1
Definition: ald_nor_lcd.h:141
NOR_ADDR_SHIFT
#define NOR_ADDR_SHIFT(NOR_ADDR, NOR_MEMORY_WIDTH_, ADDRESS)
Definition: ald_nor_lcd.h:94
NOR_MEMORY_ADRESS4
#define NOR_MEMORY_ADRESS4
Definition: ald_nor_lcd.h:62
nor_cfi_t::cfi_3
uint16_t cfi_3
Definition: ald_nor_lcd.h:143
CFI4_ADDRESS
#define CFI4_ADDRESS
Definition: ald_nor_lcd.h:49
nor_handle_t::state
__IO ald_nor_state_t state
Definition: ald_nor_lcd.h:155
CFI1_ADDRESS
#define CFI1_ADDRESS
Definition: ald_nor_lcd.h:46
CFI3_ADDRESS
#define CFI3_ADDRESS
Definition: ald_nor_lcd.h:48
nor_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_nor_lcd.h:153
__LOCK
#define __LOCK(x)
Definition: utils.h:92
nor_cfi_t::cfi_4
uint16_t cfi_4
Definition: ald_nor_lcd.h:144
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399
EBI_NORSRAM_BANK1
Definition: ald_ebi.h:190

◆ ald_nor_read_id()

ald_status_t ald_nor_read_id | ( | nor_handle_t * | hperh,
 |  | nor_id_t * | id
 | ) |  |

Read NOR flash IDs.

Parameters
hperh | pointer to a nor_handle_t structure
id | : pointer to NOR ID structure
Return values
ald status

Definition at line 106 of file ald_nor_lcd.c.

107 {
108 uint32_t devaddr = 0;
109
110 __LOCK(hperh);
111
112 if (hperh->state == ALD_NOR_STATE_BUSY)
113 return BUSY;
114
115 /* Select the NOR device address */
116 if (hperh->init.bank == EBI_NORSRAM_BANK1)
117 devaddr = NOR_MEMORY_ADRESS1;
118 else if (hperh->init.bank == EBI_NORSRAM_BANK2)
119 devaddr = NOR_MEMORY_ADRESS2;
120 else if (hperh->init.bank == EBI_NORSRAM_BANK3)
121 devaddr = NOR_MEMORY_ADRESS3;
122 else
123 devaddr = NOR_MEMORY_ADRESS4;
124
125 hperh->state = ALD_NOR_STATE_BUSY;
126
127 /* Send read ID command */
128 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
129 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
130 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
131
132 /* Read the NOR IDs */
133 id->m_code = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, MC_ADDRESS);
134 id->device_code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, DEVICE_CODE1_ADDR);
135 id->device_code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, DEVICE_CODE2_ADDR);
136 id->device_code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, DEVICE_CODE3_ADDR);
137
138 hperh->state = ALD_NOR_STATE_READY;
139 __UNLOCK(hperh);
140
141 return OK;
142 }
NOR_CMD_DATA_AUTO_SELECT
#define NOR_CMD_DATA_AUTO_SELECT
Definition: ald_nor_lcd.h:75
ALD_NOR_STATE_READY
Definition: ald_nor_lcd.h:111
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
NOR_MEMORY_ADRESS1
#define NOR_MEMORY_ADRESS1
Definition: ald_nor_lcd.h:59
BUSY
Definition: utils.h:57
DEVICE_CODE3_ADDR
#define DEVICE_CODE3_ADDR
Definition: ald_nor_lcd.h:43
ALD_NOR_STATE_BUSY
Definition: ald_nor_lcd.h:112
EBI_NORSRAM_BANK2
Definition: ald_ebi.h:191
NOR_MEMORY_ADRESS3
#define NOR_MEMORY_ADRESS3
Definition: ald_nor_lcd.h:61
NOR_CMD_ADDRESS_SECOND
#define NOR_CMD_ADDRESS_SECOND
Definition: ald_nor_lcd.h:66
EBI_NORSRAM_BANK3
Definition: ald_ebi.h:192
NOR_CMD_ADDRESS_FIRST
#define NOR_CMD_ADDRESS_FIRST
Definition: ald_nor_lcd.h:64
DEVICE_CODE2_ADDR
#define DEVICE_CODE2_ADDR
Definition: ald_nor_lcd.h:42
NORMEMDATWIDTH
static uint32_t NORMEMDATWIDTH
Definition: ald_nor_lcd.c:33
NOR_CMD_DATA_FIRST
#define NOR_CMD_DATA_FIRST
Definition: ald_nor_lcd.h:73
NOR_MEMORY_ADRESS2
#define NOR_MEMORY_ADRESS2
Definition: ald_nor_lcd.h:60
NOR_WRITE
#define NOR_WRITE(ADDR, DATA)
Definition: ald_nor_lcd.h:98
NOR_ADDR_SHIFT
#define NOR_ADDR_SHIFT(NOR_ADDR, NOR_MEMORY_WIDTH_, ADDRESS)
Definition: ald_nor_lcd.h:94
NOR_MEMORY_ADRESS4
#define NOR_MEMORY_ADRESS4
Definition: ald_nor_lcd.h:62
NOR_CMD_ADDRESS_THIRD
#define NOR_CMD_ADDRESS_THIRD
Definition: ald_nor_lcd.h:67
nor_handle_t::state
__IO ald_nor_state_t state
Definition: ald_nor_lcd.h:155
DEVICE_CODE1_ADDR
#define DEVICE_CODE1_ADDR
Definition: ald_nor_lcd.h:41
MC_ADDRESS
#define MC_ADDRESS
Definition: ald_nor_lcd.h:40
NOR_CMD_DATA_SECOND
#define NOR_CMD_DATA_SECOND
Definition: ald_nor_lcd.h:74
nor_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_nor_lcd.h:153
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399
EBI_NORSRAM_BANK1
Definition: ald_ebi.h:190

◆ ald_nor_return_readmode()

ald_status_t ald_nor_return_readmode ( nor_handle_t * hperh )

Returns the NOR memory to Read mode.

Parameters
hperh pointer to a nor_handle_t structure
Return values
ald status

Definition at line 149 of file ald_nor_lcd.c.

150 {
151 uint32_t devaddr = 0;
152
153 __LOCK(hperh);
154
155 if (hperh->state == ALD_NOR_STATE_BUSY)
156 return BUSY;
157
158 /* Select the NOR device address */
159 if (hperh->init.bank == EBI_NORSRAM_BANK1)
160 devaddr = NOR_MEMORY_ADRESS1;
161 else if (hperh->init.bank == EBI_NORSRAM_BANK2)
162 devaddr = NOR_MEMORY_ADRESS2;
163 else if (hperh->init.bank == EBI_NORSRAM_BANK3)
164 devaddr = NOR_MEMORY_ADRESS3;
165 else
166 devaddr = NOR_MEMORY_ADRESS4;
167
168 NOR_WRITE(devaddr, NOR_CMD_DATA_READ_RESET);
169 hperh->state = ALD_NOR_STATE_READY;
170 __UNLOCK(hperh);
171
172 return OK;
173 }
ALD_NOR_STATE_READY
Definition: ald_nor_lcd.h:111
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
NOR_MEMORY_ADRESS1
#define NOR_MEMORY_ADRESS1
Definition: ald_nor_lcd.h:59
BUSY
Definition: utils.h:57
ALD_NOR_STATE_BUSY
Definition: ald_nor_lcd.h:112
EBI_NORSRAM_BANK2
Definition: ald_ebi.h:191
NOR_MEMORY_ADRESS3
#define NOR_MEMORY_ADRESS3
Definition: ald_nor_lcd.h:61
NOR_CMD_DATA_READ_RESET
#define NOR_CMD_DATA_READ_RESET
Definition: ald_nor_lcd.h:72
EBI_NORSRAM_BANK3
Definition: ald_ebi.h:192
NOR_MEMORY_ADRESS2
#define NOR_MEMORY_ADRESS2
Definition: ald_nor_lcd.h:60
NOR_WRITE
#define NOR_WRITE(ADDR, DATA)
Definition: ald_nor_lcd.h:98
NOR_MEMORY_ADRESS4
#define NOR_MEMORY_ADRESS4
Definition: ald_nor_lcd.h:62
nor_handle_t::state
__IO ald_nor_state_t state
Definition: ald_nor_lcd.h:155
nor_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_nor_lcd.h:153
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399
EBI_NORSRAM_BANK1
Definition: ald_ebi.h:190


ALD User Manual: Control functions

Functions
Control functions
EASTSOFT ES32F3xx ALD » NOR_LCD » NOR_LCD Public Functions EASTSOFT ES32F3xx ALD » NOR_LCD » | NOR_Public_Functions

NOR_LCD Control functions. More...

Collaboration diagram for Control functions:

Functions

ald_status_t | ald_nor_write_enable (nor_handle_t *hperh)
Enables dynamically NOR write operation. More...
ald_status_t | ald_nor_write_disable (nor_handle_t *hperh)
Disables dynamically NOR write operation. More...

Detailed Description

NOR_LCD Control functions.

Function Documentation

◆ ald_nor_write_disable()

ald_status_t ald_nor_write_disable ( nor_handle_t * hperh )

Disables dynamically NOR write operation.

Parameters
hperh pointer to a nor_handle_t structure
Return values
ald status

Definition at line 508 of file ald_nor_lcd.c.

509 {
510 __LOCK(hperh);
511 hperh->state = ALD_NOR_STATE_BUSY;
512 /* Disable write operation */
513 ald_ebi_nor_sram_write_disable(hperh->instance, hperh->init.bank);
514 hperh->state = ALD_NOR_STATE_PROTECTED;
515 __UNLOCK(hperh);
516
517 return OK;
518 }
ALD_NOR_STATE_PROTECTED
Definition: ald_nor_lcd.h:114
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
ALD_NOR_STATE_BUSY
Definition: ald_nor_lcd.h:112
ald_ebi_nor_sram_write_disable
void ald_ebi_nor_sram_write_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Disables dynamically EBI_NORSRAM write operation.
Definition: ald_ebi.c:249
nor_handle_t::instance
EBI_NOR_SRAM_TypeDef * instance
Definition: ald_nor_lcd.h:151
nor_handle_t::state
__IO ald_nor_state_t state
Definition: ald_nor_lcd.h:155
nor_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_nor_lcd.h:153
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399

◆ ald_nor_write_enable()

ald_status_t ald_nor_write_enable ( nor_handle_t * hperh )

Enables dynamically NOR write operation.

Parameters
hperh pointer to a nor_handle_t structure
Return values
ald status

Definition at line 492 of file ald_nor_lcd.c.

493 {
494 __LOCK(hperh);
495 /* Enable write operation */
496 ald_ebi_nor_sram_write_enable(hperh->instance, hperh->init.bank);
497 hperh->state = ALD_NOR_STATE_READY;
498 __UNLOCK(hperh);
499
500 return OK;
501 }
ALD_NOR_STATE_READY
Definition: ald_nor_lcd.h:111
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
ald_ebi_nor_sram_write_enable
void ald_ebi_nor_sram_write_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Enables dynamically NOR-FLASH/SRAM write operation.
Definition: ald_ebi.c:234
nor_handle_t::instance
EBI_NOR_SRAM_TypeDef * instance
Definition: ald_nor_lcd.h:151
nor_handle_t::state
__IO ald_nor_state_t state
Definition: ald_nor_lcd.h:155
nor_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_nor_lcd.h:153
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399


ALD User Manual: State functions

Functions
State functions
EASTSOFT ES32F3xx ALD » NOR_LCD » NOR_LCD Public Functions EASTSOFT ES32F3xx ALD » NOR_LCD » | NOR_Public_Functions

NOR_LCD State functions. More...

Collaboration diagram for State functions:

Functions

ald_nor_state_t | ald_nor_get_state (nor_handle_t *hperh)
return the NOR controller state More...
nor_status_t | ald_nor_get_status (nor_handle_t *hperh, uint32_t addr, uint32_t timeout)
Returns the NOR operation status. More...

Detailed Description

NOR_LCD State functions.

Function Documentation

◆ ald_nor_get_state()

ald_nor_state_t ald_nor_get_state ( nor_handle_t * hperh )

return the NOR controller state

Parameters
hperh pointer to a nor_handle_t structure
Return values
nor controller state

Definition at line 532 of file ald_nor_lcd.c.

533 {
534 return hperh->state;
535 }
nor_handle_t::state
__IO ald_nor_state_t state
Definition: ald_nor_lcd.h:155

◆ ald_nor_get_status()

nor_status_t ald_nor_get_status | ( | nor_handle_t * | hperh,
 |  | uint32_t | addr,
 |  | uint32_t | timeout
 | ) |  |

Returns the NOR operation status.

Parameters
hperh | pointer to a nor_handle_t structure
addr | device address
timeout | nor progamming timeout
Return values
nor status

Definition at line 544 of file ald_nor_lcd.c.

545 {
546 nor_status_t status = ALD_NOR_STATUS_ONGOING;
547 uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
548 uint32_t tickstart = 0;
549
550 /* Get tick */
551 tickstart = ald_get_tick();
552 while ((status != ALD_NOR_STATUS_SUCCESS) && (status != ALD_NOR_STATUS_TIMEOUT)) {
553 /* Check for the Timeout */
554 if (timeout != ALD_MAX_DELAY) {
555 if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout))
556 status = ALD_NOR_STATUS_TIMEOUT;
557 }
558
559 /* Read NOR status register (DQ6 and DQ5) */
560 tmp_sr1 = *(__IO uint16_t *)addr;
561 tmp_sr2 = *(__IO uint16_t *)addr;
562
563 /* If DQ6 did not toggle between the two reads then return NOR_Success */
564 if ((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
565 return ALD_NOR_STATUS_SUCCESS;
566
567 if ((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
568 status = ALD_NOR_STATUS_ONGOING;
569
570 tmp_sr1 = *(__IO uint16_t *)addr;
571 tmp_sr2 = *(__IO uint16_t *)addr;
572
573 /* If DQ6 did not toggle between the two reads then return NOR_Success */
574 if ((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
575 return ALD_NOR_STATUS_SUCCESS;
576 else if ((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
577 return ALD_NOR_STATUS_ERROR;
578 }
579
580 return status;
581 }
ALD_MAX_DELAY
#define ALD_MAX_DELAY
Definition: utils.h:88
ALD_NOR_STATUS_TIMEOUT
Definition: ald_nor_lcd.h:124
ALD_NOR_STATUS_ONGOING
Definition: ald_nor_lcd.h:122
NOR_MASK_STATUS_DQ6
#define NOR_MASK_STATUS_DQ6
Definition: ald_nor_lcd.h:86
NOR_MASK_STATUS_DQ5
#define NOR_MASK_STATUS_DQ5
Definition: ald_nor_lcd.h:85
ALD_NOR_STATUS_ERROR
Definition: ald_nor_lcd.h:123
ALD_NOR_STATUS_SUCCESS
Definition: ald_nor_lcd.h:121
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
nor_status_t
nor_status_t
EBI NOR Status typedef.
Definition: ald_nor_lcd.h:120


ALD User Manual: NOR LCD Private Constants

Macros
NOR LCD Private Constants
EASTSOFT ES32F3xx ALD » NOR_LCD
Collaboration diagram for NOR LCD Private Constants:

Macros

#define | MC_ADDRESS ((uint16_t)0x0000U)
#define | DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
#define | DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
#define | DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
#define | CFI1_ADDRESS ((uint16_t)0x10U)
#define | CFI2_ADDRESS ((uint16_t)0x11U)
#define | CFI3_ADDRESS ((uint16_t)0x12U)
#define | CFI4_ADDRESS ((uint16_t)0x13U)
#define | NOR_TMEOUT ((uint16_t)0xFFFFU)
#define | NOR_MEMORY_8B ((uint8_t)0x0U)
#define | NOR_MEMORY_16B ((uint8_t)0x1U)
#define | NOR_MEMORY_ADRESS1 EBI_BANK1_1
#define | NOR_MEMORY_ADRESS2 EBI_BANK1_2
#define | NOR_MEMORY_ADRESS3 EBI_BANK1_3
#define | NOR_MEMORY_ADRESS4 EBI_BANK1_4
#define | NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555U
#define | NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055U
#define | NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AAU
#define | NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555U
#define | NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555U
#define | NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AAU
#define | NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555U
#define | NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0U
#define | NOR_CMD_DATA_FIRST (uint16_t)0x00AAU
#define | NOR_CMD_DATA_SECOND (uint16_t)0x0055U
#define | NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090U
#define | NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0U
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080U
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AAU
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055U
#define | NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010U
#define | NOR_CMD_DATA_CFI (uint16_t)0x0098U
#define | NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25U
#define | NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29U
#define | NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30U
#define | NOR_MASK_STATUS_DQ5 (uint16_t)0x0020U
#define | NOR_MASK_STATUS_DQ6 (uint16_t)0x0040U

Detailed Description

Macro Definition Documentation

◆ CFI1_ADDRESS

#define CFI1_ADDRESS ((uint16_t)0x10U)

Definition at line 46 of file ald_nor_lcd.h.

◆ CFI2_ADDRESS

#define CFI2_ADDRESS ((uint16_t)0x11U)

Definition at line 47 of file ald_nor_lcd.h.

◆ CFI3_ADDRESS

#define CFI3_ADDRESS ((uint16_t)0x12U)

Definition at line 48 of file ald_nor_lcd.h.

◆ CFI4_ADDRESS

#define CFI4_ADDRESS ((uint16_t)0x13U)

Definition at line 49 of file ald_nor_lcd.h.

◆ DEVICE_CODE1_ADDR

#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)

Definition at line 41 of file ald_nor_lcd.h.

◆ DEVICE_CODE2_ADDR

#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)

Definition at line 42 of file ald_nor_lcd.h.

◆ DEVICE_CODE3_ADDR

#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)

Definition at line 43 of file ald_nor_lcd.h.

◆ MC_ADDRESS

#define MC_ADDRESS ((uint16_t)0x0000U)

Definition at line 40 of file ald_nor_lcd.h.

◆ NOR_CMD_ADDRESS_FIFTH

#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AAU

Definition at line 69 of file ald_nor_lcd.h.

◆ NOR_CMD_ADDRESS_FIRST

#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555U

Definition at line 64 of file ald_nor_lcd.h.

◆ NOR_CMD_ADDRESS_FIRST_CFI

#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055U

Definition at line 65 of file ald_nor_lcd.h.

◆ NOR_CMD_ADDRESS_FOURTH

#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555U

Definition at line 68 of file ald_nor_lcd.h.

◆ NOR_CMD_ADDRESS_SECOND

#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AAU

Definition at line 66 of file ald_nor_lcd.h.

◆ NOR_CMD_ADDRESS_SIXTH

#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555U

Definition at line 70 of file ald_nor_lcd.h.

◆ NOR_CMD_ADDRESS_THIRD

#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555U

Definition at line 67 of file ald_nor_lcd.h.

◆ NOR_CMD_DATA_AUTO_SELECT

#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090U

Definition at line 75 of file ald_nor_lcd.h.

◆ NOR_CMD_DATA_BLOCK_ERASE

#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30U

Definition at line 84 of file ald_nor_lcd.h.

◆ NOR_CMD_DATA_BUFFER_AND_PROG

#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25U

Definition at line 82 of file ald_nor_lcd.h.

◆ NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM

#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29U

Definition at line 83 of file ald_nor_lcd.h.

◆ NOR_CMD_DATA_CFI

#define NOR_CMD_DATA_CFI (uint16_t)0x0098U

Definition at line 81 of file ald_nor_lcd.h.

◆ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH

#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055U

Definition at line 79 of file ald_nor_lcd.h.

◆ NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH

#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AAU

Definition at line 78 of file ald_nor_lcd.h.

◆ NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD

#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080U

Definition at line 77 of file ald_nor_lcd.h.

◆ NOR_CMD_DATA_CHIP_ERASE

#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010U

Definition at line 80 of file ald_nor_lcd.h.

◆ NOR_CMD_DATA_FIRST

#define NOR_CMD_DATA_FIRST (uint16_t)0x00AAU

Definition at line 73 of file ald_nor_lcd.h.

◆ NOR_CMD_DATA_PROGRAM

#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0U

Definition at line 76 of file ald_nor_lcd.h.

◆ NOR_CMD_DATA_READ_RESET

#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0U

Definition at line 72 of file ald_nor_lcd.h.

◆ NOR_CMD_DATA_SECOND

#define NOR_CMD_DATA_SECOND (uint16_t)0x0055U

Definition at line 74 of file ald_nor_lcd.h.

◆ NOR_MASK_STATUS_DQ5

#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020U

Definition at line 85 of file ald_nor_lcd.h.

◆ NOR_MASK_STATUS_DQ6

#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040U

Definition at line 86 of file ald_nor_lcd.h.

◆ NOR_MEMORY_16B

#define NOR_MEMORY_16B ((uint8_t)0x1U)

Definition at line 56 of file ald_nor_lcd.h.

◆ NOR_MEMORY_8B

#define NOR_MEMORY_8B ((uint8_t)0x0U)

Definition at line 55 of file ald_nor_lcd.h.

◆ NOR_MEMORY_ADRESS1

#define NOR_MEMORY_ADRESS1 EBI_BANK1_1

Definition at line 59 of file ald_nor_lcd.h.

◆ NOR_MEMORY_ADRESS2

#define NOR_MEMORY_ADRESS2 EBI_BANK1_2

Definition at line 60 of file ald_nor_lcd.h.

◆ NOR_MEMORY_ADRESS3

#define NOR_MEMORY_ADRESS3 EBI_BANK1_3

Definition at line 61 of file ald_nor_lcd.h.

◆ NOR_MEMORY_ADRESS4

#define NOR_MEMORY_ADRESS4 EBI_BANK1_4

Definition at line 62 of file ald_nor_lcd.h.

◆ NOR_TMEOUT

#define NOR_TMEOUT ((uint16_t)0xFFFFU)

Definition at line 52 of file ald_nor_lcd.h.


ALD User Manual: NOR_LCD Private Macros

Macros
NOR_LCD Private Macros
EASTSOFT ES32F3xx ALD » NOR_LCD
Collaboration diagram for NOR_LCD Private Macros:

Macros

#define | NOR_ADDR_SHIFT(NOR_ADDR, NOR_MEMORY_WIDTH_, ADDRESS)
#define | NOR_WRITE(ADDR, DATA) (*(__IO uint16_t *)((uint32_t)(ADDR)) = (DATA))

Detailed Description

Macro Definition Documentation

◆ NOR_ADDR_SHIFT

#define NOR_ADDR_SHIFT | ( | NOR_ADDR,
 |  | NOR_MEMORY_WIDTH_,
 |  | ADDRESS
 | ) |
Value:
((uint32_t)(((NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B) ? \
((uint32_t)((NOR_ADDR) + (2U * (ADDRESS)))): \
((uint32_t)((NOR_ADDR) + (ADDRESS)))))
NOR_MEMORY_16B
#define NOR_MEMORY_16B
Definition: ald_nor_lcd.h:56

Definition at line 94 of file ald_nor_lcd.h.

◆ NOR_WRITE

#define NOR_WRITE | ( | ADDR,
 |  | DATA
 | ) | (*(__IO uint16_t *)((uint32_t)(ADDR)) = (DATA))

Definition at line 98 of file ald_nor_lcd.h.


ALD User Manual: NOR_LCD Public Types

Data Structures | Enumerations
NOR_LCD Public Types
EASTSOFT ES32F3xx ALD » NOR_LCD
Collaboration diagram for NOR_LCD Public Types:

Data Structures

struct | nor_id_t
EBI NOR ID typedef. More...
struct | nor_cfi_t
EBI NOR CFI typedef. More...
struct | nor_handle_t
NOR handle Structure definition. More...

Enumerations

enum ald_nor_state_t {
ALD_NOR_STATE_RESET = 0x00U, ALD_NOR_STATE_READY = 0x01U, ALD_NOR_STATE_BUSY = 0x02U, ALD_NOR_STATE_ERROR = 0x03U,
ALD_NOR_STATE_PROTECTED = 0x04U
}
ALD SRAM State structures definition. More...
enum nor_status_t { ALD_NOR_STATUS_SUCCESS = 0U, ALD_NOR_STATUS_ONGOING, ALD_NOR_STATUS_ERROR, ALD_NOR_STATUS_TIMEOUT }
EBI NOR Status typedef. More...

Detailed Description

Enumeration Type Documentation

◆ ald_nor_state_t

enum ald_nor_state_t

ALD SRAM State structures definition.

Enumerator
ALD_NOR_STATE_RESET | NOR not yet initialized or disabled
ALD_NOR_STATE_READY | NOR initialized and ready for use
ALD_NOR_STATE_BUSY | NOR internal processing is ongoing
ALD_NOR_STATE_ERROR | NOR error state
ALD_NOR_STATE_PROTECTED | NOR NORSRAM device write protected

Definition at line 109 of file ald_nor_lcd.h.

109 {
110 ALD_NOR_STATE_RESET = 0x00U,
111 ALD_NOR_STATE_READY = 0x01U,
112 ALD_NOR_STATE_BUSY = 0x02U,
113 ALD_NOR_STATE_ERROR = 0x03U,
114 ALD_NOR_STATE_PROTECTED = 0x04U
115 } ald_nor_state_t;
ALD_NOR_STATE_PROTECTED
Definition: ald_nor_lcd.h:114
ALD_NOR_STATE_READY
Definition: ald_nor_lcd.h:111
ALD_NOR_STATE_BUSY
Definition: ald_nor_lcd.h:112
ald_nor_state_t
ald_nor_state_t
ALD SRAM State structures definition.
Definition: ald_nor_lcd.h:109
ALD_NOR_STATE_ERROR
Definition: ald_nor_lcd.h:113
ALD_NOR_STATE_RESET
Definition: ald_nor_lcd.h:110

◆ nor_status_t

enum nor_status_t

EBI NOR Status typedef.

Enumerator
ALD_NOR_STATUS_SUCCESS | NOR status success
ALD_NOR_STATUS_ONGOING | NOR status ongoing
ALD_NOR_STATUS_ERROR | NOR status error
ALD_NOR_STATUS_TIMEOUT | NOR status timeout

Definition at line 120 of file ald_nor_lcd.h.

120 {
121 ALD_NOR_STATUS_SUCCESS = 0U,
122 ALD_NOR_STATUS_ONGOING,
123 ALD_NOR_STATUS_ERROR,
124 ALD_NOR_STATUS_TIMEOUT,
125 } nor_status_t;
ALD_NOR_STATUS_TIMEOUT
Definition: ald_nor_lcd.h:124
ALD_NOR_STATUS_ONGOING
Definition: ald_nor_lcd.h:122
ALD_NOR_STATUS_ERROR
Definition: ald_nor_lcd.h:123
ALD_NOR_STATUS_SUCCESS
Definition: ald_nor_lcd.h:121
nor_status_t
nor_status_t
EBI NOR Status typedef.
Definition: ald_nor_lcd.h:120


ALD User Manual: nor_id_t Struct Reference

Data Fields
nor_id_t Struct Reference
EASTSOFT ES32F3xx ALD » NOR_LCD » NOR_LCD Public Types

EBI NOR ID typedef. More...

#include <ald_nor_lcd.h>

Data Fields

uint16_t | m_code
uint16_t | device_code1
uint16_t | device_code2
uint16_t | device_code3

Detailed Description

EBI NOR ID typedef.

Definition at line 130 of file ald_nor_lcd.h.

Field Documentation

◆ device_code1

uint16_t device_code1

DEVICE_CODE1_ADDR code1

Definition at line 132 of file ald_nor_lcd.h.

◆ device_code2

uint16_t device_code2

DEVICE_CODE1_ADDR code2

Definition at line 133 of file ald_nor_lcd.h.

◆ device_code3

uint16_t device_code3

DEVICE_CODE1_ADDR code3

Definition at line 134 of file ald_nor_lcd.h.

◆ m_code

uint16_t m_code

Defines the device's manufacturer code used to identify the memory

Definition at line 131 of file ald_nor_lcd.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_nor_lcd.h


ALD User Manual: nor_cfi_t Struct Reference

Data Fields
nor_cfi_t Struct Reference
EASTSOFT ES32F3xx ALD » NOR_LCD » NOR_LCD Public Types

EBI NOR CFI typedef. More...

#include <ald_nor_lcd.h>

Data Fields

uint16_t | cfi_1
uint16_t | cfi_2
uint16_t | cfi_3
uint16_t | cfi_4

Detailed Description

EBI NOR CFI typedef.

Definition at line 140 of file ald_nor_lcd.h.

Field Documentation

◆ cfi_1

uint16_t cfi_1

NOR CFI 1

Definition at line 141 of file ald_nor_lcd.h.

◆ cfi_2

uint16_t cfi_2

NOR CFI 2

Definition at line 142 of file ald_nor_lcd.h.

◆ cfi_3

uint16_t cfi_3

NOR CFI 3

Definition at line 143 of file ald_nor_lcd.h.

◆ cfi_4

uint16_t cfi_4

NOR CFI 4

Definition at line 144 of file ald_nor_lcd.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_nor_lcd.h


ALD User Manual: nor_handle_t Struct Reference

Data Fields
nor_handle_t Struct Reference
EASTSOFT ES32F3xx ALD » NOR_LCD » NOR_LCD Public Types

NOR handle Structure definition. More...

#include <ald_nor_lcd.h>

Collaboration diagram for nor_handle_t:
[legend]

Data Fields

EBI_NOR_SRAM_TypeDef * instance
EBI_NOR_SRAM_EXTENDED_TypeDef * ext
ald_ebi_nor_sram_init_t init
lock_state_t lock
__IO ald_nor_state_t state

Detailed Description

NOR handle Structure definition.

Definition at line 150 of file ald_nor_lcd.h.

Field Documentation

◆ ext

EBI_NOR_SRAM_EXTENDED_TypeDef* ext

Extended mode register base address

Definition at line 152 of file ald_nor_lcd.h.

◆ init

ald_ebi_nor_sram_init_t init

NOR device control configuration parameters

Definition at line 153 of file ald_nor_lcd.h.

◆ instance

EBI_NOR_SRAM_TypeDef* instance

Register base address

Definition at line 151 of file ald_nor_lcd.h.

◆ lock

lock_state_t lock

NOR locking object

Definition at line 154 of file ald_nor_lcd.h.

◆ state

__IO ald_nor_state_t state

NOR device access state

Definition at line 155 of file ald_nor_lcd.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_nor_lcd.h


ALD User Manual: NOR_Public_Functions

Modules
NOR_Public_Functions
EASTSOFT ES32F3xx ALD » NOR_LCD
Collaboration diagram for NOR_Public_Functions:

Modules

NOR_Public_Functions_Group1
I/O operation functions
NOR_LCD I/O operation functions.
Control functions
NOR_LCD Control functions.
State functions
NOR_LCD State functions.

Detailed Description


ALD User Manual: NOR_Public_Functions_Group1

Functions
NOR_Public_Functions_Group1
EASTSOFT ES32F3xx ALD » NOR_LCD » NOR_Public_Functions
Collaboration diagram for NOR_Public_Functions_Group1:

Functions

ald_status_t | ald_nor_init (nor_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing)
Perform the NOR memory Initialization sequence. More...
ald_status_t | ald_nor_deinit (nor_handle_t *hperh)
Perform NOR memory De-Initialization sequence. More...

Detailed Description

Function Documentation

◆ ald_nor_deinit()

ald_status_t ald_nor_deinit ( nor_handle_t * hperh )

Perform NOR memory De-Initialization sequence.

Parameters
hperh pointer to a nor_handle_t structure
Return values
ald status

Definition at line 84 of file ald_nor_lcd.c.

85 {
86 ald_ebi_nor_sram_deinit(hperh->instance, hperh->ext, hperh->init.bank);
87 hperh->state = ALD_NOR_STATE_RESET;
88 __UNLOCK(hperh);
89
90 return OK;
91 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
ald_ebi_nor_sram_deinit
ald_status_t ald_ebi_nor_sram_deinit(EBI_NOR_SRAM_TypeDef *dev, EBI_NOR_SRAM_EXTENDED_TypeDef *e_dev, uint32_t bank)
DeInitialize the EBI_NOR_SRAM peripheral.
Definition: ald_ebi.c:172
nor_handle_t::instance
EBI_NOR_SRAM_TypeDef * instance
Definition: ald_nor_lcd.h:151
nor_handle_t::state
__IO ald_nor_state_t state
Definition: ald_nor_lcd.h:155
nor_handle_t::ext
EBI_NOR_SRAM_EXTENDED_TypeDef * ext
Definition: ald_nor_lcd.h:152
ALD_NOR_STATE_RESET
Definition: ald_nor_lcd.h:110
nor_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_nor_lcd.h:153
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399

◆ ald_nor_init()

ald_status_t ald_nor_init | ( | nor_handle_t * | hperh,
 |  | ald_ebi_nor_sram_timing_t * | timing,
 |  | ald_ebi_nor_sram_timing_t * | ext_timing
 | ) |  |

Perform the NOR memory Initialization sequence.

Parameters
hperh | pointer to a nor_handle_t structure
timing | pointer to NOR control timing structure
ext_timing | pointer to NOR extended mode timing structure
Return values
ald status

Definition at line 53 of file ald_nor_lcd.c.

54 {
55 if (hperh == NULL)
56 return ERROR;
57 if (hperh->state == ALD_NOR_STATE_RESET)
58 hperh->lock = UNLOCK;
59
60 /* Initialize NOR control Interface */
61 ald_ebi_nor_sram_init(hperh->instance, &(hperh->init));
62 /* Initialize NOR timing Interface */
63 ald_ebi_nor_sram_timing_init(hperh->instance, timing, hperh->init.bank);
64 /* Initialize NOR extended mode timing Interface */
65 ald_ebi_nor_sram_ext_timing_init(hperh->ext, ext_timing, hperh->init.bank, hperh->init.ext_mode);
66 /* Enable the NORSRAM device */
67 ald_ebi_nor_sram_enable(hperh->instance, hperh->init.bank);
68
69 /* Initialize NOR Memory Data Width*/
70 if (hperh->init.width == EBI_NORSRAM_MEM_BUS_WIDTH_8)
71 NORMEMDATWIDTH = NOR_MEMORY_8B;
72 else
73 NORMEMDATWIDTH = NOR_MEMORY_16B;
74
75 hperh->state = ALD_NOR_STATE_READY;
76 return OK;
77 }
ALD_NOR_STATE_READY
Definition: ald_nor_lcd.h:111
OK
Definition: utils.h:55
UNLOCK
Definition: type.h:59
ald_ebi_nor_sram_init_t::ext_mode
ebi_extended_mode_t ext_mode
Definition: ald_ebi.h:409
ald_ebi_nor_sram_timing_init
void ald_ebi_nor_sram_timing_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank)
Initialize the EBI_NOR_SRAM Timing according to the specified parameters in the EBI_NOR_SRAM_TimingTy...
Definition: ald_ebi.c:104
NORMEMDATWIDTH
static uint32_t NORMEMDATWIDTH
Definition: ald_nor_lcd.c:33
nor_handle_t::lock
lock_state_t lock
Definition: ald_nor_lcd.h:154
nor_handle_t::instance
EBI_NOR_SRAM_TypeDef * instance
Definition: ald_nor_lcd.h:151
EBI_NORSRAM_MEM_BUS_WIDTH_8
Definition: ald_ebi.h:209
nor_handle_t::state
__IO ald_nor_state_t state
Definition: ald_nor_lcd.h:155
nor_handle_t::ext
EBI_NOR_SRAM_EXTENDED_TypeDef * ext
Definition: ald_nor_lcd.h:152
ALD_NOR_STATE_RESET
Definition: ald_nor_lcd.h:110
NOR_MEMORY_16B
#define NOR_MEMORY_16B
Definition: ald_nor_lcd.h:56
ald_ebi_nor_sram_init
void ald_ebi_nor_sram_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_init_t *init)
Initialize the EBI_NOR_SRAM device according to the specified control parameters in the EBI_NOR_SRAM_...
Definition: ald_ebi.c:43
ald_ebi_nor_sram_init_t::width
ebi_norsram_mem_bus_width_t width
Definition: ald_ebi.h:402
NOR_MEMORY_8B
#define NOR_MEMORY_8B
Definition: ald_nor_lcd.h:55
nor_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_nor_lcd.h:153
ERROR
Definition: utils.h:56
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399
ald_ebi_nor_sram_enable
void ald_ebi_nor_sram_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Enable the NOR/SRAM device access.
Definition: ald_ebi.c:206
ald_ebi_nor_sram_ext_timing_init
void ald_ebi_nor_sram_ext_timing_init(EBI_NOR_SRAM_EXTENDED_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank, uint32_t mode)
Initialize the EBI_NOR_SRAM Extended mode Timing according to the specified parameters in the EBI_NOR...
Definition: ald_ebi.c:138


ALD User Manual: PIS

Modules
PIS
EASTSOFT ES32F3xx ALD

PIS module driver. More...

Collaboration diagram for PIS:

Modules

PIS Public Functions
PIS Public Types
PIS Private Macros

Detailed Description

PIS module driver.


ALD User Manual: PIS Public Functions

Modules
PIS Public Functions
EASTSOFT ES32F3xx ALD » PIS
Collaboration diagram for PIS Public Functions:

Modules

Initialization functions
Initialization and Configuration functions.
Operation functions
PIS output enable or disable functions.
Peripheral State and Errors functions
PIS State and Errors functions.
modulate output functions
PIS modulate output signal functions.

Detailed Description


ALD User Manual: Initialization functions

Functions
Initialization functions
EASTSOFT ES32F3xx ALD » PIS » PIS Public Functions

Initialization and Configuration functions. More...

Collaboration diagram for Initialization functions:

Functions

ald_status_t | ald_pis_create (pis_handle_t *hperh)
Create the PIS mode according to the specified parameters in the pis_handle_t and create the associated handle. More...
ald_status_t | ald_pis_destroy (pis_handle_t *hperh)
Destroy the PIS mode according to the specified parameters in the pis_init_t and create the associated handle. More...

Detailed Description

Initialization and Configuration functions.

Function Documentation

◆ ald_pis_create()

ald_status_t ald_pis_create ( pis_handle_t * hperh )

Create the PIS mode according to the specified parameters in the pis_handle_t and create the associated handle.

Parameters
hperh Pointer to a pis_handle_t structure that contains the configuration information for the specified PIS module.
Return values
Status,see ald_status_t.

Definition at line 45 of file ald_pis.c.

46 {
47 if (hperh == NULL)
48 return ERROR;
49
50 assert_param(IS_PIS_SRC(hperh->init.producer_src));
51 assert_param(IS_PIS_TRIG(hperh->init.consumer_trig));
52 assert_param(IS_PIS_CLOCK(hperh->init.producer_clk));
53 assert_param(IS_PIS_CLOCK(hperh->init.consumer_clk));
54 assert_param(IS_PIS_EDGE(hperh->init.producer_edge));
55 assert_param(IS_PIS_SIGNAL_MODE(hperh->init.producer_signal));
56
57 __LOCK(hperh);
58 hperh->perh = PIS;
59
60 /* get location of consumer in channel and position of con0/con1
61 * accord to comsumer_trig information */
62 hperh->consumer_ch = (pis_ch_t)(hperh->init.consumer_trig & 0x0F);
63 hperh->consumer_con = (pis_con_t)((hperh->init.consumer_trig >> 4) & 0x0F);
64 hperh->consumer_pos = (1U << (uint32_t)((hperh->init.consumer_trig >> 8) & 0xFF));
65
66 if (hperh->perh->CH_CON[hperh->consumer_ch] != 0) {
67 __UNLOCK(hperh);
68 return BUSY;
69 }
70
71 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SRCS_MSK, ((hperh->init.producer_src) >> 4) << PIS_CH0_CON_SRCS_POSS);
72 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_MSIGS_MSK, ((hperh->init.producer_src) & 0xf) << PIS_CH0_CON_MSIGS_POSS);
73
74 if (hperh->init.producer_clk == hperh->init.consumer_clk) {
75 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_DIRECT << PIS_CH0_CON_SYNCSEL_POSS);
76 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, (hperh->init.consumer_clk) << PIS_CH0_CON_PULCK_POSS);
77 }
78 else {
79 if (hperh->init.producer_signal == PIS_OUT_LEVEL) {
80 if (hperh->init.consumer_clk == PIS_CLK_PCLK1)
81 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_LEVEL_ASY_APB1 << PIS_CH0_CON_SYNCSEL_POSS);
82 if (hperh->init.consumer_clk == PIS_CLK_PCLK2)
83 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_LEVEL_ASY_APB2 << PIS_CH0_CON_SYNCSEL_POSS);
84 if (hperh->init.consumer_clk == PIS_CLK_SYS)
85 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_LEVEL_ASY_AHB << PIS_CH0_CON_SYNCSEL_POSS);
86 }
87
88 if (hperh->init.producer_signal == PIS_OUT_PULSE) {
89 if (hperh->init.consumer_clk == PIS_CLK_PCLK1)
90 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_PULSE_ASY_APB1 << PIS_CH0_CON_SYNCSEL_POSS);
91 if (hperh->init.consumer_clk == PIS_CLK_PCLK2)
92 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_PULSE_ASY_APB2 << PIS_CH0_CON_SYNCSEL_POSS);
93 if (hperh->init.consumer_clk == PIS_CLK_SYS)
94 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_PULSE_ASY_AHB << PIS_CH0_CON_SYNCSEL_POSS);
95 }
96 }
97
98 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, hperh->init.consumer_clk << PIS_CH0_CON_PULCK_POSS);
99 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_EDGS_MSK, hperh->init.producer_edge << PIS_CH0_CON_EDGS_POSS);
100 hperh->check_info = hperh->perh->CH_CON[hperh->consumer_ch];
101
102 /* enable consumer bit, switch pin of consumer */
103 if (hperh->init.input_chan == PIS_CHAN_INPUT) {
104 switch (hperh->consumer_con) {
105 case PIS_CON_0:
106 PIS->TAR_CON0 |= hperh->consumer_pos;
107 break;
108 case PIS_CON_1:
109 PIS->TAR_CON1 |= hperh->consumer_pos;
110 break;
111 default:
112 break;
113 }
114 }
115
116 __UNLOCK(hperh);
117 return OK;
118 }
OK
Definition: utils.h:55
IS_PIS_EDGE
#define IS_PIS_EDGE(x)
Definition: ald_pis.h:623
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
pis_con_t
pis_con_t
Indirect value,no care of it.
Definition: ald_pis.h:322
PIS_CLK_PCLK1
Definition: ald_pis.h:251
PIS_OUT_LEVEL
Definition: ald_pis.h:271
pis_init_t::producer_src
pis_src_t producer_src
Definition: ald_pis.h:396
PIS_CON_1
Definition: ald_pis.h:324
PIS_SYN_PULSE_ASY_APB2
Definition: ald_pis.h:283
IS_PIS_TRIG
#define IS_PIS_TRIG(x)
Definition: ald_pis.h:558
pis_handle_s::consumer_ch
pis_ch_t consumer_ch
Definition: ald_pis.h:421
IS_PIS_CLOCK
#define IS_PIS_CLOCK(x)
Definition: ald_pis.h:618
PIS_SYN_PULSE_ASY_AHB
Definition: ald_pis.h:284
pis_ch_t
pis_ch_t
Pis channel.
Definition: ald_pis.h:290
IS_PIS_SIGNAL_MODE
#define IS_PIS_SIGNAL_MODE(x)
Definition: ald_pis.h:621
IS_PIS_SRC
#define IS_PIS_SRC(x)
Definition: ald_pis.h:437
PIS_CHAN_INPUT
Definition: ald_pis.h:389
PIS_CLK_SYS
Definition: ald_pis.h:253
pis_init_t::input_chan
pis_input_sel_t input_chan
Definition: ald_pis.h:402
PIS_SYN_LEVEL_ASY_AHB
Definition: ald_pis.h:281
pis_init_t::producer_signal
pis_output_t producer_signal
Definition: ald_pis.h:397
pis_init_t::producer_edge
pis_edge_t producer_edge
Definition: ald_pis.h:399
PIS_CON_0
Definition: ald_pis.h:323
PIS_SYN_LEVEL_ASY_APB1
Definition: ald_pis.h:279
pis_handle_s::consumer_pos
uint8_t consumer_pos
Definition: ald_pis.h:423
PIS_SYN_DIRECT
Definition: ald_pis.h:278
PIS_OUT_PULSE
Definition: ald_pis.h:272
PIS_CLK_PCLK2
Definition: ald_pis.h:252
pis_handle_s::perh
PIS_TypeDef * perh
Definition: ald_pis.h:419
pis_handle_s::consumer_con
pis_con_t consumer_con
Definition: ald_pis.h:422
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
pis_init_t::producer_clk
pis_clock_t producer_clk
Definition: ald_pis.h:398
pis_handle_s::init
pis_init_t init
Definition: ald_pis.h:420
pis_init_t::consumer_trig
pis_trig_t consumer_trig
Definition: ald_pis.h:400
pis_handle_s::check_info
uint32_t check_info
Definition: ald_pis.h:424
PIS_SYN_PULSE_ASY_APB1
Definition: ald_pis.h:282
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
pis_init_t::consumer_clk
pis_clock_t consumer_clk
Definition: ald_pis.h:401
PIS_SYN_LEVEL_ASY_APB2
Definition: ald_pis.h:280

◆ ald_pis_destroy()

ald_status_t ald_pis_destroy ( pis_handle_t * hperh )

Destroy the PIS mode according to the specified parameters in the pis_init_t and create the associated handle.

Parameters
hperh Pointer to a pis_handle_t structure that contains the configuration information for the specified PIS module.
Return values
Status,see ald_status_t.

Definition at line 127 of file ald_pis.c.

128 {
129 assert_param(IS_PIS(hperh->perh));
130
131 if (hperh->check_info != hperh->perh->CH_CON[hperh->consumer_ch])
132 return ERROR;
133
134 __LOCK(hperh);
135
136 CLEAR_BIT(PIS->CH_OER, (1U << (uint32_t)hperh->consumer_ch));
137 WRITE_REG(hperh->perh->CH_CON[hperh->consumer_ch], 0x0);
138
139 switch (hperh->consumer_con) {
140 case PIS_CON_0:
141 PIS->TAR_CON0 &= ~(hperh->consumer_pos);
142 break;
143 case PIS_CON_1:
144 PIS->TAR_CON1 &= ~(hperh->consumer_pos);
145 break;
146 default:
147 break;
148 }
149
150 hperh->state = PIS_STATE_RESET;
151 __UNLOCK(hperh);
152
153 return OK;
154 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
PIS_STATE_RESET
Definition: ald_pis.h:332
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
PIS_CON_1
Definition: ald_pis.h:324
pis_handle_s::consumer_ch
pis_ch_t consumer_ch
Definition: ald_pis.h:421
PIS_CON_0
Definition: ald_pis.h:323
pis_handle_s::consumer_pos
uint8_t consumer_pos
Definition: ald_pis.h:423
pis_handle_s::state
pis_state_t state
Definition: ald_pis.h:426
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
pis_handle_s::perh
PIS_TypeDef * perh
Definition: ald_pis.h:419
pis_handle_s::consumer_con
pis_con_t consumer_con
Definition: ald_pis.h:422
IS_PIS
#define IS_PIS(x)
Definition: ald_pis.h:436
pis_handle_s::check_info
uint32_t check_info
Definition: ald_pis.h:424
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56


ALD User Manual: Operation functions

Functions
Operation functions
EASTSOFT ES32F3xx ALD » PIS » PIS Public Functions

PIS output enable or disable functions. More...

Collaboration diagram for Operation functions:

Functions

ald_status_t | ald_pis_output_start (pis_handle_t *hperh, pis_out_ch_t ch)
Start the PIS output function. More...
ald_status_t | ald_pis_output_stop (pis_handle_t *hperh, pis_out_ch_t ch)
Stop the PIS output function. More...

Detailed Description

PIS output enable or disable functions.

Function Documentation

◆ ald_pis_output_start()

ald_status_t ald_pis_output_start | ( | pis_handle_t * | hperh,
 |  | pis_out_ch_t | ch
 | ) |  |

Start the PIS output function.

Parameters
hperh Pointer to a pis_handle_t structure that contains the configuration information for the specified PIS module.
ch The PIS channel enable output This parameter can be one of the following values:
  • PIS_OUT_CH_0
  • PIS_OUT_CH_1
  • PIS_OUT_CH_2
  • PIS_OUT_CH_3
Return values
Status,see ald_status_t.

Definition at line 176 of file ald_pis.c.

177 {
178 assert_param(IS_PIS(hperh->perh));
179 assert_param(IS_PIS_OUPUT_CH(ch));
180 __LOCK(hperh);
181 SET_BIT(PIS->CH_OER, (1 << ch));
182 __UNLOCK(hperh);
183
184 return OK;
185 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
IS_PIS_OUPUT_CH
#define IS_PIS_OUPUT_CH(x)
Definition: ald_pis.h:629
assert_param
#define assert_param(x)
Definition: type.h:88
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
pis_handle_s::perh
PIS_TypeDef * perh
Definition: ald_pis.h:419
IS_PIS
#define IS_PIS(x)
Definition: ald_pis.h:436
__LOCK
#define __LOCK(x)
Definition: utils.h:92

◆ ald_pis_output_stop()

ald_status_t ald_pis_output_stop | ( | pis_handle_t * | hperh,
 |  | pis_out_ch_t | ch
 | ) |  |

Stop the PIS output function.

Parameters
hperh Pointer to a pis_handle_t structure that contains the configuration information for the specified PIS module.
ch The PIS channel disable output This parameter can be one of the following values:
  • PIS_OUT_CH_0
  • PIS_OUT_CH_1
  • PIS_OUT_CH_2
  • PIS_OUT_CH_3
Return values
Status,see ald_status_t.

Definition at line 199 of file ald_pis.c.

200 {
201 assert_param(IS_PIS(hperh->perh));
202 assert_param(IS_PIS_OUPUT_CH(ch));
203 __LOCK(hperh);
204 CLEAR_BIT(PIS->CH_OER, (1 << ch));
205 __UNLOCK(hperh);
206
207 return OK;
208 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
IS_PIS_OUPUT_CH
#define IS_PIS_OUPUT_CH(x)
Definition: ald_pis.h:629
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
pis_handle_s::perh
PIS_TypeDef * perh
Definition: ald_pis.h:419
IS_PIS
#define IS_PIS(x)
Definition: ald_pis.h:436
__LOCK
#define __LOCK(x)
Definition: utils.h:92


ALD User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
EASTSOFT ES32F3xx ALD » PIS » PIS Public Functions

PIS State and Errors functions. More...

Collaboration diagram for Peripheral State and Errors functions:

Functions

pis_state_t ald_pis_get_state (pis_handle_t *hperh)
Returns the PIS state. More...

Detailed Description

PIS State and Errors functions.

Function Documentation

◆ ald_pis_get_state()

pis_state_t ald_pis_get_state ( pis_handle_t * hperh )

Returns the PIS state.

Parameters
hperh Pointer to a pis_handle_t structure that contains the configuration information for the specified PIS module.
Return values
ALD state

Definition at line 224 of file ald_pis.c.

225 {
226 assert_param(IS_PIS(hperh->perh));
227 return hperh->state;
228 }
assert_param
#define assert_param(x)
Definition: type.h:88
pis_handle_s::state
pis_state_t state
Definition: ald_pis.h:426
pis_handle_s::perh
PIS_TypeDef * perh
Definition: ald_pis.h:419
IS_PIS
#define IS_PIS(x)
Definition: ald_pis.h:436


ALD User Manual: modulate output functions

Functions
modulate output functions
EASTSOFT ES32F3xx ALD » PIS » PIS Public Functions

PIS modulate output signal functions. More...

Collaboration diagram for modulate output functions:

Functions

ald_status_t ald_pis_modu_config (pis_handle_t *hperh, pis_modulate_config_t *config)
Config the PIS modulate signal function. More...

Detailed Description

PIS modulate output signal functions.

Function Documentation

◆ ald_pis_modu_config()

ald_status_t ald_pis_modu_config | ( | pis_handle_t * | hperh,
 |  | pis_modulate_config_t * | config
 | ) |  |

Config the PIS modulate signal function.

Parameters
hperh | Pointer to a pis_handle_t structure that contains the configuration information for the specified PIS module.
config | Pointer to a pis_modulate_config_t structure that contains the selected target (UART0,UART1,UART2,UART3 or LPUART0) how to modulate the target output signal.
Return values
Status,see ald_status_t.

Definition at line 248 of file ald_pis.c.

249 {
250 assert_param(IS_PIS(hperh->perh));
251 assert_param(IS_PIS_MODU_TARGET(config->target));
252 assert_param(IS_PIS_MODU_LEVEL(config->level));
253 assert_param(IS_PIS_MODU_SRC(config->src));
254 assert_param(IS_PIS_MODU_CHANNEL(config->channel));
255 __LOCK(hperh);
256
257 switch (config->target) {
258 case PIS_UART0_TX:
259 MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXMLVLS_MSK, config->level << PIS_UART0_TXMCR_TXMLVLS_POS);
260 MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXMSS_MSK, config->src << PIS_UART0_TXMCR_TXMSS_POSS);
261 MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXSIGS_MSK, config->channel << PIS_UART0_TXMCR_TXSIGS_POSS);
262 break;
263
264 case PIS_UART1_TX:
265 MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXMLVLS_MSK, config->level << PIS_UART1_TXMCR_TXMLVLS_POS);
266 MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXMSS_MSK, config->src << PIS_UART1_TXMCR_TXMSS_POSS);
267 MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXSIGS_MSK, config->channel << PIS_UART1_TXMCR_TXSIGS_POSS);
268 break;
269
270 case PIS_UART2_TX:
271 MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXMLVLS_MSK, config->level << PIS_UART2_TXMCR_TXMLVLS_POS);
272 MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXMSS_MSK, config->src << PIS_UART2_TXMCR_TXMSS_POSS);
273 MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXSIGS_MSK, config->channel << PIS_UART2_TXMCR_TXSIGS_POSS);
274 break;
275
276 case PIS_UART3_TX:
277 MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXMLVLS_MSK, config->level << PIS_UART3_TXMCR_TXMLVLS_POS);
278 MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXMSS_MSK, config->src << PIS_UART3_TXMCR_TXMSS_POSS);
279 MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXSIGS_MSK, config->channel << PIS_UART3_TXMCR_TXSIGS_POSS);
280 break;
281
282 case PIS_LPUART0_TX:
283 MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_LPUART0_TXMCR_TXMLVLS_MSK, config->level << PIS_LPUART0_TXMCR_TXMLVLS_POS);
284 MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_LPUART0_TXMCR_TXMSS_MSK, config->src << PIS_LPUART0_TXMCR_TXMSS_POSS);
285 MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_LPUART0_TXMCR_TXSIGS_MSK, config->channel << PIS_LPUART0_TXMCR_TXSIGS_POSS);
286 break;
287
288 default:
289 break;
290 }
291
292 __UNLOCK(hperh);
293 return OK;
294 }
pis_modulate_config_t::level
pis_modu_level_t level
Definition: ald_pis.h:410
IS_PIS_MODU_CHANNEL
#define IS_PIS_MODU_CHANNEL(x)
Definition: ald_pis.h:649
pis_modulate_config_t::target
pis_modu_targ_t target
Definition: ald_pis.h:409
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
IS_PIS_MODU_TARGET
#define IS_PIS_MODU_TARGET(x)
Definition: ald_pis.h:633
PIS_UART2_TX
Definition: ald_pis.h:345
pis_modulate_config_t::src
pis_modu_src_t src
Definition: ald_pis.h:411
PIS_UART1_TX
Definition: ald_pis.h:344
pis_modulate_config_t::channel
pis_modu_channel_t channel
Definition: ald_pis.h:412
IS_PIS_MODU_SRC
#define IS_PIS_MODU_SRC(x)
Definition: ald_pis.h:640
IS_PIS_MODU_LEVEL
#define IS_PIS_MODU_LEVEL(x)
Definition: ald_pis.h:638
pis_handle_s::perh
PIS_TypeDef * perh
Definition: ald_pis.h:419
PIS_LPUART0_TX
Definition: ald_pis.h:347
PIS_UART3_TX
Definition: ald_pis.h:346
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_PIS
#define IS_PIS(x)
Definition: ald_pis.h:436
__LOCK
#define __LOCK(x)
Definition: utils.h:92
PIS_UART0_TX
Definition: ald_pis.h:343


ALD User Manual: PIS Public Types

Data Structures | Typedefs | Enumerations
PIS Public Types
EASTSOFT ES32F3xx ALD » PIS
Collaboration diagram for PIS Public Types:

Data Structures

struct | pis_init_t
PIS init structure definition. More...
struct | pis_modulate_config_t
PIS modulate config structure definition. More...
struct | pis_handle_s
PIS Handle Structure definition. More...

Typedefs

typedef struct pis_handle_s pis_handle_t
PIS Handle Structure definition. More...

Enumerations

enum pis_src_t {
PIS_NON = 0x0U, PIS_GPIO_PIN0 = 0x10U, PIS_GPIO_PIN1 = 0x11U, PIS_GPIO_PIN2 = 0x12U,
PIS_GPIO_PIN3 = 0x13U, PIS_GPIO_PIN4 = 0x14U, PIS_GPIO_PIN5 = 0x15U, PIS_GPIO_PIN6 = 0x16U,
PIS_GPIO_PIN7 = 0x17U, PIS_GPIO_PIN8 = 0x18U, PIS_GPIO_PIN9 = 0x19U, PIS_GPIO_PIN10 = 0x1aU,
PIS_GPIO_PIN11 = 0x1bU, PIS_GPIO_PIN12 = 0x1cU, PIS_GPIO_PIN13 = 0x1dU, PIS_GPIO_PIN14 = 0x1eU,
PIS_GPIO_PIN15 = 0x1fU, PIS_ACMP_OUT0 = 0x30U, PIS_ACMP_OUT1 = 0x31U, PIS_DAC0_CH0 = 0x40U,
PIS_DAC0_CH1 = 0x41U, PIS_ADC0_INSERT = 0x60U, PIS_ADC0_NORMAL = 0x61U, PIS_ADC0_RESERVE = 0x62U,
PIS_LVD = 0x70U, PIS_UART0_RESERVE0 = 0x80U, PIS_UART0_RESERVE1 = 0x81U, PIS_UART0_IRDAOUT = 0x82U,
PIS_UART0_RTSOUT = 0x83U, PIS_UART0_TXOUT = 0x84U, PIS_UART0_SYN_SEND = 0x85U, PIS_UART0_SYN_RECV = 0x86U,
PIS_UART1_RESERVE0 = 0x90U, PIS_UART1_RESERVE1 = 0x91U, PIS_UART1_IRDA = 0x92U, PIS_UART1_RTS = 0x93U,
PIS_UART1_TXOUT = 0x94U, PIS_UART1_SYN_SEND = 0x95U, PIS_UART1_SYN_RECV = 0x96U, PIS_UART2_RESERVE0 = 0xa0U,
PIS_UART2_RESERVE1 = 0xa1U, PIS_UART2_IRDA = 0xa2U, PIS_UART2_RTS = 0xa3U, PIS_UART2_TXOUT = 0xa4U,
PIS_UART2_SYN_SEND = 0xa5U, PIS_UART2_SYN_RECV = 0xa6U, PIS_UART3_RESERVE0 = 0xb1U, PIS_UART3_RESERVE1 = 0xb2U,
PIS_UART3_IRDA = 0xb3U, PIS_UART3_RTS = 0xb4U, PIS_UART3_TXOUT = 0xb5U, PIS_UART3_SYN_SEND = 0xb6U,
PIS_UART3_SYN_RECV = 0xb7U, PIS_UART4_RECV = 0xc0U, PIS_UART4_SEND = 0xc1U, PIS_UART4_TXOUT = 0xc2U,
PIS_UART5_RECV = 0xd0U, PIS_UART5_SEND = 0xd1U, PIS_UART5_TXOUT = 0xd2U, PIS_SPI0_RECV = 0xe0U,
PIS_SPI0_SEND = 0xe1U, PIS_SPI0_NE = 0xe2U, PIS_SPI1_RECV = 0xf0U, PIS_SPI1_SEND = 0xf1U,
PIS_SPI1_NE = 0xf2U, PIS_I2C0_RECV = 0x100U, PIS_I2C0_SEND = 0x101U, PIS_I2C1_RECV = 0x110U,
PIS_I2C1_SEND = 0x111U, PIS_TIMER0_UPDATA = 0x120U, PIS_TIMER0_TRIG = 0x121U, PIS_TIMER0_INPUT_1 = 0x122U,
PIS_TIMER0_OUTPUT_1 = 0x123U, PIS_TIMER0_INPUT_2 = 0x124U, PIS_TIMER0_OUTPUT_2 = 0x125U, PIS_TIMER0_INPUT_3 = 0x126U,
PIS_TIMER0_OUTPUT_3 = 0x127U, PIS_TIMER0_INPUT_4 = 0x128U, PIS_TIMER0_OUTPUT_4 = 0x129U, PIS_TIMER1_UPDATA = 0x130U,
PIS_TIMER1_TRIG = 0x131U, PIS_TIMER1_INPUT_1 = 0x132U, PIS_TIMER1_OUTPUT_1 = 0x133U, PIS_TIMER1_INPUT_2 = 0x134U,
PIS_TIMER1_OUTPUT_2 = 0x135U, PIS_TIMER1_INPUT_3 = 0x136U, PIS_TIMER1_OUTPUT_3 = 0x137U, PIS_TIMER1_INPUT_4 = 0x138U,
PIS_TIMER1_OUTPUT_4 = 0x139U, PIS_TIMER2_UPDATA = 0x140U, PIS_TIMER2_TRIG = 0x141U, PIS_TIMER2_INPUT_1 = 0x142U,
PIS_TIMER2_OUTPUT_1 = 0x143U, PIS_TIMER2_INPUT_2 = 0x144U, PIS_TIMER2_OUTPUT_2 = 0x145U, PIS_TIMER2_INPUT_3 = 0x146U,
PIS_TIMER2_OUTPUT_3 = 0x147U, PIS_TIMER2_INPUT_4 = 0x148U, PIS_TIMER2_OUTPUT_4 = 0x149U, PIS_TIMER3_UPDATA = 0x150U,
PIS_TIMER3_TRIG = 0x151U, PIS_TIMER3_INPUT_1 = 0x152U, PIS_TIMER3_OUTPUT_1 = 0x153U, PIS_TIMER3_INPUT_2 = 0x154U,
PIS_TIMER3_OUTPUT_2 = 0x155U, PIS_TIMER3_INPUT_3 = 0x156U, PIS_TIMER3_OUTPUT_3 = 0x157U, PIS_TIMER3_INPUT_4 = 0x158U,
PIS_TIMER3_OUTPUT_4 = 0x159U, PIS_RTC_CLOCK = 0x160U, PIS_RTC_ALARM = 0x161U, PIS_LPTIMER0_SYN_UPDATA = 0x170U,
PIS_LPTIMER0_ASY_UPDATA = 0x171U, PIS_LPUART0_ASY_RECV = 0x180U, PIS_LPUART0_ASY_SEND = 0x181U, PIS_LPUART0_SYN_RECV = 0x182U,
PIS_LPUART0_SYN_SEND = 0x183U, PIS_DMA = 0x190U, PIS_ADC1_INSERT = 0x1a0U, PIS_ADC1_NORMAL = 0x1a1U,
PIS_ADC1_RESERVE = 0x1a2U
}
Producer entry. More...
enum pis_trig_t {
PIS_CH12_TIMER0_ITR0 = 0x003CU, PIS_CH13_TIMER0_ITR1 = 0x003DU, PIS_CH14_TIMER0_ITR2 = 0x003EU, PIS_CH15_TIMER0_ITR3 = 0x003FU,
PIS_CH12_TIMER1_ITR0 = 0x003CU, PIS_CH13_TIMER1_ITR1 = 0x003DU, PIS_CH14_TIMER1_ITR2 = 0x003EU, PIS_CH15_TIMER1_ITR3 = 0x003FU,
PIS_CH12_TIMER2_ITR0 = 0x003CU, PIS_CH13_TIMER2_ITR1 = 0x003DU, PIS_CH14_TIMER2_ITR2 = 0x003EU, PIS_CH15_TIMER2_ITR3 = 0x003FU,
PIS_CH12_TIMER3_ITR0 = 0x003CU, PIS_CH13_TIMER3_ITR1 = 0x003DU, PIS_CH14_TIMER3_ITR2 = 0x003EU, PIS_CH15_TIMER3_ITR3 = 0x003FU,
PIS_CH6_ADC0_NORMAL = 0x0036U, PIS_CH7_ADC0_INSERT = 0x0037U, PIS_CH0_ADC1_NORMAL = 0x0030U, PIS_CH1_ADC1_INSERT = 0x0031U,
PIS_CH0_LPTIM0_EXT0 = 0x0030U, PIS_CH1_LPTIM0_EXT1 = 0x0031U, PIS_CH2_LPTIM0_EXT2 = 0x0032U, PIS_CH3_LPTIM0_EXT3 = 0x0033U,
PIS_CH4_LPTIM0_EXT4 = 0x0034U, PIS_CH5_LPTIM0_EXT5 = 0x0035U, PIS_CH6_LPTIM0_EXT6 = 0x0036U, PIS_CH7_LPTIM0_EXT7 = 0x0037U,
PIS_CH7_DMA_REQUEST = 0x0037U, PIS_CH15_LPUART0_RXD = 0x081FU, PIS_CH14_UART5_RXD = 0x071EU, PIS_CH13_UART4_RXD = 0x061DU,
PIS_CH12_UART3_RXD = 0x031CU, PIS_CH11_UART2_RXD = 0x021BU, PIS_CH10_UART1_RXD = 0x011AU, PIS_CH9_UART0_RXD = 0x0019U,
PIS_CH8_TIMER3_CH4IN = 0x1B08U, PIS_CH8_TIMER2_CH4IN = 0x1308U, PIS_CH8_SPI1_CLK = 0x0F18U, PIS_CH7_TIMER3_CH3IN = 0x1A07U,
PIS_CH7_TIMER2_CH3IN = 0x1207U, PIS_CH7_SPI1_RX = 0x0E17U, PIS_CH6_TIMER3_CH2IN = 0x1906U, PIS_CH6_TIMER2_CH2IN = 0x1106U,
PIS_CH6_SPI0_CLK = 0x0D16U, PIS_CH5_TIMER3_CH1IN = 0x1805U, PIS_CH5_TIMER2_CH1IN = 0x1005U, PIS_CH5_SPI0_RX = 0x0C15U,
PIS_CH4_TIMER1_CH4IN = 0x0B04U, PIS_CH4_TIMER0_CH4IN = 0x0304U, PIS_CH3_TIMER1_CH3IN = 0x0A03U, PIS_CH3_TIMER0_CH3IN = 0x0203U,
PIS_CH2_TIMER1_CH2IN = 0x0902U, PIS_CH2_TIMER0_CH2IN = 0x0102U, PIS_CH1_TIMER1_CH1IN = 0x0801U, PIS_CH0_TIMER0_CH1IN = 0x0000U,
PIS_CH0_TIMER0_BRKIN = 0x0400U, PIS_CH0_TIMER1_BRKIN = 0x0C00U, PIS_TRIG_RESERVE = 0xFFFFU
}
Consumer entry. More...
enum | pis_clock_t { PIS_CLK_PCLK1 = 0U, PIS_CLK_PCLK2 = 1U, PIS_CLK_SYS = 2U, PIS_CLK_RESERVE = 3U }
Clock select. More...
enum | pis_edge_t { PIS_EDGE_NONE = 0U, PIS_EDGE_UP = 1U, PIS_EDGE_DOWN = 2U, PIS_EDGE_UP_DOWN = 3U }
Level select. More...
enum | pis_output_t { PIS_OUT_LEVEL = 0U, PIS_OUT_PULSE = 1U }
Output style. More...
enum pis_syncsel_t {
PIS_SYN_DIRECT = 0U, PIS_SYN_LEVEL_ASY_APB1 = 1U, PIS_SYN_LEVEL_ASY_APB2 = 2U, PIS_SYN_LEVEL_ASY_AHB = 3U,
PIS_SYN_PULSE_ASY_APB1 = 4U, PIS_SYN_PULSE_ASY_APB2 = 5U, PIS_SYN_PULSE_ASY_AHB = 6U
}
Sync select. More...
enum pis_ch_t {
PIS_CH_0 = 0U, PIS_CH_1 = 1U, PIS_CH_2 = 2U, PIS_CH_3 = 3U,
PIS_CH_4 = 4U, PIS_CH_5 = 5U, PIS_CH_6 = 6U, PIS_CH_7 = 7U,
PIS_CH_8 = 8U, PIS_CH_9 = 9U, PIS_CH_10 = 10U, PIS_CH_11 = 11U,
PIS_CH_12 = 12U, PIS_CH_13 = 13U, PIS_CH_14 = 14U, PIS_CH_15 = 15U
}
Pis channel. More...
enum | pis_out_ch_t { PIS_OUT_CH_0 = 0U, PIS_OUT_CH_1 = 1U, PIS_OUT_CH_2 = 2U, PIS_OUT_CH_3 = 3U }
Pis output channel. More...
enum | pis_con_t { PIS_CON_0 = 0U, PIS_CON_1 = 1U, PIS_CON_NONE = 2U }
Indirect value,no care of it. More...
enum pis_state_t {
PIS_STATE_RESET = 0x00U, PIS_STATE_READY = 0x01U, PIS_STATE_BUSY = 0x02U, PIS_STATE_TIMEOUT = 0x03U,
PIS_STATE_ERROR = 0x04U
}
PIS state structures definition. More...
enum pis_modu_targ_t {
PIS_UART0_TX = 0U, PIS_UART1_TX = 1U, PIS_UART2_TX = 2U, PIS_UART3_TX = 3U,
PIS_LPUART0_TX = 4U
}
PIS modulate target. More...
enum | pis_modu_level_t { PIS_LOW_LEVEL = 0U, PIS_HIGH_LEVEL = 1U }
PIS modulate level. More...
enum pis_modu_src_t {
PIS_SRC_NONE = 0U, PIS_SRC_TIMER0 = 1U, PIS_SRC_TIMER1 = 2U, PIS_SRC_TIMER2 = 3U,
PIS_SRC_TIMER3 = 4U, PIS_SRC_TIMER6 = 5U, PIS_SRC_TIMER7 = 6U, PIS_SRC_LPTIM0 = 7U,
PIS_SRC_BUZ = 8U
}
PIS modulate source. More...
enum | pis_modu_channel_t { PIS_TIMER_CH1 = 0U, PIS_TIMER_CH2 = 1U, PIS_TIMER_CH3 = 2U, PIS_TIMER_CH4 = 3U }
PIS modulate channel. More...
enum | pis_input_sel_t { PIS_NONE_INPUT = 0U, PIS_PORT_INPUT = 1U, PIS_CHAN_INPUT = 2U }
PIS input channel chose. More...

Detailed Description

  In PIS module, for the convenience of code maintenance,
  TIMERx is used to indicate the sequence of the timer peripheral.
  Different product series TIMERx represent different meanings:
  1. For ES32F36xx series:
  TIMER0 ----> AD16C4T0
  TIMER1 ----> AD16C4T1
  TIMER2 ----> GP32C4T0
  TIMER3 ----> GP32C4T1

  2. For ES32F393x/ES32F336x/ES32F392x series:
  TIMER0 ----> GP16C4T0
  TIMER1 ----> GP16C4T1
  TIMER2 ----> GP32C4T0
  TIMER3 ----> GP32C4T1

Typedef Documentation

◆ pis_handle_t

typedef struct pis_handle_s pis_handle_t

PIS Handle Structure definition.

Enumeration Type Documentation

◆ pis_ch_t

enum pis_ch_t

Pis channel.

Enumerator
PIS_CH_0 | Channel 0
PIS_CH_1 | Channel 1
PIS_CH_2 | Channel 2
PIS_CH_3 | Channel 3
PIS_CH_4 | Channel 4
PIS_CH_5 | Channel 5
PIS_CH_6 | Channel 6
PIS_CH_7 | Channel 7
PIS_CH_8 | Channel 8
PIS_CH_9 | Channel 9
PIS_CH_10 | Channel 10
PIS_CH_11 | Channel 11
PIS_CH_12 | Channel 12
PIS_CH_13 | Channel 13
PIS_CH_14 | Channel 14
PIS_CH_15 | Channel 15

Definition at line 290 of file ald_pis.h.

290 {
291 PIS_CH_0 = 0U,
292 PIS_CH_1 = 1U,
293 PIS_CH_2 = 2U,
294 PIS_CH_3 = 3U,
295 PIS_CH_4 = 4U,
296 PIS_CH_5 = 5U,
297 PIS_CH_6 = 6U,
298 PIS_CH_7 = 7U,
299 PIS_CH_8 = 8U,
300 PIS_CH_9 = 9U,
301 PIS_CH_10 = 10U,
302 PIS_CH_11 = 11U,
303 PIS_CH_12 = 12U,
304 PIS_CH_13 = 13U,
305 PIS_CH_14 = 14U,
306 PIS_CH_15 = 15U,
307 } pis_ch_t;
PIS_CH_13
Definition: ald_pis.h:304
PIS_CH_4
Definition: ald_pis.h:295
PIS_CH_0
Definition: ald_pis.h:291
PIS_CH_7
Definition: ald_pis.h:298
PIS_CH_6
Definition: ald_pis.h:297
PIS_CH_15
Definition: ald_pis.h:306
pis_ch_t
pis_ch_t
Pis channel.
Definition: ald_pis.h:290
PIS_CH_8
Definition: ald_pis.h:299
PIS_CH_10
Definition: ald_pis.h:301
PIS_CH_5
Definition: ald_pis.h:296
PIS_CH_14
Definition: ald_pis.h:305
PIS_CH_2
Definition: ald_pis.h:293
PIS_CH_12
Definition: ald_pis.h:303
PIS_CH_9
Definition: ald_pis.h:300
PIS_CH_3
Definition: ald_pis.h:294
PIS_CH_11
Definition: ald_pis.h:302
PIS_CH_1
Definition: ald_pis.h:292

◆ pis_clock_t

enum pis_clock_t

Clock select.

Enumerator
PIS_CLK_PCLK1 | APB1 peripherals clock
PIS_CLK_PCLK2 | APB2 peripherals clock
PIS_CLK_SYS | AHB peripherals clock
PIS_CLK_RESERVE | reserve clock

Definition at line 250 of file ald_pis.h.

250 {
251 PIS_CLK_PCLK1 = 0U,
252 PIS_CLK_PCLK2 = 1U,
253 PIS_CLK_SYS = 2U,
254 PIS_CLK_RESERVE = 3U,
255 } pis_clock_t;
PIS_CLK_PCLK1
Definition: ald_pis.h:251
pis_clock_t
pis_clock_t
Clock select.
Definition: ald_pis.h:250
PIS_CLK_SYS
Definition: ald_pis.h:253
PIS_CLK_PCLK2
Definition: ald_pis.h:252
PIS_CLK_RESERVE
Definition: ald_pis.h:254

◆ pis_con_t

enum pis_con_t

Indirect value,no care of it.

Enumerator
PIS_CON_0 | Con 0
PIS_CON_1 | Con 1
PIS_CON_NONE | None

Definition at line 322 of file ald_pis.h.

322 {
323 PIS_CON_0 = 0U,
324 PIS_CON_1 = 1U,
325 PIS_CON_NONE = 2U,
326 } pis_con_t;
pis_con_t
pis_con_t
Indirect value,no care of it.
Definition: ald_pis.h:322
PIS_CON_1
Definition: ald_pis.h:324
PIS_CON_NONE
Definition: ald_pis.h:325
PIS_CON_0
Definition: ald_pis.h:323

◆ pis_edge_t

enum pis_edge_t

Level select.

Enumerator
PIS_EDGE_NONE | None edge
PIS_EDGE_UP | Up edge
PIS_EDGE_DOWN | Down edge
PIS_EDGE_UP_DOWN | Up and down edge

Definition at line 260 of file ald_pis.h.

260 {
261 PIS_EDGE_NONE = 0U,
262 PIS_EDGE_UP = 1U,
263 PIS_EDGE_DOWN = 2U,
264 PIS_EDGE_UP_DOWN = 3U,
265 } pis_edge_t;
PIS_EDGE_UP_DOWN
Definition: ald_pis.h:264
PIS_EDGE_DOWN
Definition: ald_pis.h:263
PIS_EDGE_UP
Definition: ald_pis.h:262
PIS_EDGE_NONE
Definition: ald_pis.h:261
pis_edge_t
pis_edge_t
Level select.
Definition: ald_pis.h:260

◆ pis_input_sel_t

enum pis_input_sel_t

PIS input channel chose.

Enumerator
PIS_NONE_INPUT | Consumer input none
PIS_PORT_INPUT | Consumer input choose external port
PIS_CHAN_INPUT | Consumer input choose pis channel

Definition at line 386 of file ald_pis.h.

386 {
387 PIS_NONE_INPUT = 0U,
388 PIS_PORT_INPUT = 1U,
389 PIS_CHAN_INPUT = 2U,
390 } pis_input_sel_t;
PIS_PORT_INPUT
Definition: ald_pis.h:388
PIS_NONE_INPUT
Definition: ald_pis.h:387
pis_input_sel_t
pis_input_sel_t
PIS input channel chose.
Definition: ald_pis.h:386
PIS_CHAN_INPUT
Definition: ald_pis.h:389

◆ pis_modu_channel_t

enum pis_modu_channel_t

PIS modulate channel.

Enumerator
PIS_TIMER_CH1 | Src is TIMERx and choose channel 1
PIS_TIMER_CH2 | Src is TIMERx and choose channel 2
PIS_TIMER_CH3 | Src is TIMERx and choose channel 3
PIS_TIMER_CH4 | Src is TIMERx and choose channel 4

Definition at line 376 of file ald_pis.h.

376 {
377 PIS_TIMER_CH1 = 0U,
378 PIS_TIMER_CH2 = 1U,
379 PIS_TIMER_CH3 = 2U,
380 PIS_TIMER_CH4 = 3U,
381 } pis_modu_channel_t;
pis_modu_channel_t
pis_modu_channel_t
PIS modulate channel.
Definition: ald_pis.h:376
PIS_TIMER_CH2
Definition: ald_pis.h:378
PIS_TIMER_CH3
Definition: ald_pis.h:379
PIS_TIMER_CH4
Definition: ald_pis.h:380
PIS_TIMER_CH1
Definition: ald_pis.h:377

◆ pis_modu_level_t

enum pis_modu_level_t

PIS modulate level.

Enumerator
PIS_LOW_LEVEL | Modulate low level
PIS_HIGH_LEVEL | Modulate high level

Definition at line 353 of file ald_pis.h.

353 {
354 PIS_LOW_LEVEL = 0U,
355 PIS_HIGH_LEVEL = 1U,
356 } pis_modu_level_t;
PIS_LOW_LEVEL
Definition: ald_pis.h:354
PIS_HIGH_LEVEL
Definition: ald_pis.h:355
pis_modu_level_t
pis_modu_level_t
PIS modulate level.
Definition: ald_pis.h:353

◆ pis_modu_src_t

enum pis_modu_src_t

PIS modulate source.

Enumerator
PIS_SRC_NONE | Stop modulate
PIS_SRC_TIMER0 | Modulate source is TIMER0
PIS_SRC_TIMER1 | Modulate source is TIMER1
PIS_SRC_TIMER2 | Modulate source is TIMER2
PIS_SRC_TIMER3 | Modulate source is TIMER3
PIS_SRC_TIMER6 | Modulate source is TIMER6
PIS_SRC_TIMER7 | Modulate source is TIMER7
PIS_SRC_LPTIM0 | Modulate source is LPTIM0
PIS_SRC_BUZ | Modulate source is buz

Definition at line 361 of file ald_pis.h.

361 {
362 PIS_SRC_NONE = 0U,
363 PIS_SRC_TIMER0 = 1U,
364 PIS_SRC_TIMER1 = 2U,
365 PIS_SRC_TIMER2 = 3U,
366 PIS_SRC_TIMER3 = 4U,
367 PIS_SRC_TIMER6 = 5U,
368 PIS_SRC_TIMER7 = 6U,
369 PIS_SRC_LPTIM0 = 7U,
370 PIS_SRC_BUZ = 8U,
371 } pis_modu_src_t;
PIS_SRC_BUZ
Definition: ald_pis.h:370
PIS_SRC_TIMER0
Definition: ald_pis.h:363
pis_modu_src_t
pis_modu_src_t
PIS modulate source.
Definition: ald_pis.h:361
PIS_SRC_TIMER6
Definition: ald_pis.h:367
PIS_SRC_TIMER2
Definition: ald_pis.h:365
PIS_SRC_TIMER7
Definition: ald_pis.h:368
PIS_SRC_TIMER1
Definition: ald_pis.h:364
PIS_SRC_LPTIM0
Definition: ald_pis.h:369
PIS_SRC_NONE
Definition: ald_pis.h:362
PIS_SRC_TIMER3
Definition: ald_pis.h:366

◆ pis_modu_targ_t

enum pis_modu_targ_t

PIS modulate target.

Enumerator
PIS_UART0_TX | Modulate uart0 tx
PIS_UART1_TX | Modulate uart1 tx
PIS_UART2_TX | Modulate uart2 tx
PIS_UART3_TX | Modulate uart3 tx
PIS_LPUART0_TX | Modulate lpuart0 tx

Definition at line 342 of file ald_pis.h.

342 {
343 PIS_UART0_TX = 0U,
344 PIS_UART1_TX = 1U,
345 PIS_UART2_TX = 2U,
346 PIS_UART3_TX = 3U,
347 PIS_LPUART0_TX = 4U,
348 } pis_modu_targ_t;
PIS_UART2_TX
Definition: ald_pis.h:345
PIS_UART1_TX
Definition: ald_pis.h:344
pis_modu_targ_t
pis_modu_targ_t
PIS modulate target.
Definition: ald_pis.h:342
PIS_LPUART0_TX
Definition: ald_pis.h:347
PIS_UART3_TX
Definition: ald_pis.h:346
PIS_UART0_TX
Definition: ald_pis.h:343

◆ pis_out_ch_t

enum pis_out_ch_t

Pis output channel.

Enumerator
PIS_OUT_CH_0 | Channel 0
PIS_OUT_CH_1 | Channel 1
PIS_OUT_CH_2 | Channel 2
PIS_OUT_CH_3 | Channel 3

Definition at line 312 of file ald_pis.h.

312 {
313 PIS_OUT_CH_0 = 0U,
314 PIS_OUT_CH_1 = 1U,
315 PIS_OUT_CH_2 = 2U,
316 PIS_OUT_CH_3 = 3U,
317 } pis_out_ch_t;
PIS_OUT_CH_0
Definition: ald_pis.h:313
PIS_OUT_CH_1
Definition: ald_pis.h:314
PIS_OUT_CH_2
Definition: ald_pis.h:315
PIS_OUT_CH_3
Definition: ald_pis.h:316
pis_out_ch_t
pis_out_ch_t
Pis output channel.
Definition: ald_pis.h:312

◆ pis_output_t

enum pis_output_t

Output style.

Enumerator
PIS_OUT_LEVEL | Level
PIS_OUT_PULSE | Pulse

Definition at line 270 of file ald_pis.h.

270 {
271 PIS_OUT_LEVEL = 0U,
272 PIS_OUT_PULSE = 1U,
273 } pis_output_t;
PIS_OUT_LEVEL
Definition: ald_pis.h:271
pis_output_t
pis_output_t
Output style.
Definition: ald_pis.h:270
PIS_OUT_PULSE
Definition: ald_pis.h:272

◆ pis_src_t

enum pis_src_t

Producer entry.

Enumerator
PIS_NON | No async
PIS_GPIO_PIN0 | Pin0, level,support async
PIS_GPIO_PIN1 | Pin1, level,support async
PIS_GPIO_PIN2 | Pin2, level,support async
PIS_GPIO_PIN3 | Pin3, level,support async
PIS_GPIO_PIN4 | Pin4, level,support async
PIS_GPIO_PIN5 | Pin5, level,support async
PIS_GPIO_PIN6 | Pin6, level,support async
PIS_GPIO_PIN7 | Pin7, level,support async
PIS_GPIO_PIN8 | Pin8, level,support async
PIS_GPIO_PIN9 | Pin9, level,support async
PIS_GPIO_PIN10 | Pin10, level,support async
PIS_GPIO_PIN11 | Pin11, level,support async
PIS_GPIO_PIN12 | Pin12, level,support async
PIS_GPIO_PIN13 | Pin13, level,support async
PIS_GPIO_PIN14 | Pin14, level,support async
PIS_GPIO_PIN15 | Pin15, level,support async
PIS_ACMP_OUT0 | Acmp0 output, level,support async
PIS_ACMP_OUT1 | Acmp1 output, level,support async
PIS_DAC0_CH0 | Dac0 channel 0, pclk2 pulse,support async
PIS_DAC0_CH1 | Dac0 channel 1, pclk2 pulse,support async
PIS_ADC0_INSERT | Adc0 insert, pclk2 pulse,support async
PIS_ADC0_NORMAL | Adc0 normal, pclk2 pulse,support async
PIS_ADC0_RESERVE | Adc0 reserve
PIS_LVD | Lvd, level,support async
PIS_UART0_RESERVE0 | Uart0 reserve bit 0
PIS_UART0_RESERVE1 | Uart0 reserve bit 1
PIS_UART0_IRDAOUT | Uart0 irdaout, level,support async
PIS_UART0_RTSOUT | Uart0 rtsout, level,support async
PIS_UART0_TXOUT | Uart0 txout, level,support async
PIS_UART0_SYN_SEND | Uart0 syn send, pulse,support async
PIS_UART0_SYN_RECV | Uart0 syn recv, pulse,support async
PIS_UART1_RESERVE0 | Uart1 reserve bit 0
PIS_UART1_RESERVE1 | Uart1 reserve bit 1
PIS_UART1_IRDA | Uart1 irdaout, level,support async
PIS_UART1_RTS | Uart1 rtsout, level,support async
PIS_UART1_TXOUT | Uart1 txout, level,support async
PIS_UART1_SYN_SEND | Uart1 syn send, pulse,support async
PIS_UART1_SYN_RECV | Uart1 syn recv, pulse,support async
PIS_UART2_RESERVE0 | Uart2 reserve bit 0
PIS_UART2_RESERVE1 | Uart2 reserve bit 1
PIS_UART2_IRDA | Uart2 irdaout, level,support async
PIS_UART2_RTS | Uart2 rtsout, level,support async
PIS_UART2_TXOUT | Uart2 txout, level,support async
PIS_UART2_SYN_SEND | Uart2 syn send, pulse,support async
PIS_UART2_SYN_RECV | Uart2 syn recv, pulse,support async
PIS_UART3_RESERVE0 | Uart3 reserve bit 0
PIS_UART3_RESERVE1 | Uart3 reserve bit 1
PIS_UART3_IRDA | Uart3 irdaout, level,support async
PIS_UART3_RTS | Uart3 rtsout, level,support async
PIS_UART3_TXOUT | Uart3 txout, level,support async
PIS_UART3_SYN_SEND | Uart3 syn send, pulse,support async
PIS_UART3_SYN_RECV | Uart3 syn recv, pulse,support async
PIS_UART4_RECV | uart4 recv, plck1 pulse
PIS_UART4_SEND | uart4 send, plck1 pulse
PIS_UART4_TXOUT | uart4 txout, plck1 level
PIS_UART5_RECV | uart5 recv, plck1 pulse
PIS_UART5_SEND | uart5 send, plck1 pulse
PIS_UART5_TXOUT | uart5 txout, plck1 level
PIS_SPI0_RECV | Spi0 recv, plck1 pulse
PIS_SPI0_SEND | Spi0 send, plck1 pulse
PIS_SPI0_NE | Spi0 ne, plck1 level
PIS_SPI1_RECV | Spi1 recv, plck1 pulse
PIS_SPI1_SEND | Spi1 send, plck1 pulse
PIS_SPI1_NE | Spi1 ne, plck1 level
PIS_I2C0_RECV | I2c0 recv, plck1 level
PIS_I2C0_SEND | I2c0 send, plck1 level
PIS_I2C1_RECV | I2c1 recv, plck1 level
PIS_I2C1_SEND | I2c1 send, plck1 level
PIS_TIMER0_UPDATA | Timer0 updata, plck1 pulse
PIS_TIMER0_TRIG | Timer0 trig, plck1 pulse
PIS_TIMER0_INPUT_1 | Timer0 chan1 input catch, plck1 pulse
PIS_TIMER0_OUTPUT_1 | Timer0 chan1 output compare, plck1 pulse
PIS_TIMER0_INPUT_2 | Timer0 chan2 input catch, plck1 pulse
PIS_TIMER0_OUTPUT_2 | Timer0 chan2 output compare, plck1 pulse
PIS_TIMER0_INPUT_3 | Timer0 chan3 input catch, plck1 pulse
PIS_TIMER0_OUTPUT_3 | Timer0 chan3 output compare, plck1 pulse
PIS_TIMER0_INPUT_4 | Timer0 chan4 input catch, plck1 pulse
PIS_TIMER0_OUTPUT_4 | Timer0 chan4 output compare, plck1 pulse
PIS_TIMER1_UPDATA | Timer1 updata, plck1 pulse
PIS_TIMER1_TRIG | Timer1 trig, plck1 pulse
PIS_TIMER1_INPUT_1 | Timer1 chan1 input catch, plck1 pulse
PIS_TIMER1_OUTPUT_1 | Timer1 chan1 output compare, plck1 pulse
PIS_TIMER1_INPUT_2 | Timer1 chan2 input catch, plck1 pulse
PIS_TIMER1_OUTPUT_2 | Timer1 chan2 output compare, plck1 pulse
PIS_TIMER1_INPUT_3 | Timer1 chan3 input catch, plck1 pulse
PIS_TIMER1_OUTPUT_3 | Timer1 chan3 output compare, plck1 pulse
PIS_TIMER1_INPUT_4 | Timer1 chan4 input catch, plck1 pulse
PIS_TIMER1_OUTPUT_4 | Timer1 chan4 output compare, plck1 pulse
PIS_TIMER2_UPDATA | Timer2 updata, plck1 pulse
PIS_TIMER2_TRIG | Timer2 trig, plck1 pulse
PIS_TIMER2_INPUT_1 | Timer2 chan1 input catch, plck1 pulse
PIS_TIMER2_OUTPUT_1 | Timer2 chan1 output compare, plck1 pulse
PIS_TIMER2_INPUT_2 | Timer2 chan2 input catch, plck1 pulse
PIS_TIMER2_OUTPUT_2 | Timer2 chan2 output compare, plck1 pulse
PIS_TIMER2_INPUT_3 | Timer2 chan3 input catch, plck1 pulse
PIS_TIMER2_OUTPUT_3 | Timer2 chan3 output compare, plck1 pulse
PIS_TIMER2_INPUT_4 | Timer2 chan4 input catch, plck1 pulse
PIS_TIMER2_OUTPUT_4 | Timer2 chan4 output compare, plck1 pulse
PIS_TIMER3_UPDATA | Timer3 updata, plck1 pulse
PIS_TIMER3_TRIG | Timer3 trig, plck1 pulse
PIS_TIMER3_INPUT_1 | Timer3 chan1 input catch, plck1 pulse
PIS_TIMER3_OUTPUT_1 | Timer3 chan1 output compare, plck1 pulse
PIS_TIMER3_INPUT_2 | Timer3 chan2 input catch, plck1 pulse
PIS_TIMER3_OUTPUT_2 | Timer3 chan2 output compare, plck1 pulse
PIS_TIMER3_INPUT_3 | Timer3 chan3 input catch, plck1 pulse
PIS_TIMER3_OUTPUT_3 | Timer3 chan3 output compare, plck1 pulse
PIS_TIMER3_INPUT_4 | Timer3 chan4 input catch, plck1 pulse
PIS_TIMER3_OUTPUT_4 | Timer3 chan4 output compare, plck1 pulse
PIS_RTC_CLOCK | Rtc clock, pulse,support async
PIS_RTC_ALARM | Rtc alarm, pulse,support async
PIS_LPTIMER0_SYN_UPDATA | Lptimer0 syn updata, pulse,support async
PIS_LPTIMER0_ASY_UPDATA | Lptimer0 asy updata, pulse,support async
PIS_LPUART0_ASY_RECV | Lpuart0 asy recv, pulse,support async
PIS_LPUART0_ASY_SEND | Lpuart0 asy send, pulse,support async
PIS_LPUART0_SYN_RECV | Lpuart0 syn recv, pulse,support async
PIS_LPUART0_SYN_SEND | Lpuart0 syn recv, pulse,support async
PIS_DMA | Dma, pulse,support async
PIS_ADC1_INSERT | Adc1 insert, pclk2 pulse,support async
PIS_ADC1_NORMAL | Adc1 normal, pclk2 pulse,support async
PIS_ADC1_RESERVE | Adc1 reserve

Definition at line 58 of file ald_pis.h.

58 {
59 PIS_NON = 0x0U,
60 PIS_GPIO_PIN0 = 0x10U,
61 PIS_GPIO_PIN1 = 0x11U,
62 PIS_GPIO_PIN2 = 0x12U,
63 PIS_GPIO_PIN3 = 0x13U,
64 PIS_GPIO_PIN4 = 0x14U,
65 PIS_GPIO_PIN5 = 0x15U,
66 PIS_GPIO_PIN6 = 0x16U,
67 PIS_GPIO_PIN7 = 0x17U,
68 PIS_GPIO_PIN8 = 0x18U,
69 PIS_GPIO_PIN9 = 0x19U,
70 PIS_GPIO_PIN10 = 0x1aU,
71 PIS_GPIO_PIN11 = 0x1bU,
72 PIS_GPIO_PIN12 = 0x1cU,
73 PIS_GPIO_PIN13 = 0x1dU,
74 PIS_GPIO_PIN14 = 0x1eU,
75 PIS_GPIO_PIN15 = 0x1fU,
76 PIS_ACMP_OUT0 = 0x30U,
77 PIS_ACMP_OUT1 = 0x31U,
78 PIS_DAC0_CH0 = 0x40U,
79 PIS_DAC0_CH1 = 0x41U,
80 PIS_ADC0_INSERT = 0x60U,
81 PIS_ADC0_NORMAL = 0x61U,
82 PIS_ADC0_RESERVE = 0x62U,
83 PIS_LVD = 0x70U,
84 PIS_UART0_RESERVE0 = 0x80U,
85 PIS_UART0_RESERVE1 = 0x81U,
86 PIS_UART0_IRDAOUT = 0x82U,
87 PIS_UART0_RTSOUT = 0x83U,
88 PIS_UART0_TXOUT = 0x84U,
89 PIS_UART0_SYN_SEND = 0x85U,
90 PIS_UART0_SYN_RECV = 0x86U,
91 PIS_UART1_RESERVE0 = 0x90U,
92 PIS_UART1_RESERVE1 = 0x91U,
93 PIS_UART1_IRDA = 0x92U,
94 PIS_UART1_RTS = 0x93U,
95 PIS_UART1_TXOUT = 0x94U,
96 PIS_UART1_SYN_SEND = 0x95U,
97 PIS_UART1_SYN_RECV = 0x96U,
98 PIS_UART2_RESERVE0 = 0xa0U,
99 PIS_UART2_RESERVE1 = 0xa1U,
100 PIS_UART2_IRDA = 0xa2U,
101 PIS_UART2_RTS = 0xa3U,
102 PIS_UART2_TXOUT = 0xa4U,
103 PIS_UART2_SYN_SEND = 0xa5U,
104 PIS_UART2_SYN_RECV = 0xa6U,
105 PIS_UART3_RESERVE0 = 0xb1U,
106 PIS_UART3_RESERVE1 = 0xb2U,
107 PIS_UART3_IRDA = 0xb3U,
108 PIS_UART3_RTS = 0xb4U,
109 PIS_UART3_TXOUT = 0xb5U,
110 PIS_UART3_SYN_SEND = 0xb6U,
111 PIS_UART3_SYN_RECV = 0xb7U,
112 PIS_UART4_RECV = 0xc0U,
113 PIS_UART4_SEND = 0xc1U,
114 PIS_UART4_TXOUT = 0xc2U,
115 PIS_UART5_RECV = 0xd0U,
116 PIS_UART5_SEND = 0xd1U,
117 PIS_UART5_TXOUT = 0xd2U,
118 PIS_SPI0_RECV = 0xe0U,
119 PIS_SPI0_SEND = 0xe1U,
120 PIS_SPI0_NE = 0xe2U,
121 PIS_SPI1_RECV = 0xf0U,
122 PIS_SPI1_SEND = 0xf1U,
123 PIS_SPI1_NE = 0xf2U,
124 PIS_I2C0_RECV = 0x100U,
125 PIS_I2C0_SEND = 0x101U,
126 PIS_I2C1_RECV = 0x110U,
127 PIS_I2C1_SEND = 0x111U,
128 PIS_TIMER0_UPDATA = 0x120U,
129 PIS_TIMER0_TRIG = 0x121U,
130 PIS_TIMER0_INPUT_1 = 0x122U,
131 PIS_TIMER0_OUTPUT_1 = 0x123U,
132 PIS_TIMER0_INPUT_2 = 0x124U,
133 PIS_TIMER0_OUTPUT_2 = 0x125U,
134 PIS_TIMER0_INPUT_3 = 0x126U,
135 PIS_TIMER0_OUTPUT_3 = 0x127U,
136 PIS_TIMER0_INPUT_4 = 0x128U,
137 PIS_TIMER0_OUTPUT_4 = 0x129U,
138 PIS_TIMER1_UPDATA = 0x130U,
139 PIS_TIMER1_TRIG = 0x131U,
140 PIS_TIMER1_INPUT_1 = 0x132U,
141 PIS_TIMER1_OUTPUT_1 = 0x133U,
142 PIS_TIMER1_INPUT_2 = 0x134U,
143 PIS_TIMER1_OUTPUT_2 = 0x135U,
144 PIS_TIMER1_INPUT_3 = 0x136U,
145 PIS_TIMER1_OUTPUT_3 = 0x137U,
146 PIS_TIMER1_INPUT_4 = 0x138U,
147 PIS_TIMER1_OUTPUT_4 = 0x139U,
148 PIS_TIMER2_UPDATA = 0x140U,
149 PIS_TIMER2_TRIG = 0x141U,
150 PIS_TIMER2_INPUT_1 = 0x142U,
151 PIS_TIMER2_OUTPUT_1 = 0x143U,
152 PIS_TIMER2_INPUT_2 = 0x144U,
153 PIS_TIMER2_OUTPUT_2 = 0x145U,
154 PIS_TIMER2_INPUT_3 = 0x146U,
155 PIS_TIMER2_OUTPUT_3 = 0x147U,
156 PIS_TIMER2_INPUT_4 = 0x148U,
157 PIS_TIMER2_OUTPUT_4 = 0x149U,
158 PIS_TIMER3_UPDATA = 0x150U,
159 PIS_TIMER3_TRIG = 0x151U,
160 PIS_TIMER3_INPUT_1 = 0x152U,
161 PIS_TIMER3_OUTPUT_1 = 0x153U,
162 PIS_TIMER3_INPUT_2 = 0x154U,
163 PIS_TIMER3_OUTPUT_2 = 0x155U,
164 PIS_TIMER3_INPUT_3 = 0x156U,
165 PIS_TIMER3_OUTPUT_3 = 0x157U,
166 PIS_TIMER3_INPUT_4 = 0x158U,
167 PIS_TIMER3_OUTPUT_4 = 0x159U,
168 PIS_RTC_CLOCK = 0x160U,
169 PIS_RTC_ALARM = 0x161U,
170 PIS_LPTIMER0_SYN_UPDATA = 0x170U,
171 PIS_LPTIMER0_ASY_UPDATA = 0x171U,
172 PIS_LPUART0_ASY_RECV = 0x180U,
173 PIS_LPUART0_ASY_SEND = 0x181U,
174 PIS_LPUART0_SYN_RECV = 0x182U,
175 PIS_LPUART0_SYN_SEND = 0x183U,
176 PIS_DMA = 0x190U,
177 PIS_ADC1_INSERT = 0x1a0U,
178 PIS_ADC1_NORMAL = 0x1a1U,
179 PIS_ADC1_RESERVE = 0x1a2U,
180 } pis_src_t;
PIS_UART0_IRDAOUT
Definition: ald_pis.h:86
PIS_ADC0_INSERT
Definition: ald_pis.h:80
PIS_TIMER0_TRIG
Definition: ald_pis.h:129
PIS_LVD
Definition: ald_pis.h:83
PIS_TIMER0_INPUT_4
Definition: ald_pis.h:136
PIS_TIMER0_UPDATA
Definition: ald_pis.h:128
PIS_TIMER1_UPDATA
Definition: ald_pis.h:138
PIS_TIMER2_UPDATA
Definition: ald_pis.h:148
PIS_UART0_RESERVE0
Definition: ald_pis.h:84
PIS_SPI0_RECV
Definition: ald_pis.h:118
PIS_UART2_RESERVE1
Definition: ald_pis.h:99
PIS_UART4_TXOUT
Definition: ald_pis.h:114
PIS_GPIO_PIN14
Definition: ald_pis.h:74
PIS_GPIO_PIN3
Definition: ald_pis.h:63
PIS_I2C1_RECV
Definition: ald_pis.h:126
PIS_LPTIMER0_SYN_UPDATA
Definition: ald_pis.h:170
PIS_ADC1_RESERVE
Definition: ald_pis.h:179
PIS_UART3_IRDA
Definition: ald_pis.h:107
PIS_UART2_RTS
Definition: ald_pis.h:101
PIS_UART2_TXOUT
Definition: ald_pis.h:102
PIS_ADC1_NORMAL
Definition: ald_pis.h:178
PIS_UART5_SEND
Definition: ald_pis.h:116
PIS_GPIO_PIN1
Definition: ald_pis.h:61
PIS_UART3_SYN_SEND
Definition: ald_pis.h:110
PIS_SPI0_NE
Definition: ald_pis.h:120
PIS_TIMER3_INPUT_4
Definition: ald_pis.h:166
PIS_DAC0_CH1
Definition: ald_pis.h:79
PIS_UART1_SYN_SEND
Definition: ald_pis.h:96
PIS_LPTIMER0_ASY_UPDATA
Definition: ald_pis.h:171
PIS_UART4_RECV
Definition: ald_pis.h:112
PIS_TIMER1_OUTPUT_4
Definition: ald_pis.h:147
PIS_GPIO_PIN7
Definition: ald_pis.h:67
PIS_UART1_IRDA
Definition: ald_pis.h:93
PIS_SPI1_NE
Definition: ald_pis.h:123
PIS_UART2_SYN_SEND
Definition: ald_pis.h:103
PIS_TIMER2_OUTPUT_3
Definition: ald_pis.h:155
PIS_ADC1_INSERT
Definition: ald_pis.h:177
PIS_GPIO_PIN6
Definition: ald_pis.h:66
PIS_UART0_SYN_RECV
Definition: ald_pis.h:90
PIS_TIMER0_INPUT_2
Definition: ald_pis.h:132
PIS_LPUART0_ASY_RECV
Definition: ald_pis.h:172
PIS_TIMER0_OUTPUT_4
Definition: ald_pis.h:137
PIS_UART5_TXOUT
Definition: ald_pis.h:117
PIS_TIMER3_INPUT_2
Definition: ald_pis.h:162
PIS_UART1_RTS
Definition: ald_pis.h:94
PIS_UART1_TXOUT
Definition: ald_pis.h:95
PIS_UART2_SYN_RECV
Definition: ald_pis.h:104
PIS_SPI0_SEND
Definition: ald_pis.h:119
PIS_UART5_RECV
Definition: ald_pis.h:115
PIS_TIMER1_INPUT_1
Definition: ald_pis.h:140
PIS_UART0_RESERVE1
Definition: ald_pis.h:85
PIS_GPIO_PIN4
Definition: ald_pis.h:64
PIS_TIMER3_OUTPUT_3
Definition: ald_pis.h:165
PIS_TIMER0_OUTPUT_2
Definition: ald_pis.h:133
PIS_UART3_SYN_RECV
Definition: ald_pis.h:111
PIS_TIMER2_OUTPUT_1
Definition: ald_pis.h:151
PIS_TIMER2_OUTPUT_4
Definition: ald_pis.h:157
PIS_LPUART0_SYN_SEND
Definition: ald_pis.h:175
PIS_GPIO_PIN5
Definition: ald_pis.h:65
PIS_UART0_RTSOUT
Definition: ald_pis.h:87
PIS_ACMP_OUT1
Definition: ald_pis.h:77
PIS_TIMER2_INPUT_4
Definition: ald_pis.h:156
PIS_TIMER1_OUTPUT_2
Definition: ald_pis.h:143
PIS_GPIO_PIN11
Definition: ald_pis.h:71
PIS_TIMER3_INPUT_1
Definition: ald_pis.h:160
PIS_UART3_TXOUT
Definition: ald_pis.h:109
PIS_UART1_RESERVE1
Definition: ald_pis.h:92
PIS_DMA
Definition: ald_pis.h:176
PIS_GPIO_PIN15
Definition: ald_pis.h:75
PIS_TIMER2_INPUT_2
Definition: ald_pis.h:152
PIS_TIMER3_OUTPUT_4
Definition: ald_pis.h:167
PIS_TIMER0_OUTPUT_3
Definition: ald_pis.h:135
PIS_TIMER2_OUTPUT_2
Definition: ald_pis.h:153
PIS_TIMER0_OUTPUT_1
Definition: ald_pis.h:131
PIS_TIMER2_INPUT_1
Definition: ald_pis.h:150
PIS_TIMER2_INPUT_3
Definition: ald_pis.h:154
PIS_GPIO_PIN2
Definition: ald_pis.h:62
PIS_UART0_TXOUT
Definition: ald_pis.h:88
PIS_UART2_IRDA
Definition: ald_pis.h:100
PIS_ACMP_OUT0
Definition: ald_pis.h:76
PIS_TIMER1_OUTPUT_3
Definition: ald_pis.h:145
PIS_GPIO_PIN13
Definition: ald_pis.h:73
PIS_UART1_SYN_RECV
Definition: ald_pis.h:97
PIS_GPIO_PIN10
Definition: ald_pis.h:70
PIS_UART0_SYN_SEND
Definition: ald_pis.h:89
PIS_UART3_RESERVE1
Definition: ald_pis.h:106
PIS_UART1_RESERVE0
Definition: ald_pis.h:91
PIS_RTC_CLOCK
Definition: ald_pis.h:168
PIS_TIMER3_OUTPUT_1
Definition: ald_pis.h:161
PIS_I2C0_RECV
Definition: ald_pis.h:124
PIS_GPIO_PIN8
Definition: ald_pis.h:68
PIS_UART3_RTS
Definition: ald_pis.h:108
PIS_GPIO_PIN12
Definition: ald_pis.h:72
PIS_TIMER0_INPUT_1
Definition: ald_pis.h:130
PIS_I2C1_SEND
Definition: ald_pis.h:127
PIS_RTC_ALARM
Definition: ald_pis.h:169
PIS_TIMER1_INPUT_4
Definition: ald_pis.h:146
PIS_NON
Definition: ald_pis.h:59
PIS_TIMER1_OUTPUT_1
Definition: ald_pis.h:141
PIS_GPIO_PIN0
Definition: ald_pis.h:60
PIS_UART2_RESERVE0
Definition: ald_pis.h:98
PIS_UART3_RESERVE0
Definition: ald_pis.h:105
PIS_TIMER3_OUTPUT_2
Definition: ald_pis.h:163
PIS_TIMER1_INPUT_3
Definition: ald_pis.h:144
PIS_TIMER3_TRIG
Definition: ald_pis.h:159
PIS_TIMER2_TRIG
Definition: ald_pis.h:149
PIS_I2C0_SEND
Definition: ald_pis.h:125
PIS_GPIO_PIN9
Definition: ald_pis.h:69
PIS_LPUART0_SYN_RECV
Definition: ald_pis.h:174
PIS_ADC0_NORMAL
Definition: ald_pis.h:81
PIS_DAC0_CH0
Definition: ald_pis.h:78
PIS_ADC0_RESERVE
Definition: ald_pis.h:82
PIS_UART4_SEND
Definition: ald_pis.h:113
PIS_SPI1_RECV
Definition: ald_pis.h:121
pis_src_t
pis_src_t
Producer entry.
Definition: ald_pis.h:58
PIS_TIMER1_INPUT_2
Definition: ald_pis.h:142
PIS_TIMER1_TRIG
Definition: ald_pis.h:139
PIS_TIMER3_UPDATA
Definition: ald_pis.h:158
PIS_TIMER3_INPUT_3
Definition: ald_pis.h:164
PIS_LPUART0_ASY_SEND
Definition: ald_pis.h:173
PIS_TIMER0_INPUT_3
Definition: ald_pis.h:134
PIS_SPI1_SEND
Definition: ald_pis.h:122

◆ pis_state_t

enum pis_state_t

PIS state structures definition.

Enumerator
PIS_STATE_RESET | Peripheral is not initialized
PIS_STATE_READY | Peripheral Initialized and ready for use
PIS_STATE_BUSY | An internal process is ongoing
PIS_STATE_TIMEOUT | Timeout state
PIS_STATE_ERROR | Error

Definition at line 331 of file ald_pis.h.

331 {
332 PIS_STATE_RESET = 0x00U,
333 PIS_STATE_READY = 0x01U,
334 PIS_STATE_BUSY = 0x02U,
335 PIS_STATE_TIMEOUT = 0x03U,
336 PIS_STATE_ERROR = 0x04U,
337 } pis_state_t;
PIS_STATE_BUSY
Definition: ald_pis.h:334
PIS_STATE_RESET
Definition: ald_pis.h:332
PIS_STATE_ERROR
Definition: ald_pis.h:336
pis_state_t
pis_state_t
PIS state structures definition.
Definition: ald_pis.h:331
PIS_STATE_TIMEOUT
Definition: ald_pis.h:335
PIS_STATE_READY
Definition: ald_pis.h:333

◆ pis_syncsel_t

enum pis_syncsel_t

Sync select.

Enumerator
PIS_SYN_DIRECT | Direct
PIS_SYN_LEVEL_ASY_APB1 | Producer level signal and Consumer in APB1
PIS_SYN_LEVEL_ASY_APB2 | Producer level signal and Consumer in APB2
PIS_SYN_LEVEL_ASY_AHB | Producer level signal and Consumer in AHB
PIS_SYN_PULSE_ASY_APB1 | Producer Pulse signal and Consumer in APB1
PIS_SYN_PULSE_ASY_APB2 | Producer Pulse signal and Consumer in APB2
PIS_SYN_PULSE_ASY_AHB | Producer Pulse signal and Consumer in AHB

Definition at line 277 of file ald_pis.h.

277 {
278 PIS_SYN_DIRECT = 0U,
279 PIS_SYN_LEVEL_ASY_APB1 = 1U,
280 PIS_SYN_LEVEL_ASY_APB2 = 2U,
281 PIS_SYN_LEVEL_ASY_AHB = 3U,
282 PIS_SYN_PULSE_ASY_APB1 = 4U,
283 PIS_SYN_PULSE_ASY_APB2 = 5U,
284 PIS_SYN_PULSE_ASY_AHB = 6U,
285 } pis_syncsel_t;
PIS_SYN_PULSE_ASY_APB2
Definition: ald_pis.h:283
PIS_SYN_PULSE_ASY_AHB
Definition: ald_pis.h:284
pis_syncsel_t
pis_syncsel_t
Sync select.
Definition: ald_pis.h:277
PIS_SYN_LEVEL_ASY_AHB
Definition: ald_pis.h:281
PIS_SYN_LEVEL_ASY_APB1
Definition: ald_pis.h:279
PIS_SYN_DIRECT
Definition: ald_pis.h:278
PIS_SYN_PULSE_ASY_APB1
Definition: ald_pis.h:282
PIS_SYN_LEVEL_ASY_APB2
Definition: ald_pis.h:280

◆ pis_trig_t

enum pis_trig_t

Consumer entry.

Enumerator
PIS_CH12_TIMER0_ITR0 |
PIS_CH13_TIMER0_ITR1 | Tim0 internal input chan0
PIS_CH14_TIMER0_ITR2 | Tim0 internal input chan1
PIS_CH15_TIMER0_ITR3 | Tim0 internal input chan2
PIS_CH12_TIMER1_ITR0 | Tim0 internal input chan3
PIS_CH13_TIMER1_ITR1 | Tim1 internal input chan0
PIS_CH14_TIMER1_ITR2 | Tim1 internal input chan1
PIS_CH15_TIMER1_ITR3 | Tim1 internal input chan2
PIS_CH12_TIMER2_ITR0 | Tim1 internal input chan3
PIS_CH13_TIMER2_ITR1 | Tim2 internal input chan0
PIS_CH14_TIMER2_ITR2 | Tim2 internal input chan1
PIS_CH15_TIMER2_ITR3 | Tim2 internal input chan2
PIS_CH12_TIMER3_ITR0 | Tim2 internal input chan3
PIS_CH13_TIMER3_ITR1 | Tim3 internal input chan0
PIS_CH14_TIMER3_ITR2 | Tim3 internal input chan1
PIS_CH15_TIMER3_ITR3 | Tim3 internal input chan2
PIS_CH6_ADC0_NORMAL | Tim3 internal input chan3
PIS_CH7_ADC0_INSERT | ADC0 normal transform
PIS_CH0_ADC1_NORMAL | ADC0 insert transform
PIS_CH1_ADC1_INSERT | ADC1 normal transform
PIS_CH0_LPTIM0_EXT0 | ADC1 insert transform
PIS_CH1_LPTIM0_EXT1 | Lptim0 external trigger 0
PIS_CH2_LPTIM0_EXT2 | Lptim0 external trigger 1
PIS_CH3_LPTIM0_EXT3 | Lptim0 external trigger 2
PIS_CH4_LPTIM0_EXT4 | Lptim0 external trigger 3
PIS_CH5_LPTIM0_EXT5 | Lptim0 external trigger 4
PIS_CH6_LPTIM0_EXT6 | Lptim0 external trigger 5
PIS_CH7_LPTIM0_EXT7 | Lptim0 external trigger 6
PIS_CH7_DMA_REQUEST | Lptim0 external trigger 7
PIS_CH15_LPUART0_RXD | DMA request 7 Lpuart Rx data
PIS_CH14_UART5_RXD | Uart5 Rx data
PIS_CH13_UART4_RXD | Uart4 Rx data
PIS_CH12_UART3_RXD | Uart3 Rx data
PIS_CH11_UART2_RXD | Uart2 Rx data
PIS_CH10_UART1_RXD | Uart1 Rx data
PIS_CH9_UART0_RXD | Uart0 Rx data
PIS_CH8_TIMER3_CH4IN | Tim3 input chan4
PIS_CH8_TIMER2_CH4IN | Tim2 input chan4
PIS_CH8_SPI1_CLK | Spi1 clk
PIS_CH7_TIMER3_CH3IN | Tim3 input chan3
PIS_CH7_TIMER2_CH3IN | Tim2 input chan3
PIS_CH7_SPI1_RX | Spi1 rx
PIS_CH6_TIMER3_CH2IN | Tim3 input chan2
PIS_CH6_TIMER2_CH2IN | Tim2 input chan2
PIS_CH6_SPI0_CLK | SPI0 CLK
PIS_CH5_TIMER3_CH1IN | Tim3 input chan1
PIS_CH5_TIMER2_CH1IN | Tim2 input chan1
PIS_CH5_SPI0_RX | SPI0 RX
PIS_CH4_TIMER1_CH4IN | Tim1 input chan4
PIS_CH4_TIMER0_CH4IN | Tim0 input chan4
PIS_CH3_TIMER1_CH3IN | Tim1 input chan3
PIS_CH3_TIMER0_CH3IN | Tim0 input chan3
PIS_CH2_TIMER1_CH2IN | Tim1 input chan2
PIS_CH2_TIMER0_CH2IN | Tim0 input chan2
PIS_CH1_TIMER1_CH1IN | Tim1 input chan1
PIS_CH0_TIMER0_CH1IN | Tim0 input chan1
PIS_CH0_TIMER0_BRKIN | Tim0 break in
PIS_CH0_TIMER1_BRKIN | Tim1 break in
PIS_TRIG_RESERVE | Other Consumer

Definition at line 185 of file ald_pis.h.

185 {
186 PIS_CH12_TIMER0_ITR0 = 0x003CU,
187 PIS_CH13_TIMER0_ITR1 = 0x003DU,
188 PIS_CH14_TIMER0_ITR2 = 0x003EU,
189 PIS_CH15_TIMER0_ITR3 = 0x003FU,
190 PIS_CH12_TIMER1_ITR0 = 0x003CU,
191 PIS_CH13_TIMER1_ITR1 = 0x003DU,
192 PIS_CH14_TIMER1_ITR2 = 0x003EU,
193 PIS_CH15_TIMER1_ITR3 = 0x003FU,
194 PIS_CH12_TIMER2_ITR0 = 0x003CU,
195 PIS_CH13_TIMER2_ITR1 = 0x003DU,
196 PIS_CH14_TIMER2_ITR2 = 0x003EU,
197 PIS_CH15_TIMER2_ITR3 = 0x003FU,
198 PIS_CH12_TIMER3_ITR0 = 0x003CU,
199 PIS_CH13_TIMER3_ITR1 = 0x003DU,
200 PIS_CH14_TIMER3_ITR2 = 0x003EU,
201 PIS_CH15_TIMER3_ITR3 = 0x003FU,
202 PIS_CH6_ADC0_NORMAL = 0x0036U,
203 PIS_CH7_ADC0_INSERT = 0x0037U,
204 PIS_CH0_ADC1_NORMAL = 0x0030U,
205 PIS_CH1_ADC1_INSERT = 0x0031U,
206 PIS_CH0_LPTIM0_EXT0 = 0x0030U,
207 PIS_CH1_LPTIM0_EXT1 = 0x0031U,
208 PIS_CH2_LPTIM0_EXT2 = 0x0032U,
209 PIS_CH3_LPTIM0_EXT3 = 0x0033U,
210 PIS_CH4_LPTIM0_EXT4 = 0x0034U,
211 PIS_CH5_LPTIM0_EXT5 = 0x0035U,
212 PIS_CH6_LPTIM0_EXT6 = 0x0036U,
213 PIS_CH7_LPTIM0_EXT7 = 0x0037U,
214 PIS_CH7_DMA_REQUEST = 0x0037U,
215 PIS_CH15_LPUART0_RXD = 0x081FU,
216 PIS_CH14_UART5_RXD = 0x071EU,
217 PIS_CH13_UART4_RXD = 0x061DU,
218 PIS_CH12_UART3_RXD = 0x031CU,
219 PIS_CH11_UART2_RXD = 0x021BU,
220 PIS_CH10_UART1_RXD = 0x011AU,
221 PIS_CH9_UART0_RXD = 0x0019U,
222 PIS_CH8_TIMER3_CH4IN = 0x1B08U,
223 PIS_CH8_TIMER2_CH4IN = 0x1308U,
224 PIS_CH8_SPI1_CLK = 0x0F18U,
225 PIS_CH7_TIMER3_CH3IN = 0x1A07U,
226 PIS_CH7_TIMER2_CH3IN = 0x1207U,
227 PIS_CH7_SPI1_RX = 0x0E17U,
228 PIS_CH6_TIMER3_CH2IN = 0x1906U,
229 PIS_CH6_TIMER2_CH2IN = 0x1106U,
230 PIS_CH6_SPI0_CLK = 0x0D16U,
231 PIS_CH5_TIMER3_CH1IN = 0x1805U,
232 PIS_CH5_TIMER2_CH1IN = 0x1005U,
233 PIS_CH5_SPI0_RX = 0x0C15U,
234 PIS_CH4_TIMER1_CH4IN = 0x0B04U,
235 PIS_CH4_TIMER0_CH4IN = 0x0304U,
236 PIS_CH3_TIMER1_CH3IN = 0x0A03U,
237 PIS_CH3_TIMER0_CH3IN = 0x0203U,
238 PIS_CH2_TIMER1_CH2IN = 0x0902U,
239 PIS_CH2_TIMER0_CH2IN = 0x0102U,
240 PIS_CH1_TIMER1_CH1IN = 0x0801U,
241 PIS_CH0_TIMER0_CH1IN = 0x0000U,
242 PIS_CH0_TIMER0_BRKIN = 0x0400U,
243 PIS_CH0_TIMER1_BRKIN = 0x0C00U,
244 PIS_TRIG_RESERVE = 0xFFFFU,
245 } pis_trig_t;
PIS_CH5_TIMER2_CH1IN
Definition: ald_pis.h:232
PIS_CH13_UART4_RXD
Definition: ald_pis.h:217
PIS_CH13_TIMER3_ITR1
Definition: ald_pis.h:199
PIS_CH5_SPI0_RX
Definition: ald_pis.h:233
PIS_CH4_TIMER1_CH4IN
Definition: ald_pis.h:234
PIS_CH3_TIMER0_CH3IN
Definition: ald_pis.h:237
PIS_CH12_TIMER0_ITR0
Definition: ald_pis.h:186
PIS_CH7_LPTIM0_EXT7
Definition: ald_pis.h:213
PIS_CH7_TIMER3_CH3IN
Definition: ald_pis.h:225
PIS_CH13_TIMER0_ITR1
Definition: ald_pis.h:187
PIS_CH13_TIMER2_ITR1
Definition: ald_pis.h:195
PIS_CH6_LPTIM0_EXT6
Definition: ald_pis.h:212
PIS_CH7_SPI1_RX
Definition: ald_pis.h:227
PIS_CH7_DMA_REQUEST
Definition: ald_pis.h:214
PIS_CH0_LPTIM0_EXT0
Definition: ald_pis.h:206
PIS_CH5_TIMER3_CH1IN
Definition: ald_pis.h:231
PIS_TRIG_RESERVE
Definition: ald_pis.h:244
PIS_CH0_TIMER0_BRKIN
Definition: ald_pis.h:242
PIS_CH6_SPI0_CLK
Definition: ald_pis.h:230
PIS_CH8_TIMER2_CH4IN
Definition: ald_pis.h:223
PIS_CH5_LPTIM0_EXT5
Definition: ald_pis.h:211
PIS_CH8_TIMER3_CH4IN
Definition: ald_pis.h:222
PIS_CH2_TIMER0_CH2IN
Definition: ald_pis.h:239
PIS_CH4_LPTIM0_EXT4
Definition: ald_pis.h:210
PIS_CH9_UART0_RXD
Definition: ald_pis.h:221
PIS_CH6_TIMER2_CH2IN
Definition: ald_pis.h:229
PIS_CH6_TIMER3_CH2IN
Definition: ald_pis.h:228
PIS_CH2_TIMER1_CH2IN
Definition: ald_pis.h:238
PIS_CH6_ADC0_NORMAL
Definition: ald_pis.h:202
PIS_CH7_ADC0_INSERT
Definition: ald_pis.h:203
PIS_CH12_UART3_RXD
Definition: ald_pis.h:218
PIS_CH14_UART5_RXD
Definition: ald_pis.h:216
PIS_CH12_TIMER2_ITR0
Definition: ald_pis.h:194
PIS_CH11_UART2_RXD
Definition: ald_pis.h:219
PIS_CH14_TIMER3_ITR2
Definition: ald_pis.h:200
PIS_CH15_TIMER0_ITR3
Definition: ald_pis.h:189
PIS_CH12_TIMER3_ITR0
Definition: ald_pis.h:198
PIS_CH14_TIMER0_ITR2
Definition: ald_pis.h:188
PIS_CH14_TIMER2_ITR2
Definition: ald_pis.h:196
PIS_CH1_TIMER1_CH1IN
Definition: ald_pis.h:240
PIS_CH3_TIMER1_CH3IN
Definition: ald_pis.h:236
PIS_CH1_ADC1_INSERT
Definition: ald_pis.h:205
PIS_CH15_TIMER2_ITR3
Definition: ald_pis.h:197
PIS_CH15_LPUART0_RXD
Definition: ald_pis.h:215
PIS_CH0_TIMER1_BRKIN
Definition: ald_pis.h:243
PIS_CH8_SPI1_CLK
Definition: ald_pis.h:224
PIS_CH12_TIMER1_ITR0
Definition: ald_pis.h:190
PIS_CH1_LPTIM0_EXT1
Definition: ald_pis.h:207
PIS_CH2_LPTIM0_EXT2
Definition: ald_pis.h:208
PIS_CH7_TIMER2_CH3IN
Definition: ald_pis.h:226
PIS_CH15_TIMER1_ITR3
Definition: ald_pis.h:193
PIS_CH14_TIMER1_ITR2
Definition: ald_pis.h:192
PIS_CH3_LPTIM0_EXT3
Definition: ald_pis.h:209
PIS_CH0_ADC1_NORMAL
Definition: ald_pis.h:204
PIS_CH4_TIMER0_CH4IN
Definition: ald_pis.h:235
PIS_CH0_TIMER0_CH1IN
Definition: ald_pis.h:241
PIS_CH10_UART1_RXD
Definition: ald_pis.h:220
pis_trig_t
pis_trig_t
Consumer entry.
Definition: ald_pis.h:185
PIS_CH13_TIMER1_ITR1
Definition: ald_pis.h:191
PIS_CH15_TIMER3_ITR3
Definition: ald_pis.h:201


ALD User Manual: pis_init_t Struct Reference

Data Fields
pis_init_t Struct Reference
EASTSOFT ES32F3xx ALD » PIS » PIS Public Types

PIS init structure definition. More...

#include <ald_pis.h>

Data Fields

pis_src_t producer_src
pis_output_t producer_signal
pis_clock_t producer_clk
pis_edge_t producer_edge
pis_trig_t consumer_trig
pis_clock_t consumer_clk
pis_input_sel_t input_chan

Detailed Description

PIS init structure definition.

Definition at line 395 of file ald_pis.h.

Field Documentation

◆ consumer_clk

pis_clock_t consumer_clk

Consumer clock

Definition at line 401 of file ald_pis.h.

◆ consumer_trig

pis_trig_t consumer_trig

Consumer entry

Definition at line 400 of file ald_pis.h.

◆ input_chan

pis_input_sel_t input_chan

Consumer input channel

Definition at line 402 of file ald_pis.h.

◆ producer_clk

pis_clock_t producer_clk

Producer module clock

Definition at line 398 of file ald_pis.h.

◆ producer_edge

pis_edge_t producer_edge

Producer module pin output edge

Definition at line 399 of file ald_pis.h.

◆ producer_signal

pis_output_t producer_signal

Producer signal mode

Definition at line 397 of file ald_pis.h.

◆ producer_src

pis_src_t producer_src

Producer entry

Definition at line 396 of file ald_pis.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_pis.h


ALD User Manual: pis_modulate_config_t Struct Reference

Data Fields
pis_modulate_config_t Struct Reference
EASTSOFT ES32F3xx ALD » PIS » PIS Public Types

PIS modulate config structure definition. More...

#include <ald_pis.h>

Data Fields

pis_modu_targ_t target
pis_modu_level_t level
pis_modu_src_t src
pis_modu_channel_t channel

Detailed Description

PIS modulate config structure definition.

Definition at line 408 of file ald_pis.h.

Field Documentation

◆ channel

pis_modu_channel_t channel

Modulate channel

Definition at line 412 of file ald_pis.h.

◆ level

pis_modu_level_t level

Modulate level

Definition at line 410 of file ald_pis.h.

◆ src

pis_modu_src_t src

Modulate src

Definition at line 411 of file ald_pis.h.

◆ target

pis_modu_targ_t target

Modulate target

Definition at line 409 of file ald_pis.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_pis.h


ALD User Manual: pis_handle_s Struct Reference

Data Fields
pis_handle_s Struct Reference
EASTSOFT ES32F3xx ALD » PIS » PIS Public Types

PIS Handle Structure definition. More...

#include <ald_pis.h>

Collaboration diagram for pis_handle_s:
[legend]

Data Fields

PIS_TypeDef * | perh
pis_init_t init
pis_ch_t consumer_ch
pis_con_t consumer_con
uint8_t | consumer_pos
uint32_t | check_info
lock_state_t lock
pis_state_t state

Detailed Description

PIS Handle Structure definition.

Definition at line 418 of file ald_pis.h.

Field Documentation

◆ check_info

uint32_t check_info

When destroy a handle ,user need check whether is right that ready to destroy

Definition at line 424 of file ald_pis.h.

◆ consumer_ch

pis_ch_t consumer_ch

Indirect value, no care of it

Definition at line 421 of file ald_pis.h.

◆ consumer_con

pis_con_t consumer_con

Indirect value, no care of it

Definition at line 422 of file ald_pis.h.

◆ consumer_pos

uint8_t consumer_pos

Indirect value, no care of it

Definition at line 423 of file ald_pis.h.

◆ init

pis_init_t init

PIS required parameters

Definition at line 420 of file ald_pis.h.

◆ lock

lock_state_t lock

Locking object

Definition at line 425 of file ald_pis.h.

◆ perh

PIS_TypeDef* perh

Register base address

Definition at line 419 of file ald_pis.h.

◆ state

pis_state_t state

PIS operation state

Definition at line 426 of file ald_pis.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_pis.h


ALD User Manual: PIS Private Macros

Macros
PIS Private Macros
EASTSOFT ES32F3xx ALD » PIS
Collaboration diagram for PIS Private Macros:

Macros

#define | IS_PIS(x) (((x) == PIS))
#define | IS_PIS_SRC(x)
#define | IS_PIS_TRIG(x)
#define | IS_PIS_CLOCK(x)
#define | IS_PIS_SIGNAL_MODE(x)
#define | IS_PIS_EDGE(x)
#define | IS_PIS_OUTPUT(x)
#define | IS_PIS_OUPUT_CH(x)
#define | IS_PIS_MODU_TARGET(x)
#define | IS_PIS_MODU_LEVEL(x)
#define | IS_PIS_MODU_SRC(x)
#define | IS_PIS_MODU_CHANNEL(x)

Detailed Description

Macro Definition Documentation

◆ IS_PIS

#define IS_PIS ( x ) (((x) == PIS))

Definition at line 436 of file ald_pis.h.

◆ IS_PIS_CLOCK

#define IS_PIS_CLOCK ( x )
Value:
(((x) == PIS_CLK_PCLK1) || \
((x) == PIS_CLK_PCLK2) || \
((x) == PIS_CLK_SYS))
PIS_CLK_PCLK1
Definition: ald_pis.h:251
PIS_CLK_SYS
Definition: ald_pis.h:253
PIS_CLK_PCLK2
Definition: ald_pis.h:252

Definition at line 618 of file ald_pis.h.

◆ IS_PIS_EDGE

#define IS_PIS_EDGE ( x )
Value:
(((x) == PIS_EDGE_NONE) || \
((x) == PIS_EDGE_UP) || \
((x) == PIS_EDGE_DOWN) || \
((x) == PIS_EDGE_UP_DOWN))
PIS_EDGE_UP_DOWN
Definition: ald_pis.h:264
PIS_EDGE_DOWN
Definition: ald_pis.h:263
PIS_EDGE_UP
Definition: ald_pis.h:262
PIS_EDGE_NONE
Definition: ald_pis.h:261

Definition at line 623 of file ald_pis.h.

◆ IS_PIS_MODU_CHANNEL

#define IS_PIS_MODU_CHANNEL ( x )
Value:
(((x) == PIS_TIMER_CH1) || \
((x) == PIS_TIMER_CH2) || \
((x) == PIS_TIMER_CH3) || \
((x) == PIS_TIMER_CH4))
PIS_TIMER_CH2
Definition: ald_pis.h:378
PIS_TIMER_CH3
Definition: ald_pis.h:379
PIS_TIMER_CH4
Definition: ald_pis.h:380
PIS_TIMER_CH1
Definition: ald_pis.h:377

Definition at line 649 of file ald_pis.h.

◆ IS_PIS_MODU_LEVEL

#define IS_PIS_MODU_LEVEL ( x )
Value:
(((x) == PIS_LOW_LEVEL) || \
((x) == PIS_HIGH_LEVEL))
PIS_LOW_LEVEL
Definition: ald_pis.h:354
PIS_HIGH_LEVEL
Definition: ald_pis.h:355

Definition at line 638 of file ald_pis.h.

◆ IS_PIS_MODU_SRC

#define IS_PIS_MODU_SRC ( x )
Value:
(((x) == PIS_SRC_NONE) || \
((x) == PIS_SRC_TIMER0) || \
((x) == PIS_SRC_TIMER1) || \
((x) == PIS_SRC_TIMER2) || \
((x) == PIS_SRC_TIMER3) || \
((x) == PIS_SRC_TIMER6) || \
((x) == PIS_SRC_TIMER7) || \
((x) == PIS_SRC_LPTIM0) || \
((x) == PIS_SRC_BUZ))
PIS_SRC_BUZ
Definition: ald_pis.h:370
PIS_SRC_TIMER0
Definition: ald_pis.h:363
PIS_SRC_TIMER6
Definition: ald_pis.h:367
PIS_SRC_TIMER2
Definition: ald_pis.h:365
PIS_SRC_TIMER7
Definition: ald_pis.h:368
PIS_SRC_TIMER1
Definition: ald_pis.h:364
PIS_SRC_LPTIM0
Definition: ald_pis.h:369
PIS_SRC_NONE
Definition: ald_pis.h:362
PIS_SRC_TIMER3
Definition: ald_pis.h:366

Definition at line 640 of file ald_pis.h.

◆ IS_PIS_MODU_TARGET

#define IS_PIS_MODU_TARGET ( x )
Value:
(((x) == PIS_UART0_TX) || \
((x) == PIS_UART1_TX) || \
((x) == PIS_UART2_TX) || \
((x) == PIS_UART3_TX) || \
((x) == PIS_LPUART0_TX))
PIS_UART2_TX
Definition: ald_pis.h:345
PIS_UART1_TX
Definition: ald_pis.h:344
PIS_LPUART0_TX
Definition: ald_pis.h:347
PIS_UART3_TX
Definition: ald_pis.h:346
PIS_UART0_TX
Definition: ald_pis.h:343

Definition at line 633 of file ald_pis.h.

◆ IS_PIS_OUPUT_CH

#define IS_PIS_OUPUT_CH ( x )
Value:
(((x) == PIS_OUT_CH_0) || \
((x) == PIS_OUT_CH_1) || \
((x) == PIS_OUT_CH_2) || \
((x) == PIS_OUT_CH_3))
PIS_OUT_CH_0
Definition: ald_pis.h:313
PIS_OUT_CH_1
Definition: ald_pis.h:314
PIS_OUT_CH_2
Definition: ald_pis.h:315
PIS_OUT_CH_3
Definition: ald_pis.h:316

Definition at line 629 of file ald_pis.h.

◆ IS_PIS_OUTPUT

#define IS_PIS_OUTPUT ( x )
Value:
(((x) == PIS_OUT_LEVEL) || \
((x) == PIS_OUT_PULSE))
PIS_OUT_LEVEL
Definition: ald_pis.h:271
PIS_OUT_PULSE
Definition: ald_pis.h:272

Definition at line 627 of file ald_pis.h.

◆ IS_PIS_SIGNAL_MODE

#define IS_PIS_SIGNAL_MODE ( x )
Value:
(((x) == PIS_OUT_LEVEL) || \
((x) == PIS_OUT_PULSE))
PIS_OUT_LEVEL
Definition: ald_pis.h:271
PIS_OUT_PULSE
Definition: ald_pis.h:272

Definition at line 621 of file ald_pis.h.

◆ IS_PIS_SRC

#define IS_PIS_SRC ( x )

Definition at line 437 of file ald_pis.h.

◆ IS_PIS_TRIG

#define IS_PIS_TRIG ( x )

Definition at line 558 of file ald_pis.h.


ALD User Manual: PMU

Modules
PMU
EASTSOFT ES32F3xx ALD

PMU module driver. More...

Collaboration diagram for PMU:

Modules

PMU Private Functions
PMU Public Functions
PMU Public Macros
PMU Public Types
PMU Private Macros

Detailed Description

PMU module driver.


ALD User Manual: PMU Private Functions

Functions
PMU Private Functions
EASTSOFT ES32F3xx ALD » PMU
Collaboration diagram for PMU Private Functions:

Functions

void ald_lvd_irq_handler (void)
PMU module interrupt handler. More...

Detailed Description

Function Documentation

◆ ald_lvd_irq_handler()

void ald_lvd_irq_handler ( void )

PMU module interrupt handler.

Return values
None

Definition at line 40 of file ald_pmu.c.

41 {
42 SYSCFG_UNLOCK();
43 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
44 SYSCFG_LOCK();
45
46 return;
47 }
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39


ALD User Manual: PMU Public Functions

Modules
PMU Public Functions
EASTSOFT ES32F3xx ALD » PMU
Collaboration diagram for PMU Public Functions:

Modules

Low Power Mode
Low power mode select functions.
LVD Configure
LVD configure functions.

Detailed Description


ALD User Manual: Low Power Mode

Functions
Low Power Mode
EASTSOFT ES32F3xx ALD » PMU » PMU Public Functions

Low power mode select functions. More...

Collaboration diagram for Low Power Mode:

Functions

void | ald_pmu_stop1_enter (void)
Enter stop1 mode. More...
void | ald_pmu_stop2_enter (void)
Enter stop2 mode. More...
void | ald_pmu_standby_enter (bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
Enter standby mode. More...
void | ald_pmu_ldo_12_config (type_func_t state)
Enable/Disable LDO(1.2V) hold mode. It must be disabled in STOP1. More...
void | ald_pmu_ldo_18_config (pmu_ldo_18_mode_t mode)
Configure LDO(1.8V) mode. More...
flag_status_t | ald_pmu_get_status (pmu_status_t sr)
Get wakup status. More...
void | ald_pmu_clear_status (pmu_status_t sr)
Clear wakup status. More...
void | ald_pmu_perh_power_config (pmu_perh_power_t perh, type_func_t state)
Configure peripheral power. More...
__STATIC_INLINE__ void | ald_pmu_sleep ()
__STATIC_INLINE__ void | ald_pmu_sleep_deep ()

Detailed Description

Low power mode select functions.

==============================================================================
            ##### Low power mode select functions #####
==============================================================================
  [..]  This section provides functions allowing to:
    (+) Enter stop1 mode.
    (+) Enter stop2 mode.
    (+) Enter standby mode.
    (+) Get wakeup status.
    (+) Clear wakeup status.

Function Documentation

◆ ald_pmu_clear_status()

void ald_pmu_clear_status ( pmu_status_t sr )

Clear wakup status.

Parameters
sr Status bit.
Return values
None

Definition at line 239 of file ald_pmu.c.

240 {
241 assert_param(IS_PMU_STATUS(sr));
242 SYSCFG_UNLOCK();
243
244 if (sr == PMU_SR_WUF)
245 SET_BIT(PMU->CR0, PMU_CR0_CWUF_MSK);
246 else if (sr == PMU_SR_STANDBYF)
247 SET_BIT(PMU->CR0, PMU_CR0_CSTANDBYF_MSK);
248 else
249 ;/* do nothing */
250
251 SYSCFG_LOCK();
252 return;
253 }
PMU_SR_STANDBYF
Definition: ald_pmu.h:119
PMU_SR_WUF
Definition: ald_pmu.h:118
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
IS_PMU_STATUS
#define IS_PMU_STATUS(x)
Definition: ald_pmu.h:194
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39

◆ ald_pmu_get_status()

flag_status_t ald_pmu_get_status ( pmu_status_t sr )

Get wakup status.

Parameters
sr Status bit.
Return values
Status.

Definition at line 224 of file ald_pmu.c.

225 {
226 assert_param(IS_PMU_STATUS(sr));
227
228 if (READ_BIT(PMU->SR, sr))
229 return SET;
230
231 return RESET;
232 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
IS_PMU_STATUS
#define IS_PMU_STATUS(x)
Definition: ald_pmu.h:194
RESET
Definition: type.h:38
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69

◆ ald_pmu_ldo_12_config()

void ald_pmu_ldo_12_config ( type_func_t state )

Enable/Disable LDO(1.2V) hold mode. It must be disabled in STOP1.

Parameters
state Enable/Disable
Return values
None

Definition at line 157 of file ald_pmu.c.

158 {
159 assert_param(IS_FUNC_STATE(state));
160 SYSCFG_UNLOCK();
161
162 if (state)
163 SET_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK);
164 else
165 CLEAR_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK);
166
167 SYSCFG_LOCK();
168 return;
169 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_pmu_ldo_18_config()

void ald_pmu_ldo_18_config ( pmu_ldo_18_mode_t mode )

Configure LDO(1.8V) mode.

Parameters
mode Mode of the LDO(1.8V)
Return values
None

Definition at line 176 of file ald_pmu.c.

177 {
178 uint32_t cnt = 4000;
179
180 assert_param(IS_PMU_LDO18_MODE(mode));
181
182 SYSCFG_UNLOCK();
183 MODIFY_REG(PMU->CR1, PMU_CR1_LDO18MOD_MSK, mode << PMU_CR1_LDO18MOD_POSS);
184 SYSCFG_LOCK();
185
186 while ((!(PMU->CR1 & PMU_CR1_LDO18RDY_MSK)) && (cnt--));
187 return;
188 }
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
IS_PMU_LDO18_MODE
#define IS_PMU_LDO18_MODE(x)
Definition: ald_pmu.h:190
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39

◆ ald_pmu_perh_power_config()

void ald_pmu_perh_power_config | ( | pmu_perh_power_t | perh,
 |  | type_func_t | state
 | ) |  |

Configure peripheral power.

Parameters
perh | The peripheral
state | ENABLE/DISABLE
Return values
None

Definition at line 261 of file ald_pmu.c.

262 {
263 assert_param(IS_PMU_PERH_POWER(perh));
264 assert_param(IS_FUNC_STATE(state));
265
266 SYSCFG_UNLOCK();
267
268 if (state)
269 SET_BIT(PMU->PWRCR, perh);
270 else
271 CLEAR_BIT(PMU->PWRCR, perh);
272
273 SYSCFG_LOCK();
274 return;
275 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
IS_PMU_PERH_POWER
#define IS_PMU_PERH_POWER(x)
Definition: ald_pmu.h:222

◆ ald_pmu_sleep()

__STATIC_INLINE__ void ald_pmu_sleep ( )

Definition at line 244 of file ald_pmu.h.

245 {
246 __WFI();
247 }

◆ ald_pmu_sleep_deep()

__STATIC_INLINE__ void ald_pmu_sleep_deep ( )

Definition at line 249 of file ald_pmu.h.

250 {
251 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
252 __WFI();
253 }

◆ ald_pmu_standby_enter()

void ald_pmu_standby_enter | ( | bkpc_wakeup_port_t | port,
 |  | bkpc_wakeup_level_t | level
 | ) |  |

Enter standby mode.

Parameters
port | The port whick wake up the standby mode.
level | Wakeup level.
Return values
None

Definition at line 136 of file ald_pmu.c.

137 {
138 ald_bkpc_standby_wakeup_config(port, level);
139
140 SYSCFG_UNLOCK();
141 MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STANDBY << PMU_CR0_LPM_POSS);
142 SYSCFG_LOCK();
143
144 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
145 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
146 __WFI();
147 SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
148
149 return;
150 }
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
ald_bkpc_standby_wakeup_config
void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
Configure standby wakeup in backup field.
Definition: ald_bkpc.c:57
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
PMU_LP_STANDBY
Definition: ald_pmu.h:104
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39

◆ ald_pmu_stop1_enter()

void ald_pmu_stop1_enter ( void )

Enter stop1 mode.

Return values
None

Definition at line 78 of file ald_pmu.c.

79 {
80 int cnt = 4000;
81
82 SYSCFG_UNLOCK();
83
84 CLEAR_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK);
85 #ifdef ES32F336x /* MCU Series: ES32F336x */
86 SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK);
87 #endif
88 MODIFY_REG(PMU->CR1, PMU_CR1_LDO18MOD_MSK, PMU_LDO_18_HOLD << PMU_CR1_LDO18MOD_POSS);
89 MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STOP1 << PMU_CR0_LPM_POSS);
90 SYSCFG_LOCK();
91
92 while ((!(PMU->CR1 & PMU_CR1_LDO18RDY_MSK)) && (cnt--));
93
94 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
95 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
96 __WFI();
97 SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
98
99 return;
100 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
PMU_LDO_18_HOLD
Definition: ald_pmu.h:113
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
PMU_LP_STOP1
Definition: ald_pmu.h:102

◆ ald_pmu_stop2_enter()

void ald_pmu_stop2_enter ( void )

Enter stop2 mode.

Return values
None

Definition at line 106 of file ald_pmu.c.

107 {
108 int cnt = 4000;
109
110 SYSCFG_UNLOCK();
111
112 SET_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK);
113 #ifdef ES32F336x /* MCU Series: ES32F336x */
114 SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK);
115 #endif
116 MODIFY_REG(PMU->CR1, PMU_CR1_LDO18MOD_MSK, PMU_LDO_18_HOLD << PMU_CR1_LDO18MOD_POSS);
117 MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STOP2 << PMU_CR0_LPM_POSS);
118 SYSCFG_LOCK();
119
120 while ((!(PMU->CR1 & PMU_CR1_LDO18RDY_MSK)) && (cnt--));
121
122 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
123 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
124 __WFI();
125 SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
126
127 return;
128 }
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
PMU_LDO_18_HOLD
Definition: ald_pmu.h:113
PMU_LP_STOP2
Definition: ald_pmu.h:103
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39


ALD User Manual: LVD Configure

Functions
LVD Configure
EASTSOFT ES32F3xx ALD » PMU » PMU Public Functions

LVD configure functions. More...

Collaboration diagram for LVD Configure:

Functions

void | ald_pmu_lvd_config (pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state)
Configure lvd using specified parameters. More...
void | ald_lvd_irq_handler (void)
PMU module interrupt handler. More...

Detailed Description

LVD configure functions.

==============================================================================
            ##### LVD configure functions #####
==============================================================================
  [..]  This section provides functions allowing to:
    (+) Configure lvd parameters.

Function Documentation

◆ ald_lvd_irq_handler()

void ald_lvd_irq_handler ( void )

PMU module interrupt handler.

Return values
None

Definition at line 40 of file ald_pmu.c.

41 {
42 SYSCFG_UNLOCK();
43 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
44 SYSCFG_LOCK();
45
46 return;
47 }
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39

◆ ald_pmu_lvd_config()

void ald_pmu_lvd_config | ( | pmu_lvd_voltage_sel_t | sel,
 |  | pmu_lvd_trigger_mode_t | mode,
 |  | type_func_t | state
 | ) |  |

Configure lvd using specified parameters.

Parameters
sel | LVD threshold voltage.
mode | LVD trigger mode.
state | New state, ENABLE/DISABLE;
Return values
None

Definition at line 301 of file ald_pmu.c.

302 {
303 assert_param(IS_FUNC_STATE(state));
304 SYSCFG_UNLOCK();
305
306 if (state) {
307 assert_param(IS_PMU_LVD_VOL_SEL(sel));
308 assert_param(IS_PMU_LVD_TRIGGER_MODE(mode));
309
310 MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, sel << PMU_LVDCR_LVDS_POSS);
311 MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVIFS_MSK, mode << PMU_LVDCR_LVIFS_POSS);
312 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK);
313 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
314 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK);
315 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK);
316 }
317 else {
318 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
319 CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK);
320 CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK);
321 }
322
323 SYSCFG_LOCK();
324 return;
325 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
IS_PMU_LVD_VOL_SEL
#define IS_PMU_LVD_VOL_SEL(x)
Definition: ald_pmu.h:198
IS_PMU_LVD_TRIGGER_MODE
#define IS_PMU_LVD_TRIGGER_MODE(x)
Definition: ald_pmu.h:213
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73


ALD User Manual: PMU Public Macros

Macros
PMU Public Macros
EASTSOFT ES32F3xx ALD » PMU
Collaboration diagram for PMU Public Macros:

Macros

#define | PMU_LPSTOP_ENABLE()
#define | PMU_LPSTOP_DISABLE()
#define | PMU_FLASH_MODE_IDLE()
#define | PMU_FLASH_MODE_WAIT()
#define | PMU_MTSTOP_ENABLE()
#define | PMU_MTSTOP_DISABLE()
#define | PMU_VREF_ENABLE()
#define | PMU_VREF_DISABLE()
#define | PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS))

Detailed Description

Macro Definition Documentation

◆ PMU_FLASH_MODE_IDLE

#define PMU_FLASH_MODE_IDLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->CR0, PMU_CR0_SFPD_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 52 of file ald_pmu.h.

◆ PMU_FLASH_MODE_WAIT

#define PMU_FLASH_MODE_WAIT ( )
Value:
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->CR0, PMU_CR0_SFPD_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 58 of file ald_pmu.h.

◆ PMU_GET_LVD_STATUS

#define PMU_GET_LVD_STATUS ( ) (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS))

Definition at line 89 of file ald_pmu.h.

◆ PMU_LPSTOP_DISABLE

#define PMU_LPSTOP_DISABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 46 of file ald_pmu.h.

◆ PMU_LPSTOP_ENABLE

#define PMU_LPSTOP_ENABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 40 of file ald_pmu.h.

◆ PMU_MTSTOP_DISABLE

#define PMU_MTSTOP_DISABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 70 of file ald_pmu.h.

◆ PMU_MTSTOP_ENABLE

#define PMU_MTSTOP_ENABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 64 of file ald_pmu.h.

◆ PMU_VREF_DISABLE

#define PMU_VREF_DISABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
CLEAR_BIT(PMU->VREFCR, PMU_VREFCR_VREFEN_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 82 of file ald_pmu.h.

◆ PMU_VREF_ENABLE

#define PMU_VREF_ENABLE ( )
Value:
do { \
SYSCFG_UNLOCK(); \
SET_BIT(PMU->VREFCR, PMU_VREFCR_VREFEN_MSK); \
SYSCFG_LOCK(); \
} while (0)

Definition at line 76 of file ald_pmu.h.


ALD User Manual: PMU Public Types

Enumerations
PMU Public Types
EASTSOFT ES32F3xx ALD » PMU
Collaboration diagram for PMU Public Types:

Enumerations

enum | pmu_lp_mode_t { PMU_LP_STOP1 = 0x0U, PMU_LP_STOP2 = 0x1U, PMU_LP_STANDBY = 0x2U }
Low power mode. More...
enum | pmu_ldo_18_mode_t { PMU_LDO_18_DRV_HIGH = 0x0U, PMU_LDO_18_DRV_LOW = 0x1U, PMU_LDO_18_HOLD = 0x2U, PMU_LDO_18_OFF = 0x3U }
LDO_18 mode. More...
enum | pmu_status_t { PMU_SR_WUF = (1U << 0), PMU_SR_STANDBYF = (1U << 1), PMU_SR_USBRDY = (1U << 2), PMU_SR_RSTAT = (1U << 3) }
enum pmu_lvd_voltage_sel_t {
PMU_LVD_VOL_SEL_2_2 = 0x0U, PMU_LVD_VOL_SEL_2_4 = 0x1U, PMU_LVD_VOL_SEL_2_6 = 0x2U, PMU_LVD_VOL_SEL_2_8 = 0x3U,
PMU_LVD_VOL_SEL_3_0 = 0x4U, PMU_LVD_VOL_SEL_3_2 = 0x5U, PMU_LVD_VOL_SEL_3_4 = 0x6U, PMU_LVD_VOL_SEL_3_6 = 0x7U,
PMU_LVD_VOL_SEL_3_8 = 0x8U, PMU_LVD_VOL_SEL_4_0 = 0x9U, PMU_LVD_VOL_SEL_4_2 = 0xAU, PMU_LVD_VOL_SEL_4_4 = 0xBU,
PMU_LVD_VOL_SEL_4_6 = 0xCU, PMU_LVD_VOL_SEL_4_8 = 0xDU, PMU_LVD_VOL_SEL_EXT = 0xFU
}
LVD voltage select. More...
enum pmu_lvd_trigger_mode_t {
PMU_LVD_TRIGGER_RISING_EDGE = 0x0U, PMU_LVD_TRIGGER_FALLING_EDGE = 0x1U, PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2U, PMU_LVD_TRIGGER_LOW_LEVEL = 0x3U,
PMU_LVD_TRIGGER_RISING_FALLING = 0x4U
}
LVD trigger mode. More...
enum | pmu_ldo_lpmode_output_t { PMU_LDO_LPMODE_OUTPUT_0_9 = 0x0U, PMU_LDO_LPMODE_OUTPUT_1_0 = 0x1U, PMU_LDO_LPMODE_OUTPUT_1_1 = 0x2U, PMU_LDO_LPMODE_OUTPUT_1_2 = 0x3U }
LDO output voltage selest in low power mode. More...
enum pmu_perh_power_t {
PMU_POWER_SRAM0 = 0x1U, PMU_POWER_SRAM1 = 0x2U, PMU_POWER_SRAM2 = 0x4U, PMU_POWER_SRAM3 = 0x8U,
PMU_POWER_SRAM4 = 0x10U, PMU_POWER_SRAM5 = 0x20U, PMU_POWER_CAN = 0x100U, PMU_POWER_QSPI = 0x400U,
PMU_POWER_USB = 0x800U, PMU_POWER_ROM = 0x1000U
}

Detailed Description

Enumeration Type Documentation

◆ pmu_ldo_18_mode_t

enum pmu_ldo_18_mode_t

LDO_18 mode.

Enumerator
PMU_LDO_18_DRV_HIGH | High drive
PMU_LDO_18_DRV_LOW | Low drive
PMU_LDO_18_HOLD | Hold
PMU_LDO_18_OFF | Turn off

Definition at line 110 of file ald_pmu.h.

110 {
111 PMU_LDO_18_DRV_HIGH = 0x0U,
112 PMU_LDO_18_DRV_LOW = 0x1U,
113 PMU_LDO_18_HOLD = 0x2U,
114 PMU_LDO_18_OFF = 0x3U,
115 } pmu_ldo_18_mode_t;
PMU_LDO_18_OFF
Definition: ald_pmu.h:114
PMU_LDO_18_HOLD
Definition: ald_pmu.h:113
PMU_LDO_18_DRV_LOW
Definition: ald_pmu.h:112
pmu_ldo_18_mode_t
pmu_ldo_18_mode_t
LDO_18 mode.
Definition: ald_pmu.h:110
PMU_LDO_18_DRV_HIGH
Definition: ald_pmu.h:111

◆ pmu_ldo_lpmode_output_t

enum pmu_ldo_lpmode_output_t

LDO output voltage selest in low power mode.

Enumerator
PMU_LDO_LPMODE_OUTPUT_0_9 | 0.9V
PMU_LDO_LPMODE_OUTPUT_1_0 | 1.0V
PMU_LDO_LPMODE_OUTPUT_1_1 | 1.1V
PMU_LDO_LPMODE_OUTPUT_1_2 | 1.2V

Definition at line 159 of file ald_pmu.h.

159 {
160 PMU_LDO_LPMODE_OUTPUT_0_9 = 0x0U,
161 PMU_LDO_LPMODE_OUTPUT_1_0 = 0x1U,
162 PMU_LDO_LPMODE_OUTPUT_1_1 = 0x2U,
163 PMU_LDO_LPMODE_OUTPUT_1_2 = 0x3U,
164 } pmu_ldo_lpmode_output_t;
PMU_LDO_LPMODE_OUTPUT_1_0
Definition: ald_pmu.h:161
PMU_LDO_LPMODE_OUTPUT_1_2
Definition: ald_pmu.h:163
pmu_ldo_lpmode_output_t
pmu_ldo_lpmode_output_t
LDO output voltage selest in low power mode.
Definition: ald_pmu.h:159
PMU_LDO_LPMODE_OUTPUT_1_1
Definition: ald_pmu.h:162
PMU_LDO_LPMODE_OUTPUT_0_9
Definition: ald_pmu.h:160

◆ pmu_lp_mode_t

enum pmu_lp_mode_t

Low power mode.

Enumerator
PMU_LP_STOP1 | Stop1
PMU_LP_STOP2 | Stop2
PMU_LP_STANDBY | Standby

Definition at line 101 of file ald_pmu.h.

101 {
102 PMU_LP_STOP1 = 0x0U,
103 PMU_LP_STOP2 = 0x1U,
104 PMU_LP_STANDBY = 0x2U,
105 } pmu_lp_mode_t;
PMU_LP_STOP2
Definition: ald_pmu.h:103
pmu_lp_mode_t
pmu_lp_mode_t
Low power mode.
Definition: ald_pmu.h:101
PMU_LP_STANDBY
Definition: ald_pmu.h:104
PMU_LP_STOP1
Definition: ald_pmu.h:102

◆ pmu_lvd_trigger_mode_t

enum pmu_lvd_trigger_mode_t

LVD trigger mode.

Enumerator
PMU_LVD_TRIGGER_RISING_EDGE | Rising edge
PMU_LVD_TRIGGER_FALLING_EDGE | Falling edge
PMU_LVD_TRIGGER_HIGH_LEVEL | High level
PMU_LVD_TRIGGER_LOW_LEVEL | Low level
PMU_LVD_TRIGGER_RISING_FALLING | Rising and falling edge

Definition at line 148 of file ald_pmu.h.

148 {
149 PMU_LVD_TRIGGER_RISING_EDGE = 0x0U,
150 PMU_LVD_TRIGGER_FALLING_EDGE = 0x1U,
151 PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2U,
152 PMU_LVD_TRIGGER_LOW_LEVEL = 0x3U,
153 PMU_LVD_TRIGGER_RISING_FALLING = 0x4U,
154 } pmu_lvd_trigger_mode_t;
PMU_LVD_TRIGGER_HIGH_LEVEL
Definition: ald_pmu.h:151
PMU_LVD_TRIGGER_RISING_EDGE
Definition: ald_pmu.h:149
pmu_lvd_trigger_mode_t
pmu_lvd_trigger_mode_t
LVD trigger mode.
Definition: ald_pmu.h:148
PMU_LVD_TRIGGER_FALLING_EDGE
Definition: ald_pmu.h:150
PMU_LVD_TRIGGER_LOW_LEVEL
Definition: ald_pmu.h:152
PMU_LVD_TRIGGER_RISING_FALLING
Definition: ald_pmu.h:153

◆ pmu_lvd_voltage_sel_t

enum pmu_lvd_voltage_sel_t

LVD voltage select.

Enumerator
PMU_LVD_VOL_SEL_2_2 | 2.2V ~ 2.25V
PMU_LVD_VOL_SEL_2_4 | 2.4V ~ 2.45V
PMU_LVD_VOL_SEL_2_6 | 2.6V ~ 2.65V
PMU_LVD_VOL_SEL_2_8 | 2.8V ~ 2.85V
PMU_LVD_VOL_SEL_3_0 | 3.0V ~ 3.05V
PMU_LVD_VOL_SEL_3_2 | 3.2V ~ 3.25V
PMU_LVD_VOL_SEL_3_4 | 3.4V ~ 3.45V
PMU_LVD_VOL_SEL_3_6 | 3.6V ~ 3.65V
PMU_LVD_VOL_SEL_3_8 | 3.8V ~ 3.85V
PMU_LVD_VOL_SEL_4_0 | 4.0V ~ 4.05V
PMU_LVD_VOL_SEL_4_2 | 4.2V ~ 4.25V
PMU_LVD_VOL_SEL_4_4 | 4.4V ~ 4.45V
PMU_LVD_VOL_SEL_4_6 | 4.6V ~ 4.65V
PMU_LVD_VOL_SEL_4_8 | 4.8V ~ 4.85V
PMU_LVD_VOL_SEL_EXT | Select external input. It must be 1.2V

Definition at line 127 of file ald_pmu.h.

127 {
128 PMU_LVD_VOL_SEL_2_2 = 0x0U,
129 PMU_LVD_VOL_SEL_2_4 = 0x1U,
130 PMU_LVD_VOL_SEL_2_6 = 0x2U,
131 PMU_LVD_VOL_SEL_2_8 = 0x3U,
132 PMU_LVD_VOL_SEL_3_0 = 0x4U,
133 PMU_LVD_VOL_SEL_3_2 = 0x5U,
134 PMU_LVD_VOL_SEL_3_4 = 0x6U,
135 PMU_LVD_VOL_SEL_3_6 = 0x7U,
136 PMU_LVD_VOL_SEL_3_8 = 0x8U,
137 PMU_LVD_VOL_SEL_4_0 = 0x9U,
138 PMU_LVD_VOL_SEL_4_2 = 0xAU,
139 PMU_LVD_VOL_SEL_4_4 = 0xBU,
140 PMU_LVD_VOL_SEL_4_6 = 0xCU,
141 PMU_LVD_VOL_SEL_4_8 = 0xDU,
142 PMU_LVD_VOL_SEL_EXT = 0xFU,
143 } pmu_lvd_voltage_sel_t;
PMU_LVD_VOL_SEL_4_0
Definition: ald_pmu.h:137
PMU_LVD_VOL_SEL_3_8
Definition: ald_pmu.h:136
PMU_LVD_VOL_SEL_3_2
Definition: ald_pmu.h:133
PMU_LVD_VOL_SEL_2_2
Definition: ald_pmu.h:128
PMU_LVD_VOL_SEL_4_4
Definition: ald_pmu.h:139
PMU_LVD_VOL_SEL_2_8
Definition: ald_pmu.h:131
PMU_LVD_VOL_SEL_4_2
Definition: ald_pmu.h:138
PMU_LVD_VOL_SEL_3_0
Definition: ald_pmu.h:132
PMU_LVD_VOL_SEL_4_6
Definition: ald_pmu.h:140
pmu_lvd_voltage_sel_t
pmu_lvd_voltage_sel_t
LVD voltage select.
Definition: ald_pmu.h:127
PMU_LVD_VOL_SEL_2_6
Definition: ald_pmu.h:130
PMU_LVD_VOL_SEL_3_4
Definition: ald_pmu.h:134
PMU_LVD_VOL_SEL_EXT
Definition: ald_pmu.h:142
PMU_LVD_VOL_SEL_4_8
Definition: ald_pmu.h:141
PMU_LVD_VOL_SEL_3_6
Definition: ald_pmu.h:135
PMU_LVD_VOL_SEL_2_4
Definition: ald_pmu.h:129

◆ pmu_perh_power_t

enum pmu_perh_power_t
Enumerator
PMU_POWER_SRAM0 | SRAM0
PMU_POWER_SRAM1 | SRAM1
PMU_POWER_SRAM2 | SRAM2
PMU_POWER_SRAM3 | SRAM3
PMU_POWER_SRAM4 | SRAM4
PMU_POWER_SRAM5 | SRAM5
PMU_POWER_CAN | CAN
PMU_POWER_QSPI | QSPI
PMU_POWER_USB | USB
PMU_POWER_ROM | ROM

Definition at line 166 of file ald_pmu.h.

166 {
167 PMU_POWER_SRAM0 = 0x1U,
168 PMU_POWER_SRAM1 = 0x2U,
169 PMU_POWER_SRAM2 = 0x4U,
170 PMU_POWER_SRAM3 = 0x8U,
171 PMU_POWER_SRAM4 = 0x10U,
172 PMU_POWER_SRAM5 = 0x20U,
173 PMU_POWER_CAN = 0x100U,
174 PMU_POWER_QSPI = 0x400U,
175 PMU_POWER_USB = 0x800U,
176 PMU_POWER_ROM = 0x1000U,
177 } pmu_perh_power_t;
PMU_POWER_SRAM3
Definition: ald_pmu.h:170
PMU_POWER_SRAM5
Definition: ald_pmu.h:172
PMU_POWER_ROM
Definition: ald_pmu.h:176
PMU_POWER_SRAM4
Definition: ald_pmu.h:171
PMU_POWER_SRAM1
Definition: ald_pmu.h:168
pmu_perh_power_t
pmu_perh_power_t
Definition: ald_pmu.h:166
PMU_POWER_SRAM2
Definition: ald_pmu.h:169
PMU_POWER_CAN
Definition: ald_pmu.h:173
PMU_POWER_SRAM0
Definition: ald_pmu.h:167
PMU_POWER_QSPI
Definition: ald_pmu.h:174
PMU_POWER_USB
Definition: ald_pmu.h:175

◆ pmu_status_t

enum pmu_status_t
Enumerator
PMU_SR_WUF | WakeUp status
PMU_SR_STANDBYF | Standby status
PMU_SR_USBRDY | USB Readby status
PMU_SR_RSTAT | RUN/LPRUAN status

Definition at line 117 of file ald_pmu.h.

117 {
118 PMU_SR_WUF = (1U << 0),
119 PMU_SR_STANDBYF = (1U << 1),
120 PMU_SR_USBRDY = (1U << 2),
121 PMU_SR_RSTAT = (1U << 3),
122 } pmu_status_t;
PMU_SR_STANDBYF
Definition: ald_pmu.h:119
PMU_SR_WUF
Definition: ald_pmu.h:118
PMU_SR_RSTAT
Definition: ald_pmu.h:121
pmu_status_t
pmu_status_t
Definition: ald_pmu.h:117
PMU_SR_USBRDY
Definition: ald_pmu.h:120


ALD User Manual: PMU Private Macros

Macros
PMU Private Macros
EASTSOFT ES32F3xx ALD » PMU
Collaboration diagram for PMU Private Macros:

Macros

#define | IS_PMU_LP_MODE(x)
#define | IS_PMU_LDO18_MODE(x)
#define | IS_PMU_STATUS(x)
#define | IS_PMU_LVD_VOL_SEL(x)
#define | IS_PMU_LVD_TRIGGER_MODE(x)
#define | IS_PMU_LDO_LPMODE_OUTPUT(x)
#define | IS_PMU_PERH_POWER(x)

Detailed Description

Macro Definition Documentation

◆ IS_PMU_LDO18_MODE

#define IS_PMU_LDO18_MODE ( x )
Value:
(((x) == PMU_LDO_18_DRV_HIGH) || \
((x) == PMU_LDO_18_DRV_LOW) || \
((x) == PMU_LDO_18_HOLD) || \
((x) == PMU_LDO_18_OFF))
PMU_LDO_18_OFF
Definition: ald_pmu.h:114
PMU_LDO_18_HOLD
Definition: ald_pmu.h:113
PMU_LDO_18_DRV_LOW
Definition: ald_pmu.h:112
PMU_LDO_18_DRV_HIGH
Definition: ald_pmu.h:111

Definition at line 190 of file ald_pmu.h.

◆ IS_PMU_LDO_LPMODE_OUTPUT

#define IS_PMU_LDO_LPMODE_OUTPUT ( x )
Value:
(((x) == PMU_LDO_LPMODE_OUTPUT_0_9) || \
((x) == PMU_LDO_LPMODE_OUTPUT_1_0) || \
((x) == PMU_LDO_LPMODE_OUTPUT_1_1) || \
((x) == PMU_LDO_LPMODE_OUTPUT_1_2))
PMU_LDO_LPMODE_OUTPUT_1_0
Definition: ald_pmu.h:161
PMU_LDO_LPMODE_OUTPUT_1_2
Definition: ald_pmu.h:163
PMU_LDO_LPMODE_OUTPUT_1_1
Definition: ald_pmu.h:162
PMU_LDO_LPMODE_OUTPUT_0_9
Definition: ald_pmu.h:160

Definition at line 218 of file ald_pmu.h.

◆ IS_PMU_LP_MODE

#define IS_PMU_LP_MODE ( x )
Value:
(((x) == PMU_LP_STOP1) || \
((x) == PMU_LP_STOP2) || \
((x) == PMU_LP_STANDBY))
PMU_LP_STOP2
Definition: ald_pmu.h:103
PMU_LP_STANDBY
Definition: ald_pmu.h:104
PMU_LP_STOP1
Definition: ald_pmu.h:102

Definition at line 187 of file ald_pmu.h.

◆ IS_PMU_LVD_TRIGGER_MODE

#define IS_PMU_LVD_TRIGGER_MODE ( x )
Value:
(((x) == PMU_LVD_TRIGGER_RISING_EDGE) || \
((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \
((x) == PMU_LVD_TRIGGER_HIGH_LEVEL) || \
((x) == PMU_LVD_TRIGGER_LOW_LEVEL) || \
((x) == PMU_LVD_TRIGGER_RISING_FALLING))
PMU_LVD_TRIGGER_HIGH_LEVEL
Definition: ald_pmu.h:151
PMU_LVD_TRIGGER_RISING_EDGE
Definition: ald_pmu.h:149
PMU_LVD_TRIGGER_FALLING_EDGE
Definition: ald_pmu.h:150
PMU_LVD_TRIGGER_LOW_LEVEL
Definition: ald_pmu.h:152
PMU_LVD_TRIGGER_RISING_FALLING
Definition: ald_pmu.h:153

Definition at line 213 of file ald_pmu.h.

◆ IS_PMU_LVD_VOL_SEL

#define IS_PMU_LVD_VOL_SEL ( x )
Value:
(((x) == PMU_LVD_VOL_SEL_2_2) || \
((x) == PMU_LVD_VOL_SEL_2_4) || \
((x) == PMU_LVD_VOL_SEL_2_6) || \
((x) == PMU_LVD_VOL_SEL_2_8) || \
((x) == PMU_LVD_VOL_SEL_3_0) || \
((x) == PMU_LVD_VOL_SEL_3_2) || \
((x) == PMU_LVD_VOL_SEL_3_4) || \
((x) == PMU_LVD_VOL_SEL_3_6) || \
((x) == PMU_LVD_VOL_SEL_3_8) || \
((x) == PMU_LVD_VOL_SEL_4_0) || \
((x) == PMU_LVD_VOL_SEL_4_2) || \
((x) == PMU_LVD_VOL_SEL_4_4) || \
((x) == PMU_LVD_VOL_SEL_4_6) || \
((x) == PMU_LVD_VOL_SEL_4_8) || \
((x) == PMU_LVD_VOL_SEL_EXT))
PMU_LVD_VOL_SEL_4_0
Definition: ald_pmu.h:137
PMU_LVD_VOL_SEL_3_8
Definition: ald_pmu.h:136
PMU_LVD_VOL_SEL_3_2
Definition: ald_pmu.h:133
PMU_LVD_VOL_SEL_2_2
Definition: ald_pmu.h:128
PMU_LVD_VOL_SEL_4_4
Definition: ald_pmu.h:139
PMU_LVD_VOL_SEL_2_8
Definition: ald_pmu.h:131
PMU_LVD_VOL_SEL_4_2
Definition: ald_pmu.h:138
PMU_LVD_VOL_SEL_3_0
Definition: ald_pmu.h:132
PMU_LVD_VOL_SEL_4_6
Definition: ald_pmu.h:140
PMU_LVD_VOL_SEL_2_6
Definition: ald_pmu.h:130
PMU_LVD_VOL_SEL_3_4
Definition: ald_pmu.h:134
PMU_LVD_VOL_SEL_EXT
Definition: ald_pmu.h:142
PMU_LVD_VOL_SEL_4_8
Definition: ald_pmu.h:141
PMU_LVD_VOL_SEL_3_6
Definition: ald_pmu.h:135
PMU_LVD_VOL_SEL_2_4
Definition: ald_pmu.h:129

Definition at line 198 of file ald_pmu.h.

◆ IS_PMU_PERH_POWER

#define IS_PMU_PERH_POWER ( x )
Value:
(((x) == PMU_POWER_SRAM0) || \
((x) == PMU_POWER_SRAM1) || \
((x) == PMU_POWER_SRAM2) || \
((x) == PMU_POWER_SRAM3) || \
((x) == PMU_POWER_SRAM4) || \
((x) == PMU_POWER_SRAM5) || \
((x) == PMU_POWER_CAN) || \
((x) == PMU_POWER_QSPI) || \
((x) == PMU_POWER_USB) || \
((x) == PMU_POWER_ROM))
PMU_POWER_SRAM3
Definition: ald_pmu.h:170
PMU_POWER_SRAM5
Definition: ald_pmu.h:172
PMU_POWER_ROM
Definition: ald_pmu.h:176
PMU_POWER_SRAM4
Definition: ald_pmu.h:171
PMU_POWER_SRAM1
Definition: ald_pmu.h:168
PMU_POWER_SRAM2
Definition: ald_pmu.h:169
PMU_POWER_CAN
Definition: ald_pmu.h:173
PMU_POWER_SRAM0
Definition: ald_pmu.h:167
PMU_POWER_QSPI
Definition: ald_pmu.h:174
PMU_POWER_USB
Definition: ald_pmu.h:175

Definition at line 222 of file ald_pmu.h.

◆ IS_PMU_STATUS

#define IS_PMU_STATUS ( x )
Value:
(((x) == PMU_SR_WUF) || \
((x) == PMU_SR_STANDBYF) || \
((x) == PMU_SR_USBRDY) || \
((x) == PMU_SR_RSTAT))
PMU_SR_STANDBYF
Definition: ald_pmu.h:119
PMU_SR_WUF
Definition: ald_pmu.h:118
PMU_SR_RSTAT
Definition: ald_pmu.h:121
PMU_SR_USBRDY
Definition: ald_pmu.h:120

Definition at line 194 of file ald_pmu.h.


ALD User Manual: QSPI

Modules
QSPI
EASTSOFT ES32F3xx ALD

QSPI module driver. More...

Collaboration diagram for QSPI:

Modules

QSPI Private Functions
QSPI Private functions.
QSPI Public Functions
QSPI Public Functions.
QSPI Public Types
QSPI Private Macros
QSPI Public Macros

Detailed Description

QSPI module driver.


ALD User Manual: QSPI Private Functions

Functions
QSPI Private Functions
EASTSOFT ES32F3xx ALD » QSPI

QSPI Private functions. More...

Collaboration diagram for QSPI Private Functions:

Functions

static ald_status_t | qspi_wait_for_idle (qspi_handle_t *hperh, uint32_t tickstart, uint32_t timeout)
Wait for a flag state until timeout. More...
static flag_status_t | qspi_indrd_get_status (qspi_handle_t *hperh, qspi_indrd_flag_t status)
Get indirect read status. More...

Detailed Description

QSPI Private functions.

Function Documentation

◆ qspi_indrd_get_status()

static flag_status_t qspi_indrd_get_status | ( | qspi_handle_t * | hperh,
 |  | qspi_indrd_flag_t | status
 | ) |  |
static

Get indirect read status.

Parameters
hperh | Pointer to a qspi_handle_t structure.
status | Indirect status.
Return values
Status,see ald_status_t.

Definition at line 62 of file ald_qspi.c.

63 {
64 assert_param(IS_QSPI_ALL(hperh->perh));
65 assert_param(IS_QSPI_INDIRECT_READ_STATUS(status));
66
67 if (hperh->perh->IRTR & status)
68 return SET;
69
70 return RESET;
71 }
IS_QSPI_ALL
#define IS_QSPI_ALL(x)
Definition: ald_qspi.h:380
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
IS_QSPI_INDIRECT_READ_STATUS
#define IS_QSPI_INDIRECT_READ_STATUS(x)
Definition: ald_qspi.h:369
RESET
Definition: type.h:38
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257

◆ qspi_wait_for_idle()

static ald_status_t qspi_wait_for_idle | ( | qspi_handle_t * | hperh,
 |  | uint32_t | tickstart,
 |  | uint32_t | timeout
 | ) |  |
static

Wait for a flag state until timeout.

Parameters
hperh | QSPI handle
timeout | Duration of the time out
tickstart | tick start value
Return values
Status,see ald_status_t.

Definition at line 42 of file ald_qspi.c.

43 {
44 /* Wait until flag is in expected state */
45 while (READ_BIT(hperh->perh->CR, QSPI_CR_IDLES_MSK) != QSPI_CR_IDLES) {
46 /* Check for the Timeout */
47 if (timeout != ALD_MAX_DELAY) {
48 if ((timeout == 0U) || ((ald_get_tick() - tickstart) > timeout)) {
49 return ERROR;
50 }
51 }
52 }
53 return OK;
54 }
OK
Definition: utils.h:55
ALD_MAX_DELAY
#define ALD_MAX_DELAY
Definition: utils.h:88
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257
ERROR
Definition: utils.h:56


ALD User Manual: QSPI Public Functions

Modules
QSPI Public Functions
EASTSOFT ES32F3xx ALD » QSPI

QSPI Public Functions. More...

Collaboration diagram for QSPI Public Functions:

Modules

Basic execution functions
QSPI basic execution functions.
Indirect and stig access execution functions
QSPI indirect and stig access execution functions.
Status functions
QSPI status functions.

Detailed Description

QSPI Public Functions.


ALD User Manual: Basic execution functions

Functions
Basic execution functions
EASTSOFT ES32F3xx ALD » QSPI » QSPI Public Functions

QSPI basic execution functions. More...

Collaboration diagram for Basic execution functions:

Functions

void | ald_qspi_init (qspi_handle_t *hperh)
Initializes the QSPI basic parameters. More...
uint32_t | ald_qspi_dac_rd (uint32_t addr)
DAC read. More...
void | ald_qspi_dac_wr (uint32_t addr, uint32_t dat)
DAC write . More...
ald_status_t | ald_qspi_read_config (qspi_handle_t *hperh, const qspi_read_cfg_t *rdcfg)
Configure Read Operations. More...
ald_status_t | ald_qspi_write_config (qspi_handle_t *hperh, const qspi_write_cfg_t *wrcfg)
Configure Write Operations. More...
ald_status_t | ald_qspi_device_delay_config (qspi_handle_t *hperh, qspi_dly_cfg_t *dlycfg)
QSPI Device Delay Configuration. More...
ald_status_t | ald_qspi_read_data_capture_config (qspi_handle_t *hperh, qspi_data_capture_cfg_t *dtcptcfg)
QSPI Read Data Capture Configuration. More...
ald_status_t | ald_qspi_device_size_config (qspi_handle_t *hperh, qspi_device_size_t *devcfg)
QSPI Flash memory Configuration. More...
ald_status_t | qspi_dac_config (qspi_handle_t *hperh, qspi_dac_cfg_t *dcfg)
Initializes the QSPI direct access according to the specified parameters in the associated handle. More...

Detailed Description

QSPI basic execution functions.

Function Documentation

◆ ald_qspi_dac_rd()

uint32_t ald_qspi_dac_rd ( uint32_t addr )

DAC read.

Parameters
addr address.
Return values
value

Definition at line 111 of file ald_qspi.c.

112 {
113 return ((*(volatile uint32_t *)(addr)));
114 }

◆ ald_qspi_dac_wr()

void ald_qspi_dac_wr | ( | uint32_t | addr,
 |  | uint32_t | dat
 | ) |  |

DAC write .

Parameters
addr | address.
dat | data.
Return values
None

Definition at line 122 of file ald_qspi.c.

123 {
124 (*(volatile uint32_t *)(addr)) = dat;
125 }

◆ ald_qspi_device_delay_config()

ald_status_t ald_qspi_device_delay_config | ( | qspi_handle_t * | hperh,
 |  | qspi_dly_cfg_t * | dlycfg
 | ) |  |

QSPI Device Delay Configuration.

Parameters
hperh | Pointer to the QSPI qspi_handle_t structure.
dlycfg | Device delay configuration structure.
Return values
Status,see ald_status_t.

Definition at line 205 of file ald_qspi.c.

206 {
207 ald_status_t status = ERROR;
208 uint32_t tickstart = ald_get_tick();
209
210 assert_param(IS_QSPI_ALL(hperh->perh));
211 assert_param(IS_QSPI_DEVICE_DELAY_CCSOT(dlycfg->ccsot));
212 assert_param(IS_QSPI_DEVICE_DELAY_CSEOT(dlycfg->cseot));
213 assert_param(IS_QSPI_DEVICE_DELAY_CSDADS(dlycfg->csdads));
214 assert_param(IS_QSPI_DEVICE_DELAY_CSDA(dlycfg->csda));
215
216 status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE);
217
218 if (status != OK)
219 return status;
220
221 MODIFY_REG(hperh->perh->DDLR, QSPI_DDLR_CSSOT_MSK | QSPI_DDLR_CSEOT_MSK | QSPI_DDLR_CSDADS_MSK | QSPI_DDLR_CSDA_MSK, \
222 dlycfg->ccsot | (dlycfg->cseot << 8) | (dlycfg->csdads << 16) | (dlycfg->csda << 24));
223 return status;
224 }
IS_QSPI_ALL
#define IS_QSPI_ALL(x)
Definition: ald_qspi.h:380
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
qspi_dly_cfg_t::ccsot
uint32_t ccsot
Definition: ald_qspi.h:276
qspi_dly_cfg_t::cseot
uint32_t cseot
Definition: ald_qspi.h:277
IS_QSPI_DEVICE_DELAY_CSDADS
#define IS_QSPI_DEVICE_DELAY_CSDADS(x)
Definition: ald_qspi.h:373
qspi_wait_for_idle
static ald_status_t qspi_wait_for_idle(qspi_handle_t *hperh, uint32_t tickstart, uint32_t timeout)
Wait for a flag state until timeout.
Definition: ald_qspi.c:42
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
IS_QSPI_DEVICE_DELAY_CSDA
#define IS_QSPI_DEVICE_DELAY_CSDA(x)
Definition: ald_qspi.h:374
QSPI_TIMEOUT_DEFAULT_VALUE
#define QSPI_TIMEOUT_DEFAULT_VALUE
Definition: ald_qspi.h:456
IS_QSPI_DEVICE_DELAY_CCSOT
#define IS_QSPI_DEVICE_DELAY_CCSOT(x)
Definition: ald_qspi.h:371
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
qspi_dly_cfg_t::csdads
uint32_t csdads
Definition: ald_qspi.h:278
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
IS_QSPI_DEVICE_DELAY_CSEOT
#define IS_QSPI_DEVICE_DELAY_CSEOT(x)
Definition: ald_qspi.h:372
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257
ERROR
Definition: utils.h:56
qspi_dly_cfg_t::csda
uint32_t csda
Definition: ald_qspi.h:279

◆ ald_qspi_device_size_config()

ald_status_t ald_qspi_device_size_config | ( | qspi_handle_t * | hperh,
 |  | qspi_device_size_t * | devcfg
 | ) |  |

QSPI Flash memory Configuration.

Parameters
hperh | Pointer to the QSPI qspi_handle_t structure.
devcfg | flash parameter configuration structure.
Return values
Status,see ald_status_t.

Definition at line 258 of file ald_qspi.c.

259 {
260 ald_status_t status = ERROR;
261 uint32_t tickstart = ald_get_tick();
262
263 assert_param(IS_QSPI_ADDR_SIZE(devcfg->addr));
264 assert_param(IS_QSPI_PAGE_SIZE(devcfg->page));
265 assert_param(IS_QSPI_BLOCK_SIZE(devcfg->blk));
266 assert_param(IS_QSPI_NSS_SIZE(devcfg->cs0));
267 assert_param(IS_QSPI_NSS_SIZE(devcfg->cs1));
268 assert_param(IS_QSPI_NSS_SIZE(devcfg->cs2));
269 assert_param(IS_QSPI_NSS_SIZE(devcfg->cs3));
270
271 status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE);
272
273 if (status != OK)
274 return status;
275
276 MODIFY_REG(hperh->perh->DSCR, QSPI_DSCR_ADSIZE_MSK | QSPI_DSCR_PASIZE_MSK | QSPI_DSCR_BKSIZE_MSK | QSPI_DSCR_CS0SIZE_MSK | \
277 QSPI_DSCR_CS1SIZE_MSK | QSPI_DSCR_CS2SIZE_MSK | QSPI_DSCR_CS3SIZE_MSK, \
278 (devcfg->addr << QSPI_DSCR_ADSIZE_POSS) | \
279 (devcfg->page << QSPI_DSCR_PASIZE_POSS) | \
280 (devcfg->blk << QSPI_DSCR_BKSIZE_POSS) | \
281 (devcfg->cs0 << QSPI_DSCR_CS0SIZE_POSS) | \
282 (devcfg->cs1 << QSPI_DSCR_CS1SIZE_POSS) | \
283 (devcfg->cs2 << QSPI_DSCR_CS2SIZE_POSS) | \
284 (devcfg->cs3 << QSPI_DSCR_CS3SIZE_POSS));
285 return OK;
286 }
OK
Definition: utils.h:55
qspi_device_size_t::cs2
qspi_nss_size_t cs2
Definition: ald_qspi.h:134
assert_param
#define assert_param(x)
Definition: type.h:88
qspi_device_size_t::cs1
qspi_nss_size_t cs1
Definition: ald_qspi.h:133
qspi_device_size_t::cs0
qspi_nss_size_t cs0
Definition: ald_qspi.h:132
qspi_device_size_t::cs3
qspi_nss_size_t cs3
Definition: ald_qspi.h:135
qspi_device_size_t::page
uint16_t page
Definition: ald_qspi.h:130
qspi_device_size_t::blk
uint16_t blk
Definition: ald_qspi.h:131
IS_QSPI_NSS_SIZE
#define IS_QSPI_NSS_SIZE(x)
Definition: ald_qspi.h:386
qspi_wait_for_idle
static ald_status_t qspi_wait_for_idle(qspi_handle_t *hperh, uint32_t tickstart, uint32_t timeout)
Wait for a flag state until timeout.
Definition: ald_qspi.c:42
IS_QSPI_ADDR_SIZE
#define IS_QSPI_ADDR_SIZE(x)
Definition: ald_qspi.h:383
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
QSPI_TIMEOUT_DEFAULT_VALUE
#define QSPI_TIMEOUT_DEFAULT_VALUE
Definition: ald_qspi.h:456
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257
IS_QSPI_PAGE_SIZE
#define IS_QSPI_PAGE_SIZE(x)
Definition: ald_qspi.h:384
ERROR
Definition: utils.h:56
qspi_device_size_t::addr
uint8_t addr
Definition: ald_qspi.h:129
IS_QSPI_BLOCK_SIZE
#define IS_QSPI_BLOCK_SIZE(x)
Definition: ald_qspi.h:385

◆ ald_qspi_init()

void ald_qspi_init ( qspi_handle_t * hperh )

Initializes the QSPI basic parameters.

Parameters
hperh Pointer to the QSPI qspi_handle_t structure.
Return values
None.

Definition at line 90 of file ald_qspi.c.

91 {
92 assert_param(IS_QSPI_CLOCK_PRESCALER(hperh->init.clkdiv));
93 assert_param(IS_QSPI_CLOCK_PHASE(hperh->init.chpa));
94 assert_param(IS_QSPI_CLOCK_POLARITY(hperh->init.cpol));
95
96 MODIFY_REG(hperh->perh->CR, QSPI_CR_BAUD_MSK | QSPI_CR_CPOL_MSK | QSPI_CR_CPHA_MSK | \
97 QSPI_CR_PSL_MSK | QSPI_CR_SWPP_MSK , (hperh->init.clkdiv << QSPI_CR_BAUD_POSS) | \
98 (hperh->init.cpol << QSPI_CR_CPOL_POS) | \
99 (hperh->init.chpa << QSPI_CR_CPHA_POS) | \
100 (hperh->init.chipsel << QSPI_CR_PSL_POSS) | \
101 (hperh->init.wrppin << QSPI_CR_SWPP_POS));
102
103 return;
104 }
IS_QSPI_CLOCK_POLARITY
#define IS_QSPI_CLOCK_POLARITY(x)
Definition: ald_qspi.h:415
IS_QSPI_CLOCK_PHASE
#define IS_QSPI_CLOCK_PHASE(x)
Definition: ald_qspi.h:413
qspi_init_t::chpa
qspi_cpha_t chpa
Definition: ald_qspi.h:180
assert_param
#define assert_param(x)
Definition: type.h:88
IS_QSPI_CLOCK_PRESCALER
#define IS_QSPI_CLOCK_PRESCALER(x)
Definition: ald_qspi.h:397
qspi_handle_t::init
qspi_init_t init
Definition: ald_qspi.h:258
qspi_init_t::wrppin
type_func_t wrppin
Definition: ald_qspi.h:176
qspi_init_t::chipsel
qspi_nss_t chipsel
Definition: ald_qspi.h:178
qspi_init_t::clkdiv
qspi_clk_div_t clkdiv
Definition: ald_qspi.h:175
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257
qspi_init_t::cpol
qspi_cpol_t cpol
Definition: ald_qspi.h:179

◆ ald_qspi_read_config()

ald_status_t ald_qspi_read_config | ( | qspi_handle_t * | hperh,
 |  | const qspi_read_cfg_t * | rdcfg
 | ) |  |

Configure Read Operations.

Parameters
hperh | Pointer to the QSPI qspi_handle_t structure.
rdcfg | Pointer to configuration structure for QSPI read operations.
Return values
Status,see ald_status_t.

Definition at line 133 of file ald_qspi.c.

134 {
135 ald_status_t status = ERROR;
136 uint32_t tickstart = ald_get_tick();
137
138 assert_param(IS_QSPI_RD_OPCODE(rdcfg->rdcde));
139 assert_param(IS_QSPI_DCYLES(rdcfg->dcyles));
140 assert_param(IS_QSPI_XFER_TYPE(rdcfg->datxfer));
141 assert_param(IS_QSPI_XFER_TYPE(rdcfg->addxfer));
142 assert_param(IS_QSPI_XFER_TYPE(rdcfg->instxfer));
143
144 status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE);
145
146 if (status != OK)
147 return status;
148
149 MODIFY_REG(hperh->perh->DRIR, QSPI_DRIR_RINST_MSK | QSPI_DRIR_MBEN_MSK | \
150 QSPI_DRIR_DCYC_MSK | QSPI_DRIR_ADMODE_MSK | \
151 QSPI_DRIR_DMODE_MSK | QSPI_DRIR_IMODE_MSK | \
152 QSPI_DRIR_DDRM_MSK, \
153 (rdcfg->rdcde | (rdcfg->dcyles << 24) | \
154 (rdcfg->addxfer << 12) | (rdcfg->instxfer << 8) | \
155 (rdcfg->ddrbit << QSPI_DRIR_DDRM_POS) | (rdcfg->modebit << QSPI_DRIR_MBEN_POS)) | \
156 (rdcfg->datxfer << QSPI_DRIR_DMODE_POSS));
157
158 if (rdcfg->modebit)
159 MODIFY_REG(hperh->perh->MBR, QSPI_MBR_MODEB_MSK, rdcfg->mbitval);
160
161 return status;
162 }
qspi_read_cfg_t::datxfer
qspi_xfer_t datxfer
Definition: ald_qspi.h:201
OK
Definition: utils.h:55
qspi_read_cfg_t::mbitval
uint8_t mbitval
Definition: ald_qspi.h:197
assert_param
#define assert_param(x)
Definition: type.h:88
qspi_read_cfg_t::dcyles
uint8_t dcyles
Definition: ald_qspi.h:196
qspi_read_cfg_t::addxfer
qspi_xfer_t addxfer
Definition: ald_qspi.h:200
IS_QSPI_RD_OPCODE
#define IS_QSPI_RD_OPCODE(x)
Definition: ald_qspi.h:395
qspi_read_cfg_t::instxfer
qspi_xfer_t instxfer
Definition: ald_qspi.h:202
qspi_wait_for_idle
static ald_status_t qspi_wait_for_idle(qspi_handle_t *hperh, uint32_t tickstart, uint32_t timeout)
Wait for a flag state until timeout.
Definition: ald_qspi.c:42
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
qspi_read_cfg_t::rdcde
uint8_t rdcde
Definition: ald_qspi.h:195
QSPI_TIMEOUT_DEFAULT_VALUE
#define QSPI_TIMEOUT_DEFAULT_VALUE
Definition: ald_qspi.h:456
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257
IS_QSPI_XFER_TYPE
#define IS_QSPI_XFER_TYPE(x)
Definition: ald_qspi.h:388
ERROR
Definition: utils.h:56
qspi_read_cfg_t::ddrbit
type_func_t ddrbit
Definition: ald_qspi.h:198
qspi_read_cfg_t::modebit
type_func_t modebit
Definition: ald_qspi.h:199
IS_QSPI_DCYLES
#define IS_QSPI_DCYLES(x)
Definition: ald_qspi.h:381

◆ ald_qspi_read_data_capture_config()

ald_status_t ald_qspi_read_data_capture_config | ( | qspi_handle_t * | hperh,
 |  | qspi_data_capture_cfg_t * | dtcptcfg
 | ) |  |

QSPI Read Data Capture Configuration.

Parameters
hperh | Pointer to the QSPI qspi_handle_t structure.
dtcptcfg | Data capture configuration structure.
Return values
Status,see ald_status_t.

Definition at line 232 of file ald_qspi.c.

233 {
234 ald_status_t status = ERROR;
235 uint32_t tickstart = ald_get_tick();
236
237 assert_param(IS_QSPI_ALL(hperh->perh));
238 assert_param(IS_QSPI_READ_DATA_CAPTURE_DELAY_READ(dtcptcfg->dlydcl));
239 assert_param(IS_QSPI_READ_DATA_SAMPLE_EDGE(dtcptcfg->smpledge));
240 assert_param(IS_QSPI_READ_DATA_DELAY_TRANSMIT(dtcptcfg->dlytd));
241
242 status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE);
243
244 if (status != OK)
245 return status;
246
247 MODIFY_REG(hperh->perh->RDCR, QSPI_RDCR_BYLPC_MSK | QSPI_RDCR_DLYR_MSK | QSPI_RDCR_SMES_MSK | QSPI_RDCR_DLYT_MSK, \
248 dtcptcfg->bypsalcc | (dtcptcfg->dlydcl << 1) | (dtcptcfg->smpledge << 5) | (dtcptcfg->dlytd << 16));
249 return status;
250 }
IS_QSPI_ALL
#define IS_QSPI_ALL(x)
Definition: ald_qspi.h:380
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
qspi_data_capture_cfg_t::bypsalcc
type_func_t bypsalcc
Definition: ald_qspi.h:288
IS_QSPI_READ_DATA_DELAY_TRANSMIT
#define IS_QSPI_READ_DATA_DELAY_TRANSMIT(x)
Definition: ald_qspi.h:379
qspi_data_capture_cfg_t::smpledge
qspi_data_sampled_t smpledge
Definition: ald_qspi.h:289
qspi_wait_for_idle
static ald_status_t qspi_wait_for_idle(qspi_handle_t *hperh, uint32_t tickstart, uint32_t timeout)
Wait for a flag state until timeout.
Definition: ald_qspi.c:42
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
IS_QSPI_READ_DATA_CAPTURE_DELAY_READ
#define IS_QSPI_READ_DATA_CAPTURE_DELAY_READ(x)
Definition: ald_qspi.h:376
QSPI_TIMEOUT_DEFAULT_VALUE
#define QSPI_TIMEOUT_DEFAULT_VALUE
Definition: ald_qspi.h:456
qspi_data_capture_cfg_t::dlytd
uint32_t dlytd
Definition: ald_qspi.h:286
qspi_data_capture_cfg_t::dlydcl
uint32_t dlydcl
Definition: ald_qspi.h:287
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257
IS_QSPI_READ_DATA_SAMPLE_EDGE
#define IS_QSPI_READ_DATA_SAMPLE_EDGE(x)
Definition: ald_qspi.h:377
ERROR
Definition: utils.h:56

◆ ald_qspi_write_config()

ald_status_t ald_qspi_write_config | ( | qspi_handle_t * | hperh,
 |  | const qspi_write_cfg_t * | wrcfg
 | ) |  |

Configure Write Operations.

Parameters
hperh | Pointer to the QSPI qspi_handle_t structure.
wrcfg | Pointer to configuration structure for QSPI write operations.
Return values
Status,see ald_status_t.

Definition at line 170 of file ald_qspi.c.

171 {
172 ald_status_t status = ERROR;
173 uint32_t tickstart = ald_get_tick();
174
175 assert_param(IS_QSPI_WR_OPCODE(wrcfg->wrcde));
176 assert_param(IS_QSPI_DCYLES(wrcfg->dcyles));
177 assert_param(IS_QSPI_XFER_TYPE(wrcfg->datxfer));
178 assert_param(IS_QSPI_XFER_TYPE(wrcfg->addxfer));
179
180 status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE);
181
182 if (status != OK)
183 return status;
184
185 MODIFY_REG(hperh->perh->DWIR, QSPI_DWIR_WINST_MSK | QSPI_DWIR_DCYC_MSK | \
186 QSPI_DWIR_ADMODE_MSK | QSPI_DWIR_DMODE_MSK,
187 wrcfg->wrcde | \
188 (wrcfg->addxfer << 12) | \
189 (wrcfg->datxfer << 16) | \
190 (wrcfg->dcyles << 24));
191 if (wrcfg->autowel)
192 CLEAR_BIT(hperh->perh->DWIR, QSPI_DWIR_WELD_MSK);
193 else
194 SET_BIT(hperh->perh->DWIR, QSPI_DWIR_WELD_MSK);
195
196 return status;
197 }
OK
Definition: utils.h:55
qspi_write_cfg_t::datxfer
qspi_xfer_t datxfer
Definition: ald_qspi.h:212
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
qspi_write_cfg_t::addxfer
qspi_xfer_t addxfer
Definition: ald_qspi.h:211
IS_QSPI_WR_OPCODE
#define IS_QSPI_WR_OPCODE(x)
Definition: ald_qspi.h:396
qspi_write_cfg_t::dcyles
uint8_t dcyles
Definition: ald_qspi.h:210
qspi_write_cfg_t::autowel
type_func_t autowel
Definition: ald_qspi.h:214
qspi_wait_for_idle
static ald_status_t qspi_wait_for_idle(qspi_handle_t *hperh, uint32_t tickstart, uint32_t timeout)
Wait for a flag state until timeout.
Definition: ald_qspi.c:42
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
QSPI_TIMEOUT_DEFAULT_VALUE
#define QSPI_TIMEOUT_DEFAULT_VALUE
Definition: ald_qspi.h:456
qspi_write_cfg_t::wrcde
uint8_t wrcde
Definition: ald_qspi.h:209
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257
IS_QSPI_XFER_TYPE
#define IS_QSPI_XFER_TYPE(x)
Definition: ald_qspi.h:388
ERROR
Definition: utils.h:56
IS_QSPI_DCYLES
#define IS_QSPI_DCYLES(x)
Definition: ald_qspi.h:381

◆ qspi_dac_config()

ald_status_t qspi_dac_config | ( | qspi_handle_t * | hperh,
 |  | qspi_dac_cfg_t * | dcfg
 | ) |  |

Initializes the QSPI direct access according to the specified parameters in the associated handle.

Parameters
hperh | Pointer to the QSPI qspi_handle_t structure.
dcfg | : structure that contains the indirect read command configuration information.
Return values
Status,see ald_status_t.

Definition at line 295 of file ald_qspi.c.

296 {
297 ald_status_t status = ERROR;
298 uint32_t tickstart = ald_get_tick();
299
300 assert_param(IS_QSPI_WR_OPCODE(dcfg->wrinit.wrcde));
301 assert_param(IS_QSPI_DCYLES(dcfg->wrinit.dcyles));
302 assert_param(IS_QSPI_XFER_TYPE(dcfg->wrinit.datxfer));
303 assert_param(IS_QSPI_XFER_TYPE(dcfg->wrinit.addxfer));
304 assert_param(IS_QSPI_XFER_TYPE(dcfg->wrinit.instxfer));
305
306 status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE);
307
308 if (status != OK)
309 return status;
310
311 QSPI_DISABLE(hperh);
312 ald_qspi_init(hperh);
313
314 if (ald_qspi_write_config(hperh, &dcfg->wrinit) != OK)
315 return ERROR;
316 if (ald_qspi_read_config(hperh, &dcfg->rdinit) != OK)
317 return ERROR;
318
319 MODIFY_REG(hperh->perh->DWIR, QSPI_DWIR_WINST_MSK | QSPI_DWIR_DCYC_MSK | \
320 QSPI_DWIR_ADMODE_MSK | QSPI_DWIR_DMODE_MSK | \
321 QSPI_DWIR_WELD_MSK, dcfg->wrinit.wrcde | dcfg->wrinit.autowel | \
322 (dcfg->wrinit.addxfer << 12) | \
323 (dcfg->wrinit.datxfer << 16) | \
324 (dcfg->wrinit.dcyles << 24));
325 MODIFY_REG(hperh->perh->DRIR, QSPI_DRIR_RINST_MSK, dcfg->wrinit.instxfer);
326
327 if (dcfg->addrremap)
328 MODIFY_REG(hperh->perh->RAR, QSPI_RAR_READDR_MSK, dcfg->remapaddr);
329
330 MODIFY_REG(hperh->perh->CR, QSPI_CR_DTRM_MSK | QSPI_CR_ADEN_MSK | QSPI_CR_XIPIM_MSK | \
331 QSPI_CR_XIPNX_MSK | QSPI_CR_AREN_MSK | QSPI_CR_DMAEN_MSK, \
332 dcfg->dtrprtcol | dcfg->ahbdecoder);
333 QSPI_ENABLE(hperh);
334 return OK;
335 }
OK
Definition: utils.h:55
qspi_write_cfg_t::datxfer
qspi_xfer_t datxfer
Definition: ald_qspi.h:212
assert_param
#define assert_param(x)
Definition: type.h:88
qspi_write_cfg_t::addxfer
qspi_xfer_t addxfer
Definition: ald_qspi.h:211
qspi_dac_cfg_t::remapaddr
uint32_t remapaddr
Definition: ald_qspi.h:247
IS_QSPI_WR_OPCODE
#define IS_QSPI_WR_OPCODE(x)
Definition: ald_qspi.h:396
qspi_write_cfg_t::dcyles
uint8_t dcyles
Definition: ald_qspi.h:210
qspi_dac_cfg_t::ahbdecoder
type_func_t ahbdecoder
Definition: ald_qspi.h:243
ald_qspi_write_config
ald_status_t ald_qspi_write_config(qspi_handle_t *hperh, const qspi_write_cfg_t *wrcfg)
Configure Write Operations.
Definition: ald_qspi.c:170
QSPI_DISABLE
#define QSPI_DISABLE(hperh)
Definition: ald_qspi.h:465
qspi_write_cfg_t::autowel
type_func_t autowel
Definition: ald_qspi.h:214
QSPI_ENABLE
#define QSPI_ENABLE(hperh)
Definition: ald_qspi.h:464
qspi_wait_for_idle
static ald_status_t qspi_wait_for_idle(qspi_handle_t *hperh, uint32_t tickstart, uint32_t timeout)
Wait for a flag state until timeout.
Definition: ald_qspi.c:42
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
qspi_dac_cfg_t::wrinit
qspi_write_cfg_t wrinit
Definition: ald_qspi.h:250
qspi_dac_cfg_t::dtrprtcol
type_func_t dtrprtcol
Definition: ald_qspi.h:242
QSPI_TIMEOUT_DEFAULT_VALUE
#define QSPI_TIMEOUT_DEFAULT_VALUE
Definition: ald_qspi.h:456
qspi_dac_cfg_t::addrremap
type_func_t addrremap
Definition: ald_qspi.h:246
qspi_write_cfg_t::wrcde
uint8_t wrcde
Definition: ald_qspi.h:209
ald_qspi_init
void ald_qspi_init(qspi_handle_t *hperh)
Initializes the QSPI basic parameters.
Definition: ald_qspi.c:90
qspi_dac_cfg_t::rdinit
qspi_read_cfg_t rdinit
Definition: ald_qspi.h:249
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257
qspi_write_cfg_t::instxfer
qspi_xfer_t instxfer
Definition: ald_qspi.h:213
ald_qspi_read_config
ald_status_t ald_qspi_read_config(qspi_handle_t *hperh, const qspi_read_cfg_t *rdcfg)
Configure Read Operations.
Definition: ald_qspi.c:133
IS_QSPI_XFER_TYPE
#define IS_QSPI_XFER_TYPE(x)
Definition: ald_qspi.h:388
ERROR
Definition: utils.h:56
IS_QSPI_DCYLES
#define IS_QSPI_DCYLES(x)
Definition: ald_qspi.h:381


ALD User Manual: Indirect and stig access execution functions

Functions
Indirect and stig access execution functions
EASTSOFT ES32F3xx ALD » QSPI » QSPI Public Functions

QSPI indirect and stig access execution functions. More...

Collaboration diagram for Indirect and stig access execution functions:

Functions

ald_status_t | ald_qspi_indac_config (qspi_handle_t *hperh, qspi_indac_cfg_t *indcfg)
Initializes the QSPI indirect access according to the specified parameters in the associated handle. More...
ald_status_t | ald_qspi_indac_transmit_by_it (qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size)
QSPI write data by interrupt. More...
ald_status_t | ald_qspi_indac_transmit_by_poll (qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size)
Transmit data to flash by poll. More...
ald_status_t | ald_qspi_indac_read_by_poll (qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size)
Read data from flash by poll. More...
ald_status_t | ald_qspi_indac_read_by_it (qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size)
QSPI read data by interrupt. More...
ald_status_t | ald_qspi_execute_stig_cmd (qspi_handle_t *hperh, const qspi_stig_cmd_t *stigcmd)
Execute a STIG command. More...
ald_status_t | ald_qspi_indac_transmit_by_dma (qspi_handle_t *hperh, uint32_t addr, uint8_t *psrc, uint16_t size)
Sends an amount of data with DMA. More...
ald_status_t | ald_qspi_indac_read_by_dma (qspi_handle_t *hperh, uint32_t addr, uint8_t *pdbuf, uint16_t size)
Receive an amount of data with DMA. More...

Detailed Description

QSPI indirect and stig access execution functions.

Function Documentation

◆ ald_qspi_execute_stig_cmd()

ald_status_t ald_qspi_execute_stig_cmd | ( | qspi_handle_t * | hperh,
 |  | const qspi_stig_cmd_t * | stigcmd
 | ) |  |

Execute a STIG command.

Parameters
hperh | Pointer to the QSPI qspi_handle_t structure.
stigcmd | Pointer to a structure that describes the STIG command.
Return values
Status,see ald_status_t.

Definition at line 594 of file ald_qspi.c.

595 {
596 uint32_t i;
597 ald_status_t status = ERROR;
598 uint32_t tickstart = ald_get_tick();
599
600 assert_param(IS_QSPI_ALL(hperh->perh));
601 assert_param(stigcmd->addr_len <= 4);
602 assert_param(stigcmd->wr_len <= 8);
603 assert_param(stigcmd->rd_len <= 8);
604 assert_param(stigcmd->d_sycle < 32);
605
606 if (stigcmd->wr_len)
607 assert_param(stigcmd->wr_buf);
608 if (stigcmd->rd_len)
609 assert_param(stigcmd->rd_buf);
610
611 /* wait for Flash idle */
612 status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE);
613
614 if (status != OK)
615 return ERROR;
616
617 MODIFY_REG(hperh->perh->FCR, QSPI_FCR_OPCODE_MSK | QSPI_FCR_DUMNUM_MSK , ((stigcmd->code << 24) | (stigcmd->d_sycle << 7)));
618
619 if (stigcmd->wr_len) {
620 uint32_t buffer[2] = {0, 0};
621 uint8_t * dst = (uint8_t *) buffer;
622 uint8_t * src = stigcmd->wr_buf;
623
624 MODIFY_REG(hperh->perh->FCR, QSPI_FCR_WDNUM_MSK, (stigcmd->wr_len - 1) << QSPI_FCR_WDNUM_POSS);
625 SET_BIT(hperh->perh->FCR, QSPI_FCR_WREN_MSK);
626
627 for (i = 0; i < stigcmd->wr_len; i++)
628 dst[i] = src[i];
629
630 hperh->perh->FCWLR = buffer[0];
631 hperh->perh->FCWHR = buffer[1];
632 } else {
633 CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_WDNUM_MSK);
634 CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_WREN_MSK);
635 }
636
637 if (stigcmd->addr_len) {
638 SET_BIT(hperh->perh->FCR, QSPI_FCR_ADDREN_MSK);
639
640 MODIFY_REG(hperh->perh->FCR, QSPI_FCR_ADNUM_MSK, (stigcmd->addr_len - 1) << QSPI_FCR_ADNUM_POSS);
641 MODIFY_REG(hperh->perh->FCAR, QSPI_FCAR_CMDADR_MSK, stigcmd->addr);
642 } else {
643 CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_ADDREN_MSK);
644 CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_ADNUM_MSK);
645 CLEAR_BIT(hperh->perh->FCAR, QSPI_FCAR_CMDADR_MSK);
646 }
647
648 if (stigcmd->mode_bit) {
649 SET_BIT(hperh->perh->FCR, QSPI_FCR_MODBEN_MSK);
650 MODIFY_REG(hperh->perh->MBR, QSPI_MBR_MODEB_MSK, stigcmd->val);
651 } else {
652 CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_MODBEN_MSK);
653 CLEAR_BIT(hperh->perh->MBR, QSPI_MBR_MODEB_MSK);
654 }
655
656 if (stigcmd->rd_len) {
657 SET_BIT(hperh->perh->FCR, QSPI_FCR_RDEN_MSK);
658 MODIFY_REG(hperh->perh->FCR, QSPI_FCR_RDNUM_MSK, (stigcmd->rd_len - 1) << QSPI_FCR_RDNUM_POSS);
659 } else {
660 CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_RDEN_MSK);
661 CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_RDNUM_MSK);
662 }
663
664 /* Start command execution */
665 SET_BIT(hperh->perh->FCR, QSPI_FCR_CMDT_MSK);
666
667 while (hperh->perh->FCR & QSPI_FCR_CMDS_MSK);
668
669 /* Read data if any */
670 if (stigcmd->rd_len) {
671 uint32_t buffer[2] = { 0, 0 };
672 const uint8_t * src = (const uint8_t *)buffer;
673 uint8_t * dst = stigcmd->rd_buf;
674
675 buffer[0] = hperh->perh->FCRLR;
676 buffer[1] = hperh->perh->FCRHR;
677
678 for (i = 0; i < stigcmd->rd_len; i++) {
679 dst[i] = src[i];
680 }
681 }
682
683 return OK;
684 }
IS_QSPI_ALL
#define IS_QSPI_ALL(x)
Definition: ald_qspi.h:380
OK
Definition: utils.h:55
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
qspi_stig_cmd_t::val
uint32_t val
Definition: ald_qspi.h:165
qspi_stig_cmd_t::wr_len
uint32_t wr_len
Definition: ald_qspi.h:161
qspi_stig_cmd_t::rd_len
uint32_t rd_len
Definition: ald_qspi.h:159
qspi_stig_cmd_t::addr_len
uint32_t addr_len
Definition: ald_qspi.h:160
qspi_wait_for_idle
static ald_status_t qspi_wait_for_idle(qspi_handle_t *hperh, uint32_t tickstart, uint32_t timeout)
Wait for a flag state until timeout.
Definition: ald_qspi.c:42
qspi_stig_cmd_t::rd_buf
void * rd_buf
Definition: ald_qspi.h:167
qspi_stig_cmd_t::addr
uint32_t addr
Definition: ald_qspi.h:166
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
qspi_stig_cmd_t::wr_buf
void * wr_buf
Definition: ald_qspi.h:168
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
QSPI_TIMEOUT_DEFAULT_VALUE
#define QSPI_TIMEOUT_DEFAULT_VALUE
Definition: ald_qspi.h:456
qspi_stig_cmd_t::code
uint32_t code
Definition: ald_qspi.h:158
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
qspi_stig_cmd_t::d_sycle
uint32_t d_sycle
Definition: ald_qspi.h:162
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
qspi_stig_cmd_t::mode_bit
type_func_t mode_bit
Definition: ald_qspi.h:163
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257
ERROR
Definition: utils.h:56

◆ ald_qspi_indac_config()

ald_status_t ald_qspi_indac_config | ( | qspi_handle_t * | hperh,
 |  | qspi_indac_cfg_t * | indcfg
 | ) |  |

Initializes the QSPI indirect access according to the specified parameters in the associated handle.

Parameters
hperh | Pointer to the QSPI qspi_handle_t structure.
indcfg | Pointer to indirect access initialization structure qspi_indac_config_t.
Return values
Status,see ald_status_t.

Definition at line 352 of file ald_qspi.c.

353 {
354 ald_status_t status = ERROR;
355 uint32_t tickstart = ald_get_tick();
356
357 assert_param(IS_QSPI_ALL(hperh->perh));
358 assert_param(IS_QSPI_SRAM_PARTITION(indcfg->srampt));
359 assert_param(IS_QSPI_INDIRECT_TRIGGER_RANGE(indcfg->trgrng));
360 assert_param(IS_QSPI_INDIRECT_READ_WATERMARK(indcfg->rdwmark));
361
362 status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE);
363
364 if (status != OK)
365 return status;
366
367 QSPI_DISABLE(hperh);
368
369 MODIFY_REG(hperh->perh->SPR, QSPI_SPR_SRAMPS_MSK, indcfg->srampt);
370 MODIFY_REG(hperh->perh->IATR, QSPI_IATR_INDTAD_MSK, indcfg->trgaddr);
371 MODIFY_REG(hperh->perh->ITARR, QSPI_ITARR_RNGW_MSK, indcfg->trgrng);
372 MODIFY_REG(hperh->perh->IWTWR, QSPI_IWTWR_VAULE_MSK, indcfg->wrwmark);
373 MODIFY_REG(hperh->perh->IRTWR, QSPI_IRTWR_VAULE_MSK, indcfg->rdwmark);
374
375 QSPI_ENABLE(hperh);
376
377 return OK;
378 }
IS_QSPI_ALL
#define IS_QSPI_ALL(x)
Definition: ald_qspi.h:380
OK
Definition: utils.h:55
qspi_indac_cfg_t::wrwmark
uint32_t wrwmark
Definition: ald_qspi.h:234
assert_param
#define assert_param(x)
Definition: type.h:88
IS_QSPI_INDIRECT_READ_WATERMARK
#define IS_QSPI_INDIRECT_READ_WATERMARK(x)
Definition: ald_qspi.h:367
IS_QSPI_INDIRECT_TRIGGER_RANGE
#define IS_QSPI_INDIRECT_TRIGGER_RANGE(x)
Definition: ald_qspi.h:366
qspi_indac_cfg_t::trgaddr
uint32_t trgaddr
Definition: ald_qspi.h:232
qspi_indac_cfg_t::srampt
uint32_t srampt
Definition: ald_qspi.h:231
QSPI_DISABLE
#define QSPI_DISABLE(hperh)
Definition: ald_qspi.h:465
qspi_indac_cfg_t::trgrng
uint32_t trgrng
Definition: ald_qspi.h:233
QSPI_ENABLE
#define QSPI_ENABLE(hperh)
Definition: ald_qspi.h:464
qspi_wait_for_idle
static ald_status_t qspi_wait_for_idle(qspi_handle_t *hperh, uint32_t tickstart, uint32_t timeout)
Wait for a flag state until timeout.
Definition: ald_qspi.c:42
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
qspi_indac_cfg_t::rdwmark
uint32_t rdwmark
Definition: ald_qspi.h:235
QSPI_TIMEOUT_DEFAULT_VALUE
#define QSPI_TIMEOUT_DEFAULT_VALUE
Definition: ald_qspi.h:456
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257
IS_QSPI_SRAM_PARTITION
#define IS_QSPI_SRAM_PARTITION(x)
Definition: ald_qspi.h:365
ERROR
Definition: utils.h:56

◆ ald_qspi_indac_read_by_dma()

ald_status_t ald_qspi_indac_read_by_dma | ( | qspi_handle_t * | hperh,
 |  | uint32_t | addr,
 |  | uint8_t * | pdbuf,
 |  | uint16_t | size
 | ) |  |

Receive an amount of data with DMA.

Parameters
hperh | Pointer to a qspi_handle_t structure.
addr | Read start address.
pdbuf | Pointer to data buffer.
size | Read data bytes.
Return values
Status,see ald_status_t.

Definition at line 749 of file ald_qspi.c.

750 {
751 uint16_t cnt = 0;
752 ald_status_t status = OK;
753 uint32_t *tmp = (uint32_t *)pdbuf;
754 /* Get Indirect Read Trigger Address */
755 __IO uint32_t *data_reg = (uint32_t *)hperh->perh->IATR;
756
757 assert_param(IS_QSPI_ALL(hperh->perh));
758
759 if ((pdbuf == NULL) || (size == 0))
760 return ERROR;
761
762 MODIFY_REG(hperh->perh->IRTSAR, QSPI_IRTSAR_ADDR_MSK, addr);
763 MODIFY_REG(hperh->perh->IRTNR, QSPI_IRTNR_NUM_MSK, size);
764
765 QSPI_DMA_ENABLE(hperh);
766
767 if (size % 4)
768 cnt = (size / 4) + 1;
769 else
770 cnt = size / 4;
771
772 __LOCK(hperh);
773
774 hperh->hdma.perh = DMA0;
775 hperh->hdma.cplt_cbk = NULL;
776 ald_dma_config_struct(&hperh->hdma.config);
777
778 hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD;
779 hperh->hdma.config.src = (void *)data_reg;
780 hperh->hdma.config.dst = (void *)tmp;
781 hperh->hdma.config.size = cnt;
782 hperh->hdma.config.src_inc = DMA_DATA_INC_NONE;
783 hperh->hdma.config.dst_inc = DMA_DATA_INC_WORD;
784 hperh->hdma.config.msel = DMA_MSEL_QSPI;
785 hperh->hdma.config.msigsel = DMA_MSIGSEL_QSPI_READ;
786 hperh->hdma.config.channel = 0;
787 hperh->hdma.config.R_power = DMA_R_POWER_4;
788 hperh->hdma.config.burst = ENABLE;
789 ald_dma_config_basic(&hperh->hdma);
790
791 /* Trigger indirect write */
792 SET_BIT(hperh->perh->IRTR, QSPI_IRTR_RDST_MSK);
793 __UNLOCK(hperh);
794
795 return status;
796 }
IS_QSPI_ALL
#define IS_QSPI_ALL(x)
Definition: ald_qspi.h:380
DMA_R_POWER_4
Definition: ald_dma.h:253
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
dma_config_t::R_power
dma_arbiter_config_t R_power
Definition: ald_dma.h:284
assert_param
#define assert_param(x)
Definition: type.h:88
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
DMA_DATA_INC_WORD
Definition: ald_dma.h:219
DMA_DATA_SIZE_WORD
Definition: ald_dma.h:229
QSPI_DMA_ENABLE
#define QSPI_DMA_ENABLE(hperh)
Definition: ald_qspi.h:468
DMA_MSEL_QSPI
Definition: ald_dma.h:107
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
DMA_MSIGSEL_QSPI_READ
Definition: ald_dma.h:171
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
qspi_handle_t::hdma
dma_handle_t hdma
Definition: ald_qspi.h:266
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294

◆ ald_qspi_indac_read_by_it()

ald_status_t ald_qspi_indac_read_by_it | ( | qspi_handle_t * | hperh,
 |  | uint32_t | saddr,
 |  | uint8_t * | desbuf,
 |  | uint16_t | size
 | ) |  |

QSPI read data by interrupt.

Parameters
hperh | Pointer to a qspi_handle_t structure.
saddr | Read start address.
desbuf | Pointer to destination data buffer.
size | Read bytes length.
Return values
Status,see ald_status_t.

Definition at line 563 of file ald_qspi.c.

564 {
565 assert_param(IS_QSPI_ALL(hperh->perh));
566
567 if ((desbuf == NULL) || (size == 0))
568 return ERROR;
569
570 hperh->state = QSPI_STATE_BUSY_RX;
571 hperh->rx_buf = desbuf;
572 hperh->rx_cnt = 0;
573 hperh->rx_size = size;
574 hperh->tx_buf = NULL;
575 hperh->tx_cnt = 0;
576 hperh->tx_size = 0;
577
578 ald_qspi_clear_it_flag(hperh, QSPI_IF_INDCF);
579 MODIFY_REG(hperh->perh->IRTSAR, QSPI_IRTSAR_ADDR_MSK, saddr);
580 MODIFY_REG(hperh->perh->IRTNR, QSPI_IRTNR_NUM_MSK, size);
581 ald_qspi_interrupt_config(hperh, QSPI_IT_INDTWF, ENABLE);
582 ald_qspi_interrupt_config(hperh, QSPI_IT_INDCF, ENABLE);
583 SET_BIT(hperh->perh->IRTR, QSPI_IRTR_RDST_MSK);
584
585 return OK;
586 }
IS_QSPI_ALL
#define IS_QSPI_ALL(x)
Definition: ald_qspi.h:380
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
qspi_handle_t::rx_size
uint16_t rx_size
Definition: ald_qspi.h:263
qspi_handle_t::tx_buf
uint8_t * tx_buf
Definition: ald_qspi.h:259
qspi_handle_t::rx_buf
uint8_t * rx_buf
Definition: ald_qspi.h:262
qspi_handle_t::tx_size
uint16_t tx_size
Definition: ald_qspi.h:260
QSPI_STATE_BUSY_RX
Definition: ald_qspi.h:39
qspi_handle_t::rx_cnt
uint16_t rx_cnt
Definition: ald_qspi.h:264
ald_qspi_clear_it_flag
void ald_qspi_clear_it_flag(qspi_handle_t *hperh, qspi_flag_t flag)
Clear the QSPI interrupt flag.
Definition: ald_qspi.c:832
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
qspi_handle_t::tx_cnt
uint16_t tx_cnt
Definition: ald_qspi.h:261
qspi_handle_t::state
qspi_state_t state
Definition: ald_qspi.h:268
QSPI_IT_INDTWF
Definition: ald_qspi.h:331
QSPI_IF_INDCF
Definition: ald_qspi.h:354
QSPI_IT_INDCF
Definition: ald_qspi.h:335
ald_qspi_interrupt_config
void ald_qspi_interrupt_config(qspi_handle_t *hperh, qspi_it_t it, type_func_t state)
Enable/disable the specified QSPI interrupts.
Definition: ald_qspi.c:982
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257
ERROR
Definition: utils.h:56

◆ ald_qspi_indac_read_by_poll()

ald_status_t ald_qspi_indac_read_by_poll | ( | qspi_handle_t * | hperh,
 |  | uint32_t | saddr,
 |  | uint8_t * | desbuf,
 |  | uint16_t | size
 | ) |  |

Read data from flash by poll.

Parameters
hperh | Pointer to a qspi_handle_t structure.
saddr | Read start address.
desbuf | Pointer to data buffer.
size | Read bytes number.
Return values
Status,see ald_status_t.

Definition at line 496 of file ald_qspi.c.

497 {
498
499 uint32_t i = 0, j = 0, cnt = 0;
500 uint32_t tmp = 0;
501 uint32_t idx = 0, rxsm = 1;
502
503 assert_param(IS_QSPI_ALL(hperh->perh));
504
505 if ((desbuf == NULL) || (size == 0))
506 return ERROR;
507
508 MODIFY_REG(hperh->perh->IRTSAR, QSPI_IRTSAR_ADDR_MSK, saddr);
509 MODIFY_REG(hperh->perh->IRTNR, QSPI_IRTNR_NUM_MSK, size);
510 /* Counter read times totally */
511 if (size % 4)
512 cnt = (size / 4) + 1;
513 else
514 cnt = size / 4;
515 /* Get read SRAM partition (unit: 4bytes)*/
516 rxsm = READ_REG(hperh->perh->SPR) + 1;
517 if (cnt <= rxsm) {
518 SET_BIT(hperh->perh->IRTR, QSPI_IRTR_RDST_MSK);
519 do {
520 tmp = READ_REG(hperh->perh->SFLR);
521 tmp = tmp & 0x0000ffffU;
522 } while (tmp != cnt);
523 for (i = 0; i < cnt; ++i)
524 *(uint32_t *)(desbuf + 4 * i) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS;
525 } else {
526 SET_BIT(hperh->perh->IRTR, QSPI_IRTR_RDST_MSK);
527 for (j = 0; j < (cnt / rxsm); ++j) {
528 do {
529 tmp = READ_REG(hperh->perh->SFLR);
530 tmp = tmp & 0x0000ffffU;
531 } while (tmp != rxsm);
532 for (i = 0; i < rxsm; ++i) {
533 *(uint32_t *)(desbuf + idx + 4 * i) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS;
534 }
535 idx += rxsm * 4;
536 }
537 do {
538 tmp = READ_REG(hperh->perh->SFLR);
539 tmp = tmp & 0x0000ffffU;
540 } while ( tmp != (cnt % rxsm));
541
542 for (j = 0; j < (cnt % rxsm); ++j) {
543 *(uint32_t *)(desbuf + idx + 4 * i) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS;
544 }
545 }
546 /* Wait for indirect read operation completely */
547 do {
548 tmp = READ_REG(hperh->perh->IRTR);
549 } while (tmp & 0x04);
550
551 return OK;
552 }
IS_QSPI_ALL
#define IS_QSPI_ALL(x)
Definition: ald_qspi.h:380
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
READ_REG
#define READ_REG(reg)
Definition: type.h:73
QSPI_MEMORY_ADDRESS
#define QSPI_MEMORY_ADDRESS
Definition: ald_qspi.h:454
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257
ERROR
Definition: utils.h:56

◆ ald_qspi_indac_transmit_by_dma()

ald_status_t ald_qspi_indac_transmit_by_dma | ( | qspi_handle_t * | hperh,
 |  | uint32_t | addr,
 |  | uint8_t * | psrc,
 |  | uint16_t | size
 | ) |  |

Sends an amount of data with DMA.

Parameters
hperh | Pointer to a qspi_handle_t structure.
addr | Write start address.
psrc | Pointer to data buffer.
size | Write data bytes.
Return values
Status,see ald_status_t.

Definition at line 695 of file ald_qspi.c.

696 {
697 uint16_t cnt = 0;
698 uint32_t *tmp = (uint32_t*)psrc;
699 /* Get Indirect Read Trigger Address */
700 __IO uint32_t *data_reg = (uint32_t *)hperh->perh->IATR;
701
702 assert_param(IS_QSPI_ALL(hperh->perh));
703
704 if ((psrc == NULL) || (size == 0))
705 return ERROR;
706
707 MODIFY_REG(hperh->perh->IWTSAR, QSPI_IWTSAR_ADDR_MSK, addr);
708 MODIFY_REG(hperh->perh->IWTNR, QSPI_IWTNR_NUM_MSK, size);
709 QSPI_DMA_ENABLE(hperh);
710 if (size % 4)
711 cnt = (size / 4) + 1;
712 else
713 cnt = size / 4;
714
715 __LOCK(hperh);
716
717 hperh->hdma.perh = DMA0;
718 hperh->hdma.cplt_cbk = NULL;
719 ald_dma_config_struct(&hperh->hdma.config);
720
721 hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD;
722 hperh->hdma.config.src = (void *)tmp;
723 hperh->hdma.config.dst = (void *)data_reg;
724 hperh->hdma.config.size = cnt;
725 hperh->hdma.config.src_inc = DMA_DATA_INC_WORD;
726 hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE;
727 hperh->hdma.config.msel = DMA_MSEL_QSPI;
728 hperh->hdma.config.msigsel = DMA_MSIGSEL_QSPI_WRITE;
729 hperh->hdma.config.channel = 0;
730 hperh->hdma.config.R_power = DMA_R_POWER_4;
731 hperh->hdma.config.burst = ENABLE;
732 ald_dma_config_basic(&hperh->hdma);
733
734 /* Trigger indirect write */
735 SET_BIT(hperh->perh->IWTR, QSPI_IWTR_WRST_MSK);
736 __UNLOCK(hperh);
737
738 return OK;
739 }
IS_QSPI_ALL
#define IS_QSPI_ALL(x)
Definition: ald_qspi.h:380
DMA_R_POWER_4
Definition: ald_dma.h:253
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
dma_config_t::R_power
dma_arbiter_config_t R_power
Definition: ald_dma.h:284
assert_param
#define assert_param(x)
Definition: type.h:88
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
DMA_DATA_INC_WORD
Definition: ald_dma.h:219
DMA_DATA_SIZE_WORD
Definition: ald_dma.h:229
QSPI_DMA_ENABLE
#define QSPI_DMA_ENABLE(hperh)
Definition: ald_qspi.h:468
DMA_MSEL_QSPI
Definition: ald_dma.h:107
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
qspi_handle_t::hdma
dma_handle_t hdma
Definition: ald_qspi.h:266
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
DMA_MSIGSEL_QSPI_WRITE
Definition: ald_dma.h:170
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294

◆ ald_qspi_indac_transmit_by_it()

ald_status_t ald_qspi_indac_transmit_by_it | ( | qspi_handle_t * | hperh,
 |  | uint32_t | saddr,
 |  | uint8_t * | psrc,
 |  | uint32_t | size
 | ) |  |

QSPI write data by interrupt.

Parameters
hperh | Pointer to a qspi_handle_t structure.
saddr | Write start address.
psrc | Pointer to source data buffer.
size | : Write bytes number.
Return values
Status,see ald_status_t.

Definition at line 388 of file ald_qspi.c.

389 {
390 uint32_t i = 0;
391 uint32_t tmp = 0, pgsize = 0;
392 assert_param(IS_QSPI_ALL(hperh->perh));
393
394 if ((psrc == NULL) || (size == 0))
395 return ERROR;
396
397 hperh->state = QSPI_STATE_BUSY_TX;
398 hperh->rx_buf = NULL;
399 hperh->rx_cnt = 0;
400 hperh->rx_size = 0;
401 hperh->tx_buf = psrc;
402 hperh->tx_cnt = 0;
403 hperh->tx_size = size;
404
405 tmp = READ_REG(hperh->perh->DSCR);
406 pgsize = (tmp & 0xfff0) >> 4;
407
408 if (size >= pgsize)
409 tmp = pgsize;
410 else
411 tmp = size;
412
413 hperh->tx_cnt += tmp;
414
415 ald_qspi_clear_it_flag(hperh, QSPI_IF_INDCF);
416 MODIFY_REG(hperh->perh->IWTSAR, QSPI_IWTSAR_ADDR_MSK, saddr);
417 MODIFY_REG(hperh->perh->IWTNR, QSPI_IWTNR_NUM_MSK, size);
418 ald_qspi_interrupt_config(hperh, QSPI_IT_INDTWF, ENABLE);
419 ald_qspi_interrupt_config(hperh, QSPI_IT_INDCF, ENABLE);
420
421 /* Trigger indirect write */
422 SET_BIT(hperh->perh->IWTR, QSPI_IWTR_WRST_MSK);
423
424 for (i = 0; i < (tmp / 4); ++i)
425 *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(psrc + 4 * i));
426
427 return OK;
428 }
IS_QSPI_ALL
#define IS_QSPI_ALL(x)
Definition: ald_qspi.h:380
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
QSPI_STATE_BUSY_TX
Definition: ald_qspi.h:38
assert_param
#define assert_param(x)
Definition: type.h:88
READ_REG
#define READ_REG(reg)
Definition: type.h:73
qspi_handle_t::rx_size
uint16_t rx_size
Definition: ald_qspi.h:263
qspi_handle_t::tx_buf
uint8_t * tx_buf
Definition: ald_qspi.h:259
qspi_handle_t::rx_buf
uint8_t * rx_buf
Definition: ald_qspi.h:262
qspi_handle_t::tx_size
uint16_t tx_size
Definition: ald_qspi.h:260
QSPI_MEMORY_ADDRESS
#define QSPI_MEMORY_ADDRESS
Definition: ald_qspi.h:454
qspi_handle_t::rx_cnt
uint16_t rx_cnt
Definition: ald_qspi.h:264
ald_qspi_clear_it_flag
void ald_qspi_clear_it_flag(qspi_handle_t *hperh, qspi_flag_t flag)
Clear the QSPI interrupt flag.
Definition: ald_qspi.c:832
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
qspi_handle_t::tx_cnt
uint16_t tx_cnt
Definition: ald_qspi.h:261
qspi_handle_t::state
qspi_state_t state
Definition: ald_qspi.h:268
QSPI_IT_INDTWF
Definition: ald_qspi.h:331
QSPI_IF_INDCF
Definition: ald_qspi.h:354
QSPI_IT_INDCF
Definition: ald_qspi.h:335
ald_qspi_interrupt_config
void ald_qspi_interrupt_config(qspi_handle_t *hperh, qspi_it_t it, type_func_t state)
Enable/disable the specified QSPI interrupts.
Definition: ald_qspi.c:982
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257
ERROR
Definition: utils.h:56

◆ ald_qspi_indac_transmit_by_poll()

ald_status_t ald_qspi_indac_transmit_by_poll | ( | qspi_handle_t * | hperh,
 |  | uint32_t | saddr,
 |  | uint8_t * | psrc,
 |  | uint32_t | size
 | ) |  |

Transmit data to flash by poll.

Parameters
hperh | Pointer to a qspi_handle_t structure.
saddr | Write start address.
psrc | Pointer to source data buffer.
size | Write bytes number.
Return values
Status,see ald_status_t.

Definition at line 438 of file ald_qspi.c.

439 {
440 uint32_t i, j = 0, cnt = 0;
441 uint32_t tmp = 0;
442 uint32_t idx = 0, txsm = 0;
443 assert_param(IS_QSPI_ALL(hperh->perh));
444
445 if ((psrc == NULL) || (size == 0))
446 return ERROR;
447
448 MODIFY_REG(hperh->perh->IWTSAR, QSPI_IWTSAR_ADDR_MSK, saddr);
449 MODIFY_REG(hperh->perh->IWTNR, QSPI_IWTNR_NUM_MSK, size);
450
451 /* Counter write times totally */
452 if (size % 4)
453 cnt = (size / 4) + 1;
454 else
455 cnt = size / 4;
456 /* Get transmit SRAM partition (unit:4bytes)*/
457 tmp = READ_REG(hperh->perh->SPR);
458 txsm = QSPI_SRAM_SIZE - tmp;
459 if (cnt <= txsm) {
460 /* Trigger indirect write */
461 SET_BIT(hperh->perh->IWTR, QSPI_IWTR_WRST_MSK);
462 for (i = 0; i < cnt; ++i)
463 *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(psrc + 4 *i));
464 } else {
465 SET_BIT(hperh->perh->IWTR, QSPI_IWTR_WRST_MSK);
466 for (j = 0; j < (cnt / txsm); ++j) {
467 for (i = 0; i < txsm; ++i) {
468 *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(psrc + idx + 4 *i));
469 }
470 idx += txsm * 4;
471 do {
472 tmp = READ_REG(hperh->perh->SFLR);
473 tmp = (tmp >> 16) & 0xffff;
474 } while (tmp != 0);
475 }
476
477 for (j = 0; j < (cnt % txsm); ++j)
478 *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(psrc + idx + 4 *j));
479 }
480 /* Wait for indirect read operation completely */
481 do {
482 tmp = READ_REG(hperh->perh->IWTR);
483 } while ( tmp & 0x4);
484
485 return OK;
486 }
IS_QSPI_ALL
#define IS_QSPI_ALL(x)
Definition: ald_qspi.h:380
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
READ_REG
#define READ_REG(reg)
Definition: type.h:73
QSPI_MEMORY_ADDRESS
#define QSPI_MEMORY_ADDRESS
Definition: ald_qspi.h:454
QSPI_SRAM_SIZE
#define QSPI_SRAM_SIZE
Definition: ald_qspi.h:455
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257
ERROR
Definition: utils.h:56


ALD User Manual: Status functions

Functions
Status functions
EASTSOFT ES32F3xx ALD » QSPI » QSPI Public Functions

QSPI status functions. More...

Collaboration diagram for Status functions:

Functions

flag_status_t | qspi_get_flag_status (qspi_handle_t *hperh, qspi_flag_t flag)
Get the status of QSPI interrupt flag. More...
void | ald_qspi_clear_it_flag (qspi_handle_t *hperh, qspi_flag_t flag)
Clear the QSPI interrupt flag. More...
uint16_t | qspi_read_sram_fill_level (qspi_handle_t *hperh, qspi_sram_t srt)
Read QSPI SRAM fill level. More...
void | ald_qspi_write_proect_config (qspi_handle_t *hperh, qspi_wr_protect_t *wpcfg)
QSPI Write Protect Configuration. More...
void | ald_qspi_write_proect_inverse (qspi_handle_t *hperh, type_func_t state)
QSPI Write Protect Inversion. More...
void | ald_qspi_irq_handler (qspi_handle_t *hperh)
QSPI interrupt handler. More...
void | ald_qspi_interrupt_config (qspi_handle_t *hperh, qspi_it_t it, type_func_t state)
Enable/disable the specified QSPI interrupts. More...
void | ald_qspi_legacy_config (qspi_handle_t *hperh, const qspi_legacy_cfg_t *config)
Configure the QSPI legacy . More...
flag_status_t | qspi_indwr_get_status (qspi_handle_t *hperh, qspi_indwr_status_t status)
Get QSPI indirect write access status. More...
ald_status_t | qspi_indwr_wait_flag (qspi_handle_t *hperh, qspi_indwr_status_t flag, flag_status_t status, uint32_t timeout)
Wait indirect wriet a flag state until time out. More...
ald_status_t | qspi_indrd_wait_flag (qspi_handle_t *hperh, qspi_indrd_flag_t flag, flag_status_t status, uint32_t timeout)
QSPI Indirect read operation wait for specified status. More...
void | qspi_clear_flag_status (qspi_handle_t *hperh, qspi_flag_t flag)
Clear the QSPI interrupt flag. More...
ald_status_t | ald_qspi_auto_poll (qspi_handle_t *hperh, qspi_auto_poll_t *apcfg)

Detailed Description

QSPI status functions.

Function Documentation

◆ ald_qspi_auto_poll()

ald_status_t ald_qspi_auto_poll | ( | qspi_handle_t * | hperh,
 |  | qspi_auto_poll_t * | apcfg
 | ) |  |

◆ ald_qspi_clear_it_flag()

void ald_qspi_clear_it_flag | ( | qspi_handle_t * | hperh,
 |  | qspi_flag_t | flag
 | ) |  |

Clear the QSPI interrupt flag.

Parameters
hperh | Pointer to a qspi_handle_t structure.
flag | Specifies the QSPI interrupt flag. This parameter can be one of the qspi_flag_t.
Return values
None

Definition at line 832 of file ald_qspi.c.

833 {
834 assert_param(IS_QSPI_ALL(hperh->perh));
835 assert_param(IS_QSPI_IF(flag));
836
837 hperh->perh->IFR = flag;
838
839 return;
840 }
IS_QSPI_ALL
#define IS_QSPI_ALL(x)
Definition: ald_qspi.h:380
assert_param
#define assert_param(x)
Definition: type.h:88
IS_QSPI_IF
#define IS_QSPI_IF(x)
Definition: ald_qspi.h:417
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257

◆ ald_qspi_interrupt_config()

void ald_qspi_interrupt_config | ( | qspi_handle_t * | hperh,
 |  | qspi_it_t | it,
 |  | type_func_t | state
 | ) |  |

Enable/disable the specified QSPI interrupts.

Parameters
hperh | Pointer to a qspi_handle_t structure.
it | Specifies the QSPI interrupt sources to be enabled or disabled. This parameter can be one of the qspi_it_t.
state New state of the specified QSPI interrupts. This parameter can be:
  • ENABLE
  • DISABLE
Return values
None

Definition at line 982 of file ald_qspi.c.

983 {
984 assert_param(IS_QSPI_ALL(hperh->perh));
985 assert_param(IS_QSPI_IT(it));
986 assert_param(IS_FUNC_STATE(state));
987
988 if (state == ENABLE)
989 hperh->perh->IMR |= (uint32_t)it;
990 else
991 hperh->perh->IMR &= (uint32_t)(~it);
992
993 return;
994 }
IS_QSPI_ALL
#define IS_QSPI_ALL(x)
Definition: ald_qspi.h:380
ENABLE
Definition: type.h:49
assert_param
#define assert_param(x)
Definition: type.h:88
IS_QSPI_IT
#define IS_QSPI_IT(x)
Definition: ald_qspi.h:431
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_qspi_irq_handler()

void ald_qspi_irq_handler ( qspi_handle_t * hperh )

QSPI interrupt handler.

Return values
None

Definition at line 908 of file ald_qspi.c.

909 {
910 uint32_t regs = 0;
911 uint32_t tmp = 0, i = 0;
912
913 regs = READ_REG(hperh->perh->DSCR);
914 regs = (regs & 0x0000fff0) >> 4;
915
916 // indirect transmit
917 if (hperh->state == QSPI_STATE_BUSY_TX) {
918
919 //QSPI indirect transmit(xfer length longer than watermark value)
920 if (qspi_get_flag_status(hperh, QSPI_IF_INDTWF) == SET) {
921 ald_qspi_clear_it_flag(hperh, QSPI_IF_INDTWF);
922 tmp = hperh->tx_size - hperh->tx_cnt;
923 if (tmp > regs) {
924 for (i = 0; i < (regs / 4); ++i) {
925 *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(hperh->tx_buf + hperh->tx_cnt + 4 * i));
926 }
927 hperh->tx_cnt += regs;
928 } else {
929 for (i = 0; i < (tmp / 4); ++i) {
930 *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(hperh->tx_buf + hperh->tx_cnt + 4 * i));
931 }
932 hperh->tx_cnt += tmp;
933 }
934 }
935 //QSPI indirect transmit completely
936 if (qspi_get_flag_status(hperh, QSPI_IF_INDCF) == SET) {
937 ald_qspi_clear_it_flag(hperh, QSPI_IF_INDCF);
938 ald_qspi_interrupt_config(hperh, QSPI_IT_INDTWF, DISABLE);
939 //transmit completely callback
940 }
941
942 }
943
944 // indirect receive
945 if (hperh->state == QSPI_STATE_BUSY_RX) {
946 if (qspi_get_flag_status(hperh, QSPI_IF_INDTWF) == SET) {
947 ald_qspi_clear_it_flag(hperh, QSPI_IF_INDTWF);
948 tmp = READ_REG(hperh->perh->SFLR);
949 tmp = tmp & 0xffff;
950
951 for (i = 0; i < tmp; ++i) {
952 *(uint32_t *)(hperh->rx_buf + hperh->rx_cnt + i*4) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS;
953 }
954 hperh->rx_cnt += tmp*4;
955 }
956
957 if (qspi_get_flag_status(hperh, QSPI_IF_INDCF) == SET) {
958 ald_qspi_clear_it_flag(hperh, QSPI_IF_INDCF);
959 ald_qspi_interrupt_config(hperh, QSPI_IT_INDTWF, DISABLE);
960
961 tmp = READ_REG(hperh->perh->SFLR);
962 tmp = tmp & 0xffff;
963
964 for (i = 0; i < tmp; ++i) {
965 *(uint32_t *)(hperh->rx_buf + hperh->rx_cnt + i*4) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS;
966 }
967 }
968 }
969 }
QSPI_STATE_BUSY_TX
Definition: ald_qspi.h:38
READ_REG
#define READ_REG(reg)
Definition: type.h:73
SET
Definition: type.h:39
DISABLE
Definition: type.h:48
qspi_handle_t::tx_buf
uint8_t * tx_buf
Definition: ald_qspi.h:259
qspi_handle_t::rx_buf
uint8_t * rx_buf
Definition: ald_qspi.h:262
qspi_handle_t::tx_size
uint16_t tx_size
Definition: ald_qspi.h:260
QSPI_MEMORY_ADDRESS
#define QSPI_MEMORY_ADDRESS
Definition: ald_qspi.h:454
QSPI_STATE_BUSY_RX
Definition: ald_qspi.h:39
qspi_handle_t::rx_cnt
uint16_t rx_cnt
Definition: ald_qspi.h:264
ald_qspi_clear_it_flag
void ald_qspi_clear_it_flag(qspi_handle_t *hperh, qspi_flag_t flag)
Clear the QSPI interrupt flag.
Definition: ald_qspi.c:832
qspi_handle_t::tx_cnt
uint16_t tx_cnt
Definition: ald_qspi.h:261
qspi_handle_t::state
qspi_state_t state
Definition: ald_qspi.h:268
QSPI_IT_INDTWF
Definition: ald_qspi.h:331
QSPI_IF_INDTWF
Definition: ald_qspi.h:350
QSPI_IF_INDCF
Definition: ald_qspi.h:354
qspi_get_flag_status
flag_status_t qspi_get_flag_status(qspi_handle_t *hperh, qspi_flag_t flag)
Get the status of QSPI interrupt flag.
Definition: ald_qspi.c:814
ald_qspi_interrupt_config
void ald_qspi_interrupt_config(qspi_handle_t *hperh, qspi_it_t it, type_func_t state)
Enable/disable the specified QSPI interrupts.
Definition: ald_qspi.c:982
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257

◆ ald_qspi_legacy_config()

void ald_qspi_legacy_config | ( | qspi_handle_t * | hperh,
 |  | const qspi_legacy_cfg_t * | config
 | ) |  |

Configure the QSPI legacy .

Parameters
hperh | Pointer to a qspi_handle_t structure.
config | structure that contains the legacy configuration information.
Return values
None

Definition at line 1002 of file ald_qspi.c.

1003 {
1004 assert_param(IS_QSPI_ALL(hperh->perh));
1005
1006 MODIFY_REG(hperh->perh->TXHR, QSPI_TXHR_TXTH_MSK, config->tx_thrd);
1007 MODIFY_REG(hperh->perh->RXHR, QSPI_RXHR_RXTH_MSK, config->rx_thrd);
1008 QSPI_LEGACY_SPI_ENABLE(hperh);
1009
1010 return;
1011 }
IS_QSPI_ALL
#define IS_QSPI_ALL(x)
Definition: ald_qspi.h:380
assert_param
#define assert_param(x)
Definition: type.h:88
qspi_legacy_cfg_t::rx_thrd
uint8_t rx_thrd
Definition: ald_qspi.h:188
qspi_legacy_cfg_t::tx_thrd
uint8_t tx_thrd
Definition: ald_qspi.h:187
QSPI_LEGACY_SPI_ENABLE
#define QSPI_LEGACY_SPI_ENABLE(hperh)
Definition: ald_qspi.h:460
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257

◆ ald_qspi_write_proect_config()

void ald_qspi_write_proect_config | ( | qspi_handle_t * | hperh,
 |  | qspi_wr_protect_t * | wpcfg
 | ) |  |

QSPI Write Protect Configuration.

Parameters
hperh | Pointer to the QSPI qspi_handle_t structure.
wpcfg | Pointer to the QSPI write protect configuration structer.
Return values
None.

Definition at line 865 of file ald_qspi.c.

866 {
867 assert_param(IS_QSPI_ALL(hperh->perh));
868
869 MODIFY_REG(hperh->perh->WPLR, QSPI_WPLR_LBLKNUM_MSK, wpcfg->lowblk);
870 MODIFY_REG(hperh->perh->WPHR, QSPI_WPHR_HBLKNUM_MSK, wpcfg->upblk);
871 QSPI_WRITE_PROTECT_ENABLE(hperh);
872
873 return;
874 }
IS_QSPI_ALL
#define IS_QSPI_ALL(x)
Definition: ald_qspi.h:380
assert_param
#define assert_param(x)
Definition: type.h:88
qspi_wr_protect_t::upblk
uint32_t upblk
Definition: ald_qspi.h:151
QSPI_WRITE_PROTECT_ENABLE
#define QSPI_WRITE_PROTECT_ENABLE(hperh)
Definition: ald_qspi.h:462
qspi_wr_protect_t::lowblk
uint32_t lowblk
Definition: ald_qspi.h:150
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257

◆ ald_qspi_write_proect_inverse()

void ald_qspi_write_proect_inverse | ( | qspi_handle_t * | hperh,
 |  | type_func_t | state
 | ) |  |

QSPI Write Protect Inversion.

Parameters
hperh Pointer to the QSPI qspi_handle_t structure.
state SRAM protect inversion state. This parameter can be:
  • ENABLE
  • DISABLE
Return values
None.

Definition at line 885 of file ald_qspi.c.

886 {
887 assert_param(IS_FUNC_STATE(state));
888 assert_param(IS_QSPI_ALL(hperh->perh));
889
890 if (state) {
891 QSPI_WRITE_PROTECT_DISABLE(hperh);
892 SET_BIT(hperh->perh->WPCR, QSPI_WPCR_WPINV_MSK);
893 QSPI_WRITE_PROTECT_ENABLE(hperh);
894 }
895 else {
896 QSPI_WRITE_PROTECT_DISABLE(hperh);
897 SET_BIT(hperh->perh->WPCR, QSPI_WPCR_WPINV_MSK);
898 QSPI_WRITE_PROTECT_ENABLE(hperh);
899 }
900
901 return;
902 }
IS_QSPI_ALL
#define IS_QSPI_ALL(x)
Definition: ald_qspi.h:380
assert_param
#define assert_param(x)
Definition: type.h:88
QSPI_WRITE_PROTECT_ENABLE
#define QSPI_WRITE_PROTECT_ENABLE(hperh)
Definition: ald_qspi.h:462
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
QSPI_WRITE_PROTECT_DISABLE
#define QSPI_WRITE_PROTECT_DISABLE(hperh)
Definition: ald_qspi.h:463
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ qspi_clear_flag_status()

void qspi_clear_flag_status | ( | qspi_handle_t * | hperh,
 |  | qspi_flag_t | flag
 | ) |  |

Clear the QSPI interrupt flag.

Parameters
hperh | Pointer to a qspi_handle_t structure.
flag | Specifies the QSPI interrupt flag. This parameter can be one of the qspi_flag_t.
Return values
None

Definition at line 1088 of file ald_qspi.c.

1089 {
1090 assert_param(IS_QSPI_ALL(hperh->perh));
1091 assert_param(IS_QSPI_IF(flag));
1092
1093 hperh->perh->IFR = flag;
1094 return;
1095 }
IS_QSPI_ALL
#define IS_QSPI_ALL(x)
Definition: ald_qspi.h:380
assert_param
#define assert_param(x)
Definition: type.h:88
IS_QSPI_IF
#define IS_QSPI_IF(x)
Definition: ald_qspi.h:417
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257

◆ qspi_get_flag_status()

flag_status_t qspi_get_flag_status | ( | qspi_handle_t * | hperh,
 |  | qspi_flag_t | flag
 | ) |  |

Get the status of QSPI interrupt flag.

Parameters
hperh | Pointer to a qspi_handle_t structure.
flag | Specifies the QSPI interrupt flag. This parameter can be one of the qspi_flag_t.
Return values
Status,see flag_status_t.

Definition at line 814 of file ald_qspi.c.

815 {
816 assert_param(IS_QSPI_ALL(hperh->perh));
817 assert_param(IS_QSPI_IF(flag));
818
819 if (hperh->perh->IFR & flag)
820 return SET;
821
822 return RESET;
823 }
IS_QSPI_ALL
#define IS_QSPI_ALL(x)
Definition: ald_qspi.h:380
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
RESET
Definition: type.h:38
IS_QSPI_IF
#define IS_QSPI_IF(x)
Definition: ald_qspi.h:417
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257

◆ qspi_indrd_wait_flag()

ald_status_t qspi_indrd_wait_flag | ( | qspi_handle_t * | hperh,
 |  | qspi_indrd_flag_t | flag,
 |  | flag_status_t | status,
 |  | uint32_t | timeout
 | ) |  |

QSPI Indirect read operation wait for specified status.

Parameters
hperh | Pointer to a qspi_handle_t structure.
flag | specifies the qspi flag to check.
status | The new Flag status (SET or RESET).
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 1064 of file ald_qspi.c.

1065 {
1066 uint32_t tick;
1067
1068 if (timeout == 0)
1069 return ERROR;
1070
1071 tick = ald_get_tick();
1072
1073 /* Waiting for flag */
1074 while ((qspi_indrd_get_status(hperh, flag)) != status) {
1075 if (((ald_get_tick()) - tick) > timeout)
1076 return TIMEOUT;
1077 }
1078 return OK;
1079 }
OK
Definition: utils.h:55
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
qspi_indrd_get_status
static flag_status_t qspi_indrd_get_status(qspi_handle_t *hperh, qspi_indrd_flag_t status)
Get indirect read status.
Definition: ald_qspi.c:62
ERROR
Definition: utils.h:56

◆ qspi_indwr_get_status()

flag_status_t qspi_indwr_get_status | ( | qspi_handle_t * | hperh,
 |  | qspi_indwr_status_t | status
 | ) |  |

Get QSPI indirect write access status.

Parameters
hperh | Pointer to the QSPI qspi_handle_t structure.
status | qspi indirect write status.
Return values
Status,see ald_status_t.

Definition at line 1019 of file ald_qspi.c.

1020 {
1021 assert_param(IS_QSPI_ALL(hperh->perh));
1022 assert_param(IS_QSPI_INDIRECT_WRITE_STATUS(status));
1023
1024 if (hperh->perh->IWTR & status)
1025 return SET;
1026
1027 return RESET;
1028 }
IS_QSPI_ALL
#define IS_QSPI_ALL(x)
Definition: ald_qspi.h:380
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
RESET
Definition: type.h:38
IS_QSPI_INDIRECT_WRITE_STATUS
#define IS_QSPI_INDIRECT_WRITE_STATUS(x)
Definition: ald_qspi.h:370
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257

◆ qspi_indwr_wait_flag()

ald_status_t qspi_indwr_wait_flag | ( | qspi_handle_t * | hperh,
 |  | qspi_indwr_status_t | flag,
 |  | flag_status_t | status,
 |  | uint32_t | timeout
 | ) |  |

Wait indirect wriet a flag state until time out.

Parameters
hperh | Pointer to the QSPI qspi_handle_t structure.
flag | Flag checked,the parameter can be one of qspi_indwr_status_t.
status | Value of the flag expected,the parameter can be one of flag_status_t.
timeout | Duration of the time out.
Return values
Status,see ald_status_t.

Definition at line 1038 of file ald_qspi.c.

1039 {
1040 uint32_t tick;
1041
1042 if (timeout == 0)
1043 return ERROR;
1044
1045 tick = ald_get_tick();
1046
1047 /* Waiting for flag */
1048 while ((qspi_indwr_get_status(hperh, flag)) != status) {
1049 if (((ald_get_tick()) - tick) > timeout)
1050 return TIMEOUT;
1051 }
1052
1053 return OK;
1054 }
OK
Definition: utils.h:55
qspi_indwr_get_status
flag_status_t qspi_indwr_get_status(qspi_handle_t *hperh, qspi_indwr_status_t status)
Get QSPI indirect write access status.
Definition: ald_qspi.c:1019
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
ERROR
Definition: utils.h:56

◆ qspi_read_sram_fill_level()

uint16_t qspi_read_sram_fill_level | ( | qspi_handle_t * | hperh,
 |  | qspi_sram_t | srt
 | ) |  |

Read QSPI SRAM fill level.

Parameters
hperh | Pointer to the QSPI qspi_handle_t structure.
srt | QSPI embeded SRAM type,the value can be one of qspi_sram_t.
Return values
sram fill level value.

Definition at line 848 of file ald_qspi.c.

849 {
850 assert_param(IS_QSPI_ALL(hperh->perh));
851 assert_param(IS_QSPI_INDIRECT_SRAM_FILL_TYPE(srt));
852
853 if (srt == QSPI_SRAM_RD)
854 return READ_BITS(hperh->perh->SFLR, QSPI_SFLR_INDRSFL_MSK, QSPI_SFLR_INDRSFL_POSS);
855
856 return READ_BITS(hperh->perh->SFLR, QSPI_SFLR_INDWSFL_MSK, QSPI_SFLR_INDWSFL_POSS);
857 }
IS_QSPI_ALL
#define IS_QSPI_ALL(x)
Definition: ald_qspi.h:380
assert_param
#define assert_param(x)
Definition: type.h:88
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
QSPI_SRAM_RD
Definition: ald_qspi.h:55
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257
IS_QSPI_INDIRECT_SRAM_FILL_TYPE
#define IS_QSPI_INDIRECT_SRAM_FILL_TYPE(x)
Definition: ald_qspi.h:368


ALD User Manual: QSPI Public Types

Data Structures | Enumerations
QSPI Public Types
EASTSOFT ES32F3xx ALD » QSPI
Collaboration diagram for QSPI Public Types:

Data Structures

struct | qspi_device_size_t
Qspi external flash device configuration. More...
struct | qspi_wr_protect_t
Flash write-protected blocks configuration. More...
struct | qspi_stig_cmd_t
QSPI STIG Command Structure. More...
struct | qspi_init_t
QSPI base initialization structure. More...
struct | qspi_legacy_cfg_t
QSPI legacy initialization structure. More...
struct | qspi_read_cfg_t
QSPI Device Read Instruction Configuration structure. More...
struct | qspi_write_cfg_t
QSPI Device Write Instruction Configuration structure. More...
struct | qspi_indac_wr_cfg_t
QSPI Indirect Configuration structure.involatile parameters. More...
struct | qspi_indac_rd_cfg_t
struct | qspi_indac_cfg_t
struct | qspi_dac_cfg_t
QSPI DAC configuration. More...
struct | qspi_handle_t
QSPI Handle Structure definition. More...
struct | qspi_dly_cfg_t
Defines command to be executed using STIG mechanism. More...
struct | qspi_data_capture_cfg_t
QSPI Read Data Capture Configuration. More...
struct | qspi_auto_poll_t
QSPI Auto Poll Configuration Struction. More...

Enumerations

enum | qspi_state_t { QSPI_STATE_BUSY_TX = 0x11U, QSPI_STATE_BUSY_RX = 0x21U }
ALD QSPI state. More...
enum | qspi_xfer_t { QSPI_XFER_SINGLE = 0x00U, QSPI_XFER_DUAL = 0x01U, QSPI_XFER_QUAD = 0x02U }
QSPI Instruction Transfer Type. More...
enum | qspi_sram_t { QSPI_SRAM_RD = 0U, QSPI_SRAM_WR = 1U }
QSPI Indirect Access SRAM fill level. More...
enum | qspi_cpha_t { QSPI_CPHA_1E = 0U, QSPI_CPHA_2E = 1U }
QSPI Clock Phase. More...
enum | qspi_cpol_t { QSPI_CPOL_L = 0U, QSPI_CPOL_H = 1U }
QSPI_Clock_Polarity QSPI Clock Polarity. More...
enum | qspi_nss_decode_t { QSPI_SINGLE_CHIP = 0x0U, QSPI_MULTI_CHIP = 0x1U }
QSPI peripheral select decode. More...
enum qspi_clk_div_t {
QSPI_DIV_2 = 0x0U, QSPI_DIV_4 = 0x1U, QSPI_DIV_6 = 0x2U, QSPI_DIV_8 = 0x3U,
QSPI_DIV_10 = 0x4U, QSPI_DIV_12 = 0x5U, QSPI_DIV_14 = 0x6U, QSPI_DIV_16 = 0x7U,
QSPI_DIV_18 = 0x8U, QSPI_DIV_20 = 0x9U, QSPI_DIV_22 = 0xAU, QSPI_DIV_24 = 0xBU,
QSPI_DIV_26 = 0xCU, QSPI_DIV_28 = 0xDU, QSPI_DIV_30 = 0xEU, QSPI_DIV_32 = 0xFU
}
QSPI_Baud_Rate_Clock_Prescaler QSPI Baud Rate Clock Prescaler. More...
enum | qspi_nss_t { QSPI_CS_NSS0 = 0x0U, QSPI_CS_NSS1 = 0x1U, QSPI_CS_NSS2 = 0x3U, QSPI_CS_NSS3 = 0x7U }
QSPI Peripheral chip select decode. More...
enum | qspi_nss_size_t { QSPI_NSS_512M = 0x0U, QSPI_NSS_1G = 0x1U, QSPI_NSS_2G = 0x2U, QSPI_NSS_4G = 0x3U }
Size of flash connected to CS[x](x = 0 ~ 3)pin. More...
enum | qspi_data_sampled_t { QSPI_FALLING_E = 0x0U, QSPI_RISING_E = 0x1U }
QSPI Sample Edge Selection. More...
enum | qspi_indwr_status_t { QSPI_INDWR_PROGRESS = (1U << 2), QSPI_INDWR_CPLT = (1U << 5) }
QSPI Indirect Write Progress Status. More...
enum | qspi_indrd_flag_t { QSPI_INDRD_PROGRESS = (1U << 2), QSPI_RD_CPLT = (1U << 5) }
QSPI Indirect Read Progress Status. More...
enum qspi_it_t {
QSPI_IT_POLLF = (1U << 13), QSPI_IT_INDRSFF = (1U << 12), QSPI_IT_SRFFF = (1U << 11), QSPI_IT_SRFNEF = (1U << 10),
QSPI_IT_STFFF = (1U << 9), QSPI_IT_STFNFF = (1U << 8), QSPI_IT_ROVF = (1U << 7), QSPI_IT_INDTWF = (1U << 6),
QSPI_IT_AHBAEF = (1U << 5), QSPI_IT_WPAF = (1U << 4), QSPI_IT_INDRRF = (1U << 3), QSPI_IT_INDCF = (1U << 2),
QSPI_IT_UDFF = (1U << 1), QSPI_IT_MODFF = (1U << 0)
}
QSPI_Interrupt_definition QSPI Interrupt Definition. More...
enum qspi_flag_t {
QSPI_IF_POLLF = (1U << 13), QSPI_IF_INDRSFF = (1U << 12), QSPI_IF_SRFFF = (1U << 11), QSPI_IF_SRFNEF = (1U << 10),
QSPI_IF_STFFF = (1U << 9), QSPI_IF_STFNFF = (1U << 8), QSPI_IF_ROVF = (1U << 7), QSPI_IF_INDTWF = (1U << 6),
QSPI_IF_AHBAEF = (1U << 5), QSPI_IF_WPAF = (1U << 4), QSPI_IF_INDRRF = (1U << 3), QSPI_IF_INDCF = (1U << 2),
QSPI_IF_UDFF = (1U << 1), QSPI_IF_MODFF = (1U << 0)
}
QSPI_Flag_definition QSPI Flag Definition. More...

Detailed Description

Enumeration Type Documentation

◆ qspi_clk_div_t

enum qspi_clk_div_t

QSPI_Baud_Rate_Clock_Prescaler QSPI Baud Rate Clock Prescaler.

Enumerator
QSPI_DIV_2 | Master mode baud rate dibisor 2
QSPI_DIV_4 | Master mode baud rate dibisor 4
QSPI_DIV_6 | Master mode baud rate dibisor 6
QSPI_DIV_8 | Master mode baud rate dibisor 8
QSPI_DIV_10 | Master mode baud rate dibisor 10
QSPI_DIV_12 | Master mode baud rate dibisor 12
QSPI_DIV_14 | Master mode baud rate dibisor 14
QSPI_DIV_16 | Master mode baud rate dibisor 16
QSPI_DIV_18 | Master mode baud rate dibisor 18
QSPI_DIV_20 | Master mode baud rate dibisor 20
QSPI_DIV_22 | Master mode baud rate dibisor 22
QSPI_DIV_24 | Master mode baud rate dibisor 24
QSPI_DIV_26 | Master mode baud rate dibisor 26
QSPI_DIV_28 | Master mode baud rate dibisor 28
QSPI_DIV_30 | Master mode baud rate dibisor 30
QSPI_DIV_32 | Master mode baud rate dibisor 32

Definition at line 86 of file ald_qspi.h.

86 {
87 QSPI_DIV_2 = 0x0U,
88 QSPI_DIV_4 = 0x1U,
89 QSPI_DIV_6 = 0x2U,
90 QSPI_DIV_8 = 0x3U,
91 QSPI_DIV_10 = 0x4U,
92 QSPI_DIV_12 = 0x5U,
93 QSPI_DIV_14 = 0x6U,
94 QSPI_DIV_16 = 0x7U,
95 QSPI_DIV_18 = 0x8U,
96 QSPI_DIV_20 = 0x9U,
97 QSPI_DIV_22 = 0xAU,
98 QSPI_DIV_24 = 0xBU,
99 QSPI_DIV_26 = 0xCU,
100 QSPI_DIV_28 = 0xDU,
101 QSPI_DIV_30 = 0xEU,
102 QSPI_DIV_32 = 0xFU,
103 } qspi_clk_div_t;
QSPI_DIV_4
Definition: ald_qspi.h:88
QSPI_DIV_10
Definition: ald_qspi.h:91
QSPI_DIV_32
Definition: ald_qspi.h:102
QSPI_DIV_26
Definition: ald_qspi.h:99
qspi_clk_div_t
qspi_clk_div_t
QSPI_Baud_Rate_Clock_Prescaler QSPI Baud Rate Clock Prescaler.
Definition: ald_qspi.h:86
QSPI_DIV_30
Definition: ald_qspi.h:101
QSPI_DIV_16
Definition: ald_qspi.h:94
QSPI_DIV_24
Definition: ald_qspi.h:98
QSPI_DIV_12
Definition: ald_qspi.h:92
QSPI_DIV_22
Definition: ald_qspi.h:97
QSPI_DIV_28
Definition: ald_qspi.h:100
QSPI_DIV_14
Definition: ald_qspi.h:93
QSPI_DIV_2
Definition: ald_qspi.h:87
QSPI_DIV_6
Definition: ald_qspi.h:89
QSPI_DIV_8
Definition: ald_qspi.h:90
QSPI_DIV_20
Definition: ald_qspi.h:96
QSPI_DIV_18
Definition: ald_qspi.h:95

◆ qspi_cpha_t

enum qspi_cpha_t

QSPI Clock Phase.

Enumerator
QSPI_CPHA_1E | First edge
QSPI_CPHA_2E | Second edge

Definition at line 62 of file ald_qspi.h.

62 {
63 QSPI_CPHA_1E = 0U,
64 QSPI_CPHA_2E = 1U,
65 } qspi_cpha_t;
QSPI_CPHA_1E
Definition: ald_qspi.h:63
QSPI_CPHA_2E
Definition: ald_qspi.h:64
qspi_cpha_t
qspi_cpha_t
QSPI Clock Phase.
Definition: ald_qspi.h:62

◆ qspi_cpol_t

enum qspi_cpol_t

QSPI_Clock_Polarity QSPI Clock Polarity.

Enumerator
QSPI_CPOL_L | QSPI clock polarity low
QSPI_CPOL_H | QSPI clock polarity high

Definition at line 70 of file ald_qspi.h.

70 {
71 QSPI_CPOL_L = 0U,
72 QSPI_CPOL_H = 1U,
73 } qspi_cpol_t;
QSPI_CPOL_H
Definition: ald_qspi.h:72
QSPI_CPOL_L
Definition: ald_qspi.h:71
qspi_cpol_t
qspi_cpol_t
QSPI_Clock_Polarity QSPI Clock Polarity.
Definition: ald_qspi.h:70

◆ qspi_data_sampled_t

enum qspi_data_sampled_t

QSPI Sample Edge Selection.

Enumerator
QSPI_FALLING_E | Data outputs from flash are sampled on falling edge of the ref_clk
QSPI_RISING_E | Data outputs from flash are sampled on rising edge of the ref_clk

Definition at line 141 of file ald_qspi.h.

141 {
142 QSPI_FALLING_E = 0x0U,
143 QSPI_RISING_E = 0x1U,
144 } qspi_data_sampled_t;
QSPI_RISING_E
Definition: ald_qspi.h:143
qspi_data_sampled_t
qspi_data_sampled_t
QSPI Sample Edge Selection.
Definition: ald_qspi.h:141
QSPI_FALLING_E
Definition: ald_qspi.h:142

◆ qspi_flag_t

enum qspi_flag_t

QSPI_Flag_definition QSPI Flag Definition.

Enumerator
QSPI_IF_POLLF | Programmed polls cycles expired flag
QSPI_IF_INDRSFF | Indirect read partition of SRAM is full flag
QSPI_IF_SRFFF | Small rx FIFO full flag
QSPI_IF_SRFNEF | Small rx FIFO not empty flag
QSPI_IF_STFFF | Small tx FIFO full flag
QSPI_IF_STFNFF | Small tx FIFO not full flag
QSPI_IF_ROVF | Receive overflow flag
QSPI_IF_INDTWF | Indirect transfer watermark level breached flag
QSPI_IF_AHBAEF | Illegal AHB access detected flag
QSPI_IF_WPAF | Write to protected area was rejected flag
QSPI_IF_INDRRF | Indirect operation could not be accepted flag
QSPI_IF_INDCF | Controller has completed last triggered indirect operation flag
QSPI_IF_UDFF | Underflow detected flag
QSPI_IF_MODFF | Mode fail M flag

Definition at line 342 of file ald_qspi.h.

342 {
343 QSPI_IF_POLLF = (1U << 13),
344 QSPI_IF_INDRSFF = (1U << 12),
345 QSPI_IF_SRFFF = (1U << 11),
346 QSPI_IF_SRFNEF = (1U << 10),
347 QSPI_IF_STFFF = (1U << 9),
348 QSPI_IF_STFNFF = (1U << 8),
349 QSPI_IF_ROVF = (1U << 7),
350 QSPI_IF_INDTWF = (1U << 6),
351 QSPI_IF_AHBAEF = (1U << 5),
352 QSPI_IF_WPAF = (1U << 4),
353 QSPI_IF_INDRRF = (1U << 3),
354 QSPI_IF_INDCF = (1U << 2),
355 QSPI_IF_UDFF = (1U << 1),
356 QSPI_IF_MODFF = (1U << 0),
357 } qspi_flag_t;
qspi_flag_t
qspi_flag_t
QSPI_Flag_definition QSPI Flag Definition.
Definition: ald_qspi.h:342
QSPI_IF_UDFF
Definition: ald_qspi.h:355
QSPI_IF_STFFF
Definition: ald_qspi.h:347
QSPI_IF_POLLF
Definition: ald_qspi.h:343
QSPI_IF_SRFFF
Definition: ald_qspi.h:345
QSPI_IF_INDRRF
Definition: ald_qspi.h:353
QSPI_IF_INDRSFF
Definition: ald_qspi.h:344
QSPI_IF_SRFNEF
Definition: ald_qspi.h:346
QSPI_IF_AHBAEF
Definition: ald_qspi.h:351
QSPI_IF_STFNFF
Definition: ald_qspi.h:348
QSPI_IF_WPAF
Definition: ald_qspi.h:352
QSPI_IF_INDTWF
Definition: ald_qspi.h:350
QSPI_IF_INDCF
Definition: ald_qspi.h:354
QSPI_IF_MODFF
Definition: ald_qspi.h:356
QSPI_IF_ROVF
Definition: ald_qspi.h:349

◆ qspi_indrd_flag_t

enum qspi_indrd_flag_t

QSPI Indirect Read Progress Status.

Enumerator
QSPI_INDRD_PROGRESS | Indirect read operation in progress
QSPI_RD_CPLT | Indirect read completion

Definition at line 303 of file ald_qspi.h.

303 {
304 QSPI_INDRD_PROGRESS = (1U << 2),
305 QSPI_RD_CPLT = (1U << 5),
306 } qspi_indrd_flag_t;
QSPI_RD_CPLT
Definition: ald_qspi.h:305
QSPI_INDRD_PROGRESS
Definition: ald_qspi.h:304
qspi_indrd_flag_t
qspi_indrd_flag_t
QSPI Indirect Read Progress Status.
Definition: ald_qspi.h:303

◆ qspi_indwr_status_t

enum qspi_indwr_status_t

QSPI Indirect Write Progress Status.

Enumerator
QSPI_INDWR_PROGRESS | Indirect write operation in progress
QSPI_INDWR_CPLT | Indirect write completion

Definition at line 295 of file ald_qspi.h.

295 {
296 QSPI_INDWR_PROGRESS = (1U << 2),
297 QSPI_INDWR_CPLT = (1U << 5),
298 } qspi_indwr_status_t;
QSPI_INDWR_CPLT
Definition: ald_qspi.h:297
QSPI_INDWR_PROGRESS
Definition: ald_qspi.h:296
qspi_indwr_status_t
qspi_indwr_status_t
QSPI Indirect Write Progress Status.
Definition: ald_qspi.h:295

◆ qspi_it_t

enum qspi_it_t

QSPI_Interrupt_definition QSPI Interrupt Definition.

Enumerator
QSPI_IT_POLLF | Programmed polls cycles expired flag
QSPI_IT_INDRSFF | Indirect read partition of SRAM is full flag
QSPI_IT_SRFFF | Small rx FIFO full flag
QSPI_IT_SRFNEF | Small rx FIFO not empty flag
QSPI_IT_STFFF | Small tx FIFO full flag
QSPI_IT_STFNFF | Small tx FIFO not full flag
QSPI_IT_ROVF | Receive overflow flag
QSPI_IT_INDTWF | Indirect transfer watermark level breached flag
QSPI_IT_AHBAEF | Illegal AHB access detected flag
QSPI_IT_WPAF | Write to protected area was rejected flag
QSPI_IT_INDRRF | Indirect operation could not be accepted flag
QSPI_IT_INDCF | Controller has completed last triggered indirect operation flag
QSPI_IT_UDFF | Underflow detected flag
QSPI_IT_MODFF | Mode fail M flag

Definition at line 323 of file ald_qspi.h.

323 {
324 QSPI_IT_POLLF = (1U << 13),
325 QSPI_IT_INDRSFF = (1U << 12),
326 QSPI_IT_SRFFF = (1U << 11),
327 QSPI_IT_SRFNEF = (1U << 10),
328 QSPI_IT_STFFF = (1U << 9),
329 QSPI_IT_STFNFF = (1U << 8),
330 QSPI_IT_ROVF = (1U << 7),
331 QSPI_IT_INDTWF = (1U << 6),
332 QSPI_IT_AHBAEF = (1U << 5),
333 QSPI_IT_WPAF = (1U << 4),
334 QSPI_IT_INDRRF = (1U << 3),
335 QSPI_IT_INDCF = (1U << 2),
336 QSPI_IT_UDFF = (1U << 1),
337 QSPI_IT_MODFF = (1U << 0),
338 } qspi_it_t;
QSPI_IT_AHBAEF
Definition: ald_qspi.h:332
QSPI_IT_WPAF
Definition: ald_qspi.h:333
qspi_it_t
qspi_it_t
QSPI_Interrupt_definition QSPI Interrupt Definition.
Definition: ald_qspi.h:323
QSPI_IT_SRFNEF
Definition: ald_qspi.h:327
QSPI_IT_INDRSFF
Definition: ald_qspi.h:325
QSPI_IT_MODFF
Definition: ald_qspi.h:337
QSPI_IT_STFNFF
Definition: ald_qspi.h:329
QSPI_IT_SRFFF
Definition: ald_qspi.h:326
QSPI_IT_INDRRF
Definition: ald_qspi.h:334
QSPI_IT_STFFF
Definition: ald_qspi.h:328
QSPI_IT_INDTWF
Definition: ald_qspi.h:331
QSPI_IT_ROVF
Definition: ald_qspi.h:330
QSPI_IT_INDCF
Definition: ald_qspi.h:335
QSPI_IT_POLLF
Definition: ald_qspi.h:324
QSPI_IT_UDFF
Definition: ald_qspi.h:336

◆ qspi_nss_decode_t

enum qspi_nss_decode_t

QSPI peripheral select decode.

Enumerator
QSPI_SINGLE_CHIP | Only 1 of 4 selects n_ss_out[3:0] is active
QSPI_MULTI_CHIP | Allow external 4-to-16 decode

Definition at line 78 of file ald_qspi.h.

78 {
79 QSPI_SINGLE_CHIP = 0x0U,
80 QSPI_MULTI_CHIP = 0x1U,
81 } qspi_nss_decode_t;
QSPI_MULTI_CHIP
Definition: ald_qspi.h:80
qspi_nss_decode_t
qspi_nss_decode_t
QSPI peripheral select decode.
Definition: ald_qspi.h:78
QSPI_SINGLE_CHIP
Definition: ald_qspi.h:79

◆ qspi_nss_size_t

enum qspi_nss_size_t

Size of flash connected to CS[x](x = 0 ~ 3)pin.

Enumerator
QSPI_NSS_512M | size of 512Mb
QSPI_NSS_1G | size of 1Gb
QSPI_NSS_2G | size of 2Gb
QSPI_NSS_4G | size of 3Gb

Definition at line 118 of file ald_qspi.h.

118 {
119 QSPI_NSS_512M = 0x0U,
120 QSPI_NSS_1G = 0x1U,
121 QSPI_NSS_2G = 0x2U,
122 QSPI_NSS_4G = 0x3U,
123 } qspi_nss_size_t;
qspi_nss_size_t
qspi_nss_size_t
Size of flash connected to CS[x](x = 0 ~ 3)pin.
Definition: ald_qspi.h:118
QSPI_NSS_512M
Definition: ald_qspi.h:119
QSPI_NSS_4G
Definition: ald_qspi.h:122
QSPI_NSS_2G
Definition: ald_qspi.h:121
QSPI_NSS_1G
Definition: ald_qspi.h:120

◆ qspi_nss_t

enum qspi_nss_t

QSPI Peripheral chip select decode.

Enumerator
QSPI_CS_NSS0 | NSS0 active
QSPI_CS_NSS1 | NSS1 active
QSPI_CS_NSS2 | NSS2 active
QSPI_CS_NSS3 | NSS3 active

Definition at line 108 of file ald_qspi.h.

108 {
109 QSPI_CS_NSS0 = 0x0U,
110 QSPI_CS_NSS1 = 0x1U,
111 QSPI_CS_NSS2 = 0x3U,
112 QSPI_CS_NSS3 = 0x7U,
113 } qspi_nss_t;
QSPI_CS_NSS3
Definition: ald_qspi.h:112
QSPI_CS_NSS2
Definition: ald_qspi.h:111
QSPI_CS_NSS0
Definition: ald_qspi.h:109
qspi_nss_t
qspi_nss_t
QSPI Peripheral chip select decode.
Definition: ald_qspi.h:108
QSPI_CS_NSS1
Definition: ald_qspi.h:110

◆ qspi_sram_t

enum qspi_sram_t

QSPI Indirect Access SRAM fill level.

Enumerator
QSPI_SRAM_RD | SRAM fill level(indirect write partition)in units of words(4bytes)
QSPI_SRAM_WR | SRAM fill level(indirect read partition)in units of words(4bytes)

Definition at line 54 of file ald_qspi.h.

54 {
55 QSPI_SRAM_RD = 0U,
56 QSPI_SRAM_WR = 1U,
57 } qspi_sram_t;
QSPI_SRAM_WR
Definition: ald_qspi.h:56
qspi_sram_t
qspi_sram_t
QSPI Indirect Access SRAM fill level.
Definition: ald_qspi.h:54
QSPI_SRAM_RD
Definition: ald_qspi.h:55

◆ qspi_state_t

enum qspi_state_t

ALD QSPI state.

Enumerator
QSPI_STATE_BUSY_TX | Data Transmission process is ongoing
QSPI_STATE_BUSY_RX | Data Reception process is ongoing

Definition at line 37 of file ald_qspi.h.

37 {
38 QSPI_STATE_BUSY_TX = 0x11U,
39 QSPI_STATE_BUSY_RX = 0x21U,
40 } qspi_state_t;
QSPI_STATE_BUSY_TX
Definition: ald_qspi.h:38
QSPI_STATE_BUSY_RX
Definition: ald_qspi.h:39
qspi_state_t
qspi_state_t
ALD QSPI state.
Definition: ald_qspi.h:37

◆ qspi_xfer_t

enum qspi_xfer_t

QSPI Instruction Transfer Type.

Enumerator
QSPI_XFER_SINGLE | Instruction shifted on DQ0 only
QSPI_XFER_DUAL | Instruction,Address and data sent on DQ0 and DQ1
QSPI_XFER_QUAD | Instruction,Address and data sent on DQ0,DQ1 and DQ2

Definition at line 45 of file ald_qspi.h.

45 {
46 QSPI_XFER_SINGLE = 0x00U,
47 QSPI_XFER_DUAL = 0x01U,
48 QSPI_XFER_QUAD = 0x02U,
49 } qspi_xfer_t;
QSPI_XFER_SINGLE
Definition: ald_qspi.h:46
QSPI_XFER_QUAD
Definition: ald_qspi.h:48
qspi_xfer_t
qspi_xfer_t
QSPI Instruction Transfer Type.
Definition: ald_qspi.h:45
QSPI_XFER_DUAL
Definition: ald_qspi.h:47


ALD User Manual: qspi_device_size_t Struct Reference

Data Fields
qspi_device_size_t Struct Reference
EASTSOFT ES32F3xx ALD » QSPI » QSPI Public Types

Qspi external flash device configuration. More...

#include <ald_qspi.h>

Data Fields

uint8_t | addr
uint16_t | page
uint16_t | blk
qspi_nss_size_t cs0
qspi_nss_size_t cs1
qspi_nss_size_t cs2
qspi_nss_size_t cs3

Detailed Description

Qspi external flash device configuration.

Definition at line 128 of file ald_qspi.h.

Field Documentation

◆ addr

uint8_t addr

Peripheral address

Definition at line 129 of file ald_qspi.h.

◆ blk

uint16_t blk

Flash block size

Definition at line 131 of file ald_qspi.h.

◆ cs0

qspi_nss_size_t cs0

NSS0 flash size

Definition at line 132 of file ald_qspi.h.

◆ cs1

qspi_nss_size_t cs1

NSS1 flash size

Definition at line 133 of file ald_qspi.h.

◆ cs2

qspi_nss_size_t cs2

NSS2 flash size

Definition at line 134 of file ald_qspi.h.

◆ cs3

qspi_nss_size_t cs3

NSS3 flash size

Definition at line 135 of file ald_qspi.h.

◆ page

uint16_t page

Flash page size

Definition at line 130 of file ald_qspi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_qspi.h


ALD User Manual: qspi_wr_protect_t Struct Reference

Data Fields
qspi_wr_protect_t Struct Reference
EASTSOFT ES32F3xx ALD » QSPI » QSPI Public Types

Flash write-protected blocks configuration. More...

#include <ald_qspi.h>

Data Fields

uint32_t | lowblk
uint32_t | upblk

Detailed Description

Flash write-protected blocks configuration.

Definition at line 149 of file ald_qspi.h.

Field Documentation

◆ lowblk

uint32_t lowblk

the lower block in the range of blocks that is to be locked from writing

Definition at line 150 of file ald_qspi.h.

◆ upblk

uint32_t upblk

upper block in the range of blocks that is to be locked from writing

Definition at line 151 of file ald_qspi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_qspi.h


ALD User Manual: qspi_stig_cmd_t Struct Reference

Data Fields
qspi_stig_cmd_t Struct Reference
EASTSOFT ES32F3xx ALD » QSPI » QSPI Public Types

QSPI STIG Command Structure. More...

#include <ald_qspi.h>

Data Fields

uint32_t | code
uint32_t | rd_len
uint32_t | addr_len
uint32_t | wr_len
uint32_t | d_sycle
type_func_t mode_bit
type_func_t op_addr
uint32_t | val
uint32_t | addr
void * | rd_buf
void * | wr_buf

Detailed Description

QSPI STIG Command Structure.

Definition at line 157 of file ald_qspi.h.

Field Documentation

◆ addr

uint32_t addr

Flash opcde address

Definition at line 166 of file ald_qspi.h.

◆ addr_len

uint32_t addr_len

Number of Address Bytes

Definition at line 160 of file ald_qspi.h.

◆ code

uint32_t code

command op-code

Definition at line 158 of file ald_qspi.h.

◆ d_sycle

uint32_t d_sycle

Number of dummy cycles

Definition at line 162 of file ald_qspi.h.

◆ mode_bit

type_func_t mode_bit

Mode Bit Configuration register are sent following the address bytes

Definition at line 163 of file ald_qspi.h.

◆ op_addr

type_func_t op_addr

If opcde requires an address

Definition at line 164 of file ald_qspi.h.

◆ rd_buf

void* rd_buf

Buffer for read data

Definition at line 167 of file ald_qspi.h.

◆ rd_len

uint32_t rd_len

Number of Read Data Bytes

Definition at line 159 of file ald_qspi.h.

◆ val

uint32_t val

Mode bits,sent to device following the address

Definition at line 165 of file ald_qspi.h.

◆ wr_buf

void* wr_buf

Buffer with data to write

Definition at line 168 of file ald_qspi.h.

◆ wr_len

uint32_t wr_len

Number of Write Data Bytes

Definition at line 161 of file ald_qspi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_qspi.h


ALD User Manual: qspi_init_t Struct Reference

Data Fields
qspi_init_t Struct Reference
EASTSOFT ES32F3xx ALD » QSPI » QSPI Public Types

QSPI base initialization structure. More...

#include <ald_qspi.h>

Data Fields

qspi_clk_div_t clkdiv
type_func_t wrppin
qspi_nss_decode_t nssdcode
qspi_nss_t chipsel
qspi_cpol_t cpol
qspi_cpha_t chpa

Detailed Description

QSPI base initialization structure.

Definition at line 174 of file ald_qspi.h.

Field Documentation

◆ chipsel

qspi_nss_t chipsel

QSPI Peripheral Select Line

Definition at line 178 of file ald_qspi.h.

◆ chpa

qspi_cpha_t chpa

QSPI phase

Definition at line 180 of file ald_qspi.h.

◆ clkdiv

qspi_clk_div_t clkdiv

QSPI Baud Rate Clock Prescaler

Definition at line 175 of file ald_qspi.h.

◆ cpol

qspi_cpol_t cpol

QSPI polarity

Definition at line 179 of file ald_qspi.h.

◆ nssdcode

qspi_nss_decode_t nssdcode

QSPI Peripheral Select Decode

Definition at line 177 of file ald_qspi.h.

◆ wrppin

type_func_t wrppin

QSPI Set Write Protect Pin

Definition at line 176 of file ald_qspi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_qspi.h


ALD User Manual: qspi_legacy_cfg_t Struct Reference

Data Fields
qspi_legacy_cfg_t Struct Reference
EASTSOFT ES32F3xx ALD » QSPI » QSPI Public Types

QSPI legacy initialization structure. More...

#include <ald_qspi.h>

Data Fields

uint8_t | tx_thrd
uint8_t | rx_thrd

Detailed Description

QSPI legacy initialization structure.

Definition at line 186 of file ald_qspi.h.

Field Documentation

◆ rx_thrd

uint8_t rx_thrd

Rx FIFO threshhold

Definition at line 188 of file ald_qspi.h.

◆ tx_thrd

uint8_t tx_thrd

Tx FIFO threshhold

Definition at line 187 of file ald_qspi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_qspi.h


ALD User Manual: qspi_read_cfg_t Struct Reference

Data Fields
qspi_read_cfg_t Struct Reference
EASTSOFT ES32F3xx ALD » QSPI » QSPI Public Types

QSPI Device Read Instruction Configuration structure. More...

#include <ald_qspi.h>

Data Fields

uint8_t | rdcde
uint8_t | dcyles
uint8_t | mbitval
type_func_t ddrbit
type_func_t modebit
qspi_xfer_t addxfer
qspi_xfer_t datxfer
qspi_xfer_t instxfer

Detailed Description

QSPI Device Read Instruction Configuration structure.

Definition at line 194 of file ald_qspi.h.

Field Documentation

◆ addxfer

qspi_xfer_t addxfer

Transfer type used for address

Definition at line 200 of file ald_qspi.h.

◆ datxfer

qspi_xfer_t datxfer

Transfer type used for data

Definition at line 201 of file ald_qspi.h.

◆ dcyles

uint8_t dcyles

Number of dummy read clock cycles

Definition at line 196 of file ald_qspi.h.

◆ ddrbit

type_func_t ddrbit

Opcode from bit 7 to 0 is compliant with DDR command

Definition at line 198 of file ald_qspi.h.

◆ instxfer

qspi_xfer_t instxfer

Transfer type used for instruction

Definition at line 202 of file ald_qspi.h.

◆ mbitval

uint8_t mbitval

Mode bits,sent to device following the address bytes

Definition at line 197 of file ald_qspi.h.

◆ modebit

type_func_t modebit

Enable mode bit

Definition at line 199 of file ald_qspi.h.

◆ rdcde

uint8_t rdcde

Read opcode in non-xip mode

Definition at line 195 of file ald_qspi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_qspi.h


ALD User Manual: qspi_write_cfg_t Struct Reference

Data Fields
qspi_write_cfg_t Struct Reference
EASTSOFT ES32F3xx ALD » QSPI » QSPI Public Types

QSPI Device Write Instruction Configuration structure. More...

#include <ald_qspi.h>

Data Fields

uint8_t | wrcde
uint8_t | dcyles
qspi_xfer_t addxfer
qspi_xfer_t datxfer
qspi_xfer_t instxfer
type_func_t autowel

Detailed Description

QSPI Device Write Instruction Configuration structure.

Definition at line 208 of file ald_qspi.h.

Field Documentation

◆ addxfer

qspi_xfer_t addxfer

Transfer type used for address

Definition at line 211 of file ald_qspi.h.

◆ autowel

type_func_t autowel

Turn off automatic

Definition at line 214 of file ald_qspi.h.

◆ datxfer

qspi_xfer_t datxfer

Transfer type used for data

Definition at line 212 of file ald_qspi.h.

◆ dcyles

uint8_t dcyles

Number of dummy read clock cycles

Definition at line 210 of file ald_qspi.h.

◆ instxfer

qspi_xfer_t instxfer

Transfer type used for instruction

Definition at line 213 of file ald_qspi.h.

◆ wrcde

uint8_t wrcde

Write opcode

Definition at line 209 of file ald_qspi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_qspi.h


ALD User Manual: qspi_indac_wr_cfg_t Struct Reference

Data Fields
qspi_indac_wr_cfg_t Struct Reference
EASTSOFT ES32F3xx ALD » QSPI » QSPI Public Types

QSPI Indirect Configuration structure.involatile parameters. More...

#include <ald_qspi.h>

Data Fields

uint32_t | saddr
uint32_t | wrlen

Detailed Description

QSPI Indirect Configuration structure.involatile parameters.

Definition at line 220 of file ald_qspi.h.

Field Documentation

◆ saddr

uint32_t saddr

Flash start address, commence write operation

Definition at line 221 of file ald_qspi.h.

◆ wrlen

uint32_t wrlen

Number of indirect write bytes

Definition at line 222 of file ald_qspi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_qspi.h


ALD User Manual: qspi_indac_rd_cfg_t Struct Reference

Data Fields
qspi_indac_rd_cfg_t Struct Reference
EASTSOFT ES32F3xx ALD » QSPI » QSPI Public Types

#include <ald_qspi.h>

Data Fields

uint32_t | saddr
uint32_t | rdlen

Detailed Description

Definition at line 225 of file ald_qspi.h.

Field Documentation

◆ rdlen

uint32_t rdlen

Number of indirect read bytes

Definition at line 227 of file ald_qspi.h.

◆ saddr

uint32_t saddr

FLASH start address, commence read operation

Definition at line 226 of file ald_qspi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_qspi.h


ALD User Manual: qspi_indac_cfg_t Struct Reference

Data Fields
qspi_indac_cfg_t Struct Reference
EASTSOFT ES32F3xx ALD » QSPI » QSPI Public Types

#include <ald_qspi.h>

Data Fields

uint32_t | srampt
uint32_t | trgaddr
uint32_t | trgrng
uint32_t | wrwmark
uint32_t | rdwmark

Detailed Description

Definition at line 230 of file ald_qspi.h.

Field Documentation

◆ rdwmark

uint32_t rdwmark

Fill level passes watermark, an interrupt generated

Definition at line 235 of file ald_qspi.h.

◆ srampt

uint32_t srampt

Defines the size of the indirect read partion in the SRAM

Definition at line 231 of file ald_qspi.h.

◆ trgaddr

uint32_t trgaddr

Indirect trigger address which is used by AHB controller

Definition at line 232 of file ald_qspi.h.

◆ trgrng

uint32_t trgrng

The offset of indirect trigger address

Definition at line 233 of file ald_qspi.h.

◆ wrwmark

uint32_t wrwmark

Maximum fill level of SRAM before a DMA, 0xFFFFFFFF disable the function

Definition at line 234 of file ald_qspi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_qspi.h


ALD User Manual: qspi_dac_cfg_t Struct Reference

Data Fields
qspi_dac_cfg_t Struct Reference
EASTSOFT ES32F3xx ALD » QSPI » QSPI Public Types

QSPI DAC configuration. More...

#include <ald_qspi.h>

Collaboration diagram for qspi_dac_cfg_t:
[legend]

Data Fields

type_func_t dtrprtcol
type_func_t ahbdecoder
type_func_t xipimmed
type_func_t xipnextrd
type_func_t addrremap
uint32_t remapaddr
type_func_t dmaperh
qspi_read_cfg_t rdinit
qspi_write_cfg_t wrinit

Detailed Description

QSPI DAC configuration.

Definition at line 241 of file ald_qspi.h.

Field Documentation

◆ addrremap

type_func_t addrremap

Enable AHB address re-mapping

Definition at line 246 of file ald_qspi.h.

◆ ahbdecoder

type_func_t ahbdecoder

AHB decoder, direct access mode only

Definition at line 243 of file ald_qspi.h.

◆ dmaperh

type_func_t dmaperh

QSPI dma interface

Definition at line 248 of file ald_qspi.h.

◆ dtrprtcol

type_func_t dtrprtcol

DTR protocol

Definition at line 242 of file ald_qspi.h.

◆ rdinit

qspi_read_cfg_t rdinit

QSPI read instruction configuration

Definition at line 249 of file ald_qspi.h.

◆ remapaddr

uint32_t remapaddr

Remap incoming AHB address to different address

Definition at line 247 of file ald_qspi.h.

◆ wrinit

qspi_write_cfg_t wrinit

QSPI write instruction configuration

Definition at line 250 of file ald_qspi.h.

◆ xipimmed

type_func_t xipimmed

QSPI Enter XIP Immediately

Definition at line 244 of file ald_qspi.h.

◆ xipnextrd

type_func_t xipnextrd

QSPI Enter XIP Next Read

Definition at line 245 of file ald_qspi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_qspi.h


ALD User Manual: qspi_handle_t Struct Reference

Data Fields
qspi_handle_t Struct Reference
EASTSOFT ES32F3xx ALD » QSPI » QSPI Public Types

QSPI Handle Structure definition. More...

#include <ald_qspi.h>

Collaboration diagram for qspi_handle_t:
[legend]

Data Fields

QSPI_TypeDef * | perh
qspi_init_t init
uint8_t * | tx_buf
uint16_t | tx_size
uint16_t | tx_cnt
uint8_t * | rx_buf
uint16_t | rx_size
uint16_t | rx_cnt
dma_handle_t hdma
qspi_state_t state
__IO lock_state_t | lock

Detailed Description

QSPI Handle Structure definition.

Definition at line 256 of file ald_qspi.h.

Field Documentation

◆ hdma

dma_handle_t hdma

QSPI Rx/Tx DMA Handle parameters

Definition at line 266 of file ald_qspi.h.

◆ init

qspi_init_t init

QSPI communication parameters

Definition at line 258 of file ald_qspi.h.

◆ lock

__IO lock_state_t lock

Locking object

Definition at line 269 of file ald_qspi.h.

◆ perh

QSPI_TypeDef* perh

QSPI registers base address

Definition at line 257 of file ald_qspi.h.

◆ rx_buf

uint8_t* rx_buf

Pointer to QSPI receive buffer

Definition at line 262 of file ald_qspi.h.

◆ rx_cnt

uint16_t rx_cnt

QSPI receive counter

Definition at line 264 of file ald_qspi.h.

◆ rx_size

uint16_t rx_size

QSPI receive size

Definition at line 263 of file ald_qspi.h.

◆ state

qspi_state_t state

QSPI communication state

Definition at line 268 of file ald_qspi.h.

◆ tx_buf

uint8_t* tx_buf

Pointer to QSPI transfer buffer

Definition at line 259 of file ald_qspi.h.

◆ tx_cnt

uint16_t tx_cnt

QSPI transfer counter

Definition at line 261 of file ald_qspi.h.

◆ tx_size

uint16_t tx_size

QSPI transfer size

Definition at line 260 of file ald_qspi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_qspi.h


ALD User Manual: qspi_dly_cfg_t Struct Reference

Data Fields
qspi_dly_cfg_t Struct Reference
EASTSOFT ES32F3xx ALD » QSPI » QSPI Public Types

Defines command to be executed using STIG mechanism. More...

#include <ald_qspi.h>

Data Fields

uint32_t | ccsot
uint32_t | cseot
uint32_t | csdads
uint32_t | csda

Detailed Description

Defines command to be executed using STIG mechanism.

Definition at line 275 of file ald_qspi.h.

Field Documentation

◆ ccsot

uint32_t ccsot

range [0 ~ 255]

Definition at line 276 of file ald_qspi.h.

◆ csda

uint32_t csda

range [0 ~ 255]

Definition at line 279 of file ald_qspi.h.

◆ csdads

uint32_t csdads

range [0 ~ 255]

Definition at line 278 of file ald_qspi.h.

◆ cseot

uint32_t cseot

range [0 ~ 255]

Definition at line 277 of file ald_qspi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_qspi.h


ALD User Manual: qspi_data_capture_cfg_t Struct Reference

Data Fields
qspi_data_capture_cfg_t Struct Reference
EASTSOFT ES32F3xx ALD » QSPI » QSPI Public Types

QSPI Read Data Capture Configuration. More...

#include <ald_qspi.h>

Data Fields

uint32_t | dlytd
uint32_t | dlydcl
type_func_t bypsalcc
qspi_data_sampled_t smpledge

Detailed Description

QSPI Read Data Capture Configuration.

Definition at line 285 of file ald_qspi.h.

Field Documentation

◆ bypsalcc

type_func_t bypsalcc

Bypass of the adapted loopback clock circuit type_func_t

Definition at line 288 of file ald_qspi.h.

◆ dlydcl

uint32_t dlydcl

Delay the read data capturing logic [0 ~ 15]

Definition at line 287 of file ald_qspi.h.

◆ dlytd

uint32_t dlytd

Delay transmitted data [0 ~ 15]

Definition at line 286 of file ald_qspi.h.

◆ smpledge

qspi_data_sampled_t smpledge

Sample edge selection(of the flash data outputs) qspi_data_sampled_t

Definition at line 289 of file ald_qspi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_qspi.h


ALD User Manual: qspi_auto_poll_t Struct Reference

Data Fields
qspi_auto_poll_t Struct Reference
EASTSOFT ES32F3xx ALD » QSPI » QSPI Public Types

QSPI Auto Poll Configuration Struction. More...

#include <ald_qspi.h>

Data Fields

uint32_t | opcode
uint32_t | indx
uint32_t | polarity
uint32_t | validcnt
uint32_t | repdly
uint32_t | polexpcnt

Detailed Description

QSPI Auto Poll Configuration Struction.

Definition at line 311 of file ald_qspi.h.

Field Documentation

◆ indx

uint32_t indx

Polling bit index

Definition at line 313 of file ald_qspi.h.

◆ opcode

uint32_t opcode

Automatically poll operation code

Definition at line 312 of file ald_qspi.h.

◆ polarity

uint32_t polarity

Defines polling polarity

Definition at line 314 of file ald_qspi.h.

◆ polexpcnt

uint32_t polexpcnt

Poll cycles,which polling expiration interrupt is generated

Definition at line 317 of file ald_qspi.h.

◆ repdly

uint32_t repdly

Defines additional delay for maintain de-assert during auto-polling phase

Definition at line 316 of file ald_qspi.h.

◆ validcnt

uint32_t validcnt

Expect true result times

Definition at line 315 of file ald_qspi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_qspi.h


ALD User Manual: QSPI Private Macros

Macros
QSPI Private Macros
EASTSOFT ES32F3xx ALD » QSPI
Collaboration diagram for QSPI Private Macros:

Macros

#define | IS_QSPI_SRAM_PARTITION(x) ((x) < 255)
#define | IS_QSPI_INDIRECT_TRIGGER_RANGE(x) (((x) < 16))
#define | IS_QSPI_INDIRECT_READ_WATERMARK(x) ((x) < 512)
#define | IS_QSPI_INDIRECT_SRAM_FILL_TYPE(x) (((x) == QSPI_SRAM_RD) || ((x) == QSPI_SRAM_WR))
#define | IS_QSPI_INDIRECT_READ_STATUS(x) (((x) == QSPI_INDRD_PROGRESS) || ((x) == QSPI_RD_CPLT))
#define | IS_QSPI_INDIRECT_WRITE_STATUS(x) (((x) == QSPI_INDWR_PROGRESS) || ((x) == QSPI_INDWR_CPLT))
#define | IS_QSPI_DEVICE_DELAY_CCSOT(x) ((x) < 256)
#define | IS_QSPI_DEVICE_DELAY_CSEOT(x) ((x) < 256)
#define | IS_QSPI_DEVICE_DELAY_CSDADS(x) ((x) < 256)
#define | IS_QSPI_DEVICE_DELAY_CSDA(x) ((x) < 256)
#define | IS_QSPI_READ_DATA_CAPTURE_DELAY_READ(x) ((x) < 16)
#define | IS_QSPI_READ_DATA_SAMPLE_EDGE(x)
#define | IS_QSPI_READ_DATA_DELAY_TRANSMIT(x) ((x) < 16)
#define | IS_QSPI_ALL(x) ((x) == QSPI)
#define | IS_QSPI_DCYLES(x) ((x) <= 31)
#define | IS_QSPI_ADDR_SIZE(x) ((x) <= 15)
#define | IS_QSPI_PAGE_SIZE(x) ((x) <= 0xfff)
#define | IS_QSPI_BLOCK_SIZE(x) ((x) <= 0x1f)
#define | IS_QSPI_NSS_SIZE(x) ((x) <= 3)
#define | IS_QSPI_XFER_TYPE(x)
#define | IS_QSPI_DDR_BIT_ENABLE(x)
#define | IS_QSPI_MODE_BIT_ENABLE(x)
#define | IS_QSPI_RD_OPCODE(x) (((x) < 0xFF))
#define | IS_QSPI_WR_OPCODE(x) (((x) < 0xFF))
#define | IS_QSPI_CLOCK_PRESCALER(x)
#define | IS_QSPI_CLOCK_PHASE(x)
#define | IS_QSPI_CLOCK_POLARITY(x)
#define | IS_QSPI_IF(x)
#define | IS_QSPI_IT(x)

Detailed Description

Macro Definition Documentation

◆ IS_QSPI_ADDR_SIZE

#define IS_QSPI_ADDR_SIZE ( x ) ((x) <= 15)

Definition at line 383 of file ald_qspi.h.

◆ IS_QSPI_ALL

#define IS_QSPI_ALL ( x ) ((x) == QSPI)

Definition at line 380 of file ald_qspi.h.

◆ IS_QSPI_BLOCK_SIZE

#define IS_QSPI_BLOCK_SIZE ( x ) ((x) <= 0x1f)

Definition at line 385 of file ald_qspi.h.

◆ IS_QSPI_CLOCK_PHASE

#define IS_QSPI_CLOCK_PHASE ( x )
Value:
(((x) == QSPI_CPHA_1E) || \
((x) == QSPI_CPHA_2E))
QSPI_CPHA_1E
Definition: ald_qspi.h:63
QSPI_CPHA_2E
Definition: ald_qspi.h:64

Definition at line 413 of file ald_qspi.h.

◆ IS_QSPI_CLOCK_POLARITY

#define IS_QSPI_CLOCK_POLARITY ( x )
Value:
(((x) == QSPI_CPOL_L) || \
((x) == QSPI_CPOL_H))
QSPI_CPOL_H
Definition: ald_qspi.h:72
QSPI_CPOL_L
Definition: ald_qspi.h:71

Definition at line 415 of file ald_qspi.h.

◆ IS_QSPI_CLOCK_PRESCALER

#define IS_QSPI_CLOCK_PRESCALER ( x )
Value:
(((x) == QSPI_DIV_2) || \
((x) == QSPI_DIV_4) || \
((x) == QSPI_DIV_6) || \
((x) == QSPI_DIV_8) || \
((x) == QSPI_DIV_10) || \
((x) == QSPI_DIV_12) || \
((x) == QSPI_DIV_14) || \
((x) == QSPI_DIV_16) || \
((x) == QSPI_DIV_18) || \
((x) == QSPI_DIV_20) || \
((x) == QSPI_DIV_22) || \
((x) == QSPI_DIV_24) || \
((x) == QSPI_DIV_26) || \
((x) == QSPI_DIV_28) || \
((x) == QSPI_DIV_30) || \
((x) == QSPI_DIV_32))
QSPI_DIV_4
Definition: ald_qspi.h:88
QSPI_DIV_10
Definition: ald_qspi.h:91
QSPI_DIV_32
Definition: ald_qspi.h:102
QSPI_DIV_26
Definition: ald_qspi.h:99
QSPI_DIV_30
Definition: ald_qspi.h:101
QSPI_DIV_16
Definition: ald_qspi.h:94
QSPI_DIV_24
Definition: ald_qspi.h:98
QSPI_DIV_12
Definition: ald_qspi.h:92
QSPI_DIV_22
Definition: ald_qspi.h:97
QSPI_DIV_28
Definition: ald_qspi.h:100
QSPI_DIV_14
Definition: ald_qspi.h:93
QSPI_DIV_2
Definition: ald_qspi.h:87
QSPI_DIV_6
Definition: ald_qspi.h:89
QSPI_DIV_8
Definition: ald_qspi.h:90
QSPI_DIV_20
Definition: ald_qspi.h:96
QSPI_DIV_18
Definition: ald_qspi.h:95

Definition at line 397 of file ald_qspi.h.

◆ IS_QSPI_DCYLES

#define IS_QSPI_DCYLES ( x ) ((x) <= 31)

Definition at line 381 of file ald_qspi.h.

◆ IS_QSPI_DDR_BIT_ENABLE

#define IS_QSPI_DDR_BIT_ENABLE ( x )
Value:
(((x) == QSPI_READ_DDR_BIT_DISABLE) || \
((x) == QSPI_READ_DDR_BIT_ENABLE))

Definition at line 391 of file ald_qspi.h.

◆ IS_QSPI_DEVICE_DELAY_CCSOT

#define IS_QSPI_DEVICE_DELAY_CCSOT ( x ) ((x) < 256)

Definition at line 371 of file ald_qspi.h.

◆ IS_QSPI_DEVICE_DELAY_CSDA

#define IS_QSPI_DEVICE_DELAY_CSDA ( x ) ((x) < 256)

Definition at line 374 of file ald_qspi.h.

◆ IS_QSPI_DEVICE_DELAY_CSDADS

#define IS_QSPI_DEVICE_DELAY_CSDADS ( x ) ((x) < 256)

Definition at line 373 of file ald_qspi.h.

◆ IS_QSPI_DEVICE_DELAY_CSEOT

#define IS_QSPI_DEVICE_DELAY_CSEOT ( x ) ((x) < 256)

Definition at line 372 of file ald_qspi.h.

◆ IS_QSPI_IF

#define IS_QSPI_IF ( x )
Value:
(((x) == QSPI_IF_POLLF) || \
((x) == QSPI_IF_INDRSFF) || \
((x) == QSPI_IF_SRFFF) || \
((x) == QSPI_IF_SRFNEF) || \
((x) == QSPI_IF_STFFF) || \
((x) == QSPI_IF_STFNFF) || \
((x) == QSPI_IF_ROVF) || \
((x) == QSPI_IF_INDTWF) || \
((x) == QSPI_IF_AHBAEF) || \
((x) == QSPI_IF_WPAF) || \
((x) == QSPI_IF_INDRRF) || \
((x) == QSPI_IF_INDCF) || \
((x) == QSPI_IF_UDFF) || \
((x) == QSPI_IF_MODFF))
QSPI_IF_UDFF
Definition: ald_qspi.h:355
QSPI_IF_STFFF
Definition: ald_qspi.h:347
QSPI_IF_POLLF
Definition: ald_qspi.h:343
QSPI_IF_SRFFF
Definition: ald_qspi.h:345
QSPI_IF_INDRRF
Definition: ald_qspi.h:353
QSPI_IF_INDRSFF
Definition: ald_qspi.h:344
QSPI_IF_SRFNEF
Definition: ald_qspi.h:346
QSPI_IF_AHBAEF
Definition: ald_qspi.h:351
QSPI_IF_STFNFF
Definition: ald_qspi.h:348
QSPI_IF_WPAF
Definition: ald_qspi.h:352
QSPI_IF_INDTWF
Definition: ald_qspi.h:350
QSPI_IF_INDCF
Definition: ald_qspi.h:354
QSPI_IF_MODFF
Definition: ald_qspi.h:356
QSPI_IF_ROVF
Definition: ald_qspi.h:349

Definition at line 417 of file ald_qspi.h.

◆ IS_QSPI_INDIRECT_READ_STATUS

#define IS_QSPI_INDIRECT_READ_STATUS ( x ) (((x) == QSPI_INDRD_PROGRESS) || ((x) == QSPI_RD_CPLT))

Definition at line 369 of file ald_qspi.h.

◆ IS_QSPI_INDIRECT_READ_WATERMARK

#define IS_QSPI_INDIRECT_READ_WATERMARK ( x ) ((x) < 512)

Definition at line 367 of file ald_qspi.h.

◆ IS_QSPI_INDIRECT_SRAM_FILL_TYPE

#define IS_QSPI_INDIRECT_SRAM_FILL_TYPE ( x ) (((x) == QSPI_SRAM_RD) || ((x) == QSPI_SRAM_WR))

Definition at line 368 of file ald_qspi.h.

◆ IS_QSPI_INDIRECT_TRIGGER_RANGE

#define IS_QSPI_INDIRECT_TRIGGER_RANGE ( x ) (((x) < 16))

Definition at line 366 of file ald_qspi.h.

◆ IS_QSPI_INDIRECT_WRITE_STATUS

#define IS_QSPI_INDIRECT_WRITE_STATUS ( x ) (((x) == QSPI_INDWR_PROGRESS) || ((x) == QSPI_INDWR_CPLT))

Definition at line 370 of file ald_qspi.h.

◆ IS_QSPI_IT

#define IS_QSPI_IT ( x )
Value:
(((x) == QSPI_IT_POLLF) || \
((x) == QSPI_IT_INDRSFF) || \
((x) == QSPI_IT_SRFFF) || \
((x) == QSPI_IT_SRFNEF) || \
((x) == QSPI_IT_STFFF) || \
((x) == QSPI_IT_STFNFF) || \
((x) == QSPI_IT_ROVF) || \
((x) == QSPI_IT_INDTWF) || \
((x) == QSPI_IT_AHBAEF) || \
((x) == QSPI_IT_WPAF) || \
((x) == QSPI_IT_INDRRF) || \
((x) == QSPI_IT_INDCF) || \
((x) == QSPI_IT_UDFF) || \
((x) == QSPI_IT_MODFF))
QSPI_IT_AHBAEF
Definition: ald_qspi.h:332
QSPI_IT_WPAF
Definition: ald_qspi.h:333
QSPI_IT_SRFNEF
Definition: ald_qspi.h:327
QSPI_IT_INDRSFF
Definition: ald_qspi.h:325
QSPI_IT_MODFF
Definition: ald_qspi.h:337
QSPI_IT_STFNFF
Definition: ald_qspi.h:329
QSPI_IT_SRFFF
Definition: ald_qspi.h:326
QSPI_IT_INDRRF
Definition: ald_qspi.h:334
QSPI_IT_STFFF
Definition: ald_qspi.h:328
QSPI_IT_INDTWF
Definition: ald_qspi.h:331
QSPI_IT_ROVF
Definition: ald_qspi.h:330
QSPI_IT_INDCF
Definition: ald_qspi.h:335
QSPI_IT_POLLF
Definition: ald_qspi.h:324
QSPI_IT_UDFF
Definition: ald_qspi.h:336

Definition at line 431 of file ald_qspi.h.

◆ IS_QSPI_MODE_BIT_ENABLE

#define IS_QSPI_MODE_BIT_ENABLE ( x )
Value:
(((x) == QSPI_READ_INST_MODE_BIT_DISABLE) || \
((x) == QSPI_READ_INST_MODE_BIT_ENABLE))

Definition at line 393 of file ald_qspi.h.

◆ IS_QSPI_NSS_SIZE

#define IS_QSPI_NSS_SIZE ( x ) ((x) <= 3)

Definition at line 386 of file ald_qspi.h.

◆ IS_QSPI_PAGE_SIZE

#define IS_QSPI_PAGE_SIZE ( x ) ((x) <= 0xfff)

Definition at line 384 of file ald_qspi.h.

◆ IS_QSPI_RD_OPCODE

#define IS_QSPI_RD_OPCODE ( x ) (((x) < 0xFF))

Definition at line 395 of file ald_qspi.h.

◆ IS_QSPI_READ_DATA_CAPTURE_DELAY_READ

#define IS_QSPI_READ_DATA_CAPTURE_DELAY_READ ( x ) ((x) < 16)

Definition at line 376 of file ald_qspi.h.

◆ IS_QSPI_READ_DATA_DELAY_TRANSMIT

#define IS_QSPI_READ_DATA_DELAY_TRANSMIT ( x ) ((x) < 16)

Definition at line 379 of file ald_qspi.h.

◆ IS_QSPI_READ_DATA_SAMPLE_EDGE

#define IS_QSPI_READ_DATA_SAMPLE_EDGE ( x )
Value:
(((x) == QSPI_FALLING_E) || \
((x) == QSPI_RISING_E))
QSPI_RISING_E
Definition: ald_qspi.h:143
QSPI_FALLING_E
Definition: ald_qspi.h:142

Definition at line 377 of file ald_qspi.h.

◆ IS_QSPI_SRAM_PARTITION

#define IS_QSPI_SRAM_PARTITION ( x ) ((x) < 255)

Definition at line 365 of file ald_qspi.h.

◆ IS_QSPI_WR_OPCODE

#define IS_QSPI_WR_OPCODE ( x ) (((x) < 0xFF))

Definition at line 396 of file ald_qspi.h.

◆ IS_QSPI_XFER_TYPE

#define IS_QSPI_XFER_TYPE ( x )
Value:
(((x) == QSPI_XFER_SINGLE) || \
((x) == QSPI_XFER_DUAL) || \
((x) == QSPI_XFER_QUAD))
QSPI_XFER_SINGLE
Definition: ald_qspi.h:46
QSPI_XFER_QUAD
Definition: ald_qspi.h:48
QSPI_XFER_DUAL
Definition: ald_qspi.h:47

Definition at line 388 of file ald_qspi.h.


ALD User Manual: QSPI Public Macros

Macros
QSPI Public Macros
EASTSOFT ES32F3xx ALD » QSPI
Collaboration diagram for QSPI Public Macros:

Macros

#define | QSPI_MEMORY_ADDRESS 0x90000000U
#define | QSPI_SRAM_SIZE 255U
#define | QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5s */
#define | QSPI_SRAM_DEPTH 0xFFU
#define | QSPI_DAC_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_DACEN_MSK)
#define | QSPI_DAC_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_DACEN_MSK)
#define | QSPI_LEGACY_SPI_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_LIMEN_MSK)
#define | QSPI_LEGACY_SPI_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_LIMEN_MSK)
#define | QSPI_WRITE_PROTECT_ENABLE(hperh) SET_BIT((hperh)->perh->WPCR, QSPI_WPCR_WPEN_MSK);
#define | QSPI_WRITE_PROTECT_DISABLE(hperh) CLEAR_BIT((hperh)->perh->WPCR, QSPI_WPCR_WPEN_MSK);
#define | QSPI_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_EN_MSK)
#define | QSPI_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_EN_MSK)
#define | QSPI_AUTO_POLL_ENABLE(hperh) CLEAR_BIT((hperh)->perh->WCR, QSPI_WCR_PDIS_MSK)
#define | QSPI_AUTO_POLL_DISABLE(hperh) SET_BIT((hperh)->perh->WCR, QSPI_WCR_PDIS_MSK)
#define | QSPI_DMA_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_DMAEN_MSK)
#define | QSPI_DMA_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_DMAEN_MSK)
#define | QSPI_CANCEL_INDIRECT_READ(hperh) SET_BIT((hperh)->perh->IRTR, QSPI_IRTR_RDDIS_MSK)

Detailed Description

Macro Definition Documentation

◆ QSPI_AUTO_POLL_DISABLE

#define QSPI_AUTO_POLL_DISABLE ( hperh ) SET_BIT((hperh)->perh->WCR, QSPI_WCR_PDIS_MSK)

Definition at line 467 of file ald_qspi.h.

◆ QSPI_AUTO_POLL_ENABLE

#define QSPI_AUTO_POLL_ENABLE ( hperh ) CLEAR_BIT((hperh)->perh->WCR, QSPI_WCR_PDIS_MSK)

Definition at line 466 of file ald_qspi.h.

◆ QSPI_CANCEL_INDIRECT_READ

#define QSPI_CANCEL_INDIRECT_READ ( hperh ) SET_BIT((hperh)->perh->IRTR, QSPI_IRTR_RDDIS_MSK)

Definition at line 470 of file ald_qspi.h.

◆ QSPI_DAC_DISABLE

#define QSPI_DAC_DISABLE ( hperh ) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_DACEN_MSK)

Definition at line 459 of file ald_qspi.h.

◆ QSPI_DAC_ENABLE

#define QSPI_DAC_ENABLE ( hperh ) SET_BIT((hperh)->perh->CR, QSPI_CR_DACEN_MSK)

Definition at line 458 of file ald_qspi.h.

◆ QSPI_DISABLE

#define QSPI_DISABLE ( hperh ) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_EN_MSK)

Definition at line 465 of file ald_qspi.h.

◆ QSPI_DMA_DISABLE

#define QSPI_DMA_DISABLE ( hperh ) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_DMAEN_MSK)

Definition at line 469 of file ald_qspi.h.

◆ QSPI_DMA_ENABLE

#define QSPI_DMA_ENABLE ( hperh ) SET_BIT((hperh)->perh->CR, QSPI_CR_DMAEN_MSK)

Definition at line 468 of file ald_qspi.h.

◆ QSPI_ENABLE

#define QSPI_ENABLE ( hperh ) SET_BIT((hperh)->perh->CR, QSPI_CR_EN_MSK)

Definition at line 464 of file ald_qspi.h.

◆ QSPI_LEGACY_SPI_DISABLE

#define QSPI_LEGACY_SPI_DISABLE ( hperh ) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_LIMEN_MSK)

Definition at line 461 of file ald_qspi.h.

◆ QSPI_LEGACY_SPI_ENABLE

#define QSPI_LEGACY_SPI_ENABLE ( hperh ) SET_BIT((hperh)->perh->CR, QSPI_CR_LIMEN_MSK)

Definition at line 460 of file ald_qspi.h.

◆ QSPI_MEMORY_ADDRESS

#define QSPI_MEMORY_ADDRESS 0x90000000U

Definition at line 454 of file ald_qspi.h.

◆ QSPI_SRAM_DEPTH

#define QSPI_SRAM_DEPTH 0xFFU

Definition at line 457 of file ald_qspi.h.

◆ QSPI_SRAM_SIZE

#define QSPI_SRAM_SIZE 255U

Definition at line 455 of file ald_qspi.h.

◆ QSPI_TIMEOUT_DEFAULT_VALUE

#define QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5s */

Definition at line 456 of file ald_qspi.h.

◆ QSPI_WRITE_PROTECT_DISABLE

#define QSPI_WRITE_PROTECT_DISABLE ( hperh ) CLEAR_BIT((hperh)->perh->WPCR, QSPI_WPCR_WPEN_MSK);

Definition at line 463 of file ald_qspi.h.

◆ QSPI_WRITE_PROTECT_ENABLE

#define QSPI_WRITE_PROTECT_ENABLE ( hperh ) SET_BIT((hperh)->perh->WPCR, QSPI_WPCR_WPEN_MSK);

Definition at line 462 of file ald_qspi.h.


ALD User Manual: RMU

Modules
RMU
EASTSOFT ES32F3xx ALD

RMU module driver. More...

Collaboration diagram for RMU:

Modules

RMU Public Functions
RMU Public Types
RMU Private Macros

Detailed Description

RMU module driver.


ALD User Manual: RMU Public Functions

Functions
RMU Public Functions
EASTSOFT ES32F3xx ALD » RMU
Collaboration diagram for RMU Public Functions:

Functions

void | ald_rmu_bor_config (rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state)
Configure BOR parameters. More...
uint32_t | ald_rmu_get_reset_status (rmu_state_t state)
Get specified reset status. More...
void | ald_rmu_clear_reset_status (rmu_state_t state)
Clear the specified reset status. More...
void | ald_rmu_reset_periperal (rmu_peripheral_t perh)
Reset peripheral device. More...

Detailed Description

Function Documentation

◆ ald_rmu_bor_config()

void ald_rmu_bor_config | ( | rmu_bor_filter_t | flt,
 |  | rmu_bor_vol_t | vol,
 |  | type_func_t | state
 | ) |  |

Configure BOR parameters.

Parameters
flt | filter time.
vol | The voltage.
state | The new status: ENABLE/DISABLE.
Return values
None

Definition at line 41 of file ald_rmu.c.

42 {
43 assert_param(IS_FUNC_STATE(state));
44
45 SYSCFG_UNLOCK();
46
47 if (state) {
48 assert_param(IS_RMU_BORFLT(flt));
49 assert_param(IS_RMU_BORVOL(vol));
50
51 MODIFY_REG(RMU->CR, RMU_CR_BORFLT_MSK, flt << RMU_CR_BORFLT_POSS);
52 MODIFY_REG(RMU->CR, RMU_CR_BORVS_MSK, vol << RMU_CR_BORVS_POSS);
53 SET_BIT(RMU->CR, RMU_CR_BOREN_MSK);
54 }
55 else {
56 CLEAR_BIT(RMU->CR, RMU_CR_BOREN_MSK);
57 }
58
59 SYSCFG_LOCK();
60 return;
61 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
IS_RMU_BORFLT
#define IS_RMU_BORFLT(x)
Definition: ald_rmu.h:176
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
IS_RMU_BORVOL
#define IS_RMU_BORVOL(x)
Definition: ald_rmu.h:183

◆ ald_rmu_clear_reset_status()

void ald_rmu_clear_reset_status ( rmu_state_t state )

Clear the specified reset status.

Parameters
state Specifies the type of the reset,
Return values
None

Definition at line 86 of file ald_rmu.c.

87 {
88 assert_param(IS_RMU_STATE_CLEAR(state));
89
90 SYSCFG_UNLOCK();
91 WRITE_REG(RMU->CRSTSR, state);
92 SYSCFG_LOCK();
93
94 return;
95 }
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
IS_RMU_STATE_CLEAR
#define IS_RMU_STATE_CLEAR(x)
Definition: ald_rmu.h:212
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39

◆ ald_rmu_get_reset_status()

uint32_t ald_rmu_get_reset_status ( rmu_state_t state )

Get specified reset status.

Parameters
state Speicifies the type of the reset,
Return values
The status.

Definition at line 68 of file ald_rmu.c.

69 {
70 assert_param(IS_RMU_STATE(state));
71
72 if (state == RMU_RST_ALL)
73 return RMU->RSTSR;
74
75 if (READ_BIT(RMU->RSTSR, state))
76 return SET;
77
78 return RESET;
79 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
RESET
Definition: type.h:38
IS_RMU_STATE
#define IS_RMU_STATE(x)
Definition: ald_rmu.h:199
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
RMU_RST_ALL
Definition: ald_rmu.h:88

◆ ald_rmu_reset_periperal()

void ald_rmu_reset_periperal ( rmu_peripheral_t perh )

Reset peripheral device.

Parameters
perh The peripheral device,
Return values
None

Definition at line 101 of file ald_rmu.c.

102 {
103 uint32_t idx, pos;
104
105 assert_param(IS_RMU_PERH(perh));
106
107 idx = ((uint32_t)perh >> 27) & 0x7;
108 pos = perh & ~(0x7 << 27);
109 SYSCFG_UNLOCK();
110
111 switch (idx) {
112 case 0:
113 WRITE_REG(RMU->AHB1RSTR, pos);
114 break;
115
116 case 1:
117 WRITE_REG(RMU->AHB2RSTR, pos);
118 break;
119
120 case 2:
121 WRITE_REG(RMU->APB1RSTR, pos);
122 break;
123
124 case 4:
125 WRITE_REG(RMU->APB2RSTR, pos);
126 break;
127
128 default:
129 break;
130 }
131
132 SYSCFG_LOCK();
133 return;
134 }
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
IS_RMU_PERH
#define IS_RMU_PERH(x)
Definition: ald_rmu.h:224


ALD User Manual: RMU Public Types

Enumerations
RMU Public Types
EASTSOFT ES32F3xx ALD » RMU
Collaboration diagram for RMU Public Types:

Enumerations

enum rmu_bor_filter_t {
RMU_BORFLT_1 = 0x1U, RMU_BORFLT_2 = 0x2U, RMU_BORFLT_3 = 0x3U, RMU_BORFLT_4 = 0x4U,
RMU_BORFLT_5 = 0x5U, RMU_BORFLT_6 = 0x6U, RMU_BORFLT_7 = 0x7U
}
RMU BOR fliter. More...
enum rmu_bor_vol_t {
RMU_VOL_NONE = 0x0U, RMU_VOL_2_0 = 0x1U, RMU_VOL_2_2 = 0x2U, RMU_VOL_2_4 = 0x3U,
RMU_VOL_2_6 = 0x4U, RMU_VOL_2_8 = 0x5U, RMU_VOL_3_0 = 0x6U, RMU_VOL_3_2 = 0x7U,
RMU_VOL_3_4 = 0x8U, RMU_VOL_3_6 = 0x9U, RMU_VOL_3_8 = 0xAU, RMU_VOL_4_0 = 0xBU,
RMU_VOL_4_2 = 0xCU, RMU_VOL_4_4 = 0xDU, RMU_VOL_4_6 = 0xEU, RMU_VOL_4_8 = 0xFU
}
RMU BOR voltage. More...
enum rmu_state_t {
RMU_RST_POR = (1U << 0), RMU_RST_WAKEUP = (1U << 1), RMU_RST_BOR = (1U << 2), RMU_RST_NMRST = (1U << 3),
RMU_RST_IWDT = (1U << 4), RMU_RST_WWDT = (1U << 5), RMU_RST_LOCKUP = (1U << 6), RMU_RST_CHIP = (1U << 7),
RMU_RST_MCU = (1U << 8), RMU_RST_CPU = (1U << 9), RMU_RST_CFG = (1U << 10), RMU_RST_CFGERR = (1U << 16),
RMU_RST_ALL = (0xFFFFFU)
}
RMU reset status. More...
enum rmu_peripheral_t {
RMU_PERH_GPIO = (1U << 0), RMU_PERH_CRC = (1U << 1), RMU_PERH_CALC = (1U << 2), RMU_PERH_CRYPT = (1U << 3),
RMU_PERH_TRNG = (1U << 4), RMU_PERH_PIS = (1U << 5), RMU_PERH_USB = (1U << 10), RMU_PERH_ECC = (1U << 11),
RMU_PERH_CHIP = (1U << 0) | (1U << 27), RMU_PERH_CPU = (1U << 1) | (1U << 27), RMU_PERH_EBI = (1U << 8) | (1U << 27), RMU_PERH_TIMER0 = (1U << 0) | (1U << 28),
RMU_PERH_TIMER1 = (1U << 1) | (1U << 28), RMU_PERH_TIMER2 = (1U << 2) | (1U << 28), RMU_PERH_TIMER3 = (1U << 3) | (1U << 28), RMU_PERH_TIMER4 = (1U << 4) | (1U << 28),
RMU_PERH_TIMER5 = (1U << 5) | (1U << 28), RMU_PERH_TIMER6 = (1U << 6) | (1U << 28), RMU_PERH_TIMER7 = (1U << 7) | (1U << 28), RMU_PERH_UART0 = (1U << 8) | (1U << 28),
RMU_PERH_UART1 = (1U << 9) | (1U << 28), RMU_PERH_UART2 = (1U << 10) | (1U << 28), RMU_PERH_UART3 = (1U << 11) | (1U << 28), RMU_PERH_UART4 = (1U << 12) | (1U << 28),
RMU_PERH_UART5 = (1U << 13) | (1U << 28), RMU_PERH_SPI0 = (1U << 16) | (1U << 28), RMU_PERH_SPI1 = (1U << 17) | (1U << 28), RMU_PERH_SPI2 = (1U << 18) | (1U << 28),
RMU_PERH_I2C0 = (1U << 20) | (1U << 28), RMU_PERH_I2C1 = (1U << 21) | (1U << 28), RMU_PERH_CAN0 = (1U << 24) | (1U << 28), RMU_PERH_QSPI = (1U << 25) | (1U << 28),
RMU_PERH_LPTIM0 = (1U << 0) | (1U << 29), RMU_PERH_LPUART0 = (1U << 2) | (1U << 29), RMU_PERH_ADC0 = (1U << 4) | (1U << 29), RMU_PERH_ADC1 = (1U << 5) | (1U << 29),
RMU_PERH_ACMP0 = (1U << 6) | (1U << 29), RMU_PERH_ACMP1 = (1U << 7) | (1U << 29), RMU_PERH_OPAMP = (1U << 8) | (1U << 29), RMU_PERH_DAC0 = (1U << 9) | (1U << 29),
RMU_PERH_ACMP2 = (1U << 11) | (1U << 29), RMU_PERH_WWDT = (1U << 12) | (1U << 29), RMU_PERH_LCD = (1U << 13) | (1U << 29), RMU_PERH_IWDT = (1U << 14) | (1U << 29),
RMU_PERH_RTC = (1U << 15) | (1U << 29), RMU_PERH_TSENSE = (1U << 16) | (1U << 29), RMU_PERH_BKPC = (1U << 17) | (1U << 29), RMU_PERH_BKPRAM = (1U << 18) | (1U << 29)
}
RMU periperal select bit. More...

Detailed Description

Enumeration Type Documentation

◆ rmu_bor_filter_t

enum rmu_bor_filter_t

RMU BOR fliter.

Enumerator
RMU_BORFLT_1 | 1 cycle
RMU_BORFLT_2 | 2 cycles
RMU_BORFLT_3 | 3 cycles
RMU_BORFLT_4 | 4 cycles
RMU_BORFLT_5 | 5 cycles
RMU_BORFLT_6 | 6 cycles
RMU_BORFLT_7 | 7 cycles

Definition at line 40 of file ald_rmu.h.

40 {
41 RMU_BORFLT_1 = 0x1U,
42 RMU_BORFLT_2 = 0x2U,
43 RMU_BORFLT_3 = 0x3U,
44 RMU_BORFLT_4 = 0x4U,
45 RMU_BORFLT_5 = 0x5U,
46 RMU_BORFLT_6 = 0x6U,
47 RMU_BORFLT_7 = 0x7U,
48 } rmu_bor_filter_t;
RMU_BORFLT_1
Definition: ald_rmu.h:41
RMU_BORFLT_6
Definition: ald_rmu.h:46
RMU_BORFLT_2
Definition: ald_rmu.h:42
RMU_BORFLT_7
Definition: ald_rmu.h:47
RMU_BORFLT_5
Definition: ald_rmu.h:45
RMU_BORFLT_4
Definition: ald_rmu.h:44
rmu_bor_filter_t
rmu_bor_filter_t
RMU BOR fliter.
Definition: ald_rmu.h:40
RMU_BORFLT_3
Definition: ald_rmu.h:43

◆ rmu_bor_vol_t

enum rmu_bor_vol_t

RMU BOR voltage.

Enumerator
RMU_VOL_NONE | Disable
RMU_VOL_2_0 | 2.0V
RMU_VOL_2_2 | 2.2V
RMU_VOL_2_4 | 2.4V
RMU_VOL_2_6 | 2.6V
RMU_VOL_2_8 | 2.8V
RMU_VOL_3_0 | 3.0V
RMU_VOL_3_2 | 3.2V
RMU_VOL_3_4 | 3.4V
RMU_VOL_3_6 | 3.6V
RMU_VOL_3_8 | 3.8V
RMU_VOL_4_0 | 4.0V
RMU_VOL_4_2 | 4.2V
RMU_VOL_4_4 | 4.4V
RMU_VOL_4_6 | 4.6V
RMU_VOL_4_8 | 4.8V

Definition at line 53 of file ald_rmu.h.

53 {
54 RMU_VOL_NONE = 0x0U,
55 RMU_VOL_2_0 = 0x1U,
56 RMU_VOL_2_2 = 0x2U,
57 RMU_VOL_2_4 = 0x3U,
58 RMU_VOL_2_6 = 0x4U,
59 RMU_VOL_2_8 = 0x5U,
60 RMU_VOL_3_0 = 0x6U,
61 RMU_VOL_3_2 = 0x7U,
62 RMU_VOL_3_4 = 0x8U,
63 RMU_VOL_3_6 = 0x9U,
64 RMU_VOL_3_8 = 0xAU,
65 RMU_VOL_4_0 = 0xBU,
66 RMU_VOL_4_2 = 0xCU,
67 RMU_VOL_4_4 = 0xDU,
68 RMU_VOL_4_6 = 0xEU,
69 RMU_VOL_4_8 = 0xFU,
70 } rmu_bor_vol_t;
RMU_VOL_4_0
Definition: ald_rmu.h:65
rmu_bor_vol_t
rmu_bor_vol_t
RMU BOR voltage.
Definition: ald_rmu.h:53
RMU_VOL_4_4
Definition: ald_rmu.h:67
RMU_VOL_4_8
Definition: ald_rmu.h:69
RMU_VOL_2_4
Definition: ald_rmu.h:57
RMU_VOL_NONE
Definition: ald_rmu.h:54
RMU_VOL_2_6
Definition: ald_rmu.h:58
RMU_VOL_4_2
Definition: ald_rmu.h:66
RMU_VOL_2_8
Definition: ald_rmu.h:59
RMU_VOL_3_6
Definition: ald_rmu.h:63
RMU_VOL_3_8
Definition: ald_rmu.h:64
RMU_VOL_3_0
Definition: ald_rmu.h:60
RMU_VOL_2_2
Definition: ald_rmu.h:56
RMU_VOL_4_6
Definition: ald_rmu.h:68
RMU_VOL_2_0
Definition: ald_rmu.h:55
RMU_VOL_3_4
Definition: ald_rmu.h:62
RMU_VOL_3_2
Definition: ald_rmu.h:61

◆ rmu_peripheral_t

enum rmu_peripheral_t

RMU periperal select bit.

  In this module, for the convenience of code maintenance,
  TIMERx is used to indicate the sequence of the timer peripheral.
  Different product series TIMERx represent different meanings:
  1. For ES32F36xx series:
  TIMER0 ----> AD16C4T0
  TIMER1 ----> AD16C4T1
  TIMER2 ----> GP32C4T0
  TIMER3 ----> GP32C4T1
  TIMER4 ----> BS16T0
  TIMER5 ----> BS16T1
  TIMER6 ----> GP16C4T0
  TIMER7 ----> GP16C4T1

  2. For ES32F393x/ES32F336x/ES32F392x series:
  TIMER0 ----> GP16C4T0
  TIMER1 ----> GP16C4T1
  TIMER2 ----> GP32C4T0
  TIMER3 ----> GP32C4T1
  TIMER4 ----> BS16T0
  TIMER5 ----> BS16T1
  TIMER6 ----> GP16C4T2
  TIMER7 ----> GP16C4T3

Enumerator
RMU_PERH_GPIO | AHB1: GPIO
RMU_PERH_CRC | AHB1: CRC
RMU_PERH_CALC | AHB1: CALC
RMU_PERH_CRYPT | AHB1: CRYPT
RMU_PERH_TRNG | AHB1: TRNG
RMU_PERH_PIS | AHB1: PIS
RMU_PERH_USB | AHB1: USB
RMU_PERH_ECC | AHB1: ECC
RMU_PERH_CHIP | AHB2: CHIP
RMU_PERH_CPU | AHB2: CPU
RMU_PERH_EBI | AHB2: EBI
RMU_PERH_TIMER0 | APB1: TIMER0
RMU_PERH_TIMER1 | APB1: TIMER1
RMU_PERH_TIMER2 | APB1: TIMER2
RMU_PERH_TIMER3 | APB1: TIMER3
RMU_PERH_TIMER4 | APB1: TIMER4
RMU_PERH_TIMER5 | APB1: TIMER5
RMU_PERH_TIMER6 | APB1: TIMER6
RMU_PERH_TIMER7 | APB1: TIMER7
RMU_PERH_UART0 | APB1: UART0
RMU_PERH_UART1 | APB1: UART1
RMU_PERH_UART2 | APB1: UART2
RMU_PERH_UART3 | APB1: UART3
RMU_PERH_UART4 | APB1: UART4
RMU_PERH_UART5 | APB1: UART5
RMU_PERH_SPI0 | APB1: SPI0
RMU_PERH_SPI1 | APB1: SPI1
RMU_PERH_SPI2 | APB1: SPI2
RMU_PERH_I2C0 | APB1: I2C0
RMU_PERH_I2C1 | APB1: I2C1
RMU_PERH_CAN0 | APB1: CAN0
RMU_PERH_QSPI | APB1: QSPI
RMU_PERH_LPTIM0 | APB2: LPTIM0
RMU_PERH_LPUART0 | APB2: LPUART
RMU_PERH_ADC0 | APB2: ADC0
RMU_PERH_ADC1 | APB2: ADC1
RMU_PERH_ACMP0 | APB2: ACMP0
RMU_PERH_ACMP1 | APB2: ACMP1
RMU_PERH_OPAMP | APB2: OPAMP
RMU_PERH_DAC0 | APB2: DAC0
RMU_PERH_ACMP2 | APB2: WWDT
RMU_PERH_WWDT | APB2: WWDT
RMU_PERH_LCD | APB2: LCD
RMU_PERH_IWDT | APB2: IWDT
RMU_PERH_RTC | APB2: RTC
RMU_PERH_TSENSE | APB2: TSENSE
RMU_PERH_BKPC | APB2: BKPC
RMU_PERH_BKPRAM | APB2: BKPRAM

Definition at line 118 of file ald_rmu.h.

118 {
119 RMU_PERH_GPIO = (1U << 0),
120 RMU_PERH_CRC = (1U << 1),
121 RMU_PERH_CALC = (1U << 2),
122 RMU_PERH_CRYPT = (1U << 3),
123 RMU_PERH_TRNG = (1U << 4),
124 RMU_PERH_PIS = (1U << 5),
125 RMU_PERH_USB = (1U << 10),
126 RMU_PERH_ECC = (1U << 11),
127 RMU_PERH_CHIP = (1U << 0) | (1U << 27),
128 RMU_PERH_CPU = (1U << 1) | (1U << 27),
129 RMU_PERH_EBI = (1U << 8) | (1U << 27),
130 RMU_PERH_TIMER0 = (1U << 0) | (1U << 28),
131 RMU_PERH_TIMER1 = (1U << 1) | (1U << 28),
132 RMU_PERH_TIMER2 = (1U << 2) | (1U << 28),
133 RMU_PERH_TIMER3 = (1U << 3) | (1U << 28),
134 RMU_PERH_TIMER4 = (1U << 4) | (1U << 28),
135 RMU_PERH_TIMER5 = (1U << 5) | (1U << 28),
136 RMU_PERH_TIMER6 = (1U << 6) | (1U << 28),
137 RMU_PERH_TIMER7 = (1U << 7) | (1U << 28),
138 RMU_PERH_UART0 = (1U << 8) | (1U << 28),
139 RMU_PERH_UART1 = (1U << 9) | (1U << 28),
140 RMU_PERH_UART2 = (1U << 10) | (1U << 28),
141 RMU_PERH_UART3 = (1U << 11) | (1U << 28),
142 RMU_PERH_UART4 = (1U << 12) | (1U << 28),
143 RMU_PERH_UART5 = (1U << 13) | (1U << 28),
144 RMU_PERH_SPI0 = (1U << 16) | (1U << 28),
145 RMU_PERH_SPI1 = (1U << 17) | (1U << 28),
146 RMU_PERH_SPI2 = (1U << 18) | (1U << 28),
147 RMU_PERH_I2C0 = (1U << 20) | (1U << 28),
148 RMU_PERH_I2C1 = (1U << 21) | (1U << 28),
149 RMU_PERH_CAN0 = (1U << 24) | (1U << 28),
150 RMU_PERH_QSPI = (1U << 25) | (1U << 28),
151 RMU_PERH_LPTIM0 = (1U << 0) | (1U << 29),
152 RMU_PERH_LPUART0 = (1U << 2) | (1U << 29),
153 RMU_PERH_ADC0 = (1U << 4) | (1U << 29),
154 RMU_PERH_ADC1 = (1U << 5) | (1U << 29),
155 RMU_PERH_ACMP0 = (1U << 6) | (1U << 29),
156 RMU_PERH_ACMP1 = (1U << 7) | (1U << 29),
157 RMU_PERH_OPAMP = (1U << 8) | (1U << 29),
158 RMU_PERH_DAC0 = (1U << 9) | (1U << 29),
159 RMU_PERH_ACMP2 = (1U << 11) | (1U << 29),
160 RMU_PERH_WWDT = (1U << 12) | (1U << 29),
161 RMU_PERH_LCD = (1U << 13) | (1U << 29),
162 RMU_PERH_IWDT = (1U << 14) | (1U << 29),
163 RMU_PERH_RTC = (1U << 15) | (1U << 29),
164 RMU_PERH_TSENSE = (1U << 16) | (1U << 29),
165 RMU_PERH_BKPC = (1U << 17) | (1U << 29),
166 RMU_PERH_BKPRAM = (1U << 18) | (1U << 29),
167 } rmu_peripheral_t;
RMU_PERH_LPTIM0
Definition: ald_rmu.h:151
RMU_PERH_CAN0
Definition: ald_rmu.h:149
RMU_PERH_ECC
Definition: ald_rmu.h:126
RMU_PERH_CRYPT
Definition: ald_rmu.h:122
RMU_PERH_I2C1
Definition: ald_rmu.h:148
RMU_PERH_SPI1
Definition: ald_rmu.h:145
RMU_PERH_ACMP2
Definition: ald_rmu.h:159
RMU_PERH_TIMER4
Definition: ald_rmu.h:134
RMU_PERH_TRNG
Definition: ald_rmu.h:123
RMU_PERH_EBI
Definition: ald_rmu.h:129
RMU_PERH_CPU
Definition: ald_rmu.h:128
RMU_PERH_ADC1
Definition: ald_rmu.h:154
RMU_PERH_LCD
Definition: ald_rmu.h:161
RMU_PERH_DAC0
Definition: ald_rmu.h:158
RMU_PERH_ACMP1
Definition: ald_rmu.h:156
rmu_peripheral_t
rmu_peripheral_t
RMU periperal select bit.
Definition: ald_rmu.h:118
RMU_PERH_UART3
Definition: ald_rmu.h:141
RMU_PERH_UART2
Definition: ald_rmu.h:140
RMU_PERH_OPAMP
Definition: ald_rmu.h:157
RMU_PERH_BKPRAM
Definition: ald_rmu.h:166
RMU_PERH_UART5
Definition: ald_rmu.h:143
RMU_PERH_GPIO
Definition: ald_rmu.h:119
RMU_PERH_TIMER1
Definition: ald_rmu.h:131
RMU_PERH_CALC
Definition: ald_rmu.h:121
RMU_PERH_SPI2
Definition: ald_rmu.h:146
RMU_PERH_TIMER6
Definition: ald_rmu.h:136
RMU_PERH_IWDT
Definition: ald_rmu.h:162
RMU_PERH_UART0
Definition: ald_rmu.h:138
RMU_PERH_ACMP0
Definition: ald_rmu.h:155
RMU_PERH_UART1
Definition: ald_rmu.h:139
RMU_PERH_TIMER5
Definition: ald_rmu.h:135
RMU_PERH_RTC
Definition: ald_rmu.h:163
RMU_PERH_I2C0
Definition: ald_rmu.h:147
RMU_PERH_TIMER2
Definition: ald_rmu.h:132
RMU_PERH_PIS
Definition: ald_rmu.h:124
RMU_PERH_TIMER7
Definition: ald_rmu.h:137
RMU_PERH_TSENSE
Definition: ald_rmu.h:164
RMU_PERH_BKPC
Definition: ald_rmu.h:165
RMU_PERH_UART4
Definition: ald_rmu.h:142
RMU_PERH_TIMER0
Definition: ald_rmu.h:130
RMU_PERH_USB
Definition: ald_rmu.h:125
RMU_PERH_WWDT
Definition: ald_rmu.h:160
RMU_PERH_ADC0
Definition: ald_rmu.h:153
RMU_PERH_CRC
Definition: ald_rmu.h:120
RMU_PERH_TIMER3
Definition: ald_rmu.h:133
RMU_PERH_QSPI
Definition: ald_rmu.h:150
RMU_PERH_CHIP
Definition: ald_rmu.h:127
RMU_PERH_SPI0
Definition: ald_rmu.h:144
RMU_PERH_LPUART0
Definition: ald_rmu.h:152

◆ rmu_state_t

enum rmu_state_t

RMU reset status.

Enumerator
RMU_RST_POR | POR
RMU_RST_WAKEUP | WAKEUP
RMU_RST_BOR | BOR
RMU_RST_NMRST | NMRST
RMU_RST_IWDT | IWDT
RMU_RST_WWDT | WWDT
RMU_RST_LOCKUP | LOCKUP
RMU_RST_CHIP | CHIP
RMU_RST_MCU | MCU
RMU_RST_CPU | CPU
RMU_RST_CFG | CFG
RMU_RST_CFGERR | CFG Error
RMU_RST_ALL | ALL

Definition at line 75 of file ald_rmu.h.

75 {
76 RMU_RST_POR = (1U << 0),
77 RMU_RST_WAKEUP = (1U << 1),
78 RMU_RST_BOR = (1U << 2),
79 RMU_RST_NMRST = (1U << 3),
80 RMU_RST_IWDT = (1U << 4),
81 RMU_RST_WWDT = (1U << 5),
82 RMU_RST_LOCKUP = (1U << 6),
83 RMU_RST_CHIP = (1U << 7),
84 RMU_RST_MCU = (1U << 8),
85 RMU_RST_CPU = (1U << 9),
86 RMU_RST_CFG = (1U << 10),
87 RMU_RST_CFGERR = (1U << 16),
88 RMU_RST_ALL = (0xFFFFFU),
89 } rmu_state_t;
RMU_RST_BOR
Definition: ald_rmu.h:78
RMU_RST_CPU
Definition: ald_rmu.h:85
RMU_RST_NMRST
Definition: ald_rmu.h:79
RMU_RST_CFG
Definition: ald_rmu.h:86
RMU_RST_WAKEUP
Definition: ald_rmu.h:77
rmu_state_t
rmu_state_t
RMU reset status.
Definition: ald_rmu.h:75
RMU_RST_IWDT
Definition: ald_rmu.h:80
RMU_RST_CHIP
Definition: ald_rmu.h:83
RMU_RST_MCU
Definition: ald_rmu.h:84
RMU_RST_POR
Definition: ald_rmu.h:76
RMU_RST_CFGERR
Definition: ald_rmu.h:87
RMU_RST_LOCKUP
Definition: ald_rmu.h:82
RMU_RST_WWDT
Definition: ald_rmu.h:81
RMU_RST_ALL
Definition: ald_rmu.h:88


ALD User Manual: RMU Private Macros

Macros
RMU Private Macros
EASTSOFT ES32F3xx ALD » RMU
Collaboration diagram for RMU Private Macros:

Macros

#define | IS_RMU_BORFLT(x)
#define | IS_RMU_BORVOL(x)
#define | IS_RMU_STATE(x)
#define | IS_RMU_STATE_CLEAR(x)
#define | IS_RMU_PERH(x)

Detailed Description

Macro Definition Documentation

◆ IS_RMU_BORFLT

#define IS_RMU_BORFLT ( x )
Value:
(((x) == RMU_BORFLT_1) || \
((x) == RMU_BORFLT_2) || \
((x) == RMU_BORFLT_3) || \
((x) == RMU_BORFLT_4) || \
((x) == RMU_BORFLT_5) || \
((x) == RMU_BORFLT_6) || \
((x) == RMU_BORFLT_7))
RMU_BORFLT_1
Definition: ald_rmu.h:41
RMU_BORFLT_6
Definition: ald_rmu.h:46
RMU_BORFLT_2
Definition: ald_rmu.h:42
RMU_BORFLT_7
Definition: ald_rmu.h:47
RMU_BORFLT_5
Definition: ald_rmu.h:45
RMU_BORFLT_4
Definition: ald_rmu.h:44
RMU_BORFLT_3
Definition: ald_rmu.h:43

Definition at line 176 of file ald_rmu.h.

◆ IS_RMU_BORVOL

#define IS_RMU_BORVOL ( x )
Value:
(((x) == RMU_VOL_NONE) || \
((x) == RMU_VOL_2_0) || \
((x) == RMU_VOL_2_2) || \
((x) == RMU_VOL_2_4) || \
((x) == RMU_VOL_2_6) || \
((x) == RMU_VOL_2_8) || \
((x) == RMU_VOL_3_0) || \
((x) == RMU_VOL_3_2) || \
((x) == RMU_VOL_3_4) || \
((x) == RMU_VOL_3_6) || \
((x) == RMU_VOL_3_8) || \
((x) == RMU_VOL_4_0) || \
((x) == RMU_VOL_4_2) || \
((x) == RMU_VOL_4_4) || \
((x) == RMU_VOL_4_6) || \
((x) == RMU_VOL_4_8))
RMU_VOL_4_0
Definition: ald_rmu.h:65
RMU_VOL_4_4
Definition: ald_rmu.h:67
RMU_VOL_4_8
Definition: ald_rmu.h:69
RMU_VOL_2_4
Definition: ald_rmu.h:57
RMU_VOL_NONE
Definition: ald_rmu.h:54
RMU_VOL_2_6
Definition: ald_rmu.h:58
RMU_VOL_4_2
Definition: ald_rmu.h:66
RMU_VOL_2_8
Definition: ald_rmu.h:59
RMU_VOL_3_6
Definition: ald_rmu.h:63
RMU_VOL_3_8
Definition: ald_rmu.h:64
RMU_VOL_3_0
Definition: ald_rmu.h:60
RMU_VOL_2_2
Definition: ald_rmu.h:56
RMU_VOL_4_6
Definition: ald_rmu.h:68
RMU_VOL_2_0
Definition: ald_rmu.h:55
RMU_VOL_3_4
Definition: ald_rmu.h:62
RMU_VOL_3_2
Definition: ald_rmu.h:61

Definition at line 183 of file ald_rmu.h.

◆ IS_RMU_PERH

#define IS_RMU_PERH ( x )

Definition at line 224 of file ald_rmu.h.

◆ IS_RMU_STATE

#define IS_RMU_STATE ( x )
Value:
(((x) == RMU_RST_POR) || \
((x) == RMU_RST_WAKEUP) || \
((x) == RMU_RST_BOR) || \
((x) == RMU_RST_NMRST) || \
((x) == RMU_RST_IWDT) || \
((x) == RMU_RST_WWDT) || \
((x) == RMU_RST_LOCKUP) || \
((x) == RMU_RST_CHIP) || \
((x) == RMU_RST_MCU) || \
((x) == RMU_RST_CPU) || \
((x) == RMU_RST_CFG) || \
((x) == RMU_RST_CFGERR) || \
((x) == RMU_RST_ALL))
RMU_RST_BOR
Definition: ald_rmu.h:78
RMU_RST_CPU
Definition: ald_rmu.h:85
RMU_RST_NMRST
Definition: ald_rmu.h:79
RMU_RST_CFG
Definition: ald_rmu.h:86
RMU_RST_WAKEUP
Definition: ald_rmu.h:77
RMU_RST_IWDT
Definition: ald_rmu.h:80
RMU_RST_CHIP
Definition: ald_rmu.h:83
RMU_RST_MCU
Definition: ald_rmu.h:84
RMU_RST_POR
Definition: ald_rmu.h:76
RMU_RST_CFGERR
Definition: ald_rmu.h:87
RMU_RST_LOCKUP
Definition: ald_rmu.h:82
RMU_RST_WWDT
Definition: ald_rmu.h:81
RMU_RST_ALL
Definition: ald_rmu.h:88

Definition at line 199 of file ald_rmu.h.

◆ IS_RMU_STATE_CLEAR

#define IS_RMU_STATE_CLEAR ( x )
Value:
(((x) == RMU_RST_POR) || \
((x) == RMU_RST_WAKEUP) || \
((x) == RMU_RST_BOR) || \
((x) == RMU_RST_NMRST) || \
((x) == RMU_RST_IWDT) || \
((x) == RMU_RST_WWDT) || \
((x) == RMU_RST_LOCKUP) || \
((x) == RMU_RST_CHIP) || \
((x) == RMU_RST_MCU) || \
((x) == RMU_RST_CPU) || \
((x) == RMU_RST_CFG) || \
((x) == RMU_RST_ALL))
RMU_RST_BOR
Definition: ald_rmu.h:78
RMU_RST_CPU
Definition: ald_rmu.h:85
RMU_RST_NMRST
Definition: ald_rmu.h:79
RMU_RST_CFG
Definition: ald_rmu.h:86
RMU_RST_WAKEUP
Definition: ald_rmu.h:77
RMU_RST_IWDT
Definition: ald_rmu.h:80
RMU_RST_CHIP
Definition: ald_rmu.h:83
RMU_RST_MCU
Definition: ald_rmu.h:84
RMU_RST_POR
Definition: ald_rmu.h:76
RMU_RST_LOCKUP
Definition: ald_rmu.h:82
RMU_RST_WWDT
Definition: ald_rmu.h:81
RMU_RST_ALL
Definition: ald_rmu.h:88

Definition at line 212 of file ald_rmu.h.


ALD User Manual: RTC

Modules
RTC
EASTSOFT ES32F3xx ALD

RTC module driver. More...

Collaboration diagram for RTC:

Modules

RTC Public Functions
RTC Public Types
RTC Public Macros
CAN Private Macros
RTC Private Functions

Detailed Description

RTC module driver.


ALD User Manual: RTC Public Functions

Modules
RTC Public Functions
EASTSOFT ES32F3xx ALD » RTC
Collaboration diagram for RTC Public Functions:

Modules

Initialization functions
Initialization functions.
Time and Date functions
RTC Time and Date functions.
Alarm functions
RTC alarm functions.
Time stamp functions
RTC time stamp functions.
Tamper functions
RTC tamper functions.
Wake-up functions
RTC wake-up functions.
Clock output functions
RTC clock output functions.
Control functions
RTC control functions.

Detailed Description


ALD User Manual: Initialization functions

Functions
Initialization functions
EASTSOFT ES32F3xx ALD » RTC » RTC Public Functions

Initialization functions. More...

Collaboration diagram for Initialization functions:

Functions

void | ald_rtc_reset (void)
Reset RTC register. More...
void | ald_rtc_init (rtc_init_t *init)
Initialize the RTC module. More...
void | ald_rtc_source_select (rtc_source_sel_t sel)
Configure the RTC source. More...

Detailed Description

Initialization functions.

===============================================================================
             ##### Initialization function #####
===============================================================================
  [..] This section provides functions allowing to initialize and configure the
        RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable
        RTC registers Write protection.
        (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
            It is split into 2 programmable prescalers to minimize power consumption.
            (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler.
            (++) When both prescalers are used, it is recommended to configure the
                asynchronous prescaler to a high value to minimize power consumption.
        (#) All RTC registers are Write protected. Writing to the RTC registers
            is enabled by writing a key into the Write Protection register.

Function Documentation

◆ ald_rtc_init()

void ald_rtc_init ( rtc_init_t * init )

Initialize the RTC module.

Parameters
init Pointer to rtc_init_t structure which contains the configuration parameters.
Return values
None

Definition at line 240 of file ald_rtc.c.

241 {
242 assert_param(IS_RTC_HOUR_FORMAT(init->hour_format));
243 assert_param(IS_RTC_OUTPUT_SEL(init->output));
244 assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity));
245
246 ald_rtc_reset();
247 RTC_UNLOCK();
248
249 MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS);
250 MODIFY_REG(RTC->CON, RTC_CON_EOS_MSK, init->output << RTC_CON_EOS_POSS);
251 MODIFY_REG(RTC->CON, RTC_CON_POL_MSK, init->output_polarity << RTC_CON_POL_POS);
252 MODIFY_REG(RTC->PSR, RTC_PSR_SPRS_MSK, init->synch_pre_div << RTC_PSR_SPRS_POSS);
253 MODIFY_REG(RTC->PSR, RTC_PSR_APRS_MSK, init->asynch_pre_div << RTC_PSR_APRS_POSS);
254 SET_BIT(RTC->CON, RTC_CON_GO_MSK);
255
256 RTC_LOCK();
257 return;
258 }
IS_RTC_OUTPUT_POLARITY
#define IS_RTC_OUTPUT_POLARITY(x)
Definition: ald_rtc.h:435
IS_RTC_HOUR_FORMAT
#define IS_RTC_HOUR_FORMAT(x)
Definition: ald_rtc.h:429
assert_param
#define assert_param(x)
Definition: type.h:88
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
rtc_init_t::hour_format
rtc_hour_format_t hour_format
Definition: ald_rtc.h:68
ald_rtc_reset
void ald_rtc_reset(void)
Reset RTC register.
Definition: ald_rtc.c:220
rtc_init_t::output_polarity
rtc_output_polarity_t output_polarity
Definition: ald_rtc.h:72
rtc_init_t::synch_pre_div
uint32_t synch_pre_div
Definition: ald_rtc.h:70
rtc_init_t::asynch_pre_div
uint32_t asynch_pre_div
Definition: ald_rtc.h:69
rtc_init_t::output
rtc_output_select_t output
Definition: ald_rtc.h:71
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_RTC_OUTPUT_SEL
#define IS_RTC_OUTPUT_SEL(x)
Definition: ald_rtc.h:431

◆ ald_rtc_reset()

void ald_rtc_reset ( void )

Reset RTC register.

Return values
None

Definition at line 220 of file ald_rtc.c.

221 {
222 RTC_UNLOCK();
223
224 WRITE_REG(RTC->CON, 0x0);
225 WRITE_REG(RTC->TAMPCON, 0x0);
226 WRITE_REG(RTC->WUMAT, 0x0);
227 WRITE_REG(RTC->IER, 0x0);
228 WRITE_REG(RTC->IFCR, ~0x0);
229
230 RTC_LOCK();
231 return;
232 }
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72

◆ ald_rtc_source_select()

void ald_rtc_source_select ( rtc_source_sel_t sel )

Configure the RTC source.

Parameters
sel RTC source type.
Return values
None

Definition at line 265 of file ald_rtc.c.

266 {
267 assert_param(IS_RTC_SOURCE_SEL(sel));
268
269 BKPC_UNLOCK();
270 MODIFY_REG(BKPC->PCCR, BKPC_PCCR_RTCCS_MSK, sel << BKPC_PCCR_RTCCS_POSS);
271
272 if (sel == RTC_SOURCE_LOSC) {
273 SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);
274 }
275 else if (sel == RTC_SOURCE_LRC) {
276 SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);
277 }
278 else {
279 ; /* do nothing */
280 }
281
282 BKPC_LOCK();
283 return;
284 }
assert_param
#define assert_param(x)
Definition: type.h:88
RTC_SOURCE_LRC
Definition: ald_rtc.h:80
IS_RTC_SOURCE_SEL
#define IS_RTC_SOURCE_SEL(x)
Definition: ald_rtc.h:437
BKPC_LOCK
#define BKPC_LOCK()
Definition: ald_bkpc.h:38
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
RTC_SOURCE_LOSC
Definition: ald_rtc.h:79
BKPC_UNLOCK
#define BKPC_UNLOCK()
Definition: ald_bkpc.h:39
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74


ALD User Manual: Time and Date functions

Functions
Time and Date functions
EASTSOFT ES32F3xx ALD » RTC » RTC Public Functions

RTC Time and Date functions. More...

Collaboration diagram for Time and Date functions:

Functions

ald_status_t | ald_rtc_set_time (rtc_time_t *time, rtc_format_t format)
Set specified time. More...
ald_status_t | ald_rtc_set_date (rtc_date_t *date, rtc_format_t format)
Set specified date. More...
void | ald_rtc_get_time (rtc_time_t *time, rtc_format_t format)
Get current time. More...
void | ald_rtc_get_date (rtc_date_t *date, rtc_format_t format)
Get current date. More...
int32_t | ald_rtc_get_date_time (rtc_date_t *date, rtc_time_t *time, rtc_format_t format)
Get time and date consistency. More...

Detailed Description

RTC Time and Date functions.

===============================================================================
                ##### Time and Date functions #####
===============================================================================

[..] This section provides functions allowing:
    [#]
      (+) To configure the time use the ald_rtc_set_time() function.
      (+) To configure the date use the ald_rtc_set_date() function.
      (+) To read the time use the ald_rtc_get_time() function.
      (+) To read the date use the ald_rtc_get_date() function.

Function Documentation

◆ ald_rtc_get_date()

void ald_rtc_get_date | ( | rtc_date_t * | date,
 |  | rtc_format_t | format
 | ) |  |

Get current date.

Parameters
date | pointer to a rtc_date_t structure.
format | Data format.
Return values
None

Definition at line 432 of file ald_rtc.c.

433 {
434 uint32_t tmp = RTC->DATE;
435
436 assert_param(date != NULL);
437 assert_param(IS_RTC_FORMAT(format));
438
439 if (format == RTC_FORMAT_DEC) {
440 date->day = bcd_to_dec(tmp & 0x3F);
441 date->month = bcd_to_dec((tmp >> 8) & 0x1F);
442 date->year = bcd_to_dec((tmp >> 16) & 0xFF);
443 date->week = bcd_to_dec((tmp >> 24) & 0x7);
444 }
445 else {
446 date->day = tmp & 0x3F;
447 date->month = (tmp >> 8) & 0x1F;
448 date->year = (tmp >> 16) & 0xFF;
449 date->week = (tmp >> 24) & 0x7;
450 }
451
452 return;
453 }
rtc_date_t::day
uint8_t day
Definition: ald_rtc.h:100
assert_param
#define assert_param(x)
Definition: type.h:88
rtc_date_t::month
uint8_t month
Definition: ald_rtc.h:101
rtc_date_t::week
uint8_t week
Definition: ald_rtc.h:99
RTC_FORMAT_DEC
Definition: ald_rtc.h:109
IS_RTC_FORMAT
#define IS_RTC_FORMAT(x)
Definition: ald_rtc.h:471
bcd_to_dec
static uint32_t bcd_to_dec(uint32_t bcd)
Converts form 2 digit BCD to Binary.
Definition: ald_rtc.c:143
rtc_date_t::year
uint8_t year
Definition: ald_rtc.h:102

◆ ald_rtc_get_date_time()

int32_t ald_rtc_get_date_time | ( | rtc_date_t * | date,
 |  | rtc_time_t * | time,
 |  | rtc_format_t | format
 | ) |  |

Get time and date consistency.

Parameters
date | pointer to a rtc_date_t structure.
time | pointer to a rtc_time_t structure.
format | Data format.
Return values
Status 0 - Consistency -1 - Not consistency

Definition at line 464 of file ald_rtc.c.

465 {
466 int32_t nr = 3;
467 rtc_date_t d_last;
468 rtc_time_t t_last;
469
470 while (nr--) {
471 ald_rtc_get_time(&t_last, format);
472 ald_rtc_get_date(&d_last, format);
473 ald_rtc_get_time(time, format);
474 ald_rtc_get_date(date, format);
475
476 if (rtc_consistency_check(&t_last, &d_last, time, date))
477 return 0;
478 }
479
480 return -1;
481 }
rtc_consistency_check
static int32_t rtc_consistency_check(rtc_time_t *t_last, rtc_date_t *d_last, rtc_time_t *time, rtc_date_t *date)
Time and Date consistency check.
Definition: ald_rtc.c:168
ald_rtc_get_time
void ald_rtc_get_time(rtc_time_t *time, rtc_format_t format)
Get current time.
Definition: ald_rtc.c:402
ald_rtc_get_date
void ald_rtc_get_date(rtc_date_t *date, rtc_format_t format)
Get current date.
Definition: ald_rtc.c:432
rtc_time_t
Time structure.
Definition: ald_rtc.h:88
rtc_date_t
Date structure.
Definition: ald_rtc.h:98

◆ ald_rtc_get_time()

void ald_rtc_get_time | ( | rtc_time_t * | time,
 |  | rtc_format_t | format
 | ) |  |

Get current time.

Parameters
time | pointer to a rtc_time_t structure.
format | Data format.
Return values
None

Definition at line 402 of file ald_rtc.c.

403 {
404 uint32_t tmp;
405
406 assert_param(time != NULL);
407 assert_param(IS_RTC_FORMAT(format));
408
409 time->sub_sec = RTC->SSEC & 0xFFFF;
410 tmp = RTC->TIME;
411
412 if (format == RTC_FORMAT_DEC) {
413 time->second = bcd_to_dec(tmp & 0x7F);
414 time->minute = bcd_to_dec((tmp >> 8) & 0x7F);
415 time->hour = bcd_to_dec((tmp >> 16) & 0x7F);
416 }
417 else {
418 time->second = tmp & 0x7F;
419 time->minute = (tmp >> 8) & 0x7F;
420 time->hour = (tmp >> 16) & 0x7F;
421 }
422
423 return;
424 }
assert_param
#define assert_param(x)
Definition: type.h:88
RTC_FORMAT_DEC
Definition: ald_rtc.h:109
IS_RTC_FORMAT
#define IS_RTC_FORMAT(x)
Definition: ald_rtc.h:471
rtc_time_t::minute
uint8_t minute
Definition: ald_rtc.h:90
rtc_time_t::hour
uint8_t hour
Definition: ald_rtc.h:89
rtc_time_t::second
uint8_t second
Definition: ald_rtc.h:91
bcd_to_dec
static uint32_t bcd_to_dec(uint32_t bcd)
Converts form 2 digit BCD to Binary.
Definition: ald_rtc.c:143
rtc_time_t::sub_sec
uint16_t sub_sec
Definition: ald_rtc.h:92

◆ ald_rtc_set_date()

ald_status_t ald_rtc_set_date | ( | rtc_date_t * | date,
 |  | rtc_format_t | format
 | ) |  |

Set specified date.

Parameters
date | pointer to a rtc_date_t structure.
format | Data format.
Return values
ALD status.

Definition at line 357 of file ald_rtc.c.

358 {
359 uint32_t tmp;
360
361 assert_param(IS_RTC_FORMAT(format));
362
363 if (format == RTC_FORMAT_DEC) {
364 assert_param(IS_RTC_DAY(date->day));
365 assert_param(IS_RTC_MONTH(date->month));
366 assert_param(IS_RTC_YEAR(date->year));
367
368 tmp = (dec_to_bcd(date->day)) |
369 (dec_to_bcd(date->month) << 8) |
370 (dec_to_bcd(date->year) << 16) |
371 (dec_to_bcd(date->week) << 24);
372 }
373 else {
374 assert_param(IS_RTC_DAY(bcd_to_dec(date->day)));
375 assert_param(IS_RTC_MONTH(bcd_to_dec(date->month)));
376 assert_param(IS_RTC_YEAR(bcd_to_dec(date->year)));
377
378 tmp = date->day | (date->month << 8) |
379 (date->year << 16) | (date->week << 24);
380 }
381
382 RTC_UNLOCK();
383 WRITE_REG(RTC->DATE, tmp);
384 RTC_LOCK();
385
386 tmp = ald_get_tick();
387
388 while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) {
389 if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE)
390 return TIMEOUT;
391 }
392
393 return OK;
394 }
rtc_date_t::day
uint8_t day
Definition: ald_rtc.h:100
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
IS_RTC_MONTH
#define IS_RTC_MONTH(x)
Definition: ald_rtc.h:561
rtc_date_t::month
uint8_t month
Definition: ald_rtc.h:101
rtc_date_t::week
uint8_t week
Definition: ald_rtc.h:99
IS_RTC_DAY
#define IS_RTC_DAY(x)
Definition: ald_rtc.h:560
RTC_FORMAT_DEC
Definition: ald_rtc.h:109
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
IS_RTC_FORMAT
#define IS_RTC_FORMAT(x)
Definition: ald_rtc.h:471
dec_to_bcd
static uint32_t dec_to_bcd(uint32_t dec)
Converts a 2 digit decimal to BCD format.
Definition: ald_rtc.c:153
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378
IS_RTC_YEAR
#define IS_RTC_YEAR(x)
Definition: ald_rtc.h:562
bcd_to_dec
static uint32_t bcd_to_dec(uint32_t bcd)
Converts form 2 digit BCD to Binary.
Definition: ald_rtc.c:143
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
rtc_date_t::year
uint8_t year
Definition: ald_rtc.h:102
RTC_TIMEOUT_VALUE
#define RTC_TIMEOUT_VALUE
Definition: ald_rtc.h:426

◆ ald_rtc_set_time()

ald_status_t ald_rtc_set_time | ( | rtc_time_t * | time,
 |  | rtc_format_t | format
 | ) |  |

Set specified time.

Parameters
time | pointer to a rtc_time_t structure.
format | Data format.
Return values
ALD status.

Definition at line 314 of file ald_rtc.c.

315 {
316 uint32_t tmp;
317
318 assert_param(IS_RTC_FORMAT(format));
319
320 if (format == RTC_FORMAT_DEC) {
321 assert_param(IS_RTC_SECOND(time->second));
322 assert_param(IS_RTC_MINUTE(time->minute));
323 assert_param(IS_RTC_HOUR(time->hour));
324
325 tmp = (dec_to_bcd(time->second)) |
326 (dec_to_bcd(time->minute) << 8) |
327 (dec_to_bcd(time->hour) << 16);
328 }
329 else {
330 assert_param(IS_RTC_SECOND(bcd_to_dec(time->second)));
331 assert_param(IS_RTC_MINUTE(bcd_to_dec(time->minute)));
332 assert_param(IS_RTC_HOUR(bcd_to_dec(time->hour)));
333
334 tmp = time->second | (time->minute << 8) | (time->hour << 16);
335 }
336
337 RTC_UNLOCK();
338 WRITE_REG(RTC->TIME, tmp);
339 RTC_LOCK();
340
341 tmp = ald_get_tick();
342
343 while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) {
344 if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE)
345 return TIMEOUT;
346 }
347
348 return OK;
349 }
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
RTC_FORMAT_DEC
Definition: ald_rtc.h:109
IS_RTC_HOUR
#define IS_RTC_HOUR(x)
Definition: ald_rtc.h:559
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
IS_RTC_FORMAT
#define IS_RTC_FORMAT(x)
Definition: ald_rtc.h:471
rtc_time_t::minute
uint8_t minute
Definition: ald_rtc.h:90
dec_to_bcd
static uint32_t dec_to_bcd(uint32_t dec)
Converts a 2 digit decimal to BCD format.
Definition: ald_rtc.c:153
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
rtc_time_t::hour
uint8_t hour
Definition: ald_rtc.h:89
TIMEOUT
Definition: utils.h:58
IS_RTC_SECOND
#define IS_RTC_SECOND(x)
Definition: ald_rtc.h:557
rtc_time_t::second
uint8_t second
Definition: ald_rtc.h:91
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378
bcd_to_dec
static uint32_t bcd_to_dec(uint32_t bcd)
Converts form 2 digit BCD to Binary.
Definition: ald_rtc.c:143
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
RTC_TIMEOUT_VALUE
#define RTC_TIMEOUT_VALUE
Definition: ald_rtc.h:426
IS_RTC_MINUTE
#define IS_RTC_MINUTE(x)
Definition: ald_rtc.h:558


ALD User Manual: Alarm functions

Functions
Alarm functions
EASTSOFT ES32F3xx ALD » RTC » RTC Public Functions

RTC alarm functions. More...

Collaboration diagram for Alarm functions:

Functions

void | ald_rtc_set_alarm (rtc_alarm_t *alarm, rtc_format_t format)
Set alarm. More...
void | ald_rtc_get_alarm (rtc_alarm_t *alarm, rtc_format_t format)
Get alarm parameters. More...

Detailed Description

RTC alarm functions.

===============================================================================
                ##### Alarm functions #####
===============================================================================

[..] This section provides functions allowing:
    [#]
      (+) To configure the alarm use ald_rtc_set_alarm() function
      (+) To read the alarm use ald_rtc_get_alarm() function

Function Documentation

◆ ald_rtc_get_alarm()

void ald_rtc_get_alarm | ( | rtc_alarm_t * | alarm,
 |  | rtc_format_t | format
 | ) |  |

Get alarm parameters.

Parameters
alarm | pointer to rtc_alarm_t struct.
format | Data format.
Return values
None

Definition at line 587 of file ald_rtc.c.

588 {
589 uint8_t week;
590 uint32_t tmp, ss_tmp;
591
592 assert_param(alarm != NULL);
593 assert_param(IS_RTC_FORMAT(format));
594
595 if (alarm->idx == RTC_ALARM_A) {
596 tmp = RTC->ALMA;
597 ss_tmp = RTC->ALMASSEC;
598 }
599 else {
600 tmp = RTC->ALMB;
601 ss_tmp = RTC->ALMBSSEC;
602 }
603
604 if ((tmp >> 31) & 0x1) {
605 alarm->sel = RTC_SELECT_WEEK;
606 week = ((tmp >> 24) & 0x7F);
607
608 switch (week) {
609 case 1:
610 alarm->week = 0;
611 break;
612 case 2:
613 alarm->week = 1;
614 break;
615 case 4:
616 alarm->week = 2;
617 break;
618 case 8:
619 alarm->week = 3;
620 break;
621 case 16:
622 alarm->week = 4;
623 break;
624 case 32:
625 alarm->week = 5;
626 break;
627 case 64:
628 alarm->week = 6;
629 break;
630 default:
631 break;
632 }
633 }
634 else {
635 alarm->sel = RTC_SELECT_DAY;
636
637 if (format == RTC_FORMAT_DEC)
638 alarm->day = bcd_to_dec((tmp >> 24) & 0x3F);
639 else
640 alarm->day = (tmp >> 24) & 0x3F;
641 }
642
643 if (format == RTC_FORMAT_DEC) {
644 alarm->time.second = bcd_to_dec(tmp & 0x7F);
645 alarm->time.minute = bcd_to_dec((tmp >> 8) & 0x7F);
646 alarm->time.hour = bcd_to_dec((tmp >> 16) & 0x3F);
647 }
648 else {
649 alarm->time.second = tmp & 0x7F;
650 alarm->time.minute = (tmp >> 8) & 0x7F;
651 alarm->time.hour = (tmp >> 16) & 0x3F;
652 }
653
654 alarm->time.sub_sec = ss_tmp & 0x7FFF;
655 alarm->ss_mask = (rtc_sub_second_mask_t)((ss_tmp >> 24) & 0xF);
656 alarm->mask = tmp & ALARM_MASK_ALL;
657
658 return;
659 }
ALARM_MASK_ALL
#define ALARM_MASK_ALL
Definition: ald_rtc.h:425
rtc_alarm_t::time
rtc_time_t time
Definition: ald_rtc.h:167
RTC_SELECT_WEEK
Definition: ald_rtc.h:159
assert_param
#define assert_param(x)
Definition: type.h:88
rtc_alarm_t::week
uint8_t week
Definition: ald_rtc.h:173
RTC_FORMAT_DEC
Definition: ald_rtc.h:109
RTC_SELECT_DAY
Definition: ald_rtc.h:158
rtc_sub_second_mask_t
rtc_sub_second_mask_t
Alarm sub-second mask.
Definition: ald_rtc.h:136
IS_RTC_FORMAT
#define IS_RTC_FORMAT(x)
Definition: ald_rtc.h:471
rtc_time_t::minute
uint8_t minute
Definition: ald_rtc.h:90
rtc_alarm_t::day
uint8_t day
Definition: ald_rtc.h:174
rtc_time_t::hour
uint8_t hour
Definition: ald_rtc.h:89
rtc_time_t::second
uint8_t second
Definition: ald_rtc.h:91
rtc_alarm_t::mask
uint32_t mask
Definition: ald_rtc.h:168
rtc_alarm_t::idx
rtc_alarm_idx_t idx
Definition: ald_rtc.h:166
bcd_to_dec
static uint32_t bcd_to_dec(uint32_t bcd)
Converts form 2 digit BCD to Binary.
Definition: ald_rtc.c:143
rtc_alarm_t::ss_mask
rtc_sub_second_mask_t ss_mask
Definition: ald_rtc.h:169
rtc_time_t::sub_sec
uint16_t sub_sec
Definition: ald_rtc.h:92
rtc_alarm_t::sel
rtc_week_day_sel_t sel
Definition: ald_rtc.h:170
RTC_ALARM_A
Definition: ald_rtc.h:117

◆ ald_rtc_set_alarm()

void ald_rtc_set_alarm | ( | rtc_alarm_t * | alarm,
 |  | rtc_format_t | format
 | ) |  |

Set alarm.

Parameters
alarm | pointer to rtc_alarm_t struct.
format | Data format.
Return values
None

Definition at line 509 of file ald_rtc.c.

510 {
511 unsigned int tmp, ss_tmp;
512
513 assert_param(IS_RTC_ALARM(alarm->idx));
514 assert_param(IS_RTC_ALARM_SEL(alarm->sel));
515 assert_param(IS_RTC_ALARM_SS_MASK(alarm->ss_mask));
516 assert_param(IS_RTC_FORMAT(format));
517
518 if (format == RTC_FORMAT_DEC) {
519 assert_param(IS_RTC_SECOND(alarm->time.second));
520 assert_param(IS_RTC_MINUTE(alarm->time.minute));
521 assert_param(IS_RTC_HOUR(alarm->time.hour));
522
523 tmp = (dec_to_bcd(alarm->time.second)) |
524 (dec_to_bcd(alarm->time.minute) << 8) |
525 (dec_to_bcd(alarm->time.hour) << 16) |
526 alarm->mask;
527
528 if (alarm->sel == RTC_SELECT_DAY) {
529 assert_param(IS_RTC_DAY(alarm->day));
530
531 tmp |= (dec_to_bcd(alarm->day) << 24);
532 tmp &= 0x7FFFFFFF; /* Reset bit31 */
533 }
534 else {
535 tmp |= (1 << (alarm->week + 24));
536 tmp |= 0x80000000; /* Set bit31 */
537 }
538 }
539 else {
540 assert_param(IS_RTC_SECOND(bcd_to_dec(alarm->time.second)));
541 assert_param(IS_RTC_MINUTE(bcd_to_dec(alarm->time.minute)));
542 assert_param(IS_RTC_HOUR(bcd_to_dec(alarm->time.hour)));
543
544 tmp = alarm->time.second |
545 (alarm->time.minute << 8) |
546 (alarm->time.hour << 16) |
547 alarm->mask;
548
549 if (alarm->sel == RTC_SELECT_DAY) {
550 assert_param(IS_RTC_DAY(bcd_to_dec(alarm->day)));
551
552 tmp |= (alarm->day << 24);
553 tmp &= 0x7FFFFFFF; /* Reset bit31 */
554 }
555 else {
556 tmp |= (1 << (alarm->week + 24));
557 tmp |= 0x80000000; /* Set bit31 */
558 }
559 }
560
561 ss_tmp = (alarm->time.sub_sec & 0x7F) |
562 (alarm->ss_mask << 24);
563
564 RTC_UNLOCK();
565
566 if (alarm->idx == RTC_ALARM_A) {
567 WRITE_REG(RTC->ALMA, tmp);
568 WRITE_REG(RTC->ALMASSEC, ss_tmp);
569 SET_BIT(RTC->CON, RTC_CON_ALMAEN_MSK);
570 }
571 else {
572 WRITE_REG(RTC->ALMB, tmp);
573 WRITE_REG(RTC->ALMBSSEC, ss_tmp);
574 SET_BIT(RTC->CON, RTC_CON_ALMBEN_MSK);
575 }
576
577 RTC_LOCK();
578 return;
579 }
rtc_alarm_t::time
rtc_time_t time
Definition: ald_rtc.h:167
assert_param
#define assert_param(x)
Definition: type.h:88
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
rtc_alarm_t::week
uint8_t week
Definition: ald_rtc.h:173
IS_RTC_DAY
#define IS_RTC_DAY(x)
Definition: ald_rtc.h:560
RTC_FORMAT_DEC
Definition: ald_rtc.h:109
IS_RTC_ALARM_SEL
#define IS_RTC_ALARM_SEL(x)
Definition: ald_rtc.h:443
RTC_SELECT_DAY
Definition: ald_rtc.h:158
IS_RTC_ALARM
#define IS_RTC_ALARM(x)
Definition: ald_rtc.h:441
IS_RTC_HOUR
#define IS_RTC_HOUR(x)
Definition: ald_rtc.h:559
IS_RTC_FORMAT
#define IS_RTC_FORMAT(x)
Definition: ald_rtc.h:471
rtc_time_t::minute
uint8_t minute
Definition: ald_rtc.h:90
rtc_alarm_t::day
uint8_t day
Definition: ald_rtc.h:174
dec_to_bcd
static uint32_t dec_to_bcd(uint32_t dec)
Converts a 2 digit decimal to BCD format.
Definition: ald_rtc.c:153
rtc_time_t::hour
uint8_t hour
Definition: ald_rtc.h:89
IS_RTC_SECOND
#define IS_RTC_SECOND(x)
Definition: ald_rtc.h:557
rtc_time_t::second
uint8_t second
Definition: ald_rtc.h:91
rtc_alarm_t::mask
uint32_t mask
Definition: ald_rtc.h:168
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
rtc_alarm_t::idx
rtc_alarm_idx_t idx
Definition: ald_rtc.h:166
bcd_to_dec
static uint32_t bcd_to_dec(uint32_t bcd)
Converts form 2 digit BCD to Binary.
Definition: ald_rtc.c:143
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
rtc_alarm_t::ss_mask
rtc_sub_second_mask_t ss_mask
Definition: ald_rtc.h:169
rtc_time_t::sub_sec
uint16_t sub_sec
Definition: ald_rtc.h:92
IS_RTC_MINUTE
#define IS_RTC_MINUTE(x)
Definition: ald_rtc.h:558
IS_RTC_ALARM_SS_MASK
#define IS_RTC_ALARM_SS_MASK(x)
Definition: ald_rtc.h:451
rtc_alarm_t::sel
rtc_week_day_sel_t sel
Definition: ald_rtc.h:170
RTC_ALARM_A
Definition: ald_rtc.h:117


ALD User Manual: Time stamp functions

Functions
Time stamp functions
EASTSOFT ES32F3xx ALD » RTC » RTC Public Functions

RTC time stamp functions. More...

Collaboration diagram for Time stamp functions:

Functions

void | ald_rtc_set_time_stamp (rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style)
Set time stamp. More...
void | ald_rtc_cancel_time_stamp (void)
Cancel time stamp. More...
void | ald_rtc_get_time_stamp (rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format)
Get time stamp value. More...

Detailed Description

RTC time stamp functions.

===============================================================================
                ##### Time stamp functions #####
===============================================================================

[..] This section provides functions allowing:
    [#]
      (+) To configure the time stamp use ald_rtc_set_time_stamp() function
      (+) To read the time stamp use ald_rtc_get_time_stamp() function
      (+) To cancel the time stamp use ald_rtc_cancel_time_stamp() function

Function Documentation

◆ ald_rtc_cancel_time_stamp()

void ald_rtc_cancel_time_stamp ( void )

Cancel time stamp.

Return values
None

Definition at line 712 of file ald_rtc.c.

713 {
714 RTC_UNLOCK();
715 CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK);
716 RTC_LOCK();
717
718 return;
719 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378

◆ ald_rtc_get_time_stamp()

void ald_rtc_get_time_stamp | ( | rtc_time_t * | ts_time,
 |  | rtc_date_t * | ts_date,
 |  | rtc_format_t | format
 | ) |  |

Get time stamp value.

Parameters
ts_time | pointer to rtc_time_t structure.
ts_date | pointer to rtc_date_t structure.
format | Data format.
Return values
None

Definition at line 728 of file ald_rtc.c.

729 {
730 uint32_t tmp0, tmp1;
731
732 assert_param(ts_time != NULL);
733 assert_param(ts_date != NULL);
734 assert_param(IS_RTC_FORMAT(format));
735
736 ts_time->sub_sec = RTC->TSSSEC & 0xFFFF;
737 tmp0 = RTC->TSTIME;
738 tmp1 = RTC->TSDATE;
739
740 if (format == RTC_FORMAT_DEC) {
741 ts_time->second = bcd_to_dec(tmp0 & 0x7F);
742 ts_time->minute = bcd_to_dec((tmp0 >> 8) & 0x7F);
743 ts_time->hour = bcd_to_dec((tmp0 >> 16) & 0x3F);
744 ts_date->day = bcd_to_dec(tmp1 & 0x3F);
745 ts_date->month = bcd_to_dec((tmp1 >> 8) & 0x1F);
746 ts_date->year = bcd_to_dec((tmp1 >> 16) & 0xFF);
747 ts_date->week = bcd_to_dec((tmp1 >> 24) & 0x7);
748 }
749 else {
750 ts_time->second = tmp0 & 0x7F;
751 ts_time->minute = (tmp0 >> 8) & 0x7F;
752 ts_time->hour = (tmp0 >> 16) & 0x3F;
753 ts_date->day = tmp1 & 0x3F;
754 ts_date->month = (tmp1 >> 8) & 0x1F;
755 ts_date->year = (tmp1 >> 16) & 0xFF;
756 ts_date->week = (tmp1 >> 24) & 0x7;
757 }
758
759 return;
760 }
rtc_date_t::day
uint8_t day
Definition: ald_rtc.h:100
assert_param
#define assert_param(x)
Definition: type.h:88
rtc_date_t::month
uint8_t month
Definition: ald_rtc.h:101
rtc_date_t::week
uint8_t week
Definition: ald_rtc.h:99
RTC_FORMAT_DEC
Definition: ald_rtc.h:109
IS_RTC_FORMAT
#define IS_RTC_FORMAT(x)
Definition: ald_rtc.h:471
rtc_time_t::minute
uint8_t minute
Definition: ald_rtc.h:90
rtc_time_t::hour
uint8_t hour
Definition: ald_rtc.h:89
rtc_time_t::second
uint8_t second
Definition: ald_rtc.h:91
bcd_to_dec
static uint32_t bcd_to_dec(uint32_t bcd)
Converts form 2 digit BCD to Binary.
Definition: ald_rtc.c:143
rtc_time_t::sub_sec
uint16_t sub_sec
Definition: ald_rtc.h:92
rtc_date_t::year
uint8_t year
Definition: ald_rtc.h:102

◆ ald_rtc_set_time_stamp()

void ald_rtc_set_time_stamp | ( | rtc_ts_signal_sel_t | sel,
 |  | rtc_ts_trigger_style_t | style
 | ) |  |

Set time stamp.

Parameters
sel time stamp signal select:
  • RTC_TS_SIGNAL_SEL_TAMPER0
  • RTC_TS_SIGNAL_SEL_TAMPER1
style time stamp trigger style:
  • RTC_TS_RISING_EDGE
  • RTC_TS_FALLING_EDGE
Return values
None

Definition at line 692 of file ald_rtc.c.

693 {
694 assert_param(IS_RTC_TS_SIGNAL(sel));
695 assert_param(IS_RTC_TS_STYLE(style));
696
697 RTC_UNLOCK();
698
699 CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK);
700 MODIFY_REG(RTC->CON, RTC_CON_TSSEL_MSK, style << RTC_CON_TSSEL_POS);
701 MODIFY_REG(RTC->CON, RTC_CON_TSPIN_MSK, sel << RTC_CON_TSPIN_POS);
702 SET_BIT(RTC->CON, RTC_CON_TSEN_MSK);
703
704 RTC_LOCK();
705 return;
706 }
IS_RTC_TS_SIGNAL
#define IS_RTC_TS_SIGNAL(x)
Definition: ald_rtc.h:467
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
IS_RTC_TS_STYLE
#define IS_RTC_TS_STYLE(x)
Definition: ald_rtc.h:469
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74


ALD User Manual: Tamper functions

Functions
Tamper functions
EASTSOFT ES32F3xx ALD » RTC » RTC Public Functions

RTC tamper functions. More...

Collaboration diagram for Tamper functions:

Functions

void | ald_rtc_set_tamper (rtc_tamper_t *tamper)
Set tamper parameters. More...
void | ald_rtc_cancel_tamper (rtc_tamper_idx_t idx)
Cancel tamper. More...

Detailed Description

RTC tamper functions.

===============================================================================
                ##### Tamper functions #####
===============================================================================

[..] This section provides functions allowing:
    [#]
      (+) To configure the tamper use ald_rtc_set_tamper() function
      (+) To cancel the tamper use ald_rtc_alarm_cmd() function

Function Documentation

◆ ald_rtc_cancel_tamper()

void ald_rtc_cancel_tamper ( rtc_tamper_idx_t idx )

Cancel tamper.

Parameters
idx index of tamper:
  • RTC_TAMPER_0
  • RTC_TAMPER_1
Return values
None

Definition at line 819 of file ald_rtc.c.

820 {
821 assert_param(IS_RTC_TAMPER(idx));
822
823 RTC_UNLOCK();
824
825 if (idx == RTC_TAMPER_0)
826 CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK);
827 else
828 CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP2EN_MSK);
829
830 RTC_LOCK();
831 return;
832 }
IS_RTC_TAMPER
#define IS_RTC_TAMPER(x)
Definition: ald_rtc.h:473
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
RTC_TAMPER_0
Definition: ald_rtc.h:198
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378

◆ ald_rtc_set_tamper()

void ald_rtc_set_tamper ( rtc_tamper_t * tamper )

Set tamper parameters.

Parameters
tamper pointer to rtc_tamper_t structure.
Return values
None

Definition at line 786 of file ald_rtc.c.

787 {
788 assert_param(IS_RTC_TAMPER(tamper->idx));
789 assert_param(IS_RTC_TAMPER_TRIGGER(tamper->trig));
790 assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(tamper->freq));
791 assert_param(IS_RTC_TAMPER_DURATION(tamper->dur));
792 assert_param(IS_FUNC_STATE(tamper->ts));
793
794 RTC_UNLOCK();
795 MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPTS_MSK, tamper->ts << RTC_TAMPCON_TAMPTS_POS);
796 MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPCKS_MSK, tamper->freq << RTC_TAMPCON_TAMPCKS_POSS);
797 MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPFLT_MSK, tamper->dur << RTC_TAMPCON_TAMPFLT_POSS);
798
799 if (tamper->idx == RTC_TAMPER_0) {
800 MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP1LV_MSK, tamper->trig << RTC_TAMPCON_TAMP1LV_POS);
801 SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK);
802 }
803 else {
804 MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP2LV_MSK, tamper->trig << RTC_TAMPCON_TAMP2LV_POS);
805 SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP2EN_MSK);
806 }
807
808 RTC_LOCK();
809 return;
810 }
IS_RTC_TAMPER
#define IS_RTC_TAMPER(x)
Definition: ald_rtc.h:473
rtc_tamper_t::ts
type_func_t ts
Definition: ald_rtc.h:242
assert_param
#define assert_param(x)
Definition: type.h:88
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
RTC_TAMPER_0
Definition: ald_rtc.h:198
IS_RTC_TAMPER_TRIGGER
#define IS_RTC_TAMPER_TRIGGER(x)
Definition: ald_rtc.h:475
rtc_tamper_t::dur
rtc_tamper_duration_t dur
Definition: ald_rtc.h:241
rtc_tamper_t::freq
rtc_tamper_sampling_freq_t freq
Definition: ald_rtc.h:240
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_RTC_TAMPER_DURATION
#define IS_RTC_TAMPER_DURATION(x)
Definition: ald_rtc.h:485
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
rtc_tamper_t::idx
rtc_tamper_idx_t idx
Definition: ald_rtc.h:238
rtc_tamper_t::trig
rtc_tamper_trigger_t trig
Definition: ald_rtc.h:239
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
IS_RTC_TAMPER_SAMPLING_FREQ
#define IS_RTC_TAMPER_SAMPLING_FREQ(x)
Definition: ald_rtc.h:477


ALD User Manual: Wake-up functions

Functions
Wake-up functions
EASTSOFT ES32F3xx ALD » RTC » RTC Public Functions

RTC wake-up functions. More...

Collaboration diagram for Wake-up functions:

Functions

void | ald_rtc_set_wakeup (rtc_wakeup_clock_t clock, uint16_t value)
Set wake-up parameters. More...
void | ald_rtc_cancel_wakeup (void)
Cancel wake-up. More...
uint16_t | ald_rtc_get_wakeup_timer_value (void)
Get wake-up re-load register value. More...

Detailed Description

RTC wake-up functions.

===============================================================================
                ##### Wake-up functions #####
===============================================================================

[..] This section provides functions allowing:
    [#]
      (+) To configure the wake-up parameters use ald_rtc_set_wakeup() function
      (+) To read the re-load register value use ald_rtc_get_wakeup_timer_value() function
      (+) To cancel the wake-up use ald_rtc_cancel_wakeup() function

Function Documentation

◆ ald_rtc_cancel_wakeup()

void ald_rtc_cancel_wakeup ( void )

Cancel wake-up.

Return values
None

Definition at line 877 of file ald_rtc.c.

878 {
879 RTC_UNLOCK();
880 CLEAR_BIT(RTC->CON, RTC_CON_WUTE_MSK);
881 RTC_LOCK();
882
883 return;
884 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378

◆ ald_rtc_get_wakeup_timer_value()

uint16_t ald_rtc_get_wakeup_timer_value ( void )

Get wake-up re-load register value.

Return values
Value of re-load register.

Definition at line 890 of file ald_rtc.c.

891 {
892 return RTC->WUMAT & 0xFFFF;
893 }

◆ ald_rtc_set_wakeup()

void ald_rtc_set_wakeup | ( | rtc_wakeup_clock_t | clock,
 |  | uint16_t | value
 | ) |  |

Set wake-up parameters.

Parameters
clock | pointer to rtc_wakeup_clock_t structure.
value | re-load value.
Return values
None

Definition at line 860 of file ald_rtc.c.

861 {
862 assert_param(IS_RTC_WAKEUP_CLOCK(clock));
863
864 RTC_UNLOCK();
865 MODIFY_REG(RTC->CON, RTC_CON_WUCKS_MSK, clock << RTC_CON_WUCKS_POSS);
866 WRITE_REG(RTC->WUMAT, value & 0xFFFF);
867 SET_BIT(RTC->CON, RTC_CON_WUTE_MSK);
868 RTC_LOCK();
869
870 return;
871 }
IS_RTC_WAKEUP_CLOCK
#define IS_RTC_WAKEUP_CLOCK(x)
Definition: ald_rtc.h:489
assert_param
#define assert_param(x)
Definition: type.h:88
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74


ALD User Manual: Clock output functions

Functions
Clock output functions
EASTSOFT ES32F3xx ALD » RTC » RTC Public Functions

RTC clock output functions. More...

Collaboration diagram for Clock output functions:

Functions

ald_status_t | ald_rtc_set_clock_output (rtc_clock_output_t clock)
Set clock output parameters. More...
void | ald_rtc_cancel_clock_output (void)
Cancel clock output. More...

Detailed Description

RTC clock output functions.

===============================================================================
                ##### Clock output functions #####
===============================================================================

[..] This section provides functions allowing:
    [#]
      (+) To configure the clock output type use ald_rtc_set_clock_output() function
      (+) To cancel the clock output use ald_rtc_cancel_clock_output() function

Function Documentation

◆ ald_rtc_cancel_clock_output()

void ald_rtc_cancel_clock_output ( void )

Cancel clock output.

Return values
None

Definition at line 949 of file ald_rtc.c.

950 {
951 RTC_UNLOCK();
952 CLEAR_BIT(RTC->CON, RTC_CON_CKOE_MSK);
953 RTC_LOCK();
954
955 return;
956 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378

◆ ald_rtc_set_clock_output()

ald_status_t ald_rtc_set_clock_output ( rtc_clock_output_t clock )

Set clock output parameters.

Parameters
clock pointer to rtc_clock_output_t structure.
Return values
ALD status.

Definition at line 919 of file ald_rtc.c.

920 {
921 uint32_t cnt = 4000;
922 assert_param(IS_RTC_CLOCK_OUTPUT(clock));
923
924 SYSCFG_UNLOCK();
925
926 if (clock == RTC_CLOCK_OUTPUT_EXA_1) {
927 SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK);
928 while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2LCKN_MSK)) && (--cnt));
929 cnt = 4000;
930 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL2RDY_MSK))) && (--cnt));
931 }
932 else {
933 CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK);
934 }
935
936 SYSCFG_LOCK();
937 RTC_UNLOCK();
938 MODIFY_REG(RTC->CON, RTC_CON_CKOS_MSK, clock << RTC_CON_CKOS_POSS);
939 SET_BIT(RTC->CON, RTC_CON_CKOE_MSK);
940 RTC_LOCK();
941
942 return OK;
943 }
OK
Definition: utils.h:55
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
RTC_CLOCK_OUTPUT_EXA_1
Definition: ald_rtc.h:266
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_RTC_CLOCK_OUTPUT
#define IS_RTC_CLOCK_OUTPUT(x)
Definition: ald_rtc.h:495
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39


ALD User Manual: Control functions

Functions
Control functions
EASTSOFT ES32F3xx ALD » RTC » RTC Public Functions

RTC control functions. More...

Collaboration diagram for Control functions:

Functions

void | ald_rtc_interrupt_config (rtc_it_t it, type_func_t state)
Enable/disable the specified RTC interrupts. More...
void | ald_rtc_alarm_cmd (rtc_alarm_idx_t idx, type_func_t state)
Enable/Disable alarm. More...
ald_status_t | ald_rtc_set_shift (type_func_t add_1s, uint16_t sub_ss)
Set shift parameters. More...
void | ald_rtc_set_cali (rtc_cali_t *config)
Set calibation. More...
void | ald_rtc_cancel_cali (void)
Cancel calibration. More...
ald_status_t | ald_rtc_get_cali_status (void)
Get calibration status. More...
void | ald_rtc_write_temp (uint16_t temp)
Write temperature value. More...
it_status_t | ald_rtc_get_it_status (rtc_it_t it)
Get the status of RTC interrupt source. More...
flag_status_t | ald_rtc_get_flag_status (rtc_flag_t flag)
Get the status of RTC interrupt flag. More...
void | ald_rtc_clear_flag_status (rtc_flag_t flag)
Clear the specified RTC pending flag. More...

Detailed Description

RTC control functions.

===============================================================================
                ##### Control functions #####
===============================================================================

[..] This section provides functions allowing:
    [#]
      (+) Configure interrupt enable/disable.
      (+) Enable/disable alarm.
      (+) Configure rtc shift.
      (+) Calibrate time.
      (+) Get interrupt source status.
      (+) Get interrupt flag status.
      (+) Clear interrupt flag.

Function Documentation

◆ ald_rtc_alarm_cmd()

void ald_rtc_alarm_cmd | ( | rtc_alarm_idx_t | idx,
 |  | type_func_t | state
 | ) |  |

Enable/Disable alarm.

Parameters
idx index of alarm:
  • RTC_ALARM_A
  • RTC_ALARM_B
state New status of the specified alarm:
  • ENABLE
  • DISABLE
Return values
None

Definition at line 1018 of file ald_rtc.c.

1019 {
1020 assert_param(IS_RTC_ALARM(idx));
1021 assert_param(IS_FUNC_STATE(state));
1022
1023 RTC_UNLOCK();
1024
1025 if (idx == RTC_ALARM_A)
1026 MODIFY_REG(RTC->CON, RTC_CON_ALMAEN_MSK, state << RTC_CON_ALMAEN_POS);
1027 else
1028 MODIFY_REG(RTC->CON, RTC_CON_ALMBEN_MSK, state << RTC_CON_ALMBEN_POS);
1029
1030 RTC_LOCK();
1031 return;
1032 }
assert_param
#define assert_param(x)
Definition: type.h:88
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
IS_RTC_ALARM
#define IS_RTC_ALARM(x)
Definition: ald_rtc.h:441
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
RTC_ALARM_A
Definition: ald_rtc.h:117

◆ ald_rtc_cancel_cali()

void ald_rtc_cancel_cali ( void )

Cancel calibration.

Return values
None

Definition at line 1095 of file ald_rtc.c.

1096 {
1097 RTC_CALI_UNLOCK();
1098 CLEAR_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK);
1099 RTC_CALI_LOCK();
1100
1101 return;
1102 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
RTC_CALI_LOCK
#define RTC_CALI_LOCK()
Definition: ald_rtc.h:424
RTC_CALI_UNLOCK
#define RTC_CALI_UNLOCK()
Definition: ald_rtc.h:423

◆ ald_rtc_clear_flag_status()

void ald_rtc_clear_flag_status ( rtc_flag_t flag )

Clear the specified RTC pending flag.

Parameters
flag specifies the flag to check.
Return values
None.

Definition at line 1170 of file ald_rtc.c.

1171 {
1172 assert_param(IS_RTC_IF(flag));
1173
1174 RTC_UNLOCK();
1175 WRITE_REG(RTC->IFCR, flag);
1176 RTC_LOCK();
1177
1178 return;
1179 }
assert_param
#define assert_param(x)
Definition: type.h:88
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
IS_RTC_IF
#define IS_RTC_IF(x)
Definition: ald_rtc.h:540
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72

◆ ald_rtc_get_cali_status()

ald_status_t ald_rtc_get_cali_status ( void )

Get calibration status.

Return values
ALD status.

Definition at line 1108 of file ald_rtc.c.

1109 {
1110 if (READ_BIT(RTC->CALCON, RTC_CALCON_ERR_MSK))
1111 return ERROR;
1112 else
1113 return OK;
1114 }
OK
Definition: utils.h:55
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
ERROR
Definition: utils.h:56

◆ ald_rtc_get_flag_status()

flag_status_t ald_rtc_get_flag_status ( rtc_flag_t flag )

Get the status of RTC interrupt flag.

Parameters
flag Specifies the RTC interrupt flag. This parameter can be one of the rtc_flag_t.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 1156 of file ald_rtc.c.

1157 {
1158 assert_param(IS_RTC_IF(flag));
1159
1160 if (READ_BIT(RTC->IFR, flag))
1161 return SET;
1162
1163 return RESET;
1164 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
RESET
Definition: type.h:38
IS_RTC_IF
#define IS_RTC_IF(x)
Definition: ald_rtc.h:540
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69

◆ ald_rtc_get_it_status()

it_status_t ald_rtc_get_it_status ( rtc_it_t it )

Get the status of RTC interrupt source.

Parameters
it Specifies the RTC interrupt source. This parameter can be one of the rtc_it_t.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 1138 of file ald_rtc.c.

1139 {
1140 assert_param(IS_RTC_IT(it));
1141
1142 if (READ_BIT(RTC->IER, it))
1143 return SET;
1144
1145 return RESET;
1146 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
RESET
Definition: type.h:38
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
IS_RTC_IT
#define IS_RTC_IT(x)
Definition: ald_rtc.h:523

◆ ald_rtc_interrupt_config()

void ald_rtc_interrupt_config | ( | rtc_it_t | it,
 |  | type_func_t | state
 | ) |  |

Enable/disable the specified RTC interrupts.

Parameters
it Specifies the RTC interrupt sources to be enabled or disabled. This parameter can be one of the rtc_it_t.
state New state of the specified RTC interrupts. This parameter can be:
  • ENABLE
  • DISABLE
Return values
None

Definition at line 992 of file ald_rtc.c.

993 {
994 assert_param(IS_RTC_IT(it));
995 assert_param(IS_FUNC_STATE(state));
996
997 RTC_UNLOCK();
998
999 if (state == ENABLE)
1000 SET_BIT(RTC->IER, it);
1001 else
1002 CLEAR_BIT(RTC->IER, it);
1003
1004 RTC_LOCK();
1005 return;
1006 }
ENABLE
Definition: type.h:49
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_RTC_IT
#define IS_RTC_IT(x)
Definition: ald_rtc.h:523
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_rtc_set_cali()

void ald_rtc_set_cali ( rtc_cali_t * config )

Set calibation.

Parameters
config pointer to rtc_cali_t structure.
Return values
None

Definition at line 1067 of file ald_rtc.c.

1068 {
1069 assert_param(IS_RTC_CALI_FREQ(config->cali_freq));
1070 assert_param(IS_RTC_CALI_TC(config->tc));
1071 assert_param(IS_RTC_CALC_FREQ(config->calc_freq));
1072 assert_param(IS_RTC_CALI_CALC(config->calc));
1073 assert_param(IS_FUNC_STATE(config->acc));
1074
1075 RTC_UNLOCK();
1076 RTC_CALI_UNLOCK();
1077
1078 MODIFY_REG(RTC->CALCON, RTC_CALCON_CALP_MSK, config->cali_freq << RTC_CALCON_CALP_POSS);
1079 MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, config->tc << RTC_CALCON_TCM_POSS);
1080 MODIFY_REG(RTC->CALCON, RTC_CALCON_TCP_MSK, config->calc_freq << RTC_CALCON_TCP_POSS);
1081 MODIFY_REG(RTC->CALCON, RTC_CALCON_ALG_MSK, config->calc << RTC_CALCON_ALG_POS);
1082 MODIFY_REG(RTC->CALCON, RTC_CALCON_DCMACC_MSK, config->acc << RTC_CALCON_DCMACC_POS);
1083 SET_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK);
1084
1085 RTC_CALI_LOCK();
1086 RTC_LOCK();
1087
1088 return;
1089 }
IS_RTC_CALC_FREQ
#define IS_RTC_CALC_FREQ(x)
Definition: ald_rtc.h:513
rtc_cali_t::cali_freq
rtc_cali_freq_t cali_freq
Definition: ald_rtc.h:319
assert_param
#define assert_param(x)
Definition: type.h:88
IS_RTC_CALI_CALC
#define IS_RTC_CALI_CALC(x)
Definition: ald_rtc.h:521
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
IS_RTC_CALI_TC
#define IS_RTC_CALI_TC(x)
Definition: ald_rtc.h:509
rtc_cali_t::calc
rtc_cali_calc_t calc
Definition: ald_rtc.h:322
rtc_cali_t::tc
rtc_cali_tc_t tc
Definition: ald_rtc.h:320
IS_RTC_CALI_FREQ
#define IS_RTC_CALI_FREQ(x)
Definition: ald_rtc.h:501
rtc_cali_t::calc_freq
rtc_cali_calc_freq_t calc_freq
Definition: ald_rtc.h:321
RTC_CALI_LOCK
#define RTC_CALI_LOCK()
Definition: ald_rtc.h:424
RTC_CALI_UNLOCK
#define RTC_CALI_UNLOCK()
Definition: ald_rtc.h:423
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
rtc_cali_t::acc
type_func_t acc
Definition: ald_rtc.h:323

◆ ald_rtc_set_shift()

ald_status_t ald_rtc_set_shift | ( | type_func_t | add_1s,
 |  | uint16_t | sub_ss
 | ) |  |

Set shift parameters.

Parameters
add_1s | Enable/Disable added 1 second.
sub_ss | value of sub-sconde.
Return values
ALD status.

Definition at line 1040 of file ald_rtc.c.

1041 {
1042 uint32_t tick;
1043
1044 assert_param(IS_FUNC_STATE(add_1s));
1045 assert_param(IS_SHIFT_SUB_SS(sub_ss));
1046
1047 RTC_UNLOCK();
1048 MODIFY_REG(RTC->SSECTR, RTC_SSECTR_TRIM_MSK, sub_ss << RTC_SSECTR_TRIM_POSS);
1049 MODIFY_REG(RTC->SSECTR, RTC_SSECTR_INC_MSK, add_1s << RTC_SSECTR_INC_POS);
1050 RTC_LOCK();
1051
1052 tick = ald_get_tick();
1053
1054 while (READ_BIT(RTC->CON, RTC_CON_SSEC_MSK)) {
1055 if ((ald_get_tick() - tick) > RTC_TIMEOUT_VALUE)
1056 return TIMEOUT;
1057 }
1058
1059 return OK;
1060 }
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
IS_SHIFT_SUB_SS
#define IS_SHIFT_SUB_SS(x)
Definition: ald_rtc.h:428
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
RTC_TIMEOUT_VALUE
#define RTC_TIMEOUT_VALUE
Definition: ald_rtc.h:426
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_rtc_write_temp()

void ald_rtc_write_temp ( uint16_t temp )

Write temperature value.

Parameters
temp the value of temperature.
Return values
None

Definition at line 1121 of file ald_rtc.c.

1122 {
1123 RTC_CALI_UNLOCK();
1124 MODIFY_REG(RTC->TEMPR, RTC_TEMPR_VAL_MSK, temp << RTC_TEMPR_VAL_POSS);
1125 RTC_CALI_LOCK();
1126
1127 return;
1128 }
RTC_CALI_LOCK
#define RTC_CALI_LOCK()
Definition: ald_rtc.h:424
RTC_CALI_UNLOCK
#define RTC_CALI_UNLOCK()
Definition: ald_rtc.h:423
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74


ALD User Manual: RTC Public Types

Data Structures | Enumerations
RTC Public Types
EASTSOFT ES32F3xx ALD » RTC
Collaboration diagram for RTC Public Types:

Data Structures

struct | rtc_init_t
Initialization structure. More...
struct | rtc_time_t
Time structure. More...
struct | rtc_date_t
Date structure. More...
struct | rtc_alarm_t
Alarm structure. More...
struct | rtc_tamper_t
Tamper structure. More...
struct | rtc_cali_t
Calibration structure. More...

Enumerations

enum | rtc_hour_format_t { RTC_HOUR_FORMAT_24 = 0x0U, RTC_HOUR_FORMAT_12 = 0x1U }
Hours format. More...
enum | rtc_output_select_t { RTC_OUTPUT_DISABLE = 0x0U, RTC_OUTPUT_ALARM_A = 0x1U, RTC_OUTPUT_ALARM_B = 0x2U, RTC_OUTPUT_WAKEUP = 0x3U }
Output mode. More...
enum | rtc_output_polarity_t { RTC_OUTPUT_POLARITY_HIGH = 0x0U, RTC_OUTPUT_POLARITY_LOW = 0x1U }
Output polarity. More...
enum | rtc_source_sel_t { RTC_SOURCE_LOSC = 0x0U, RTC_SOURCE_LRC = 0x1U, RTC_SOURCE_HRC_DIV_1M = 0x2U, RTC_SOURCE_HOSC_DIV_1M = 0x3U }
Source select. More...
enum | rtc_format_t { RTC_FORMAT_DEC = 0U, RTC_FORMAT_BCD = 1U }
Data format. More...
enum | rtc_alarm_idx_t { RTC_ALARM_A = 0x0U, RTC_ALARM_B = 0x1U }
Index of alarm. More...
enum rtc_alarm_mask_t {
RTC_ALARM_MASK_NONE = 0x0U, RTC_ALARM_MASK_WEEK_DAY = (1U << 30), RTC_ALARM_MASK_HOUR = (1U << 23), RTC_ALARM_MASK_MINUTE = (1U << 15),
RTC_ALARM_MASK_SECOND = (1U << 7), RTC_ALARM_MASK_ALL = 0x40808080U
}
Alarm mask. More...
enum rtc_sub_second_mask_t {
RTC_ALARM_SS_MASK_NONE = 0xFU, RTC_ALARM_SS_MASK_14_1 = 0x1U, RTC_ALARM_SS_MASK_14_2 = 0x2U, RTC_ALARM_SS_MASK_14_3 = 0x3U,
RTC_ALARM_SS_MASK_14_4 = 0x4U, RTC_ALARM_SS_MASK_14_5 = 0x5U, RTC_ALARM_SS_MASK_14_6 = 0x6U, RTC_ALARM_SS_MASK_14_7 = 0x7U,
RTC_ALARM_SS_MASK_14_8 = 0x8U, RTC_ALARM_SS_MASK_14_9 = 0x9U, RTC_ALARM_SS_MASK_14_10 = 0xAU, RTC_ALARM_SS_MASK_14_11 = 0xBU,
RTC_ALARM_SS_MASK_14_12 = 0xCU, RTC_ALARM_SS_MASK_14_13 = 0xDU, RTC_ALARM_SS_MASK_14 = 0xEU, RTC_ALARM_SS_MASK_ALL = 0x0U
}
Alarm sub-second mask. More...
enum | rtc_week_day_sel_t { RTC_SELECT_DAY = 0x0U, RTC_SELECT_WEEK = 0x1U }
Alarm select week or day. More...
enum | rtc_ts_signal_sel_t { RTC_TS_SIGNAL_SEL_TAMPER0 = 0U, RTC_TS_SIGNAL_SEL_TAMPER1 = 1U }
Time stamp signel select. More...
enum | rtc_ts_trigger_style_t { RTC_TS_RISING_EDGE = 0U, RTC_TS_FALLING_EDGE = 1U }
Time stamp trigger style. More...
enum | rtc_tamper_idx_t { RTC_TAMPER_0 = 0U, RTC_TAMPER_1 = 1U }
Index of tamper. More...
enum | rtc_tamper_trigger_t { RTC_TAMPER_TRIGGER_LOW = 0U, RTC_TAMPER_TRIGGER_HIGH = 1U }
Tamper trigger type. More...
enum rtc_tamper_sampling_freq_t {
RTC_TAMPER_SAMPLING_FREQ_32768 = 0U, RTC_TAMPER_SAMPLING_FREQ_16384 = 1U, RTC_TAMPER_SAMPLING_FREQ_8192 = 2U, RTC_TAMPER_SAMPLING_FREQ_4096 = 3U,
RTC_TAMPER_SAMPLING_FREQ_2048 = 4U, RTC_TAMPER_SAMPLING_FREQ_1024 = 5U, RTC_TAMPER_SAMPLING_FREQ_512 = 6U, RTC_TAMPER_SAMPLING_FREQ_256 = 7U
}
Tamper sampling frequency. More...
enum | rtc_tamper_duration_t { RTC_TAMPER_DURATION_1 = 0U, RTC_TAMPER_DURATION_2 = 1U, RTC_TAMPER_DURATION_4 = 2U, RTC_TAMPER_DURATION_8 = 3U }
Tamper filter time. More...
enum rtc_wakeup_clock_t {
RTC_WAKEUP_CLOCK_DIV_16 = 0U, RTC_WAKEUP_CLOCK_DIV_8 = 1U, RTC_WAKEUP_CLOCK_DIV_4 = 2U, RTC_WAKEUP_CLOCK_DIV_2 = 3U,
RTC_WAKEUP_CLOCK_1HZ = 4U, RTC_WAKEUP_CLOCK_1HZ_PULS = 6U
}
Wake-up clock. More...
enum rtc_clock_output_t {
RTC_CLOCK_OUTPUT_32768 = 0U, RTC_CLOCK_OUTPUT_1024 = 1U, RTC_CLOCK_OUTPUT_32 = 2U, RTC_CLOCK_OUTPUT_1 = 3U,
RTC_CLOCK_OUTPUT_CAL_1 = 4U, RTC_CLOCK_OUTPUT_EXA_1 = 5U
}
RTC clock output type. More...
enum rtc_cali_freq_t {
RTC_CALI_FREQ_10_SEC = 0U, RTC_CALI_FREQ_20_SEC = 1U, RTC_CALI_FREQ_1_MIN = 2U, RTC_CALI_FREQ_2_MIN = 3U,
RTC_CALI_FREQ_5_MIN = 4U, RTC_CALI_FREQ_10_MIN = 5U, RTC_CALI_FREQ_20_MIN = 6U, RTC_CALI_FREQ_1_SEC = 7U
}
enum | rtc_cali_tc_t { RTC_CALI_TC_NONE = 0U, RTC_CALI_TC_AUTO_BY_HW = 1U, RTC_CALI_TC_AUTO_BY_SF = 2U, RTC_CALI_TC_AUTO_BY_HW_SF = 3U }
Temperature compensate type. More...
enum rtc_cali_calc_freq_t {
RTC_CALI_CALC_FREQ_10_SEC = 0U, RTC_CALI_CALC_FREQ_20_SEC = 1U, RTC_CALI_CALC_FREQ_1_MIN = 2U, RTC_CALI_CALC_FREQ_2_MIN = 3U,
RTC_CALI_CALC_FREQ_5_MIN = 4U, RTC_CALI_CALC_FREQ_10_MIN = 5U, RTC_CALI_CALC_FREQ_20_MIN = 6U, RTC_CALI_CALC_FREQ_1_HOUR = 7U
}
enum | rtc_cali_calc_t { RTC_CALI_CALC_4 = 0U, RTC_CALI_CALC_2 = 1U }
Calibration algorithm. More...
enum rtc_it_t {
RTC_IT_SEC = (1U << 0), RTC_IT_MIN = (1U << 1), RTC_IT_HR = (1U << 2), RTC_IT_DAY = (1U << 3),
RTC_IT_MON = (1U << 4), RTC_IT_YR = (1U << 5), RTC_IT_ALMA = (1U << 8), RTC_IT_ALMB = (1U << 9),
RTC_IT_TS = (1U << 10), RTC_IT_TSOV = (1U << 11), RTC_IT_TP0 = (1U << 12), RTC_IT_TP1 = (1U << 13),
RTC_IT_RSC = (1U << 16), RTC_IT_SFC = (1U << 17), RTC_IT_WU = (1U << 18), RTC_IT_TCC = (1U << 24),
RTC_IT_TCE = (1U << 25)
}
Interrupt type. More...
enum rtc_flag_t {
RTC_IF_SEC = (1U << 0), RTC_IF_MIN = (1U << 1), RTC_IF_HR = (1U << 2), RTC_IF_DAY = (1U << 3),
RTC_IF_MON = (1U << 4), RTC_IF_YR = (1U << 5), RTC_IF_ALMA = (1U << 8), RTC_IF_ALMB = (1U << 9),
RTC_IF_TS = (1U << 10), RTC_IF_TSOV = (1U << 11), RTC_IF_TP0 = (1U << 12), RTC_IF_TP1 = (1U << 13),
RTC_IF_RSC = (1U << 16), RTC_IF_SFC = (1U << 17), RTC_IF_WU = (1U << 18), RTC_IF_TCC = (1U << 24),
RTC_IF_TCE = (1U << 25)
}
Interrupt flag. More...

Detailed Description

Enumeration Type Documentation

◆ rtc_alarm_idx_t

enum rtc_alarm_idx_t

Index of alarm.

Enumerator
RTC_ALARM_A | Alarm-A
RTC_ALARM_B | Alarm-B

Definition at line 116 of file ald_rtc.h.

116 {
117 RTC_ALARM_A = 0x0U,
118 RTC_ALARM_B = 0x1U,
119 } rtc_alarm_idx_t;
RTC_ALARM_B
Definition: ald_rtc.h:118
rtc_alarm_idx_t
rtc_alarm_idx_t
Index of alarm.
Definition: ald_rtc.h:116
RTC_ALARM_A
Definition: ald_rtc.h:117

◆ rtc_alarm_mask_t

enum rtc_alarm_mask_t

Alarm mask.

Enumerator
RTC_ALARM_MASK_NONE | Mask is disable
RTC_ALARM_MASK_WEEK_DAY | Mask week or day
RTC_ALARM_MASK_HOUR | Mask hour
RTC_ALARM_MASK_MINUTE | Mask minute
RTC_ALARM_MASK_SECOND | Mask second
RTC_ALARM_MASK_ALL | Mask all

Definition at line 124 of file ald_rtc.h.

124 {
125 RTC_ALARM_MASK_NONE = 0x0U,
126 RTC_ALARM_MASK_WEEK_DAY = (1U << 30),
127 RTC_ALARM_MASK_HOUR = (1U << 23),
128 RTC_ALARM_MASK_MINUTE = (1U << 15),
129 RTC_ALARM_MASK_SECOND = (1U << 7),
130 RTC_ALARM_MASK_ALL = 0x40808080U,
131 } rtc_alarm_mask_t;
rtc_alarm_mask_t
rtc_alarm_mask_t
Alarm mask.
Definition: ald_rtc.h:124
RTC_ALARM_MASK_ALL
Definition: ald_rtc.h:130
RTC_ALARM_MASK_WEEK_DAY
Definition: ald_rtc.h:126
RTC_ALARM_MASK_MINUTE
Definition: ald_rtc.h:128
RTC_ALARM_MASK_HOUR
Definition: ald_rtc.h:127
RTC_ALARM_MASK_NONE
Definition: ald_rtc.h:125
RTC_ALARM_MASK_SECOND
Definition: ald_rtc.h:129

◆ rtc_cali_calc_freq_t

enum rtc_cali_calc_freq_t

@ Calculate frequency

Enumerator
RTC_CALI_CALC_FREQ_10_SEC | Calculate every 10 seconds
RTC_CALI_CALC_FREQ_20_SEC | Calculate every 20 seconds
RTC_CALI_CALC_FREQ_1_MIN | Calculate every 1 minute
RTC_CALI_CALC_FREQ_2_MIN | Calculate every 2 minutes
RTC_CALI_CALC_FREQ_5_MIN | Calculate every 5 minutes
RTC_CALI_CALC_FREQ_10_MIN | Calculate every 10 minutes
RTC_CALI_CALC_FREQ_20_MIN | Calculate every 20 minutes
RTC_CALI_CALC_FREQ_1_HOUR | Calculate every 1 hour

Definition at line 296 of file ald_rtc.h.

296 {
297 RTC_CALI_CALC_FREQ_10_SEC = 0U,
298 RTC_CALI_CALC_FREQ_20_SEC = 1U,
299 RTC_CALI_CALC_FREQ_1_MIN = 2U,
300 RTC_CALI_CALC_FREQ_2_MIN = 3U,
301 RTC_CALI_CALC_FREQ_5_MIN = 4U,
302 RTC_CALI_CALC_FREQ_10_MIN = 5U,
303 RTC_CALI_CALC_FREQ_20_MIN = 6U,
304 RTC_CALI_CALC_FREQ_1_HOUR = 7U,
305 } rtc_cali_calc_freq_t;
RTC_CALI_CALC_FREQ_1_MIN
Definition: ald_rtc.h:299
RTC_CALI_CALC_FREQ_20_MIN
Definition: ald_rtc.h:303
RTC_CALI_CALC_FREQ_20_SEC
Definition: ald_rtc.h:298
RTC_CALI_CALC_FREQ_10_MIN
Definition: ald_rtc.h:302
RTC_CALI_CALC_FREQ_5_MIN
Definition: ald_rtc.h:301
RTC_CALI_CALC_FREQ_10_SEC
Definition: ald_rtc.h:297
rtc_cali_calc_freq_t
rtc_cali_calc_freq_t
Definition: ald_rtc.h:296
RTC_CALI_CALC_FREQ_1_HOUR
Definition: ald_rtc.h:304
RTC_CALI_CALC_FREQ_2_MIN
Definition: ald_rtc.h:300

◆ rtc_cali_calc_t

enum rtc_cali_calc_t

Calibration algorithm.

Enumerator
RTC_CALI_CALC_4 | 4-polynomial
RTC_CALI_CALC_2 | 2-parabola

Definition at line 310 of file ald_rtc.h.

310 {
311 RTC_CALI_CALC_4 = 0U,
312 RTC_CALI_CALC_2 = 1U,
313 } rtc_cali_calc_t;
rtc_cali_calc_t
rtc_cali_calc_t
Calibration algorithm.
Definition: ald_rtc.h:310
RTC_CALI_CALC_4
Definition: ald_rtc.h:311
RTC_CALI_CALC_2
Definition: ald_rtc.h:312

◆ rtc_cali_freq_t

enum rtc_cali_freq_t

@ Calibration frequency

Enumerator
RTC_CALI_FREQ_10_SEC | Calibrate every 10 seconds
RTC_CALI_FREQ_20_SEC | Calibrate every 20 seconds
RTC_CALI_FREQ_1_MIN | Calibrate every 1 minute
RTC_CALI_FREQ_2_MIN | Calibrate every 2 minutes
RTC_CALI_FREQ_5_MIN | Calibrate every 5 minutes
RTC_CALI_FREQ_10_MIN | Calibrate every 10 minutes
RTC_CALI_FREQ_20_MIN | Calibrate every 20 minutes
RTC_CALI_FREQ_1_SEC | Calibrate every 1 second

Definition at line 272 of file ald_rtc.h.

272 {
273 RTC_CALI_FREQ_10_SEC = 0U,
274 RTC_CALI_FREQ_20_SEC = 1U,
275 RTC_CALI_FREQ_1_MIN = 2U,
276 RTC_CALI_FREQ_2_MIN = 3U,
277 RTC_CALI_FREQ_5_MIN = 4U,
278 RTC_CALI_FREQ_10_MIN = 5U,
279 RTC_CALI_FREQ_20_MIN = 6U,
280 RTC_CALI_FREQ_1_SEC = 7U,
281 } rtc_cali_freq_t;
RTC_CALI_FREQ_20_MIN
Definition: ald_rtc.h:279
RTC_CALI_FREQ_1_SEC
Definition: ald_rtc.h:280
rtc_cali_freq_t
rtc_cali_freq_t
Definition: ald_rtc.h:272
RTC_CALI_FREQ_2_MIN
Definition: ald_rtc.h:276
RTC_CALI_FREQ_5_MIN
Definition: ald_rtc.h:277
RTC_CALI_FREQ_10_SEC
Definition: ald_rtc.h:273
RTC_CALI_FREQ_1_MIN
Definition: ald_rtc.h:275
RTC_CALI_FREQ_20_SEC
Definition: ald_rtc.h:274
RTC_CALI_FREQ_10_MIN
Definition: ald_rtc.h:278

◆ rtc_cali_tc_t

enum rtc_cali_tc_t

Temperature compensate type.

Enumerator
RTC_CALI_TC_NONE | Temperature compensate disable
RTC_CALI_TC_AUTO_BY_HW | Temperature compensate by hardware
RTC_CALI_TC_AUTO_BY_SF | Temperature compensate by software
RTC_CALI_TC_AUTO_BY_HW_SF | Temperature compensate by hardware, trigger by software

Definition at line 286 of file ald_rtc.h.

286 {
287 RTC_CALI_TC_NONE = 0U,
288 RTC_CALI_TC_AUTO_BY_HW = 1U,
289 RTC_CALI_TC_AUTO_BY_SF = 2U,
290 RTC_CALI_TC_AUTO_BY_HW_SF = 3U,
291 } rtc_cali_tc_t;
rtc_cali_tc_t
rtc_cali_tc_t
Temperature compensate type.
Definition: ald_rtc.h:286
RTC_CALI_TC_AUTO_BY_SF
Definition: ald_rtc.h:289
RTC_CALI_TC_NONE
Definition: ald_rtc.h:287
RTC_CALI_TC_AUTO_BY_HW_SF
Definition: ald_rtc.h:290
RTC_CALI_TC_AUTO_BY_HW
Definition: ald_rtc.h:288

◆ rtc_clock_output_t

enum rtc_clock_output_t

RTC clock output type.

Enumerator
RTC_CLOCK_OUTPUT_32768 | 32768Hz
RTC_CLOCK_OUTPUT_1024 | 1024Hz
RTC_CLOCK_OUTPUT_32 | 32Hz
RTC_CLOCK_OUTPUT_1 | 1Hz
RTC_CLOCK_OUTPUT_CAL_1 | 1Hz after calibration
RTC_CLOCK_OUTPUT_EXA_1 | Exact 1Hz

Definition at line 260 of file ald_rtc.h.

260 {
261 RTC_CLOCK_OUTPUT_32768 = 0U,
262 RTC_CLOCK_OUTPUT_1024 = 1U,
263 RTC_CLOCK_OUTPUT_32 = 2U,
264 RTC_CLOCK_OUTPUT_1 = 3U,
265 RTC_CLOCK_OUTPUT_CAL_1 = 4U,
266 RTC_CLOCK_OUTPUT_EXA_1 = 5U,
267 } rtc_clock_output_t;
RTC_CLOCK_OUTPUT_EXA_1
Definition: ald_rtc.h:266
RTC_CLOCK_OUTPUT_1
Definition: ald_rtc.h:264
RTC_CLOCK_OUTPUT_CAL_1
Definition: ald_rtc.h:265
RTC_CLOCK_OUTPUT_1024
Definition: ald_rtc.h:262
rtc_clock_output_t
rtc_clock_output_t
RTC clock output type.
Definition: ald_rtc.h:260
RTC_CLOCK_OUTPUT_32
Definition: ald_rtc.h:263
RTC_CLOCK_OUTPUT_32768
Definition: ald_rtc.h:261

◆ rtc_flag_t

enum rtc_flag_t

Interrupt flag.

Enumerator
RTC_IF_SEC | Second
RTC_IF_MIN | Minute
RTC_IF_HR | Hour
RTC_IF_DAY | Day
RTC_IF_MON | Month
RTC_IF_YR | Year
RTC_IF_ALMA | Alarm-A
RTC_IF_ALMB | Alarm-B
RTC_IF_TS | Time stamp
RTC_IF_TSOV | Time stamp overflow
RTC_IF_TP0 | Tamper-0
RTC_IF_TP1 | Tamper-1
RTC_IF_RSC | Synchronous complete
RTC_IF_SFC | Shift complete
RTC_IF_WU | Wake-up
RTC_IF_TCC | Temperature compensate complete
RTC_IF_TCE | Temperature compensate error

Definition at line 352 of file ald_rtc.h.

352 {
353 RTC_IF_SEC = (1U << 0),
354 RTC_IF_MIN = (1U << 1),
355 RTC_IF_HR = (1U << 2),
356 RTC_IF_DAY = (1U << 3),
357 RTC_IF_MON = (1U << 4),
358 RTC_IF_YR = (1U << 5),
359 RTC_IF_ALMA = (1U << 8),
360 RTC_IF_ALMB = (1U << 9),
361 RTC_IF_TS = (1U << 10),
362 RTC_IF_TSOV = (1U << 11),
363 RTC_IF_TP0 = (1U << 12),
364 RTC_IF_TP1 = (1U << 13),
365 RTC_IF_RSC = (1U << 16),
366 RTC_IF_SFC = (1U << 17),
367 RTC_IF_WU = (1U << 18),
368 RTC_IF_TCC = (1U << 24),
369 RTC_IF_TCE = (1U << 25),
370 } rtc_flag_t;
RTC_IF_ALMA
Definition: ald_rtc.h:359
RTC_IF_TSOV
Definition: ald_rtc.h:362
RTC_IF_YR
Definition: ald_rtc.h:358
RTC_IF_SEC
Definition: ald_rtc.h:353
RTC_IF_TP0
Definition: ald_rtc.h:363
RTC_IF_HR
Definition: ald_rtc.h:355
RTC_IF_TS
Definition: ald_rtc.h:361
RTC_IF_DAY
Definition: ald_rtc.h:356
RTC_IF_TCE
Definition: ald_rtc.h:369
RTC_IF_MON
Definition: ald_rtc.h:357
RTC_IF_RSC
Definition: ald_rtc.h:365
rtc_flag_t
rtc_flag_t
Interrupt flag.
Definition: ald_rtc.h:352
RTC_IF_MIN
Definition: ald_rtc.h:354
RTC_IF_WU
Definition: ald_rtc.h:367
RTC_IF_ALMB
Definition: ald_rtc.h:360
RTC_IF_TCC
Definition: ald_rtc.h:368
RTC_IF_SFC
Definition: ald_rtc.h:366
RTC_IF_TP1
Definition: ald_rtc.h:364

◆ rtc_format_t

enum rtc_format_t

Data format.

Enumerator
RTC_FORMAT_DEC | Decimal
RTC_FORMAT_BCD | BSD

Definition at line 108 of file ald_rtc.h.

108 {
109 RTC_FORMAT_DEC = 0U,
110 RTC_FORMAT_BCD = 1U,
111 } rtc_format_t;
rtc_format_t
rtc_format_t
Data format.
Definition: ald_rtc.h:108
RTC_FORMAT_DEC
Definition: ald_rtc.h:109
RTC_FORMAT_BCD
Definition: ald_rtc.h:110

◆ rtc_hour_format_t

enum rtc_hour_format_t

Hours format.

Enumerator
RTC_HOUR_FORMAT_24 | 24-hours format
RTC_HOUR_FORMAT_12 | 12-hours format

Definition at line 41 of file ald_rtc.h.

41 {
42 RTC_HOUR_FORMAT_24 = 0x0U,
43 RTC_HOUR_FORMAT_12 = 0x1U,
44 } rtc_hour_format_t;
rtc_hour_format_t
rtc_hour_format_t
Hours format.
Definition: ald_rtc.h:41
RTC_HOUR_FORMAT_12
Definition: ald_rtc.h:43
RTC_HOUR_FORMAT_24
Definition: ald_rtc.h:42

◆ rtc_it_t

enum rtc_it_t

Interrupt type.

Enumerator
RTC_IT_SEC | Second
RTC_IT_MIN | Minute
RTC_IT_HR | Hour
RTC_IT_DAY | Day
RTC_IT_MON | Month
RTC_IT_YR | Year
RTC_IT_ALMA | Alarm-A
RTC_IT_ALMB | Alarm-B
RTC_IT_TS | Time stamp
RTC_IT_TSOV | Time stamp overflow
RTC_IT_TP0 | Tamper-0
RTC_IT_TP1 | Tamper-1
RTC_IT_RSC | Synchronous complete
RTC_IT_SFC | Shift complete
RTC_IT_WU | Wake-up
RTC_IT_TCC | Temperature compensate complete
RTC_IT_TCE | Temperature compensate error

Definition at line 329 of file ald_rtc.h.

329 {
330 RTC_IT_SEC = (1U << 0),
331 RTC_IT_MIN = (1U << 1),
332 RTC_IT_HR = (1U << 2),
333 RTC_IT_DAY = (1U << 3),
334 RTC_IT_MON = (1U << 4),
335 RTC_IT_YR = (1U << 5),
336 RTC_IT_ALMA = (1U << 8),
337 RTC_IT_ALMB = (1U << 9),
338 RTC_IT_TS = (1U << 10),
339 RTC_IT_TSOV = (1U << 11),
340 RTC_IT_TP0 = (1U << 12),
341 RTC_IT_TP1 = (1U << 13),
342 RTC_IT_RSC = (1U << 16),
343 RTC_IT_SFC = (1U << 17),
344 RTC_IT_WU = (1U << 18),
345 RTC_IT_TCC = (1U << 24),
346 RTC_IT_TCE = (1U << 25),
347 } rtc_it_t;
RTC_IT_WU
Definition: ald_rtc.h:344
RTC_IT_TCC
Definition: ald_rtc.h:345
RTC_IT_TP1
Definition: ald_rtc.h:341
RTC_IT_TCE
Definition: ald_rtc.h:346
RTC_IT_TSOV
Definition: ald_rtc.h:339
RTC_IT_MON
Definition: ald_rtc.h:334
RTC_IT_MIN
Definition: ald_rtc.h:331
RTC_IT_TP0
Definition: ald_rtc.h:340
RTC_IT_YR
Definition: ald_rtc.h:335
RTC_IT_DAY
Definition: ald_rtc.h:333
rtc_it_t
rtc_it_t
Interrupt type.
Definition: ald_rtc.h:329
RTC_IT_SFC
Definition: ald_rtc.h:343
RTC_IT_HR
Definition: ald_rtc.h:332
RTC_IT_TS
Definition: ald_rtc.h:338
RTC_IT_SEC
Definition: ald_rtc.h:330
RTC_IT_RSC
Definition: ald_rtc.h:342
RTC_IT_ALMA
Definition: ald_rtc.h:336
RTC_IT_ALMB
Definition: ald_rtc.h:337

◆ rtc_output_polarity_t

enum rtc_output_polarity_t

Output polarity.

Enumerator
RTC_OUTPUT_POLARITY_HIGH | Polarity is high
RTC_OUTPUT_POLARITY_LOW | Polarity is low

Definition at line 59 of file ald_rtc.h.

59 {
60 RTC_OUTPUT_POLARITY_HIGH = 0x0U,
61 RTC_OUTPUT_POLARITY_LOW = 0x1U,
62 } rtc_output_polarity_t;
RTC_OUTPUT_POLARITY_LOW
Definition: ald_rtc.h:61
rtc_output_polarity_t
rtc_output_polarity_t
Output polarity.
Definition: ald_rtc.h:59
RTC_OUTPUT_POLARITY_HIGH
Definition: ald_rtc.h:60

◆ rtc_output_select_t

enum rtc_output_select_t

Output mode.

Enumerator
RTC_OUTPUT_DISABLE | Disable output
RTC_OUTPUT_ALARM_A | Output alarm_a signal
RTC_OUTPUT_ALARM_B | Output alarm_b signal
RTC_OUTPUT_WAKEUP | Output wakeup signal

Definition at line 49 of file ald_rtc.h.

49 {
50 RTC_OUTPUT_DISABLE = 0x0U,
51 RTC_OUTPUT_ALARM_A = 0x1U,
52 RTC_OUTPUT_ALARM_B = 0x2U,
53 RTC_OUTPUT_WAKEUP = 0x3U,
54 } rtc_output_select_t;
RTC_OUTPUT_DISABLE
Definition: ald_rtc.h:50
rtc_output_select_t
rtc_output_select_t
Output mode.
Definition: ald_rtc.h:49
RTC_OUTPUT_WAKEUP
Definition: ald_rtc.h:53
RTC_OUTPUT_ALARM_B
Definition: ald_rtc.h:52
RTC_OUTPUT_ALARM_A
Definition: ald_rtc.h:51

◆ rtc_source_sel_t

enum rtc_source_sel_t

Source select.

Enumerator
RTC_SOURCE_LOSC | LOSC
RTC_SOURCE_LRC | LRC
RTC_SOURCE_HRC_DIV_1M | HRC divide to 1MHz
RTC_SOURCE_HOSC_DIV_1M | HOSC divide to 1MHz

Definition at line 78 of file ald_rtc.h.

78 {
79 RTC_SOURCE_LOSC = 0x0U,
80 RTC_SOURCE_LRC = 0x1U,
81 RTC_SOURCE_HRC_DIV_1M = 0x2U,
82 RTC_SOURCE_HOSC_DIV_1M = 0x3U,
83 } rtc_source_sel_t;
rtc_source_sel_t
rtc_source_sel_t
Source select.
Definition: ald_rtc.h:78
RTC_SOURCE_HRC_DIV_1M
Definition: ald_rtc.h:81
RTC_SOURCE_LRC
Definition: ald_rtc.h:80
RTC_SOURCE_LOSC
Definition: ald_rtc.h:79
RTC_SOURCE_HOSC_DIV_1M
Definition: ald_rtc.h:82

◆ rtc_sub_second_mask_t

enum rtc_sub_second_mask_t

Alarm sub-second mask.

Enumerator
RTC_ALARM_SS_MASK_NONE | Mask is disable
RTC_ALARM_SS_MASK_14_1 | Mask bit(1-14)
RTC_ALARM_SS_MASK_14_2 | Mask bit(2-14)
RTC_ALARM_SS_MASK_14_3 | Mask bit(3-14)
RTC_ALARM_SS_MASK_14_4 | Mask bit(4-14)
RTC_ALARM_SS_MASK_14_5 | Mask bit(5-14)
RTC_ALARM_SS_MASK_14_6 | Mask bit(6-14)
RTC_ALARM_SS_MASK_14_7 | Mask bit(7-14)
RTC_ALARM_SS_MASK_14_8 | Mask bit(8-14)
RTC_ALARM_SS_MASK_14_9 | Mask bit(9-14)
RTC_ALARM_SS_MASK_14_10 | Mask bit(10-14)
RTC_ALARM_SS_MASK_14_11 | Mask bit(11-14)
RTC_ALARM_SS_MASK_14_12 | Mask bit(12-14)
RTC_ALARM_SS_MASK_14_13 | Mask bit(13-14)
RTC_ALARM_SS_MASK_14 | Mask bit14
RTC_ALARM_SS_MASK_ALL | Mask bit(0-14)

Definition at line 136 of file ald_rtc.h.

136 {
137 RTC_ALARM_SS_MASK_NONE = 0xFU,
138 RTC_ALARM_SS_MASK_14_1 = 0x1U,
139 RTC_ALARM_SS_MASK_14_2 = 0x2U,
140 RTC_ALARM_SS_MASK_14_3 = 0x3U,
141 RTC_ALARM_SS_MASK_14_4 = 0x4U,
142 RTC_ALARM_SS_MASK_14_5 = 0x5U,
143 RTC_ALARM_SS_MASK_14_6 = 0x6U,
144 RTC_ALARM_SS_MASK_14_7 = 0x7U,
145 RTC_ALARM_SS_MASK_14_8 = 0x8U,
146 RTC_ALARM_SS_MASK_14_9 = 0x9U,
147 RTC_ALARM_SS_MASK_14_10 = 0xAU,
148 RTC_ALARM_SS_MASK_14_11 = 0xBU,
149 RTC_ALARM_SS_MASK_14_12 = 0xCU,
150 RTC_ALARM_SS_MASK_14_13 = 0xDU,
151 RTC_ALARM_SS_MASK_14 = 0xEU,
152 RTC_ALARM_SS_MASK_ALL = 0x0U,
153 } rtc_sub_second_mask_t;
RTC_ALARM_SS_MASK_14_1
Definition: ald_rtc.h:138
RTC_ALARM_SS_MASK_14_11
Definition: ald_rtc.h:148
RTC_ALARM_SS_MASK_14_8
Definition: ald_rtc.h:145
RTC_ALARM_SS_MASK_14_13
Definition: ald_rtc.h:150
RTC_ALARM_SS_MASK_14_9
Definition: ald_rtc.h:146
RTC_ALARM_SS_MASK_14_3
Definition: ald_rtc.h:140
RTC_ALARM_SS_MASK_14_2
Definition: ald_rtc.h:139
rtc_sub_second_mask_t
rtc_sub_second_mask_t
Alarm sub-second mask.
Definition: ald_rtc.h:136
RTC_ALARM_SS_MASK_14
Definition: ald_rtc.h:151
RTC_ALARM_SS_MASK_14_10
Definition: ald_rtc.h:147
RTC_ALARM_SS_MASK_14_6
Definition: ald_rtc.h:143
RTC_ALARM_SS_MASK_14_7
Definition: ald_rtc.h:144
RTC_ALARM_SS_MASK_14_4
Definition: ald_rtc.h:141
RTC_ALARM_SS_MASK_ALL
Definition: ald_rtc.h:152
RTC_ALARM_SS_MASK_14_5
Definition: ald_rtc.h:142
RTC_ALARM_SS_MASK_14_12
Definition: ald_rtc.h:149
RTC_ALARM_SS_MASK_NONE
Definition: ald_rtc.h:137

◆ rtc_tamper_duration_t

enum rtc_tamper_duration_t

Tamper filter time.

Enumerator
RTC_TAMPER_DURATION_1 | Duration 1 sampling
RTC_TAMPER_DURATION_2 | Duration 2 sampling
RTC_TAMPER_DURATION_4 | Duration 4 sampling
RTC_TAMPER_DURATION_8 | Duration 8 sampling

Definition at line 227 of file ald_rtc.h.

227 {
228 RTC_TAMPER_DURATION_1 = 0U,
229 RTC_TAMPER_DURATION_2 = 1U,
230 RTC_TAMPER_DURATION_4 = 2U,
231 RTC_TAMPER_DURATION_8 = 3U,
232 } rtc_tamper_duration_t;
RTC_TAMPER_DURATION_4
Definition: ald_rtc.h:230
rtc_tamper_duration_t
rtc_tamper_duration_t
Tamper filter time.
Definition: ald_rtc.h:227
RTC_TAMPER_DURATION_2
Definition: ald_rtc.h:229
RTC_TAMPER_DURATION_1
Definition: ald_rtc.h:228
RTC_TAMPER_DURATION_8
Definition: ald_rtc.h:231

◆ rtc_tamper_idx_t

enum rtc_tamper_idx_t

Index of tamper.

Enumerator
RTC_TAMPER_0 | Tamper0
RTC_TAMPER_1 | Tamper1

Definition at line 197 of file ald_rtc.h.

197 {
198 RTC_TAMPER_0 = 0U,
199 RTC_TAMPER_1 = 1U,
200 } rtc_tamper_idx_t;
RTC_TAMPER_0
Definition: ald_rtc.h:198
rtc_tamper_idx_t
rtc_tamper_idx_t
Index of tamper.
Definition: ald_rtc.h:197
RTC_TAMPER_1
Definition: ald_rtc.h:199

◆ rtc_tamper_sampling_freq_t

enum rtc_tamper_sampling_freq_t

Tamper sampling frequency.

Enumerator
RTC_TAMPER_SAMPLING_FREQ_32768 | RTCCLK / 32768
RTC_TAMPER_SAMPLING_FREQ_16384 | RTCCLK / 16384
RTC_TAMPER_SAMPLING_FREQ_8192 | RTCCLK / 8192
RTC_TAMPER_SAMPLING_FREQ_4096 | RTCCLK / 4096
RTC_TAMPER_SAMPLING_FREQ_2048 | RTCCLK / 2048
RTC_TAMPER_SAMPLING_FREQ_1024 | RTCCLK / 1024
RTC_TAMPER_SAMPLING_FREQ_512 | RTCCLK / 512
RTC_TAMPER_SAMPLING_FREQ_256 | RTCCLK / 256

Definition at line 213 of file ald_rtc.h.

213 {
214 RTC_TAMPER_SAMPLING_FREQ_32768 = 0U,
215 RTC_TAMPER_SAMPLING_FREQ_16384 = 1U,
216 RTC_TAMPER_SAMPLING_FREQ_8192 = 2U,
217 RTC_TAMPER_SAMPLING_FREQ_4096 = 3U,
218 RTC_TAMPER_SAMPLING_FREQ_2048 = 4U,
219 RTC_TAMPER_SAMPLING_FREQ_1024 = 5U,
220 RTC_TAMPER_SAMPLING_FREQ_512 = 6U,
221 RTC_TAMPER_SAMPLING_FREQ_256 = 7U,
222 } rtc_tamper_sampling_freq_t;
RTC_TAMPER_SAMPLING_FREQ_512
Definition: ald_rtc.h:220
RTC_TAMPER_SAMPLING_FREQ_256
Definition: ald_rtc.h:221
RTC_TAMPER_SAMPLING_FREQ_4096
Definition: ald_rtc.h:217
rtc_tamper_sampling_freq_t
rtc_tamper_sampling_freq_t
Tamper sampling frequency.
Definition: ald_rtc.h:213
RTC_TAMPER_SAMPLING_FREQ_32768
Definition: ald_rtc.h:214
RTC_TAMPER_SAMPLING_FREQ_8192
Definition: ald_rtc.h:216
RTC_TAMPER_SAMPLING_FREQ_16384
Definition: ald_rtc.h:215
RTC_TAMPER_SAMPLING_FREQ_2048
Definition: ald_rtc.h:218
RTC_TAMPER_SAMPLING_FREQ_1024
Definition: ald_rtc.h:219

◆ rtc_tamper_trigger_t

enum rtc_tamper_trigger_t

Tamper trigger type.

Enumerator
RTC_TAMPER_TRIGGER_LOW | High trigger
RTC_TAMPER_TRIGGER_HIGH | Low trigger

Definition at line 205 of file ald_rtc.h.

205 {
206 RTC_TAMPER_TRIGGER_LOW = 0U,
207 RTC_TAMPER_TRIGGER_HIGH = 1U,
208 } rtc_tamper_trigger_t;
rtc_tamper_trigger_t
rtc_tamper_trigger_t
Tamper trigger type.
Definition: ald_rtc.h:205
RTC_TAMPER_TRIGGER_LOW
Definition: ald_rtc.h:206
RTC_TAMPER_TRIGGER_HIGH
Definition: ald_rtc.h:207

◆ rtc_ts_signal_sel_t

enum rtc_ts_signal_sel_t

Time stamp signel select.

Enumerator
RTC_TS_SIGNAL_SEL_TAMPER0 | Select tamper0
RTC_TS_SIGNAL_SEL_TAMPER1 | Select tamper1

Definition at line 181 of file ald_rtc.h.

181 {
182 RTC_TS_SIGNAL_SEL_TAMPER0 = 0U,
183 RTC_TS_SIGNAL_SEL_TAMPER1 = 1U,
184 } rtc_ts_signal_sel_t;
RTC_TS_SIGNAL_SEL_TAMPER0
Definition: ald_rtc.h:182
RTC_TS_SIGNAL_SEL_TAMPER1
Definition: ald_rtc.h:183
rtc_ts_signal_sel_t
rtc_ts_signal_sel_t
Time stamp signel select.
Definition: ald_rtc.h:181

◆ rtc_ts_trigger_style_t

enum rtc_ts_trigger_style_t

Time stamp trigger style.

Enumerator
RTC_TS_RISING_EDGE | Rising edge
RTC_TS_FALLING_EDGE | Falling edge

Definition at line 189 of file ald_rtc.h.

189 {
190 RTC_TS_RISING_EDGE = 0U,
191 RTC_TS_FALLING_EDGE = 1U,
192 } rtc_ts_trigger_style_t;
RTC_TS_RISING_EDGE
Definition: ald_rtc.h:190
RTC_TS_FALLING_EDGE
Definition: ald_rtc.h:191
rtc_ts_trigger_style_t
rtc_ts_trigger_style_t
Time stamp trigger style.
Definition: ald_rtc.h:189

◆ rtc_wakeup_clock_t

enum rtc_wakeup_clock_t

Wake-up clock.

Enumerator
RTC_WAKEUP_CLOCK_DIV_16 | RTCCLK / 16
RTC_WAKEUP_CLOCK_DIV_8 | RTCCLK / 8
RTC_WAKEUP_CLOCK_DIV_4 | RTCCLK / 4
RTC_WAKEUP_CLOCK_DIV_2 | RTCCLK / 2
RTC_WAKEUP_CLOCK_1HZ | 1Hz
RTC_WAKEUP_CLOCK_1HZ_PULS | 1Hz and WUT + 65536

Definition at line 248 of file ald_rtc.h.

248 {
249 RTC_WAKEUP_CLOCK_DIV_16 = 0U,
250 RTC_WAKEUP_CLOCK_DIV_8 = 1U,
251 RTC_WAKEUP_CLOCK_DIV_4 = 2U,
252 RTC_WAKEUP_CLOCK_DIV_2 = 3U,
253 RTC_WAKEUP_CLOCK_1HZ = 4U,
254 RTC_WAKEUP_CLOCK_1HZ_PULS = 6U,
255 } rtc_wakeup_clock_t;
RTC_WAKEUP_CLOCK_DIV_16
Definition: ald_rtc.h:249
RTC_WAKEUP_CLOCK_DIV_8
Definition: ald_rtc.h:250
RTC_WAKEUP_CLOCK_DIV_2
Definition: ald_rtc.h:252
RTC_WAKEUP_CLOCK_1HZ
Definition: ald_rtc.h:253
RTC_WAKEUP_CLOCK_DIV_4
Definition: ald_rtc.h:251
RTC_WAKEUP_CLOCK_1HZ_PULS
Definition: ald_rtc.h:254
rtc_wakeup_clock_t
rtc_wakeup_clock_t
Wake-up clock.
Definition: ald_rtc.h:248

◆ rtc_week_day_sel_t

enum rtc_week_day_sel_t

Alarm select week or day.

Enumerator
RTC_SELECT_DAY | Alarm select day
RTC_SELECT_WEEK | Alarm select week

Definition at line 157 of file ald_rtc.h.

157 {
158 RTC_SELECT_DAY = 0x0U,
159 RTC_SELECT_WEEK = 0x1U,
160 } rtc_week_day_sel_t;
RTC_SELECT_WEEK
Definition: ald_rtc.h:159
RTC_SELECT_DAY
Definition: ald_rtc.h:158
rtc_week_day_sel_t
rtc_week_day_sel_t
Alarm select week or day.
Definition: ald_rtc.h:157


ALD User Manual: rtc_init_t Struct Reference

Data Fields
rtc_init_t Struct Reference
EASTSOFT ES32F3xx ALD » RTC » RTC Public Types

Initialization structure. More...

#include <ald_rtc.h>

Data Fields

rtc_hour_format_t hour_format
uint32_t | asynch_pre_div
uint32_t | synch_pre_div
rtc_output_select_t output
rtc_output_polarity_t output_polarity

Detailed Description

Initialization structure.

Definition at line 67 of file ald_rtc.h.

Field Documentation

◆ asynch_pre_div

uint32_t asynch_pre_div

Asynchronous predivider value

Definition at line 69 of file ald_rtc.h.

◆ hour_format

rtc_hour_format_t hour_format

Hours format

Definition at line 68 of file ald_rtc.h.

◆ output

rtc_output_select_t output

Output signal type

Definition at line 71 of file ald_rtc.h.

◆ output_polarity

rtc_output_polarity_t output_polarity

Output polarity

Definition at line 72 of file ald_rtc.h.

◆ synch_pre_div

uint32_t synch_pre_div

Synchronous predivider value

Definition at line 70 of file ald_rtc.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_rtc.h


ALD User Manual: rtc_time_t Struct Reference

Data Fields
rtc_time_t Struct Reference
EASTSOFT ES32F3xx ALD » RTC » RTC Public Types

Time structure. More...

#include <ald_rtc.h>

Data Fields

uint8_t | hour
uint8_t | minute
uint8_t | second
uint16_t | sub_sec

Detailed Description

Time structure.

Definition at line 88 of file ald_rtc.h.

Field Documentation

◆ hour

uint8_t hour

Hours

Definition at line 89 of file ald_rtc.h.

◆ minute

uint8_t minute

Minutes

Definition at line 90 of file ald_rtc.h.

◆ second

uint8_t second

Seconds

Definition at line 91 of file ald_rtc.h.

◆ sub_sec

uint16_t sub_sec

Sub-seconds

Definition at line 92 of file ald_rtc.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_rtc.h


ALD User Manual: rtc_date_t Struct Reference

Data Fields
rtc_date_t Struct Reference
EASTSOFT ES32F3xx ALD » RTC » RTC Public Types

Date structure. More...

#include <ald_rtc.h>

Data Fields

uint8_t | week
uint8_t | day
uint8_t | month
uint8_t | year

Detailed Description

Date structure.

Definition at line 98 of file ald_rtc.h.

Field Documentation

◆ day

uint8_t day

days

Definition at line 100 of file ald_rtc.h.

◆ month

uint8_t month

months

Definition at line 101 of file ald_rtc.h.

◆ week

uint8_t week

Weeks

Definition at line 99 of file ald_rtc.h.

◆ year

uint8_t year

years

Definition at line 102 of file ald_rtc.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_rtc.h


ALD User Manual: rtc_alarm_t Struct Reference

Data Fields
rtc_alarm_t Struct Reference
EASTSOFT ES32F3xx ALD » RTC » RTC Public Types

Alarm structure. More...

#include <ald_rtc.h>

Collaboration diagram for rtc_alarm_t:
[legend]

Data Fields

rtc_alarm_idx_t idx
rtc_time_t time
uint32_t mask
rtc_sub_second_mask_t ss_mask
rtc_week_day_sel_t sel
union {
uint8_t week
uint8_t day
};

Detailed Description

Alarm structure.

Definition at line 165 of file ald_rtc.h.

Field Documentation

◆ @3

union { ... }

◆ day

uint8_t day

Alarm select day

Definition at line 174 of file ald_rtc.h.

◆ idx

rtc_alarm_idx_t idx

Index of alarm

Definition at line 166 of file ald_rtc.h.

◆ mask

uint32_t mask

Alarm mask

Definition at line 168 of file ald_rtc.h.

◆ sel

rtc_week_day_sel_t sel

Select week or day

Definition at line 170 of file ald_rtc.h.

◆ ss_mask

rtc_sub_second_mask_t ss_mask

Alarm sub-second mask

Definition at line 169 of file ald_rtc.h.

◆ time

rtc_time_t time

Time structure

Definition at line 167 of file ald_rtc.h.

◆ week

uint8_t week

Alarm select week

Definition at line 173 of file ald_rtc.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_rtc.h


ALD User Manual: rtc_tamper_t Struct Reference

Data Fields
rtc_tamper_t Struct Reference
EASTSOFT ES32F3xx ALD » RTC » RTC Public Types

Tamper structure. More...

#include <ald_rtc.h>

Data Fields

rtc_tamper_idx_t idx
rtc_tamper_trigger_t trig
rtc_tamper_sampling_freq_t freq
rtc_tamper_duration_t dur
type_func_t ts

Detailed Description

Tamper structure.

Definition at line 237 of file ald_rtc.h.

Field Documentation

◆ dur

rtc_tamper_duration_t dur

Filter time

Definition at line 241 of file ald_rtc.h.

◆ freq

rtc_tamper_sampling_freq_t freq

Sampling frequency

Definition at line 240 of file ald_rtc.h.

◆ idx

rtc_tamper_idx_t idx

Index of tamper

Definition at line 238 of file ald_rtc.h.

◆ trig

rtc_tamper_trigger_t trig

Trigger type

Definition at line 239 of file ald_rtc.h.

◆ ts

type_func_t ts

Enable/Disable trigger time stamp event

Definition at line 242 of file ald_rtc.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_rtc.h


ALD User Manual: rtc_cali_t Struct Reference

Data Fields
rtc_cali_t Struct Reference
EASTSOFT ES32F3xx ALD » RTC » RTC Public Types

Calibration structure. More...

#include <ald_rtc.h>

Data Fields

rtc_cali_freq_t cali_freq
rtc_cali_tc_t tc
rtc_cali_calc_freq_t calc_freq
rtc_cali_calc_t calc
type_func_t acc

Detailed Description

Calibration structure.

Definition at line 318 of file ald_rtc.h.

Field Documentation

◆ acc

type_func_t acc

Enable/Disable decimal accumulate

Definition at line 323 of file ald_rtc.h.

◆ calc

rtc_cali_calc_t calc

algorithm

Definition at line 322 of file ald_rtc.h.

◆ calc_freq

rtc_cali_calc_freq_t calc_freq

Calculate frequency

Definition at line 321 of file ald_rtc.h.

◆ cali_freq

rtc_cali_freq_t cali_freq

calibrate frequency

Definition at line 319 of file ald_rtc.h.

◆ tc

rtc_cali_tc_t tc

Temperature compensate type

Definition at line 320 of file ald_rtc.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_rtc.h


ALD User Manual: RTC Public Macros

Macros
RTC Public Macros
EASTSOFT ES32F3xx ALD » RTC
Collaboration diagram for RTC Public Macros:

Macros

#define | RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55U))
#define | RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0U))
#define | RTC_BY_PASS_ENABLE()
#define | RTC_BY_PASS_DISABLE()
#define | RTC_SUMMER_TIME_ENABLE()
#define | RTC_SUMMER_TIME_DISABLE()
#define | RTC_WINTER_TIME_ENABLE()
#define | RTC_WINTER_TIME_DISABLE()

Detailed Description

Macro Definition Documentation

◆ RTC_BY_PASS_DISABLE

#define RTC_BY_PASS_DISABLE ( )
Value:
do { \
RTC_UNLOCK(); \
CLEAR_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \
RTC_LOCK(); \
} while (0)

Definition at line 386 of file ald_rtc.h.

◆ RTC_BY_PASS_ENABLE

#define RTC_BY_PASS_ENABLE ( )
Value:
do { \
RTC_UNLOCK(); \
SET_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \
RTC_LOCK(); \
} while (0)

Definition at line 380 of file ald_rtc.h.

◆ RTC_LOCK

#define RTC_LOCK ( ) (WRITE_REG(RTC->WPR, 0x0U))

Definition at line 379 of file ald_rtc.h.

◆ RTC_SUMMER_TIME_DISABLE

#define RTC_SUMMER_TIME_DISABLE ( )
Value:
do { \
RTC_UNLOCK(); \
CLEAR_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \
RTC_LOCK(); \
} while (0)

Definition at line 398 of file ald_rtc.h.

◆ RTC_SUMMER_TIME_ENABLE

#define RTC_SUMMER_TIME_ENABLE ( )
Value:
do { \
RTC_UNLOCK(); \
SET_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \
RTC_LOCK(); \
} while (0)

Definition at line 392 of file ald_rtc.h.

◆ RTC_UNLOCK

#define RTC_UNLOCK ( ) (WRITE_REG(RTC->WPR, 0x55AAAA55U))

Definition at line 378 of file ald_rtc.h.

◆ RTC_WINTER_TIME_DISABLE

#define RTC_WINTER_TIME_DISABLE ( )
Value:
do { \
RTC_UNLOCK(); \
CLEAR_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \
RTC_LOCK(); \
} while (0)

Definition at line 410 of file ald_rtc.h.

◆ RTC_WINTER_TIME_ENABLE

#define RTC_WINTER_TIME_ENABLE ( )
Value:
do { \
RTC_UNLOCK(); \
SET_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \
RTC_LOCK(); \
} while (0)

Definition at line 404 of file ald_rtc.h.


ALD User Manual: RTC Private Functions

Functions
RTC Private Functions
EASTSOFT ES32F3xx ALD » RTC
Collaboration diagram for RTC Private Functions:

Functions

static uint32_t | bcd_to_dec (uint32_t bcd)
Converts form 2 digit BCD to Binary. More...
static uint32_t | dec_to_bcd (uint32_t dec)
Converts a 2 digit decimal to BCD format. More...
static int32_t | rtc_consistency_check (rtc_time_t *t_last, rtc_date_t *d_last, rtc_time_t *time, rtc_date_t *date)
Time and Date consistency check. More...

Detailed Description

Function Documentation

◆ bcd_to_dec()

static uint32_t bcd_to_dec ( uint32_t bcd )
static

Converts form 2 digit BCD to Binary.

Parameters
bcd BCD value to be converted.
Return values
Converted word.

Definition at line 143 of file ald_rtc.c.

144 {
145 return ((bcd & 0xF) + ((bcd >> 4) & 0xF) * 10);
146 }

◆ dec_to_bcd()

static uint32_t dec_to_bcd ( uint32_t dec )
static

Converts a 2 digit decimal to BCD format.

Parameters
dec Byte to be converted.
Return values
Converted byte.

Definition at line 153 of file ald_rtc.c.

154 {
155 return (((dec / 10) << 4) | (dec % 10));
156 }

◆ rtc_consistency_check()

static int32_t rtc_consistency_check | ( | rtc_time_t * | t_last,
 |  | rtc_date_t * | d_last,
 |  | rtc_time_t * | time,
 |  | rtc_date_t * | date
 | ) |  |
static

Time and Date consistency check.

Parameters
t_last | Last time.
d_last | Last date.
time | Current time.
date | Current time.
Return values
status 0 - Not consistency 1 - Consistency

Definition at line 168 of file ald_rtc.c.

170 {
171 if (t_last->second != time->second)
172 return 0;
173 if (t_last->minute != time->minute)
174 return 0;
175 if (t_last->hour != time->hour)
176 return 0;
177 if (d_last->day != date->day)
178 return 0;
179 if (d_last->month != date->month)
180 return 0;
181 if (d_last->year != date->year)
182 return 0;
183
184 return 1;
185 }
rtc_date_t::day
uint8_t day
Definition: ald_rtc.h:100
rtc_date_t::month
uint8_t month
Definition: ald_rtc.h:101
rtc_time_t::minute
uint8_t minute
Definition: ald_rtc.h:90
rtc_time_t::hour
uint8_t hour
Definition: ald_rtc.h:89
rtc_time_t::second
uint8_t second
Definition: ald_rtc.h:91
rtc_date_t::year
uint8_t year
Definition: ald_rtc.h:102


ALD User Manual: RTCHW

Modules
RTCHW
EASTSOFT ES32F3xx ALD

RTCHW module driver. More...

Collaboration diagram for RTCHW:

Modules

RTCHW Public Functions
RTCHW Public Types
RTCHW Private Macros
RTCHW Private Functions

Detailed Description

RTCHW module driver.


ALD User Manual: RTCHW Public Functions

Functions
RTCHW Public Functions
EASTSOFT ES32F3xx ALD » RTCHW
Collaboration diagram for RTCHW Public Functions:

Functions

void ald_rtc_hw_auto_cali (rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode)
Hardware automatic calibate. More...

Detailed Description

Function Documentation

◆ ald_rtc_hw_auto_cali()

void ald_rtc_hw_auto_cali | ( | rtc_hw_cali_offset_t * | config,
 |  | rtc_hw_cali_mode_t | mode
 | ) |  |

Hardware automatic calibate.

Parameters
config | pointer to rtc_hw_cali_offset_t structure.
mode | Running mode, see rtc_hw_cali_mode_t
Return values
None

Definition at line 124 of file ald_rtchw.c.

125 {
126 uint8_t shift[8] = {0, 2, 4, 6, 8, 8, 8, 8};
127 uint8_t tmp;
128 uint32_t v = 0;
129 uint16_t temp_calf;
130
131 if (!(rtc_hw_auto_check(config, mode)))
132 return;
133
134 RTC_UNLOCK();
135 RTC_CALI_UNLOCK();
136 TSENSE_UNLOCK();
137
138 temp_calf = (uint16_t)RTC->CALDR;
139 while ((READ_BITS(RTC->IFR, RTC_IFR_TCCF_MSK, RTC_IFR_TCCF_POS) == 1) && (v < 0x20000)) /* no usr trig */
140 v++;
141
142 MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, 0 << RTC_CALCON_TCM_POSS); /* disable auto compensation */
143 MODIFY_REG(TSENSE->CR, TSENSE_CR_REQEN_MSK, 0 << TSENSE_CR_REQEN_POS); /* disable temp */
144
145 RTC->CALDR = temp_calf;
146 delay_losc_clk(3);
147
148 if (mode == RTC_CALI_MODE_NORMAL) {
149 v = RTC->CALCON & ~0x01F0000F;
150 RTC->CALCON = v | (RTCINFO->RTC_CALCR & 0x01F0000F);
151 }
152 else {
153 v = RTC->CALCON & ~0x0180000F;
154 RTC->CALCON = v | (RTCINFO->RTC_CALCR & 0x0180000F);
155 MODIFY_REG(RTC->CALCON, RTC_CALCON_TCP_MSK, 7 << RTC_CALCON_TCP_POSS); // when sleep mode, caluate once in 1h
156 }
157
158 RTC->TEMPBDR = RTCINFO->RTC_TEMPBDR + config->offset_rtc_bdr;
159 RTC->LTAXR = RTCINFO->RTC_LTAXR + config->offset_ltaxr;
160 RTC->HTAXR = RTCINFO->RTC_HTAXR + config->offset_htaxr;
161 RTC->LTCAR = RTCINFO->RTC_LTCAR + config->offset_ltcar;
162 RTC->LTCBR = RTCINFO->RTC_LTCBR + config->offset_ltcbr;
163 RTC->LTCCR = RTCINFO->RTC_LTCCR + config->offset_ltccr;
164 RTC->LTCDR = RTCINFO->RTC_LTCDR + config->offset_ltcdr;
165 RTC->LTCER = RTCINFO->RTC_LTCER + config->offset_ltcer;
166 RTC->HTCAR = RTCINFO->RTC_HTCAR + config->offset_htcar;
167 RTC->HTCBR = RTCINFO->RTC_HTCBR + config->offset_htcbr;
168 RTC->HTCCR = RTCINFO->RTC_HTCCR + config->offset_htccr;
169 RTC->HTCDR = RTCINFO->RTC_HTCDR + config->offset_htcdr;
170 RTC->HTCER = RTCINFO->RTC_HTCER + config->offset_htcer;
171 MODIFY_REG(RTC->CON, RTC_CON_CKOS_MSK, 5 << RTC_CON_CKOS_POSS); /* output accuracy 1Hz */
172
173 v = TSENSE->CR & ~0x00007700;
174 TSENSE->CR = v | (RTCINFO->TEMP_CR & 0x00007700);
175 TSENSE->HTGR = RTCINFO->TEMP_HTGR + config->offset_htgr;
176 TSENSE->LTGR = RTCINFO->TEMP_LTGR + config->offset_ltgr;
177 tmp = READ_BITS(RTCINFO->TEMP_CR, TSENSE_CR_TOM_MSK, TSENSE_CR_TOM_POSS);
178 TSENSE->TCALBDR = ((RTCINFO->TEMP_TCALBDR & 0x1FFFFFF) >> shift[tmp]) + config->offset_tcalbdr;
179 TSENSE->TBDR = RTCINFO->TEMP_TBDR + config->offset_temp_bdr;
180
181 delay_losc_clk(3);
182 tmp = READ_BITS(RTCINFO->TEMP_CR, TSENSE_CR_REQEN_MSK, TSENSE_CR_REQEN_POS);
183 MODIFY_REG(TSENSE->CR, TSENSE_CR_REQEN_MSK, tmp << TSENSE_CR_REQEN_POS);
184 MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, 3 << RTC_CALCON_TCM_POSS); /* usr trig */
185
186 delay_losc_clk(3);
187 MODIFY_REG(RTC->TEMPR, RTC_TEMPR_VAL_MSK, 1 << RTC_TEMPR_VAL_POSS); /* trig immediate*/
188
189 delay_losc_clk(3);
190 tmp = READ_BITS(RTCINFO->RTC_CALCR, RTC_CALCON_TCM_MSK, RTC_CALCON_TCM_POSS);
191 MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, tmp << RTC_CALCON_TCM_POSS);
192
193 RTC_CALI_LOCK();
194 RTC_LOCK();
195 TSENSE_LOCK();
196 return;
197 }
rtc_hw_cali_offset_t::offset_ltccr
int16_t offset_ltccr
Definition: ald_rtchw.h:91
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
rtc_hw_cali_offset_t::offset_ltcer
int16_t offset_ltcer
Definition: ald_rtchw.h:99
rtc_hw_cali_offset_t::offset_rtc_bdr
int16_t offset_rtc_bdr
Definition: ald_rtchw.h:85
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
TSENSE_UNLOCK
#define TSENSE_UNLOCK()
Definition: ald_rtchw.h:120
rtc_hw_cali_offset_t::offset_htgr
int16_t offset_htgr
Definition: ald_rtchw.h:98
rtc_hw_cali_offset_t::offset_ltaxr
int16_t offset_ltaxr
Definition: ald_rtchw.h:87
rtc_hw_cali_offset_t::offset_temp_bdr
int16_t offset_temp_bdr
Definition: ald_rtchw.h:86
rtc_hw_cali_offset_t::offset_ltcar
int16_t offset_ltcar
Definition: ald_rtchw.h:89
delay_losc_clk
static void delay_losc_clk(uint16_t u)
delay losc clock
Definition: ald_rtchw.c:37
RTCINFO
#define RTCINFO
Definition: ald_rtchw.h:123
rtc_hw_cali_offset_t::offset_htcar
int16_t offset_htcar
Definition: ald_rtchw.h:93
rtc_hw_cali_offset_t::offset_htccr
int16_t offset_htccr
Definition: ald_rtchw.h:95
rtc_hw_cali_offset_t::offset_htcer
int16_t offset_htcer
Definition: ald_rtchw.h:100
rtc_hw_cali_offset_t::offset_htcdr
int16_t offset_htcdr
Definition: ald_rtchw.h:96
rtc_hw_cali_offset_t::offset_htcbr
int16_t offset_htcbr
Definition: ald_rtchw.h:94
rtc_hw_cali_offset_t::offset_htaxr
int16_t offset_htaxr
Definition: ald_rtchw.h:88
RTC_CALI_LOCK
#define RTC_CALI_LOCK()
Definition: ald_rtc.h:424
RTC_CALI_UNLOCK
#define RTC_CALI_UNLOCK()
Definition: ald_rtc.h:423
TSENSE_LOCK
#define TSENSE_LOCK()
Definition: ald_rtchw.h:119
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378
rtc_hw_cali_offset_t::offset_ltcbr
int16_t offset_ltcbr
Definition: ald_rtchw.h:90
rtc_hw_auto_check
static uint8_t rtc_hw_auto_check(rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode)
Check parameter for calibation.
Definition: ald_rtchw.c:54
RTC_CALI_MODE_NORMAL
Definition: ald_rtchw.h:42
rtc_hw_cali_offset_t::offset_tcalbdr
int16_t offset_tcalbdr
Definition: ald_rtchw.h:103
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
rtc_hw_cali_offset_t::offset_ltcdr
int16_t offset_ltcdr
Definition: ald_rtchw.h:92
rtc_hw_cali_offset_t::offset_ltgr
int16_t offset_ltgr
Definition: ald_rtchw.h:97


ALD User Manual: RTCHW Public Types

Data Structures | Enumerations
RTCHW Public Types
EASTSOFT ES32F3xx ALD » RTCHW
Collaboration diagram for RTCHW Public Types:

Data Structures

struct | RTCINFO_TypeDef
the parameters table of rtc calibration More...
struct | rtc_hw_cali_offset_t
Hardware calibration structure. More...

Enumerations

enum rtc_hw_cali_mode_t { RTC_CALI_MODE_NORMAL = 0U, RTC_CALI_MODE_SLEEP = 1U }
Hardware calibration algorithm. More...

Detailed Description

Enumeration Type Documentation

◆ rtc_hw_cali_mode_t

enum rtc_hw_cali_mode_t

Hardware calibration algorithm.

Enumerator
RTC_CALI_MODE_NORMAL | Normal mode
RTC_CALI_MODE_SLEEP | Low power mode

Definition at line 41 of file ald_rtchw.h.

41 {
42 RTC_CALI_MODE_NORMAL = 0U,
43 RTC_CALI_MODE_SLEEP = 1U,
44 } rtc_hw_cali_mode_t;
RTC_CALI_MODE_NORMAL
Definition: ald_rtchw.h:42
RTC_CALI_MODE_SLEEP
Definition: ald_rtchw.h:43
rtc_hw_cali_mode_t
rtc_hw_cali_mode_t
Hardware calibration algorithm.
Definition: ald_rtchw.h:41


ALD User Manual: RTCINFO_TypeDef Struct Reference

Data Fields
RTCINFO_TypeDef Struct Reference
EASTSOFT ES32F3xx ALD » RTCHW » RTCHW Public Types

the parameters table of rtc calibration More...

#include <ald_rtchw.h>

Data Fields

uint32_t | MODE_CALI
uint32_t | RTC_CALCR
uint32_t | RTC_TEMPBDR
uint32_t | TEMP_TBDR
uint32_t | RTC_LTAXR
uint32_t | RTC_HTAXR
uint32_t | RTC_LTCAR
uint32_t | RTC_LTCBR
uint32_t | RTC_LTCCR
uint32_t | RTC_LTCDR
uint32_t | RTC_HTCAR
uint32_t | RTC_HTCBR
uint32_t | RTC_HTCCR
uint32_t | RTC_HTCDR
uint32_t | TEMP_LTGR
uint32_t | TEMP_HTGR
uint32_t | TEMP_CR
uint32_t | rsv0
uint32_t | RTC_LTCER
uint32_t | RTC_HTCER
uint32_t | TEMP_PEAK
uint32_t | FREQ_PEAK
uint32_t | TEMP_CALI
uint32_t | TEMP_CALI_AFTER
uint32_t | TEMP_TCALBDR
uint32_t | TEMP_TCALBDR_MINUS
uint32_t | rsv1 [4]
uint32_t | SUM
uint32_t | SUM_MINUS

Detailed Description

the parameters table of rtc calibration

Definition at line 49 of file ald_rtchw.h.

Field Documentation

◆ FREQ_PEAK

uint32_t FREQ_PEAK

PEAK

Definition at line 71 of file ald_rtchw.h.

◆ MODE_CALI

uint32_t MODE_CALI

Calibration Mode

Definition at line 50 of file ald_rtchw.h.

◆ rsv0

uint32_t rsv0

Reserved

Definition at line 67 of file ald_rtchw.h.

◆ rsv1

uint32_t rsv1[4]

Reserved

Definition at line 76 of file ald_rtchw.h.

◆ RTC_CALCR

uint32_t RTC_CALCR

CALCR

Definition at line 51 of file ald_rtchw.h.

◆ RTC_HTAXR

uint32_t RTC_HTAXR

HTAXR

Definition at line 55 of file ald_rtchw.h.

◆ RTC_HTCAR

uint32_t RTC_HTCAR

HTCAR

Definition at line 60 of file ald_rtchw.h.

◆ RTC_HTCBR

uint32_t RTC_HTCBR

HTCBR

Definition at line 61 of file ald_rtchw.h.

◆ RTC_HTCCR

uint32_t RTC_HTCCR

HTCCR

Definition at line 62 of file ald_rtchw.h.

◆ RTC_HTCDR

uint32_t RTC_HTCDR

HTCDR

Definition at line 63 of file ald_rtchw.h.

◆ RTC_HTCER

uint32_t RTC_HTCER

HTCER

Definition at line 69 of file ald_rtchw.h.

◆ RTC_LTAXR

uint32_t RTC_LTAXR

LTAXR

Definition at line 54 of file ald_rtchw.h.

◆ RTC_LTCAR

uint32_t RTC_LTCAR

LTCAR

Definition at line 56 of file ald_rtchw.h.

◆ RTC_LTCBR

uint32_t RTC_LTCBR

LTCBR

Definition at line 57 of file ald_rtchw.h.

◆ RTC_LTCCR

uint32_t RTC_LTCCR

LTCCR

Definition at line 58 of file ald_rtchw.h.

◆ RTC_LTCDR

uint32_t RTC_LTCDR

LTCDR

Definition at line 59 of file ald_rtchw.h.

◆ RTC_LTCER

uint32_t RTC_LTCER

LTCER

Definition at line 68 of file ald_rtchw.h.

◆ RTC_TEMPBDR

uint32_t RTC_TEMPBDR

TEMPBDR

Definition at line 52 of file ald_rtchw.h.

◆ SUM

uint32_t SUM

SUM

Definition at line 77 of file ald_rtchw.h.

◆ SUM_MINUS

uint32_t SUM_MINUS

SUM_MINUS

Definition at line 78 of file ald_rtchw.h.

◆ TEMP_CALI

uint32_t TEMP_CALI

CALI

Definition at line 72 of file ald_rtchw.h.

◆ TEMP_CALI_AFTER

uint32_t TEMP_CALI_AFTER

AFTER

Definition at line 73 of file ald_rtchw.h.

◆ TEMP_CR

uint32_t TEMP_CR

CR

Definition at line 66 of file ald_rtchw.h.

◆ TEMP_HTGR

uint32_t TEMP_HTGR

HTGR

Definition at line 65 of file ald_rtchw.h.

◆ TEMP_LTGR

uint32_t TEMP_LTGR

LTGR

Definition at line 64 of file ald_rtchw.h.

◆ TEMP_PEAK

uint32_t TEMP_PEAK

PEAK

Definition at line 70 of file ald_rtchw.h.

◆ TEMP_TBDR

uint32_t TEMP_TBDR

TBDR

Definition at line 53 of file ald_rtchw.h.

◆ TEMP_TCALBDR

uint32_t TEMP_TCALBDR

TCALBDR

Definition at line 74 of file ald_rtchw.h.

◆ TEMP_TCALBDR_MINUS

uint32_t TEMP_TCALBDR_MINUS

TCALBDR_MINUS

Definition at line 75 of file ald_rtchw.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_rtchw.h


ALD User Manual: rtc_hw_cali_offset_t Struct Reference

Data Fields
rtc_hw_cali_offset_t Struct Reference
EASTSOFT ES32F3xx ALD » RTCHW » RTCHW Public Types

Hardware calibration structure. More...

#include <ald_rtchw.h>

Data Fields

int16_t | offset_rtc_bdr
int16_t | offset_temp_bdr
int16_t | offset_ltaxr
int16_t | offset_htaxr
int16_t | offset_ltcar
int16_t | offset_ltcbr
int16_t | offset_ltccr
int16_t | offset_ltcdr
int16_t | offset_htcar
int16_t | offset_htcbr
int16_t | offset_htccr
int16_t | offset_htcdr
int16_t | offset_ltgr
int16_t | offset_htgr
int16_t | offset_ltcer
int16_t | offset_htcer
int16_t | offset_temp_peak
int16_t | offset_freq_peak
int16_t | offset_tcalbdr
int16_t | crc
int16_t | rsv [8]

Detailed Description

Hardware calibration structure.

Definition at line 84 of file ald_rtchw.h.

Field Documentation

◆ crc

int16_t crc

offset:0x26

Definition at line 104 of file ald_rtchw.h.

◆ offset_freq_peak

int16_t offset_freq_peak

offset:0x22

Definition at line 102 of file ald_rtchw.h.

◆ offset_htaxr

int16_t offset_htaxr

offset:0x06

Definition at line 88 of file ald_rtchw.h.

◆ offset_htcar

int16_t offset_htcar

offset:0x10

Definition at line 93 of file ald_rtchw.h.

◆ offset_htcbr

int16_t offset_htcbr

offset:0x12

Definition at line 94 of file ald_rtchw.h.

◆ offset_htccr

int16_t offset_htccr

offset:0x14

Definition at line 95 of file ald_rtchw.h.

◆ offset_htcdr

int16_t offset_htcdr

offset:0x16

Definition at line 96 of file ald_rtchw.h.

◆ offset_htcer

int16_t offset_htcer

offset:0x1E

Definition at line 100 of file ald_rtchw.h.

◆ offset_htgr

int16_t offset_htgr

offset:0x1A

Definition at line 98 of file ald_rtchw.h.

◆ offset_ltaxr

int16_t offset_ltaxr

offset:0x04

Definition at line 87 of file ald_rtchw.h.

◆ offset_ltcar

int16_t offset_ltcar

offset:0x08

Definition at line 89 of file ald_rtchw.h.

◆ offset_ltcbr

int16_t offset_ltcbr

offset:0x0A

Definition at line 90 of file ald_rtchw.h.

◆ offset_ltccr

int16_t offset_ltccr

offset:0x0C

Definition at line 91 of file ald_rtchw.h.

◆ offset_ltcdr

int16_t offset_ltcdr

offset:0x0E

Definition at line 92 of file ald_rtchw.h.

◆ offset_ltcer

int16_t offset_ltcer

offset:0x1C

Definition at line 99 of file ald_rtchw.h.

◆ offset_ltgr

int16_t offset_ltgr

offset:0x18

Definition at line 97 of file ald_rtchw.h.

◆ offset_rtc_bdr

int16_t offset_rtc_bdr

offset:0x00

Definition at line 85 of file ald_rtchw.h.

◆ offset_tcalbdr

int16_t offset_tcalbdr

offset:0x24

Definition at line 103 of file ald_rtchw.h.

◆ offset_temp_bdr

int16_t offset_temp_bdr

offset:0x02

Definition at line 86 of file ald_rtchw.h.

◆ offset_temp_peak

int16_t offset_temp_peak

offset:0x20

Definition at line 101 of file ald_rtchw.h.

◆ rsv

int16_t rsv[8]

Definition at line 105 of file ald_rtchw.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_rtchw.h


ALD User Manual: RTCHW Private Macros

Macros
RTCHW Private Macros
EASTSOFT ES32F3xx ALD » RTCHW
Collaboration diagram for RTCHW Private Macros:

Macros

#define | TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0U))
#define | TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669U))
#define | RTCINFO ((RTCINFO_TypeDef *)0x81000U)

Detailed Description

Macro Definition Documentation

◆ RTCINFO

#define RTCINFO ((RTCINFO_TypeDef *)0x81000U)

Definition at line 123 of file ald_rtchw.h.

◆ TSENSE_LOCK

#define TSENSE_LOCK ( ) (WRITE_REG(TSENSE->WPR, 0x0U))

Definition at line 119 of file ald_rtchw.h.

◆ TSENSE_UNLOCK

#define TSENSE_UNLOCK ( ) (WRITE_REG(TSENSE->WPR, 0xA55A9669U))

Definition at line 120 of file ald_rtchw.h.


ALD User Manual: RTCHW Private Functions

Functions
RTCHW Private Functions
EASTSOFT ES32F3xx ALD » RTCHW
Collaboration diagram for RTCHW Private Functions:

Functions

static void | delay_losc_clk (uint16_t u)
delay losc clock More...
static uint8_t | rtc_hw_auto_check (rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode)
Check parameter for calibation. More...

Detailed Description

Function Documentation

◆ delay_losc_clk()

static void delay_losc_clk ( uint16_t u )
static

delay losc clock

Parameters
u clock numbers.
Return values
None.

Definition at line 37 of file ald_rtchw.c.

38 {
39 uint16_t i, j;
40
41 for (i = 0; i < u; i++) {
42 for (j = 0; j < 60; j++) {
43 __ASM volatile ("nop");
44 }
45 }
46 }

◆ rtc_hw_auto_check()

static uint8_t rtc_hw_auto_check | ( | rtc_hw_cali_offset_t * | config,
 |  | rtc_hw_cali_mode_t | mode
 | ) |  |
static

Check parameter for calibation.

Parameters
config | pointer to rtc_hw_cali_offset_t structure.
mode | Running mode, see rtc_hw_cali_mode_t.
Return values
Status.

Definition at line 54 of file ald_rtchw.c.

55 {
56 uint8_t tom = READ_BITS(TSENSE->CR, TSENSE_CR_TOM_MSK, TSENSE_CR_TOM_POSS);
57 uint8_t shift[8] = {0, 2, 4, 6, 8, 8, 8, 8};
58
59 if (mode == RTC_CALI_MODE_NORMAL) {
60 if ((RTC->CALCON & 0x1F3000F) != (RTCINFO->RTC_CALCR & 0x1F3000F))
61 return 1;
62 }
63 else {
64 if ((RTC->CALCON & 0x183000F) != (RTCINFO->RTC_CALCR & 0x183000F))
65 return 1;
66
67 if (READ_BITS(RTC->CALCON, RTC_CALCON_TCP_MSK, RTC_CALCON_TCP_POSS) != 7) /* when sleep mode */
68 return 1;
69 }
70
71 if ((TSENSE->CR & 0x7702) != (RTCINFO->TEMP_CR & 0x7702))
72 return 1;
73 if (RTC->TEMPBDR != RTCINFO->RTC_TEMPBDR + config->offset_rtc_bdr)
74 return 1;
75 if (RTC->LTAXR != RTCINFO->RTC_LTAXR + config->offset_ltaxr)
76 return 1;
77 if (RTC->HTAXR != RTCINFO->RTC_HTAXR + config->offset_htaxr)
78 return 1;
79 if (RTC->HTAXR != RTCINFO->RTC_HTCAR + config->offset_htcar)
80 return 1;
81 if (RTC->HTCBR != RTCINFO->RTC_HTCBR + config->offset_htcbr)
82 return 1;
83 if (RTC->HTCCR != RTCINFO->RTC_HTCCR + config->offset_htccr)
84 return 1;
85 if (RTC->HTCDR != RTCINFO->RTC_HTCDR + config->offset_htcdr)
86 return 1;
87 if (RTC->HTCER != RTCINFO->RTC_HTCER + config->offset_htcer)
88 return 1;
89 if (RTC->LTAXR != RTCINFO->RTC_LTCAR + config->offset_ltcar)
90 return 1;
91 if (RTC->LTCBR != RTCINFO->RTC_LTCBR + config->offset_ltcbr)
92 return 1;
93 if (RTC->LTCCR != RTCINFO->RTC_LTCCR + config->offset_ltccr)
94 return 1;
95 if (RTC->LTCDR != RTCINFO->RTC_LTCDR + config->offset_ltcdr)
96 return 1;
97 if (RTC->LTCER != RTCINFO->RTC_LTCER + config->offset_ltcer)
98 return 1;
99 if (TSENSE->TBDR != (RTCINFO->TEMP_TBDR & 0xFFFF) + config->offset_temp_bdr)
100 return 1;
101 if (TSENSE->LTGR != RTCINFO->TEMP_LTGR + config->offset_ltgr)
102 return 1;
103 if (TSENSE->HTGR != RTCINFO->TEMP_HTGR + config->offset_htgr)
104 return 1;
105 if (TSENSE->TCALBDR != (((RTCINFO->TEMP_TCALBDR & 0x1FFFFFF) >> shift[tom]) & 0x1FFFF)
106 + config->offset_tcalbdr)
107 return 1;
108
109 return 0;
110 }
rtc_hw_cali_offset_t::offset_ltccr
int16_t offset_ltccr
Definition: ald_rtchw.h:91
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
rtc_hw_cali_offset_t::offset_ltcer
int16_t offset_ltcer
Definition: ald_rtchw.h:99
rtc_hw_cali_offset_t::offset_rtc_bdr
int16_t offset_rtc_bdr
Definition: ald_rtchw.h:85
rtc_hw_cali_offset_t::offset_htgr
int16_t offset_htgr
Definition: ald_rtchw.h:98
rtc_hw_cali_offset_t::offset_ltaxr
int16_t offset_ltaxr
Definition: ald_rtchw.h:87
rtc_hw_cali_offset_t::offset_temp_bdr
int16_t offset_temp_bdr
Definition: ald_rtchw.h:86
rtc_hw_cali_offset_t::offset_ltcar
int16_t offset_ltcar
Definition: ald_rtchw.h:89
RTCINFO
#define RTCINFO
Definition: ald_rtchw.h:123
rtc_hw_cali_offset_t::offset_htcar
int16_t offset_htcar
Definition: ald_rtchw.h:93
rtc_hw_cali_offset_t::offset_htccr
int16_t offset_htccr
Definition: ald_rtchw.h:95
rtc_hw_cali_offset_t::offset_htcer
int16_t offset_htcer
Definition: ald_rtchw.h:100
rtc_hw_cali_offset_t::offset_htcdr
int16_t offset_htcdr
Definition: ald_rtchw.h:96
rtc_hw_cali_offset_t::offset_htcbr
int16_t offset_htcbr
Definition: ald_rtchw.h:94
rtc_hw_cali_offset_t::offset_htaxr
int16_t offset_htaxr
Definition: ald_rtchw.h:88
rtc_hw_cali_offset_t::offset_ltcbr
int16_t offset_ltcbr
Definition: ald_rtchw.h:90
RTC_CALI_MODE_NORMAL
Definition: ald_rtchw.h:42
rtc_hw_cali_offset_t::offset_tcalbdr
int16_t offset_tcalbdr
Definition: ald_rtchw.h:103
rtc_hw_cali_offset_t::offset_ltcdr
int16_t offset_ltcdr
Definition: ald_rtchw.h:92
rtc_hw_cali_offset_t::offset_ltgr
int16_t offset_ltgr
Definition: ald_rtchw.h:97


ALD User Manual: SPI

Modules
SPI
EASTSOFT ES32F3xx ALD

SPI module driver. More...

Collaboration diagram for SPI:

Modules

SPI Public Functions
SPI Private Functions
SPI Private functions.
SPI Public Types
SPI Public Macros
SPI Private Macros

Detailed Description

SPI module driver.


ALD User Manual: SPI Public Functions

Modules
SPI Public Functions
EASTSOFT ES32F3xx ALD » SPI
Collaboration diagram for SPI Public Functions:

Modules

Initialization functions
Initialization and Configuration functions.
IO fast functions
SPI Transmit and Receive functions.
IO operation functions
SPI Transmit and Receive functions.
Control functions
SPI Control functions.
Peripheral State and Errors functions
SPI State and Errors functions.

Detailed Description


ALD User Manual: Initialization functions

Functions
Initialization functions
EASTSOFT ES32F3xx ALD » SPI » SPI Public Functions

Initialization and Configuration functions. More...

Collaboration diagram for Initialization functions:

Functions

void | ald_spi_reset (spi_handle_t *hperh)
Reset the SPI peripheral. More...
ald_status_t | ald_spi_init (spi_handle_t *hperh)
Initializes the SPI mode according to the specified parameters in the SPI_init_t and create the associated handle. More...
ald_status_t | spi_fifo_threshold_config (spi_handle_t *hperh, uint8_t threshold)
Config the fifo threshold. More...

Detailed Description

Initialization and Configuration functions.

===============================================================================
             ##### Initialization and de-initialization functions #####
===============================================================================
   [..]  This subsection provides a set of functions allowing to initialize and
         reset the SPIx peripheral:

     (+) User must configure all related peripherals resources
         (CLOCK, GPIO, DMA, NVIC).

     (+) Call the function ald_spi_init() to configure the selected device with
         the selected configuration:
       (++) Mode
       (++) Direction
       (++) Data Size
       (++) Clock Polarity and Phase
       (++) NSS Management
       (++) BaudRate Prescaler
       (++) FirstBit
       (++) TIMode
       (++) CRC Calculation
       (++) CRC Polynomial if CRC enabled

     (+) Call the function ald_spi_reset() to reset the selected SPIx periperal.

Function Documentation

◆ ald_spi_init()

ald_status_t ald_spi_init ( spi_handle_t * hperh )

Initializes the SPI mode according to the specified parameters in the SPI_init_t and create the associated handle.

Parameters
hperh Pointer to a spi_handle_t structure that contains the configuration information for the specified SPI module.
Return values
Status,see ald_status_t.

Definition at line 150 of file ald_spi.c.

151 {
152 uint32_t tmp = 0;
153
154 if (hperh == NULL)
155 return ERROR;
156
157 assert_param(IS_SPI(hperh->perh));
158 assert_param(IS_SPI_MODE(hperh->init.mode));
159 assert_param(IS_SPI_DIRECTION(hperh->init.dir));
160 assert_param(IS_SPI_BAUD(hperh->init.baud));
161 assert_param(IS_SPI_FIRBIT(hperh->init.first_bit));
162 assert_param(IS_FUNC_STATE(hperh->init.ss_en));
163 assert_param(IS_FUNC_STATE(hperh->init.crc_calc));
164 assert_param(IS_SPI_DATASIZE(hperh->init.data_size));
165 assert_param(IS_SPI_CPHA(hperh->init.phase));
166 assert_param(IS_SPI_CPOL(hperh->init.polarity));
167 assert_param(IS_SPI_FRAME(hperh->init.frame));
168
169 ald_spi_reset(hperh);
170 tmp = hperh->perh->CON1;
171
172 if (hperh->init.mode == SPI_MODE_MASTER)
173 tmp |= 1 << SPI_CON1_SSOUT_POS;
174
175 tmp |= ((hperh->init.phase << SPI_CON1_CPHA_POS) | (hperh->init.polarity << SPI_CON1_CPOL_POS) |
176 (hperh->init.baud << SPI_CON1_BAUD_POSS) | (hperh->init.data_size << SPI_CON1_FLEN_POS) |
177 (hperh->init.mode << SPI_CON1_MSTREN_POS) | (hperh->init.ss_en << SPI_CON1_SSEN_POS) |
178 (hperh->init.first_bit << SPI_CON1_LSBFST_POS));
179
180 hperh->perh->CON1 = tmp;
181
182 MODIFY_REG(hperh->perh->CON2, SPI_CON2_FRF_MSK, hperh->init.frame << SPI_CON2_FRF_POS);
183
184 if (hperh->init.dir == SPI_DIRECTION_2LINES) {
185 CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK);
186 CLEAR_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK);
187 }
188 else if (hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) {
189 CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK);
190 SET_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK);
191 }
192 else if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) {
193 SET_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK);
194 CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDOEN_MSK);
195 }
196 else {
197 SET_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK);
198 SET_BIT(hperh->perh->CON1, SPI_CON1_BIDOEN_MSK);
199 }
200
201 /* configure CRC */
202 hperh->perh->CON1 |= (hperh->init.crc_calc << SPI_CON1_CRCEN_POS);
203 hperh->perh->CRCPOLY = hperh->init.crc_poly;
204
205 hperh->err_code = SPI_ERROR_NONE;
206 hperh->state = SPI_STATE_READY;
207
208 SPI_ENABLE(hperh);
209 return OK;
210 }
OK
Definition: utils.h:55
IS_SPI_CPHA
#define IS_SPI_CPHA(x)
Definition: ald_spi.h:285
SPI_MODE_MASTER
Definition: ald_spi.h:60
spi_init_t::first_bit
spi_firstbit_t first_bit
Definition: ald_spi.h:218
IS_SPI_DATASIZE
#define IS_SPI_DATASIZE(x)
Definition: ald_spi.h:301
SPI_ENABLE
#define SPI_ENABLE(x)
Definition: ald_spi.h:258
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
spi_init_t::crc_poly
uint16_t crc_poly
Definition: ald_spi.h:222
spi_init_t::ss_en
type_func_t ss_en
Definition: ald_spi.h:219
spi_init_t::crc_calc
type_func_t crc_calc
Definition: ald_spi.h:220
IS_SPI_FRAME
#define IS_SPI_FRAME(x)
Definition: ald_spi.h:346
IS_SPI_MODE
#define IS_SPI_MODE(x)
Definition: ald_spi.h:289
SPI_DIRECTION_2LINES_RXONLY
Definition: ald_spi.h:160
IS_SPI_FIRBIT
#define IS_SPI_FIRBIT(x)
Definition: ald_spi.h:291
spi_init_t::phase
spi_cpha_t phase
Definition: ald_spi.h:216
SPI_DIRECTION_2LINES
Definition: ald_spi.h:159
IS_SPI_DIRECTION
#define IS_SPI_DIRECTION(x)
Definition: ald_spi.h:307
SPI_DIRECTION_1LINE_RX
Definition: ald_spi.h:162
spi_handle_s::init
spi_init_t init
Definition: ald_spi.h:230
spi_init_t::polarity
spi_cpol_t polarity
Definition: ald_spi.h:217
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_handle_s::state
spi_state_t state
Definition: ald_spi.h:242
spi_init_t::baud
spi_baud_t baud
Definition: ald_spi.h:215
ald_spi_reset
void ald_spi_reset(spi_handle_t *hperh)
Reset the SPI peripheral.
Definition: ald_spi.c:131
IS_SPI_CPOL
#define IS_SPI_CPOL(x)
Definition: ald_spi.h:287
spi_init_t::mode
spi_mode_t mode
Definition: ald_spi.h:212
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
spi_init_t::dir
spi_direction_t dir
Definition: ald_spi.h:213
SPI_STATE_READY
Definition: ald_spi.h:145
spi_init_t::data_size
spi_datasize_t data_size
Definition: ald_spi.h:214
spi_init_t::frame
spi_frame_t frame
Definition: ald_spi.h:221
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
spi_handle_s::err_code
uint32_t err_code
Definition: ald_spi.h:243
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
ERROR
Definition: utils.h:56
SPI_ERROR_NONE
Definition: ald_spi.h:97
IS_SPI_BAUD
#define IS_SPI_BAUD(x)
Definition: ald_spi.h:293

◆ ald_spi_reset()

void ald_spi_reset ( spi_handle_t * hperh )

Reset the SPI peripheral.

Parameters
hperh Pointer to a spi_handle_t structure that contains the configuration information for the specified SPI module.
Return values
None

Definition at line 131 of file ald_spi.c.

132 {
133 hperh->perh->CON1 = 0x0;
134 hperh->perh->CON2 = 0x0;
135 hperh->perh->CRCPOLY = 0x00000007;
136
137 SPI_RESET_HANDLE_STATE(hperh);
138 __UNLOCK(hperh);
139
140 return;
141 }
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
SPI_RESET_HANDLE_STATE
#define SPI_RESET_HANDLE_STATE(x)
Definition: ald_spi.h:257

◆ spi_fifo_threshold_config()

ald_status_t spi_fifo_threshold_config | ( | spi_handle_t * | hperh,
 |  | uint8_t | threshold
 | ) |  |

Config the fifo threshold.

Parameters
hperh | Pointer to a spi_handle_t structure that contains the configuration information for the specified SPI module.
threshold | The threshold value of fifo.
Return values
Status,see ald_status_t.

Definition at line 219 of file ald_spi.c.

220 {
221 assert_param(IS_SPI(hperh->perh));
222
223 MODIFY_REG(hperh->perh->CON2, SPI_CON2_RXFTH_MSK, threshold << SPI_CON2_RXFTH_POSS);
224 MODIFY_REG(hperh->perh->CON2, SPI_CON2_TXFTH_MSK, threshold << SPI_CON2_TXFTH_POSS);
225
226 return OK;
227 }
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74


ALD User Manual: IO fast functions

Functions
IO fast functions
EASTSOFT ES32F3xx ALD » SPI » SPI Public Functions

SPI Transmit and Receive functions. More...

Collaboration diagram for IO fast functions:

Functions

int32_t | ald_spi_send_byte_fast (spi_handle_t *hperh, uint8_t data)
Transmit one byte fast in blocking mode. More...
int32_t | ald_spi_send_byte_fast_1line (spi_handle_t *hperh, uint8_t data)
Transmit one byte fast in blocking mode(1line). More...
uint8_t | ald_spi_recv_byte_fast (spi_handle_t *hperh, int *status)
Receive one byte fast in blocking mode. More...
ald_status_t | ald_spi_send_bytes_fast (spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Transmit some bytes fast in blocking mode. More...
ald_status_t | ald_spi_master_recv_bytes_fast (spi_handle_t *hperh, uint8_t *buf, uint32_t size)
Receive some bytes fast in blocking mode. More...
ald_status_t | ald_spi_slave_recv_bytes_fast (spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Receive some bytes fast in blocking mode. More...
ald_status_t | ald_spi_send_dbytes_fast (spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Transmit some double-bytes fast in blocking mode. More...
ald_status_t | ald_spi_master_recv_dbytes_fast (spi_handle_t *hperh, uint8_t *buf, uint32_t size)
Receive some double-bytes fast in blocking mode. More...
ald_status_t | ald_spi_slave_recv_dbytes_fast (spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Receive some double-bytes fast in blocking mode. More...

Detailed Description

SPI Transmit and Receive functions.

 ==============================================================================
                     ##### IO fast functions #####
===============================================================================
   This subsection provides a set of functions allowing to manage the SPI
   data transfers fast.

 *

Function Documentation

◆ ald_spi_master_recv_bytes_fast()

ald_status_t ald_spi_master_recv_bytes_fast | ( | spi_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint32_t | size
 | ) |  |

Receive some bytes fast in blocking mode.

Note
Bit width is 8-bits. Supports mode: Master.
Parameters
hperh | Pointer to a spi_handle_t structure.
buf | Data to be received.
size | Length of data.
Return values
status OK/TIMEOUT

Definition at line 352 of file ald_spi.c.

353 {
354 uint16_t cnt = 8000;
355
356 while (size--) {
357 hperh->perh->DATA = 0xFF;
358 cnt = 8000;
359 while (((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) && (--cnt));
360
361 if (cnt)
362 *buf++ = (uint8_t)hperh->perh->DATA;
363 else
364 return TIMEOUT;
365 }
366
367 return OK;
368 }
OK
Definition: utils.h:55
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
TIMEOUT
Definition: utils.h:58

◆ ald_spi_master_recv_dbytes_fast()

ald_status_t ald_spi_master_recv_dbytes_fast | ( | spi_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint32_t | size
 | ) |  |

Receive some double-bytes fast in blocking mode.

Note
Bit width is 16-bits. Supports mode: Master.
Parameters
hperh | Pointer to a spi_handle_t structure.
buf | Data to be received.
size | Length of data. Unit is double-bytes.
Return values
status OK/TIMEOUT

Definition at line 441 of file ald_spi.c.

442 {
443 uint16_t cnt = 8000;
444
445 while (size--) {
446 hperh->perh->DATA = 0xFFFF;
447 cnt = 8000;
448 while (((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) && (--cnt));
449
450 if (cnt) {
451 *(uint16_t *)buf = (uint16_t)hperh->perh->DATA;
452 buf += 2;
453 }
454 else {
455 return TIMEOUT;
456 }
457 }
458
459 return OK;
460 }
OK
Definition: utils.h:55
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
TIMEOUT
Definition: utils.h:58

◆ ald_spi_recv_byte_fast()

uint8_t ald_spi_recv_byte_fast | ( | spi_handle_t * | hperh,
 |  | int * | status
 | ) |  |

Receive one byte fast in blocking mode.

Parameters
hperh | Pointer to a spi_handle_t structure.
status | Status, success[0]/failed[-1]
Return values
Data.

Definition at line 293 of file ald_spi.c.

294 {
295 uint16_t cnt = 5000;
296
297 if (hperh->init.mode == SPI_MODE_MASTER) {
298 hperh->perh->DATA = 0xFF;
299 while (((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt));
300 }
301
302 cnt = 5000;
303 while (((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) && (--cnt));
304 *status = cnt == 0 ? - 1 : 0;
305
306 return (uint8_t)hperh->perh->DATA;
307 }
SPI_MODE_MASTER
Definition: ald_spi.h:60
spi_handle_s::init
spi_init_t init
Definition: ald_spi.h:230
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_init_t::mode
spi_mode_t mode
Definition: ald_spi.h:212

◆ ald_spi_send_byte_fast()

int32_t ald_spi_send_byte_fast | ( | spi_handle_t * | hperh,
 |  | uint8_t | data
 | ) |  |

Transmit one byte fast in blocking mode.

Parameters
hperh | Pointer to a spi_handle_t structure.
data | Data to be sent
Return values
status
  • 0 Success
  • -1 Failed

Definition at line 254 of file ald_spi.c.

255 {
256 uint16_t cnt = 5000, temp;
257
258 hperh->perh->DATA = data;
259 while (((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt));
260
261 cnt = 5000;
262 while (((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) && (--cnt));
263 temp = hperh->perh->DATA;
264 UNUSED(temp);
265
266 return cnt == 0 ? -1 : 0;
267 }
UNUSED
#define UNUSED(x)
Definition: type.h:76
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229

◆ ald_spi_send_byte_fast_1line()

int32_t ald_spi_send_byte_fast_1line | ( | spi_handle_t * | hperh,
 |  | uint8_t | data
 | ) |  |

Transmit one byte fast in blocking mode(1line).

Parameters
hperh | Pointer to a spi_handle_t structure.
data | Data to be sent
Return values
status
  • 0 Success
  • -1 Failed

Definition at line 277 of file ald_spi.c.

278 {
279 uint16_t cnt = 5000;
280
281 hperh->perh->DATA = data;
282 while (((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt));
283
284 return cnt == 0 ? -1 : 0;
285 }
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229

◆ ald_spi_send_bytes_fast()

ald_status_t ald_spi_send_bytes_fast | ( | spi_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint32_t | size,
 |  | uint32_t | timeout
 | ) |  |

Transmit some bytes fast in blocking mode.

Note
Bit width is 8-bits. Supports mode: Master/Slave.
Parameters
hperh | Pointer to a spi_handle_t structure.
buf | Data to be sent.
size | Length of data.
timeout | Timeout between two bytes.
Return values
status OK/TIMEOUT

Definition at line 318 of file ald_spi.c.

319 {
320 uint32_t tick;
321 uint16_t i, tmp = 0;
322
323 while (size--) {
324 hperh->perh->DATA = *buf++;
325 tick = ald_get_tick();
326
327 while ((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) {
328 if (((ald_get_tick()) - tick) > timeout)
329 return TIMEOUT;
330 }
331 }
332
333 for (i = 0; i < 16; ++i) {
334 if ((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK)
335 tmp = hperh->perh->DATA;
336 else
337 break;
338 }
339
340 UNUSED(tmp);
341 return OK;
342 }
OK
Definition: utils.h:55
UNUSED
#define UNUSED(x)
Definition: type.h:76
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58

◆ ald_spi_send_dbytes_fast()

ald_status_t ald_spi_send_dbytes_fast | ( | spi_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint32_t | size,
 |  | uint32_t | timeout
 | ) |  |

Transmit some double-bytes fast in blocking mode.

Note
Bit width is 16-bits. Supports mode: Master/Slave.
Parameters
hperh | Pointer to a spi_handle_t structure.
buf | Data to be sent.
size | Length of data. Unit is double-bytes.
timeout | Timeout between two dbytes.
Return values
status OK/TIMEOUT

Definition at line 406 of file ald_spi.c.

407 {
408 uint32_t tick;
409 uint16_t i, tmp = 0;
410
411 while (size--) {
412 hperh->perh->DATA = (*(uint16_t *)buf);
413 buf += 2;
414 tick = ald_get_tick();
415
416 while ((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) {
417 if (((ald_get_tick()) - tick) > timeout)
418 return TIMEOUT;
419 }
420 }
421
422 for (i = 0; i < 16; ++i) {
423 if ((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK)
424 tmp = hperh->perh->DATA;
425 else
426 break;
427 }
428
429 UNUSED(tmp);
430 return OK;
431 }
OK
Definition: utils.h:55
UNUSED
#define UNUSED(x)
Definition: type.h:76
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58

◆ ald_spi_slave_recv_bytes_fast()

ald_status_t ald_spi_slave_recv_bytes_fast | ( | spi_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint32_t | size,
 |  | uint32_t | timeout
 | ) |  |

Receive some bytes fast in blocking mode.

Note
Bit width is 8-bits. Supports mode: Slave.
Parameters
hperh | Pointer to a spi_handle_t structure.
buf | Data to be received.
size | Length of data.
timeout | Timeout between two bytes.
Return values
status OK/TIMEOUT

Definition at line 379 of file ald_spi.c.

380 {
381 uint32_t tick;
382
383 while (size--) {
384 tick = ald_get_tick();
385
386 while ((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) {
387 if (((ald_get_tick()) - tick) > timeout)
388 return TIMEOUT;
389 }
390
391 *buf++ = (uint8_t)hperh->perh->DATA;
392 }
393
394 return OK;
395 }
OK
Definition: utils.h:55
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58

◆ ald_spi_slave_recv_dbytes_fast()

ald_status_t ald_spi_slave_recv_dbytes_fast | ( | spi_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint32_t | size,
 |  | uint32_t | timeout
 | ) |  |

Receive some double-bytes fast in blocking mode.

Note
Bit width is 16-bits. Supports mode: Slave.
Parameters
hperh | Pointer to a spi_handle_t structure.
buf | Data to be received.
size | Length of data. Unit is double-bytes.
timeout | Timeout between two dbytes.
Return values
status OK/TIMEOUT

Definition at line 471 of file ald_spi.c.

472 {
473 uint32_t tick;
474
475 while (size--) {
476 tick = ald_get_tick();
477
478 while ((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) {
479 if (((ald_get_tick()) - tick) > timeout)
480 return TIMEOUT;
481 }
482
483 *(uint16_t *)buf = (uint16_t)hperh->perh->DATA;
484 buf += 2;
485 }
486
487 return OK;
488 }
OK
Definition: utils.h:55
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58


ALD User Manual: IO operation functions

Functions
IO operation functions
EASTSOFT ES32F3xx ALD » SPI » SPI Public Functions

SPI Transmit and Receive functions. More...

Collaboration diagram for IO operation functions:

Functions

ald_status_t | ald_spi_send (spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Transmit an amount of data in blocking mode. More...
ald_status_t | ald_spi_recv (spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Receive an amount of data in blocking mode. More...
ald_status_t | ald_spi_send_recv (spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout)
Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode). More...
ald_status_t | ald_spi_send_by_it (spi_handle_t *hperh, uint8_t *buf, uint16_t size)
Wraps up transmission in non blocking mode. More...
ald_status_t | ald_spi_recv_by_it (spi_handle_t *hperh, uint8_t *buf, uint16_t size)
Receives an amount of data in non blocking mode. More...
ald_status_t | ald_spi_send_recv_by_it (spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size)
Transmit and Receives an amount of data in non blocking mode. More...
ald_status_t | ald_spi_send_by_dma (spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
Transmit an amount of data used dma channel. More...
ald_status_t | ald_spi_recv_by_dma (spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
Receive an amount of data used dma channel. More...
ald_status_t | ald_spi_send_recv_by_dma (spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel)
Transmit and Receive an amount of data used dma channel. More...
ald_status_t | ald_spi_dma_pause (spi_handle_t *hperh)
Pauses the DMA Transfer. More...
ald_status_t | ald_spi_dma_resume (spi_handle_t *hperh)
Resumes the DMA Transfer. More...
ald_status_t | ald_spi_dma_stop (spi_handle_t *hperh)
Stops the DMA Transfer. More...

Detailed Description

SPI Transmit and Receive functions.

 ==============================================================================
                     ##### IO operation functions #####
===============================================================================
   This subsection provides a set of functions allowing to manage the SPI
   data transfers.

   [..] The SPI supports master or slave mode:

   (#) There are two modes of transfer:
      (++) Blocking mode: The communication is performed in polling mode.
           The ALD status of all data processing is returned by the same function
           after finishing transfer.
      (++) No-Blocking mode: The communication is performed using Interrupts
           or DMA, These APIs return the ALD status.
           The end of the data processing will be indicated through the
           dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
           using DMA mode.
           The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() and hperh->tx_rx_cplt_cbk() user callbacks
           will be executed respectivelly at the end of the transmit or Receive process
           The hperh->err_cbk() user callback will be executed when a communication error is detected

   (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
       exist for 1Line (simplex) and 2Lines (full duplex) modes.

 *

Function Documentation

◆ ald_spi_dma_pause()

ald_status_t ald_spi_dma_pause ( spi_handle_t * hperh )

Pauses the DMA Transfer.

Parameters
hperh Pointer to a spi_handle_t structure.
Return values
Status

Definition at line 1207 of file ald_spi.c.

1208 {
1209 assert_param(IS_SPI(hperh->perh));
1210
1211 __LOCK(hperh);
1212 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE);
1213 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE);
1214 __UNLOCK(hperh);
1215
1216 return OK;
1217 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
SPI_DMA_REQ_RX
Definition: ald_spi.h:170
DISABLE
Definition: type.h:48
ald_spi_dma_req_config
void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state)
Enables or disables the dma request.
Definition: ald_spi.c:1398
SPI_DMA_REQ_TX
Definition: ald_spi.h:169
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
__LOCK
#define __LOCK(x)
Definition: utils.h:92

◆ ald_spi_dma_resume()

ald_status_t ald_spi_dma_resume ( spi_handle_t * hperh )

Resumes the DMA Transfer.

Parameters
hperh Pointer to a spi_handle_t structure.
Return values
Status

Definition at line 1224 of file ald_spi.c.

1225 {
1226 assert_param(IS_SPI(hperh->perh));
1227
1228 __LOCK(hperh);
1229 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE);
1230 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE);
1231 __UNLOCK(hperh);
1232
1233 return OK;
1234 }
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
SPI_DMA_REQ_RX
Definition: ald_spi.h:170
ald_spi_dma_req_config
void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state)
Enables or disables the dma request.
Definition: ald_spi.c:1398
SPI_DMA_REQ_TX
Definition: ald_spi.h:169
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
__LOCK
#define __LOCK(x)
Definition: utils.h:92

◆ ald_spi_dma_stop()

ald_status_t ald_spi_dma_stop ( spi_handle_t * hperh )

Stops the DMA Transfer.

Parameters
hperh Pointer to a spi_handle_t structure.
Return values
Status

Definition at line 1241 of file ald_spi.c.

1242 {
1243 assert_param(IS_SPI(hperh->perh));
1244
1245 __LOCK(hperh);
1246 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE);
1247 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE);
1248 __UNLOCK(hperh);
1249
1250 hperh->state = SPI_STATE_READY;
1251 return OK;
1252 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
SPI_DMA_REQ_RX
Definition: ald_spi.h:170
DISABLE
Definition: type.h:48
ald_spi_dma_req_config
void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state)
Enables or disables the dma request.
Definition: ald_spi.c:1398
SPI_DMA_REQ_TX
Definition: ald_spi.h:169
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_handle_s::state
spi_state_t state
Definition: ald_spi.h:242
SPI_STATE_READY
Definition: ald_spi.h:145
__LOCK
#define __LOCK(x)
Definition: utils.h:92

◆ ald_spi_recv()

ald_status_t ald_spi_recv | ( | spi_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint16_t | size,
 |  | uint32_t | timeout
 | ) |  |

Receive an amount of data in blocking mode.

Parameters
hperh | Pointer to a spi_handle_t structure.
buf | Pointer to data buffer
size | Amount of data to be received
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 624 of file ald_spi.c.

625 {
626 uint32_t tick;
627 uint16_t temp;
628
629 assert_param(IS_SPI(hperh->perh));
630
631 if (hperh->state != SPI_STATE_READY)
632 return BUSY;
633 if (buf == NULL || size == 0)
634 return ERROR;
635
636 if (hperh->init.mode == SPI_MODE_MASTER)
637 return ald_spi_send_recv(hperh, buf, buf, size, timeout);
638
639 hperh->state = SPI_STATE_BUSY_RX;
640 hperh->err_code = SPI_ERROR_NONE;
641
642 if (hperh->init.crc_calc)
643 SPI_CRC_RESET(hperh);
644
645 while (size > 0) {
646 tick = ald_get_tick();
647
648 while ((hperh->perh->STAT & SPI_STATUS_RXE) != RESET) {
649 if (((ald_get_tick()) - tick) > timeout)
650 goto timeout;
651 }
652
653 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
654 *buf = hperh->perh->DATA;
655 ++buf;
656 }
657 else {
658 *(uint16_t *)buf = hperh->perh->DATA;
659 buf += 2;
660 }
661
662 --size;
663 }
664
665 if (hperh->init.crc_calc) {
666 tick = ald_get_tick();
667
668 while ((hperh->perh->STAT & SPI_STATUS_RXTH) != RESET) {
669 if (((ald_get_tick()) - tick) > timeout)
670 goto timeout;
671 }
672
673 temp = hperh->perh->DATA;
674 UNUSED(temp);
675
676 if ((hperh->perh->RIF & SPI_IF_CRCERR) != RESET) {
677 hperh->err_code |= SPI_ERROR_CRC;
678 SPI_CRC_RESET(hperh);
679 ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR);
680 hperh->state = SPI_STATE_READY;
681
682 return ERROR;
683 }
684 }
685
686 hperh->state = SPI_STATE_READY;
687 return OK;
688
689 timeout:
690 if (hperh->init.crc_calc)
691 SPI_CRC_RESET(hperh);
692
693 hperh->state = SPI_STATE_READY;
694 return TIMEOUT;
695 }
OK
Definition: utils.h:55
SPI_MODE_MASTER
Definition: ald_spi.h:60
assert_param
#define assert_param(x)
Definition: type.h:88
SPI_ERROR_CRC
Definition: ald_spi.h:99
BUSY
Definition: utils.h:57
spi_init_t::crc_calc
type_func_t crc_calc
Definition: ald_spi.h:220
SPI_STATE_BUSY_RX
Definition: ald_spi.h:148
RESET
Definition: type.h:38
ald_spi_clear_flag_status
void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag)
Clear the specified SPI pending flags.
Definition: ald_spi.c:1484
UNUSED
#define UNUSED(x)
Definition: type.h:76
SPI_STATUS_RXTH
Definition: ald_spi.h:194
spi_handle_s::init
spi_init_t init
Definition: ald_spi.h:230
ald_spi_send_recv
ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout)
Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
Definition: ald_spi.c:706
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_handle_s::state
spi_state_t state
Definition: ald_spi.h:242
SPI_IF_CRCERR
Definition: ald_spi.h:135
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
spi_init_t::mode
spi_mode_t mode
Definition: ald_spi.h:212
SPI_STATUS_RXE
Definition: ald_spi.h:190
SPI_STATE_READY
Definition: ald_spi.h:145
spi_init_t::data_size
spi_datasize_t data_size
Definition: ald_spi.h:214
SPI_CRC_RESET
#define SPI_CRC_RESET(x)
Definition: ald_spi.h:260
spi_handle_s::err_code
uint32_t err_code
Definition: ald_spi.h:243
ERROR
Definition: utils.h:56
SPI_DATA_SIZE_8
Definition: ald_spi.h:89
SPI_ERROR_NONE
Definition: ald_spi.h:97

◆ ald_spi_recv_by_dma()

ald_status_t ald_spi_recv_by_dma | ( | spi_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint16_t | size,
 |  | uint8_t | channel
 | ) |  |

Receive an amount of data used dma channel.

Parameters
hperh | Pointer to a spi_handle_t structure.
buf | Pointer to data buffer
size | Amount of data to be sent
channel | DMA channel as SPI transmit
Return values
Status,see ald_status_t.

Definition at line 1047 of file ald_spi.c.

1048 {
1049 uint16_t tmp_rx = 0xB1B2;
1050 assert_param(IS_SPI(hperh->perh));
1051
1052 if (hperh->state != SPI_STATE_READY)
1053 return BUSY;
1054 if (buf == NULL || size == 0)
1055 return ERROR;
1056
1057 __LOCK(hperh);
1058 hperh->state = SPI_STATE_BUSY_RX;
1059 hperh->err_code = SPI_ERROR_NONE;
1060
1061 hperh->rx_buf = buf;
1062 hperh->rx_size = size;
1063 hperh->rx_count = size;
1064 hperh->tx_buf = NULL;
1065 hperh->tx_size = 0;
1066 hperh->tx_count = 0;
1067
1068 if (hperh->init.dir == SPI_DIRECTION_1LINE_RX)
1069 SPI_1LINE_RX(hperh);
1070 if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) {
1071 __UNLOCK(hperh);
1072 return ERROR;
1073 }
1074 if (hperh->init.crc_calc)
1075 SPI_CRC_RESET(hperh);
1076
1077 if (hperh->hdmatx.perh == NULL)
1078 hperh->hdmatx.perh = DMA0;
1079 if (hperh->hdmarx.perh == NULL)
1080 hperh->hdmarx.perh = DMA0;
1081
1082 hperh->hdmarx.cplt_arg = (void *)hperh;
1083 hperh->hdmarx.cplt_cbk = spi_dma_recv_cplt;
1084
1085 /* Configure SPI DMA transmit */
1086 ald_dma_config_struct(&(hperh->hdmatx.config));
1087 hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD;
1088 hperh->hdmatx.config.src = (void *)&tmp_rx;
1089 hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA;
1090 hperh->hdmatx.config.size = size;
1091 hperh->hdmatx.config.src_inc = DMA_DATA_INC_NONE;
1092 hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
1093 hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2);
1094 hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY;
1095 hperh->hdmatx.config.burst = ENABLE;
1096 hperh->hdmatx.config.channel = 11;
1097 ald_dma_config_basic(&(hperh->hdmatx));
1098
1099 /* Configure DMA Receive */
1100 ald_dma_config_struct(&(hperh->hdmarx.config));
1101 hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD;
1102 hperh->hdmarx.config.src = (void *)&hperh->perh->DATA;
1103 hperh->hdmarx.config.dst = (void *)buf;
1104 hperh->hdmarx.config.size = size;
1105 hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE;
1106 hperh->hdmarx.config.dst_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;;
1107 hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2);
1108 hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR;
1109 hperh->hdmatx.config.burst = ENABLE;
1110 hperh->hdmarx.config.channel = channel;
1111 ald_dma_config_basic(&(hperh->hdmarx));
1112
1113 __UNLOCK(hperh);
1114
1115 if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX))
1116 SPI_ENABLE(hperh);
1117
1118 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE);
1119 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE);
1120
1121 return OK;
1122 }
DMA_MSEL_SPI1
Definition: ald_dma.h:91
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
spi_handle_s::rx_buf
uint8_t * rx_buf
Definition: ald_spi.h:234
SPI_MODE_MASTER
Definition: ald_spi.h:60
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
SPI_ENABLE
#define SPI_ENABLE(x)
Definition: ald_spi.h:258
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
spi_dma_recv_cplt
static void spi_dma_recv_cplt(void *arg)
DMA SPI receive process complete callback.
Definition: ald_spi.c:1861
spi_handle_s::tx_buf
uint8_t * tx_buf
Definition: ald_spi.h:231
SPI_DMA_REQ_RX
Definition: ald_spi.h:170
DMA_MSEL_SPI2
Definition: ald_dma.h:99
spi_handle_s::tx_count
uint16_t tx_count
Definition: ald_spi.h:233
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
spi_init_t::crc_calc
type_func_t crc_calc
Definition: ald_spi.h:220
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
SPI_1LINE_RX
#define SPI_1LINE_RX(x)
Definition: ald_spi.h:270
dma_config_t::src
void * src
Definition: ald_dma.h:278
SPI_DIRECTION_2LINES_RXONLY
Definition: ald_spi.h:160
SPI_STATE_BUSY_RX
Definition: ald_spi.h:148
DMA_DATA_SIZE_BYTE
Definition: ald_dma.h:227
SPI_DIRECTION_2LINES
Definition: ald_spi.h:159
SPI_DIRECTION_1LINE_RX
Definition: ald_spi.h:162
spi_handle_s::init
spi_init_t init
Definition: ald_spi.h:230
ald_spi_dma_req_config
void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state)
Enables or disables the dma request.
Definition: ald_spi.c:1398
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
SPI_DMA_REQ_TX
Definition: ald_spi.h:169
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_handle_s::state
spi_state_t state
Definition: ald_spi.h:242
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
DMA_MSIGSEL_SPI_RNR
Definition: ald_dma.h:141
DMA_DATA_INC_BYTE
Definition: ald_dma.h:217
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
spi_handle_s::tx_size
uint16_t tx_size
Definition: ald_spi.h:232
spi_init_t::mode
spi_mode_t mode
Definition: ald_spi.h:212
spi_handle_s::hdmarx
dma_handle_t hdmarx
Definition: ald_spi.h:239
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
spi_handle_s::hdmatx
dma_handle_t hdmatx
Definition: ald_spi.h:238
spi_init_t::dir
spi_direction_t dir
Definition: ald_spi.h:213
SPI_STATE_READY
Definition: ald_spi.h:145
spi_init_t::data_size
spi_datasize_t data_size
Definition: ald_spi.h:214
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
DMA_MSIGSEL_SPI_TXEMPTY
Definition: ald_dma.h:142
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
SPI_CRC_RESET
#define SPI_CRC_RESET(x)
Definition: ald_spi.h:260
spi_handle_s::err_code
uint32_t err_code
Definition: ald_spi.h:243
spi_handle_s::rx_size
uint16_t rx_size
Definition: ald_spi.h:235
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
DMA_MSEL_SPI0
Definition: ald_dma.h:90
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
SPI_DATA_SIZE_8
Definition: ald_spi.h:89
spi_handle_s::rx_count
uint16_t rx_count
Definition: ald_spi.h:236
SPI_ERROR_NONE
Definition: ald_spi.h:97
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294

◆ ald_spi_recv_by_it()

ald_status_t ald_spi_recv_by_it | ( | spi_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint16_t | size
 | ) |  |

Receives an amount of data in non blocking mode.

Parameters
hperh | Pointer to a spi_handle_t structure.
buf | Pointer to data received buffer
size | Amount of data to be sent
Return values
Status,see ald_status_t.

Definition at line 886 of file ald_spi.c.

887 {
888 assert_param(IS_SPI(hperh->perh));
889
890 if (hperh->state != SPI_STATE_READY)
891 return BUSY;
892 if (buf == NULL || size == 0)
893 return ERROR;
894 if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER))
895 return ERROR;
896
897 __LOCK(hperh);
898 hperh->state = SPI_STATE_BUSY_RX;
899 hperh->err_code = SPI_ERROR_NONE;
900
901 hperh->rx_buf = buf;
902 hperh->rx_size = size;
903 hperh->rx_count = size;
904 hperh->tx_buf = NULL;
905 hperh->tx_size = 0;
906 hperh->tx_count = 0;
907 __UNLOCK(hperh);
908
909 if (hperh->init.dir == SPI_DIRECTION_1LINE_RX)
910 SPI_1LINE_RX(hperh);
911
912 if (hperh->init.crc_calc == ENABLE) {
913 SPI_CRC_RESET(hperh);
914 ald_spi_interrupt_config(hperh, SPI_IT_CRCERR, ENABLE);
915 }
916
917 ald_spi_interrupt_config(hperh, SPI_IT_RXTH, ENABLE);
918 ald_spi_interrupt_config(hperh, SPI_IT_MODF, ENABLE);
919
920 if (hperh->init.data_size <= SPI_DATA_SIZE_8) {
921 *((uint8_t *)&(hperh->perh->DATA)) = 0xFF;
922 }
923 else {
924 *((uint16_t *)&(hperh->perh->DATA)) = 0xFFFF;
925 }
926
927 return OK;
928 }
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
spi_handle_s::rx_buf
uint8_t * rx_buf
Definition: ald_spi.h:234
SPI_MODE_MASTER
Definition: ald_spi.h:60
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
SPI_IT_CRCERR
Definition: ald_spi.h:118
ald_spi_interrupt_config
void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state)
Enables or disables the specified SPI interrupts.
Definition: ald_spi.c:1354
spi_handle_s::tx_buf
uint8_t * tx_buf
Definition: ald_spi.h:231
spi_handle_s::tx_count
uint16_t tx_count
Definition: ald_spi.h:233
spi_init_t::crc_calc
type_func_t crc_calc
Definition: ald_spi.h:220
SPI_1LINE_RX
#define SPI_1LINE_RX(x)
Definition: ald_spi.h:270
SPI_STATE_BUSY_RX
Definition: ald_spi.h:148
SPI_DIRECTION_2LINES
Definition: ald_spi.h:159
SPI_DIRECTION_1LINE_RX
Definition: ald_spi.h:162
spi_handle_s::init
spi_init_t init
Definition: ald_spi.h:230
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_handle_s::state
spi_state_t state
Definition: ald_spi.h:242
spi_handle_s::tx_size
uint16_t tx_size
Definition: ald_spi.h:232
spi_init_t::mode
spi_mode_t mode
Definition: ald_spi.h:212
spi_init_t::dir
spi_direction_t dir
Definition: ald_spi.h:213
SPI_STATE_READY
Definition: ald_spi.h:145
spi_init_t::data_size
spi_datasize_t data_size
Definition: ald_spi.h:214
SPI_CRC_RESET
#define SPI_CRC_RESET(x)
Definition: ald_spi.h:260
spi_handle_s::err_code
uint32_t err_code
Definition: ald_spi.h:243
spi_handle_s::rx_size
uint16_t rx_size
Definition: ald_spi.h:235
SPI_IT_MODF
Definition: ald_spi.h:119
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
SPI_DATA_SIZE_8
Definition: ald_spi.h:89
spi_handle_s::rx_count
uint16_t rx_count
Definition: ald_spi.h:236
SPI_ERROR_NONE
Definition: ald_spi.h:97
SPI_IT_RXTH
Definition: ald_spi.h:117

◆ ald_spi_send()

ald_status_t ald_spi_send | ( | spi_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint16_t | size,
 |  | uint32_t | timeout
 | ) |  |

Transmit an amount of data in blocking mode.

Parameters
hperh | Pointer to a spi_handle_t structure.
buf | Pointer to data buffer
size | Amount of data to be sent
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 532 of file ald_spi.c.

533 {
534 uint32_t tick;
535 uint16_t temp;
536
537 assert_param(IS_SPI(hperh->perh));
538
539 if (hperh->state != SPI_STATE_READY)
540 return BUSY;
541 if (buf == NULL || size == 0)
542 return ERROR;
543
544 hperh->state = SPI_STATE_BUSY_TX;
545
546 if (hperh->init.crc_calc)
547 SPI_CRC_RESET(hperh);
548
549 while (size > 1) {
550 tick = ald_get_tick();
551
552 while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) {
553 if (((ald_get_tick()) - tick) > timeout)
554 goto timeout;
555 }
556
557 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
558 hperh->perh->DATA = *buf;
559 ++buf;
560 }
561 else {
562 hperh->perh->DATA = (*(uint16_t *)buf);
563 buf += 2;
564 }
565
566 --size;
567 }
568
569 tick = ald_get_tick();
570
571 while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) {
572 if (((ald_get_tick()) - tick) > timeout)
573 goto timeout;
574 }
575
576 if (hperh->init.crc_calc) {
577 if (hperh->init.data_size == SPI_DATA_SIZE_8)
578 hperh->perh->DATA = *buf;
579 else
580 hperh->perh->DATA = (*(uint16_t *)buf);
581
582 SPI_CRCNEXT_ENABLE(hperh);
583 }
584 else {
585 if (hperh->init.data_size == SPI_DATA_SIZE_8)
586 hperh->perh->DATA = *buf;
587 else
588 hperh->perh->DATA = (*(uint16_t *)buf);
589 }
590
591 while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) {
592 if (((ald_get_tick()) - tick) > timeout)
593 goto timeout;
594 }
595
596 while ((hperh->perh->STAT & SPI_STATUS_BUSY) != RESET) {
597 if (((ald_get_tick()) - tick) > timeout)
598 goto timeout;
599 }
600
601 while ((spi_get_status(hperh, SPI_STATUS_RXE)) == RESET) {
602 temp = hperh->perh->DATA;
603 UNUSED(temp);
604 }
605
606 hperh->state = SPI_STATE_READY;
607 return OK;
608 timeout:
609 if (hperh->init.crc_calc)
610 SPI_CRC_RESET(hperh);
611
612 hperh->state = SPI_STATE_READY;
613 return TIMEOUT;
614 }
SPI_STATUS_TXE
Definition: ald_spi.h:185
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
spi_init_t::crc_calc
type_func_t crc_calc
Definition: ald_spi.h:220
RESET
Definition: type.h:38
UNUSED
#define UNUSED(x)
Definition: type.h:76
spi_handle_s::init
spi_init_t init
Definition: ald_spi.h:230
SPI_STATE_BUSY_TX
Definition: ald_spi.h:147
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_get_status
flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status)
Check whether the specified SPI state flag is set or not.
Definition: ald_spi.c:1428
spi_handle_s::state
spi_state_t state
Definition: ald_spi.h:242
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
SPI_STATUS_RXE
Definition: ald_spi.h:190
SPI_STATE_READY
Definition: ald_spi.h:145
spi_init_t::data_size
spi_datasize_t data_size
Definition: ald_spi.h:214
SPI_CRC_RESET
#define SPI_CRC_RESET(x)
Definition: ald_spi.h:260
SPI_CRCNEXT_ENABLE
#define SPI_CRCNEXT_ENABLE(x)
Definition: ald_spi.h:265
ERROR
Definition: utils.h:56
SPI_DATA_SIZE_8
Definition: ald_spi.h:89
SPI_STATUS_BUSY
Definition: ald_spi.h:195

◆ ald_spi_send_by_dma()

ald_status_t ald_spi_send_by_dma | ( | spi_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint16_t | size,
 |  | uint8_t | channel
 | ) |  |

Transmit an amount of data used dma channel.

Parameters
hperh | Pointer to a spi_handle_t structure.
buf | Pointer to data buffer
size | Amount of data to be sent
channel | DMA channel as SPI transmit
Return values
Status,see ald_status_t.

Definition at line 984 of file ald_spi.c.

985 {
986 assert_param(IS_SPI(hperh->perh));
987
988 if (hperh->state != SPI_STATE_READY)
989 return BUSY;
990 if (buf == NULL || size == 0)
991 return ERROR;
992
993 __LOCK(hperh);
994 hperh->state = SPI_STATE_BUSY_TX;
995 hperh->err_code = SPI_ERROR_NONE;
996
997 hperh->tx_buf = buf;
998 hperh->tx_size = size;
999 hperh->tx_count = size;
1000 hperh->rx_buf = NULL;
1001 hperh->rx_size = 0;
1002 hperh->rx_count = 0;
1003
1004 if (hperh->init.dir == SPI_DIRECTION_1LINE)
1005 SPI_1LINE_TX(hperh);
1006 if (hperh->init.crc_calc)
1007 SPI_CRC_RESET(hperh);
1008
1009 if (hperh->hdmatx.perh == NULL)
1010 hperh->hdmatx.perh = DMA0;
1011
1012 hperh->hdmatx.cplt_arg = (void *)hperh;
1013 hperh->hdmatx.cplt_cbk = spi_dma_send_cplt;
1014
1015 /* Configure SPI DMA transmit */
1016 ald_dma_config_struct(&(hperh->hdmatx.config));
1017 hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD;
1018 hperh->hdmatx.config.src = (void *)buf;
1019 hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA;
1020 hperh->hdmatx.config.size = size;
1021 hperh->hdmatx.config.src_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;
1022 hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
1023 hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2);
1024 hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY;
1025 hperh->hdmatx.config.channel = channel;
1026 hperh->hdmatx.config.burst = ENABLE;
1027 ald_dma_config_basic(&(hperh->hdmatx));
1028
1029 __UNLOCK(hperh);
1030
1031 if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0)
1032 SPI_ENABLE(hperh);
1033
1034 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE);
1035
1036 return OK;
1037 }
DMA_MSEL_SPI1
Definition: ald_dma.h:91
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
spi_handle_s::rx_buf
uint8_t * rx_buf
Definition: ald_spi.h:234
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
SPI_ENABLE
#define SPI_ENABLE(x)
Definition: ald_spi.h:258
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
spi_handle_s::tx_buf
uint8_t * tx_buf
Definition: ald_spi.h:231
DMA_MSEL_SPI2
Definition: ald_dma.h:99
spi_handle_s::tx_count
uint16_t tx_count
Definition: ald_spi.h:233
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
spi_init_t::crc_calc
type_func_t crc_calc
Definition: ald_spi.h:220
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
spi_dma_send_cplt
static void spi_dma_send_cplt(void *arg)
DMA SPI transmit process complete callback.
Definition: ald_spi.c:1822
DMA_DATA_SIZE_BYTE
Definition: ald_dma.h:227
spi_handle_s::init
spi_init_t init
Definition: ald_spi.h:230
SPI_STATE_BUSY_TX
Definition: ald_spi.h:147
ald_spi_dma_req_config
void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state)
Enables or disables the dma request.
Definition: ald_spi.c:1398
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
SPI_1LINE_TX
#define SPI_1LINE_TX(x)
Definition: ald_spi.h:269
SPI_DMA_REQ_TX
Definition: ald_spi.h:169
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_handle_s::state
spi_state_t state
Definition: ald_spi.h:242
SPI_DIRECTION_1LINE
Definition: ald_spi.h:161
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
DMA_DATA_INC_BYTE
Definition: ald_dma.h:217
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
spi_handle_s::tx_size
uint16_t tx_size
Definition: ald_spi.h:232
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
spi_handle_s::hdmatx
dma_handle_t hdmatx
Definition: ald_spi.h:238
spi_init_t::dir
spi_direction_t dir
Definition: ald_spi.h:213
SPI_STATE_READY
Definition: ald_spi.h:145
spi_init_t::data_size
spi_datasize_t data_size
Definition: ald_spi.h:214
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
DMA_MSIGSEL_SPI_TXEMPTY
Definition: ald_dma.h:142
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
SPI_CRC_RESET
#define SPI_CRC_RESET(x)
Definition: ald_spi.h:260
spi_handle_s::err_code
uint32_t err_code
Definition: ald_spi.h:243
spi_handle_s::rx_size
uint16_t rx_size
Definition: ald_spi.h:235
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
DMA_MSEL_SPI0
Definition: ald_dma.h:90
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
SPI_DATA_SIZE_8
Definition: ald_spi.h:89
spi_handle_s::rx_count
uint16_t rx_count
Definition: ald_spi.h:236
SPI_ERROR_NONE
Definition: ald_spi.h:97
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294

◆ ald_spi_send_by_it()

ald_status_t ald_spi_send_by_it | ( | spi_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint16_t | size
 | ) |  |

Wraps up transmission in non blocking mode.

Parameters
hperh | pointer to a spi_handle_t structure.
buf | Pointer to data transmitted buffer
size | Amount of data to be sent
Return values
Status,see ald_status_t.

Definition at line 850 of file ald_spi.c.

851 {
852 assert_param(IS_SPI(hperh->perh));
853
854 if (hperh->state != SPI_STATE_READY)
855 return BUSY;
856 if (buf == NULL || size == 0)
857 return ERROR;
858
859 __LOCK(hperh);
860 hperh->state = SPI_STATE_BUSY_TX;
861 hperh->err_code = SPI_ERROR_NONE;
862
863 hperh->tx_buf = buf;
864 hperh->tx_size = size;
865 hperh->tx_count = size;
866 hperh->rx_buf = NULL;
867 hperh->rx_size = 0;
868 hperh->rx_count = 0;
869 __UNLOCK(hperh);
870
871 if (hperh->init.crc_calc)
872 SPI_CRC_RESET(hperh);
873
874 ald_spi_interrupt_config(hperh, SPI_IT_TXE, ENABLE);
875
876 return OK;
877 }
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
spi_handle_s::rx_buf
uint8_t * rx_buf
Definition: ald_spi.h:234
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
ald_spi_interrupt_config
void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state)
Enables or disables the specified SPI interrupts.
Definition: ald_spi.c:1354
spi_handle_s::tx_buf
uint8_t * tx_buf
Definition: ald_spi.h:231
spi_handle_s::tx_count
uint16_t tx_count
Definition: ald_spi.h:233
spi_init_t::crc_calc
type_func_t crc_calc
Definition: ald_spi.h:220
SPI_IT_TXE
Definition: ald_spi.h:110
spi_handle_s::init
spi_init_t init
Definition: ald_spi.h:230
SPI_STATE_BUSY_TX
Definition: ald_spi.h:147
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_handle_s::state
spi_state_t state
Definition: ald_spi.h:242
spi_handle_s::tx_size
uint16_t tx_size
Definition: ald_spi.h:232
SPI_STATE_READY
Definition: ald_spi.h:145
SPI_CRC_RESET
#define SPI_CRC_RESET(x)
Definition: ald_spi.h:260
spi_handle_s::err_code
uint32_t err_code
Definition: ald_spi.h:243
spi_handle_s::rx_size
uint16_t rx_size
Definition: ald_spi.h:235
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
spi_handle_s::rx_count
uint16_t rx_count
Definition: ald_spi.h:236
SPI_ERROR_NONE
Definition: ald_spi.h:97

◆ ald_spi_send_recv()

ald_status_t ald_spi_send_recv | ( | spi_handle_t * | hperh,
 |  | uint8_t * | tx_buf,
 |  | uint8_t * | rx_buf,
 |  | uint16_t | size,
 |  | uint32_t | timeout
 | ) |  |

Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).

Parameters
hperh | Pointer to a spi_handle_t structure.
tx_buf | Pointer to data transmitted buffer
rx_buf | Pointer to data received buffer
size | Amount of data to be sent
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 706 of file ald_spi.c.

707 {
708 uint32_t tick;
709 uint16_t temp;
710
711 assert_param(IS_SPI(hperh->perh));
712
713 if (hperh->state != SPI_STATE_READY)
714 return BUSY;
715 if (hperh->init.dir != SPI_DIRECTION_2LINES)
716 return ERROR;
717 if (tx_buf == NULL || rx_buf == NULL || size == 0)
718 return ERROR;
719
720 hperh->state = SPI_STATE_BUSY_TX_RX;
721 hperh->err_code = SPI_ERROR_NONE;
722
723 if (hperh->init.crc_calc)
724 SPI_CRC_RESET(hperh);
725
726 while (size > 1) {
727 tick = ald_get_tick();
728
729 while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) {
730 if (((ald_get_tick()) - tick) > timeout)
731 goto timeout;
732 }
733
734 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
735 hperh->perh->DATA = *tx_buf;
736 ++tx_buf;
737 }
738 else {
739 hperh->perh->DATA = (*(uint16_t *)tx_buf);
740 tx_buf += 2;
741 }
742
743 tick = ald_get_tick();
744
745 while ((hperh->perh->STAT & SPI_STATUS_RXE) != RESET) {
746 if (((ald_get_tick()) - tick) > timeout)
747 goto timeout;
748 }
749
750 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
751 *rx_buf = (uint8_t)hperh->perh->DATA;
752 ++rx_buf;
753 }
754 else {
755 (*(uint16_t *)rx_buf) = hperh->perh->DATA;
756 rx_buf += 2;
757 }
758
759 --size;
760 }
761
762 tick = ald_get_tick();
763
764 while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) {
765 if (((ald_get_tick()) - tick) > timeout)
766 goto timeout;
767 }
768
769 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
770 if (hperh->init.crc_calc) {
771 hperh->perh->DATA = *tx_buf;
772 SPI_CRCNEXT_ENABLE(hperh);
773 }
774 else {
775 hperh->perh->DATA = *tx_buf;
776 }
777 }
778 else {
779 if (hperh->init.crc_calc) {
780 hperh->perh->DATA = (*(uint16_t *)tx_buf);
781 SPI_CRCNEXT_ENABLE(hperh);
782 }
783 else {
784 hperh->perh->DATA = (*(uint16_t *)tx_buf);
785 }
786 }
787
788 tick = ald_get_tick();
789
790 while ((hperh->perh->STAT & SPI_STATUS_RXE) != RESET) {
791 if (((ald_get_tick()) - tick) > timeout)
792 goto timeout;
793 }
794
795 if (hperh->init.data_size == SPI_DATA_SIZE_8)
796 *rx_buf = (uint8_t)hperh->perh->DATA;
797 else
798 (*(uint16_t *)rx_buf) = hperh->perh->DATA;
799
800 if (hperh->init.crc_calc) {
801 tick = ald_get_tick();
802
803 while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) {
804 if (((ald_get_tick()) - tick) > timeout)
805 goto timeout;
806 }
807
808 tick = ald_get_tick();
809
810 while ((hperh->perh->STAT & SPI_STATUS_RXE) != RESET) {
811 if (((ald_get_tick()) - tick) > timeout)
812 goto timeout;
813 }
814
815 temp = hperh->perh->DATA;
816 UNUSED(temp);
817
818 if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET) {
819 hperh->err_code |= SPI_ERROR_CRC;
820 SPI_CRC_RESET(hperh);
821 ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR);
822 hperh->state = SPI_STATE_READY;
823
824 return ERROR;
825 }
826 }
827
828 while ((hperh->perh->STAT & SPI_STATUS_BUSY) != RESET) {
829 if (((ald_get_tick()) - tick) > timeout)
830 goto timeout;
831 }
832
833 hperh->state = SPI_STATE_READY;
834 return OK;
835 timeout:
836 if (hperh->init.crc_calc)
837 SPI_CRC_RESET(hperh);
838
839 hperh->state = SPI_STATE_READY;
840 return TIMEOUT;
841 }
SPI_STATUS_TXE
Definition: ald_spi.h:185
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
SPI_STATE_BUSY_TX_RX
Definition: ald_spi.h:149
SPI_ERROR_CRC
Definition: ald_spi.h:99
BUSY
Definition: utils.h:57
spi_init_t::crc_calc
type_func_t crc_calc
Definition: ald_spi.h:220
ald_spi_get_flag_status
flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag)
Check whether the specified SPI flag is set or not.
Definition: ald_spi.c:1467
SPI_DIRECTION_2LINES
Definition: ald_spi.h:159
RESET
Definition: type.h:38
ald_spi_clear_flag_status
void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag)
Clear the specified SPI pending flags.
Definition: ald_spi.c:1484
UNUSED
#define UNUSED(x)
Definition: type.h:76
spi_handle_s::init
spi_init_t init
Definition: ald_spi.h:230
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_handle_s::state
spi_state_t state
Definition: ald_spi.h:242
SPI_IF_CRCERR
Definition: ald_spi.h:135
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
SPI_STATUS_RXE
Definition: ald_spi.h:190
spi_init_t::dir
spi_direction_t dir
Definition: ald_spi.h:213
SPI_STATE_READY
Definition: ald_spi.h:145
spi_init_t::data_size
spi_datasize_t data_size
Definition: ald_spi.h:214
SPI_CRC_RESET
#define SPI_CRC_RESET(x)
Definition: ald_spi.h:260
SPI_CRCNEXT_ENABLE
#define SPI_CRCNEXT_ENABLE(x)
Definition: ald_spi.h:265
spi_handle_s::err_code
uint32_t err_code
Definition: ald_spi.h:243
ERROR
Definition: utils.h:56
SPI_DATA_SIZE_8
Definition: ald_spi.h:89
SPI_ERROR_NONE
Definition: ald_spi.h:97
SPI_STATUS_BUSY
Definition: ald_spi.h:195

◆ ald_spi_send_recv_by_dma()

ald_status_t ald_spi_send_recv_by_dma | ( | spi_handle_t * | hperh,
 |  | uint8_t * | tx_buf,
 |  | uint8_t * | rx_buf,
 |  | uint16_t | size,
 |  | uint8_t | tx_channel,
 |  | uint8_t | rx_channel
 | ) |  |

Transmit and Receive an amount of data used dma channel.

Parameters
hperh | Pointer to a spi_handle_t structure.
tx_buf | Pointer to data buffer
rx_buf | Pointer to data buffer
size | Amount of data to be sent
tx_channel | DMA channel as SPI transmit
rx_channel | DMA channel as SPI receive
Return values
Status,see ald_status_t.

Definition at line 1134 of file ald_spi.c.

1135 {
1136 assert_param(IS_SPI(hperh->perh));
1137
1138 if (hperh->state != SPI_STATE_READY && hperh->state != SPI_STATE_BUSY_RX)
1139 return BUSY;
1140 if (tx_buf == NULL || rx_buf == NULL || size == 0)
1141 return ERROR;
1142
1143 __LOCK(hperh);
1144 hperh->state = SPI_STATE_BUSY_RX;
1145 hperh->err_code = SPI_ERROR_NONE;
1146
1147 hperh->tx_buf = tx_buf;
1148 hperh->tx_size = size;
1149 hperh->tx_count = size;
1150 hperh->rx_buf = rx_buf;
1151 hperh->rx_size = size;
1152 hperh->rx_count = size;
1153
1154 if (hperh->hdmatx.perh == NULL)
1155 hperh->hdmatx.perh = DMA0;
1156 if (hperh->hdmarx.perh == NULL)
1157 hperh->hdmarx.perh = DMA0;
1158
1159 hperh->hdmatx.cplt_arg = NULL;
1160 hperh->hdmatx.cplt_cbk = NULL;
1161 hperh->hdmarx.cplt_arg = (void *)hperh;
1162 hperh->hdmarx.cplt_cbk = spi_dma_send_recv_cplt;
1163
1164 if (hperh->init.crc_calc)
1165 SPI_CRC_RESET(hperh);
1166
1167 /* Configure SPI DMA transmit */
1168 ald_dma_config_struct(&(hperh->hdmatx.config));
1169 hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD;
1170 hperh->hdmatx.config.src = (void *)tx_buf;
1171 hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA;
1172 hperh->hdmatx.config.size = size;
1173 hperh->hdmatx.config.src_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;
1174 hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
1175 hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2);
1176 hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY;
1177 hperh->hdmatx.config.burst = ENABLE;
1178 hperh->hdmatx.config.channel = tx_channel;
1179 ald_dma_config_basic(&(hperh->hdmatx));
1180
1181 /* Configure DMA Receive */
1182 ald_dma_config_struct(&(hperh->hdmarx.config));
1183 hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD;
1184 hperh->hdmarx.config.src = (void *)&hperh->perh->DATA;
1185 hperh->hdmarx.config.dst = (void *)rx_buf;
1186 hperh->hdmarx.config.size = size;
1187 hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE;
1188 hperh->hdmarx.config.dst_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;;
1189 hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2);
1190 hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR;
1191 hperh->hdmarx.config.burst = ENABLE;
1192 hperh->hdmarx.config.channel = rx_channel;
1193 ald_dma_config_basic(&(hperh->hdmarx));
1194
1195 __UNLOCK(hperh);
1196 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE);
1197 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE);
1198
1199 return OK;
1200 }
DMA_MSEL_SPI1
Definition: ald_dma.h:91
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
spi_handle_s::rx_buf
uint8_t * rx_buf
Definition: ald_spi.h:234
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
spi_dma_send_recv_cplt
static void spi_dma_send_recv_cplt(void *arg)
DMA SPI transmit and receive process complete callback.
Definition: ald_spi.c:1902
spi_handle_s::tx_buf
uint8_t * tx_buf
Definition: ald_spi.h:231
SPI_DMA_REQ_RX
Definition: ald_spi.h:170
DMA_MSEL_SPI2
Definition: ald_dma.h:99
spi_handle_s::tx_count
uint16_t tx_count
Definition: ald_spi.h:233
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
spi_init_t::crc_calc
type_func_t crc_calc
Definition: ald_spi.h:220
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
SPI_STATE_BUSY_RX
Definition: ald_spi.h:148
DMA_DATA_SIZE_BYTE
Definition: ald_dma.h:227
spi_handle_s::init
spi_init_t init
Definition: ald_spi.h:230
ald_spi_dma_req_config
void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state)
Enables or disables the dma request.
Definition: ald_spi.c:1398
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
SPI_DMA_REQ_TX
Definition: ald_spi.h:169
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_handle_s::state
spi_state_t state
Definition: ald_spi.h:242
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
DMA_MSIGSEL_SPI_RNR
Definition: ald_dma.h:141
DMA_DATA_INC_BYTE
Definition: ald_dma.h:217
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
spi_handle_s::tx_size
uint16_t tx_size
Definition: ald_spi.h:232
spi_handle_s::hdmarx
dma_handle_t hdmarx
Definition: ald_spi.h:239
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
spi_handle_s::hdmatx
dma_handle_t hdmatx
Definition: ald_spi.h:238
SPI_STATE_READY
Definition: ald_spi.h:145
spi_init_t::data_size
spi_datasize_t data_size
Definition: ald_spi.h:214
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
DMA_MSIGSEL_SPI_TXEMPTY
Definition: ald_dma.h:142
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
SPI_CRC_RESET
#define SPI_CRC_RESET(x)
Definition: ald_spi.h:260
spi_handle_s::err_code
uint32_t err_code
Definition: ald_spi.h:243
spi_handle_s::rx_size
uint16_t rx_size
Definition: ald_spi.h:235
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
DMA_MSEL_SPI0
Definition: ald_dma.h:90
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
SPI_DATA_SIZE_8
Definition: ald_spi.h:89
spi_handle_s::rx_count
uint16_t rx_count
Definition: ald_spi.h:236
SPI_ERROR_NONE
Definition: ald_spi.h:97
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294

◆ ald_spi_send_recv_by_it()

ald_status_t ald_spi_send_recv_by_it | ( | spi_handle_t * | hperh,
 |  | uint8_t * | tx_buf,
 |  | uint8_t * | rx_buf,
 |  | uint16_t | size
 | ) |  |

Transmit and Receives an amount of data in non blocking mode.

Parameters
hperh | Pointer to a spi_handle_t structure that contains the configuration information for the specified SPI module.
tx_buf | Pointer to data transmitted buffer
rx_buf | Pointer to data received buffer
size | Amount of data to be sent
Return values
Status,see ald_status_t.

Definition at line 939 of file ald_spi.c.

940 {
941 assert_param(IS_SPI(hperh->perh));
942
943 if (hperh->state != SPI_STATE_READY)
944 return BUSY;
945 if (tx_buf == NULL || rx_buf == NULL || size == 0)
946 return ERROR;
947
948 __LOCK(hperh);
949 hperh->state = SPI_STATE_BUSY_TX_RX;
950 hperh->err_code = SPI_ERROR_NONE;
951
952 hperh->tx_buf = tx_buf;
953 hperh->tx_size = size;
954 hperh->tx_count = size;
955 hperh->rx_buf = rx_buf;
956 hperh->rx_size = size;
957 hperh->rx_count = size;
958 __UNLOCK(hperh);
959
960 if (hperh->init.crc_calc) {
961 SPI_CRC_RESET(hperh);
962 ald_spi_interrupt_config(hperh, SPI_IT_CRCERR, ENABLE);
963 }
964
965 if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX))
966 SPI_ENABLE(hperh);
967
968 ald_spi_interrupt_config(hperh, SPI_IT_RXTH, ENABLE);
969 ald_spi_interrupt_config(hperh, SPI_IT_TXE, ENABLE);
970 ald_spi_interrupt_config(hperh, SPI_IT_MODF, ENABLE);
971
972 return OK;
973 }
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
spi_handle_s::rx_buf
uint8_t * rx_buf
Definition: ald_spi.h:234
SPI_ENABLE
#define SPI_ENABLE(x)
Definition: ald_spi.h:258
assert_param
#define assert_param(x)
Definition: type.h:88
SPI_STATE_BUSY_TX_RX
Definition: ald_spi.h:149
BUSY
Definition: utils.h:57
SPI_IT_CRCERR
Definition: ald_spi.h:118
ald_spi_interrupt_config
void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state)
Enables or disables the specified SPI interrupts.
Definition: ald_spi.c:1354
spi_handle_s::tx_buf
uint8_t * tx_buf
Definition: ald_spi.h:231
spi_handle_s::tx_count
uint16_t tx_count
Definition: ald_spi.h:233
spi_init_t::crc_calc
type_func_t crc_calc
Definition: ald_spi.h:220
SPI_IT_TXE
Definition: ald_spi.h:110
SPI_DIRECTION_2LINES_RXONLY
Definition: ald_spi.h:160
SPI_DIRECTION_1LINE_RX
Definition: ald_spi.h:162
spi_handle_s::init
spi_init_t init
Definition: ald_spi.h:230
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_handle_s::state
spi_state_t state
Definition: ald_spi.h:242
spi_handle_s::tx_size
uint16_t tx_size
Definition: ald_spi.h:232
spi_init_t::dir
spi_direction_t dir
Definition: ald_spi.h:213
SPI_STATE_READY
Definition: ald_spi.h:145
SPI_CRC_RESET
#define SPI_CRC_RESET(x)
Definition: ald_spi.h:260
spi_handle_s::err_code
uint32_t err_code
Definition: ald_spi.h:243
spi_handle_s::rx_size
uint16_t rx_size
Definition: ald_spi.h:235
SPI_IT_MODF
Definition: ald_spi.h:119
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
spi_handle_s::rx_count
uint16_t rx_count
Definition: ald_spi.h:236
SPI_ERROR_NONE
Definition: ald_spi.h:97
SPI_IT_RXTH
Definition: ald_spi.h:117


ALD User Manual: Control functions

Functions
Control functions
EASTSOFT ES32F3xx ALD » SPI » SPI Public Functions

SPI Control functions. More...

Collaboration diagram for Control functions:

Functions

void | ald_spi_irq_handler (spi_handle_t *hperh)
This function handles SPI interrupt request. More...
void | ald_spi_interrupt_config (spi_handle_t *hperh, spi_it_t it, type_func_t state)
Enables or disables the specified SPI interrupts. More...
void | ald_spi_speed_config (spi_handle_t *hperh, spi_baud_t speed)
Configure the specified SPI speed. More...
void | ald_spi_dma_req_config (spi_handle_t *hperh, spi_dma_req_t req, type_func_t state)
Enables or disables the dma request. More...
flag_status_t | spi_get_status (spi_handle_t *hperh, spi_status_t status)
Check whether the specified SPI state flag is set or not. More...
it_status_t | ald_spi_get_it_status (spi_handle_t *hperh, spi_it_t it)
Checks whether the specified SPI interrupt has occurred or not. More...
flag_status_t | ald_spi_get_flag_status (spi_handle_t *hperh, spi_flag_t flag)
Check whether the specified SPI flag is set or not. More...
void | ald_spi_clear_flag_status (spi_handle_t *hperh, spi_flag_t flag)
Clear the specified SPI pending flags. More...
static ald_status_t | spi_wait_bsy_flag (spi_handle_t *hperh, flag_status_t status, uint32_t timeout)
static ald_status_t | spi_wait_flag_irq (spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout)
This function handles SPI communication timeout in interrupt function. More...

Detailed Description

SPI Control functions.

===============================================================================
                   ##### Peripheral Control functions #####
===============================================================================
 [..]
 This subsection provides a set of functions allowing to control the SPI.
  (+) Handle interrupt about SPI module. The ald_spi_irq_handler() function must
      be invoked by SPI-IRQ function.
  (+) Configure the interrupt DISABLE/ENABLE.
  (+) Configure the DMA request.
  (+) Get interrupt source status.
  (+) Get interrupt flag status.
  (+) Clear interrupt flag

Function Documentation

◆ ald_spi_clear_flag_status()

void ald_spi_clear_flag_status | ( | spi_handle_t * | hperh,
 |  | spi_flag_t | flag
 | ) |  |

Clear the specified SPI pending flags.

Parameters
hperh | Pointer to a spi_handle_t structure.
flag | specifies the flag to check. This parameter can be one of the spi_flag_t.
Return values
None

Definition at line 1484 of file ald_spi.c.

1485 {
1486 assert_param(IS_SPI(hperh->perh));
1487 assert_param(IS_SPI_IF(flag));
1488
1489
1490 hperh->perh->ICR |= flag;
1491 return;
1492 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_SPI_IF
#define IS_SPI_IF(x)
Definition: ald_spi.h:335
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229

◆ ald_spi_dma_req_config()

void ald_spi_dma_req_config | ( | spi_handle_t * | hperh,
 |  | spi_dma_req_t | req,
 |  | type_func_t | state
 | ) |  |

Enables or disables the dma request.

Parameters
hperh | Pointer to a spi_handle_t structure.
req | Specifies the SPI dma request sources to be enabled or disabled. This parameter can be one of the spi_dma_req_t.
state New status
  • ENABLE
  • DISABLE
Return values
None

Definition at line 1398 of file ald_spi.c.

1399 {
1400 assert_param(IS_SPI(hperh->perh));
1401 assert_param(IS_SPI_DMA_REQ(req));
1402 assert_param(IS_FUNC_STATE(state));
1403
1404 if (state == ENABLE) {
1405 if (req == SPI_DMA_REQ_TX)
1406 SET_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK);
1407 else
1408 SET_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK);
1409 }
1410 else {
1411 if (req == SPI_DMA_REQ_TX)
1412 CLEAR_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK);
1413 else
1414 CLEAR_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK);
1415 }
1416
1417 return;
1418 }
ENABLE
Definition: type.h:49
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_SPI_DMA_REQ
#define IS_SPI_DMA_REQ(x)
Definition: ald_spi.h:311
SPI_DMA_REQ_TX
Definition: ald_spi.h:169
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_spi_get_flag_status()

flag_status_t ald_spi_get_flag_status | ( | spi_handle_t * | hperh,
 |  | spi_flag_t | flag
 | ) |  |

Check whether the specified SPI flag is set or not.

Parameters
hperh | Pointer to a spi_handle_t structure.
flag | specifies the flag to check. This parameter can be one of the spi_flag_t.
Return values
Status
  • SET
  • RESET

Definition at line 1467 of file ald_spi.c.

1468 {
1469 assert_param(IS_SPI(hperh->perh));
1470 assert_param(IS_SPI_IF(flag));
1471
1472 if (hperh->perh->RIF & flag)
1473 return SET;
1474
1475 return RESET;
1476 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
IS_SPI_IF
#define IS_SPI_IF(x)
Definition: ald_spi.h:335
RESET
Definition: type.h:38
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229

◆ ald_spi_get_it_status()

it_status_t ald_spi_get_it_status | ( | spi_handle_t * | hperh,
 |  | spi_it_t | it
 | ) |  |

Checks whether the specified SPI interrupt has occurred or not.

Parameters
hperh | Pointer to a spi_handle_t structure.
it | Specifies the SPI interrupt source to check. This parameter can be one of the spi_it_t.
Return values
Status
  • SET
  • RESET

Definition at line 1448 of file ald_spi.c.

1449 {
1450 assert_param(IS_SPI(hperh->perh));
1451 assert_param(IS_SPI_IT(it));
1452
1453 if (hperh->perh->IVS & it)
1454 return SET;
1455
1456 return RESET;
1457 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
RESET
Definition: type.h:38
IS_SPI_IT
#define IS_SPI_IT(x)
Definition: ald_spi.h:324
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229

◆ ald_spi_interrupt_config()

void ald_spi_interrupt_config | ( | spi_handle_t * | hperh,
 |  | spi_it_t | it,
 |  | type_func_t | state
 | ) |  |

Enables or disables the specified SPI interrupts.

Parameters
hperh | Pointer to a spi_handle_t structure.
it | Specifies the SPI interrupt sources to be enabled or disabled. This parameter can be one of the spi_it_t.
state New status
  • ENABLE
  • DISABLE
Return values
None

Definition at line 1354 of file ald_spi.c.

1355 {
1356 assert_param(IS_SPI(hperh->perh));
1357 assert_param(IS_SPI_IT(it));
1358 assert_param(IS_FUNC_STATE(state));
1359
1360 if (state == ENABLE)
1361 hperh->perh->IER |= (uint32_t)it;
1362 else
1363 hperh->perh->IDR |= (uint32_t)it;
1364
1365 return;
1366 }
ENABLE
Definition: type.h:49
assert_param
#define assert_param(x)
Definition: type.h:88
IS_SPI_IT
#define IS_SPI_IT(x)
Definition: ald_spi.h:324
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_spi_irq_handler()

void ald_spi_irq_handler ( spi_handle_t * hperh )

This function handles SPI interrupt request.

Parameters
hperh Pointer to a spi_handle_t structure.
Return values
None

Definition at line 1284 of file ald_spi.c.

1285 {
1286 if ((hperh->state == SPI_STATE_BUSY_RX) || (hperh->state == SPI_STATE_BUSY_TX)) {
1287 if ((ald_spi_get_it_status(hperh, SPI_IT_RXTH) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXTH) != RESET))
1288 __spi_recv_by_it(hperh);
1289
1290 if ((ald_spi_get_it_status(hperh, SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXE) != RESET))
1291 __spi_send_by_it(hperh);
1292 }
1293
1294 else if (hperh->state == SPI_STATE_BUSY_TX_RX) {
1295 if (hperh->init.mode == SPI_MODE_SLAVER) {
1296 if ((ald_spi_get_it_status(hperh, SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXE) != RESET))
1297 __spi_send_recv_by_it(hperh, SPI_SR_TXE);
1298 if ((ald_spi_get_it_status(hperh, SPI_IT_RXTH) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXTH) != RESET))
1299 __spi_send_recv_by_it(hperh, SPI_SR_RXNE);
1300 }
1301 else {
1302 if (hperh->rx_size == hperh->tx_count) {
1303 if ((ald_spi_get_it_status(hperh, SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXE) != RESET))
1304 __spi_send_recv_by_it(hperh, SPI_SR_TXE);
1305 }
1306 else {
1307 if ((ald_spi_get_it_status(hperh, SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXE) != RESET)
1308 && (ald_spi_get_it_status(hperh, SPI_IT_RXTH) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXTH) != RESET))
1309 __spi_send_recv_by_it(hperh, SPI_SR_TXE_RXNE);
1310 }
1311 }
1312
1313 }
1314
1315 if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET) {
1316 hperh->err_code |= SPI_ERROR_CRC;
1317 ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR);
1318 }
1319 if (ald_spi_get_flag_status(hperh, SPI_IF_MODF) != RESET) {
1320 hperh->err_code |= SPI_ERROR_MODF;
1321 ald_spi_clear_flag_status(hperh, SPI_IF_MODF);
1322 }
1323 if (ald_spi_get_flag_status(hperh, SPI_IF_FRE) != RESET) {
1324 hperh->err_code |= SPI_ERROR_FRE;
1325 ald_spi_clear_flag_status(hperh, SPI_IF_FRE);
1326
1327 }
1328 if (ald_spi_get_flag_status(hperh, SPI_IF_TXOV) != RESET) {
1329 if (hperh->state != SPI_STATE_BUSY_TX) {
1330 hperh->err_code |= SPI_ERROR_TXOV;
1331 ald_spi_clear_flag_status(hperh, SPI_IF_TXOV);
1332 }
1333 }
1334 if (ald_spi_get_flag_status(hperh, SPI_IF_RXOV) != RESET) {
1335 if (hperh->state != SPI_STATE_BUSY_RX) {
1336 hperh->err_code |= SPI_ERROR_RXOV;
1337 ald_spi_clear_flag_status(hperh, SPI_IF_RXOV);
1338 }
1339 }
1340
1341 return;
1342 }
ald_spi_get_it_status
it_status_t ald_spi_get_it_status(spi_handle_t *hperh, spi_it_t it)
Checks whether the specified SPI interrupt has occurred or not.
Definition: ald_spi.c:1448
SPI_STATE_BUSY_TX_RX
Definition: ald_spi.h:149
SPI_ERROR_CRC
Definition: ald_spi.h:99
SPI_ERROR_RXOV
Definition: ald_spi.h:101
__spi_send_recv_by_it
static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status)
handle program when an rx no empty interrupt flag arrived in non block mode(2 lines) ...
Definition: ald_spi.c:1730
spi_handle_s::tx_count
uint16_t tx_count
Definition: ald_spi.h:233
SPI_ERROR_MODF
Definition: ald_spi.h:98
SPI_IF_TXOV
Definition: ald_spi.h:128
ald_spi_get_flag_status
flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag)
Check whether the specified SPI flag is set or not.
Definition: ald_spi.c:1467
SPI_ERROR_TXOV
Definition: ald_spi.h:102
SPI_IT_TXE
Definition: ald_spi.h:110
SPI_STATE_BUSY_RX
Definition: ald_spi.h:148
RESET
Definition: type.h:38
ald_spi_clear_flag_status
void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag)
Clear the specified SPI pending flags.
Definition: ald_spi.c:1484
SPI_MODE_SLAVER
Definition: ald_spi.h:59
spi_handle_s::init
spi_init_t init
Definition: ald_spi.h:230
SPI_IF_RXOV
Definition: ald_spi.h:132
SPI_STATE_BUSY_TX
Definition: ald_spi.h:147
spi_handle_s::state
spi_state_t state
Definition: ald_spi.h:242
SPI_IF_CRCERR
Definition: ald_spi.h:135
__spi_send_by_it
static void __spi_send_by_it(spi_handle_t *hperh)
handle program when an tx empty interrupt flag arrived in non block mode
Definition: ald_spi.c:1597
SPI_IF_TXE
Definition: ald_spi.h:127
spi_init_t::mode
spi_mode_t mode
Definition: ald_spi.h:212
SPI_SR_TXE_RXNE
Definition: ald_spi.h:204
__spi_recv_by_it
static void __spi_recv_by_it(spi_handle_t *hperh)
handle program when an rx no empty interrupt flag arrived in non block mode
Definition: ald_spi.c:1672
spi_handle_s::err_code
uint32_t err_code
Definition: ald_spi.h:243
SPI_SR_RXNE
Definition: ald_spi.h:203
SPI_IF_RXTH
Definition: ald_spi.h:134
spi_handle_s::rx_size
uint16_t rx_size
Definition: ald_spi.h:235
SPI_IT_RXTH
Definition: ald_spi.h:117
SPI_IF_MODF
Definition: ald_spi.h:136
SPI_ERROR_FRE
Definition: ald_spi.h:100
SPI_IF_FRE
Definition: ald_spi.h:137
SPI_SR_TXE
Definition: ald_spi.h:202

◆ ald_spi_speed_config()

void ald_spi_speed_config | ( | spi_handle_t * | hperh,
 |  | spi_baud_t | speed
 | ) |  |

Configure the specified SPI speed.

Parameters
hperh | Pointer to a spi_handle_t structure.
speed | Specifies the SPI speed. This parameter can be one of the spi_baud_t.
Return values
None

Definition at line 1375 of file ald_spi.c.

1376 {
1377 uint32_t tmp = 0;
1378 assert_param(IS_SPI(hperh->perh));
1379 assert_param(IS_SPI_BAUD(speed));
1380
1381 tmp = hperh->perh->CON1;
1382 tmp &= ~(0x7U << SPI_CON1_BAUD_POSS);
1383 tmp |= (speed << SPI_CON1_BAUD_POSS);
1384 hperh->perh->CON1 = tmp;
1385 return;
1386 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
IS_SPI_BAUD
#define IS_SPI_BAUD(x)
Definition: ald_spi.h:293

◆ spi_get_status()

flag_status_t spi_get_status | ( | spi_handle_t * | hperh,
 |  | spi_status_t | status
 | ) |  |

Check whether the specified SPI state flag is set or not.

Parameters
hperh | Pointer to a spi_handle_t structure.
status | specifies the flag to check. This parameter can be one of the spi_status_t.
Return values
Status
  • SET
  • RESET

Definition at line 1428 of file ald_spi.c.

1429 {
1430 assert_param(IS_SPI(hperh->perh));
1431 assert_param(IS_SPI_STATUS(status));
1432
1433 if (hperh->perh->STAT & status)
1434 return SET;
1435
1436 return RESET;
1437 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
RESET
Definition: type.h:38
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
IS_SPI_STATUS
#define IS_SPI_STATUS(x)
Definition: ald_spi.h:313

◆ spi_wait_bsy_flag()

static ald_status_t spi_wait_bsy_flag | ( | spi_handle_t * | hperh,
 |  | flag_status_t | status,
 |  | uint32_t | timeout
 | ) |  |
static

Definition at line 1521 of file ald_spi.c.

1522 {
1523 assert_param(timeout > 0);
1524
1525 while ((READ_BIT(hperh->perh->STAT, SPI_STAT_BUSY_MSK)) && (--timeout));
1526
1527 if (timeout)
1528 return OK;
1529
1530 ald_spi_interrupt_config(hperh, SPI_IT_TXE, DISABLE);
1531 ald_spi_interrupt_config(hperh, SPI_IT_RXTH, DISABLE);
1532 ald_spi_interrupt_config(hperh, SPI_IT_CRCERR, DISABLE);
1533 ald_spi_interrupt_config(hperh, SPI_IT_MODF, DISABLE);
1534
1535 return TIMEOUT;
1536 }
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
SPI_IT_CRCERR
Definition: ald_spi.h:118
ald_spi_interrupt_config
void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state)
Enables or disables the specified SPI interrupts.
Definition: ald_spi.c:1354
DISABLE
Definition: type.h:48
SPI_IT_TXE
Definition: ald_spi.h:110
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
TIMEOUT
Definition: utils.h:58
SPI_IT_MODF
Definition: ald_spi.h:119
SPI_IT_RXTH
Definition: ald_spi.h:117

◆ spi_wait_flag_irq()

static ald_status_t spi_wait_flag_irq | ( | spi_handle_t * | hperh,
 |  | spi_flag_t | flag,
 |  | flag_status_t | status,
 |  | uint32_t | timeout
 | ) |  |
static

This function handles SPI communication timeout in interrupt function.

Parameters
hperh | Pointer to a spi_handle_t structure.
flag | specifies the SPI flag to check.
status | The new Flag status (SET or RESET).
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 1503 of file ald_spi.c.

1504 {
1505 assert_param(timeout > 0);
1506
1507 while (((ald_spi_get_flag_status(hperh, flag)) != status) && (--timeout));
1508
1509 if (timeout)
1510 return OK;
1511
1512 ald_spi_interrupt_config(hperh, SPI_IT_TXE, DISABLE);
1513 ald_spi_interrupt_config(hperh, SPI_IT_RXTH, DISABLE);
1514 ald_spi_interrupt_config(hperh, SPI_IT_CRCERR, DISABLE);
1515 ald_spi_interrupt_config(hperh, SPI_IT_MODF, DISABLE);
1516
1517 return TIMEOUT;
1518 }
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
SPI_IT_CRCERR
Definition: ald_spi.h:118
ald_spi_interrupt_config
void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state)
Enables or disables the specified SPI interrupts.
Definition: ald_spi.c:1354
DISABLE
Definition: type.h:48
ald_spi_get_flag_status
flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag)
Check whether the specified SPI flag is set or not.
Definition: ald_spi.c:1467
SPI_IT_TXE
Definition: ald_spi.h:110
TIMEOUT
Definition: utils.h:58
SPI_IT_MODF
Definition: ald_spi.h:119
SPI_IT_RXTH
Definition: ald_spi.h:117


ALD User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
EASTSOFT ES32F3xx ALD » SPI » SPI Public Functions

SPI State and Errors functions. More...

Collaboration diagram for Peripheral State and Errors functions:

Functions

spi_state_t | ald_spi_get_state (spi_handle_t *hperh)
Returns the SPI state. More...
uint32_t | ald_spi_get_error (spi_handle_t *hperh)
Return the SPI error code. More...

Detailed Description

SPI State and Errors functions.

===============================================================================
                     ##### Peripheral State and Errors functions #####
===============================================================================
   [..]
   This subsection provides a set of functions allowing to control the SPI.
    (+) ald_spi_get_state() API can check in run-time the state of the SPI peripheral
    (+) ald_spi_get_error() check in run-time Errors occurring during communication

Function Documentation

◆ ald_spi_get_error()

uint32_t ald_spi_get_error ( spi_handle_t * hperh )

Return the SPI error code.

Parameters
hperh Pointer to a spi_handle_t structure.
Return values
SPI Error Code

Definition at line 1574 of file ald_spi.c.

1575 {
1576 assert_param(IS_SPI(hperh->perh));
1577 return hperh->err_code;
1578 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_handle_s::err_code
uint32_t err_code
Definition: ald_spi.h:243

◆ ald_spi_get_state()

spi_state_t ald_spi_get_state ( spi_handle_t * hperh )

Returns the SPI state.

Parameters
hperh Pointer to a spi_handle_t structure.
Return values
ALD state

Definition at line 1563 of file ald_spi.c.

1564 {
1565 assert_param(IS_SPI(hperh->perh));
1566 return hperh->state;
1567 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_handle_s::state
spi_state_t state
Definition: ald_spi.h:242


ALD User Manual: SPI Private Functions

Functions
SPI Private Functions
EASTSOFT ES32F3xx ALD » SPI

SPI Private functions. More...

Collaboration diagram for SPI Private Functions:

Functions

static void | __spi_send_by_it (spi_handle_t *hperh)
handle program when an tx empty interrupt flag arrived in non block mode More...
static void | __spi_recv_by_it (spi_handle_t *hperh)
handle program when an rx no empty interrupt flag arrived in non block mode More...
static void | __spi_send_recv_by_it (spi_handle_t *hperh, spi_sr_status_t status)
handle program when an rx no empty interrupt flag arrived in non block mode(2 lines) More...
static void | spi_dma_send_cplt (void *arg)
DMA SPI transmit process complete callback. More...
static void | spi_dma_recv_cplt (void *arg)
DMA SPI receive process complete callback. More...
static void | spi_dma_send_recv_cplt (void *arg)
DMA SPI transmit and receive process complete callback. More...

Detailed Description

SPI Private functions.

Function Documentation

◆ __spi_recv_by_it()

static void __spi_recv_by_it ( spi_handle_t * hperh )
static

handle program when an rx no empty interrupt flag arrived in non block mode

Parameters
hperh Pointer to a spi_handle_t structure.
Return values
Status,see ald_status_t.

Definition at line 1672 of file ald_spi.c.

1673 {
1674 uint16_t temp;
1675
1676 while (READ_BITS(hperh->perh->STAT, SPI_STAT_RXFLV_MSK, SPI_STAT_RXFLV_POSS)) {
1677 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
1678 *hperh->rx_buf = hperh->perh->DATA;
1679 ++hperh->rx_buf;
1680 }
1681 else {
1682 *(uint16_t *)hperh->rx_buf = hperh->perh->DATA;
1683 hperh->rx_buf += 2;
1684 }
1685
1686 --hperh->rx_count;
1687 }
1688
1689 ald_spi_clear_flag_status(hperh, SPI_IF_RXTH);
1690
1691 if (hperh->rx_count == 0) {
1692 ald_spi_interrupt_config(hperh, SPI_IT_RXTH, DISABLE);
1693 hperh->state = SPI_STATE_READY;
1694
1695 if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) {
1696 hperh->err_code |= SPI_ERROR_CRC;
1697 ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR);
1698
1699 if (hperh->err_cbk)
1700 hperh->err_cbk(hperh);
1701
1702 return;
1703 }
1704
1705 if (hperh->init.crc_calc) {
1706 temp = hperh->perh->DATA;
1707 UNUSED(temp);
1708 }
1709
1710 if (hperh->rx_cplt_cbk)
1711 hperh->rx_cplt_cbk(hperh);
1712 }
1713
1714 if (hperh->init.data_size <= SPI_DATA_SIZE_8) {
1715 hperh->perh->DATA = 0xff;
1716 }
1717 else {
1718 hperh->perh->DATA = 0xffff;
1719 }
1720
1721 return;
1722 }
spi_handle_s::rx_buf
uint8_t * rx_buf
Definition: ald_spi.h:234
SPI_ERROR_CRC
Definition: ald_spi.h:99
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
ald_spi_interrupt_config
void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state)
Enables or disables the specified SPI interrupts.
Definition: ald_spi.c:1354
DISABLE
Definition: type.h:48
spi_init_t::crc_calc
type_func_t crc_calc
Definition: ald_spi.h:220
ald_spi_get_flag_status
flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag)
Check whether the specified SPI flag is set or not.
Definition: ald_spi.c:1467
spi_handle_s::err_cbk
void(* err_cbk)(struct spi_handle_s *arg)
Definition: ald_spi.h:248
RESET
Definition: type.h:38
ald_spi_clear_flag_status
void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag)
Clear the specified SPI pending flags.
Definition: ald_spi.c:1484
UNUSED
#define UNUSED(x)
Definition: type.h:76
spi_handle_s::init
spi_init_t init
Definition: ald_spi.h:230
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_handle_s::state
spi_state_t state
Definition: ald_spi.h:242
SPI_IF_CRCERR
Definition: ald_spi.h:135
spi_handle_s::rx_cplt_cbk
void(* rx_cplt_cbk)(struct spi_handle_s *arg)
Definition: ald_spi.h:246
SPI_STATE_READY
Definition: ald_spi.h:145
spi_init_t::data_size
spi_datasize_t data_size
Definition: ald_spi.h:214
spi_handle_s::err_code
uint32_t err_code
Definition: ald_spi.h:243
SPI_IF_RXTH
Definition: ald_spi.h:134
SPI_DATA_SIZE_8
Definition: ald_spi.h:89
spi_handle_s::rx_count
uint16_t rx_count
Definition: ald_spi.h:236
SPI_IT_RXTH
Definition: ald_spi.h:117

◆ __spi_send_by_it()

static void __spi_send_by_it ( spi_handle_t * hperh )
static

handle program when an tx empty interrupt flag arrived in non block mode

Parameters
hperh Pointer to a spi_handle_t structure.
Return values
Status,see ald_status_t.

Definition at line 1597 of file ald_spi.c.

1598 {
1599 uint16_t temp;
1600
1601 if (hperh->tx_count == 0) {
1602 ald_spi_interrupt_config(hperh, SPI_IT_TXE, DISABLE);
1603 hperh->state = SPI_STATE_READY;
1604
1605 if (hperh->init.dir == SPI_DIRECTION_2LINES) {
1606 ald_spi_clear_flag_status(hperh, SPI_IF_TXOV);
1607 }
1608
1609 if ((spi_wait_bsy_flag(hperh, RESET, 5000)) != OK) {
1610 if (hperh->err_cbk)
1611 hperh->err_cbk(hperh);
1612
1613 return;
1614 }
1615
1616 while ((spi_get_status(hperh, SPI_STATUS_RXE)) == RESET) {
1617 temp = hperh->perh->DATA;
1618 UNUSED(temp);
1619 }
1620
1621 if (hperh->tx_cplt_cbk)
1622 hperh->tx_cplt_cbk(hperh);
1623
1624 return;
1625 }
1626
1627 ald_spi_clear_flag_status(hperh, SPI_IF_TXE);
1628
1629 if (hperh->tx_count == 1) {
1630 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
1631 if (hperh->init.crc_calc) {
1632 hperh->perh->DATA = *hperh->tx_buf;
1633 SPI_CRCNEXT_ENABLE(hperh);
1634 }
1635 else {
1636 hperh->perh->DATA = *hperh->tx_buf;
1637 }
1638
1639 ++hperh->tx_buf;
1640 }
1641 else {
1642 if (hperh->init.crc_calc) {
1643 hperh->perh->DATA = *(uint16_t *)hperh->tx_buf;
1644 SPI_CRCNEXT_ENABLE(hperh);
1645 }
1646 else
1647 hperh->perh->DATA = *(uint16_t *)hperh->tx_buf;
1648
1649 hperh->tx_buf += 2;
1650 }
1651 }
1652 else {
1653 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
1654 hperh->perh->DATA = *hperh->tx_buf;
1655 ++hperh->tx_buf;
1656 }
1657 else {
1658 hperh->perh->DATA = *(uint16_t *)hperh->tx_buf;
1659 hperh->tx_buf += 2;
1660 }
1661 }
1662
1663 --hperh->tx_count;
1664 return;
1665 }
OK
Definition: utils.h:55
ald_spi_interrupt_config
void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state)
Enables or disables the specified SPI interrupts.
Definition: ald_spi.c:1354
spi_handle_s::tx_buf
uint8_t * tx_buf
Definition: ald_spi.h:231
DISABLE
Definition: type.h:48
spi_handle_s::tx_count
uint16_t tx_count
Definition: ald_spi.h:233
spi_init_t::crc_calc
type_func_t crc_calc
Definition: ald_spi.h:220
SPI_IF_TXOV
Definition: ald_spi.h:128
spi_handle_s::err_cbk
void(* err_cbk)(struct spi_handle_s *arg)
Definition: ald_spi.h:248
SPI_IT_TXE
Definition: ald_spi.h:110
SPI_DIRECTION_2LINES
Definition: ald_spi.h:159
RESET
Definition: type.h:38
ald_spi_clear_flag_status
void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag)
Clear the specified SPI pending flags.
Definition: ald_spi.c:1484
UNUSED
#define UNUSED(x)
Definition: type.h:76
spi_handle_s::init
spi_init_t init
Definition: ald_spi.h:230
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_get_status
flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status)
Check whether the specified SPI state flag is set or not.
Definition: ald_spi.c:1428
spi_handle_s::state
spi_state_t state
Definition: ald_spi.h:242
spi_wait_bsy_flag
static ald_status_t spi_wait_bsy_flag(spi_handle_t *hperh, flag_status_t status, uint32_t timeout)
Definition: ald_spi.c:1521
SPI_IF_TXE
Definition: ald_spi.h:127
SPI_STATUS_RXE
Definition: ald_spi.h:190
spi_init_t::dir
spi_direction_t dir
Definition: ald_spi.h:213
SPI_STATE_READY
Definition: ald_spi.h:145
spi_init_t::data_size
spi_datasize_t data_size
Definition: ald_spi.h:214
SPI_CRCNEXT_ENABLE
#define SPI_CRCNEXT_ENABLE(x)
Definition: ald_spi.h:265
SPI_DATA_SIZE_8
Definition: ald_spi.h:89
spi_handle_s::tx_cplt_cbk
void(* tx_cplt_cbk)(struct spi_handle_s *arg)
Definition: ald_spi.h:245

◆ __spi_send_recv_by_it()

static void __spi_send_recv_by_it | ( | spi_handle_t * | hperh,
 |  | spi_sr_status_t | status
 | ) |  |
static

handle program when an rx no empty interrupt flag arrived in non block mode(2 lines)

Parameters
hperh | Pointer to a spi_handle_t structure.
status | SR.TXE or SR.RXNE set.
Return values
Status,see ald_status_t.

Definition at line 1730 of file ald_spi.c.

1731 {
1732 if (hperh->rx_count != 0) {
1733 if ((status == SPI_SR_RXNE) || (status == SPI_SR_TXE_RXNE)) {
1734 ald_spi_clear_flag_status(hperh, SPI_IF_RXTH);
1735 while (spi_get_status(hperh, SPI_STATUS_RXTH) != RESET) {
1736 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
1737 *hperh->rx_buf = hperh->perh->DATA;
1738 ++hperh->rx_buf;
1739 }
1740 else {
1741 *(uint16_t *)hperh->rx_buf = hperh->perh->DATA;
1742 hperh->rx_buf += 2;
1743 }
1744 --hperh->rx_count;
1745 }
1746 }
1747 }
1748
1749 if (hperh->tx_count != 0) {
1750 if ((status == SPI_SR_TXE) || (status == SPI_SR_TXE_RXNE)) {
1751 ald_spi_clear_flag_status(hperh, SPI_IF_TXE);
1752 if (hperh->tx_count == 1) {
1753 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
1754 if (hperh->init.crc_calc) {
1755 hperh->perh->DATA = *hperh->tx_buf;
1756 SPI_CRCNEXT_ENABLE(hperh);
1757 }
1758 else {
1759 hperh->perh->DATA = *hperh->tx_buf;
1760 }
1761
1762 ++hperh->tx_buf;
1763 }
1764 else {
1765 if (hperh->init.crc_calc) {
1766 hperh->perh->DATA = *(uint16_t *)hperh->tx_buf;
1767 SPI_CRCNEXT_ENABLE(hperh);
1768 }
1769 else {
1770 hperh->perh->DATA = *(uint16_t *)hperh->tx_buf;
1771 }
1772
1773 hperh->tx_buf += 2;
1774 }
1775
1776 --hperh->tx_count;
1777 }
1778 else {
1779 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
1780 hperh->perh->DATA = *hperh->tx_buf;
1781 ++hperh->tx_buf;
1782 }
1783 else {
1784 hperh->perh->DATA = *(uint16_t *)hperh->tx_buf;
1785 hperh->tx_buf += 2;
1786 }
1787
1788 --hperh->tx_count;
1789 }
1790 }
1791 }
1792
1793 if (hperh->rx_count == 0) {
1794 ald_spi_interrupt_config(hperh, SPI_IT_TXE, DISABLE);
1795 ald_spi_interrupt_config(hperh, SPI_IT_RXTH, DISABLE);
1796 ald_spi_interrupt_config(hperh, SPI_IT_MODF, DISABLE);
1797 hperh->state = SPI_STATE_READY;
1798
1799 if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) {
1800 hperh->err_code |= SPI_ERROR_CRC;
1801 ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR);
1802
1803 if (hperh->err_cbk)
1804 hperh->err_cbk(hperh);
1805
1806 return;
1807 }
1808
1809 if (hperh->tx_rx_cplt_cbk)
1810 hperh->tx_rx_cplt_cbk(hperh);
1811 }
1812
1813 return;
1814 }
spi_handle_s::rx_buf
uint8_t * rx_buf
Definition: ald_spi.h:234
SPI_ERROR_CRC
Definition: ald_spi.h:99
ald_spi_interrupt_config
void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state)
Enables or disables the specified SPI interrupts.
Definition: ald_spi.c:1354
spi_handle_s::tx_buf
uint8_t * tx_buf
Definition: ald_spi.h:231
DISABLE
Definition: type.h:48
spi_handle_s::tx_count
uint16_t tx_count
Definition: ald_spi.h:233
spi_init_t::crc_calc
type_func_t crc_calc
Definition: ald_spi.h:220
spi_handle_s::tx_rx_cplt_cbk
void(* tx_rx_cplt_cbk)(struct spi_handle_s *arg)
Definition: ald_spi.h:247
ald_spi_get_flag_status
flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag)
Check whether the specified SPI flag is set or not.
Definition: ald_spi.c:1467
spi_handle_s::err_cbk
void(* err_cbk)(struct spi_handle_s *arg)
Definition: ald_spi.h:248
SPI_IT_TXE
Definition: ald_spi.h:110
RESET
Definition: type.h:38
ald_spi_clear_flag_status
void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag)
Clear the specified SPI pending flags.
Definition: ald_spi.c:1484
SPI_STATUS_RXTH
Definition: ald_spi.h:194
spi_handle_s::init
spi_init_t init
Definition: ald_spi.h:230
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_get_status
flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status)
Check whether the specified SPI state flag is set or not.
Definition: ald_spi.c:1428
spi_handle_s::state
spi_state_t state
Definition: ald_spi.h:242
SPI_IF_CRCERR
Definition: ald_spi.h:135
SPI_IF_TXE
Definition: ald_spi.h:127
SPI_SR_TXE_RXNE
Definition: ald_spi.h:204
SPI_STATE_READY
Definition: ald_spi.h:145
spi_init_t::data_size
spi_datasize_t data_size
Definition: ald_spi.h:214
SPI_CRCNEXT_ENABLE
#define SPI_CRCNEXT_ENABLE(x)
Definition: ald_spi.h:265
spi_handle_s::err_code
uint32_t err_code
Definition: ald_spi.h:243
SPI_SR_RXNE
Definition: ald_spi.h:203
SPI_IF_RXTH
Definition: ald_spi.h:134
SPI_IT_MODF
Definition: ald_spi.h:119
SPI_DATA_SIZE_8
Definition: ald_spi.h:89
spi_handle_s::rx_count
uint16_t rx_count
Definition: ald_spi.h:236
SPI_IT_RXTH
Definition: ald_spi.h:117
SPI_SR_TXE
Definition: ald_spi.h:202

◆ spi_dma_recv_cplt()

static void spi_dma_recv_cplt ( void * arg )
static

DMA SPI receive process complete callback.

Parameters
arg Pointer to a spi_handle_t structure.
Return values
None

Definition at line 1861 of file ald_spi.c.

1862 {
1863 uint32_t tmp;
1864 spi_handle_t *hperh = (spi_handle_t *)arg;
1865
1866 hperh->rx_count = 0;
1867 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE);
1868 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE);
1869 hperh->state = SPI_STATE_READY;
1870
1871 if (hperh->init.crc_calc) {
1872 if ((spi_wait_flag_irq(hperh, SPI_IF_RXTH, SET, 5000)) != OK)
1873 hperh->err_code |= SPI_ERROR_FLAG;
1874
1875 tmp = hperh->perh->DATA;
1876 UNUSED(tmp);
1877
1878 if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) {
1879 SET_BIT(hperh->err_code, SPI_ERROR_CRC);
1880 SPI_CRC_RESET(hperh);
1881 ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR);
1882 }
1883 }
1884
1885 if (hperh->err_code == SPI_ERROR_NONE) {
1886 if (hperh->rx_cplt_cbk)
1887 hperh->rx_cplt_cbk(hperh);
1888 }
1889 else {
1890 if (hperh->err_cbk)
1891 hperh->err_cbk(hperh);
1892 }
1893
1894 return;
1895 }
SPI_ERROR_FLAG
Definition: ald_spi.h:103
OK
Definition: utils.h:55
SPI_ERROR_CRC
Definition: ald_spi.h:99
SET
Definition: type.h:39
SPI_DMA_REQ_RX
Definition: ald_spi.h:170
DISABLE
Definition: type.h:48
spi_init_t::crc_calc
type_func_t crc_calc
Definition: ald_spi.h:220
ald_spi_get_flag_status
flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag)
Check whether the specified SPI flag is set or not.
Definition: ald_spi.c:1467
spi_handle_s::err_cbk
void(* err_cbk)(struct spi_handle_s *arg)
Definition: ald_spi.h:248
ald_spi_clear_flag_status
void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag)
Clear the specified SPI pending flags.
Definition: ald_spi.c:1484
UNUSED
#define UNUSED(x)
Definition: type.h:76
spi_wait_flag_irq
static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout)
This function handles SPI communication timeout in interrupt function.
Definition: ald_spi.c:1503
spi_handle_s
SPI handle structure definition.
Definition: ald_spi.h:228
spi_handle_s::init
spi_init_t init
Definition: ald_spi.h:230
ald_spi_dma_req_config
void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state)
Enables or disables the dma request.
Definition: ald_spi.c:1398
SPI_DMA_REQ_TX
Definition: ald_spi.h:169
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_handle_s::state
spi_state_t state
Definition: ald_spi.h:242
SPI_IF_CRCERR
Definition: ald_spi.h:135
spi_handle_s::rx_cplt_cbk
void(* rx_cplt_cbk)(struct spi_handle_s *arg)
Definition: ald_spi.h:246
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
SPI_STATE_READY
Definition: ald_spi.h:145
SPI_CRC_RESET
#define SPI_CRC_RESET(x)
Definition: ald_spi.h:260
spi_handle_s::err_code
uint32_t err_code
Definition: ald_spi.h:243
SPI_IF_RXTH
Definition: ald_spi.h:134
spi_handle_s::rx_count
uint16_t rx_count
Definition: ald_spi.h:236
SPI_ERROR_NONE
Definition: ald_spi.h:97

◆ spi_dma_send_cplt()

static void spi_dma_send_cplt ( void * arg )
static

DMA SPI transmit process complete callback.

Parameters
arg Pointer to a spi_handle_t structure.
Return values
None

Definition at line 1822 of file ald_spi.c.

1823 {
1824 uint16_t delay, temp;
1825 spi_handle_t *hperh = (spi_handle_t *)arg;
1826
1827 hperh->tx_count = 0;
1828 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE);
1829 hperh->state = SPI_STATE_READY;
1830
1831 while ((spi_get_status(hperh, SPI_STATUS_RXE)) == RESET) {
1832 temp = hperh->perh->DATA;
1833 UNUSED(temp);
1834 }
1835
1836 if (hperh->init.dir == SPI_DIRECTION_2LINES)
1837 ald_spi_clear_flag_status(hperh, SPI_IF_TXOV);
1838
1839 if ((spi_wait_bsy_flag(hperh, RESET, 5000)) != OK)
1840 hperh->err_code |= SPI_ERROR_FLAG;
1841
1842 for (delay = 0; delay < 3000; delay++);
1843
1844 if (hperh->err_code == SPI_ERROR_NONE) {
1845 if (hperh->tx_cplt_cbk)
1846 hperh->tx_cplt_cbk(hperh);
1847 }
1848 else {
1849 if (hperh->err_cbk)
1850 hperh->err_cbk(hperh);
1851 }
1852
1853 return;
1854 }
SPI_ERROR_FLAG
Definition: ald_spi.h:103
OK
Definition: utils.h:55
DISABLE
Definition: type.h:48
spi_handle_s::tx_count
uint16_t tx_count
Definition: ald_spi.h:233
SPI_IF_TXOV
Definition: ald_spi.h:128
spi_handle_s::err_cbk
void(* err_cbk)(struct spi_handle_s *arg)
Definition: ald_spi.h:248
SPI_DIRECTION_2LINES
Definition: ald_spi.h:159
RESET
Definition: type.h:38
ald_spi_clear_flag_status
void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag)
Clear the specified SPI pending flags.
Definition: ald_spi.c:1484
UNUSED
#define UNUSED(x)
Definition: type.h:76
spi_handle_s
SPI handle structure definition.
Definition: ald_spi.h:228
spi_handle_s::init
spi_init_t init
Definition: ald_spi.h:230
ald_spi_dma_req_config
void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state)
Enables or disables the dma request.
Definition: ald_spi.c:1398
SPI_DMA_REQ_TX
Definition: ald_spi.h:169
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_get_status
flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status)
Check whether the specified SPI state flag is set or not.
Definition: ald_spi.c:1428
spi_handle_s::state
spi_state_t state
Definition: ald_spi.h:242
spi_wait_bsy_flag
static ald_status_t spi_wait_bsy_flag(spi_handle_t *hperh, flag_status_t status, uint32_t timeout)
Definition: ald_spi.c:1521
SPI_STATUS_RXE
Definition: ald_spi.h:190
spi_init_t::dir
spi_direction_t dir
Definition: ald_spi.h:213
SPI_STATE_READY
Definition: ald_spi.h:145
spi_handle_s::err_code
uint32_t err_code
Definition: ald_spi.h:243
SPI_ERROR_NONE
Definition: ald_spi.h:97
spi_handle_s::tx_cplt_cbk
void(* tx_cplt_cbk)(struct spi_handle_s *arg)
Definition: ald_spi.h:245

◆ spi_dma_send_recv_cplt()

static void spi_dma_send_recv_cplt ( void * arg )
static

DMA SPI transmit and receive process complete callback.

Parameters
arg Pointer to a SPI_handle_t structure.
Return values
None

Definition at line 1902 of file ald_spi.c.

1903 {
1904 uint32_t tmp;
1905 uint16_t delay;
1906 spi_handle_t *hperh = (spi_handle_t *)arg;
1907
1908 if (hperh->init.crc_calc) {
1909 if ((spi_wait_flag_irq(hperh, SPI_IF_RXTH, SET, 5000)) != OK)
1910 hperh->err_code |= SPI_ERROR_FLAG;
1911
1912 tmp = hperh->perh->DATA;
1913 UNUSED(tmp);
1914
1915 if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) {
1916 SET_BIT(hperh->err_code, SPI_ERROR_CRC);
1917 ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR);
1918 }
1919 }
1920
1921 if ((spi_wait_bsy_flag(hperh, RESET, 5000)) != OK)
1922 hperh->err_code |= SPI_ERROR_FLAG;
1923
1924 for (delay = 0; delay < 3000; delay++);
1925
1926 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE);
1927 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE);
1928 hperh->tx_count = 0;
1929 hperh->rx_count = 0;
1930 hperh->state = SPI_STATE_READY;
1931
1932 if (hperh->err_code == SPI_ERROR_NONE) {
1933 if (hperh->tx_rx_cplt_cbk)
1934 hperh->tx_rx_cplt_cbk(hperh);
1935 }
1936 else {
1937 if (hperh->err_cbk)
1938 hperh->err_cbk(hperh);
1939 }
1940
1941 return;
1942 }
SPI_ERROR_FLAG
Definition: ald_spi.h:103
OK
Definition: utils.h:55
SPI_ERROR_CRC
Definition: ald_spi.h:99
SET
Definition: type.h:39
SPI_DMA_REQ_RX
Definition: ald_spi.h:170
DISABLE
Definition: type.h:48
spi_handle_s::tx_count
uint16_t tx_count
Definition: ald_spi.h:233
spi_init_t::crc_calc
type_func_t crc_calc
Definition: ald_spi.h:220
spi_handle_s::tx_rx_cplt_cbk
void(* tx_rx_cplt_cbk)(struct spi_handle_s *arg)
Definition: ald_spi.h:247
ald_spi_get_flag_status
flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag)
Check whether the specified SPI flag is set or not.
Definition: ald_spi.c:1467
spi_handle_s::err_cbk
void(* err_cbk)(struct spi_handle_s *arg)
Definition: ald_spi.h:248
RESET
Definition: type.h:38
ald_spi_clear_flag_status
void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag)
Clear the specified SPI pending flags.
Definition: ald_spi.c:1484
UNUSED
#define UNUSED(x)
Definition: type.h:76
spi_wait_flag_irq
static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout)
This function handles SPI communication timeout in interrupt function.
Definition: ald_spi.c:1503
spi_handle_s
SPI handle structure definition.
Definition: ald_spi.h:228
spi_handle_s::init
spi_init_t init
Definition: ald_spi.h:230
ald_spi_dma_req_config
void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state)
Enables or disables the dma request.
Definition: ald_spi.c:1398
SPI_DMA_REQ_TX
Definition: ald_spi.h:169
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_handle_s::state
spi_state_t state
Definition: ald_spi.h:242
SPI_IF_CRCERR
Definition: ald_spi.h:135
spi_wait_bsy_flag
static ald_status_t spi_wait_bsy_flag(spi_handle_t *hperh, flag_status_t status, uint32_t timeout)
Definition: ald_spi.c:1521
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
SPI_STATE_READY
Definition: ald_spi.h:145
spi_handle_s::err_code
uint32_t err_code
Definition: ald_spi.h:243
SPI_IF_RXTH
Definition: ald_spi.h:134
spi_handle_s::rx_count
uint16_t rx_count
Definition: ald_spi.h:236
SPI_ERROR_NONE
Definition: ald_spi.h:97


ALD User Manual: SPI Public Types

Data Structures | Typedefs | Enumerations
SPI Public Types
EASTSOFT ES32F3xx ALD » SPI
Collaboration diagram for SPI Public Types:

Data Structures

struct | spi_init_t
SPI init structure definition. More...
struct | spi_handle_s
SPI handle structure definition. More...

Typedefs

typedef struct spi_handle_s spi_handle_t
SPI handle structure definition. More...

Enumerations

enum | spi_cpha_t { SPI_CPHA_FIRST = 0U, SPI_CPHA_SECOND = 1U }
clock phase More...
enum | spi_cpol_t { SPI_CPOL_LOW = 0U, SPI_CPOL_HIGH = 1U }
clock polarity More...
enum | spi_mode_t { SPI_MODE_SLAVER = 0U, SPI_MODE_MASTER = 1U }
master selection More...
enum spi_baud_t {
SPI_BAUD_2 = 0U, SPI_BAUD_4 = 1U, SPI_BAUD_8 = 2U, SPI_BAUD_16 = 3U,
SPI_BAUD_32 = 4U, SPI_BAUD_64 = 5U, SPI_BAUD_128 = 6U, SPI_BAUD_256 = 7U
}
baud rate control More...
enum | spi_firstbit_t { SPI_FIRSTBIT_MSB = 0U, SPI_FIRSTBIT_LSB = 1U }
frame format More...
enum | spi_datasize_t { SPI_DATA_SIZE_8 = 0U, SPI_DATA_SIZE_16 = 1U }
data frame format More...
enum spi_error_t {
SPI_ERROR_NONE = 0U, SPI_ERROR_MODF = 1U, SPI_ERROR_CRC = 2U, SPI_ERROR_FRE = 4U,
SPI_ERROR_RXOV = 8U, SPI_ERROR_TXOV = 0x10U, SPI_ERROR_FLAG = 0x20U
}
SPI error status. More...
enum spi_it_t {
SPI_IT_TXE = (1U << 0), SPI_IT_TXOV = (1U << 2), SPI_IT_TXUD = (1U << 3), SPI_IT_TXTH = (1U << 4),
SPI_IT_RXF = (1U << 9), SPI_IT_RXOV = (1U << 10), SPI_IT_RXUD = (1U << 11), SPI_IT_RXTH = (1U << 12),
SPI_IT_CRCERR = (1U << 16), SPI_IT_MODF = (1U << 17), SPI_IT_FRE = (1U << 18)
}
interrupt control More...
enum spi_flag_t {
SPI_IF_TXE = (1U << 0), SPI_IF_TXOV = (1U << 2), SPI_IF_TXUD = (1U << 3), SPI_IF_TXTH = (1U << 4),
SPI_IF_RXF = (1U << 9), SPI_IF_RXOV = (1U << 10), SPI_IF_RXUD = (1U << 11), SPI_IF_RXTH = (1U << 12),
SPI_IF_CRCERR = (1U << 16), SPI_IF_MODF = (1U << 17), SPI_IF_FRE = (1U << 18)
}
interrupt flag More...
enum spi_state_t {
SPI_STATE_RESET = 0x00U, SPI_STATE_READY = 0x01U, SPI_STATE_BUSY = 0x02U, SPI_STATE_BUSY_TX = 0x11U,
SPI_STATE_BUSY_RX = 0x21U, SPI_STATE_BUSY_TX_RX = 0x31U, SPI_STATE_TIMEOUT = 0x03U, SPI_STATE_ERROR = 0x04U
}
SPI state structures definition. More...
enum | spi_direction_t { SPI_DIRECTION_2LINES = 0U, SPI_DIRECTION_2LINES_RXONLY = 1U, SPI_DIRECTION_1LINE = 2U, SPI_DIRECTION_1LINE_RX = 3U }
SPI direction definition. More...
enum | spi_dma_req_t { SPI_DMA_REQ_TX = 0U, SPI_DMA_REQ_RX = 1U }
SPI dma request definition. More...
enum | spi_frame_t { SPI_FRAME_MOTOROLA = 0U, SPI_FRAME_TI = 1U }
SPI crc length definition. More...
enum spi_status_t {
SPI_STATUS_TXE = (1U << 0), SPI_STATUS_TXF = (1U << 1), SPI_STATUS_TXOV = (1U << 2), SPI_STATUS_TXUD = (1U << 3),
SPI_STATUS_TXTH = (1U << 4), SPI_STATUS_RXE = (1U << 8), SPI_STATUS_RXF = (1U << 9), SPI_STATUS_RXOV = (1U << 10),
SPI_STATUS_RXUD = (1U << 11), SPI_STATUS_RXTH = (1U << 12), SPI_STATUS_BUSY = (1U << 15)
}
SPI status definition. More...
enum | spi_sr_status_t { SPI_SR_TXE = 0U, SPI_SR_RXNE = 1U, SPI_SR_TXE_RXNE = 2U }
SPI TXE/RXNE status definition. More...

Detailed Description

Typedef Documentation

◆ spi_handle_t

typedef struct spi_handle_s spi_handle_t

SPI handle structure definition.

Enumeration Type Documentation

◆ spi_baud_t

enum spi_baud_t

baud rate control

Enumerator
SPI_BAUD_2 | fpclk/2
SPI_BAUD_4 | fpclk/4
SPI_BAUD_8 | fpclk/8
SPI_BAUD_16 | fpclk/16
SPI_BAUD_32 | fpclk/32
SPI_BAUD_64 | fpclk/64
SPI_BAUD_128 | fpclk/128
SPI_BAUD_256 | fpclk/256

Definition at line 66 of file ald_spi.h.

66 {
67 SPI_BAUD_2 = 0U,
68 SPI_BAUD_4 = 1U,
69 SPI_BAUD_8 = 2U,
70 SPI_BAUD_16 = 3U,
71 SPI_BAUD_32 = 4U,
72 SPI_BAUD_64 = 5U,
73 SPI_BAUD_128 = 6U,
74 SPI_BAUD_256 = 7U,
75 } spi_baud_t;
SPI_BAUD_256
Definition: ald_spi.h:74
SPI_BAUD_128
Definition: ald_spi.h:73
spi_baud_t
spi_baud_t
baud rate control
Definition: ald_spi.h:66
SPI_BAUD_16
Definition: ald_spi.h:70
SPI_BAUD_64
Definition: ald_spi.h:72
SPI_BAUD_2
Definition: ald_spi.h:67
SPI_BAUD_8
Definition: ald_spi.h:69
SPI_BAUD_4
Definition: ald_spi.h:68
SPI_BAUD_32
Definition: ald_spi.h:71

◆ spi_cpha_t

enum spi_cpha_t

clock phase

Enumerator
SPI_CPHA_FIRST | Transiting data in the first edge
SPI_CPHA_SECOND | Transiting data in the seconde edge

Definition at line 42 of file ald_spi.h.

42 {
43 SPI_CPHA_FIRST = 0U,
44 SPI_CPHA_SECOND = 1U,
45 } spi_cpha_t;
SPI_CPHA_FIRST
Definition: ald_spi.h:43
SPI_CPHA_SECOND
Definition: ald_spi.h:44
spi_cpha_t
spi_cpha_t
clock phase
Definition: ald_spi.h:42

◆ spi_cpol_t

enum spi_cpol_t

clock polarity

Enumerator
SPI_CPOL_LOW | Polarity hold low when spi-bus is idle
SPI_CPOL_HIGH | Polarity hold high when spi-bus is idle

Definition at line 50 of file ald_spi.h.

50 {
51 SPI_CPOL_LOW = 0U,
52 SPI_CPOL_HIGH = 1U,
53 } spi_cpol_t;
SPI_CPOL_HIGH
Definition: ald_spi.h:52
SPI_CPOL_LOW
Definition: ald_spi.h:51
spi_cpol_t
spi_cpol_t
clock polarity
Definition: ald_spi.h:50

◆ spi_datasize_t

enum spi_datasize_t

data frame format

Enumerator
SPI_DATA_SIZE_8 | 8-bit data frame format is selected for transmission/reception
SPI_DATA_SIZE_16 | 16-bit data frame format is selected for transmission/reception

Definition at line 88 of file ald_spi.h.

88 {
89 SPI_DATA_SIZE_8 = 0U,
90 SPI_DATA_SIZE_16 = 1U,
91 } spi_datasize_t;
spi_datasize_t
spi_datasize_t
data frame format
Definition: ald_spi.h:88
SPI_DATA_SIZE_16
Definition: ald_spi.h:90
SPI_DATA_SIZE_8
Definition: ald_spi.h:89

◆ spi_direction_t

enum spi_direction_t

SPI direction definition.

Enumerator
SPI_DIRECTION_2LINES | 2 lines
SPI_DIRECTION_2LINES_RXONLY | 2 lines only rx
SPI_DIRECTION_1LINE | 1 line
SPI_DIRECTION_1LINE_RX | 1 line only rx

Definition at line 158 of file ald_spi.h.

158 {
159 SPI_DIRECTION_2LINES = 0U,
160 SPI_DIRECTION_2LINES_RXONLY = 1U,
161 SPI_DIRECTION_1LINE = 2U,
162 SPI_DIRECTION_1LINE_RX = 3U,
163 } spi_direction_t;
SPI_DIRECTION_2LINES_RXONLY
Definition: ald_spi.h:160
SPI_DIRECTION_2LINES
Definition: ald_spi.h:159
SPI_DIRECTION_1LINE_RX
Definition: ald_spi.h:162
spi_direction_t
spi_direction_t
SPI direction definition.
Definition: ald_spi.h:158
SPI_DIRECTION_1LINE
Definition: ald_spi.h:161

◆ spi_dma_req_t

enum spi_dma_req_t

SPI dma request definition.

Enumerator
SPI_DMA_REQ_TX | TX dma request
SPI_DMA_REQ_RX | RX dma request

Definition at line 168 of file ald_spi.h.

168 {
169 SPI_DMA_REQ_TX = 0U,
170 SPI_DMA_REQ_RX = 1U,
171 } spi_dma_req_t;
SPI_DMA_REQ_RX
Definition: ald_spi.h:170
SPI_DMA_REQ_TX
Definition: ald_spi.h:169
spi_dma_req_t
spi_dma_req_t
SPI dma request definition.
Definition: ald_spi.h:168

◆ spi_error_t

enum spi_error_t

SPI error status.

Enumerator
SPI_ERROR_NONE | none
SPI_ERROR_MODF | mode fault
SPI_ERROR_CRC | crc error
SPI_ERROR_FRE | frame error
SPI_ERROR_RXOV | receive over error
SPI_ERROR_TXOV | dma error
SPI_ERROR_FLAG | interrupt flag error

Definition at line 96 of file ald_spi.h.

96 {
97 SPI_ERROR_NONE = 0U,
98 SPI_ERROR_MODF = 1U,
99 SPI_ERROR_CRC = 2U,
100 SPI_ERROR_FRE = 4U,
101 SPI_ERROR_RXOV = 8U,
102 SPI_ERROR_TXOV = 0x10U,
103 SPI_ERROR_FLAG = 0x20U,
104 } spi_error_t;
SPI_ERROR_FLAG
Definition: ald_spi.h:103
SPI_ERROR_CRC
Definition: ald_spi.h:99
SPI_ERROR_RXOV
Definition: ald_spi.h:101
SPI_ERROR_MODF
Definition: ald_spi.h:98
SPI_ERROR_TXOV
Definition: ald_spi.h:102
spi_error_t
spi_error_t
SPI error status.
Definition: ald_spi.h:96
SPI_ERROR_NONE
Definition: ald_spi.h:97
SPI_ERROR_FRE
Definition: ald_spi.h:100

◆ spi_firstbit_t

enum spi_firstbit_t

frame format

Enumerator
SPI_FIRSTBIT_MSB | MSB transmitted first
SPI_FIRSTBIT_LSB | LSB transmitted first

Definition at line 80 of file ald_spi.h.

80 {
81 SPI_FIRSTBIT_MSB = 0U,
82 SPI_FIRSTBIT_LSB = 1U,
83 } spi_firstbit_t;
spi_firstbit_t
spi_firstbit_t
frame format
Definition: ald_spi.h:80
SPI_FIRSTBIT_MSB
Definition: ald_spi.h:81
SPI_FIRSTBIT_LSB
Definition: ald_spi.h:82

◆ spi_flag_t

enum spi_flag_t

interrupt flag

Enumerator
SPI_IF_TXE | Transmit fifo empty interrupt flag
SPI_IF_TXOV | Transmit fifo overflow interrupt flag
SPI_IF_TXUD | Transmit fifo underflow interrupt flag
SPI_IF_TXTH | Transmit fifo under threshold interrupt flag
SPI_IF_RXF | Receive fifo full interrupt flag
SPI_IF_RXOV | Receive fifo overflow interrupt flag
SPI_IF_RXUD | Receive fifo underflow interrupt flag
SPI_IF_RXTH | Receive fifo over threshold interrupt flag
SPI_IF_CRCERR | Crc error interrupt flag
SPI_IF_MODF | Mode error interrupt flag
SPI_IF_FRE | Frame error interrupt flag

Definition at line 126 of file ald_spi.h.

126 {
127 SPI_IF_TXE = (1U << 0),
128 SPI_IF_TXOV = (1U << 2),
129 SPI_IF_TXUD = (1U << 3),
130 SPI_IF_TXTH = (1U << 4),
131 SPI_IF_RXF = (1U << 9),
132 SPI_IF_RXOV = (1U << 10),
133 SPI_IF_RXUD = (1U << 11),
134 SPI_IF_RXTH = (1U << 12),
135 SPI_IF_CRCERR = (1U << 16),
136 SPI_IF_MODF = (1U << 17),
137 SPI_IF_FRE = (1U << 18),
138 } spi_flag_t;
SPI_IF_RXF
Definition: ald_spi.h:131
SPI_IF_TXOV
Definition: ald_spi.h:128
spi_flag_t
spi_flag_t
interrupt flag
Definition: ald_spi.h:126
SPI_IF_RXOV
Definition: ald_spi.h:132
SPI_IF_CRCERR
Definition: ald_spi.h:135
SPI_IF_RXUD
Definition: ald_spi.h:133
SPI_IF_TXE
Definition: ald_spi.h:127
SPI_IF_TXUD
Definition: ald_spi.h:129
SPI_IF_TXTH
Definition: ald_spi.h:130
SPI_IF_RXTH
Definition: ald_spi.h:134
SPI_IF_MODF
Definition: ald_spi.h:136
SPI_IF_FRE
Definition: ald_spi.h:137

◆ spi_frame_t

enum spi_frame_t

SPI crc length definition.

Enumerator
SPI_FRAME_MOTOROLA | SPI motorola mode
SPI_FRAME_TI | SPI TI mode

Definition at line 176 of file ald_spi.h.

176 {
177 SPI_FRAME_MOTOROLA = 0U,
178 SPI_FRAME_TI = 1U,
179 } spi_frame_t;
SPI_FRAME_TI
Definition: ald_spi.h:178
SPI_FRAME_MOTOROLA
Definition: ald_spi.h:177
spi_frame_t
spi_frame_t
SPI crc length definition.
Definition: ald_spi.h:176

◆ spi_it_t

enum spi_it_t

interrupt control

Enumerator
SPI_IT_TXE | Transmit fifo empty interrupt
SPI_IT_TXOV | Transmit fifo overflow interrupt
SPI_IT_TXUD | Transmit fifo underflow interrupt
SPI_IT_TXTH | Transmit fifo under threshold interrupt
SPI_IT_RXF | Receive fifo full interrupt
SPI_IT_RXOV | Receive fifo overflow interrupt
SPI_IT_RXUD | Receive fifo underflow interrupt
SPI_IT_RXTH | Receive fifo over threshold interrupt
SPI_IT_CRCERR | Crc error interrupt
SPI_IT_MODF | Mode error interrupt
SPI_IT_FRE | Frame error interrupt

Definition at line 109 of file ald_spi.h.

109 {
110 SPI_IT_TXE = (1U << 0),
111 SPI_IT_TXOV = (1U << 2),
112 SPI_IT_TXUD = (1U << 3),
113 SPI_IT_TXTH = (1U << 4),
114 SPI_IT_RXF = (1U << 9),
115 SPI_IT_RXOV = (1U << 10),
116 SPI_IT_RXUD = (1U << 11),
117 SPI_IT_RXTH = (1U << 12),
118 SPI_IT_CRCERR = (1U << 16),
119 SPI_IT_MODF = (1U << 17),
120 SPI_IT_FRE = (1U << 18),
121 } spi_it_t;
SPI_IT_TXTH
Definition: ald_spi.h:113
SPI_IT_CRCERR
Definition: ald_spi.h:118
SPI_IT_TXE
Definition: ald_spi.h:110
spi_it_t
spi_it_t
interrupt control
Definition: ald_spi.h:109
SPI_IT_RXUD
Definition: ald_spi.h:116
SPI_IT_FRE
Definition: ald_spi.h:120
SPI_IT_RXF
Definition: ald_spi.h:114
SPI_IT_TXOV
Definition: ald_spi.h:111
SPI_IT_MODF
Definition: ald_spi.h:119
SPI_IT_TXUD
Definition: ald_spi.h:112
SPI_IT_RXTH
Definition: ald_spi.h:117
SPI_IT_RXOV
Definition: ald_spi.h:115

◆ spi_mode_t

enum spi_mode_t

master selection

Enumerator
SPI_MODE_SLAVER | Slave mode
SPI_MODE_MASTER | Master mode

Definition at line 58 of file ald_spi.h.

58 {
59 SPI_MODE_SLAVER = 0U,
60 SPI_MODE_MASTER = 1U,
61 } spi_mode_t;
SPI_MODE_MASTER
Definition: ald_spi.h:60
SPI_MODE_SLAVER
Definition: ald_spi.h:59
spi_mode_t
spi_mode_t
master selection
Definition: ald_spi.h:58

◆ spi_sr_status_t

enum spi_sr_status_t

SPI TXE/RXNE status definition.

Enumerator
SPI_SR_TXE | SR.TXE set
SPI_SR_RXNE | SR.RXTH set
SPI_SR_TXE_RXNE | SR.TXE and SR.RXNE set

Definition at line 201 of file ald_spi.h.

201 {
202 SPI_SR_TXE = 0U,
203 SPI_SR_RXNE = 1U,
204 SPI_SR_TXE_RXNE = 2U,
205 } spi_sr_status_t;
SPI_SR_TXE_RXNE
Definition: ald_spi.h:204
SPI_SR_RXNE
Definition: ald_spi.h:203
spi_sr_status_t
spi_sr_status_t
SPI TXE/RXNE status definition.
Definition: ald_spi.h:201
SPI_SR_TXE
Definition: ald_spi.h:202

◆ spi_state_t

enum spi_state_t

SPI state structures definition.

Enumerator
SPI_STATE_RESET | Peripheral is not initialized
SPI_STATE_READY | Peripheral Initialized and ready for use
SPI_STATE_BUSY | an internal process is ongoing
SPI_STATE_BUSY_TX | transmit is ongoing
SPI_STATE_BUSY_RX | receive is ongoing
SPI_STATE_BUSY_TX_RX | transmit and receive are ongoing
SPI_STATE_TIMEOUT | Timeout state
SPI_STATE_ERROR | Error

Definition at line 143 of file ald_spi.h.

143 {
144 SPI_STATE_RESET = 0x00U,
145 SPI_STATE_READY = 0x01U,
146 SPI_STATE_BUSY = 0x02U,
147 SPI_STATE_BUSY_TX = 0x11U,
148 SPI_STATE_BUSY_RX = 0x21U,
149 SPI_STATE_BUSY_TX_RX = 0x31U,
150 SPI_STATE_TIMEOUT = 0x03U,
151 SPI_STATE_ERROR = 0x04U,
152 } spi_state_t;
SPI_STATE_BUSY
Definition: ald_spi.h:146
SPI_STATE_TIMEOUT
Definition: ald_spi.h:150
spi_state_t
spi_state_t
SPI state structures definition.
Definition: ald_spi.h:143
SPI_STATE_BUSY_TX_RX
Definition: ald_spi.h:149
SPI_STATE_RESET
Definition: ald_spi.h:144
SPI_STATE_BUSY_RX
Definition: ald_spi.h:148
SPI_STATE_BUSY_TX
Definition: ald_spi.h:147
SPI_STATE_ERROR
Definition: ald_spi.h:151
SPI_STATE_READY
Definition: ald_spi.h:145

◆ spi_status_t

enum spi_status_t

SPI status definition.

Enumerator
SPI_STATUS_TXE | Transmit fifo empty status
SPI_STATUS_TXF | Transmit fifo full status
SPI_STATUS_TXOV | Transmit fifo overflow status
SPI_STATUS_TXUD | Transmit fifo underflow status
SPI_STATUS_TXTH | Transmit fifo under threshold status
SPI_STATUS_RXE | Receive fifo empty status
SPI_STATUS_RXF | Receive fifo full status
SPI_STATUS_RXOV | Receive fifo overflow status
SPI_STATUS_RXUD | Receive fifo underflow status
SPI_STATUS_RXTH | Receive fifo under threshold status
SPI_STATUS_BUSY | BUSY status

Definition at line 184 of file ald_spi.h.

184 {
185 SPI_STATUS_TXE = (1U << 0),
186 SPI_STATUS_TXF = (1U << 1),
187 SPI_STATUS_TXOV = (1U << 2),
188 SPI_STATUS_TXUD = (1U << 3),
189 SPI_STATUS_TXTH = (1U << 4),
190 SPI_STATUS_RXE = (1U << 8),
191 SPI_STATUS_RXF = (1U << 9),
192 SPI_STATUS_RXOV = (1U << 10),
193 SPI_STATUS_RXUD = (1U << 11),
194 SPI_STATUS_RXTH = (1U << 12),
195 SPI_STATUS_BUSY = (1U << 15),
196 } spi_status_t;
SPI_STATUS_TXE
Definition: ald_spi.h:185
SPI_STATUS_TXOV
Definition: ald_spi.h:187
SPI_STATUS_RXF
Definition: ald_spi.h:191
SPI_STATUS_TXUD
Definition: ald_spi.h:188
SPI_STATUS_RXOV
Definition: ald_spi.h:192
SPI_STATUS_RXTH
Definition: ald_spi.h:194
spi_status_t
spi_status_t
SPI status definition.
Definition: ald_spi.h:184
SPI_STATUS_RXUD
Definition: ald_spi.h:193
SPI_STATUS_TXF
Definition: ald_spi.h:186
SPI_STATUS_RXE
Definition: ald_spi.h:190
SPI_STATUS_BUSY
Definition: ald_spi.h:195
SPI_STATUS_TXTH
Definition: ald_spi.h:189


ALD User Manual: spi_init_t Struct Reference

Data Fields
spi_init_t Struct Reference
EASTSOFT ES32F3xx ALD » SPI » SPI Public Types

SPI init structure definition. More...

#include <ald_spi.h>

Data Fields

spi_mode_t mode
spi_direction_t dir
spi_datasize_t data_size
spi_baud_t baud
spi_cpha_t phase
spi_cpol_t polarity
spi_firstbit_t first_bit
type_func_t ss_en
type_func_t crc_calc
spi_frame_t frame
uint16_t crc_poly

Detailed Description

SPI init structure definition.

Definition at line 211 of file ald_spi.h.

Field Documentation

◆ baud

spi_baud_t baud

SPI baudrate prescaler

Definition at line 215 of file ald_spi.h.

◆ crc_calc

type_func_t crc_calc

SPI crc calculation

Definition at line 220 of file ald_spi.h.

◆ crc_poly

uint16_t crc_poly

SPI crc polynomial

Definition at line 222 of file ald_spi.h.

◆ data_size

spi_datasize_t data_size

SPI data size

Definition at line 214 of file ald_spi.h.

◆ dir

spi_direction_t dir

SPI direction

Definition at line 213 of file ald_spi.h.

◆ first_bit

spi_firstbit_t first_bit

SPI first bit

Definition at line 218 of file ald_spi.h.

◆ frame

spi_frame_t frame

SPI frame format

Definition at line 221 of file ald_spi.h.

◆ mode

spi_mode_t mode

SPI mode

Definition at line 212 of file ald_spi.h.

◆ phase

spi_cpha_t phase

SPI clock phase

Definition at line 216 of file ald_spi.h.

◆ polarity

spi_cpol_t polarity

SPI clock polarity

Definition at line 217 of file ald_spi.h.

◆ ss_en

type_func_t ss_en

SPI ssm enable or disable

Definition at line 219 of file ald_spi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_spi.h


ALD User Manual: spi_handle_s Struct Reference

Data Fields
spi_handle_s Struct Reference
EASTSOFT ES32F3xx ALD » SPI » SPI Public Types

SPI handle structure definition. More...

#include <ald_spi.h>

Collaboration diagram for spi_handle_s:
[legend]

Data Fields

SPI_I2S_TypeDef * | perh
spi_init_t init
uint8_t * | tx_buf
uint16_t | tx_size
uint16_t | tx_count
uint8_t * | rx_buf
uint16_t | rx_size
uint16_t | rx_count
dma_handle_t hdmatx
dma_handle_t hdmarx
lock_state_t lock
spi_state_t state
uint32_t | err_code
void(* | tx_cplt_cbk )(struct spi_handle_s *arg)
void(* | rx_cplt_cbk )(struct spi_handle_s *arg)
void(* | tx_rx_cplt_cbk )(struct spi_handle_s *arg)
void(* | err_cbk )(struct spi_handle_s *arg)

Detailed Description

SPI handle structure definition.

Definition at line 228 of file ald_spi.h.

Field Documentation

◆ err_cbk

void(* err_cbk) (struct spi_handle_s *arg)

error callback

Definition at line 248 of file ald_spi.h.

◆ err_code

uint32_t err_code

SPI error code

Definition at line 243 of file ald_spi.h.

◆ hdmarx

dma_handle_t hdmarx

SPI Rx DMA handle parameters

Definition at line 239 of file ald_spi.h.

◆ hdmatx

dma_handle_t hdmatx

SPI Tx DMA handle parameters

Definition at line 238 of file ald_spi.h.

◆ init

spi_init_t init

SPI communication parameters

Definition at line 230 of file ald_spi.h.

◆ lock

lock_state_t lock

Locking object

Definition at line 241 of file ald_spi.h.

◆ perh

SPI_I2S_TypeDef* perh

SPI registers base address

Definition at line 229 of file ald_spi.h.

◆ rx_buf

uint8_t* rx_buf

Pointer to SPI Rx transfer buffer

Definition at line 234 of file ald_spi.h.

◆ rx_count

uint16_t rx_count

SPI Rx Transfer Counter

Definition at line 236 of file ald_spi.h.

◆ rx_cplt_cbk

void(* rx_cplt_cbk) (struct spi_handle_s *arg)

Rx completed callback

Definition at line 246 of file ald_spi.h.

◆ rx_size

uint16_t rx_size

SPI Rx Transfer size

Definition at line 235 of file ald_spi.h.

◆ state

spi_state_t state

SPI communication state

Definition at line 242 of file ald_spi.h.

◆ tx_buf

uint8_t* tx_buf

Pointer to SPI Tx transfer buffer

Definition at line 231 of file ald_spi.h.

◆ tx_count

uint16_t tx_count

SPI Tx transfer counter

Definition at line 233 of file ald_spi.h.

◆ tx_cplt_cbk

void(* tx_cplt_cbk) (struct spi_handle_s *arg)

Tx completed callback

Definition at line 245 of file ald_spi.h.

◆ tx_rx_cplt_cbk

void(* tx_rx_cplt_cbk) (struct spi_handle_s *arg)

Tx & Rx completed callback

Definition at line 247 of file ald_spi.h.

◆ tx_size

uint16_t tx_size

SPI Tx transfer size

Definition at line 232 of file ald_spi.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_spi.h


ALD User Manual: SPI Public Macros

Macros
SPI Public Macros
EASTSOFT ES32F3xx ALD » SPI
Collaboration diagram for SPI Public Macros:

Macros

#define | SPI_RESET_HANDLE_STATE(x) ((x)->state = SPI_STATE_RESET)
#define | SPI_ENABLE(x) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS))
#define | SPI_DISABLE(x) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS))
#define | SPI_CRC_RESET(x)
#define | SPI_CRCNEXT_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
#define | SPI_CRCNEXT_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
#define | SPI_RXONLY_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))
#define | SPI_RXONLY_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))
#define | SPI_1LINE_TX(x) (SET_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK))
#define | SPI_1LINE_RX(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK))
#define | SPI_SSI_HIGH(x) (SET_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK))
#define | SPI_SSI_LOW(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK))
#define | SPI_SSOE_ENABLE(x) (SET_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK))
#define | SPI_SSOE_DISABLE(x) (CLEAR_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK))

Detailed Description

Macro Definition Documentation

◆ SPI_1LINE_RX

#define SPI_1LINE_RX ( x ) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK))

Definition at line 270 of file ald_spi.h.

◆ SPI_1LINE_TX

#define SPI_1LINE_TX ( x ) (SET_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK))

Definition at line 269 of file ald_spi.h.

◆ SPI_CRC_RESET

#define SPI_CRC_RESET ( x )
Value:
do { \
CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \
SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \
} while (0)

Definition at line 260 of file ald_spi.h.

◆ SPI_CRCNEXT_DISABLE

#define SPI_CRCNEXT_DISABLE ( x ) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))

Definition at line 266 of file ald_spi.h.

◆ SPI_CRCNEXT_ENABLE

#define SPI_CRCNEXT_ENABLE ( x ) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))

Definition at line 265 of file ald_spi.h.

◆ SPI_DISABLE

#define SPI_DISABLE ( x ) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS))

Definition at line 259 of file ald_spi.h.

◆ SPI_ENABLE

#define SPI_ENABLE ( x ) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS))

Definition at line 258 of file ald_spi.h.

◆ SPI_RESET_HANDLE_STATE

#define SPI_RESET_HANDLE_STATE ( x ) ((x)->state = SPI_STATE_RESET)

Definition at line 257 of file ald_spi.h.

◆ SPI_RXONLY_DISABLE

#define SPI_RXONLY_DISABLE ( x ) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))

Definition at line 268 of file ald_spi.h.

◆ SPI_RXONLY_ENABLE

#define SPI_RXONLY_ENABLE ( x ) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))

Definition at line 267 of file ald_spi.h.

◆ SPI_SSI_HIGH

#define SPI_SSI_HIGH ( x ) (SET_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK))

Definition at line 271 of file ald_spi.h.

◆ SPI_SSI_LOW

#define SPI_SSI_LOW ( x ) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK))

Definition at line 272 of file ald_spi.h.

◆ SPI_SSOE_DISABLE

#define SPI_SSOE_DISABLE ( x ) (CLEAR_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK))

Definition at line 274 of file ald_spi.h.

◆ SPI_SSOE_ENABLE

#define SPI_SSOE_ENABLE ( x ) (SET_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK))

Definition at line 273 of file ald_spi.h.


ALD User Manual: SPI Private Macros

Macros
SPI Private Macros
EASTSOFT ES32F3xx ALD » SPI
Collaboration diagram for SPI Private Macros:

Macros

#define | IS_SPI(x)
#define | IS_SPI_CPHA(x)
#define | IS_SPI_CPOL(x)
#define | IS_SPI_MODE(x)
#define | IS_SPI_FIRBIT(x)
#define | IS_SPI_BAUD(x)
#define | IS_SPI_DATASIZE(x)
#define | IS_SPI_BIDOE(x)
#define | IS_SPI_BIDMODE(x)
#define | IS_SPI_DIRECTION(x)
#define | IS_SPI_DMA_REQ(x)
#define | IS_SPI_STATUS(x)
#define | IS_SPI_IT(x)
#define | IS_SPI_IF(x)
#define | IS_SPI_FRAME(x)

Detailed Description

Macro Definition Documentation

◆ IS_SPI

#define IS_SPI ( x )
Value:
(((x) == SPI0) || \
((x) == SPI1) || \
((x) == SPI2))

Definition at line 282 of file ald_spi.h.

◆ IS_SPI_BAUD

#define IS_SPI_BAUD ( x )
Value:
(((x) == SPI_BAUD_2) || \
((x) == SPI_BAUD_4) || \
((x) == SPI_BAUD_8) || \
((x) == SPI_BAUD_16) || \
((x) == SPI_BAUD_32) || \
((x) == SPI_BAUD_64) || \
((x) == SPI_BAUD_128) || \
((x) == SPI_BAUD_256))
SPI_BAUD_256
Definition: ald_spi.h:74
SPI_BAUD_128
Definition: ald_spi.h:73
SPI_BAUD_16
Definition: ald_spi.h:70
SPI_BAUD_64
Definition: ald_spi.h:72
SPI_BAUD_2
Definition: ald_spi.h:67
SPI_BAUD_8
Definition: ald_spi.h:69
SPI_BAUD_4
Definition: ald_spi.h:68
SPI_BAUD_32
Definition: ald_spi.h:71

Definition at line 293 of file ald_spi.h.

◆ IS_SPI_BIDMODE

#define IS_SPI_BIDMODE ( x )
Value:
(((x) == SPI_BIDMODE_DUAL) || \
((x) == SPI_BIDMODE_SOLE))

Definition at line 305 of file ald_spi.h.

◆ IS_SPI_BIDOE

#define IS_SPI_BIDOE ( x )
Value:
(((x) == SPI_BID_RX) || \
((x) == SPI_BID_TX))

Definition at line 303 of file ald_spi.h.

◆ IS_SPI_CPHA

#define IS_SPI_CPHA ( x )
Value:
(((x) == SPI_CPHA_FIRST) || \
((x) == SPI_CPHA_SECOND))
SPI_CPHA_FIRST
Definition: ald_spi.h:43
SPI_CPHA_SECOND
Definition: ald_spi.h:44

Definition at line 285 of file ald_spi.h.

◆ IS_SPI_CPOL

#define IS_SPI_CPOL ( x )
Value:
(((x) == SPI_CPOL_LOW) || \
((x) == SPI_CPOL_HIGH))
SPI_CPOL_HIGH
Definition: ald_spi.h:52
SPI_CPOL_LOW
Definition: ald_spi.h:51

Definition at line 287 of file ald_spi.h.

◆ IS_SPI_DATASIZE

#define IS_SPI_DATASIZE ( x )
Value:
(((x) == SPI_DATA_SIZE_8) || \
((x) == SPI_DATA_SIZE_16))
SPI_DATA_SIZE_16
Definition: ald_spi.h:90
SPI_DATA_SIZE_8
Definition: ald_spi.h:89

Definition at line 301 of file ald_spi.h.

◆ IS_SPI_DIRECTION

#define IS_SPI_DIRECTION ( x )
Value:
(((x) == SPI_DIRECTION_2LINES) || \
((x) == SPI_DIRECTION_2LINES_RXONLY) || \
((x) == SPI_DIRECTION_1LINE) || \
((x) == SPI_DIRECTION_1LINE_RX))
SPI_DIRECTION_2LINES_RXONLY
Definition: ald_spi.h:160
SPI_DIRECTION_2LINES
Definition: ald_spi.h:159
SPI_DIRECTION_1LINE_RX
Definition: ald_spi.h:162
SPI_DIRECTION_1LINE
Definition: ald_spi.h:161

Definition at line 307 of file ald_spi.h.

◆ IS_SPI_DMA_REQ

#define IS_SPI_DMA_REQ ( x )
Value:
(((x) == SPI_DMA_REQ_TX) || \
((x) == SPI_DMA_REQ_RX))
SPI_DMA_REQ_RX
Definition: ald_spi.h:170
SPI_DMA_REQ_TX
Definition: ald_spi.h:169

Definition at line 311 of file ald_spi.h.

◆ IS_SPI_FIRBIT

#define IS_SPI_FIRBIT ( x )
Value:
(((x) == SPI_FIRSTBIT_MSB) || \
((x) == SPI_FIRSTBIT_LSB))
SPI_FIRSTBIT_MSB
Definition: ald_spi.h:81
SPI_FIRSTBIT_LSB
Definition: ald_spi.h:82

Definition at line 291 of file ald_spi.h.

◆ IS_SPI_FRAME

#define IS_SPI_FRAME ( x )
Value:
(((x) == SPI_FRAME_MOTOROLA) || \
((x) == SPI_FRAME_TI) )
SPI_FRAME_TI
Definition: ald_spi.h:178
SPI_FRAME_MOTOROLA
Definition: ald_spi.h:177

Definition at line 346 of file ald_spi.h.

◆ IS_SPI_IF

#define IS_SPI_IF ( x )
Value:
(((x) == SPI_IF_TXE) || \
((x) == SPI_IF_TXOV) || \
((x) == SPI_IF_TXUD) || \
((x) == SPI_IF_TXTH) || \
((x) == SPI_IF_RXF) || \
((x) == SPI_IF_RXOV) || \
((x) == SPI_IF_RXUD) || \
((x) == SPI_IF_RXTH) || \
((x) == SPI_IF_CRCERR) || \
((x) == SPI_IF_MODF) || \
((x) == SPI_IF_FRE))
SPI_IF_RXF
Definition: ald_spi.h:131
SPI_IF_TXOV
Definition: ald_spi.h:128
SPI_IF_RXOV
Definition: ald_spi.h:132
SPI_IF_CRCERR
Definition: ald_spi.h:135
SPI_IF_RXUD
Definition: ald_spi.h:133
SPI_IF_TXE
Definition: ald_spi.h:127
SPI_IF_TXUD
Definition: ald_spi.h:129
SPI_IF_TXTH
Definition: ald_spi.h:130
SPI_IF_RXTH
Definition: ald_spi.h:134
SPI_IF_MODF
Definition: ald_spi.h:136
SPI_IF_FRE
Definition: ald_spi.h:137

Definition at line 335 of file ald_spi.h.

◆ IS_SPI_IT

#define IS_SPI_IT ( x )
Value:
(((x) == SPI_IT_TXE) || \
((x) == SPI_IT_TXOV) || \
((x) == SPI_IT_TXUD) || \
((x) == SPI_IT_TXTH) || \
((x) == SPI_IT_RXF) || \
((x) == SPI_IT_RXOV) || \
((x) == SPI_IT_RXUD) || \
((x) == SPI_IT_RXTH) || \
((x) == SPI_IT_CRCERR) || \
((x) == SPI_IT_MODF) || \
((x) == SPI_IT_FRE))
SPI_IT_TXTH
Definition: ald_spi.h:113
SPI_IT_CRCERR
Definition: ald_spi.h:118
SPI_IT_TXE
Definition: ald_spi.h:110
SPI_IT_RXUD
Definition: ald_spi.h:116
SPI_IT_FRE
Definition: ald_spi.h:120
SPI_IT_RXF
Definition: ald_spi.h:114
SPI_IT_TXOV
Definition: ald_spi.h:111
SPI_IT_MODF
Definition: ald_spi.h:119
SPI_IT_TXUD
Definition: ald_spi.h:112
SPI_IT_RXTH
Definition: ald_spi.h:117
SPI_IT_RXOV
Definition: ald_spi.h:115

Definition at line 324 of file ald_spi.h.

◆ IS_SPI_MODE

#define IS_SPI_MODE ( x )
Value:
(((x) == SPI_MODE_SLAVER) || \
((x) == SPI_MODE_MASTER))
SPI_MODE_MASTER
Definition: ald_spi.h:60
SPI_MODE_SLAVER
Definition: ald_spi.h:59

Definition at line 289 of file ald_spi.h.

◆ IS_SPI_STATUS

#define IS_SPI_STATUS ( x )
Value:
(((x) == SPI_STATUS_TXE) || \
((x) == SPI_STATUS_TXF) || \
((x) == SPI_STATUS_TXOV) || \
((x) == SPI_STATUS_TXUD) || \
((x) == SPI_STATUS_TXTH) || \
((x) == SPI_STATUS_RXE) || \
((x) == SPI_STATUS_RXF) || \
((x) == SPI_STATUS_RXOV) || \
((x) == SPI_STATUS_RXUD) || \
((x) == SPI_STATUS_RXTH) || \
((x) == SPI_STATUS_BUSY))
SPI_STATUS_TXE
Definition: ald_spi.h:185
SPI_STATUS_TXOV
Definition: ald_spi.h:187
SPI_STATUS_RXF
Definition: ald_spi.h:191
SPI_STATUS_TXUD
Definition: ald_spi.h:188
SPI_STATUS_RXOV
Definition: ald_spi.h:192
SPI_STATUS_RXTH
Definition: ald_spi.h:194
SPI_STATUS_RXUD
Definition: ald_spi.h:193
SPI_STATUS_TXF
Definition: ald_spi.h:186
SPI_STATUS_RXE
Definition: ald_spi.h:190
SPI_STATUS_BUSY
Definition: ald_spi.h:195
SPI_STATUS_TXTH
Definition: ald_spi.h:189

Definition at line 313 of file ald_spi.h.


ALD User Manual: SRAM

Modules
SRAM
EASTSOFT ES32F3xx ALD

SRAM module driver. More...

Collaboration diagram for SRAM:

Modules

SRAM Public Functions
SRAM Public Types

Detailed Description

SRAM module driver.


ALD User Manual: SRAM Public Functions

Modules
SRAM Public Functions
EASTSOFT ES32F3xx ALD » SRAM
Collaboration diagram for SRAM Public Functions:

Modules

Initialization functions
Initialization functions.
I/O operation functions
I/O operation functions.
Control functions
Control functions.
State functions
State functions.

Detailed Description


ALD User Manual: Initialization functions

Functions
Initialization functions
EASTSOFT ES32F3xx ALD » SRAM » SRAM Public Functions

Initialization functions. More...

Collaboration diagram for Initialization functions:

Functions

ald_status_t | ald_sram_init (sram_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing)
Performs the SRAM device initialization sequence. More...
ald_status_t | ald_sram_deinit (sram_handle_t *hperh)
Performs the SRAM device De-initialization sequence. More...

Detailed Description

Initialization functions.

Function Documentation

◆ ald_sram_deinit()

ald_status_t ald_sram_deinit ( sram_handle_t * hperh )

Performs the SRAM device De-initialization sequence.

Parameters
hperh pointer to a sram_handle_t structure
Return values
ald status

Definition at line 68 of file ald_sram.c.

69 {
70 ald_ebi_nor_sram_deinit(hperh->instance, hperh->ext, hperh->init.bank);
71 hperh->state = ALD_SRAM_STATE_RESET;
72 __UNLOCK(hperh);
73
74 return OK;
75 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
sram_handle_t::instance
EBI_NOR_SRAM_TypeDef * instance
Definition: ald_sram.h:54
ald_ebi_nor_sram_deinit
ald_status_t ald_ebi_nor_sram_deinit(EBI_NOR_SRAM_TypeDef *dev, EBI_NOR_SRAM_EXTENDED_TypeDef *e_dev, uint32_t bank)
DeInitialize the EBI_NOR_SRAM peripheral.
Definition: ald_ebi.c:172
sram_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_sram.h:56
ALD_SRAM_STATE_RESET
Definition: ald_sram.h:43
sram_handle_t::state
__IO ald_sram_state_t state
Definition: ald_sram.h:58
sram_handle_t::ext
EBI_NOR_SRAM_EXTENDED_TypeDef * ext
Definition: ald_sram.h:55
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399

◆ ald_sram_init()

ald_status_t ald_sram_init | ( | sram_handle_t * | hperh,
 |  | ald_ebi_nor_sram_timing_t * | timing,
 |  | ald_ebi_nor_sram_timing_t * | ext_timing
 | ) |  |

Performs the SRAM device initialization sequence.

Parameters
hperh | pointer to a sram_handle_t structure
timing | Pointer to SRAM control timing structure
ext_timing | Pointer to SRAM extended mode timing structure
Return values
ald status

Definition at line 43 of file ald_sram.c.

44 {
45 if (hperh == NULL)
46 return ERROR;
47
48 if (hperh->state == ALD_SRAM_STATE_RESET)
49 hperh->lock = UNLOCK;
50
51 /* Initialize SRAM control Interface */
52 ald_ebi_nor_sram_init(hperh->instance, &(hperh->init));
53 /* Initialize SRAM timing Interface */
54 ald_ebi_nor_sram_timing_init(hperh->instance, timing, hperh->init.bank);
55 /* Initialize SRAM extended mode timing Interface */
56 ald_ebi_nor_sram_ext_timing_init(hperh->ext, ext_timing, hperh->init.bank, hperh->init.ext_mode);
57 /* Enable the NORSRAM device */
58 ald_ebi_nor_sram_enable(hperh->instance, hperh->init.bank);
59
60 return OK;
61 }
OK
Definition: utils.h:55
sram_handle_t::lock
lock_state_t lock
Definition: ald_sram.h:57
sram_handle_t::instance
EBI_NOR_SRAM_TypeDef * instance
Definition: ald_sram.h:54
UNLOCK
Definition: type.h:59
sram_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_sram.h:56
ald_ebi_nor_sram_init_t::ext_mode
ebi_extended_mode_t ext_mode
Definition: ald_ebi.h:409
ald_ebi_nor_sram_timing_init
void ald_ebi_nor_sram_timing_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank)
Initialize the EBI_NOR_SRAM Timing according to the specified parameters in the EBI_NOR_SRAM_TimingTy...
Definition: ald_ebi.c:104
ALD_SRAM_STATE_RESET
Definition: ald_sram.h:43
ald_ebi_nor_sram_init
void ald_ebi_nor_sram_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_init_t *init)
Initialize the EBI_NOR_SRAM device according to the specified control parameters in the EBI_NOR_SRAM_...
Definition: ald_ebi.c:43
sram_handle_t::state
__IO ald_sram_state_t state
Definition: ald_sram.h:58
ERROR
Definition: utils.h:56
sram_handle_t::ext
EBI_NOR_SRAM_EXTENDED_TypeDef * ext
Definition: ald_sram.h:55
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399
ald_ebi_nor_sram_enable
void ald_ebi_nor_sram_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Enable the NOR/SRAM device access.
Definition: ald_ebi.c:206
ald_ebi_nor_sram_ext_timing_init
void ald_ebi_nor_sram_ext_timing_init(EBI_NOR_SRAM_EXTENDED_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank, uint32_t mode)
Initialize the EBI_NOR_SRAM Extended mode Timing according to the specified parameters in the EBI_NOR...
Definition: ald_ebi.c:138


ALD User Manual: I/O operation functions

Functions
I/O operation functions
EASTSOFT ES32F3xx ALD » SRAM » SRAM Public Functions

I/O operation functions. More...

Collaboration diagram for I/O operation functions:

Functions

ald_status_t | ald_sram_read_8b (sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size)
Reads 8-bit buffer from SRAM memory. More...
ald_status_t | ald_sram_write_8b (sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size)
Writes 8-bit buffer to SRAM memory. More...
ald_status_t | ald_sram_read_16b (sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size)
Reads 16-bit buffer from SRAM memory. More...
ald_status_t | ald_sram_write_16b (sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size)
Writes 16-bit buffer to SRAM memory. More...
ald_status_t | ald_sram_read_32b (sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size)
Reads 32-bit buffer from SRAM memory. More...
ald_status_t | ald_sram_write_32b (sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size)
Writes 32-bit buffer to SRAM memory. More...
ald_status_t | ald_sram_read_by_dma (sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch)
Reads a halfwords data from the SRAM memory using DMA transfer. More...
ald_status_t | ald_sram_write_by_dma (sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch)
Write a halfwords data to the SRAM memory using DMA transfer. More...

Detailed Description

I/O operation functions.

Function Documentation

◆ ald_sram_read_16b()

ald_status_t ald_sram_read_16b | ( | sram_handle_t * | hperh,
 |  | uint32_t * | addr,
 |  | uint16_t * | buf,
 |  | uint32_t | size
 | ) |  |

Reads 16-bit buffer from SRAM memory.

Parameters
hperh | pointer to a sram_handle_t structure that contains the configuration information for SRAM module.
addr | Pointer to read start address
buf | Pointer to destination buffer
size | Size of the buffer to read from memory
Return values
ald status

Definition at line 146 of file ald_sram.c.

147 {
148 __IO uint16_t * psramaddr = (uint16_t *)addr;
149
150 __LOCK(hperh);
151 hperh->state = ALD_SRAM_STATE_BUSY;
152
153 /* Read data from memory */
154 for (; size != 0U; size--)
155 *buf++ = *(__IO uint16_t *)psramaddr++;
156
157 hperh->state = ALD_SRAM_STATE_READY;
158 __UNLOCK(hperh);
159
160 return OK;
161 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
ALD_SRAM_STATE_READY
Definition: ald_sram.h:44
ALD_SRAM_STATE_BUSY
Definition: ald_sram.h:45
sram_handle_t::state
__IO ald_sram_state_t state
Definition: ald_sram.h:58
__LOCK
#define __LOCK(x)
Definition: utils.h:92

◆ ald_sram_read_32b()

ald_status_t ald_sram_read_32b | ( | sram_handle_t * | hperh,
 |  | uint32_t * | addr,
 |  | uint32_t * | buf,
 |  | uint32_t | size
 | ) |  |

Reads 32-bit buffer from SRAM memory.

Parameters
hperh | pointer to a sram_handle_t structure
addr | Pointer to read start address
buf | Pointer to destination buffer
size | Size of the buffer to read from memory
Return values
ald status

Definition at line 200 of file ald_sram.c.

201 {
202 __LOCK(hperh);
203 hperh->state = ALD_SRAM_STATE_BUSY;
204
205 /* Read data from memory */
206 for (; size != 0U; size--)
207 *buf++ = *(__IO uint32_t *)addr++;
208
209 hperh->state = ALD_SRAM_STATE_READY;
210 __UNLOCK(hperh);
211
212 return OK;
213 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
ALD_SRAM_STATE_READY
Definition: ald_sram.h:44
ALD_SRAM_STATE_BUSY
Definition: ald_sram.h:45
sram_handle_t::state
__IO ald_sram_state_t state
Definition: ald_sram.h:58
__LOCK
#define __LOCK(x)
Definition: utils.h:92

◆ ald_sram_read_8b()

ald_status_t ald_sram_read_8b | ( | sram_handle_t * | hperh,
 |  | uint32_t * | addr,
 |  | uint8_t * | buf,
 |  | uint32_t | size
 | ) |  |

Reads 8-bit buffer from SRAM memory.

Parameters
hperh | pointer to a sram_handle_t structure
addr | Pointer to read start address
buf | Pointer to destination buffer
size | Size of the buffer to read from memory
Return values
ald status

Definition at line 92 of file ald_sram.c.

93 {
94 __IO uint8_t * psramaddr = (uint8_t *)addr;
95
96 __LOCK(hperh);
97 hperh->state = ALD_SRAM_STATE_BUSY;
98
99 /* Read data from memory */
100 for (; size != 0U; size--)
101 *buf++ = *(__IO uint8_t *)psramaddr++;
102
103 hperh->state = ALD_SRAM_STATE_READY;
104 __UNLOCK(hperh);
105
106 return OK;
107 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
ALD_SRAM_STATE_READY
Definition: ald_sram.h:44
ALD_SRAM_STATE_BUSY
Definition: ald_sram.h:45
sram_handle_t::state
__IO ald_sram_state_t state
Definition: ald_sram.h:58
__LOCK
#define __LOCK(x)
Definition: utils.h:92

◆ ald_sram_read_by_dma()

ald_status_t ald_sram_read_by_dma | ( | sram_handle_t * | hperh,
 |  | uint16_t * | addr,
 |  | uint16_t * | buf,
 |  | uint16_t | size,
 |  | uint8_t | ch
 | ) |  |

Reads a halfwords data from the SRAM memory using DMA transfer.

Parameters
hperh | pointer to a sram_handle_t structure that contains the configuration information for SRAM module.
addr | Pointer to read start address
buf | Pointer to destination buffer
size | Size of the buffer to read from memory
ch | Index of DMA channel
Return values
ald status

Definition at line 253 of file ald_sram.c.

254 {
255 if (buf == NULL)
256 return ERROR;
257
258 hperh->hdma.perh = DMA0;
259 hperh->hdma.cplt_cbk = hperh->cplt_cbk;
260 ald_dma_config_struct(&hperh->hdma.config);
261
262 hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD;
263 hperh->hdma.config.src = (void *)addr;
264 hperh->hdma.config.dst = (void *)buf;
265 hperh->hdma.config.size = size;
266 hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD;
267 hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD;
268 hperh->hdma.config.msel = DMA_MSEL_NONE;
269 hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE;
270 hperh->hdma.config.channel = ch;
271 hperh->hdma.config.R_power = DMA_R_POWER_4;
272 hperh->hdma.config.burst = ENABLE;
273
274 ald_dma_config_auto(&hperh->hdma);
275 return OK;
276 }
DMA_R_POWER_4
Definition: ald_dma.h:253
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
OK
Definition: utils.h:55
DMA_MSEL_NONE
Definition: ald_dma.h:78
dma_config_t::R_power
dma_arbiter_config_t R_power
Definition: ald_dma.h:284
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
sram_handle_t::hdma
dma_handle_t hdma
Definition: ald_sram.h:60
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
DMA_MSIGSEL_NONE
Definition: ald_dma.h:115
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
ald_dma_config_auto
void ald_dma_config_auto(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is automatic. This mode is used to carry data from memory to memory.
Definition: ald_dma.c:392
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
ERROR
Definition: utils.h:56
sram_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_sram.h:61
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294

◆ ald_sram_write_16b()

ald_status_t ald_sram_write_16b | ( | sram_handle_t * | hperh,
 |  | uint32_t * | addr,
 |  | uint16_t * | buf,
 |  | uint32_t | size
 | ) |  |

Writes 16-bit buffer to SRAM memory.

Parameters
hperh | pointer to a sram_handle_t structure that contains the configuration information for SRAM module.
addr | Pointer to write start address
buf | Pointer to source buffer to write
size | Size of the buffer to write to memory
Return values
ald status

Definition at line 172 of file ald_sram.c.

173 {
174 __IO uint16_t * psramaddr = (uint16_t *)addr;
175
176 if (hperh->state == ALD_SRAM_STATE_PROTECTED)
177 return ERROR;
178
179 __LOCK(hperh);
180 hperh->state = ALD_SRAM_STATE_BUSY;
181
182 /* Write data to memory */
183 for (; size != 0U; size--)
184 *(__IO uint16_t *)psramaddr++ = *buf++;
185
186 hperh->state = ALD_SRAM_STATE_READY;
187 __UNLOCK(hperh);
188
189 return OK;
190 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
ALD_SRAM_STATE_PROTECTED
Definition: ald_sram.h:47
ALD_SRAM_STATE_READY
Definition: ald_sram.h:44
ALD_SRAM_STATE_BUSY
Definition: ald_sram.h:45
sram_handle_t::state
__IO ald_sram_state_t state
Definition: ald_sram.h:58
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56

◆ ald_sram_write_32b()

ald_status_t ald_sram_write_32b | ( | sram_handle_t * | hperh,
 |  | uint32_t * | addr,
 |  | uint32_t * | buf,
 |  | uint32_t | size
 | ) |  |

Writes 32-bit buffer to SRAM memory.

Parameters
hperh | pointer to a sram_handle_t structure that contains the configuration information for SRAM module.
addr | Pointer to write start address
buf | Pointer to source buffer to write
size | Size of the buffer to write to memory
Return values
ald status

Definition at line 224 of file ald_sram.c.

225 {
226 if (hperh->state == ALD_SRAM_STATE_PROTECTED)
227 return ERROR;
228
229 __LOCK(hperh);
230 hperh->state = ALD_SRAM_STATE_BUSY;
231
232 /* Write data to memory */
233 for (; size != 0U; size--)
234 *(__IO uint32_t *)addr++ = *buf++;
235
236 hperh->state = ALD_SRAM_STATE_READY;
237 __UNLOCK(hperh);
238
239 return OK;
240 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
ALD_SRAM_STATE_PROTECTED
Definition: ald_sram.h:47
ALD_SRAM_STATE_READY
Definition: ald_sram.h:44
ALD_SRAM_STATE_BUSY
Definition: ald_sram.h:45
sram_handle_t::state
__IO ald_sram_state_t state
Definition: ald_sram.h:58
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56

◆ ald_sram_write_8b()

ald_status_t ald_sram_write_8b | ( | sram_handle_t * | hperh,
 |  | uint32_t * | addr,
 |  | uint8_t * | buf,
 |  | uint32_t | size
 | ) |  |

Writes 8-bit buffer to SRAM memory.

Parameters
hperh | pointer to a sram_handle_t structure
addr | Pointer to write start address
buf | Pointer to source buffer to write
size | Size of the buffer to write to memory
Return values
ald status

Definition at line 117 of file ald_sram.c.

118 {
119 __IO uint8_t * psramaddr = (uint8_t *)addr;
120
121 if (hperh->state == ALD_SRAM_STATE_PROTECTED)
122 return ERROR;
123
124 __LOCK(hperh);
125 hperh->state = ALD_SRAM_STATE_BUSY;
126
127 /* Write data to memory */
128 for (; size != 0U; size--)
129 *(__IO uint8_t *)psramaddr++ = *buf++;
130
131 hperh->state = ALD_SRAM_STATE_READY;
132 __UNLOCK(hperh);
133
134 return OK;
135 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
ALD_SRAM_STATE_PROTECTED
Definition: ald_sram.h:47
ALD_SRAM_STATE_READY
Definition: ald_sram.h:44
ALD_SRAM_STATE_BUSY
Definition: ald_sram.h:45
sram_handle_t::state
__IO ald_sram_state_t state
Definition: ald_sram.h:58
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56

◆ ald_sram_write_by_dma()

ald_status_t ald_sram_write_by_dma | ( | sram_handle_t * | hperh,
 |  | uint16_t * | addr,
 |  | uint16_t * | buf,
 |  | uint16_t | size,
 |  | uint8_t | ch
 | ) |  |

Write a halfwords data to the SRAM memory using DMA transfer.

Parameters
hperh | pointer to a sram_handle_t structure that contains the configuration information for SRAM module.
addr | Pointer to write start address
buf | Pointer to destination buffer
size | Size of the buffer to write from memory
ch | Index of DMA channel
Return values
ald status

Definition at line 288 of file ald_sram.c.

289 {
290 if (buf == NULL)
291 return ERROR;
292 ;
293 hperh->hdma.perh = DMA0;
294 hperh->hdma.cplt_cbk = hperh->cplt_cbk;
295 ald_dma_config_struct(&hperh->hdma.config);
296
297 hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD;
298 hperh->hdma.config.src = (void *)buf;
299 hperh->hdma.config.dst = (void *)addr;
300 hperh->hdma.config.size = size;
301 hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD;
302 hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD;
303 hperh->hdma.config.msel = DMA_MSEL_NONE;
304 hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE;
305 hperh->hdma.config.channel = ch;
306 hperh->hdma.config.R_power = DMA_R_POWER_4;
307 hperh->hdma.config.burst = ENABLE;
308
309 ald_dma_config_auto(&hperh->hdma);
310 return OK;
311 }
DMA_R_POWER_4
Definition: ald_dma.h:253
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
OK
Definition: utils.h:55
DMA_MSEL_NONE
Definition: ald_dma.h:78
dma_config_t::R_power
dma_arbiter_config_t R_power
Definition: ald_dma.h:284
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
sram_handle_t::hdma
dma_handle_t hdma
Definition: ald_sram.h:60
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
DMA_MSIGSEL_NONE
Definition: ald_dma.h:115
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
ald_dma_config_auto
void ald_dma_config_auto(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is automatic. This mode is used to carry data from memory to memory.
Definition: ald_dma.c:392
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
ERROR
Definition: utils.h:56
sram_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_sram.h:61
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294


ALD User Manual: Control functions

Functions
Control functions
EASTSOFT ES32F3xx ALD » SRAM » SRAM Public Functions

Control functions. More...

Collaboration diagram for Control functions:

Functions

ald_status_t | ald_sram_write_enable (sram_handle_t *hperh)
Enables dynamically SRAM write operation. More...
ald_status_t | ald_sram_write_disable (sram_handle_t *hperh)
Disables dynamically SRAM write operation. More...

Detailed Description

Control functions.

Function Documentation

◆ ald_sram_write_disable()

ald_status_t ald_sram_write_disable ( sram_handle_t * hperh )

Disables dynamically SRAM write operation.

Parameters
hperh pointer to a sram_handle_t structure
Return values
ald status

Definition at line 341 of file ald_sram.c.

342 {
343 __LOCK(hperh);
344 hperh->state = ALD_SRAM_STATE_BUSY;
345 ald_ebi_nor_sram_write_disable(hperh->instance, hperh->init.bank);
346 hperh->state = ALD_SRAM_STATE_PROTECTED;
347 __UNLOCK(hperh);
348
349 return OK;
350 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
ALD_SRAM_STATE_PROTECTED
Definition: ald_sram.h:47
sram_handle_t::instance
EBI_NOR_SRAM_TypeDef * instance
Definition: ald_sram.h:54
sram_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_sram.h:56
ALD_SRAM_STATE_BUSY
Definition: ald_sram.h:45
ald_ebi_nor_sram_write_disable
void ald_ebi_nor_sram_write_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Disables dynamically EBI_NORSRAM write operation.
Definition: ald_ebi.c:249
sram_handle_t::state
__IO ald_sram_state_t state
Definition: ald_sram.h:58
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399

◆ ald_sram_write_enable()

ald_status_t ald_sram_write_enable ( sram_handle_t * hperh )

Enables dynamically SRAM write operation.

Parameters
hperh pointer to a sram_handle_t structure
Return values
ald status

Definition at line 326 of file ald_sram.c.

327 {
328 __LOCK(hperh);
329 ald_ebi_nor_sram_write_enable(hperh->instance, hperh->init.bank);
330 hperh->state = ALD_SRAM_STATE_READY;
331 __UNLOCK(hperh);
332
333 return OK;
334 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
sram_handle_t::instance
EBI_NOR_SRAM_TypeDef * instance
Definition: ald_sram.h:54
sram_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_sram.h:56
ald_ebi_nor_sram_write_enable
void ald_ebi_nor_sram_write_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Enables dynamically NOR-FLASH/SRAM write operation.
Definition: ald_ebi.c:234
ALD_SRAM_STATE_READY
Definition: ald_sram.h:44
sram_handle_t::state
__IO ald_sram_state_t state
Definition: ald_sram.h:58
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399


ALD User Manual: State functions

Functions
State functions
EASTSOFT ES32F3xx ALD » SRAM » SRAM Public Functions

State functions. More...

Collaboration diagram for State functions:

Functions

ald_sram_state_t ald_sram_get_state (sram_handle_t *hperh)
Returns the SRAM controller state. More...

Detailed Description

State functions.

Function Documentation

◆ ald_sram_get_state()

ald_sram_state_t ald_sram_get_state ( sram_handle_t * hperh )

Returns the SRAM controller state.

Parameters
hperh pointer to a SRAM_HandleTypeDef structure
Return values
ald state

Definition at line 364 of file ald_sram.c.

365 {
366 return hperh->state;
367 }
sram_handle_t::state
__IO ald_sram_state_t state
Definition: ald_sram.h:58


ALD User Manual: SRAM Public Types

Data Structures | Enumerations
SRAM Public Types
EASTSOFT ES32F3xx ALD » SRAM
Collaboration diagram for SRAM Public Types:

Data Structures

struct sram_handle_t
SRAM handle Structure definition. More...

Enumerations

enum ald_sram_state_t {
ALD_SRAM_STATE_RESET = 0x00U, ALD_SRAM_STATE_READY = 0x01U, ALD_SRAM_STATE_BUSY = 0x02U, ALD_SRAM_STATE_ERROR = 0x03U,
ALD_SRAM_STATE_PROTECTED = 0x04U
}
ALD SRAM State structures definition. More...

Detailed Description

Enumeration Type Documentation

◆ ald_sram_state_t

enum ald_sram_state_t

ALD SRAM State structures definition.

Enumerator
ALD_SRAM_STATE_RESET | SRAM not yet initialized or disabled
ALD_SRAM_STATE_READY | SRAM initialized and ready for use
ALD_SRAM_STATE_BUSY | SRAM internal process is ongoing
ALD_SRAM_STATE_ERROR | SRAM error state
ALD_SRAM_STATE_PROTECTED | SRAM peripheral NORSRAM device write protected

Definition at line 42 of file ald_sram.h.

42 {
43 ALD_SRAM_STATE_RESET = 0x00U,
44 ALD_SRAM_STATE_READY = 0x01U,
45 ALD_SRAM_STATE_BUSY = 0x02U,
46 ALD_SRAM_STATE_ERROR = 0x03U,
47 ALD_SRAM_STATE_PROTECTED = 0x04U
48 } ald_sram_state_t;
ALD_SRAM_STATE_ERROR
Definition: ald_sram.h:46
ALD_SRAM_STATE_PROTECTED
Definition: ald_sram.h:47
ALD_SRAM_STATE_READY
Definition: ald_sram.h:44
ALD_SRAM_STATE_BUSY
Definition: ald_sram.h:45
ALD_SRAM_STATE_RESET
Definition: ald_sram.h:43
ald_sram_state_t
ald_sram_state_t
ALD SRAM State structures definition.
Definition: ald_sram.h:42


ALD User Manual: sram_handle_t Struct Reference

Data Fields
sram_handle_t Struct Reference
EASTSOFT ES32F3xx ALD » SRAM » SRAM Public Types

SRAM handle Structure definition. More...

#include <ald_sram.h>

Collaboration diagram for sram_handle_t:
[legend]

Data Fields

EBI_NOR_SRAM_TypeDef * instance
EBI_NOR_SRAM_EXTENDED_TypeDef * ext
ald_ebi_nor_sram_init_t init
lock_state_t lock
__IO ald_sram_state_t | state
dma_handle_t hdma
void(* | cplt_cbk )(void *arg)

Detailed Description

SRAM handle Structure definition.

Definition at line 53 of file ald_sram.h.

Field Documentation

◆ cplt_cbk

void(* cplt_cbk) (void *arg)

DMA transmit completely callback function

Definition at line 61 of file ald_sram.h.

◆ ext

EBI_NOR_SRAM_EXTENDED_TypeDef* ext

Extended mode register base address

Definition at line 55 of file ald_sram.h.

◆ hdma

dma_handle_t hdma

SRAM DMA Handle parameters

Definition at line 60 of file ald_sram.h.

◆ init

ald_ebi_nor_sram_init_t init

SRAM device control configuration parameters

Definition at line 56 of file ald_sram.h.

◆ instance

EBI_NOR_SRAM_TypeDef* instance

Register base address

Definition at line 54 of file ald_sram.h.

◆ lock

lock_state_t lock

SRAM locking object

Definition at line 57 of file ald_sram.h.

◆ state

__IO ald_sram_state_t state

SRAM device access state

Definition at line 58 of file ald_sram.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_sram.h


ALD User Manual: SYSCFG

Modules
SYSCFG
EASTSOFT ES32F3xx ALD

SYSCFG module driver. More...

Collaboration diagram for SYSCFG:

Modules

SYSCFG Public Macros
SYSCFG Public Functions

Detailed Description

SYSCFG module driver.


ALD User Manual: SYSCFG Public Macros

Macros
SYSCFG Public Macros
EASTSOFT ES32F3xx ALD » SYSCFG
Collaboration diagram for SYSCFG Public Macros:

Macros

#define | SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0U)
#define | SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996U)
#define | GET_SYSCFG_LOCK() READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK)
#define | SYSCFG_BOOTFLASH_MAPPING_ENABLE() SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK)
#define | SYSCFG_BOOTFLASH_MAPPING_DISABLE() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK)

Detailed Description

Macro Definition Documentation

◆ GET_SYSCFG_LOCK

#define GET_SYSCFG_LOCK ( ) READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK)

Definition at line 41 of file ald_syscfg.h.

◆ SYSCFG_BOOTFLASH_MAPPING_DISABLE

#define SYSCFG_BOOTFLASH_MAPPING_DISABLE ( ) CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK)

Definition at line 44 of file ald_syscfg.h.

◆ SYSCFG_BOOTFLASH_MAPPING_ENABLE

#define SYSCFG_BOOTFLASH_MAPPING_ENABLE ( ) SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK)

Definition at line 43 of file ald_syscfg.h.

◆ SYSCFG_LOCK

#define SYSCFG_LOCK ( ) WRITE_REG(SYSCFG->PROT, 0x0U)

Definition at line 39 of file ald_syscfg.h.

◆ SYSCFG_UNLOCK

#define SYSCFG_UNLOCK ( ) WRITE_REG(SYSCFG->PROT, 0x55AA6996U)

Definition at line 40 of file ald_syscfg.h.


ALD User Manual: SYSCFG Public Functions

Functions
SYSCFG Public Functions
EASTSOFT ES32F3xx ALD » SYSCFG
Collaboration diagram for SYSCFG Public Functions:

Functions

__STATIC_INLINE__ void ald_vtor_config (uint32_t offset, type_func_t status)
Set the offset of the interrup vector map. More...

Detailed Description

Function Documentation

◆ ald_vtor_config()

__STATIC_INLINE__ void ald_vtor_config | ( | uint32_t | offset,
 |  | type_func_t | status
 | ) |  |

Set the offset of the interrup vector map.

Parameters
offset | Offset of the interrup vector map
status | ENABLE/DISABLE
Return values
None

Definition at line 58 of file ald_syscfg.h.

59 {
60 SCB->VTOR = status ? (offset & ~0x3FU) : 0;
61 return;
62 }


ALD User Manual: TIMER

Modules
TIMER
EASTSOFT ES32F3xx ALD

TIMER module driver. More...

Collaboration diagram for TIMER:

Modules

TIMER Private Functions
TIMER Public Functions
TIMER Public Types
TIMER Public Macros
TIMER Private Macros

Detailed Description

TIMER module driver.


ALD User Manual: TIMER Private Functions

Functions
TIMER Private Functions
EASTSOFT ES32F3xx ALD » TIMER
Collaboration diagram for TIMER Private Functions:

Functions

static void | timer_base_set_config (TIMER_TypeDef *TIMERx, timer_base_init_t *init)
Time Base configuration. More...
static void | timer_oc1_set_config (TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
Time Ouput Compare 1 configuration. More...
static void | timer_oc2_set_config (TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
Time Ouput Compare 2 configuration. More...
static void | timer_oc3_set_config (TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
Time Ouput Compare 3 configuration. More...
static void | timer_oc4_set_config (TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
Time Ouput Compare 4 configuration. More...
static void | timer_ccx_channel_cmd (TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x. More...
static void | timer_ccxn_channel_cmd (TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel xN. More...
static void | timer_ti1_set_config (TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, timer_ic_select_t sel, uint32_t filter)
Configure the TI1 as Input. More...
static void | timer_ti1_set_config_stage (TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter)
Configure the Polarity and Filter for TI1. More...
static void | timer_ti2_set_config (TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, timer_ic_select_t sel, uint32_t filter)
Configure the TI2 as Input. More...
static void | timer_ti2_set_config_stage (TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter)
Configure the Polarity and Filter for TI2. More...
static void | timer_ti3_set_config (TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, timer_ic_select_t sel, uint32_t filter)
Configure the TI3 as Input. More...
static void | timer_ti4_set_config (TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, timer_ic_select_t sel, uint32_t filter)
Configure the TI4 as Input. More...
static void | timer_etr_set_config (TIMER_TypeDef *TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter)
Configures the TIMERx External Trigger (ETR). More...
static void | timer_slave_set_config (timer_handle_t *hperh, timer_slave_config_t *config)
Time Slave configuration. More...
static void | timer_dma_oc_cplt (void *arg)
TIMER DMA out compare complete callback. More...
static void | timer_dma_capture_cplt (void *arg)
TIMER DMA Capture complete callback. More...
static void | timer_dma_period_elapse_cplt (void *arg)
TIMER DMA Period Elapse complete callback. More...
static void | timer_dma_error (void *arg)
TIMER DMA error callback. More...
static void | timer_dma_msel (TIMER_TypeDef *hperh, dma_config_t *config)
Timer DMA msel signal configuration. More...

Detailed Description

Function Documentation

◆ timer_base_set_config()

static void timer_base_set_config | ( | TIMER_TypeDef * | TIMERx,
 |  | timer_base_init_t * | init
 | ) |  |
static

Time Base configuration.

Parameters
TIMERx | TIMER periheral
init | TIMER Base configuration structure
Return values
None

Definition at line 3258 of file ald_timer.c.

3259 {
3260 assert_param(IS_TIMER_COUNTER_MODE(init->mode));
3261 assert_param(IS_TIMER_CLOCK_DIVISION(init->clk_div));
3262
3263 if (init->mode == TIMER_CNT_MODE_UP || init->mode == TIMER_CNT_MODE_DOWN) {
3264 CLEAR_BIT(TIMERx->CON1, TIMER_CON1_CMSEL_MSK);
3265 MODIFY_REG(TIMERx->CON1, TIMER_CON1_DIRSEL_MSK, init->mode << TIMER_CON1_DIRSEL_POS);
3266 }
3267 else {
3268 MODIFY_REG(TIMERx->CON1, TIMER_CON1_CMSEL_MSK, (init->mode - 1) << TIMER_CON1_CMSEL_POSS);
3269 }
3270
3271 if (IS_TIMER_CLOCK_DIVISION_INSTANCE(TIMERx))
3272 MODIFY_REG(TIMERx->CON1, TIMER_CON1_DFCKSEL_MSK, init->clk_div << TIMER_CON1_DFCKSEL_POSS);
3273
3274 WRITE_REG(TIMERx->AR, init->period);
3275 WRITE_REG(TIMERx->PRES, init->prescaler);
3276
3277 if (IS_TIMER_REPETITION_COUNTER_INSTANCE(TIMERx))
3278 WRITE_REG(TIMERx->REPAR, init->re_cnt);
3279
3280 return;
3281 }
timer_base_init_t::re_cnt
uint32_t re_cnt
Definition: ald_timer.h:141
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
timer_base_init_t::clk_div
timer_clock_division_t clk_div
Definition: ald_timer.h:140
IS_TIMER_COUNTER_MODE
#define IS_TIMER_COUNTER_MODE(x)
Definition: ald_timer.h:847
timer_base_init_t::period
uint32_t period
Definition: ald_timer.h:139
timer_base_init_t::prescaler
uint32_t prescaler
Definition: ald_timer.h:137
TIMER_CNT_MODE_UP
Definition: ald_timer.h:44
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
TIMER_CNT_MODE_DOWN
Definition: ald_timer.h:45
timer_base_init_t::mode
timer_cnt_mode_t mode
Definition: ald_timer.h:138
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_TIMER_CLOCK_DIVISION
#define IS_TIMER_CLOCK_DIVISION(x)
Definition: ald_timer.h:852

◆ timer_ccx_channel_cmd()

static void timer_ccx_channel_cmd | ( | TIMER_TypeDef * | TIMERx,
 |  | timer_channel_t | ch,
 |  | type_func_t | state
 | ) |  |
static

Enables or disables the TIMER Capture Compare Channel x.

Parameters
TIMERx | Select the TIMER peripheral
ch specifies the TIMER Channel This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1
  • TIMER_CHANNEL_2: TIMER Channel 2
  • TIMER_CHANNEL_3: TIMER Channel 3
  • TIMER_CHANNEL_4: TIMER Channel 4
state | specifies the TIMER Channel CCxE bit new state.
Return values
None

Definition at line 3410 of file ald_timer.c.

3411 {
3412 assert_param(IS_TIMER_CC2_INSTANCE(TIMERx));
3413 assert_param(IS_TIMER_CHANNELS(ch));
3414
3415 switch (ch) {
3416 case TIMER_CHANNEL_1:
3417 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK, state << TIMER_CCEP_CC1EN_POS);
3418 break;
3419
3420 case TIMER_CHANNEL_2:
3421 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK, state << TIMER_CCEP_CC2EN_POS);
3422 break;
3423
3424 case TIMER_CHANNEL_3:
3425 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK, state << TIMER_CCEP_CC3EN_POS);
3426 break;
3427
3428 case TIMER_CHANNEL_4:
3429 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK, state << TIMER_CCEP_CC4EN_POS);
3430 break;
3431
3432 default:
3433 break;
3434 }
3435 }
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_CHANNEL_3
Definition: ald_timer.h:112
TIMER_CHANNEL_1
Definition: ald_timer.h:110
IS_TIMER_CHANNELS
#define IS_TIMER_CHANNELS(x)
Definition: ald_timer.h:873
TIMER_CHANNEL_4
Definition: ald_timer.h:113
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ timer_ccxn_channel_cmd()

static void timer_ccxn_channel_cmd | ( | TIMER_TypeDef * | TIMERx,
 |  | timer_channel_t | ch,
 |  | type_func_t | state
 | ) |  |
static

Enables or disables the TIMER Capture Compare Channel xN.

Parameters
TIMERx | Select the TIMER peripheral
ch specifies the TIMER Channel This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1
  • TIMER_CHANNEL_2: TIMER Channel 2
  • TIMER_CHANNEL_3: TIMER Channel 3
state | specifies the TIMER Channel CCxNE bit new state.
Return values
None

Definition at line 3447 of file ald_timer.c.

3448 {
3449 switch (ch) {
3450 case TIMER_CHANNEL_1:
3451 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK, state << TIMER_CCEP_CC1NEN_POS);
3452 break;
3453
3454 case TIMER_CHANNEL_2:
3455 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK, state << TIMER_CCEP_CC2NEN_POS);
3456 break;
3457
3458 case TIMER_CHANNEL_3:
3459 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK, state << TIMER_CCEP_CC3NEN_POS);
3460 break;
3461
3462 default:
3463 break;
3464 }
3465
3466 }
TIMER_CHANNEL_3
Definition: ald_timer.h:112
TIMER_CHANNEL_1
Definition: ald_timer.h:110
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ timer_dma_capture_cplt()

void timer_dma_capture_cplt ( void * arg )
static

TIMER DMA Capture complete callback.

Parameters
arg pointer to TIMER handle.
Return values
None

Definition at line 3208 of file ald_timer.c.

3209 {
3210 timer_handle_t *hperh = (timer_handle_t *)arg;
3211
3212 if (hperh->capture_cbk)
3213 hperh->capture_cbk(hperh);
3214
3215 hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED;
3216 return;
3217 }
timer_handle_s::capture_cbk
void(* capture_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:196
timer_handle_s
TIMER time base handle structure definition.
Definition: ald_timer.h:182
TIMER_ACTIVE_CHANNEL_CLEARED
Definition: ald_timer.h:176
timer_handle_s::ch
timer_active_channel_t ch
Definition: ald_timer.h:185

◆ timer_dma_error()

void timer_dma_error ( void * arg )
static

TIMER DMA error callback.

Parameters
arg pointer to TIMER handle.
Return values
None

Definition at line 3240 of file ald_timer.c.

3241 {
3242 timer_handle_t *hperh = (timer_handle_t *)arg;
3243
3244 hperh->state = TIMER_STATE_READY;
3245 if (hperh->error_cbk)
3246 hperh->error_cbk(hperh);
3247
3248 return;
3249 }
TIMER_STATE_READY
Definition: ald_timer.h:162
timer_handle_s
TIMER time base handle structure definition.
Definition: ald_timer.h:182
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
timer_handle_s::error_cbk
void(* error_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:201

◆ timer_dma_msel()

static void timer_dma_msel | ( | TIMER_TypeDef * | hperh,
 |  | dma_config_t * | config
 | ) |  |
static

Timer DMA msel signal configuration.

Parameters
hperh | pointer to a timer_handle_t structure that contains the configuration information for TIMER module.
config | DMA configuration structure
Return values
None

Definition at line 3640 of file ald_timer.c.

3641 {
3642 #if defined (ES32F36xx)
3643 if (hperh == AD16C4T0)
3644 config->msel = DMA_MSEL_TIMER0;
3645 if (hperh == AD16C4T1)
3646 config->msel = DMA_MSEL_TIMER1;
3647 if (hperh == GP32C4T0)
3648 config->msel = DMA_MSEL_TIMER2;
3649 if (hperh == GP32C4T1)
3650 config->msel = DMA_MSEL_TIMER3;
3651 if (hperh == BS16T0)
3652 config->msel = DMA_MSEL_TIMER4;
3653 if (hperh == BS16T1)
3654 config->msel = DMA_MSEL_TIMER5;
3655 if (hperh == GP32C4T0)
3656 config->msel = DMA_MSEL_TIMER6;
3657 if (hperh == GP32C4T1)
3658 config->msel = DMA_MSEL_TIMER7;
3659 #elif defined(ES32F39xx) || defined(ES32F336x)
3660 if (hperh == GP16C4T0)
3661 config->msel = DMA_MSEL_TIMER0;
3662 if (hperh == GP16C4T1)
3663 config->msel = DMA_MSEL_TIMER1;
3664 if (hperh == GP32C4T0)
3665 config->msel = DMA_MSEL_TIMER2;
3666 if (hperh == GP32C4T1)
3667 config->msel = DMA_MSEL_TIMER3;
3668 if (hperh == BS16T0)
3669 config->msel = DMA_MSEL_TIMER4;
3670 if (hperh == BS16T1)
3671 config->msel = DMA_MSEL_TIMER5;
3672 if (hperh == GP16C4T2)
3673 config->msel = DMA_MSEL_TIMER6;
3674 if (hperh == GP16C4T3)
3675 config->msel = DMA_MSEL_TIMER7;
3676 #endif
3677 }
DMA_MSEL_TIMER2
Definition: ald_dma.h:96
DMA_MSEL_TIMER4
Definition: ald_dma.h:100
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
DMA_MSEL_TIMER6
Definition: ald_dma.h:102
DMA_MSEL_TIMER7
Definition: ald_dma.h:103
DMA_MSEL_TIMER0
Definition: ald_dma.h:94
DMA_MSEL_TIMER3
Definition: ald_dma.h:97
DMA_MSEL_TIMER1
Definition: ald_dma.h:95
DMA_MSEL_TIMER5
Definition: ald_dma.h:101

◆ timer_dma_oc_cplt()

void timer_dma_oc_cplt ( void * arg )
static

TIMER DMA out compare complete callback.

Parameters
arg pointer to TIMER handle.
Return values
None

Definition at line 3189 of file ald_timer.c.

3190 {
3191 timer_handle_t *hperh = (timer_handle_t *)arg;
3192
3193 if (hperh->delay_elapse_cbk)
3194 hperh->delay_elapse_cbk(hperh);
3195
3196 if (hperh->pwm_pulse_finish_cbk)
3197 hperh->pwm_pulse_finish_cbk(hperh);
3198
3199 hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED;
3200 return;
3201 }
timer_handle_s
TIMER time base handle structure definition.
Definition: ald_timer.h:182
TIMER_ACTIVE_CHANNEL_CLEARED
Definition: ald_timer.h:176
timer_handle_s::delay_elapse_cbk
void(* delay_elapse_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:195
timer_handle_s::ch
timer_active_channel_t ch
Definition: ald_timer.h:185
timer_handle_s::pwm_pulse_finish_cbk
void(* pwm_pulse_finish_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:197

◆ timer_dma_period_elapse_cplt()

void timer_dma_period_elapse_cplt ( void * arg )
static

TIMER DMA Period Elapse complete callback.

Parameters
arg pointer to TIMER handle.
Return values
None

Definition at line 3224 of file ald_timer.c.

3225 {
3226 timer_handle_t *hperh = (timer_handle_t *)arg;
3227
3228 if (hperh->period_elapse_cbk)
3229 hperh->period_elapse_cbk(hperh);
3230
3231 hperh->state = TIMER_STATE_READY;
3232 return;
3233 }
TIMER_STATE_READY
Definition: ald_timer.h:162
timer_handle_s
TIMER time base handle structure definition.
Definition: ald_timer.h:182
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
timer_handle_s::period_elapse_cbk
void(* period_elapse_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:194

◆ timer_etr_set_config()

static void timer_etr_set_config | ( | TIMER_TypeDef * | TIMERx,
 |  | timer_etr_psc_t | psc,
 |  | timer_clock_polarity_t | polarity,
 |  | uint32_t | filter
 | ) |  |
static

Configures the TIMERx External Trigger (ETR).

Parameters
TIMERx | Select the TIMER peripheral
psc | The external Trigger Prescaler.
polarity | The external Trigger Polarity.
filter | External Trigger Filter. This parameter must be a value between 0x00 and 0x0F
Return values
None

Definition at line 3587 of file ald_timer.c.

3588 {
3589 MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETFLT_MSK, filter << TIMER_SMCON_ETFLT_POSS);
3590 MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPSEL_MSK, psc << TIMER_SMCON_ETPSEL_POSS);
3591 CLEAR_BIT(TIMERx->SMCON, TIMER_SMCON_ECM2EN_MSK);
3592 MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPOL_MSK, polarity << TIMER_SMCON_ETPOL_POS);
3593 return;
3594 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74

◆ timer_oc1_set_config()

static void timer_oc1_set_config | ( | TIMER_TypeDef * | TIMERx,
 |  | timer_oc_init_t * | oc_config
 | ) |  |
static

Time Ouput Compare 1 configuration.

Parameters
TIMERx | Select the TIMER peripheral
oc_config | The ouput configuration structure
Return values
None

Definition at line 3289 of file ald_timer.c.

3290 {
3291 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK);
3292 CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK);
3293 CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK);
3294 MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH1OMOD_POSS);
3295 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC1POL_POS);
3296
3297 if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_1)) {
3298 assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity));
3299 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC1NPOL_POS);
3300 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK);
3301 }
3302
3303 if (IS_TIMER_BREAK_INSTANCE(TIMERx)) {
3304 assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle));
3305 assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle));
3306
3307 MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1_MSK, oc_config->oc_idle << TIMER_CON2_OISS1_POS);
3308 MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS1N_POS);
3309 }
3310
3311 WRITE_REG(TIMERx->CCVAL1, oc_config->pulse);
3312 }
timer_oc_init_t::oc_idle
timer_oc_idle_t oc_idle
Definition: ald_timer.h:153
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_TIMER_OCNIDLE_STATE
#define IS_TIMER_OCNIDLE_STATE(x)
Definition: ald_timer.h:871
TIMER_CHANNEL_1
Definition: ald_timer.h:110
timer_oc_init_t::ocn_polarity
timer_ocn_polarity_t ocn_polarity
Definition: ald_timer.h:151
timer_oc_init_t::ocn_idle
timer_ocn_idle_t ocn_idle
Definition: ald_timer.h:154
timer_oc_init_t::oc_polarity
timer_oc_polarity_t oc_polarity
Definition: ald_timer.h:150
timer_oc_init_t::pulse
uint32_t pulse
Definition: ald_timer.h:149
timer_oc_init_t::oc_mode
timer_oc_mode_t oc_mode
Definition: ald_timer.h:148
IS_TIMER_OCIDLE_STATE
#define IS_TIMER_OCIDLE_STATE(x)
Definition: ald_timer.h:869
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_TIMER_OCN_POLARITY
#define IS_TIMER_OCN_POLARITY(x)
Definition: ald_timer.h:867

◆ timer_oc2_set_config()

static void timer_oc2_set_config | ( | TIMER_TypeDef * | TIMERx,
 |  | timer_oc_init_t * | oc_config
 | ) |  |
static

Time Ouput Compare 2 configuration.

Parameters
TIMERx | Select the TIMER peripheral
oc_config | The ouput configuration structure
Return values
None

Definition at line 3320 of file ald_timer.c.

3321 {
3322 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK);
3323 CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK);
3324 CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK);
3325 MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH2OMOD_POSS);
3326 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC2POL_POS);
3327
3328 if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_2)) {
3329 assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity));
3330 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC2NPOL_POS);
3331 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK);
3332 }
3333
3334 if (IS_TIMER_BREAK_INSTANCE(TIMERx)) {
3335 assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle));
3336 assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle));
3337
3338 MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2_MSK, oc_config->oc_idle << TIMER_CON2_OISS2_POS);
3339 MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS2N_POS);
3340 }
3341
3342 WRITE_REG(TIMERx->CCVAL2, oc_config->pulse);
3343 }
timer_oc_init_t::oc_idle
timer_oc_idle_t oc_idle
Definition: ald_timer.h:153
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_TIMER_OCNIDLE_STATE
#define IS_TIMER_OCNIDLE_STATE(x)
Definition: ald_timer.h:871
timer_oc_init_t::ocn_polarity
timer_ocn_polarity_t ocn_polarity
Definition: ald_timer.h:151
timer_oc_init_t::ocn_idle
timer_ocn_idle_t ocn_idle
Definition: ald_timer.h:154
timer_oc_init_t::oc_polarity
timer_oc_polarity_t oc_polarity
Definition: ald_timer.h:150
timer_oc_init_t::pulse
uint32_t pulse
Definition: ald_timer.h:149
timer_oc_init_t::oc_mode
timer_oc_mode_t oc_mode
Definition: ald_timer.h:148
IS_TIMER_OCIDLE_STATE
#define IS_TIMER_OCIDLE_STATE(x)
Definition: ald_timer.h:869
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_TIMER_OCN_POLARITY
#define IS_TIMER_OCN_POLARITY(x)
Definition: ald_timer.h:867
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ timer_oc3_set_config()

static void timer_oc3_set_config | ( | TIMER_TypeDef * | TIMERx,
 |  | timer_oc_init_t * | oc_config
 | ) |  |
static

Time Ouput Compare 3 configuration.

Parameters
TIMERx | Select the TIMER peripheral
oc_config | The ouput configuration structure
Return values
None

Definition at line 3351 of file ald_timer.c.

3352 {
3353 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK);
3354 CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK);
3355 CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK);
3356 MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH3OMOD_POSS);
3357 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC3POL_POS);
3358
3359 if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_3)) {
3360 assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity));
3361 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC3NPOL_POS);
3362 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK);
3363 }
3364
3365 if (IS_TIMER_BREAK_INSTANCE(TIMERx)) {
3366 assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle));
3367 assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle));
3368
3369 MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3_MSK, oc_config->oc_idle << TIMER_CON2_OISS3_POS);
3370 MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS3N_POS);
3371 }
3372
3373 WRITE_REG(TIMERx->CCVAL3, oc_config->pulse);
3374 }
timer_oc_init_t::oc_idle
timer_oc_idle_t oc_idle
Definition: ald_timer.h:153
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_CHANNEL_3
Definition: ald_timer.h:112
IS_TIMER_OCNIDLE_STATE
#define IS_TIMER_OCNIDLE_STATE(x)
Definition: ald_timer.h:871
timer_oc_init_t::ocn_polarity
timer_ocn_polarity_t ocn_polarity
Definition: ald_timer.h:151
timer_oc_init_t::ocn_idle
timer_ocn_idle_t ocn_idle
Definition: ald_timer.h:154
timer_oc_init_t::oc_polarity
timer_oc_polarity_t oc_polarity
Definition: ald_timer.h:150
timer_oc_init_t::pulse
uint32_t pulse
Definition: ald_timer.h:149
timer_oc_init_t::oc_mode
timer_oc_mode_t oc_mode
Definition: ald_timer.h:148
IS_TIMER_OCIDLE_STATE
#define IS_TIMER_OCIDLE_STATE(x)
Definition: ald_timer.h:869
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_TIMER_OCN_POLARITY
#define IS_TIMER_OCN_POLARITY(x)
Definition: ald_timer.h:867

◆ timer_oc4_set_config()

static void timer_oc4_set_config | ( | TIMER_TypeDef * | TIMERx,
 |  | timer_oc_init_t * | oc_config
 | ) |  |
static

Time Ouput Compare 4 configuration.

Parameters
TIMERx | Select the TIMER peripheral
oc_config | The ouput configuration structure
Return values
None

Definition at line 3382 of file ald_timer.c.

3383 {
3384 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK);
3385 CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK);
3386 CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK);
3387 MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH4OMOD_POSS);
3388 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC4POL_POS);
3389
3390 if (IS_TIMER_BREAK_INSTANCE(TIMERx)) {
3391 assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle));
3392 MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS4_MSK, oc_config->oc_idle << TIMER_CON2_OISS4_POS);
3393 }
3394
3395 WRITE_REG(TIMERx->CCVAL4, oc_config->pulse);
3396 }
timer_oc_init_t::oc_idle
timer_oc_idle_t oc_idle
Definition: ald_timer.h:153
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
timer_oc_init_t::oc_polarity
timer_oc_polarity_t oc_polarity
Definition: ald_timer.h:150
timer_oc_init_t::pulse
uint32_t pulse
Definition: ald_timer.h:149
timer_oc_init_t::oc_mode
timer_oc_mode_t oc_mode
Definition: ald_timer.h:148
IS_TIMER_OCIDLE_STATE
#define IS_TIMER_OCIDLE_STATE(x)
Definition: ald_timer.h:869
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74

◆ timer_slave_set_config()

static void timer_slave_set_config | ( | timer_handle_t * | hperh,
 |  | timer_slave_config_t * | config
 | ) |  |
static

Time Slave configuration.

Parameters
hperh | pointer to a timer_handle_t structure that contains the configuration information for TIMER module.
config | The slave configuration structure
Return values
None

Definition at line 3603 of file ald_timer.c.

3604 {
3605 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, config->input << TIMER_SMCON_TSSEL_POSS);
3606 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS);
3607
3608 switch (config->input) {
3609 case TIMER_TS_ETRF:
3610 timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter);
3611 break;
3612
3613 case TIMER_TS_TI1F_ED:
3614 CLEAR_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK);
3615 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->filter << TIMER_CHMR1_I1FLT_POSS);
3616 break;
3617
3618 case TIMER_TS_TI1FP1:
3619 timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter);
3620 break;
3621
3622 case TIMER_TS_TI2FP2:
3623 timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter);
3624 break;
3625
3626 default:
3627 break;
3628 }
3629 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
TIMER_TS_TI1FP1
Definition: ald_timer.h:379
timer_ti1_set_config_stage
static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter)
Configure the Polarity and Filter for TI1.
Definition: ald_timer.c:3496
TIMER_TS_TI1F_ED
Definition: ald_timer.h:378
timer_slave_config_t::mode
timer_slave_mode_t mode
Definition: ald_timer.h:388
timer_slave_config_t::psc
timer_etr_psc_t psc
Definition: ald_timer.h:391
TIMER_TS_ETRF
Definition: ald_timer.h:381
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_TS_TI2FP2
Definition: ald_timer.h:380
timer_slave_config_t::polarity
timer_clock_polarity_t polarity
Definition: ald_timer.h:390
timer_ti2_set_config_stage
static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter)
Configure the Polarity and Filter for TI2.
Definition: ald_timer.c:3532
timer_ic_polarity_t
timer_ic_polarity_t
TIMER input capture polarity.
Definition: ald_timer.h:217
timer_slave_config_t::input
timer_ts_t input
Definition: ald_timer.h:389
timer_slave_config_t::filter
uint32_t filter
Definition: ald_timer.h:392
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
timer_etr_set_config
static void timer_etr_set_config(TIMER_TypeDef *TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter)
Configures the TIMERx External Trigger (ETR).
Definition: ald_timer.c:3587

◆ timer_ti1_set_config()

static void timer_ti1_set_config | ( | TIMER_TypeDef * | TIMERx,
 |  | timer_ic_polarity_t | polarity,
 |  | timer_ic_select_t | sel,
 |  | uint32_t | filter
 | ) |  |
static

Configure the TI1 as Input.

Parameters
TIMERx | Select the TIMER peripheral.
polarity | The Input Polarity.
sel | specifies the input to be used.
filter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values
None

Definition at line 3477 of file ald_timer.c.

3479 {
3480 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK);
3481 MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, sel << TIMER_CHMR1_CC1SSEL_POSS);
3482 MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS);
3483 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS);
3484
3485 return;
3486 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74

◆ timer_ti1_set_config_stage()

static void timer_ti1_set_config_stage | ( | TIMER_TypeDef * | TIMERx,
 |  | timer_ic_polarity_t | polarity,
 |  | uint32_t | filter
 | ) |  |
static

Configure the Polarity and Filter for TI1.

Parameters
TIMERx | Select the TIMER peripheral.
polarity | The Input Polarity.
filter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values
None

Definition at line 3496 of file ald_timer.c.

3497 {
3498 MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS);
3499 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS);
3500
3501 return;
3502 }
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74

◆ timer_ti2_set_config()

static void timer_ti2_set_config | ( | TIMER_TypeDef * | TIMERx,
 |  | timer_ic_polarity_t | polarity,
 |  | timer_ic_select_t | sel,
 |  | uint32_t | filter
 | ) |  |
static

Configure the TI2 as Input.

Parameters
TIMERx | Select the TIMER peripheral.
polarity | The Input Polarity.
sel | specifies the input to be used.
filter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values
None

Definition at line 3513 of file ald_timer.c.

3515 {
3516 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK);
3517 MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, sel << TIMER_CHMR1_CC2SSEL_POSS);
3518 MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS);
3519 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS);
3520
3521 return;
3522 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74

◆ timer_ti2_set_config_stage()

static void timer_ti2_set_config_stage | ( | TIMER_TypeDef * | TIMERx,
 |  | timer_ic_polarity_t | polarity,
 |  | uint32_t | filter
 | ) |  |
static

Configure the Polarity and Filter for TI2.

Parameters
TIMERx | Select the TIMER peripheral.
polarity | The Input Polarity.
filter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values
None

Definition at line 3532 of file ald_timer.c.

3533 {
3534 MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS);
3535 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS);
3536 return;
3537 }
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74

◆ timer_ti3_set_config()

static void timer_ti3_set_config | ( | TIMER_TypeDef * | TIMERx,
 |  | timer_ic_polarity_t | polarity,
 |  | timer_ic_select_t | sel,
 |  | uint32_t | filter
 | ) |  |
static

Configure the TI3 as Input.

Parameters
TIMERx | Select the TIMER peripheral.
polarity | The Input Polarity.
sel | specifies the input to be used.
filter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values
None

Definition at line 3548 of file ald_timer.c.

3550 {
3551 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK);
3552 MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK, sel << TIMER_CHMR2_CC3SSEL_POSS);
3553 MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I3FLT_MSK, filter << TIMER_CHMR2_I3FLT_POSS);
3554 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, polarity << TIMER_CCEP_CC3POL_POS);
3555
3556 return;
3557 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74

◆ timer_ti4_set_config()

static void timer_ti4_set_config | ( | TIMER_TypeDef * | TIMERx,
 |  | timer_ic_polarity_t | polarity,
 |  | timer_ic_select_t | sel,
 |  | uint32_t | filter
 | ) |  |
static

Configure the TI4 as Input.

Parameters
TIMERx | Select the TIMER peripheral.
polarity | The Input Polarity.
sel | specifies the input to be used.
filter | Specifies the Input Capture Filter. This parameter must be a value between 0x00 and 0x0F.
Return values
None

Definition at line 3568 of file ald_timer.c.

3570 {
3571 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK);
3572 MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK, sel << TIMER_CHMR2_CC4SSEL_POSS);
3573 MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I4FLT_MSK, filter << TIMER_CHMR2_I4FLT_POSS);
3574 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, polarity << TIMER_CCEP_CC4POL_POS);
3575 return;
3576 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74


ALD User Manual: TIMER Public Functions

Modules
TIMER Public Functions
EASTSOFT ES32F3xx ALD » TIMER
Collaboration diagram for TIMER Public Functions:

Modules

TIMER Base functions
Time Base functions.
TIMER Output Compare functions
Time Output Compare functions.
TIMER PWM functions
TIMER PWM functions.
TIMER Input Capture functions
Time Input Capture functions.
TIMER One Pulse functions
Time One Pulse functions.
TIMER Encoder functions
TIMER Encoder functions.
TIMER Hall Sensor functions
TIMER Hall Sensor functions.
TIMER complementary output compare functions
TIMER complementary output compare functions.
TIMER complementary PWM functions
TIMER complementary PWM functions.
TIMER complementary one pulse functions
TIMER complementary one pulse functions.
Peripheral Control functions
Peripheral Control functions.
Peripheral State functions
Peripheral State functions.

Detailed Description


ALD User Manual: TIMER Base functions

Functions
TIMER Base functions
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Functions

Time Base functions. More...

Collaboration diagram for TIMER Base functions:

Functions

ald_status_t | ald_timer_base_init (timer_handle_t *hperh)
Initializes the TIMER Time base Unit according to the specified parameters in the timer_handle_t and create the associated handle. More...
void | ald_timer_base_reset (timer_handle_t *hperh)
Reset the TIMER base peripheral. More...
void | ald_timer_base_start (timer_handle_t *hperh)
Starts the TIMER Base generation. More...
void | ald_timer_base_stop (timer_handle_t *hperh)
Stops the TIMER Base generation. More...
void | ald_timer_base_start_by_it (timer_handle_t *hperh)
Starts the TIMER Base generation in interrupt mode. More...
void | ald_timer_base_stop_by_it (timer_handle_t *hperh)
Stops the TIMER Base generation in interrupt mode. More...
ald_status_t | ald_timer_base_start_by_dma (timer_handle_t *hperh, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER Base generation in DMA mode. More...
void | ald_timer_base_stop_by_dma (timer_handle_t *hperh)
Stops the TIMER Base generation in DMA mode. More...

Detailed Description

Time Base functions.

==============================================================================
            ##### Timer Base functions #####
==============================================================================
[..]
  This section provides functions allowing to:
  (+) Initialize and configure the TIMER base.
  (+) Reset the TIMER base.
  (+) Start the Time Base.
  (+) Stop the Time Base.
  (+) Start the Time Base and enable interrupt.
  (+) Stop the Time Base and disable interrupt.
  (+) Start the Time Base and enable DMA transfer.
  (+) Stop the Time Base and disable DMA transfer.

Function Documentation

◆ ald_timer_base_init()

ald_status_t ald_timer_base_init ( timer_handle_t * hperh )

Initializes the TIMER Time base Unit according to the specified parameters in the timer_handle_t and create the associated handle.

Parameters
hperh TIMER base handle
Return values
Status,see ald_status_t.

Definition at line 97 of file ald_timer.c.

98 {
99 if (hperh == NULL)
100 return ERROR;
101
102 assert_param(IS_TIMER_INSTANCE(hperh->perh));
103 assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode));
104 assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div));
105
106 if (hperh->state == TIMER_STATE_RESET)
107 hperh->lock = UNLOCK;
108
109 hperh->state = TIMER_STATE_BUSY;
110 timer_base_set_config(hperh->perh, &hperh->init);
111 hperh->state = TIMER_STATE_READY;
112
113 return OK;
114 }
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_STATE_RESET
Definition: ald_timer.h:161
timer_base_init_t::clk_div
timer_clock_division_t clk_div
Definition: ald_timer.h:140
IS_TIMER_COUNTER_MODE
#define IS_TIMER_COUNTER_MODE(x)
Definition: ald_timer.h:847
TIMER_STATE_READY
Definition: ald_timer.h:162
timer_handle_s::init
timer_base_init_t init
Definition: ald_timer.h:184
UNLOCK
Definition: type.h:59
TIMER_STATE_BUSY
Definition: ald_timer.h:163
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_base_set_config
static void timer_base_set_config(TIMER_TypeDef *TIMERx, timer_base_init_t *init)
Time Base configuration.
Definition: ald_timer.c:3258
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
timer_base_init_t::mode
timer_cnt_mode_t mode
Definition: ald_timer.h:138
IS_TIMER_CLOCK_DIVISION
#define IS_TIMER_CLOCK_DIVISION(x)
Definition: ald_timer.h:852
timer_handle_s::lock
lock_state_t lock
Definition: ald_timer.h:186
ERROR
Definition: utils.h:56

◆ ald_timer_base_reset()

void ald_timer_base_reset ( timer_handle_t * hperh )

Reset the TIMER base peripheral.

Parameters
hperh TIMER base handle
Return values
Status,see ald_status_t.

Definition at line 121 of file ald_timer.c.

122 {
123 assert_param(IS_TIMER_INSTANCE(hperh->perh));
124
125 hperh->state = TIMER_STATE_BUSY;
126 TIMER_DISABLE(hperh);
127 hperh->state = TIMER_STATE_RESET;
128 __UNLOCK(hperh);
129
130 return;
131 }
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_STATE_RESET
Definition: ald_timer.h:161
TIMER_STATE_BUSY
Definition: ald_timer.h:163
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187

◆ ald_timer_base_start()

void ald_timer_base_start ( timer_handle_t * hperh )

Starts the TIMER Base generation.

Parameters
hperh TIMER handle
Return values
None

Definition at line 138 of file ald_timer.c.

139 {
140 assert_param(IS_TIMER_INSTANCE(hperh->perh));
141
142 hperh->state = TIMER_STATE_BUSY;
143 TIMER_ENABLE(hperh);
144 hperh->state = TIMER_STATE_READY;
145
146 return;
147 }
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_STATE_READY
Definition: ald_timer.h:162
TIMER_ENABLE
#define TIMER_ENABLE(hperh)
Enable the TIMER peripheral.
Definition: ald_timer.h:550
TIMER_STATE_BUSY
Definition: ald_timer.h:163
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187

◆ ald_timer_base_start_by_dma()

ald_status_t ald_timer_base_start_by_dma | ( | timer_handle_t * | hperh,
 |  | uint16_t * | buf,
 |  | uint32_t | len,
 |  | uint8_t | dma_ch
 | ) |  |

Starts the TIMER Base generation in DMA mode.

Parameters
hperh | TIMER handle
buf | The source Buffer address.
len | The length of buffer to be transferred from memory to TIMER peripheral
dma_ch | Channel of DMA.
Return values
Status,see ald_status_t.

Definition at line 204 of file ald_timer.c.

206 {
207 assert_param(IS_TIMER_INSTANCE(hperh->perh));
208
209 if ((hperh->state == TIMER_STATE_BUSY))
210 return BUSY;
211 if ((hperh->state == TIMER_STATE_READY)) {
212 if (((uint32_t)buf == 0 ) || (len == 0))
213 return ERROR;
214 }
215
216 hperh->state = TIMER_STATE_BUSY;
217
218 if (hperh->hdma1.perh == NULL)
219 hperh->hdma1.perh = DMA0;
220
221 hperh->hdma1.cplt_cbk = timer_dma_period_elapse_cplt;
222 hperh->hdma1.cplt_arg = (void *)hperh;
223 hperh->hdma1.err_cbk = timer_dma_error;
224 hperh->hdma1.err_arg = (void *)hperh;
225
226 ald_dma_config_struct(&hperh->hdma1.config);
227 hperh->hdma1.config.src = (void *)buf;
228 hperh->hdma1.config.dst = (void *)&hperh->perh->AR;
229 hperh->hdma1.config.size = len;
230 hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD;
231 hperh->hdma1.config.src_inc = DMA_DATA_INC_HALFWORD;
232 hperh->hdma1.config.dst_inc = DMA_DATA_INC_NONE;
233 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_UPDATE;
234 hperh->hdma1.config.channel = dma_ch;
235
236 timer_dma_msel(hperh->perh, &hperh->hdma1.config);
237 ald_dma_config_basic(&hperh->hdma1);
238 ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, ENABLE);
239 TIMER_ENABLE(hperh);
240
241 return OK;
242 }
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ENABLE
Definition: type.h:49
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
DMA_MSIGSEL_TIMER_UPDATE
Definition: ald_dma.h:151
TIMER_STATE_READY
Definition: ald_timer.h:162
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
timer_dma_msel
static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config)
Timer DMA msel signal configuration.
Definition: ald_timer.c:3640
timer_dma_period_elapse_cplt
static void timer_dma_period_elapse_cplt(void *arg)
TIMER DMA Period Elapse complete callback.
Definition: ald_timer.c:3224
TIMER_ENABLE
#define TIMER_ENABLE(hperh)
Enable the TIMER peripheral.
Definition: ald_timer.h:550
TIMER_STATE_BUSY
Definition: ald_timer.h:163
timer_handle_s::hdma1
dma_handle_t hdma1
Definition: ald_timer.h:190
timer_dma_error
static void timer_dma_error(void *arg)
TIMER DMA error callback.
Definition: ald_timer.c:3240
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DMA_UPDATE
Definition: ald_timer.h:506
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
ald_timer_dma_req_config
void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state)
Configure DMA request source.
Definition: ald_timer.c:3050
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294

◆ ald_timer_base_start_by_it()

void ald_timer_base_start_by_it ( timer_handle_t * hperh )

Starts the TIMER Base generation in interrupt mode.

Parameters
hperh TIMER handle
Return values
None

Definition at line 170 of file ald_timer.c.

171 {
172 assert_param(IS_TIMER_INSTANCE(hperh->perh));
173
174 ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, ENABLE);
175 TIMER_ENABLE(hperh);
176
177 return;
178 }
ENABLE
Definition: type.h:49
assert_param
#define assert_param(x)
Definition: type.h:88
ald_timer_interrupt_config
void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts.
Definition: ald_timer.c:3075
TIMER_ENABLE
#define TIMER_ENABLE(hperh)
Enable the TIMER peripheral.
Definition: ald_timer.h:550
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_IT_UPDATE
Definition: ald_timer.h:492

◆ ald_timer_base_stop()

void ald_timer_base_stop ( timer_handle_t * hperh )

Stops the TIMER Base generation.

Parameters
hperh TIMER handle
Return values
None

Definition at line 154 of file ald_timer.c.

155 {
156 assert_param(IS_TIMER_INSTANCE(hperh->perh));
157
158 hperh->state = TIMER_STATE_BUSY;
159 TIMER_DISABLE(hperh);
160 hperh->state = TIMER_STATE_READY;
161
162 return;
163 }
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_STATE_READY
Definition: ald_timer.h:162
TIMER_STATE_BUSY
Definition: ald_timer.h:163
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187

◆ ald_timer_base_stop_by_dma()

void ald_timer_base_stop_by_dma ( timer_handle_t * hperh )

Stops the TIMER Base generation in DMA mode.

Parameters
hperh TIMER handle
Return values
None

Definition at line 249 of file ald_timer.c.

250 {
251 assert_param(IS_TIMER_INSTANCE(hperh->perh));
252
253 ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, DISABLE);
254 TIMER_DISABLE(hperh);
255 hperh->state = TIMER_STATE_READY;
256
257 return;
258 }
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_STATE_READY
Definition: ald_timer.h:162
DISABLE
Definition: type.h:48
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
TIMER_DMA_UPDATE
Definition: ald_timer.h:506
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
ald_timer_dma_req_config
void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state)
Configure DMA request source.
Definition: ald_timer.c:3050

◆ ald_timer_base_stop_by_it()

void ald_timer_base_stop_by_it ( timer_handle_t * hperh )

Stops the TIMER Base generation in interrupt mode.

Parameters
hperh TIMER handle
Return values
None

Definition at line 185 of file ald_timer.c.

186 {
187 assert_param(IS_TIMER_INSTANCE(hperh->perh));
188
189 ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, DISABLE);
190 TIMER_DISABLE(hperh);
191
192 return;
193 }
assert_param
#define assert_param(x)
Definition: type.h:88
DISABLE
Definition: type.h:48
ald_timer_interrupt_config
void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts.
Definition: ald_timer.c:3075
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
TIMER_IT_UPDATE
Definition: ald_timer.h:492


ALD User Manual: TIMER Output Compare functions

Functions
TIMER Output Compare functions
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Functions

Time Output Compare functions. More...

Collaboration diagram for TIMER Output Compare functions:

Functions

ald_status_t | ald_timer_oc_init (timer_handle_t *hperh)
Initializes the TIMER Output Compare according to the specified parameters in the timer_handle_t and create the associated handle. More...
void | ald_timer_oc_start (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Output Compare signal generation. More...
void | ald_timer_oc_stop (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Output Compare signal generation. More...
void | ald_timer_oc_start_by_it (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Output Compare signal generation in interrupt mode. More...
void | ald_timer_oc_stop_by_it (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Output Compare signal generation in interrupt mode. More...
ald_status_t | ald_timer_oc_start_by_dma (timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER Output Compare signal generation in DMA mode. More...
void | ald_timer_oc_stop_by_dma (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Output Compare signal generation in DMA mode. More...

Detailed Description

Time Output Compare functions.

==============================================================================
                ##### Time Output Compare functions #####
==============================================================================
[..]
  This section provides functions allowing to:
  (+) Initialize and configure the TIMER Output Compare.
  (+) Start the Time Output Compare.
  (+) Stop the Time Output Compare.
  (+) Start the Time Output Compare and enable interrupt.
  (+) Stop the Time Output Compare and disable interrupt.
  (+) Start the Time Output Compare and enable DMA transfer.
  (+) Stop the Time Output Compare and disable DMA transfer.

Function Documentation

◆ ald_timer_oc_init()

ald_status_t ald_timer_oc_init ( timer_handle_t * hperh )

Initializes the TIMER Output Compare according to the specified parameters in the timer_handle_t and create the associated handle.

Parameters
hperh TIMER handle
Return values
Status,see ald_status_t.

Definition at line 290 of file ald_timer.c.

291 {
292 return ald_timer_base_init(hperh);
293 }
ald_timer_base_init
ald_status_t ald_timer_base_init(timer_handle_t *hperh)
Initializes the TIMER Time base Unit according to the specified parameters in the timer_handle_t and ...
Definition: ald_timer.c:97

◆ ald_timer_oc_start()

void ald_timer_oc_start | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Starts the TIMER Output Compare signal generation.

Parameters
hperh TIMER handle
ch : TIMER Channel to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
  • TIMER_CHANNEL_4: TIMER Channel 4 selected
Return values
None

Definition at line 306 of file ald_timer.c.

307 {
308 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
309
310 timer_ccx_channel_cmd(hperh->perh, ch, ENABLE);
311
312 if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
313 TIMER_MOE_ENABLE(hperh);
314
315 TIMER_ENABLE(hperh);
316 return;
317 }
ENABLE
Definition: type.h:49
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_ENABLE
#define TIMER_ENABLE(hperh)
Enable the TIMER peripheral.
Definition: ald_timer.h:550
RESET
Definition: type.h:38
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
TIMER_MOE_ENABLE
#define TIMER_MOE_ENABLE(hperh)
Enable the TIMER main output.
Definition: ald_timer.h:555

◆ ald_timer_oc_start_by_dma()

ald_status_t ald_timer_oc_start_by_dma | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch,
 |  | uint16_t * | buf,
 |  | uint32_t | len,
 |  | uint8_t | dma_ch
 | ) |  |

Starts the TIMER Output Compare signal generation in DMA mode.

Parameters
hperh | TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
  • TIMER_CHANNEL_4: TIMER Channel 4 selected
buf | The source Buffer address.
len | The length of buffer to be transferred from memory to TIMER peripheral
dma_ch | Channel of DMA.
Return values
Status,see ald_status_t.

Definition at line 454 of file ald_timer.c.

456 {
457 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
458
459 if ((hperh->state == TIMER_STATE_BUSY))
460 return BUSY;
461 if ((hperh->state == TIMER_STATE_READY)) {
462 if (((uint32_t)buf == 0 ) || (len == 0))
463 return ERROR;
464 }
465
466 hperh->state = TIMER_STATE_BUSY;
467
468 if (hperh->hdma1.perh == NULL)
469 hperh->hdma1.perh = DMA0;
470
471 hperh->hdma1.cplt_cbk = timer_dma_oc_cplt;
472 hperh->hdma1.cplt_arg = (void *)hperh;
473 hperh->hdma1.err_cbk = timer_dma_error;
474 hperh->hdma1.err_arg = (void *)hperh;
475
476 ald_dma_config_struct(&hperh->hdma1.config);
477 hperh->hdma1.config.src = (void *)buf;
478 hperh->hdma1.config.size = len;
479 hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD;
480 hperh->hdma1.config.src_inc = DMA_DATA_INC_HALFWORD;
481 hperh->hdma1.config.dst_inc = DMA_DATA_INC_NONE;
482 hperh->hdma1.config.channel = dma_ch;
483
484
485 timer_dma_msel(hperh->perh, &hperh->hdma1.config);
486
487 switch (ch) {
488 case TIMER_CHANNEL_1:
489 hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL1;
490 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1;
491 ald_dma_config_basic(&hperh->hdma1);
492 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE);
493 hperh->ch = TIMER_ACTIVE_CHANNEL_1;
494 break;
495
496 case TIMER_CHANNEL_2:
497 hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL2;
498 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2;
499 ald_dma_config_basic(&hperh->hdma1);
500 ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE);
501 hperh->ch = TIMER_ACTIVE_CHANNEL_2;
502 break;
503
504 case TIMER_CHANNEL_3:
505 hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL3;
506 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH3;
507 ald_dma_config_basic(&hperh->hdma1);
508 ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE);
509 hperh->ch = TIMER_ACTIVE_CHANNEL_3;
510 break;
511
512 case TIMER_CHANNEL_4:
513 hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL4;
514 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH4;
515 ald_dma_config_basic(&hperh->hdma1);
516 ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE);
517 hperh->ch = TIMER_ACTIVE_CHANNEL_4;
518 break;
519
520 default:
521 break;
522 }
523
524 timer_ccx_channel_cmd(hperh->perh, ch, ENABLE);
525
526 if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
527 TIMER_MOE_ENABLE(hperh);
528
529 TIMER_ENABLE(hperh);
530 return OK;
531 }
DMA_MSIGSEL_TIMER_CH1
Definition: ald_dma.h:145
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ENABLE
Definition: type.h:49
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
TIMER_ACTIVE_CHANNEL_3
Definition: ald_timer.h:174
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_CHANNEL_3
Definition: ald_timer.h:112
BUSY
Definition: utils.h:57
TIMER_ACTIVE_CHANNEL_2
Definition: ald_timer.h:173
TIMER_STATE_READY
Definition: ald_timer.h:162
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
timer_dma_oc_cplt
static void timer_dma_oc_cplt(void *arg)
TIMER DMA out compare complete callback.
Definition: ald_timer.c:3189
timer_dma_msel
static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config)
Timer DMA msel signal configuration.
Definition: ald_timer.c:3640
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_ENABLE
#define TIMER_ENABLE(hperh)
Enable the TIMER peripheral.
Definition: ald_timer.h:550
TIMER_STATE_BUSY
Definition: ald_timer.h:163
RESET
Definition: type.h:38
timer_handle_s::hdma1
dma_handle_t hdma1
Definition: ald_timer.h:190
timer_dma_error
static void timer_dma_error(void *arg)
TIMER DMA error callback.
Definition: ald_timer.c:3240
DMA_MSIGSEL_TIMER_CH4
Definition: ald_dma.h:148
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DMA_CC2
Definition: ald_timer.h:508
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
DMA_MSIGSEL_TIMER_CH2
Definition: ald_dma.h:146
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
TIMER_DMA_CC3
Definition: ald_timer.h:509
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
TIMER_CHANNEL_4
Definition: ald_timer.h:113
DMA_MSIGSEL_TIMER_CH3
Definition: ald_dma.h:147
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
TIMER_ACTIVE_CHANNEL_1
Definition: ald_timer.h:172
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
timer_handle_s::ch
timer_active_channel_t ch
Definition: ald_timer.h:185
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
TIMER_ACTIVE_CHANNEL_4
Definition: ald_timer.h:175
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
ald_timer_dma_req_config
void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state)
Configure DMA request source.
Definition: ald_timer.c:3050
TIMER_DMA_CC1
Definition: ald_timer.h:507
TIMER_DMA_CC4
Definition: ald_timer.h:510
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
TIMER_MOE_ENABLE
#define TIMER_MOE_ENABLE(hperh)
Enable the TIMER main output.
Definition: ald_timer.h:555
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
TIMER_CHANNEL_2
Definition: ald_timer.h:111
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294

◆ ald_timer_oc_start_by_it()

void ald_timer_oc_start_by_it | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Starts the TIMER Output Compare signal generation in interrupt mode.

Parameters
hperh TIMER handle
ch TIMER Channel to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
  • TIMER_CHANNEL_4: TIMER Channel 4 selected
Return values
None

Definition at line 355 of file ald_timer.c.

356 {
357 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
358
359 switch (ch) {
360 case TIMER_CHANNEL_1:
361 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE);
362 break;
363
364 case TIMER_CHANNEL_2:
365 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE);
366 break;
367
368 case TIMER_CHANNEL_3:
369 ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE);
370 break;
371
372 case TIMER_CHANNEL_4:
373 ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE);
374 break;
375
376 default:
377 break;
378 }
379
380 timer_ccx_channel_cmd(hperh->perh, ch, ENABLE);
381
382 if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
383 TIMER_MOE_ENABLE(hperh);
384
385 TIMER_ENABLE(hperh);
386 return;
387 }
TIMER_IT_CC1
Definition: ald_timer.h:493
ENABLE
Definition: type.h:49
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_CHANNEL_3
Definition: ald_timer.h:112
TIMER_IT_CC4
Definition: ald_timer.h:496
ald_timer_interrupt_config
void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts.
Definition: ald_timer.c:3075
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_IT_CC2
Definition: ald_timer.h:494
TIMER_ENABLE
#define TIMER_ENABLE(hperh)
Enable the TIMER peripheral.
Definition: ald_timer.h:550
RESET
Definition: type.h:38
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
TIMER_CHANNEL_4
Definition: ald_timer.h:113
TIMER_IT_CC3
Definition: ald_timer.h:495
TIMER_MOE_ENABLE
#define TIMER_MOE_ENABLE(hperh)
Enable the TIMER main output.
Definition: ald_timer.h:555
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ ald_timer_oc_stop()

void ald_timer_oc_stop | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Stops the TIMER Output Compare signal generation.

Parameters
hperh TIMER handle
ch TIMER Channel to be disabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
  • TIMER_CHANNEL_4: TIMER Channel 4 selected
Return values
None

Definition at line 330 of file ald_timer.c.

331 {
332 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
333
334 timer_ccx_channel_cmd(hperh->perh, ch, DISABLE);
335
336 if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
337 TIMER_MOE_DISABLE(hperh);
338
339 TIMER_DISABLE(hperh);
340 hperh->state = TIMER_STATE_READY;
341 return;
342 }
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_STATE_READY
Definition: ald_timer.h:162
DISABLE
Definition: type.h:48
RESET
Definition: type.h:38
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
TIMER_MOE_DISABLE
#define TIMER_MOE_DISABLE(hperh)
Disable the TIMER main output.
Definition: ald_timer.h:572
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410

◆ ald_timer_oc_stop_by_dma()

void ald_timer_oc_stop_by_dma | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Stops the TIMER Output Compare signal generation in DMA mode.

Parameters
hperh TIMER handle
ch TIMER Channels to be disabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
  • TIMER_CHANNEL_4: TIMER Channel 4 selected
Return values
None

Definition at line 544 of file ald_timer.c.

545 {
546 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
547
548 switch (ch) {
549 case TIMER_CHANNEL_1:
550 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE);
551 break;
552
553 case TIMER_CHANNEL_2:
554 ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE);
555 break;
556
557 case TIMER_CHANNEL_3:
558 ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE);
559 break;
560
561 case TIMER_CHANNEL_4:
562 ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE);
563 break;
564
565 default:
566 break;
567 }
568
569 timer_ccx_channel_cmd(hperh->perh, ch, DISABLE);
570
571 if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
572 TIMER_MOE_DISABLE(hperh);
573
574 TIMER_DISABLE(hperh);
575 hperh->state = TIMER_STATE_READY;
576 return;
577 }
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_CHANNEL_3
Definition: ald_timer.h:112
TIMER_STATE_READY
Definition: ald_timer.h:162
DISABLE
Definition: type.h:48
TIMER_CHANNEL_1
Definition: ald_timer.h:110
RESET
Definition: type.h:38
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
TIMER_DMA_CC2
Definition: ald_timer.h:508
TIMER_MOE_DISABLE
#define TIMER_MOE_DISABLE(hperh)
Disable the TIMER main output.
Definition: ald_timer.h:572
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
TIMER_DMA_CC3
Definition: ald_timer.h:509
TIMER_CHANNEL_4
Definition: ald_timer.h:113
ald_timer_dma_req_config
void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state)
Configure DMA request source.
Definition: ald_timer.c:3050
TIMER_DMA_CC1
Definition: ald_timer.h:507
TIMER_DMA_CC4
Definition: ald_timer.h:510
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ ald_timer_oc_stop_by_it()

void ald_timer_oc_stop_by_it | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Stops the TIMER Output Compare signal generation in interrupt mode.

Parameters
hperh TIMER handle
ch TIMER Channel to be disabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
  • TIMER_CHANNEL_4: TIMER Channel 4 selected
Return values
None

Definition at line 400 of file ald_timer.c.

401 {
402 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
403
404 switch (ch) {
405 case TIMER_CHANNEL_1:
406 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE);
407 break;
408
409 case TIMER_CHANNEL_2:
410 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE);
411 break;
412
413 case TIMER_CHANNEL_3:
414 ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE);
415 break;
416
417 case TIMER_CHANNEL_4:
418 ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE);
419 break;
420
421 default:
422 break;
423 }
424
425 timer_ccx_channel_cmd(hperh->perh, ch, DISABLE);
426
427 if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
428 TIMER_MOE_DISABLE(hperh);
429
430 TIMER_DISABLE(hperh);
431 hperh->state = TIMER_STATE_READY;
432 return;
433 }
TIMER_IT_CC1
Definition: ald_timer.h:493
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_CHANNEL_3
Definition: ald_timer.h:112
TIMER_IT_CC4
Definition: ald_timer.h:496
TIMER_STATE_READY
Definition: ald_timer.h:162
DISABLE
Definition: type.h:48
ald_timer_interrupt_config
void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts.
Definition: ald_timer.c:3075
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_IT_CC2
Definition: ald_timer.h:494
RESET
Definition: type.h:38
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
TIMER_MOE_DISABLE
#define TIMER_MOE_DISABLE(hperh)
Disable the TIMER main output.
Definition: ald_timer.h:572
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
TIMER_CHANNEL_4
Definition: ald_timer.h:113
TIMER_IT_CC3
Definition: ald_timer.h:495
TIMER_CHANNEL_2
Definition: ald_timer.h:111


ALD User Manual: TIMER PWM functions

Functions
TIMER PWM functions
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Functions

TIMER PWM functions. More...

Collaboration diagram for TIMER PWM functions:

Functions

ald_status_t | ald_timer_pwm_init (timer_handle_t *hperh)
Initializes the TIMER PWM Time Base according to the specified parameters in the timer_handle_t and create the associated handle. More...
void | ald_timer_pwm_start (timer_handle_t *hperh, timer_channel_t ch)
Starts the PWM signal generation. More...
void | ald_timer_pwm_stop (timer_handle_t *hperh, timer_channel_t ch)
Stops the PWM signal generation. More...
void | ald_timer_pwm_start_by_it (timer_handle_t *hperh, timer_channel_t ch)
Starts the PWM signal generation in interrupt mode. More...
void | ald_timer_pwm_stop_by_it (timer_handle_t *hperh, timer_channel_t ch)
Stops the PWM signal generation in interrupt mode. More...
ald_status_t | ald_timer_pwm_start_by_dma (timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER PWM signal generation in DMA mode. More...
void | ald_timer_pwm_stop_by_dma (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER PWM signal generation in DMA mode. More...
void | ald_timer_pwm_set_freq (timer_handle_t *hperh, uint16_t freq)
Set the PWM freq. More...
void | ald_timer_pwm_set_duty (timer_handle_t *hperh, timer_channel_t ch, uint16_t duty)
Set the PWM duty. More...
void | ald_timer_pwm_set_input (timer_handle_t *hperh, timer_channel_t ch)
Set capture the PWM. More...

Detailed Description

TIMER PWM functions.

    ==============================================================================
    ##### Time PWM functions #####
    ==============================================================================
    [..]
        This section provides functions allowing to:
        (+) Initialize and configure the TIMER PWM.
        (+) Start the Time PWM.
        (+) Stop the Time PWM.
        (+) Start the Time PWM and enable interrupt.
        (+) Stop the Time PWM and disable interrupt.
        (+) Start the Time PWM and enable DMA transfer.
        (+) Stop the Time PWM and disable DMA transfer.

Function Documentation

◆ ald_timer_pwm_init()

ald_status_t ald_timer_pwm_init ( timer_handle_t * hperh )

Initializes the TIMER PWM Time Base according to the specified parameters in the timer_handle_t and create the associated handle.

Parameters
hperh TIMER handle
Return values
Status,see ald_status_t.

Definition at line 609 of file ald_timer.c.

610 {
611 return ald_timer_base_init(hperh);
612 }
ald_timer_base_init
ald_status_t ald_timer_base_init(timer_handle_t *hperh)
Initializes the TIMER Time base Unit according to the specified parameters in the timer_handle_t and ...
Definition: ald_timer.c:97

◆ ald_timer_pwm_set_duty()

void ald_timer_pwm_set_duty | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch,
 |  | uint16_t | duty
 | ) |  |

Set the PWM duty.

Parameters
hperh | TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
  • TIMER_CHANNEL_4: TIMER Channel 4 selected
duty | PWM duty to set
Return values
None

Definition at line 750 of file ald_timer.c.

751 {
752 uint32_t tmp = (hperh->init.period + 1) * duty / 100 - 1;
753
754 if (ch == TIMER_CHANNEL_1)
755 WRITE_REG(hperh->perh->CCVAL1, tmp);
756 else if (ch == TIMER_CHANNEL_2)
757 WRITE_REG(hperh->perh->CCVAL2, tmp);
758 else if (ch == TIMER_CHANNEL_3)
759 WRITE_REG(hperh->perh->CCVAL3, tmp);
760 else if (ch == TIMER_CHANNEL_4)
761 WRITE_REG(hperh->perh->CCVAL4, tmp);
762 else {
763 ;/* do nothing */
764 }
765 }
TIMER_CHANNEL_3
Definition: ald_timer.h:112
TIMER_CHANNEL_1
Definition: ald_timer.h:110
timer_base_init_t::period
uint32_t period
Definition: ald_timer.h:139
timer_handle_s::init
timer_base_init_t init
Definition: ald_timer.h:184
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_CHANNEL_4
Definition: ald_timer.h:113
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ ald_timer_pwm_set_freq()

void ald_timer_pwm_set_freq | ( | timer_handle_t * | hperh,
 |  | uint16_t | freq
 | ) |  |

Set the PWM freq.

Parameters
hperh | TIMER handle
freq | PWM freq to set
Return values
None

Definition at line 726 of file ald_timer.c.

727 {
728 uint32_t _arr;
729
730 if (freq == 0)
731 return;
732
733 _arr = ald_cmu_get_pclk1_clock() / (hperh->init.prescaler + 1) / freq - 1;
734 WRITE_REG(hperh->perh->AR, _arr);
735 hperh->init.period = _arr;
736 }
timer_base_init_t::period
uint32_t period
Definition: ald_timer.h:139
timer_handle_s::init
timer_base_init_t init
Definition: ald_timer.h:184
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_base_init_t::prescaler
uint32_t prescaler
Definition: ald_timer.h:137
ald_cmu_get_pclk1_clock
uint32_t ald_cmu_get_pclk1_clock(void)
Get APB1 clock.
Definition: ald_cmu.c:627
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72

◆ ald_timer_pwm_set_input()

void ald_timer_pwm_set_input | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Set capture the PWM.

Parameters
hperh TIMER handle
ch TIMER Channels to be captured the PWM This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
Return values
None

Definition at line 776 of file ald_timer.c.

777 {
778 assert_param(IS_TIMER_PWM_INPUT_INSTANCE(hperh->perh, ch));
779
780 CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK);
781 switch (ch) {
782 case TIMER_CHANNEL_1:
783 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC1SSEL_POSS);
784 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC2SSEL_POSS);
785 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS);
786 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1NPOL_POS);
787 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS);
788 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2NPOL_POS);
789 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS);
790 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS);
791 break;
792 case TIMER_CHANNEL_2:
793 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC1SSEL_POSS);
794 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC2SSEL_POSS);
795 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS);
796 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC1NPOL_POS);
797 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS);
798 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC2NPOL_POS);
799 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS);
800 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS);
801 break;
802 default:
803 break;
804 }
805
806 SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK);
807 SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2EN_MSK);
808
809 return;
810 }
TIMER_IC_SEL_DIRECT
Definition: ald_timer.h:226
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_TS_TI1FP1
Definition: ald_timer.h:379
TIMER_CHANNEL_1
Definition: ald_timer.h:110
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_TS_TI2FP2
Definition: ald_timer.h:380
TIMER_MODE_RESET
Definition: ald_timer.h:364
TIMER_IC_SEL_INDIRECT
Definition: ald_timer.h:227
TIMER_IC_POLARITY_RISE
Definition: ald_timer.h:218
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
TIMER_IC_POLARITY_FALL
Definition: ald_timer.h:219
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ ald_timer_pwm_start()

void ald_timer_pwm_start | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Starts the PWM signal generation.

Parameters
hperh TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
  • TIMER_CHANNEL_4: TIMER Channel 4 selected
Return values
None

Definition at line 625 of file ald_timer.c.

626 {
627 ald_timer_oc_start(hperh, ch);
628 return;
629 }
ald_timer_oc_start
void ald_timer_oc_start(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Output Compare signal generation.
Definition: ald_timer.c:306

◆ ald_timer_pwm_start_by_dma()

ald_status_t ald_timer_pwm_start_by_dma | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch,
 |  | uint16_t * | buf,
 |  | uint32_t | len,
 |  | uint8_t | dma_ch
 | ) |  |

Starts the TIMER PWM signal generation in DMA mode.

Parameters
hperh | TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
  • TIMER_CHANNEL_4: TIMER Channel 4 selected
buf | The source Buffer address.
len | The length of buffer to be transferred from memory to TIMER peripheral
dma_ch | Channel of DMA.
Return values
Status,see ald_status_t.

Definition at line 697 of file ald_timer.c.

699 {
700 return ald_timer_oc_start_by_dma(hperh, ch, buf, len, dma_ch);
701 }
ald_timer_oc_start_by_dma
ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER Output Compare signal generation in DMA mode.
Definition: ald_timer.c:454

◆ ald_timer_pwm_start_by_it()

void ald_timer_pwm_start_by_it | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Starts the PWM signal generation in interrupt mode.

Parameters
hperh TIMER handle
ch TIMER Channel to be disabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
  • TIMER_CHANNEL_4: TIMER Channel 4 selected
Return values
None

Definition at line 659 of file ald_timer.c.

660 {
661 ald_timer_oc_start_by_it(hperh, ch);
662 return;
663 }
ald_timer_oc_start_by_it
void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Output Compare signal generation in interrupt mode.
Definition: ald_timer.c:355

◆ ald_timer_pwm_stop()

void ald_timer_pwm_stop | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Stops the PWM signal generation.

Parameters
hperh TIMER handle
ch TIMER Channels to be disabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
  • TIMER_CHANNEL_4: TIMER Channel 4 selected
Return values
None

Definition at line 642 of file ald_timer.c.

643 {
644 ald_timer_oc_stop(hperh, ch);
645 return;
646 }
ald_timer_oc_stop
void ald_timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Output Compare signal generation.
Definition: ald_timer.c:330

◆ ald_timer_pwm_stop_by_dma()

void ald_timer_pwm_stop_by_dma | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Stops the TIMER PWM signal generation in DMA mode.

Parameters
hperh TIMER handle
ch TIMER Channels to be disabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
  • TIMER_CHANNEL_4: TIMER Channel 4 selected
Return values
None

Definition at line 714 of file ald_timer.c.

715 {
716 ald_timer_oc_stop_by_dma(hperh, ch);
717 return;
718 }
ald_timer_oc_stop_by_dma
void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Output Compare signal generation in DMA mode.
Definition: ald_timer.c:544

◆ ald_timer_pwm_stop_by_it()

void ald_timer_pwm_stop_by_it | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Stops the PWM signal generation in interrupt mode.

Parameters
hperh TIMER handle
ch TIMER Channels to be disabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
  • TIMER_CHANNEL_4: TIMER Channel 4 selected
Return values
None

Definition at line 676 of file ald_timer.c.

677 {
678 ald_timer_oc_stop_by_it(hperh, ch);
679 return;
680 }
ald_timer_oc_stop_by_it
void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Output Compare signal generation in interrupt mode.
Definition: ald_timer.c:400


ALD User Manual: TIMER Input Capture functions

Functions
TIMER Input Capture functions
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Functions

Time Input Capture functions. More...

Collaboration diagram for TIMER Input Capture functions:

Functions

ald_status_t | ald_timer_ic_init (timer_handle_t *hperh)
Initializes the TIMER Input Capture Time base according to the specified parameters in the timer_handle_t and create the associated handle. More...
void | ald_timer_ic_start (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Input Capture measurement. More...
void | ald_timer_ic_stop (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Input Capture measurement. More...
void | ald_timer_ic_start_by_it (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Input Capture measurement in interrupt mode. More...
void | ald_timer_ic_stop_by_it (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Input Capture measurement in interrupt mode. More...
ald_status_t | ald_timer_ic_start_by_dma (timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER Input Capture measurement in DMA mode. More...
void | ald_timer_ic_stop_by_dma (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Input Capture measurement in DMA mode. More...

Detailed Description

Time Input Capture functions.

 ==============================================================================
             ##### Time Input Capture functions #####
 ==============================================================================
[..]
  This section provides functions allowing to:
  (+) Initialize and configure the TIMER Input Capture.
  (+) Start the Time Input Capture.
  (+) Stop the Time Input Capture.
  (+) Start the Time Input Capture and enable interrupt.
  (+) Stop the Time Input Capture and disable interrupt.
  (+) Start the Time Input Capture and enable DMA transfer.
  (+) Stop the Time Input Capture and disable DMA transfer.

 *

Function Documentation

◆ ald_timer_ic_init()

ald_status_t ald_timer_ic_init ( timer_handle_t * hperh )

Initializes the TIMER Input Capture Time base according to the specified parameters in the timer_handle_t and create the associated handle.

Parameters
hperh TIMER handle
Return values
Status,see ald_status_t.

Definition at line 841 of file ald_timer.c.

842 {
843 return ald_timer_base_init(hperh);
844 }
ald_timer_base_init
ald_status_t ald_timer_base_init(timer_handle_t *hperh)
Initializes the TIMER Time base Unit according to the specified parameters in the timer_handle_t and ...
Definition: ald_timer.c:97

◆ ald_timer_ic_start()

void ald_timer_ic_start | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Starts the TIMER Input Capture measurement.

Parameters
hperh TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
  • TIMER_CHANNEL_4: TIMER Channel 4 selected
Return values
None

Definition at line 857 of file ald_timer.c.

858 {
859 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
860
861 timer_ccx_channel_cmd(hperh->perh, ch, ENABLE);
862 TIMER_ENABLE(hperh);
863 return;
864 }
ENABLE
Definition: type.h:49
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_ENABLE
#define TIMER_ENABLE(hperh)
Enable the TIMER peripheral.
Definition: ald_timer.h:550
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410

◆ ald_timer_ic_start_by_dma()

ald_status_t ald_timer_ic_start_by_dma | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch,
 |  | uint16_t * | buf,
 |  | uint32_t | len,
 |  | uint8_t | dma_ch
 | ) |  |

Starts the TIMER Input Capture measurement in DMA mode.

Parameters
hperh | TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
  • TIMER_CHANNEL_4: TIMER Channel 4 selected
buf | The destination Buffer address.
len | The length of buffer to be transferred TIMER peripheral to memory
dma_ch | Channel of DMA.
Return values
Status,see ald_status_t.

Definition at line 975 of file ald_timer.c.

977 {
978 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
979
980 if ((hperh->state == TIMER_STATE_BUSY))
981 return BUSY;
982 if ((hperh->state == TIMER_STATE_READY)) {
983 if (((uint32_t)buf == 0 ) || (len == 0))
984 return ERROR;
985 }
986
987 hperh->state = TIMER_STATE_BUSY;
988
989 if (hperh->perh == NULL)
990 hperh->hdma1.perh = DMA0;
991
992 hperh->hdma1.cplt_cbk = timer_dma_capture_cplt;
993 hperh->hdma1.cplt_arg = (void *)hperh;
994 hperh->hdma1.err_cbk = timer_dma_error;
995 hperh->hdma1.err_arg = (void *)hperh;
996
997 ald_dma_config_struct(&hperh->hdma1.config);
998 hperh->hdma1.config.dst = (void *)buf;
999 hperh->hdma1.config.size = len;
1000 hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD;
1001 hperh->hdma1.config.src_inc = DMA_DATA_INC_NONE;
1002 hperh->hdma1.config.dst_inc = DMA_DATA_INC_HALFWORD;
1003 hperh->hdma1.config.channel = dma_ch;
1004
1005 timer_dma_msel(hperh->perh, &hperh->hdma1.config);
1006
1007 switch (ch) {
1008 case TIMER_CHANNEL_1:
1009 hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1;
1010 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1;
1011 ald_dma_config_basic(&hperh->hdma1);
1012 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE);
1013 hperh->ch = TIMER_ACTIVE_CHANNEL_1;
1014 break;
1015
1016 case TIMER_CHANNEL_2:
1017 hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL2;
1018 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2;
1019 ald_dma_config_basic(&hperh->hdma1);
1020 ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE);
1021 hperh->ch = TIMER_ACTIVE_CHANNEL_2;
1022 break;
1023
1024 case TIMER_CHANNEL_3:
1025 hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL3;
1026 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH3;
1027 ald_dma_config_basic(&hperh->hdma1);
1028 ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE);
1029 hperh->ch = TIMER_ACTIVE_CHANNEL_3;
1030 break;
1031
1032 case TIMER_CHANNEL_4:
1033 hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL4;
1034 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH4;
1035 ald_dma_config_basic(&hperh->hdma1);
1036 ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE);
1037 hperh->ch = TIMER_ACTIVE_CHANNEL_4;
1038 break;
1039
1040 default:
1041 break;
1042 }
1043
1044 timer_ccx_channel_cmd(hperh->perh, ch, ENABLE);
1045 TIMER_ENABLE(hperh);
1046 return OK;
1047 }
DMA_MSIGSEL_TIMER_CH1
Definition: ald_dma.h:145
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ENABLE
Definition: type.h:49
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
TIMER_ACTIVE_CHANNEL_3
Definition: ald_timer.h:174
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_CHANNEL_3
Definition: ald_timer.h:112
BUSY
Definition: utils.h:57
TIMER_ACTIVE_CHANNEL_2
Definition: ald_timer.h:173
TIMER_STATE_READY
Definition: ald_timer.h:162
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
timer_dma_msel
static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config)
Timer DMA msel signal configuration.
Definition: ald_timer.c:3640
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_ENABLE
#define TIMER_ENABLE(hperh)
Enable the TIMER peripheral.
Definition: ald_timer.h:550
TIMER_STATE_BUSY
Definition: ald_timer.h:163
timer_handle_s::hdma1
dma_handle_t hdma1
Definition: ald_timer.h:190
timer_dma_error
static void timer_dma_error(void *arg)
TIMER DMA error callback.
Definition: ald_timer.c:3240
DMA_MSIGSEL_TIMER_CH4
Definition: ald_dma.h:148
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DMA_CC2
Definition: ald_timer.h:508
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
DMA_MSIGSEL_TIMER_CH2
Definition: ald_dma.h:146
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
TIMER_DMA_CC3
Definition: ald_timer.h:509
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
timer_dma_capture_cplt
static void timer_dma_capture_cplt(void *arg)
TIMER DMA Capture complete callback.
Definition: ald_timer.c:3208
TIMER_CHANNEL_4
Definition: ald_timer.h:113
DMA_MSIGSEL_TIMER_CH3
Definition: ald_dma.h:147
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
TIMER_ACTIVE_CHANNEL_1
Definition: ald_timer.h:172
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
timer_handle_s::ch
timer_active_channel_t ch
Definition: ald_timer.h:185
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
TIMER_ACTIVE_CHANNEL_4
Definition: ald_timer.h:175
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
ald_timer_dma_req_config
void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state)
Configure DMA request source.
Definition: ald_timer.c:3050
TIMER_DMA_CC1
Definition: ald_timer.h:507
TIMER_DMA_CC4
Definition: ald_timer.h:510
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
TIMER_CHANNEL_2
Definition: ald_timer.h:111
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294

◆ ald_timer_ic_start_by_it()

void ald_timer_ic_start_by_it | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Starts the TIMER Input Capture measurement in interrupt mode.

Parameters
hperh TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
  • TIMER_CHANNEL_4: TIMER Channel 4 selected
Return values
None

Definition at line 897 of file ald_timer.c.

898 {
899 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
900
901 switch (ch) {
902 case TIMER_CHANNEL_1:
903 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE);
904 break;
905 case TIMER_CHANNEL_2:
906 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE);
907 break;
908 case TIMER_CHANNEL_3:
909 ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE);
910 break;
911 case TIMER_CHANNEL_4:
912 ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE);
913 break;
914 default:
915 break;
916 }
917
918 timer_ccx_channel_cmd(hperh->perh, ch, ENABLE);
919 TIMER_ENABLE(hperh);
920 return;
921 }
TIMER_IT_CC1
Definition: ald_timer.h:493
ENABLE
Definition: type.h:49
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_CHANNEL_3
Definition: ald_timer.h:112
TIMER_IT_CC4
Definition: ald_timer.h:496
ald_timer_interrupt_config
void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts.
Definition: ald_timer.c:3075
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_IT_CC2
Definition: ald_timer.h:494
TIMER_ENABLE
#define TIMER_ENABLE(hperh)
Enable the TIMER peripheral.
Definition: ald_timer.h:550
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
TIMER_CHANNEL_4
Definition: ald_timer.h:113
TIMER_IT_CC3
Definition: ald_timer.h:495
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ ald_timer_ic_stop()

void ald_timer_ic_stop | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Stops the TIMER Input Capture measurement.

Parameters
hperh TIMER handle
ch TIMER Channels to be disabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
  • TIMER_CHANNEL_4: TIMER Channel 4 selected
Return values
None

Definition at line 877 of file ald_timer.c.

878 {
879 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
880
881 timer_ccx_channel_cmd(hperh->perh, ch, DISABLE);
882 TIMER_DISABLE(hperh);
883 return;
884 }
assert_param
#define assert_param(x)
Definition: type.h:88
DISABLE
Definition: type.h:48
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410

◆ ald_timer_ic_stop_by_dma()

void ald_timer_ic_stop_by_dma | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Stops the TIMER Input Capture measurement in DMA mode.

Parameters
hperh TIMER handle
ch TIMER Channels to be disabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
  • TIMER_CHANNEL_4: TIMER Channel 4 selected
Return values
None

Definition at line 1060 of file ald_timer.c.

1061 {
1062 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
1063
1064 switch (ch) {
1065 case TIMER_CHANNEL_1:
1066 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE);
1067 break;
1068 case TIMER_CHANNEL_2:
1069 ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE);
1070 break;
1071 case TIMER_CHANNEL_3:
1072 ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE);
1073 break;
1074 case TIMER_CHANNEL_4:
1075 ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE);
1076 break;
1077 default:
1078 break;
1079 }
1080
1081 timer_ccx_channel_cmd(hperh->perh, ch, DISABLE);
1082 TIMER_DISABLE(hperh);
1083 hperh->state = TIMER_STATE_READY;
1084 return;
1085 }
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_CHANNEL_3
Definition: ald_timer.h:112
TIMER_STATE_READY
Definition: ald_timer.h:162
DISABLE
Definition: type.h:48
TIMER_CHANNEL_1
Definition: ald_timer.h:110
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
TIMER_DMA_CC2
Definition: ald_timer.h:508
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
TIMER_DMA_CC3
Definition: ald_timer.h:509
TIMER_CHANNEL_4
Definition: ald_timer.h:113
ald_timer_dma_req_config
void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state)
Configure DMA request source.
Definition: ald_timer.c:3050
TIMER_DMA_CC1
Definition: ald_timer.h:507
TIMER_DMA_CC4
Definition: ald_timer.h:510
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ ald_timer_ic_stop_by_it()

void ald_timer_ic_stop_by_it | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Stops the TIMER Input Capture measurement in interrupt mode.

Parameters
hperh TIMER handle
ch TIMER Channels to be disabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
  • TIMER_CHANNEL_4: TIMER Channel 4 selected
Return values
None

Definition at line 934 of file ald_timer.c.

935 {
936 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
937
938 switch (ch) {
939 case TIMER_CHANNEL_1:
940 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE);
941 break;
942 case TIMER_CHANNEL_2:
943 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE);
944 break;
945 case TIMER_CHANNEL_3:
946 ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE);
947 break;
948 case TIMER_CHANNEL_4:
949 ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE);
950 break;
951 default:
952 break;
953 }
954
955 timer_ccx_channel_cmd(hperh->perh, ch, DISABLE);
956 TIMER_DISABLE(hperh);
957 return;
958 }
TIMER_IT_CC1
Definition: ald_timer.h:493
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_CHANNEL_3
Definition: ald_timer.h:112
TIMER_IT_CC4
Definition: ald_timer.h:496
DISABLE
Definition: type.h:48
ald_timer_interrupt_config
void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts.
Definition: ald_timer.c:3075
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_IT_CC2
Definition: ald_timer.h:494
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
TIMER_CHANNEL_4
Definition: ald_timer.h:113
TIMER_IT_CC3
Definition: ald_timer.h:495
TIMER_CHANNEL_2
Definition: ald_timer.h:111


ALD User Manual: TIMER One Pulse functions

Functions
TIMER One Pulse functions
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Functions

Time One Pulse functions. More...

Collaboration diagram for TIMER One Pulse functions:

Functions

ald_status_t | ald_timer_one_pulse_init (timer_handle_t *hperh, timer_op_mode_t mode)
Initializes the TIMER One Pulse Time Base according to the specified parameters in the timer_handle_t and create the associated handle. More...
void | ald_timer_one_pulse_start (timer_handle_t *hperh, timer_op_output_channel_t ch)
Starts the TIMER One Pulse signal generation. More...
void | ald_timer_one_pulse_stop (timer_handle_t *hperh, timer_op_output_channel_t ch)
Stops the TIMER One Pulse signal generation. More...
void | ald_timer_one_pulse_start_by_it (timer_handle_t *hperh, timer_op_output_channel_t ch)
Starts the TIMER One Pulse signal generation in interrupt mode. More...
void | ald_timer_one_pulse_stop_by_it (timer_handle_t *hperh, timer_op_output_channel_t ch)
Stops the TIMER One Pulse signal generation in interrupt mode. More...

Detailed Description

Time One Pulse functions.

==============================================================================
                      ##### Time One Pulse functions #####
==============================================================================
[..]
  This section provides functions allowing to:
  (+) Initialize and configure the TIMER One Pulse.
  (+) Start the Time One Pulse.
  (+) Stop the Time One Pulse.
  (+) Start the Time One Pulse and enable interrupt.
  (+) Stop the Time One Pulse and disable interrupt.
  (+) Start the Time One Pulse and enable DMA transfer.
  (+) Stop the Time One Pulse and disable DMA transfer.

*

Function Documentation

◆ ald_timer_one_pulse_init()

ald_status_t ald_timer_one_pulse_init | ( | timer_handle_t * | hperh,
 |  | timer_op_mode_t | mode
 | ) |  |

Initializes the TIMER One Pulse Time Base according to the specified parameters in the timer_handle_t and create the associated handle.

Parameters
hperh TIMER handle
mode Select the One pulse mode. This parameter can be one of the following values:
  • TIMER_OP_MODE_SINGLE: Only one pulse will be generated.
  • TIMER_OP_MODE_REPEAT: Repetitive pulses wil be generated.
Return values
Status,see ald_status_t.

Definition at line 1121 of file ald_timer.c.

1122 {
1123 if (hperh == NULL)
1124 return ERROR;
1125
1126 assert_param(IS_TIMER_INSTANCE(hperh->perh));
1127 assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode));
1128 assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div));
1129 assert_param(IS_TIMER_OP_MODE(mode));
1130
1131 if (hperh->state == TIMER_STATE_RESET)
1132 hperh->lock = UNLOCK;
1133
1134 hperh->state = TIMER_STATE_BUSY;
1135 timer_base_set_config(hperh->perh, &hperh->init);
1136 MODIFY_REG(hperh->perh->CON1, TIMER_CON1_SPMEN_MSK, mode << TIMER_CON1_SPMEN_POS);
1137 hperh->state = TIMER_STATE_READY;
1138
1139 return OK;
1140 }
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_STATE_RESET
Definition: ald_timer.h:161
timer_base_init_t::clk_div
timer_clock_division_t clk_div
Definition: ald_timer.h:140
IS_TIMER_COUNTER_MODE
#define IS_TIMER_COUNTER_MODE(x)
Definition: ald_timer.h:847
TIMER_STATE_READY
Definition: ald_timer.h:162
timer_handle_s::init
timer_base_init_t init
Definition: ald_timer.h:184
UNLOCK
Definition: type.h:59
TIMER_STATE_BUSY
Definition: ald_timer.h:163
IS_TIMER_OP_MODE
#define IS_TIMER_OP_MODE(x)
Definition: ald_timer.h:878
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_base_set_config
static void timer_base_set_config(TIMER_TypeDef *TIMERx, timer_base_init_t *init)
Time Base configuration.
Definition: ald_timer.c:3258
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
timer_base_init_t::mode
timer_cnt_mode_t mode
Definition: ald_timer.h:138
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_TIMER_CLOCK_DIVISION
#define IS_TIMER_CLOCK_DIVISION(x)
Definition: ald_timer.h:852
timer_handle_s::lock
lock_state_t lock
Definition: ald_timer.h:186
ERROR
Definition: utils.h:56

◆ ald_timer_one_pulse_start()

void ald_timer_one_pulse_start | ( | timer_handle_t * | hperh,
 |  | timer_op_output_channel_t | ch
 | ) |  |

Starts the TIMER One Pulse signal generation.

Parameters
hperh TIMER One Pulse handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected
Return values
None

Definition at line 1151 of file ald_timer.c.

1152 {
1153 /* Enable the Capture compare and the Input Capture channels
1154 * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2)
1155 * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and
1156 * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output
1157 * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together
1158 */
1159 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1160 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
1161
1162 if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
1163 TIMER_MOE_ENABLE(hperh);
1164
1165 return;
1166 }
ENABLE
Definition: type.h:49
TIMER_CHANNEL_1
Definition: ald_timer.h:110
RESET
Definition: type.h:38
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
TIMER_MOE_ENABLE
#define TIMER_MOE_ENABLE(hperh)
Enable the TIMER main output.
Definition: ald_timer.h:555
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ ald_timer_one_pulse_start_by_it()

void ald_timer_one_pulse_start_by_it | ( | timer_handle_t * | hperh,
 |  | timer_op_output_channel_t | ch
 | ) |  |

Starts the TIMER One Pulse signal generation in interrupt mode.

Parameters
hperh TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected
Return values
None

Definition at line 1198 of file ald_timer.c.

1199 {
1200 /* Enable the Capture compare and the Input Capture channels
1201 * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2)
1202 * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and
1203 * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output
1204 * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together
1205 */
1206 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE);
1207 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE);
1208 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1209 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
1210
1211 if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
1212 TIMER_MOE_ENABLE(hperh);
1213
1214 return;
1215 }
TIMER_IT_CC1
Definition: ald_timer.h:493
ENABLE
Definition: type.h:49
ald_timer_interrupt_config
void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts.
Definition: ald_timer.c:3075
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_IT_CC2
Definition: ald_timer.h:494
RESET
Definition: type.h:38
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
TIMER_MOE_ENABLE
#define TIMER_MOE_ENABLE(hperh)
Enable the TIMER main output.
Definition: ald_timer.h:555
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ ald_timer_one_pulse_stop()

void ald_timer_one_pulse_stop | ( | timer_handle_t * | hperh,
 |  | timer_op_output_channel_t | ch
 | ) |  |

Stops the TIMER One Pulse signal generation.

Parameters
hperh TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected
Return values
None

Definition at line 1177 of file ald_timer.c.

1178 {
1179 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1180 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
1181
1182 if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
1183 TIMER_MOE_DISABLE(hperh);
1184
1185 TIMER_DISABLE(hperh);
1186 return;
1187 }
DISABLE
Definition: type.h:48
TIMER_CHANNEL_1
Definition: ald_timer.h:110
RESET
Definition: type.h:38
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
TIMER_MOE_DISABLE
#define TIMER_MOE_DISABLE(hperh)
Disable the TIMER main output.
Definition: ald_timer.h:572
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ ald_timer_one_pulse_stop_by_it()

void ald_timer_one_pulse_stop_by_it | ( | timer_handle_t * | hperh,
 |  | timer_op_output_channel_t | ch
 | ) |  |

Stops the TIMER One Pulse signal generation in interrupt mode.

Parameters
hperh : TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_OP_OUTPUT_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_OP_OUTPUT_CHANNEL_2: TIMER Channel 2 selected
Return values
None

Definition at line 1226 of file ald_timer.c.

1227 {
1228 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE);
1229 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE);
1230 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1231 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
1232
1233 if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
1234 TIMER_MOE_DISABLE(hperh);
1235
1236 TIMER_DISABLE(hperh);
1237 return;
1238 }
TIMER_IT_CC1
Definition: ald_timer.h:493
DISABLE
Definition: type.h:48
ald_timer_interrupt_config
void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts.
Definition: ald_timer.c:3075
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_IT_CC2
Definition: ald_timer.h:494
RESET
Definition: type.h:38
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
TIMER_MOE_DISABLE
#define TIMER_MOE_DISABLE(hperh)
Disable the TIMER main output.
Definition: ald_timer.h:572
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
TIMER_CHANNEL_2
Definition: ald_timer.h:111


ALD User Manual: TIMER Encoder functions

Functions
TIMER Encoder functions
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Functions

TIMER Encoder functions. More...

Collaboration diagram for TIMER Encoder functions:

Functions

ald_status_t | ald_timer_encoder_init (timer_handle_t *hperh, timer_encoder_init_t *config)
Initializes the TIMER Encoder Interface and create the associated handle. More...
void | ald_timer_encoder_start (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Encoder Interface. More...
void | ald_timer_encoder_stop (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Encoder Interface. More...
void | ald_timer_encoder_start_by_it (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Encoder Interface in interrupt mode. More...
void | ald_timer_encoder_stop_by_it (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Encoder Interface in interrupt mode. More...
ald_status_t | ald_timer_encoder_start_by_dma (timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf1, uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2)
Starts the TIMER Encoder Interface in DMA mode. More...
void | ald_timer_encoder_stop_by_dma (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Encoder Interface in DMA mode. More...

Detailed Description

TIMER Encoder functions.

      ==============================================================================
      ##### Time Encoder functions #####
      ==============================================================================
      [..]
        This section provides functions allowing to:
        (+) Initialize and configure the TIMER Encoder.
        (+) Start the Time Encoder.
        (+) Stop the Time Encoder.
        (+) Start the Time Encoder and enable interrupt.
        (+) Stop the Time Encoder and disable interrupt.
        (+) Start the Time Encoder and enable DMA transfer.
        (+) Stop the Time Encoder and disable DMA transfer.

*

Function Documentation

◆ ald_timer_encoder_init()

ald_status_t ald_timer_encoder_init | ( | timer_handle_t * | hperh,
 |  | timer_encoder_init_t * | config
 | ) |  |

Initializes the TIMER Encoder Interface and create the associated handle.

Parameters
hperh | TIMER handle
config | TIMER Encoder Interface configuration structure
Return values
Status,see ald_status_t.

Definition at line 1269 of file ald_timer.c.

1270 {
1271 if (hperh == NULL)
1272 return ERROR;
1273
1274 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
1275 assert_param(IS_TIMER_ENCODER_MODE(config->mode));
1276 assert_param(IS_TIMER_IC_POLARITY(config->ic1_polarity));
1277 assert_param(IS_TIMER_IC_POLARITY(config->ic2_polarity));
1278 assert_param(IS_TIMER_IC_SELECT(config->ic1_sel));
1279 assert_param(IS_TIMER_IC_SELECT(config->ic2_sel));
1280 assert_param(IS_TIMER_IC_PSC(config->ic1_psc));
1281 assert_param(IS_TIMER_IC_PSC(config->ic2_psc));
1282 assert_param(IS_TIMER_IC_FILTER(config->ic1_filter));
1283 assert_param(IS_TIMER_IC_FILTER(config->ic2_filter));
1284
1285 if (hperh->state == TIMER_STATE_RESET)
1286 hperh->lock = UNLOCK;
1287
1288 hperh->state = TIMER_STATE_BUSY;
1289 CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK);
1290 timer_base_set_config(hperh->perh, &hperh->init);
1291
1292 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS);
1293 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, config->ic1_sel << TIMER_CHMR1_CC1SSEL_POSS);
1294 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, config->ic2_sel << TIMER_CHMR1_CC2SSEL_POSS);
1295 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->ic1_psc << TIMER_CHMR1_IC1PRES_POSS);
1296 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->ic2_psc << TIMER_CHMR1_IC2PRES_POSS);
1297 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->ic1_filter << TIMER_CHMR1_I1FLT_POSS);
1298 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I2FLT_MSK, config->ic2_filter << TIMER_CHMR1_I2FLT_POSS);
1299 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, (config->ic1_polarity & 0x1) << TIMER_CCEP_CC1POL_POS);
1300 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, ((config->ic1_polarity >> 1) & 0x1) << TIMER_CCEP_CC1NPOL_POS);
1301 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, (config->ic2_polarity & 0x1) << TIMER_CCEP_CC2POL_POS);
1302 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, ((config->ic2_polarity >> 1) & 0x1) << TIMER_CCEP_CC2NPOL_POS);
1303
1304 hperh->state = TIMER_STATE_READY;
1305 return OK;
1306 }
OK
Definition: utils.h:55
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_STATE_RESET
Definition: ald_timer.h:161
TIMER_STATE_READY
Definition: ald_timer.h:162
timer_encoder_init_t::ic1_polarity
timer_ic_polarity_t ic1_polarity
Definition: ald_timer.h:246
timer_handle_s::init
timer_base_init_t init
Definition: ald_timer.h:184
UNLOCK
Definition: type.h:59
TIMER_STATE_BUSY
Definition: ald_timer.h:163
timer_encoder_init_t::ic2_filter
uint32_t ic2_filter
Definition: ald_timer.h:253
timer_encoder_init_t::ic1_filter
uint32_t ic1_filter
Definition: ald_timer.h:249
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_encoder_init_t::mode
timer_encoder_mode_t mode
Definition: ald_timer.h:245
timer_encoder_init_t::ic2_sel
timer_ic_select_t ic2_sel
Definition: ald_timer.h:251
timer_base_set_config
static void timer_base_set_config(TIMER_TypeDef *TIMERx, timer_base_init_t *init)
Time Base configuration.
Definition: ald_timer.c:3258
IS_TIMER_IC_FILTER
#define IS_TIMER_IC_FILTER(x)
Definition: ald_timer.h:894
IS_TIMER_IC_SELECT
#define IS_TIMER_IC_SELECT(x)
Definition: ald_timer.h:887
IS_TIMER_IC_PSC
#define IS_TIMER_IC_PSC(x)
Definition: ald_timer.h:890
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
timer_encoder_init_t::ic1_psc
timer_ic_prescaler_t ic1_psc
Definition: ald_timer.h:248
IS_TIMER_ENCODER_MODE
#define IS_TIMER_ENCODER_MODE(x)
Definition: ald_timer.h:882
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
timer_encoder_init_t::ic2_psc
timer_ic_prescaler_t ic2_psc
Definition: ald_timer.h:252
timer_encoder_init_t::ic2_polarity
timer_ic_polarity_t ic2_polarity
Definition: ald_timer.h:250
timer_handle_s::lock
lock_state_t lock
Definition: ald_timer.h:186
IS_TIMER_IC_POLARITY
#define IS_TIMER_IC_POLARITY(x)
Definition: ald_timer.h:885
ERROR
Definition: utils.h:56
timer_encoder_init_t::ic1_sel
timer_ic_select_t ic1_sel
Definition: ald_timer.h:247

◆ ald_timer_encoder_start()

void ald_timer_encoder_start | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Starts the TIMER Encoder Interface.

Parameters
hperh TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected
Return values
None

Definition at line 1318 of file ald_timer.c.

1319 {
1320 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
1321
1322 switch (ch) {
1323 case TIMER_CHANNEL_1:
1324 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1325 break;
1326 case TIMER_CHANNEL_2:
1327 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
1328 break;
1329 default:
1330 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1331 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
1332 break;
1333 }
1334
1335 TIMER_ENABLE(hperh);
1336 return;
1337 }
ENABLE
Definition: type.h:49
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_ENABLE
#define TIMER_ENABLE(hperh)
Enable the TIMER peripheral.
Definition: ald_timer.h:550
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ ald_timer_encoder_start_by_dma()

ald_status_t ald_timer_encoder_start_by_dma | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch,
 |  | uint16_t * | buf1,
 |  | uint16_t * | buf2,
 |  | uint32_t | len,
 |  | uint8_t | dma_ch1,
 |  | uint8_t | dma_ch2
 | ) |  |

Starts the TIMER Encoder Interface in DMA mode.

Parameters
hperh | TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected
buf1 | The destination Buffer address. Reading data from CCR1.
buf2 | The destination Buffer address. Reading data from CCR2.
len | The length of buffer to be transferred TIMER peripheral to memory
dma_ch1 | Channel of DMA.
dma_ch2 | Channel of DMA.
Return values
Status,see ald_status_t.

Definition at line 1457 of file ald_timer.c.

1460 {
1461 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
1462
1463 if ((hperh->state == TIMER_STATE_BUSY))
1464 return BUSY;
1465 if ((hperh->state == TIMER_STATE_READY)) {
1466 if (((uint32_t)buf1 == 0) || ((uint32_t)buf2 == 0) || (len == 0))
1467 return ERROR;
1468 }
1469
1470 if (hperh->hdma1.perh == NULL)
1471 hperh->hdma1.perh = DMA0;
1472 if (hperh->hdma2.perh == NULL)
1473 hperh->hdma2.perh = DMA0;
1474
1475 hperh->state = TIMER_STATE_BUSY;
1476 hperh->hdma1.cplt_cbk = timer_dma_capture_cplt;
1477 hperh->hdma1.cplt_arg = (void *)hperh;
1478 hperh->hdma1.err_cbk = timer_dma_error;
1479 hperh->hdma1.err_arg = (void *)hperh;
1480
1481 ald_dma_config_struct(&hperh->hdma1.config);
1482 hperh->hdma1.config.size = len;
1483 hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD;
1484 hperh->hdma1.config.src_inc = DMA_DATA_INC_NONE;
1485 hperh->hdma1.config.dst_inc = DMA_DATA_INC_HALFWORD;
1486
1487 timer_dma_msel(hperh->perh, &hperh->hdma1.config);
1488
1489 switch (ch) {
1490 case TIMER_CHANNEL_1:
1491 hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1;
1492 hperh->hdma1.config.dst = (void *)buf1;
1493 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1;
1494 hperh->hdma1.config.channel = dma_ch1;
1495 ald_dma_config_basic(&hperh->hdma1);
1496 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE);
1497 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1498 TIMER_ENABLE(hperh);
1499 break;
1500
1501 case TIMER_CHANNEL_2:
1502 hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL2;
1503 hperh->hdma1.config.dst = (void *)buf2;
1504 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2;
1505 hperh->hdma1.config.channel = dma_ch2;
1506 ald_dma_config_basic(&hperh->hdma1);
1507 ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE);
1508 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
1509 TIMER_ENABLE(hperh);
1510 break;
1511
1512 default:
1513 hperh->hdma2.cplt_cbk = timer_dma_capture_cplt;
1514 hperh->hdma2.cplt_arg = (void *)hperh;
1515 hperh->hdma2.err_cbk = timer_dma_error;
1516 hperh->hdma2.err_arg = (void *)hperh;
1517 memcpy(&hperh->hdma2.config, &hperh->hdma1.config, sizeof(dma_config_t));
1518
1519 hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1;
1520 hperh->hdma1.config.dst = (void *)buf1;
1521 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1;
1522 hperh->hdma1.config.channel = dma_ch1;
1523 ald_dma_config_basic(&hperh->hdma1);
1524 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE);
1525
1526 hperh->hdma2.config.src = (void *)&hperh->perh->CCVAL2;
1527 hperh->hdma2.config.dst = (void *)buf2;
1528 hperh->hdma2.config.msigsel = DMA_MSIGSEL_TIMER_CH2;
1529 hperh->hdma2.config.channel = dma_ch2;
1530 ald_dma_config_basic(&hperh->hdma2);
1531 ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE);
1532
1533 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1534 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
1535 TIMER_ENABLE(hperh);
1536 break;
1537 }
1538
1539 return OK;
1540 }
DMA_MSIGSEL_TIMER_CH1
Definition: ald_dma.h:145
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ENABLE
Definition: type.h:49
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
timer_handle_s::hdma2
dma_handle_t hdma2
Definition: ald_timer.h:191
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
TIMER_STATE_READY
Definition: ald_timer.h:162
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
timer_dma_msel
static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config)
Timer DMA msel signal configuration.
Definition: ald_timer.c:3640
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_ENABLE
#define TIMER_ENABLE(hperh)
Enable the TIMER peripheral.
Definition: ald_timer.h:550
TIMER_STATE_BUSY
Definition: ald_timer.h:163
timer_handle_s::hdma1
dma_handle_t hdma1
Definition: ald_timer.h:190
timer_dma_error
static void timer_dma_error(void *arg)
TIMER DMA error callback.
Definition: ald_timer.c:3240
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
dma_config_t
DMA channal configure structure.
Definition: ald_dma.h:277
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DMA_CC2
Definition: ald_timer.h:508
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
DMA_MSIGSEL_TIMER_CH2
Definition: ald_dma.h:146
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
timer_dma_capture_cplt
static void timer_dma_capture_cplt(void *arg)
TIMER DMA Capture complete callback.
Definition: ald_timer.c:3208
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
ald_timer_dma_req_config
void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state)
Configure DMA request source.
Definition: ald_timer.c:3050
TIMER_DMA_CC1
Definition: ald_timer.h:507
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
TIMER_CHANNEL_2
Definition: ald_timer.h:111
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294

◆ ald_timer_encoder_start_by_it()

void ald_timer_encoder_start_by_it | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Starts the TIMER Encoder Interface in interrupt mode.

Parameters
hperh TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected
Return values
None

Definition at line 1380 of file ald_timer.c.

1381 {
1382 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
1383
1384 switch (ch) {
1385 case TIMER_CHANNEL_1:
1386 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1387 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE);
1388 break;
1389 case TIMER_CHANNEL_2:
1390 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
1391 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE);
1392 break;
1393 default:
1394 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1395 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
1396 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE);
1397 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE);
1398 break;
1399 }
1400
1401 TIMER_ENABLE(hperh);
1402 return;
1403 }
TIMER_IT_CC1
Definition: ald_timer.h:493
ENABLE
Definition: type.h:49
assert_param
#define assert_param(x)
Definition: type.h:88
ald_timer_interrupt_config
void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts.
Definition: ald_timer.c:3075
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_IT_CC2
Definition: ald_timer.h:494
TIMER_ENABLE
#define TIMER_ENABLE(hperh)
Enable the TIMER peripheral.
Definition: ald_timer.h:550
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ ald_timer_encoder_stop()

void ald_timer_encoder_stop | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Stops the TIMER Encoder Interface.

Parameters
hperh TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected
Return values
None

Definition at line 1349 of file ald_timer.c.

1350 {
1351 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
1352
1353 switch (ch) {
1354 case TIMER_CHANNEL_1:
1355 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1356 break;
1357 case TIMER_CHANNEL_2:
1358 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
1359 break;
1360 default:
1361 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1362 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
1363 break;
1364 }
1365
1366 TIMER_DISABLE(hperh);
1367 return;
1368 }
assert_param
#define assert_param(x)
Definition: type.h:88
DISABLE
Definition: type.h:48
TIMER_CHANNEL_1
Definition: ald_timer.h:110
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ ald_timer_encoder_stop_by_dma()

void ald_timer_encoder_stop_by_dma | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Stops the TIMER Encoder Interface in DMA mode.

Parameters
hperh TIMER handle
ch TIMER Channels to be disabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected
Return values
None

Definition at line 1552 of file ald_timer.c.

1553 {
1554 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
1555
1556 switch (ch) {
1557 case TIMER_CHANNEL_1:
1558 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1559 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE);
1560 break;
1561 case TIMER_CHANNEL_2:
1562 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
1563 ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE);
1564 break;
1565 default:
1566 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1567 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
1568 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE);
1569 ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE);
1570 break;
1571 }
1572
1573 TIMER_DISABLE(hperh);
1574 hperh->state = TIMER_STATE_READY;
1575 return;
1576 }
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_STATE_READY
Definition: ald_timer.h:162
DISABLE
Definition: type.h:48
TIMER_CHANNEL_1
Definition: ald_timer.h:110
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
TIMER_DMA_CC2
Definition: ald_timer.h:508
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
ald_timer_dma_req_config
void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state)
Configure DMA request source.
Definition: ald_timer.c:3050
TIMER_DMA_CC1
Definition: ald_timer.h:507
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ ald_timer_encoder_stop_by_it()

void ald_timer_encoder_stop_by_it | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Stops the TIMER Encoder Interface in interrupt mode.

Parameters
hperh TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_ALL: TIMER Channel 1 and TIMER Channel 2 are selected
Return values
None

Definition at line 1415 of file ald_timer.c.

1416 {
1417 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
1418
1419 switch (ch) {
1420 case TIMER_CHANNEL_1:
1421 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1422 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE);
1423 break;
1424 case TIMER_CHANNEL_2:
1425 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
1426 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE);
1427 break;
1428 default:
1429 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1430 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
1431 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE);
1432 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE);
1433 break;
1434 }
1435
1436 TIMER_DISABLE(hperh);
1437 hperh->state = TIMER_STATE_READY;
1438 return;
1439 }
TIMER_IT_CC1
Definition: ald_timer.h:493
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_STATE_READY
Definition: ald_timer.h:162
DISABLE
Definition: type.h:48
ald_timer_interrupt_config
void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts.
Definition: ald_timer.c:3075
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_IT_CC2
Definition: ald_timer.h:494
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
TIMER_CHANNEL_2
Definition: ald_timer.h:111


ALD User Manual: TIMER Hall Sensor functions

Functions
TIMER Hall Sensor functions
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Functions

TIMER Hall Sensor functions. More...

Collaboration diagram for TIMER Hall Sensor functions:

Functions

ald_status_t | ald_timer_hall_sensor_init (timer_handle_t *hperh, timer_hall_sensor_init_t *config)
Initializes the TIMER Encoder Interface and create the associated handle. More...
void | ald_timer_hall_sensor_start (timer_handle_t *hperh)
Starts the TIMER hall sensor interface. More...
void | ald_timer_hall_sensor_stop (timer_handle_t *hperh)
Stops the TIMER hall sensor interface. More...
void | ald_timer_hall_sensor_start_by_it (timer_handle_t *hperh)
Starts the TIMER hall sensor interface in interrupt mode. More...
void | ald_timer_hall_sensor_stop_by_it (timer_handle_t *hperh)
Stops the TIMER hall sensor interface in interrupt mode. More...
ald_status_t | ald_timer_hall_sensor_start_by_dma (timer_handle_t *hperh, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER hall sensor interface in DMA mode. More...
void | ald_timer_hall_sensor_stop_by_dma (timer_handle_t *hperh)
Stops the TIMER hall sensor interface in DMA mode. More...

Detailed Description

TIMER Hall Sensor functions.

      ==============================================================================
      ##### Time Hall Sensor functions #####
      ==============================================================================
      [..]
        This section provides functions allowing to:
        (+) Initialize and configure the TIMER hall sensor.
        (+) Start the hall sensor.
        (+) Stop the hall sensor.
        (+) Start the hall sensor and enable interrupt.
        (+) Stop the hall sensor and disable interrupt.
        (+) Start the hall sensor and enable DMA transfer.
        (+) Stop the hal sensor and disable DMA transfer.

*

Function Documentation

◆ ald_timer_hall_sensor_init()

ald_status_t ald_timer_hall_sensor_init | ( | timer_handle_t * | hperh,
 |  | timer_hall_sensor_init_t * | config
 | ) |  |

Initializes the TIMER Encoder Interface and create the associated handle.

Parameters
hperh | TIMER handle
config | TIMER Encoder Interface configuration structure
Return values
Status,see ald_status_t.

Definition at line 1608 of file ald_timer.c.

1609 {
1610 timer_oc_init_t oc;
1611
1612 assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh));
1613 assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode));
1614 assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div));
1615 assert_param(IS_TIMER_IC_POLARITY(config->polarity));
1616 assert_param(IS_TIMER_IC_PSC(config->psc));
1617 assert_param(IS_TIMER_IC_FILTER(config->filter));
1618
1619 if (hperh->state == TIMER_STATE_RESET)
1620 hperh->lock = UNLOCK;
1621
1622 hperh->state = TIMER_STATE_READY;
1623 timer_base_set_config(hperh->perh, &hperh->init);
1624 timer_ti1_set_config(hperh->perh, config->polarity, TIMER_IC_SEL_TRC, config->filter);
1625
1626 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS);
1627 SET_BIT(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK);
1628 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS);
1629 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS);
1630
1631 oc.oc_mode = TIMER_OC_MODE_PWM2;
1632 oc.pulse = config->delay;
1633 oc.oc_polarity = TIMER_OC_POLARITY_HIGH;
1634 oc.ocn_polarity = TIMER_OCN_POLARITY_HIGH;
1635 oc.oc_fast_en = DISABLE;
1636 oc.oc_idle = TIMER_OC_IDLE_RESET;
1637 oc.ocn_idle = TIMER_OCN_IDLE_RESET;
1638 timer_oc2_set_config(hperh->perh, &oc);
1639
1640 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_TRGO_OC2REF << TIMER_SMCON_SMODS_POSS);
1641 return OK;
1642 }
TIMER_OC_MODE_PWM2
Definition: ald_timer.h:71
timer_oc_init_t::oc_idle
timer_oc_idle_t oc_idle
Definition: ald_timer.h:153
TIMER_TRGO_OC2REF
Definition: ald_timer.h:461
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_STATE_RESET
Definition: ald_timer.h:161
timer_base_init_t::clk_div
timer_clock_division_t clk_div
Definition: ald_timer.h:140
IS_TIMER_COUNTER_MODE
#define IS_TIMER_COUNTER_MODE(x)
Definition: ald_timer.h:847
TIMER_STATE_READY
Definition: ald_timer.h:162
DISABLE
Definition: type.h:48
timer_oc_init_t::oc_fast_en
type_func_t oc_fast_en
Definition: ald_timer.h:152
TIMER_TS_TI1F_ED
Definition: ald_timer.h:378
TIMER_IC_SEL_TRC
Definition: ald_timer.h:228
timer_hall_sensor_init_t::psc
timer_ic_prescaler_t psc
Definition: ald_timer.h:400
timer_handle_s::init
timer_base_init_t init
Definition: ald_timer.h:184
timer_oc_init_t::ocn_polarity
timer_ocn_polarity_t ocn_polarity
Definition: ald_timer.h:151
UNLOCK
Definition: type.h:59
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_oc_init_t
TIMER output compare configuration structure definition.
Definition: ald_timer.h:147
timer_oc_init_t::ocn_idle
timer_ocn_idle_t ocn_idle
Definition: ald_timer.h:154
timer_oc_init_t::oc_polarity
timer_oc_polarity_t oc_polarity
Definition: ald_timer.h:150
timer_base_set_config
static void timer_base_set_config(TIMER_TypeDef *TIMERx, timer_base_init_t *init)
Time Base configuration.
Definition: ald_timer.c:3258
TIMER_OCN_POLARITY_HIGH
Definition: ald_timer.h:86
IS_TIMER_IC_FILTER
#define IS_TIMER_IC_FILTER(x)
Definition: ald_timer.h:894
IS_TIMER_IC_PSC
#define IS_TIMER_IC_PSC(x)
Definition: ald_timer.h:890
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
TIMER_MODE_RESET
Definition: ald_timer.h:364
TIMER_OC_POLARITY_HIGH
Definition: ald_timer.h:78
TIMER_OC_IDLE_RESET
Definition: ald_timer.h:94
timer_oc_init_t::pulse
uint32_t pulse
Definition: ald_timer.h:149
timer_hall_sensor_init_t::polarity
timer_ic_polarity_t polarity
Definition: ald_timer.h:399
timer_oc_init_t::oc_mode
timer_oc_mode_t oc_mode
Definition: ald_timer.h:148
timer_ti1_set_config
static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, timer_ic_select_t sel, uint32_t filter)
Configure the TI1 as Input.
Definition: ald_timer.c:3477
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
timer_hall_sensor_init_t::filter
uint32_t filter
Definition: ald_timer.h:401
timer_hall_sensor_init_t::delay
uint32_t delay
Definition: ald_timer.h:402
timer_base_init_t::mode
timer_cnt_mode_t mode
Definition: ald_timer.h:138
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_TIMER_CLOCK_DIVISION
#define IS_TIMER_CLOCK_DIVISION(x)
Definition: ald_timer.h:852
timer_handle_s::lock
lock_state_t lock
Definition: ald_timer.h:186
IS_TIMER_IC_POLARITY
#define IS_TIMER_IC_POLARITY(x)
Definition: ald_timer.h:885
timer_oc2_set_config
static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
Time Ouput Compare 2 configuration.
Definition: ald_timer.c:3320
TIMER_OCN_IDLE_RESET
Definition: ald_timer.h:102

◆ ald_timer_hall_sensor_start()

void ald_timer_hall_sensor_start ( timer_handle_t * hperh )

Starts the TIMER hall sensor interface.

Parameters
hperh TIMER handle
Return values
None

Definition at line 1648 of file ald_timer.c.

1649 {
1650 assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh));
1651
1652 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1653 TIMER_ENABLE(hperh);
1654
1655 return;
1656 }
ENABLE
Definition: type.h:49
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_ENABLE
#define TIMER_ENABLE(hperh)
Enable the TIMER peripheral.
Definition: ald_timer.h:550
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410

◆ ald_timer_hall_sensor_start_by_dma()

ald_status_t ald_timer_hall_sensor_start_by_dma | ( | timer_handle_t * | hperh,
 |  | uint16_t * | buf,
 |  | uint32_t | len,
 |  | uint8_t | dma_ch
 | ) |  |

Starts the TIMER hall sensor interface in DMA mode.

Parameters
hperh | TIMER handle
buf | The destination Buffer address. Reading data from CCR1.
len | The length of buffer to be transferred TIMER peripheral to memory
dma_ch | Channel of DMA.
Return values
Status,see ald_status_t.

Definition at line 1714 of file ald_timer.c.

1716 {
1717 assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh));
1718
1719 if ((hperh->state == TIMER_STATE_BUSY))
1720 return BUSY;
1721 if ((hperh->state == TIMER_STATE_READY)) {
1722 if (((uint32_t)buf == 0) || (len == 0))
1723 return ERROR;
1724 }
1725
1726 if (hperh->hdma1.perh == NULL)
1727 hperh->hdma1.perh = DMA0;
1728
1729 hperh->state = TIMER_STATE_BUSY;
1730 hperh->hdma1.cplt_cbk = timer_dma_capture_cplt;
1731 hperh->hdma1.cplt_arg = (void *)hperh;
1732 hperh->hdma1.err_cbk = timer_dma_error;
1733 hperh->hdma1.err_arg = (void *)hperh;
1734
1735 ald_dma_config_struct(&hperh->hdma1.config);
1736 hperh->hdma1.config.size = len;
1737 hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD;
1738 hperh->hdma1.config.src_inc = DMA_DATA_INC_NONE;
1739 hperh->hdma1.config.dst_inc = DMA_DATA_INC_HALFWORD;
1740
1741 timer_dma_msel(hperh->perh, &hperh->hdma1.config);
1742
1743 hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1;
1744 hperh->hdma1.config.dst = (void *)buf;
1745 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1;
1746 hperh->hdma1.config.channel = dma_ch;
1747 ald_dma_config_basic(&hperh->hdma1);
1748 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE);
1749 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1750 TIMER_ENABLE(hperh);
1751
1752 return OK;
1753 }
DMA_MSIGSEL_TIMER_CH1
Definition: ald_dma.h:145
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ENABLE
Definition: type.h:49
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
TIMER_STATE_READY
Definition: ald_timer.h:162
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
timer_dma_msel
static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config)
Timer DMA msel signal configuration.
Definition: ald_timer.c:3640
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_ENABLE
#define TIMER_ENABLE(hperh)
Enable the TIMER peripheral.
Definition: ald_timer.h:550
TIMER_STATE_BUSY
Definition: ald_timer.h:163
timer_handle_s::hdma1
dma_handle_t hdma1
Definition: ald_timer.h:190
timer_dma_error
static void timer_dma_error(void *arg)
TIMER DMA error callback.
Definition: ald_timer.c:3240
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
timer_dma_capture_cplt
static void timer_dma_capture_cplt(void *arg)
TIMER DMA Capture complete callback.
Definition: ald_timer.c:3208
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
ald_timer_dma_req_config
void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state)
Configure DMA request source.
Definition: ald_timer.c:3050
TIMER_DMA_CC1
Definition: ald_timer.h:507
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294

◆ ald_timer_hall_sensor_start_by_it()

void ald_timer_hall_sensor_start_by_it ( timer_handle_t * hperh )

Starts the TIMER hall sensor interface in interrupt mode.

Parameters
hperh TIMER handle
Return values
None

Definition at line 1678 of file ald_timer.c.

1679 {
1680 assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh));
1681
1682 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE);
1683 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1684 TIMER_ENABLE(hperh);
1685
1686 return;
1687 }
TIMER_IT_CC1
Definition: ald_timer.h:493
ENABLE
Definition: type.h:49
assert_param
#define assert_param(x)
Definition: type.h:88
ald_timer_interrupt_config
void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts.
Definition: ald_timer.c:3075
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_ENABLE
#define TIMER_ENABLE(hperh)
Enable the TIMER peripheral.
Definition: ald_timer.h:550
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410

◆ ald_timer_hall_sensor_stop()

void ald_timer_hall_sensor_stop ( timer_handle_t * hperh )

Stops the TIMER hall sensor interface.

Parameters
hperh TIMER handle
Return values
None

Definition at line 1663 of file ald_timer.c.

1664 {
1665 assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh));
1666
1667 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1668 TIMER_DISABLE(hperh);
1669
1670 return;
1671 }
assert_param
#define assert_param(x)
Definition: type.h:88
DISABLE
Definition: type.h:48
TIMER_CHANNEL_1
Definition: ald_timer.h:110
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410

◆ ald_timer_hall_sensor_stop_by_dma()

void ald_timer_hall_sensor_stop_by_dma ( timer_handle_t * hperh )

Stops the TIMER hall sensor interface in DMA mode.

Parameters
hperh TIMER handle
Return values
None

Definition at line 1759 of file ald_timer.c.

1760 {
1761 assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh));
1762
1763 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE);
1764 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1765 TIMER_DISABLE(hperh);
1766
1767 return;
1768 }
assert_param
#define assert_param(x)
Definition: type.h:88
DISABLE
Definition: type.h:48
TIMER_CHANNEL_1
Definition: ald_timer.h:110
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
ald_timer_dma_req_config
void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state)
Configure DMA request source.
Definition: ald_timer.c:3050
TIMER_DMA_CC1
Definition: ald_timer.h:507

◆ ald_timer_hall_sensor_stop_by_it()

void ald_timer_hall_sensor_stop_by_it ( timer_handle_t * hperh )

Stops the TIMER hall sensor interface in interrupt mode.

Parameters
hperh TIMER handle
Return values
None

Definition at line 1694 of file ald_timer.c.

1695 {
1696 assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh));
1697
1698 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1699 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE);
1700 TIMER_DISABLE(hperh);
1701
1702 return;
1703 }
TIMER_IT_CC1
Definition: ald_timer.h:493
assert_param
#define assert_param(x)
Definition: type.h:88
DISABLE
Definition: type.h:48
ald_timer_interrupt_config
void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts.
Definition: ald_timer.c:3075
TIMER_CHANNEL_1
Definition: ald_timer.h:110
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410


ALD User Manual: TIMER complementary output compare functions

Functions
TIMER complementary output compare functions
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Functions

TIMER complementary output compare functions. More...

Collaboration diagram for TIMER complementary output compare functions:

Functions

void | ald_timer_ocn_start (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER output compare signal generation on the complementary output. More...
void | ald_timer_ocn_stop (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER output compare signal generation on the complementary output. More...
void | ald_timer_ocn_start_by_it (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER output compare signal generation on the complementary output. in interrupt mode. More...
void | ald_timer_ocn_stop_by_it (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER output compare signal generation on the complementary output. in interrupt mode. More...
ald_status_t | ald_timer_ocn_start_by_dma (timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER output compare signal generation on the complementary output. in DMA mode. More...
void | ald_timer_ocn_stop_by_dma (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER output compare signal generation on the complementary output. in DMA mode. More...

Detailed Description

TIMER complementary output compare functions.

      ==============================================================================
      ##### Time complementary output compare functions #####
      ==============================================================================
      [..]
        This section provides functions allowing to:
        (+) Start the Time complementary output compare.
        (+) Stop the Time complementary output compare.
        (+) Start the Time complementary output compare and enable interrupt.
        (+) Stop the Time complementary output compare and disable interrupt.
        (+) Start the Time complementary output compare and enable DMA transfer.
        (+) Stop the Time complementary output compare and disable DMA transfer.

*

Function Documentation

◆ ald_timer_ocn_start()

void ald_timer_ocn_start | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Starts the TIMER output compare signal generation on the complementary output.

Parameters
hperh TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
Return values
None

Definition at line 1804 of file ald_timer.c.

1805 {
1806 assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch));
1807
1808 timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE);
1809 TIMER_MOE_ENABLE(hperh);
1810 TIMER_ENABLE(hperh);
1811
1812 return;
1813 }
ENABLE
Definition: type.h:49
assert_param
#define assert_param(x)
Definition: type.h:88
timer_ccxn_channel_cmd
static void timer_ccxn_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel xN.
Definition: ald_timer.c:3447
TIMER_ENABLE
#define TIMER_ENABLE(hperh)
Enable the TIMER peripheral.
Definition: ald_timer.h:550
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_MOE_ENABLE
#define TIMER_MOE_ENABLE(hperh)
Enable the TIMER main output.
Definition: ald_timer.h:555

◆ ald_timer_ocn_start_by_dma()

ald_status_t ald_timer_ocn_start_by_dma | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch,
 |  | uint16_t * | buf,
 |  | uint32_t | len,
 |  | uint8_t | dma_ch
 | ) |  |

Starts the TIMER output compare signal generation on the complementary output. in DMA mode.

Parameters
hperh | TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
buf | The destination Buffer address. Reading data from CCRx.
len | The length of buffer to be transferred TIMER peripheral to memory
dma_ch | Channel of DMA.
Return values
None

Definition at line 1934 of file ald_timer.c.

1936 {
1937 assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch));
1938
1939 if ((hperh->state == TIMER_STATE_BUSY))
1940 return BUSY;
1941 if ((hperh->state == TIMER_STATE_READY)) {
1942 if (((uint32_t)buf == 0 ) || (len == 0))
1943 return ERROR;
1944 }
1945
1946 hperh->state = TIMER_STATE_BUSY;
1947
1948 if (hperh->hdma1.perh == NULL)
1949 hperh->hdma1.perh = DMA0;
1950
1951 hperh->hdma1.cplt_cbk = timer_dma_oc_cplt;
1952 hperh->hdma1.cplt_arg = (void *)hperh;
1953 hperh->hdma1.err_cbk = timer_dma_error;
1954 hperh->hdma1.err_arg = (void *)hperh;
1955
1956 ald_dma_config_struct(&hperh->hdma1.config);
1957 hperh->hdma1.config.src = (void *)buf;
1958 hperh->hdma1.config.size = len;
1959 hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD;
1960 hperh->hdma1.config.src_inc = DMA_DATA_INC_HALFWORD;
1961 hperh->hdma1.config.dst_inc = DMA_DATA_INC_NONE;
1962 hperh->hdma1.config.channel = dma_ch;
1963 hperh->hdma1.config.msel = DMA_MSEL_TIMER0;
1964
1965 switch (ch) {
1966 case TIMER_CHANNEL_1:
1967 hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL1;
1968 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1;
1969 ald_dma_config_basic(&hperh->hdma1);
1970 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE);
1971 hperh->ch = TIMER_ACTIVE_CHANNEL_1;
1972 break;
1973
1974 case TIMER_CHANNEL_2:
1975 hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL2;
1976 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2;
1977 ald_dma_config_basic(&hperh->hdma1);
1978 ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE);
1979 hperh->ch = TIMER_ACTIVE_CHANNEL_2;
1980 break;
1981
1982 case TIMER_CHANNEL_3:
1983 hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL3;
1984 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH3;
1985 ald_dma_config_basic(&hperh->hdma1);
1986 ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE);
1987 hperh->ch = TIMER_ACTIVE_CHANNEL_3;
1988 break;
1989
1990 default:
1991 break;
1992 }
1993
1994 timer_ccx_channel_cmd(hperh->perh, ch, ENABLE);
1995 TIMER_MOE_ENABLE(hperh);
1996 TIMER_ENABLE(hperh);
1997
1998 return OK;
1999 }
DMA_MSIGSEL_TIMER_CH1
Definition: ald_dma.h:145
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ENABLE
Definition: type.h:49
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
TIMER_ACTIVE_CHANNEL_3
Definition: ald_timer.h:174
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_CHANNEL_3
Definition: ald_timer.h:112
BUSY
Definition: utils.h:57
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
TIMER_ACTIVE_CHANNEL_2
Definition: ald_timer.h:173
TIMER_STATE_READY
Definition: ald_timer.h:162
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
timer_dma_oc_cplt
static void timer_dma_oc_cplt(void *arg)
TIMER DMA out compare complete callback.
Definition: ald_timer.c:3189
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_ENABLE
#define TIMER_ENABLE(hperh)
Enable the TIMER peripheral.
Definition: ald_timer.h:550
TIMER_STATE_BUSY
Definition: ald_timer.h:163
timer_handle_s::hdma1
dma_handle_t hdma1
Definition: ald_timer.h:190
timer_dma_error
static void timer_dma_error(void *arg)
TIMER DMA error callback.
Definition: ald_timer.c:3240
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DMA_CC2
Definition: ald_timer.h:508
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
DMA_MSIGSEL_TIMER_CH2
Definition: ald_dma.h:146
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
TIMER_DMA_CC3
Definition: ald_timer.h:509
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
DMA_MSEL_TIMER0
Definition: ald_dma.h:94
DMA_MSIGSEL_TIMER_CH3
Definition: ald_dma.h:147
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
TIMER_ACTIVE_CHANNEL_1
Definition: ald_timer.h:172
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
timer_handle_s::ch
timer_active_channel_t ch
Definition: ald_timer.h:185
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
ald_timer_dma_req_config
void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state)
Configure DMA request source.
Definition: ald_timer.c:3050
TIMER_DMA_CC1
Definition: ald_timer.h:507
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
TIMER_MOE_ENABLE
#define TIMER_MOE_ENABLE(hperh)
Enable the TIMER main output.
Definition: ald_timer.h:555
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
TIMER_CHANNEL_2
Definition: ald_timer.h:111
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294

◆ ald_timer_ocn_start_by_it()

void ald_timer_ocn_start_by_it | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Starts the TIMER output compare signal generation on the complementary output. in interrupt mode.

Parameters
hperh TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
Return values
None

Definition at line 1847 of file ald_timer.c.

1848 {
1849 assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch));
1850
1851 switch (ch) {
1852 case TIMER_CHANNEL_1:
1853 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE);
1854 break;
1855
1856 case TIMER_CHANNEL_2:
1857 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE);
1858 break;
1859
1860 case TIMER_CHANNEL_3:
1861 ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE);
1862 break;
1863 default:
1864 break;
1865 }
1866
1867 ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, ENABLE);
1868 timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE);
1869 TIMER_MOE_ENABLE(hperh);
1870 TIMER_ENABLE(hperh);
1871
1872 return;
1873 }
TIMER_IT_CC1
Definition: ald_timer.h:493
ENABLE
Definition: type.h:49
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_CHANNEL_3
Definition: ald_timer.h:112
timer_ccxn_channel_cmd
static void timer_ccxn_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel xN.
Definition: ald_timer.c:3447
ald_timer_interrupt_config
void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts.
Definition: ald_timer.c:3075
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_IT_CC2
Definition: ald_timer.h:494
TIMER_ENABLE
#define TIMER_ENABLE(hperh)
Enable the TIMER peripheral.
Definition: ald_timer.h:550
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_IT_BREAK
Definition: ald_timer.h:499
TIMER_IT_CC3
Definition: ald_timer.h:495
TIMER_MOE_ENABLE
#define TIMER_MOE_ENABLE(hperh)
Enable the TIMER main output.
Definition: ald_timer.h:555
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ ald_timer_ocn_stop()

void ald_timer_ocn_stop | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Stops the TIMER output compare signal generation on the complementary output.

Parameters
hperh TIMER handle
ch TIMER Channels to be disabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
Return values
None

Definition at line 1825 of file ald_timer.c.

1826 {
1827 assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch));
1828
1829 timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE);
1830 TIMER_MOE_DISABLE(hperh);
1831 TIMER_DISABLE(hperh);
1832
1833 return;
1834 }
assert_param
#define assert_param(x)
Definition: type.h:88
DISABLE
Definition: type.h:48
timer_ccxn_channel_cmd
static void timer_ccxn_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel xN.
Definition: ald_timer.c:3447
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
TIMER_MOE_DISABLE
#define TIMER_MOE_DISABLE(hperh)
Disable the TIMER main output.
Definition: ald_timer.h:572

◆ ald_timer_ocn_stop_by_dma()

void ald_timer_ocn_stop_by_dma | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Starts the TIMER output compare signal generation on the complementary output. in DMA mode.

Parameters
hperh TIMER handle
ch TIMER Channels to be disabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
Return values
None

Definition at line 2012 of file ald_timer.c.

2013 {
2014 assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch));
2015
2016 switch (ch) {
2017 case TIMER_CHANNEL_1:
2018 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE);
2019 break;
2020
2021 case TIMER_CHANNEL_2:
2022 ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE);
2023 break;
2024
2025 case TIMER_CHANNEL_3:
2026 ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE);
2027 break;
2028 default:
2029 break;
2030 }
2031
2032 timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE);
2033 TIMER_MOE_DISABLE(hperh);
2034 TIMER_DISABLE(hperh);
2035
2036 return;
2037 }
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_CHANNEL_3
Definition: ald_timer.h:112
DISABLE
Definition: type.h:48
timer_ccxn_channel_cmd
static void timer_ccxn_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel xN.
Definition: ald_timer.c:3447
TIMER_CHANNEL_1
Definition: ald_timer.h:110
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
TIMER_DMA_CC2
Definition: ald_timer.h:508
TIMER_MOE_DISABLE
#define TIMER_MOE_DISABLE(hperh)
Disable the TIMER main output.
Definition: ald_timer.h:572
TIMER_DMA_CC3
Definition: ald_timer.h:509
ald_timer_dma_req_config
void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state)
Configure DMA request source.
Definition: ald_timer.c:3050
TIMER_DMA_CC1
Definition: ald_timer.h:507
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ ald_timer_ocn_stop_by_it()

void ald_timer_ocn_stop_by_it | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Stops the TIMER output compare signal generation on the complementary output. in interrupt mode.

Parameters
hperh TIMER handle
ch TIMER Channels to be disabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
Return values
None

Definition at line 1886 of file ald_timer.c.

1887 {
1888 assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch));
1889
1890 switch (ch) {
1891 case TIMER_CHANNEL_1:
1892 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE);
1893 break;
1894
1895 case TIMER_CHANNEL_2:
1896 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE);
1897 break;
1898
1899 case TIMER_CHANNEL_3:
1900 ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE);
1901 break;
1902 default:
1903 break;
1904 }
1905
1906 if ((!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1NEN_MSK)))
1907 && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2NEN_MSK)))
1908 && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC3NEN_MSK)))) {
1909 ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, DISABLE);
1910 }
1911
1912 timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE);
1913 TIMER_MOE_DISABLE(hperh);
1914 TIMER_DISABLE(hperh);
1915
1916 return;
1917 }
TIMER_IT_CC1
Definition: ald_timer.h:493
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_CHANNEL_3
Definition: ald_timer.h:112
DISABLE
Definition: type.h:48
timer_ccxn_channel_cmd
static void timer_ccxn_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel xN.
Definition: ald_timer.c:3447
ald_timer_interrupt_config
void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts.
Definition: ald_timer.c:3075
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_IT_CC2
Definition: ald_timer.h:494
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
TIMER_MOE_DISABLE
#define TIMER_MOE_DISABLE(hperh)
Disable the TIMER main output.
Definition: ald_timer.h:572
TIMER_IT_BREAK
Definition: ald_timer.h:499
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
TIMER_IT_CC3
Definition: ald_timer.h:495
TIMER_CHANNEL_2
Definition: ald_timer.h:111


ALD User Manual: TIMER complementary PWM functions

Functions
TIMER complementary PWM functions
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Functions

TIMER complementary PWM functions. More...

Collaboration diagram for TIMER complementary PWM functions:

Functions

void | ald_timer_pwmn_start (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER PWM signal generation on the complementary output. More...
void | ald_timer_pwmn_stop (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER PWM signal generation on the complementary output. More...
void | ald_timer_pwmn_start_by_it (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER PWM signal generation on the complementary output. in interrupt mode. More...
void | ald_timer_pwmn_stop_by_it (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER PWM signal generation on the complementary output. in interrupt mode. More...
ald_status_t | ald_timer_pwmn_start_by_dma (timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER PWM signal generation on the complementary output. in DMA mode. More...
void | ald_timer_pwmn_stop_by_dma (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER PWM signal generation on the complementary output. in DMA mode. More...

Detailed Description

TIMER complementary PWM functions.

      ==============================================================================
      ##### Time complementary PWM functions #####
      ==============================================================================
      [..]
        This section provides functions allowing to:
        (+) Start the Time complementary PWM.
        (+) Stop the Time complementary PWM.
        (+) Start the Time complementary PWM and enable interrupt.
        (+) Stop the Time complementary PWM and disable interrupt.
        (+) Start the Time complementary PWM and enable DMA transfer.
        (+) Stop the Time complementary PWM and disable DMA transfer.

*

Function Documentation

◆ ald_timer_pwmn_start()

void ald_timer_pwmn_start | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Starts the TIMER PWM signal generation on the complementary output.

Parameters
hperh TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
Return values
None

Definition at line 2073 of file ald_timer.c.

2074 {
2075 ald_timer_ocn_start(hperh, ch);
2076 }
ald_timer_ocn_start
void ald_timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER output compare signal generation on the complementary output.
Definition: ald_timer.c:1804

◆ ald_timer_pwmn_start_by_dma()

ald_status_t ald_timer_pwmn_start_by_dma | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch,
 |  | uint16_t * | buf,
 |  | uint32_t | len,
 |  | uint8_t | dma_ch
 | ) |  |

Starts the TIMER PWM signal generation on the complementary output. in DMA mode.

Parameters
hperh | TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
buf | The destination Buffer address. Reading data from CCRx.
len | The length of buffer to be transferred TIMER peripheral to memory
dma_ch | Channel of DMA.
Return values
None

Definition at line 2140 of file ald_timer.c.

2142 {
2143 return ald_timer_ocn_start_by_dma(hperh, ch, buf, len, dma_ch);
2144 }
ald_timer_ocn_start_by_dma
ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER output compare signal generation on the complementary output. in DMA mode...
Definition: ald_timer.c:1934

◆ ald_timer_pwmn_start_by_it()

void ald_timer_pwmn_start_by_it | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Starts the TIMER PWM signal generation on the complementary output. in interrupt mode.

Parameters
hperh TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
Return values
None

Definition at line 2104 of file ald_timer.c.

2105 {
2106 ald_timer_ocn_start_by_it(hperh, ch);
2107 }
ald_timer_ocn_start_by_it
void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER output compare signal generation on the complementary output. in interrupt mode...
Definition: ald_timer.c:1847

◆ ald_timer_pwmn_stop()

void ald_timer_pwmn_stop | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Stops the TIMER PWM signal generation on the complementary output.

Parameters
hperh TIMER handle
ch TIMER Channels to be disabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
Return values
None

Definition at line 2088 of file ald_timer.c.

2089 {
2090 ald_timer_ocn_stop(hperh, ch);
2091 }
ald_timer_ocn_stop
void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER output compare signal generation on the complementary output.
Definition: ald_timer.c:1825

◆ ald_timer_pwmn_stop_by_dma()

void ald_timer_pwmn_stop_by_dma | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Starts the TIMER PWM signal generation on the complementary output. in DMA mode.

Parameters
hperh TIMER handle
ch TIMER Channels to be disabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
Return values
None

Definition at line 2157 of file ald_timer.c.

2158 {
2159 ald_timer_ocn_stop_by_dma(hperh, ch);
2160 }
ald_timer_ocn_stop_by_dma
void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER output compare signal generation on the complementary output. in DMA mode...
Definition: ald_timer.c:2012

◆ ald_timer_pwmn_stop_by_it()

void ald_timer_pwmn_stop_by_it | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Stops the TIMER PWM signal generation on the complementary output. in interrupt mode.

Parameters
hperh TIMER handle
ch TIMER Channels to be disabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
Return values
None

Definition at line 2120 of file ald_timer.c.

2121 {
2122 ald_timer_ocn_stop_by_it(hperh, ch);
2123 }
ald_timer_ocn_stop_by_it
void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER output compare signal generation on the complementary output. in interrupt mode...
Definition: ald_timer.c:1886


ALD User Manual: TIMER complementary one pulse functions

Functions
TIMER complementary one pulse functions
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Functions

TIMER complementary one pulse functions. More...

Collaboration diagram for TIMER complementary one pulse functions:

Functions

void | ald_timer_one_pulse_n_start (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER one pulse signal generation on the complementary output. More...
void | ald_timer_one_pulse_n_stop (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER one pulse signal generation on the complementary output. More...
void | ald_timer_one_pulse_n_start_by_it (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER one pulse signal generation on the complementary output. in interrupt mode. More...
void | ald_timer_one_pulse_n_stop_by_it (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER one pulse signal generation on the complementary output. in interrupt mode. More...

Detailed Description

TIMER complementary one pulse functions.

      ==============================================================================
      ##### Time complementary one pulse functions #####
      ==============================================================================
      [..]
        This section provides functions allowing to:
        (+) Start the Time complementary one pulse.
        (+) Stop the Time complementary one pulse.
        (+) Start the Time complementary one pulse and enable interrupt.
        (+) Stop the Time complementary one pulse and disable interrupt.

*

Function Documentation

◆ ald_timer_one_pulse_n_start()

void ald_timer_one_pulse_n_start | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Starts the TIMER one pulse signal generation on the complementary output.

Parameters
hperh TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
Return values
None

Definition at line 2193 of file ald_timer.c.

2194 {
2195 ald_timer_ocn_start(hperh, ch);
2196 }
ald_timer_ocn_start
void ald_timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER output compare signal generation on the complementary output.
Definition: ald_timer.c:1804

◆ ald_timer_one_pulse_n_start_by_it()

void ald_timer_one_pulse_n_start_by_it | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Starts the TIMER one pulse signal generation on the complementary output. in interrupt mode.

Parameters
hperh TIMER handle
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
Return values
None

Definition at line 2222 of file ald_timer.c.

2223 {
2224 ald_timer_ocn_start_by_it(hperh, ch);
2225 }
ald_timer_ocn_start_by_it
void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER output compare signal generation on the complementary output. in interrupt mode...
Definition: ald_timer.c:1847

◆ ald_timer_one_pulse_n_stop()

void ald_timer_one_pulse_n_stop | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Stops the TIMER one pulse signal generation on the complementary output.

Parameters
hperh TIMER handle
ch TIMER Channels to be disabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
Return values
None

Definition at line 2207 of file ald_timer.c.

2208 {
2209 ald_timer_ocn_stop(hperh, ch);
2210 }
ald_timer_ocn_stop
void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER output compare signal generation on the complementary output.
Definition: ald_timer.c:1825

◆ ald_timer_one_pulse_n_stop_by_it()

void ald_timer_one_pulse_n_stop_by_it | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Stops the TIMER one pulse signal generation on the complementary output. in interrupt mode.

Parameters
hperh TIMER handle
ch TIMER Channels to be disabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
Return values
None

Definition at line 2237 of file ald_timer.c.

2238 {
2239 ald_timer_ocn_stop_by_it(hperh, ch);
2240 }
ald_timer_ocn_stop_by_it
void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER output compare signal generation on the complementary output. in interrupt mode...
Definition: ald_timer.c:1886


ALD User Manual: Peripheral Control functions

Functions
Peripheral Control functions
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Functions

Peripheral Control functions. More...

Collaboration diagram for Peripheral Control functions:

Functions

ald_status_t | ald_timer_oc_config_channel (timer_handle_t *hperh, timer_oc_init_t *config, timer_channel_t ch)
Initializes the TIMER Output Compare Channels according to the specified parameters in the timer_oc_init_t. More...
ald_status_t | ald_timer_ic_config_channel (timer_handle_t *hperh, timer_ic_init_t *config, timer_channel_t ch)
Initializes the TIMER Input Capture Channels according to the specified parameters in the timer_ic_init_t. More...
ald_status_t | ald_timer_one_pulse_config_channel (timer_handle_t *hperh, timer_one_pulse_init_t *config, timer_channel_t ch_out, timer_channel_t ch_in)
Initializes the TIMER One Pulse Channels according to the specified parameters in the timer_one_pulse_init_t. More...
ald_status_t | ald_timer_config_oc_ref_clear (timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch)
Configures the OCRef clear feature. More...
ald_status_t | ald_timer_config_clock_source (timer_handle_t *hperh, timer_clock_config_t *config)
Configures the clock source to be used. More...
ald_status_t | ald_timer_config_ti1_input (timer_handle_t *hperh, uint32_t ti1_select)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input. More...
ald_status_t | ald_timer_slave_config_sync (timer_handle_t *hperh, timer_slave_config_t *config)
Configures the TIMER in Slave mode. More...
ald_status_t | ald_timer_slave_config_sync_by_it (timer_handle_t *hperh, timer_slave_config_t *config)
Configures the TIMER in Slave mode in interrupt mode. More...
ald_status_t | ald_timer_generate_event (timer_handle_t *hperh, timer_event_source_t event)
Generate a software event. More...
uint32_t | ald_timer_read_capture_value (timer_handle_t *hperh, timer_channel_t ch)
Read the captured value from Capture Compare unit. More...
void | ald_timer_set_output_mode (timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch)
Sets TIMER output mode. More...
void | ald_timer_com_change_config (timer_handle_t *hperh, timer_com_channel_config_t *config)
Configure the channel in commutation event. More...
void | ald_timer_com_event_config (timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi)
Configure the TIMER commutation event sequence. More...
void | ald_timer_com_event_config_it (timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi)
Configure the TIMER commutation event sequence with interrupt. More...
void | ald_timer_break_dead_time_config (timer_handle_t *hperh, timer_break_dead_time_t *config)
Configure the break, dead timere, lock level state. More...
void | ald_timer_master_sync_config (timer_handle_t *hperh, timer_master_config_t *config)
Configure the master mode. More...
void | ald_timer_irq_handler (timer_handle_t *hperh)
This function handles TIMER interrupts requests. More...
void | ald_timer_dma_req_config (timer_handle_t *hperh, timer_dma_req_t req, type_func_t state)
Configure DMA request source. More...
void | ald_timer_interrupt_config (timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts. More...
it_status_t | ald_timer_get_it_status (timer_handle_t *hperh, timer_it_t it)
Get the status of TIMER interrupt source. More...
flag_status_t | ald_timer_get_flag_status (timer_handle_t *hperh, timer_flag_t flag)
Get the status of TIMER interrupt flag. More...
void | ald_timer_clear_flag_status (timer_handle_t *hperh, timer_flag_t flag)
Clear the TIMER interrupt flag. More...

Detailed Description

Peripheral Control functions.

 ==============================================================================
                  ##### Peripheral Control functions #####
 ==============================================================================
[..]
  This section provides functions allowing to:
     (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
     (+) Configure External Clock source.
     (+) Configure Complementary channels, break features and dead timere.
     (+) Configure Master and the Slave synchronization.
     (+) Handle TIMER interrupt.
     (+) Get TIMER compare register's vale.
     (+) Configure TIMER interrupt ENABLE/DISABLE.
     (+) Get TIMER interrupt source status.
     (+) Get TIMER interrupt flag status.
     (+) Clear TIMER interrupt flag.

Function Documentation

◆ ald_timer_break_dead_time_config()

void ald_timer_break_dead_time_config | ( | timer_handle_t * | hperh,
 |  | timer_break_dead_time_t * | config
 | ) |  |

Configure the break, dead timere, lock level state.

Parameters
hperh | TIMER handle
config | Pointer to the timer_break_dead_timere_t structure.
Return values
None

Definition at line 2875 of file ald_timer.c.

2876 {
2877 uint32_t tmp;
2878
2879 assert_param(IS_TIMER_BREAK_INSTANCE(hperh->perh));
2880 assert_param(IS_FUNC_STATE(config->off_run));
2881 assert_param(IS_FUNC_STATE(config->off_idle));
2882 assert_param(IS_TIMER_CLOCK_LEVEL(config->lock_level));
2883 assert_param(IS_TIMER_DEAD_TIMERE(config->dead_time));
2884 assert_param(IS_FUNC_STATE(config->break_state));
2885 assert_param(IS_TIMER_BREAK_POLARITY(config->polarity));
2886 assert_param(IS_FUNC_STATE(config->auto_out));
2887
2888 tmp = READ_REG(hperh->perh->BDCFG);
2889 MODIFY_REG(tmp, TIMER_BDCFG_OFFSSR_MSK, config->off_run << TIMER_BDCFG_OFFSSR_POS);
2890 MODIFY_REG(tmp, TIMER_BDCFG_OFFSSI_MSK, config->off_idle << TIMER_BDCFG_OFFSSI_POS);
2891 MODIFY_REG(tmp, TIMER_BDCFG_LOCKLVL_MSK, config->lock_level << TIMER_BDCFG_LOCKLVL_POSS);
2892 MODIFY_REG(tmp, TIMER_BDCFG_DT_MSK, config->dead_time << TIMER_BDCFG_DT_POSS);
2893 MODIFY_REG(tmp, TIMER_BDCFG_BRKEN_MSK, config->break_state << TIMER_BDCFG_BRKEN_POS);
2894 MODIFY_REG(tmp, TIMER_BDCFG_BRKP_MSK, config->polarity << TIMER_BDCFG_BRKP_POS);
2895 MODIFY_REG(tmp, TIMER_BDCFG_AOEN_MSK, config->auto_out << TIMER_BDCFG_AOEN_POS);
2896 WRITE_REG(hperh->perh->BDCFG, tmp);
2897
2898 hperh->state = TIMER_STATE_READY;
2899 return;
2900 }
timer_break_dead_time_t::off_run
type_func_t off_run
Definition: ald_timer.h:427
assert_param
#define assert_param(x)
Definition: type.h:88
READ_REG
#define READ_REG(reg)
Definition: type.h:73
TIMER_STATE_READY
Definition: ald_timer.h:162
timer_break_dead_time_t::off_idle
type_func_t off_idle
Definition: ald_timer.h:428
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_break_dead_time_t::break_state
type_func_t break_state
Definition: ald_timer.h:431
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
timer_break_dead_time_t::polarity
timer_break_polarity_t polarity
Definition: ald_timer.h:432
timer_break_dead_time_t::dead_time
uint32_t dead_time
Definition: ald_timer.h:430
IS_TIMER_DEAD_TIMERE
#define IS_TIMER_DEAD_TIMERE(x)
Definition: ald_timer.h:895
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_TIMER_CLOCK_LEVEL
#define IS_TIMER_CLOCK_LEVEL(x)
Definition: ald_timer.h:945
timer_break_dead_time_t::lock_level
timer_lock_level_t lock_level
Definition: ald_timer.h:429
IS_TIMER_BREAK_POLARITY
#define IS_TIMER_BREAK_POLARITY(x)
Definition: ald_timer.h:949
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
timer_break_dead_time_t::auto_out
type_func_t auto_out
Definition: ald_timer.h:433

◆ ald_timer_clear_flag_status()

void ald_timer_clear_flag_status | ( | timer_handle_t * | hperh,
 |  | timer_flag_t | flag
 | ) |  |

Clear the TIMER interrupt flag.

Parameters
hperh | Pointer to a uart_handle_t structure.
flag | Specifies the TIMER interrupt flag. This parameter can be one of the timer_flag_t.
Return values
None

Definition at line 3136 of file ald_timer.c.

3137 {
3138 assert_param(IS_TIMER_INSTANCE(hperh->perh));
3139 assert_param(IS_TIMER_FLAG(flag));
3140
3141 hperh->perh->ICR = flag;
3142 return;
3143 }
assert_param
#define assert_param(x)
Definition: type.h:88
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
IS_TIMER_FLAG
#define IS_TIMER_FLAG(x)
Definition: ald_timer.h:974

◆ ald_timer_com_change_config()

void ald_timer_com_change_config | ( | timer_handle_t * | hperh,
 |  | timer_com_channel_config_t * | config
 | ) |  |

Configure the channel in commutation event.

Parameters
hperh | TIMER handel
config | Parameters of the channel.
Return values
None

Definition at line 2777 of file ald_timer.c.

2778 {
2779 uint32_t cm1, cm2, cce;
2780
2781 assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh));
2782 assert_param(IS_FUNC_STATE(config->ch[0].en));
2783 assert_param(IS_FUNC_STATE(config->ch[0].n_en));
2784 assert_param(IS_TIMER_OC_MODE(config->ch[0].mode));
2785 assert_param(IS_FUNC_STATE(config->ch[1].en));
2786 assert_param(IS_FUNC_STATE(config->ch[1].n_en));
2787 assert_param(IS_TIMER_OC_MODE(config->ch[1].mode));
2788 assert_param(IS_FUNC_STATE(config->ch[2].en));
2789 assert_param(IS_FUNC_STATE(config->ch[2].n_en));
2790 assert_param(IS_TIMER_OC_MODE(config->ch[2].mode));
2791
2792 TIMER_MOE_DISABLE(hperh);
2793 TIMER_DISABLE(hperh);
2794
2795 cm1 = hperh->perh->CHMR1;
2796 cm2 = hperh->perh->CHMR2;
2797 cce = hperh->perh->CCEP;
2798
2799 MODIFY_REG(cm1, (0x7 << 4), (config->ch[0].mode << 4));
2800 MODIFY_REG(cm1, (0x7 << 12), (config->ch[1].mode << 12));
2801 MODIFY_REG(cm2, (0x7 << 4), (config->ch[2].mode << 4));
2802 MODIFY_REG(cce, (0x1 << 0), (config->ch[0].en << 0));
2803 MODIFY_REG(cce, (0x1 << 2), (config->ch[0].n_en << 2));
2804 MODIFY_REG(cce, (0x1 << 4), (config->ch[1].en << 4));
2805 MODIFY_REG(cce, (0x1 << 6), (config->ch[1].n_en << 6));
2806 MODIFY_REG(cce, (0x1 << 8), (config->ch[2].en << 8));
2807 MODIFY_REG(cce, (0x1 << 10), (config->ch[2].n_en << 10));
2808
2809 WRITE_REG(hperh->perh->CHMR1, cm1);
2810 WRITE_REG(hperh->perh->CHMR2, cm2);
2811 WRITE_REG(hperh->perh->CCEP, cce);
2812
2813 TIMER_MOE_ENABLE(hperh);
2814 TIMER_ENABLE(hperh);
2815 return;
2816 }
assert_param
#define assert_param(x)
Definition: type.h:88
timer_channel_config_t::n_en
type_func_t n_en
Definition: ald_timer.h:441
TIMER_ENABLE
#define TIMER_ENABLE(hperh)
Enable the TIMER peripheral.
Definition: ald_timer.h:550
IS_TIMER_OC_MODE
#define IS_TIMER_OC_MODE(x)
Definition: ald_timer.h:857
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
TIMER_MOE_DISABLE
#define TIMER_MOE_DISABLE(hperh)
Disable the TIMER main output.
Definition: ald_timer.h:572
timer_channel_config_t::mode
timer_oc_mode_t mode
Definition: ald_timer.h:442
timer_channel_config_t::en
type_func_t en
Definition: ald_timer.h:440
timer_com_channel_config_t::ch
timer_channel_config_t ch[3]
Definition: ald_timer.h:449
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
TIMER_MOE_ENABLE
#define TIMER_MOE_ENABLE(hperh)
Enable the TIMER main output.
Definition: ald_timer.h:555
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_timer_com_event_config()

void ald_timer_com_event_config | ( | timer_handle_t * | hperh,
 |  | timer_ts_t | ts,
 |  | type_func_t | trgi
 | ) |  |

Configure the TIMER commutation event sequence.

Parameters
hperh TIMER handel
ts the internal trigger corresponding to the timerer interfacing with the hall sensor. This parameter can be one of the following values:
  • TIMER_TS_ITR0
  • TIMER_TS_ITR1
  • TIMER_TS_ITR2
  • TIMER_TS_ITR3
trgi the commutation event source. This parameter can be one of the following values:
  • ENABLE: Commutation event source is TRGI
  • DISABLE: Commutation event source is set by software using the COMG bit
Return values
None

Definition at line 2834 of file ald_timer.c.

2835 {
2836 assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh));
2837 assert_param(IS_TIMER_TS(ts));
2838 assert_param(IS_FUNC_STATE(trgi));
2839
2840 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ts << TIMER_SMCON_TSSEL_POSS);
2841 SET_BIT(hperh->perh->CON2, TIMER_CON2_CCPCEN_MSK);
2842 MODIFY_REG(hperh->perh->CON2, TIMER_CON2_CCUSEL_MSK, trgi << TIMER_CON2_CCUSEL_POS);
2843
2844 return;
2845 }
assert_param
#define assert_param(x)
Definition: type.h:88
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_TIMER_TS
#define IS_TIMER_TS(x)
Definition: ald_timer.h:937
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_timer_com_event_config_it()

void ald_timer_com_event_config_it | ( | timer_handle_t * | hperh,
 |  | timer_ts_t | ts,
 |  | type_func_t | trgi
 | ) |  |

Configure the TIMER commutation event sequence with interrupt.

Parameters
hperh TIMER handel
ts the internal trigger corresponding to the timerer interfacing with the hall sensor. This parameter can be one of the following values:
  • TIMER_TS_ITR0
  • TIMER_TS_ITR1
  • TIMER_TS_ITR2
  • TIMER_TS_ITR3
trgi the commutation event source. This parameter can be one of the following values:
  • ENABLE: Commutation event source is TRGI
  • DISABLE: Commutation event source is set by software using the COMG bit
Return values
None

Definition at line 2863 of file ald_timer.c.

2864 {
2865 ald_timer_com_event_config(hperh, ts, trgi);
2866 ald_timer_interrupt_config(hperh, TIMER_IT_COM, ENABLE);
2867 }
ald_timer_com_event_config
void ald_timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi)
Configure the TIMER commutation event sequence.
Definition: ald_timer.c:2834
ENABLE
Definition: type.h:49
ald_timer_interrupt_config
void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts.
Definition: ald_timer.c:3075
TIMER_IT_COM
Definition: ald_timer.h:497

◆ ald_timer_config_clock_source()

ald_status_t ald_timer_config_clock_source | ( | timer_handle_t * | hperh,
 |  | timer_clock_config_t * | config
 | ) |  |

Configures the clock source to be used.

Parameters
hperh | TIMER handle
config | pointer to a timer_clock_config_t structure that contains the clock source information for the TIMER peripheral.
Return values
Status,see ald_status_t.

Definition at line 2518 of file ald_timer.c.

2519 {
2520 assert_param(IS_TIMER_INSTANCE(hperh->perh));
2521 assert_param(IS_TIMER_CLOCK_SOURCE(config->source));
2522 assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity));
2523 assert_param(IS_TIMER_ETR_PSC(config->psc));
2524 assert_param(IS_TIMER_IC_FILTER(config->filter));
2525
2526 __LOCK(hperh);
2527 hperh->state = TIMER_STATE_BUSY;
2528 WRITE_REG(hperh->perh->SMCON, 0x0);
2529
2530 switch (config->source) {
2531 case TIMER_SRC_INTER:
2532 CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK);
2533 break;
2534
2535 case TIMER_SRC_ETRMODE1:
2536 timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter);
2537 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ETRF << TIMER_SMCON_TSSEL_POSS);
2538 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
2539 break;
2540
2541 case TIMER_SRC_ETRMODE2:
2542 timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter);
2543 SET_BIT(hperh->perh->SMCON, TIMER_SMCON_ECM2EN_MSK);
2544 break;
2545
2546 case TIMER_SRC_TI1:
2547 timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter);
2548 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS);
2549 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
2550 break;
2551
2552 case TIMER_SRC_TI2:
2553 timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter);
2554 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS);
2555 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
2556 break;
2557
2558 case TIMER_SRC_TI1ED:
2559 timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter);
2560 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS);
2561 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
2562 break;
2563
2564 case TIMER_SRC_ITR0:
2565 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR0 << TIMER_SMCON_TSSEL_POSS);
2566 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
2567 break;
2568
2569 case TIMER_SRC_ITR1:
2570 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR1 << TIMER_SMCON_TSSEL_POSS);
2571 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
2572 break;
2573
2574 case TIMER_SRC_ITR2:
2575 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR2 << TIMER_SMCON_TSSEL_POSS);
2576 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
2577 break;
2578
2579 case TIMER_SRC_ITR3:
2580 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR3 << TIMER_SMCON_TSSEL_POSS);
2581 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
2582 break;
2583 default:
2584 break;
2585 }
2586
2587 hperh->state = TIMER_STATE_READY;
2588 __UNLOCK(hperh);
2589 return OK;
2590 }
timer_clock_config_t::source
timer_clock_source_t source
Definition: ald_timer.h:350
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_STATE_READY
Definition: ald_timer.h:162
TIMER_TS_TI1FP1
Definition: ald_timer.h:379
TIMER_SRC_ITR1
Definition: ald_timer.h:327
timer_ti1_set_config_stage
static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter)
Configure the Polarity and Filter for TI1.
Definition: ald_timer.c:3496
timer_clock_config_t::psc
timer_etr_psc_t psc
Definition: ald_timer.h:352
TIMER_SRC_INTER
Definition: ald_timer.h:325
TIMER_TS_TI1F_ED
Definition: ald_timer.h:378
IS_TIMER_ETR_PSC
#define IS_TIMER_ETR_PSC(x)
Definition: ald_timer.h:900
timer_clock_config_t::polarity
timer_clock_polarity_t polarity
Definition: ald_timer.h:351
TIMER_STATE_BUSY
Definition: ald_timer.h:163
TIMER_SRC_ETRMODE1
Definition: ald_timer.h:333
TIMER_TS_ETRF
Definition: ald_timer.h:381
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_TS_TI2FP2
Definition: ald_timer.h:380
IS_TIMER_IC_FILTER
#define IS_TIMER_IC_FILTER(x)
Definition: ald_timer.h:894
TIMER_SRC_ITR3
Definition: ald_timer.h:329
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
TIMER_SRC_TI1
Definition: ald_timer.h:331
timer_ti2_set_config_stage
static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter)
Configure the Polarity and Filter for TI2.
Definition: ald_timer.c:3532
TIMER_TS_ITR2
Definition: ald_timer.h:376
TIMER_SRC_ITR2
Definition: ald_timer.h:328
TIMER_SRC_TI2
Definition: ald_timer.h:332
timer_ic_polarity_t
timer_ic_polarity_t
TIMER input capture polarity.
Definition: ald_timer.h:217
IS_TIMER_CLOCK_SOURCE
#define IS_TIMER_CLOCK_SOURCE(x)
Definition: ald_timer.h:906
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
TIMER_MODE_EXTERNAL1
Definition: ald_timer.h:367
TIMER_TS_ITR1
Definition: ald_timer.h:375
TIMER_SRC_ETRMODE2
Definition: ald_timer.h:324
TIMER_TS_ITR0
Definition: ald_timer.h:374
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_TIMER_CLOCK_POLARITY
#define IS_TIMER_CLOCK_POLARITY(x)
Definition: ald_timer.h:916
timer_etr_set_config
static void timer_etr_set_config(TIMER_TypeDef *TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter)
Configures the TIMERx External Trigger (ETR).
Definition: ald_timer.c:3587
TIMER_TS_ITR3
Definition: ald_timer.h:377
__LOCK
#define __LOCK(x)
Definition: utils.h:92
TIMER_SRC_ITR0
Definition: ald_timer.h:326
TIMER_SRC_TI1ED
Definition: ald_timer.h:330
timer_clock_config_t::filter
uint32_t filter
Definition: ald_timer.h:353

◆ ald_timer_config_oc_ref_clear()

ald_status_t ald_timer_config_oc_ref_clear | ( | timer_handle_t * | hperh,
 |  | timer_clear_input_config_t * | config,
 |  | timer_channel_t | ch
 | ) |  |

Configures the OCRef clear feature.

Parameters
hperh | TIMER handle
config | pointer to a TIMER_ClearInputConfigTypeDef structure that contains the OCREF clear feature and parameters for the TIMER peripheral.
ch specifies the TIMER Channel This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1
  • TIMER_CHANNEL_2: TIMER Channel 2
  • TIMER_CHANNEL_3: TIMER Channel 3
  • TIMER_CHANNEL_4: TIMER Channel 4
Return values
Status,see ald_status_t.

Definition at line 2460 of file ald_timer.c.

2461 {
2462 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
2463 assert_param(IS_FUNC_STATE(config->state));
2464 assert_param(IS_TIMER_CLEAR_INPUT_SOURCE(config->source));
2465 assert_param(IS_TIMER_CLEAR_INPUT_POLARITY(config->polarity));
2466 assert_param(IS_TIMER_ETR_PSC(config->psc));
2467 assert_param(IS_TIMER_CHNREF_CLEAR(config->clrsel));
2468 assert_param(IS_TIMER_IC_FILTER(config->filter));
2469
2470 if (config->source == TIMER_INPUT_NONE) {
2471 timer_etr_set_config(hperh->perh, TIMER_ETR_PSC_DIV1, TIMER_CLK_POLARITY_NO_INV, 0);
2472 }
2473 else {
2474 timer_etr_set_config(hperh->perh, config->psc,
2475 (timer_clock_polarity_t)config->polarity, config->filter);
2476 }
2477
2478 if (config->clrsel == TIMER_CHNREF_CLR_CMP_IN) {
2479 CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_CHCSEL_MASK);
2480 }
2481 else {
2482 SET_BIT(hperh->perh->SMCON, TIMER_SMCON_CHCSEL_MASK);
2483 }
2484
2485 switch (ch) {
2486 case TIMER_CHANNEL_1:
2487 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OCLREN_MSK, config->state << TIMER_CHMR1_CH1OCLREN_POS);
2488 break;
2489
2490 case TIMER_CHANNEL_2:
2491 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OCLREN_MSK, config->state << TIMER_CHMR1_CH2OCLREN_POS);
2492 break;
2493
2494 case TIMER_CHANNEL_3:
2495 assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh));
2496 MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OCLREN_MSK, config->state << TIMER_CHMR2_CH3OCLREN_POS);
2497 break;
2498
2499 case TIMER_CHANNEL_4:
2500 assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh));
2501 MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OCLREN_MSK, config->state << TIMER_CHMR2_CH4OCLREN_POS);
2502 break;
2503
2504 default:
2505 break;
2506 }
2507
2508 return OK;
2509 }
OK
Definition: utils.h:55
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_CHANNEL_3
Definition: ald_timer.h:112
timer_clock_polarity_t
timer_clock_polarity_t
TIMER clock polarity.
Definition: ald_timer.h:338
timer_clear_input_config_t::state
type_func_t state
Definition: ald_timer.h:313
IS_TIMER_ETR_PSC
#define IS_TIMER_ETR_PSC(x)
Definition: ald_timer.h:900
TIMER_CHANNEL_1
Definition: ald_timer.h:110
timer_clear_input_config_t::psc
timer_etr_psc_t psc
Definition: ald_timer.h:316
timer_clear_input_config_t::source
timer_clear_input_source_t source
Definition: ald_timer.h:314
TIMER_ETR_PSC_DIV1
Definition: ald_timer.h:298
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_CLK_POLARITY_NO_INV
Definition: ald_timer.h:340
IS_TIMER_IC_FILTER
#define IS_TIMER_IC_FILTER(x)
Definition: ald_timer.h:894
TIMER_INPUT_NONE
Definition: ald_timer.h:284
IS_TIMER_CLEAR_INPUT_POLARITY
#define IS_TIMER_CLEAR_INPUT_POLARITY(x)
Definition: ald_timer.h:898
timer_clear_input_config_t::clrsel
timer_chnref_clr_sel_t clrsel
Definition: ald_timer.h:317
IS_TIMER_CHNREF_CLEAR
#define IS_TIMER_CHNREF_CLEAR(X)
Definition: ald_timer.h:904
TIMER_CHANNEL_4
Definition: ald_timer.h:113
timer_clear_input_config_t::filter
uint32_t filter
Definition: ald_timer.h:318
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
timer_clear_input_config_t::polarity
timer_clear_input_polarity_t polarity
Definition: ald_timer.h:315
TIMER_CHNREF_CLR_CMP_IN
Definition: ald_timer.h:307
IS_TIMER_CLEAR_INPUT_SOURCE
#define IS_TIMER_CLEAR_INPUT_SOURCE(x)
Definition: ald_timer.h:896
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
timer_etr_set_config
static void timer_etr_set_config(TIMER_TypeDef *TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter)
Configures the TIMERx External Trigger (ETR).
Definition: ald_timer.c:3587
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ ald_timer_config_ti1_input()

ald_status_t ald_timer_config_ti1_input | ( | timer_handle_t * | hperh,
 |  | uint32_t | ti1_select
 | ) |  |

Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input.

Parameters
hperh TIMER handle.
ti1_select Indicate whether or not channel 1 is connected to the output of a XOR gate. This parameter can be one of the following values:
  • 0: The TIMERx_CH1 pin is connected to TI1 input
  • 1: The TIMERx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination)
Return values
Status,see ald_status_t.

Definition at line 2604 of file ald_timer.c.

2605 {
2606 assert_param(IS_TIMER_INSTANCE(hperh->perh));
2607
2608 MODIFY_REG(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK, ti1_select << TIMER_CON2_I1FSEL_POS);
2609 return OK;
2610 }
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74

◆ ald_timer_dma_req_config()

void ald_timer_dma_req_config | ( | timer_handle_t * | hperh,
 |  | timer_dma_req_t | req,
 |  | type_func_t | state
 | ) |  |

Configure DMA request source.

Parameters
hperh | TIMER handle
req | DMA request source.
state | New state of the specified DMA request.
Return values
None

Definition at line 3050 of file ald_timer.c.

3051 {
3052 assert_param(IS_TIMER_INSTANCE(hperh->perh));
3053 assert_param(IS_TIMER_DMA_REQ(req));
3054 assert_param(IS_FUNC_STATE(state));
3055
3056 if (state == ENABLE)
3057 SET_BIT(hperh->perh->DMAEN, req);
3058 else
3059 CLEAR_BIT(hperh->perh->DMAEN, req);
3060
3061 return;
3062 }
ENABLE
Definition: type.h:49
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
IS_TIMER_DMA_REQ
#define IS_TIMER_DMA_REQ(x)
Definition: ald_timer.h:967
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_timer_generate_event()

ald_status_t ald_timer_generate_event | ( | timer_handle_t * | hperh,
 |  | timer_event_source_t | event
 | ) |  |

Generate a software event.

Parameters
hperh | TIMER handle
event | specifies the event source.
Return values
Status,see ald_status_t.

Definition at line 2678 of file ald_timer.c.

2679 {
2680 assert_param(IS_TIMER_INSTANCE(hperh->perh));
2681 assert_param(IS_TIMER_EVENT_SOURCE(event));
2682
2683 __LOCK(hperh);
2684 hperh->state = TIMER_STATE_BUSY;
2685 WRITE_REG(hperh->perh->SGE, event);
2686 hperh->state = TIMER_STATE_READY;
2687 __UNLOCK(hperh);
2688
2689 return OK;
2690 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
IS_TIMER_EVENT_SOURCE
#define IS_TIMER_EVENT_SOURCE(x)
Definition: ald_timer.h:929
TIMER_STATE_READY
Definition: ald_timer.h:162
TIMER_STATE_BUSY
Definition: ald_timer.h:163
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
__LOCK
#define __LOCK(x)
Definition: utils.h:92

◆ ald_timer_get_flag_status()

flag_status_t ald_timer_get_flag_status | ( | timer_handle_t * | hperh,
 |  | timer_flag_t | flag
 | ) |  |

Get the status of TIMER interrupt flag.

Parameters
hperh | Pointer to a timer_handle_t structure.
flag | Specifies the TIMER interrupt flag. This parameter can be one of the timer_flag_t.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 3118 of file ald_timer.c.

3119 {
3120 assert_param(IS_TIMER_INSTANCE(hperh->perh));
3121 assert_param(IS_TIMER_FLAG(flag));
3122
3123 if (hperh->perh->RIF & flag)
3124 return SET;
3125
3126 return RESET;
3127 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
RESET
Definition: type.h:38
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
IS_TIMER_FLAG
#define IS_TIMER_FLAG(x)
Definition: ald_timer.h:974

◆ ald_timer_get_it_status()

it_status_t ald_timer_get_it_status | ( | timer_handle_t * | hperh,
 |  | timer_it_t | it
 | ) |  |

Get the status of TIMER interrupt source.

Parameters
hperh | Pointer to a timer_handle_t structure.
it | Specifies the TIMER interrupt source. This parameter can be one of the timer_it_t.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 3098 of file ald_timer.c.

3099 {
3100 assert_param(IS_TIMER_INSTANCE(hperh->perh));
3101 assert_param(IS_TIMER_IT(it));
3102
3103 if (hperh->perh->IVS & it)
3104 return SET;
3105
3106 return RESET;
3107 }
IS_TIMER_IT
#define IS_TIMER_IT(x)
Definition: ald_timer.h:959
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
RESET
Definition: type.h:38
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183

◆ ald_timer_ic_config_channel()

ald_status_t ald_timer_ic_config_channel | ( | timer_handle_t * | hperh,
 |  | timer_ic_init_t * | config,
 |  | timer_channel_t | ch
 | ) |  |

Initializes the TIMER Input Capture Channels according to the specified parameters in the timer_ic_init_t.

Parameters
hperh | TIMER handle
config | TIMER Input Capture configuration structure
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
  • TIMER_CHANNEL_4: TIMER Channel 4 selected
Return values
Status,see ald_status_t.

Definition at line 2329 of file ald_timer.c.

2330 {
2331 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
2332 assert_param(IS_TIMER_IC_POLARITY(config->polarity));
2333 assert_param(IS_TIMER_IC_SELECT(config->sel));
2334 assert_param(IS_TIMER_IC_PSC(config->psc));
2335 assert_param(IS_TIMER_IC_FILTER(config->filter));
2336
2337 __LOCK(hperh);
2338 hperh->state = TIMER_STATE_BUSY;
2339
2340 switch (ch) {
2341 case TIMER_CHANNEL_1:
2342 timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter);
2343 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS);
2344 break;
2345
2346 case TIMER_CHANNEL_2:
2347 timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter);
2348 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->psc << TIMER_CHMR1_IC2PRES_POSS);
2349 break;
2350
2351 case TIMER_CHANNEL_3:
2352 timer_ti3_set_config(hperh->perh, config->polarity, config->sel, config->filter);
2353 MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC3PRES_MSK, config->psc << TIMER_CHMR2_IC3PRES_POSS);
2354 break;
2355
2356 case TIMER_CHANNEL_4:
2357 timer_ti4_set_config(hperh->perh, config->polarity, config->sel, config->filter);
2358 MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC4PRES_MSK, config->psc << TIMER_CHMR2_IC4PRES_POSS);
2359 break;
2360
2361 default:
2362 break;
2363 }
2364
2365 hperh->state = TIMER_STATE_READY;
2366 __UNLOCK(hperh);
2367 return OK;
2368 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
timer_ic_init_t::psc
timer_ic_prescaler_t psc
Definition: ald_timer.h:262
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_CHANNEL_3
Definition: ald_timer.h:112
timer_ic_init_t::polarity
timer_ic_polarity_t polarity
Definition: ald_timer.h:260
TIMER_STATE_READY
Definition: ald_timer.h:162
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_STATE_BUSY
Definition: ald_timer.h:163
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_ti2_set_config
static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, timer_ic_select_t sel, uint32_t filter)
Configure the TI2 as Input.
Definition: ald_timer.c:3513
IS_TIMER_IC_FILTER
#define IS_TIMER_IC_FILTER(x)
Definition: ald_timer.h:894
IS_TIMER_IC_SELECT
#define IS_TIMER_IC_SELECT(x)
Definition: ald_timer.h:887
IS_TIMER_IC_PSC
#define IS_TIMER_IC_PSC(x)
Definition: ald_timer.h:890
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
TIMER_CHANNEL_4
Definition: ald_timer.h:113
timer_ti1_set_config
static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, timer_ic_select_t sel, uint32_t filter)
Configure the TI1 as Input.
Definition: ald_timer.c:3477
timer_ic_init_t::filter
uint32_t filter
Definition: ald_timer.h:263
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
timer_ti3_set_config
static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, timer_ic_select_t sel, uint32_t filter)
Configure the TI3 as Input.
Definition: ald_timer.c:3548
IS_TIMER_IC_POLARITY
#define IS_TIMER_IC_POLARITY(x)
Definition: ald_timer.h:885
__LOCK
#define __LOCK(x)
Definition: utils.h:92
timer_ic_init_t::sel
timer_ic_select_t sel
Definition: ald_timer.h:261
TIMER_CHANNEL_2
Definition: ald_timer.h:111
timer_ti4_set_config
static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, timer_ic_select_t sel, uint32_t filter)
Configure the TI4 as Input.
Definition: ald_timer.c:3568

◆ ald_timer_interrupt_config()

void ald_timer_interrupt_config | ( | timer_handle_t * | hperh,
 |  | timer_it_t | it,
 |  | type_func_t | state
 | ) |  |

Enable/disable the specified TIMER interrupts.

Parameters
hperh | Pointer to a timer_handle_t structure.
it | Specifies the timer interrupt sources to be enabled or disabled. This parameter can be one of the timer_it_t.
state New state of the specified TIMER interrupts. This parameter can be:
  • ENABLE
  • DISABLE
Return values
None

Definition at line 3075 of file ald_timer.c.

3076 {
3077 assert_param(IS_TIMER_INSTANCE(hperh->perh));
3078 assert_param(IS_TIMER_IT(it));
3079 assert_param(IS_FUNC_STATE(state));
3080
3081 if (state == ENABLE)
3082 SET_BIT(hperh->perh->IER, it);
3083 else
3084 SET_BIT(hperh->perh->IDR, it);
3085
3086 return;
3087 }
ENABLE
Definition: type.h:49
IS_TIMER_IT
#define IS_TIMER_IT(x)
Definition: ald_timer.h:959
assert_param
#define assert_param(x)
Definition: type.h:88
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_timer_irq_handler()

void ald_timer_irq_handler ( timer_handle_t * hperh )

This function handles TIMER interrupts requests.

Parameters
hperh TIMER handle
Return values
None

Definition at line 2927 of file ald_timer.c.

2928 {
2929 uint32_t reg = hperh->perh->IFM;
2930
2931 /* Capture or compare 1 event */
2932 if (READ_BIT(reg, TIMER_FLAG_CC1)) {
2933 ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC1);
2934 hperh->ch = TIMER_ACTIVE_CHANNEL_1;
2935
2936 /* Input capture event */
2937 if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK)) {
2938 if (hperh->capture_cbk)
2939 hperh->capture_cbk(hperh);
2940 }
2941 else { /* Output compare event */
2942 if (hperh->delay_elapse_cbk)
2943 hperh->delay_elapse_cbk(hperh);
2944 if (hperh->pwm_pulse_finish_cbk)
2945 hperh->pwm_pulse_finish_cbk(hperh);
2946 }
2947
2948 hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED;
2949 }
2950 /* Capture or compare 2 event */
2951 if (READ_BIT(reg, TIMER_FLAG_CC2)) {
2952 ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC2);
2953 hperh->ch = TIMER_ACTIVE_CHANNEL_2;
2954
2955 /* Input capture event */
2956 if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK)) {
2957 if (hperh->capture_cbk)
2958 hperh->capture_cbk(hperh);
2959 }
2960 else { /* Output compare event */
2961 if (hperh->delay_elapse_cbk)
2962 hperh->delay_elapse_cbk(hperh);
2963 if (hperh->pwm_pulse_finish_cbk)
2964 hperh->pwm_pulse_finish_cbk(hperh);
2965 }
2966
2967 hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED;
2968 }
2969 /* Capture or compare 3 event */
2970 if (READ_BIT(reg, TIMER_FLAG_CC3)) {
2971 ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC3);
2972 hperh->ch = TIMER_ACTIVE_CHANNEL_3;
2973
2974 /* Input capture event */
2975 if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC3SSEL_MSK)) {
2976 if (hperh->capture_cbk)
2977 hperh->capture_cbk(hperh);
2978 }
2979 else { /* Output compare event */
2980 if (hperh->delay_elapse_cbk)
2981 hperh->delay_elapse_cbk(hperh);
2982 if (hperh->pwm_pulse_finish_cbk)
2983 hperh->pwm_pulse_finish_cbk(hperh);
2984 }
2985
2986 hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED;
2987 }
2988 /* Capture or compare 4 event */
2989 if (READ_BIT(reg, TIMER_FLAG_CC4)) {
2990 ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC4);
2991 hperh->ch = TIMER_ACTIVE_CHANNEL_4;
2992
2993 /* Input capture event */
2994 if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC4SSEL_MSK)) {
2995 if (hperh->capture_cbk)
2996 hperh->capture_cbk(hperh);
2997 }
2998 else { /* Output compare event */
2999 if (hperh->delay_elapse_cbk)
3000 hperh->delay_elapse_cbk(hperh);
3001 if (hperh->pwm_pulse_finish_cbk)
3002 hperh->pwm_pulse_finish_cbk(hperh);
3003 }
3004
3005 hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED;
3006 }
3007
3008 /* TIMER Update event */
3009 if (READ_BIT(reg, TIMER_FLAG_UPDATE)) {
3010 ald_timer_clear_flag_status(hperh, TIMER_FLAG_UPDATE);
3011
3012 if (hperh->period_elapse_cbk)
3013 hperh->period_elapse_cbk(hperh);
3014 }
3015
3016 /* TIMER Break input event */
3017 if (READ_BIT(reg, TIMER_FLAG_BREAK)) {
3018 ald_timer_clear_flag_status(hperh, TIMER_FLAG_BREAK);
3019
3020 if (hperh->break_cbk)
3021 hperh->break_cbk(hperh);
3022 }
3023
3024 /* TIMER Trigger detection event */
3025 if (READ_BIT(reg, TIMER_FLAG_TRIGGER)) {
3026 ald_timer_clear_flag_status(hperh, TIMER_FLAG_TRIGGER);
3027
3028 if (hperh->trigger_cbk)
3029 hperh->trigger_cbk(hperh);
3030 }
3031
3032 /* TIMER commutation event */
3033 if (READ_BIT(reg, TIMER_FLAG_COM)) {
3034 ald_timer_clear_flag_status(hperh, TIMER_FLAG_COM);
3035
3036 if (hperh->com_cbk)
3037 hperh->com_cbk(hperh);
3038 }
3039
3040 return;
3041 }
timer_handle_s::capture_cbk
void(* capture_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:196
TIMER_ACTIVE_CHANNEL_3
Definition: ald_timer.h:174
timer_handle_s::trigger_cbk
void(* trigger_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:198
TIMER_ACTIVE_CHANNEL_2
Definition: ald_timer.h:173
timer_handle_s::break_cbk
void(* break_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:199
TIMER_FLAG_CC1
Definition: ald_timer.h:520
ald_timer_clear_flag_status
void ald_timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag)
Clear the TIMER interrupt flag.
Definition: ald_timer.c:3136
timer_handle_s::com_cbk
void(* com_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:200
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
TIMER_FLAG_CC3
Definition: ald_timer.h:522
TIMER_ACTIVE_CHANNEL_CLEARED
Definition: ald_timer.h:176
TIMER_FLAG_CC4
Definition: ald_timer.h:523
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
TIMER_FLAG_TRIGGER
Definition: ald_timer.h:525
TIMER_FLAG_CC2
Definition: ald_timer.h:521
timer_handle_s::delay_elapse_cbk
void(* delay_elapse_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:195
TIMER_ACTIVE_CHANNEL_1
Definition: ald_timer.h:172
timer_handle_s::ch
timer_active_channel_t ch
Definition: ald_timer.h:185
timer_handle_s::pwm_pulse_finish_cbk
void(* pwm_pulse_finish_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:197
TIMER_FLAG_BREAK
Definition: ald_timer.h:526
TIMER_ACTIVE_CHANNEL_4
Definition: ald_timer.h:175
TIMER_FLAG_COM
Definition: ald_timer.h:524
TIMER_FLAG_UPDATE
Definition: ald_timer.h:519
timer_handle_s::period_elapse_cbk
void(* period_elapse_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:194

◆ ald_timer_master_sync_config()

void ald_timer_master_sync_config | ( | timer_handle_t * | hperh,
 |  | timer_master_config_t * | config
 | ) |  |

Configure the master mode.

Parameters
hperh | TIMER handle
config | Pointer to the timer_master_config_t structure.
Return values
None

Definition at line 2908 of file ald_timer.c.

2909 {
2910 assert_param(IS_TIMER_INSTANCE(hperh->perh));
2911 assert_param(IS_TIMER_MASTER_MODE_SEL(config->sel));
2912 assert_param(IS_FUNC_STATE(config->master_en));
2913
2914 hperh->state = TIMER_STATE_BUSY;
2915 MODIFY_REG(hperh->perh->CON2, TIMER_CON2_TRGOSEL_MSK, config->sel << TIMER_CON2_TRGOSEL_POSS);
2916 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_MSCFG_MSK, config->master_en << TIMER_SMCON_MSCFG_POS);
2917 hperh->state = TIMER_STATE_READY;
2918
2919 return;
2920 }
assert_param
#define assert_param(x)
Definition: type.h:88
timer_master_config_t::sel
timer_master_mode_sel_t sel
Definition: ald_timer.h:470
TIMER_STATE_READY
Definition: ald_timer.h:162
TIMER_STATE_BUSY
Definition: ald_timer.h:163
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
timer_master_config_t::master_en
type_func_t master_en
Definition: ald_timer.h:471
IS_TIMER_MASTER_MODE_SEL
#define IS_TIMER_MASTER_MODE_SEL(x)
Definition: ald_timer.h:951
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_timer_oc_config_channel()

ald_status_t ald_timer_oc_config_channel | ( | timer_handle_t * | hperh,
 |  | timer_oc_init_t * | config,
 |  | timer_channel_t | ch
 | ) |  |

Initializes the TIMER Output Compare Channels according to the specified parameters in the timer_oc_init_t.

Parameters
hperh | TIMER handle
config | TIMER Output Compare configuration structure
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
  • TIMER_CHANNEL_3: TIMER Channel 3 selected
  • TIMER_CHANNEL_4: TIMER Channel 4 selected
Return values
Status,see ald_status_t.

Definition at line 2281 of file ald_timer.c.

2282 {
2283 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
2284 assert_param(IS_TIMER_OC_MODE(config->oc_mode));
2285 assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity));
2286
2287 __LOCK(hperh);
2288 hperh->state = TIMER_STATE_BUSY;
2289
2290 switch (ch) {
2291 case TIMER_CHANNEL_1:
2292 timer_oc1_set_config(hperh->perh, config);
2293 break;
2294
2295 case TIMER_CHANNEL_2:
2296 timer_oc2_set_config(hperh->perh, config);
2297 break;
2298
2299 case TIMER_CHANNEL_3:
2300 timer_oc3_set_config(hperh->perh, config);
2301 break;
2302
2303 case TIMER_CHANNEL_4:
2304 timer_oc4_set_config(hperh->perh, config);
2305 break;
2306
2307 default:
2308 break;
2309 }
2310
2311 hperh->state = TIMER_STATE_READY;
2312 __UNLOCK(hperh);
2313 return OK;
2314 }
timer_oc3_set_config
static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
Time Ouput Compare 3 configuration.
Definition: ald_timer.c:3351
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_CHANNEL_3
Definition: ald_timer.h:112
TIMER_STATE_READY
Definition: ald_timer.h:162
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_STATE_BUSY
Definition: ald_timer.h:163
IS_TIMER_OC_MODE
#define IS_TIMER_OC_MODE(x)
Definition: ald_timer.h:857
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_oc_init_t::oc_polarity
timer_oc_polarity_t oc_polarity
Definition: ald_timer.h:150
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
TIMER_CHANNEL_4
Definition: ald_timer.h:113
timer_oc1_set_config
static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
Time Ouput Compare 1 configuration.
Definition: ald_timer.c:3289
timer_oc_init_t::oc_mode
timer_oc_mode_t oc_mode
Definition: ald_timer.h:148
timer_oc4_set_config
static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
Time Ouput Compare 4 configuration.
Definition: ald_timer.c:3382
__LOCK
#define __LOCK(x)
Definition: utils.h:92
timer_oc2_set_config
static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
Time Ouput Compare 2 configuration.
Definition: ald_timer.c:3320
TIMER_CHANNEL_2
Definition: ald_timer.h:111
IS_TIMER_OC_POLARITY
#define IS_TIMER_OC_POLARITY(x)
Definition: ald_timer.h:865

◆ ald_timer_one_pulse_config_channel()

ald_status_t ald_timer_one_pulse_config_channel | ( | timer_handle_t * | hperh,
 |  | timer_one_pulse_init_t * | config,
 |  | timer_channel_t | ch_out,
 |  | timer_channel_t | ch_in
 | ) |  |

Initializes the TIMER One Pulse Channels according to the specified parameters in the timer_one_pulse_init_t.

Parameters
hperh | TIMER handle
config | TIMER One Pulse configuration structure
ch_out TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
ch_in TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1: TIMER Channel 1 selected
  • TIMER_CHANNEL_2: TIMER Channel 2 selected
Return values
Status,see ald_status_t.

Definition at line 2385 of file ald_timer.c.

2387 {
2388 timer_oc_init_t tmp;
2389
2390 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
2391 assert_param(IS_TIMER_OC_MODE(config->mode));
2392 assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity));
2393 assert_param(IS_TIMER_OCN_POLARITY(config->ocn_polarity));
2394 assert_param(IS_TIMER_OCIDLE_STATE(config->oc_idle));
2395 assert_param(IS_TIMER_OCNIDLE_STATE(config->ocn_idle));
2396 assert_param(IS_TIMER_IC_POLARITY(config->polarity));
2397 assert_param(IS_TIMER_IC_SELECT(config->sel));
2398 assert_param(IS_TIMER_IC_FILTER(config->filter));
2399
2400 if (ch_out == ch_in)
2401 return ERROR;
2402
2403 __LOCK(hperh);
2404 hperh->state = TIMER_STATE_BUSY;
2405
2406 tmp.oc_mode = config->mode;
2407 tmp.pulse = config->pulse;
2408 tmp.oc_polarity = config->oc_polarity;
2409 tmp.ocn_polarity = config->ocn_polarity;
2410 tmp.oc_idle = config->oc_idle;
2411 tmp.ocn_idle = config->ocn_idle;
2412
2413 switch (ch_out) {
2414 case TIMER_CHANNEL_1:
2415 timer_oc1_set_config(hperh->perh, &tmp);
2416 break;
2417 case TIMER_CHANNEL_2:
2418 timer_oc2_set_config(hperh->perh, &tmp);
2419 break;
2420 default:
2421 break;
2422 }
2423
2424 switch (ch_in) {
2425 case TIMER_CHANNEL_1:
2426 timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter);
2427 CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK);
2428 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS);
2429 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS);
2430 break;
2431
2432 case TIMER_CHANNEL_2:
2433 timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter);
2434 CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK);
2435 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS);
2436 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS);
2437 break;
2438 default:
2439 break;
2440 }
2441
2442 hperh->state = TIMER_STATE_READY;
2443 __UNLOCK(hperh);
2444 return OK;
2445 }
timer_one_pulse_init_t::oc_polarity
timer_oc_polarity_t oc_polarity
Definition: ald_timer.h:272
timer_oc_init_t::oc_idle
timer_oc_idle_t oc_idle
Definition: ald_timer.h:153
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_STATE_READY
Definition: ald_timer.h:162
TIMER_TS_TI1FP1
Definition: ald_timer.h:379
IS_TIMER_OCNIDLE_STATE
#define IS_TIMER_OCNIDLE_STATE(x)
Definition: ald_timer.h:871
TIMER_CHANNEL_1
Definition: ald_timer.h:110
timer_oc_init_t::ocn_polarity
timer_ocn_polarity_t ocn_polarity
Definition: ald_timer.h:151
timer_one_pulse_init_t::polarity
timer_ic_polarity_t polarity
Definition: ald_timer.h:276
TIMER_STATE_BUSY
Definition: ald_timer.h:163
IS_TIMER_OC_MODE
#define IS_TIMER_OC_MODE(x)
Definition: ald_timer.h:857
timer_one_pulse_init_t::pulse
uint16_t pulse
Definition: ald_timer.h:271
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_one_pulse_init_t::ocn_polarity
timer_ocn_polarity_t ocn_polarity
Definition: ald_timer.h:273
timer_oc_init_t
TIMER output compare configuration structure definition.
Definition: ald_timer.h:147
timer_oc_init_t::ocn_idle
timer_ocn_idle_t ocn_idle
Definition: ald_timer.h:154
timer_ti2_set_config
static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, timer_ic_select_t sel, uint32_t filter)
Configure the TI2 as Input.
Definition: ald_timer.c:3513
TIMER_TS_TI2FP2
Definition: ald_timer.h:380
timer_oc_init_t::oc_polarity
timer_oc_polarity_t oc_polarity
Definition: ald_timer.h:150
timer_one_pulse_init_t::sel
timer_ic_select_t sel
Definition: ald_timer.h:277
IS_TIMER_IC_FILTER
#define IS_TIMER_IC_FILTER(x)
Definition: ald_timer.h:894
timer_one_pulse_init_t::mode
timer_oc_mode_t mode
Definition: ald_timer.h:270
IS_TIMER_IC_SELECT
#define IS_TIMER_IC_SELECT(x)
Definition: ald_timer.h:887
timer_one_pulse_init_t::oc_idle
timer_oc_idle_t oc_idle
Definition: ald_timer.h:274
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
timer_oc1_set_config
static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
Time Ouput Compare 1 configuration.
Definition: ald_timer.c:3289
timer_oc_init_t::pulse
uint32_t pulse
Definition: ald_timer.h:149
timer_one_pulse_init_t::ocn_idle
timer_ocn_idle_t ocn_idle
Definition: ald_timer.h:275
timer_oc_init_t::oc_mode
timer_oc_mode_t oc_mode
Definition: ald_timer.h:148
IS_TIMER_OCIDLE_STATE
#define IS_TIMER_OCIDLE_STATE(x)
Definition: ald_timer.h:869
timer_ti1_set_config
static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, timer_ic_select_t sel, uint32_t filter)
Configure the TI1 as Input.
Definition: ald_timer.c:3477
TIMER_MODE_TRIG
Definition: ald_timer.h:366
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_TIMER_OCN_POLARITY
#define IS_TIMER_OCN_POLARITY(x)
Definition: ald_timer.h:867
IS_TIMER_IC_POLARITY
#define IS_TIMER_IC_POLARITY(x)
Definition: ald_timer.h:885
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
timer_oc2_set_config
static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
Time Ouput Compare 2 configuration.
Definition: ald_timer.c:3320
TIMER_CHANNEL_2
Definition: ald_timer.h:111
IS_TIMER_OC_POLARITY
#define IS_TIMER_OC_POLARITY(x)
Definition: ald_timer.h:865
timer_one_pulse_init_t::filter
uint32_t filter
Definition: ald_timer.h:278

◆ ald_timer_read_capture_value()

uint32_t ald_timer_read_capture_value | ( | timer_handle_t * | hperh,
 |  | timer_channel_t | ch
 | ) |  |

Read the captured value from Capture Compare unit.

Parameters
hperh TIMER handle.
ch TIMER Channels to be enabled This parameter can be one of the following values:
  • TIMER_CHANNEL_1 : TIMER Channel 1 selected
  • TIMER_CHANNEL_2 : TIMER Channel 2 selected
  • TIMER_CHANNEL_3 : TIMER Channel 3 selected
  • TIMER_CHANNEL_4 : TIMER Channel 4 selected
Return values
Captured value

Definition at line 2703 of file ald_timer.c.

2704 {
2705 uint32_t tmp;
2706
2707 __LOCK(hperh);
2708 hperh->state = TIMER_STATE_BUSY;
2709
2710 switch (ch) {
2711 case TIMER_CHANNEL_1:
2712 tmp = hperh->perh->CCVAL1;
2713 break;
2714 case TIMER_CHANNEL_2:
2715 tmp = hperh->perh->CCVAL2;
2716 break;
2717 case TIMER_CHANNEL_3:
2718 tmp = hperh->perh->CCVAL3;
2719 break;
2720 case TIMER_CHANNEL_4:
2721 tmp = hperh->perh->CCVAL4;
2722 break;
2723 default:
2724 tmp = hperh->perh->CCVAL1;
2725 break;
2726 }
2727
2728 hperh->state = TIMER_STATE_READY;
2729 __UNLOCK(hperh);
2730 return tmp;
2731 }
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
TIMER_CHANNEL_3
Definition: ald_timer.h:112
TIMER_STATE_READY
Definition: ald_timer.h:162
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_STATE_BUSY
Definition: ald_timer.h:163
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
TIMER_CHANNEL_4
Definition: ald_timer.h:113
__LOCK
#define __LOCK(x)
Definition: utils.h:92
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ ald_timer_set_output_mode()

void ald_timer_set_output_mode | ( | timer_handle_t * | hperh,
 |  | timer_oc_mode_t | mode,
 |  | timer_channel_t | ch
 | ) |  |

Sets TIMER output mode.

Parameters
hperh | TIMER handle.
mode | TIMER output mode.
ch TIMER Channels. This parameter can be one of the following values:
  • TIMER_CHANNEL_1 : TIMER Channel 1 selected
  • TIMER_CHANNEL_2 : TIMER Channel 2 selected
  • TIMER_CHANNEL_3 : TIMER Channel 3 selected
  • TIMER_CHANNEL_4 : TIMER Channel 4 selected
Return values
None

Definition at line 2745 of file ald_timer.c.

2746 {
2747 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
2748 assert_param(IS_TIMER_OC_MODE(mode));
2749 assert_param(IS_TIMER_CHANNELS(ch));
2750
2751 switch (ch) {
2752 case TIMER_CHANNEL_1:
2753 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, mode << TIMER_CHMR1_CH1OMOD_POSS);
2754 break;
2755 case TIMER_CHANNEL_2:
2756 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, mode << TIMER_CHMR1_CH2OMOD_POSS);
2757 break;
2758 case TIMER_CHANNEL_3:
2759 MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, mode << TIMER_CHMR2_CH3OMOD_POSS);
2760 break;
2761 case TIMER_CHANNEL_4:
2762 MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, mode << TIMER_CHMR2_CH4OMOD_POSS);
2763 break;
2764 default:
2765 break;
2766 }
2767
2768 return;
2769 }
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_CHANNEL_3
Definition: ald_timer.h:112
TIMER_CHANNEL_1
Definition: ald_timer.h:110
IS_TIMER_OC_MODE
#define IS_TIMER_OC_MODE(x)
Definition: ald_timer.h:857
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
IS_TIMER_CHANNELS
#define IS_TIMER_CHANNELS(x)
Definition: ald_timer.h:873
TIMER_CHANNEL_4
Definition: ald_timer.h:113
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ ald_timer_slave_config_sync()

ald_status_t ald_timer_slave_config_sync | ( | timer_handle_t * | hperh,
 |  | timer_slave_config_t * | config
 | ) |  |

Configures the TIMER in Slave mode.

Parameters
hperh | TIMER handle.
config | pointer to a timer_slave_config_t structure that contains the selected trigger (internal trigger input, filtered timerer input or external trigger input) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1).
Return values
Status,see ald_status_t.

Definition at line 2621 of file ald_timer.c.

2622 {
2623 assert_param(IS_TIMER_INSTANCE(hperh->perh));
2624 assert_param(IS_TIMER_SLAVE_MODE(config->mode));
2625 assert_param(IS_TIMER_TS(config->input));
2626 assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity));
2627 assert_param(IS_TIMER_ETR_PSC(config->psc));
2628 assert_param(IS_TIMER_IC_FILTER(config->filter));
2629
2630 __LOCK(hperh);
2631 hperh->state = TIMER_STATE_BUSY;
2632
2633 timer_slave_set_config(hperh, config);
2634 ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, DISABLE);
2635 ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE);
2636
2637 hperh->state = TIMER_STATE_READY;
2638 __UNLOCK(hperh);
2639 return OK;
2640 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_STATE_READY
Definition: ald_timer.h:162
DISABLE
Definition: type.h:48
TIMER_DMA_TRIGGER
Definition: ald_timer.h:512
ald_timer_interrupt_config
void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts.
Definition: ald_timer.c:3075
IS_TIMER_ETR_PSC
#define IS_TIMER_ETR_PSC(x)
Definition: ald_timer.h:900
timer_slave_config_t::mode
timer_slave_mode_t mode
Definition: ald_timer.h:388
TIMER_STATE_BUSY
Definition: ald_timer.h:163
timer_slave_config_t::psc
timer_etr_psc_t psc
Definition: ald_timer.h:391
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_slave_config_t::polarity
timer_clock_polarity_t polarity
Definition: ald_timer.h:390
IS_TIMER_IC_FILTER
#define IS_TIMER_IC_FILTER(x)
Definition: ald_timer.h:894
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
timer_slave_config_t::input
timer_ts_t input
Definition: ald_timer.h:389
TIMER_IT_TRIGGER
Definition: ald_timer.h:498
IS_TIMER_TS
#define IS_TIMER_TS(x)
Definition: ald_timer.h:937
timer_slave_config_t::filter
uint32_t filter
Definition: ald_timer.h:392
timer_slave_set_config
static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t *config)
Time Slave configuration.
Definition: ald_timer.c:3603
IS_TIMER_CLOCK_POLARITY
#define IS_TIMER_CLOCK_POLARITY(x)
Definition: ald_timer.h:916
ald_timer_dma_req_config
void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state)
Configure DMA request source.
Definition: ald_timer.c:3050
IS_TIMER_SLAVE_MODE
#define IS_TIMER_SLAVE_MODE(x)
Definition: ald_timer.h:921
__LOCK
#define __LOCK(x)
Definition: utils.h:92

◆ ald_timer_slave_config_sync_by_it()

ald_status_t ald_timer_slave_config_sync_by_it | ( | timer_handle_t * | hperh,
 |  | timer_slave_config_t * | config
 | ) |  |

Configures the TIMER in Slave mode in interrupt mode.

Parameters
hperh | TIMER handle.
config | pointer to a timer_slave_config_t structure that contains the selected trigger (internal trigger input, filtered timerer input or external trigger input) and the ) and the Slave mode (Disable, Reset, Gated, Trigger, External clock mode 1).
Return values
Status,see ald_status_t.

Definition at line 2651 of file ald_timer.c.

2652 {
2653 assert_param(IS_TIMER_INSTANCE(hperh->perh));
2654 assert_param(IS_TIMER_SLAVE_MODE(config->mode));
2655 assert_param(IS_TIMER_TS(config->input));
2656 assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity));
2657 assert_param(IS_TIMER_ETR_PSC(config->psc));
2658 assert_param(IS_TIMER_IC_FILTER(config->filter));
2659
2660 __LOCK(hperh);
2661 hperh->state = TIMER_STATE_BUSY;
2662
2663 timer_slave_set_config(hperh, config);
2664 ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, ENABLE);
2665 ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE);
2666
2667 hperh->state = TIMER_STATE_READY;
2668 __UNLOCK(hperh);
2669 return OK;
2670 }
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_STATE_READY
Definition: ald_timer.h:162
DISABLE
Definition: type.h:48
TIMER_DMA_TRIGGER
Definition: ald_timer.h:512
ald_timer_interrupt_config
void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts.
Definition: ald_timer.c:3075
IS_TIMER_ETR_PSC
#define IS_TIMER_ETR_PSC(x)
Definition: ald_timer.h:900
timer_slave_config_t::mode
timer_slave_mode_t mode
Definition: ald_timer.h:388
TIMER_STATE_BUSY
Definition: ald_timer.h:163
timer_slave_config_t::psc
timer_etr_psc_t psc
Definition: ald_timer.h:391
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_slave_config_t::polarity
timer_clock_polarity_t polarity
Definition: ald_timer.h:390
IS_TIMER_IC_FILTER
#define IS_TIMER_IC_FILTER(x)
Definition: ald_timer.h:894
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
timer_slave_config_t::input
timer_ts_t input
Definition: ald_timer.h:389
TIMER_IT_TRIGGER
Definition: ald_timer.h:498
IS_TIMER_TS
#define IS_TIMER_TS(x)
Definition: ald_timer.h:937
timer_slave_config_t::filter
uint32_t filter
Definition: ald_timer.h:392
timer_slave_set_config
static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t *config)
Time Slave configuration.
Definition: ald_timer.c:3603
IS_TIMER_CLOCK_POLARITY
#define IS_TIMER_CLOCK_POLARITY(x)
Definition: ald_timer.h:916
ald_timer_dma_req_config
void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state)
Configure DMA request source.
Definition: ald_timer.c:3050
IS_TIMER_SLAVE_MODE
#define IS_TIMER_SLAVE_MODE(x)
Definition: ald_timer.h:921
__LOCK
#define __LOCK(x)
Definition: utils.h:92


ALD User Manual: Peripheral State functions

Functions
Peripheral State functions
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Functions

Peripheral State functions. More...

Collaboration diagram for Peripheral State functions:

Functions

timer_state_t ald_timer_get_state (timer_handle_t *hperh)
Return the TIMER Base state. More...

Detailed Description

Peripheral State functions.

==============================================================================
                      ##### Peripheral State functions #####
==============================================================================
  [..]
  This subsection permit to get in run-timere the status of the peripheral
  and the data flow.

Function Documentation

◆ ald_timer_get_state()

timer_state_t ald_timer_get_state ( timer_handle_t * hperh )

Return the TIMER Base state.

Parameters
hperh TIMER handle
Return values
TIMER peripheral state

Definition at line 3168 of file ald_timer.c.

3169 {
3170 return hperh->state;
3171 }
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187


ALD User Manual: TIMER Public Types

Data Structures | Typedefs | Enumerations
TIMER Public Types
EASTSOFT ES32F3xx ALD » TIMER
Collaboration diagram for TIMER Public Types:

Data Structures

struct | timer_base_init_t
TIMER time base configuration structure definition. More...
struct | timer_oc_init_t
TIMER output compare configuration structure definition. More...
struct | timer_handle_s
TIMER time base handle structure definition. More...
struct | timer_encoder_init_t
TIMER encoder configuration structure definition. More...
struct | timer_ic_init_t
TIMER input capture configuration structure definition. More...
struct | timer_one_pulse_init_t
TIMER one pulse mode configuration structure definition. More...
struct | timer_clear_input_config_t
TIMER clear input configuration handle structure definition. More...
struct | timer_clock_config_t
TIMER clock config structure definition. More...
struct | timer_slave_config_t
TIMER slave configuration structure definition. More...
struct | timer_hall_sensor_init_t
TIMER hall sensor configuretion structure definition. More...
struct | timer_break_dead_time_t
TIMER break and dead time configuretion structure definition. More...
struct | timer_channel_config_t
TIMER commutation event channel configuretion structure definition. More...
struct | timer_com_channel_config_t
TIMER commutation event configuretion structure definition. More...
struct | timer_master_config_t
TIMER master configuretion structure definition. More...

Typedefs

typedef struct timer_handle_s timer_handle_t
TIMER time base handle structure definition. More...

Enumerations

enum timer_cnt_mode_t {
TIMER_CNT_MODE_UP = 0U, TIMER_CNT_MODE_DOWN = 1U, TIMER_CNT_MODE_CENTER1 = 2U, TIMER_CNT_MODE_CENTER2 = 3U,
TIMER_CNT_MODE_CENTER3 = 4U
}
TIMER counter mode. More...
enum | timer_clock_division_t { TIMER_CLOCK_DIV1 = 0U, TIMER_CLOCK_DIV2 = 1U, TIMER_CLOCK_DIV4 = 2U }
TIMER clock division. More...
enum timer_oc_mode_t {
TIMER_OC_MODE_TIMERING = 0U, TIMER_OC_MODE_ACTIVE = 1U, TIMER_OC_MODE_INACTIVE = 2U, TIMER_OC_MODE_TOGGLE = 3U,
TIMER_OC_MODE_FORCE_INACTIVE = 4U, TIMER_OC_MODE_FORCE_ACTIVE = 5U, TIMER_OC_MODE_PWM1 = 6U, TIMER_OC_MODE_PWM2 = 7U
}
TIMER output compare and PWM modes. More...
enum | timer_oc_polarity_t { TIMER_OC_POLARITY_HIGH = 0U, TIMER_OC_POLARITY_LOW = 1U }
TIMER output compare polarity. More...
enum | timer_ocn_polarity_t { TIMER_OCN_POLARITY_HIGH = 0U, TIMER_OCN_POLARITY_LOW = 1U }
TIMER complementary output compare polarity. More...
enum | timer_oc_idle_t { TIMER_OC_IDLE_RESET = 0U, TIMER_OC_IDLE_SET = 1U }
TIMER output compare idle state. More...
enum | timer_ocn_idle_t { TIMER_OCN_IDLE_RESET = 0U, TIMER_OCN_IDLE_SET = 1U }
TIMER complementary output compare idle state. More...
enum timer_channel_t {
TIMER_CHANNEL_1 = 0U, TIMER_CHANNEL_2 = 1U, TIMER_CHANNEL_3 = 2U, TIMER_CHANNEL_4 = 3U,
TIMER_CHANNEL_ALL = 0xFU
}
TIMER channel. More...
enum | timer_op_mode_t { TIMER_OP_MODE_REPEAT = 0U, TIMER_OP_MODE_SINGLE = 1U }
TIMER one pulse mode. More...
enum | timer_op_output_channel_t { TIMER_OP_OUTPUT_CHANNEL_1 = 0U, TIMER_OP_OUTPUT_CHANNEL_2 = 1U }
TIMER one pulse output channel. More...
enum timer_state_t {
TIMER_STATE_RESET = 0x00U, TIMER_STATE_READY = 0x01U, TIMER_STATE_BUSY = 0x02U, TIMER_STATE_TIMEREOUT = 0x03U,
TIMER_STATE_ERROR = 0x04U
}
State structures definition. More...
enum timer_active_channel_t {
TIMER_ACTIVE_CHANNEL_1 = 0x01U, TIMER_ACTIVE_CHANNEL_2 = 0x02U, TIMER_ACTIVE_CHANNEL_3 = 0x04U, TIMER_ACTIVE_CHANNEL_4 = 0x08U,
TIMER_ACTIVE_CHANNEL_CLEARED = 0x00U
}
Active channel structures definition. More...
enum | timer_encoder_mode_t { TIMER_ENC_MODE_TI1 = 1U, TIMER_ENC_MODE_TI2 = 2U, TIMER_ENC_MODE_TI12 = 3U }
TIMER encoder mode. More...
enum | timer_ic_polarity_t { TIMER_IC_POLARITY_RISE = 0U, TIMER_IC_POLARITY_FALL = 1U }
TIMER input capture polarity. More...
enum | timer_ic_select_t { TIMER_IC_SEL_DIRECT = 1U, TIMER_IC_SEL_INDIRECT = 2U, TIMER_IC_SEL_TRC = 3U }
TIMER input capture selection. More...
enum | timer_ic_prescaler_t { TIMER_IC_PSC_DIV1 = 0U, TIMER_IC_PSC_DIV2 = 1U, TIMER_IC_PSC_DIV4 = 2U, TIMER_IC_PSC_DIV8 = 3U }
TIMER input capture prescaler. More...
enum | timer_clear_input_source_t { TIMER_INPUT_NONE = 0U, TIMER_INPUT_ETR = 1U }
TIMER clear input source. More...
enum | timer_clear_input_polarity_t { TIMER_POLARITY_NO_INV = 0U, TIMER_POLARITY_INV = 1U }
TIMER clear input polarity. More...
enum | timer_etr_psc_t { TIMER_ETR_PSC_DIV1 = 0U, TIMER_ETR_PSC_DIV2 = 1U, TIMER_ETR_PSC_DIV4 = 2U, TIMER_ETR_PSC_DIV8 = 3U }
TIMER clear input polarity. More...
enum | timer_chnref_clr_sel_t { TIMER_CHNREF_CLR_CMP_IN = 0U, TIMER_CHNREF_CLR_ETF = 1U }
TIMER CHnREF Clear Select. More...
enum timer_clock_source_t {
TIMER_SRC_ETRMODE2 = 0U, TIMER_SRC_INTER = 1U, TIMER_SRC_ITR0 = 2U, TIMER_SRC_ITR1 = 3U,
TIMER_SRC_ITR2 = 4U, TIMER_SRC_ITR3 = 5U, TIMER_SRC_TI1ED = 6U, TIMER_SRC_TI1 = 7U,
TIMER_SRC_TI2 = 8U, TIMER_SRC_ETRMODE1 = 9U
}
TIMER clock source. More...
enum timer_clock_polarity_t {
TIMER_CLK_POLARITY_INV = 1U, TIMER_CLK_POLARITY_NO_INV = 0U, TIMER_CLK_POLARITY_RISE = 0U, TIMER_CLK_POLARITY_FALL = 1U,
TIMER_CLK_POLARITY_BOTH = 3U
}
TIMER clock polarity. More...
enum timer_slave_mode_t {
TIMER_MODE_DISABLE = 0U, TIMER_MODE_ENC1 = 1U, TIMER_MODE_ENC2 = 2U, TIMER_MODE_ENC3 = 3U,
TIMER_MODE_RESET = 4U, TIMER_MODE_GATED = 5U, TIMER_MODE_TRIG = 6U, TIMER_MODE_EXTERNAL1 = 7U
}
TIMER slave mode. More...
enum timer_ts_t {
TIMER_TS_ITR0 = 0U, TIMER_TS_ITR1 = 1U, TIMER_TS_ITR2 = 2U, TIMER_TS_ITR3 = 3U,
TIMER_TS_TI1F_ED = 4U, TIMER_TS_TI1FP1 = 5U, TIMER_TS_TI2FP2 = 6U, TIMER_TS_ETRF = 7U
}
TIMER ts definition. More...
enum | timer_lock_level_t { TIMER_LOCK_LEVEL_OFF = 0U, TIMER_LOCK_LEVEL_1 = 1U, TIMER_LOCK_LEVEL_2 = 2U, TIMER_LOCK_LEVEL_3 = 3U }
TIMER lock level. More...
enum | timer_break_polarity_t { TIMER_BREAK_POLARITY_LOW = 0U, TIMER_BREAK_POLARITY_HIGH = 1U }
TIMER break polarity. More...
enum timer_master_mode_sel_t {
TIMER_TRGO_RESET = 0U, TIMER_TRGO_ENABLE = 1U, TIMER_TRGO_UPDATE = 2U, TIMER_TRGO_OC1 = 3U,
TIMER_TRGO_OC1REF = 4U, TIMER_TRGO_OC2REF = 5U, TIMER_TRGO_OC3REF = 6U, TIMER_TRGO_OC4REF = 7U
}
TIMER master mode selection. More...
enum timer_event_source_t {
TIMER_SRC_UPDATE = (1U << 0), TIMER_SRC_CC1 = (1U << 1), TIMER_SRC_CC2 = (1U << 2), TIMER_SRC_CC3 = (1U << 3),
TIMER_SRC_CC4 = (1U << 4), TIMER_SRC_COM = (1U << 5), TIMER_SRC_TRIG = (1U << 6), TIMER_SRC_BREAK = (1U << 7)
}
Specifies the event source. More...
enum timer_it_t {
TIMER_IT_UPDATE = (1U << 0), TIMER_IT_CC1 = (1U << 1), TIMER_IT_CC2 = (1U << 2), TIMER_IT_CC3 = (1U << 3),
TIMER_IT_CC4 = (1U << 4), TIMER_IT_COM = (1U << 5), TIMER_IT_TRIGGER = (1U << 6), TIMER_IT_BREAK = (1U << 7)
}
TIMER interrupt definition. More...
enum timer_dma_req_t {
TIMER_DMA_UPDATE = (1U << 0), TIMER_DMA_CC1 = (1U << 1), TIMER_DMA_CC2 = (1U << 2), TIMER_DMA_CC3 = (1U << 3),
TIMER_DMA_CC4 = (1U << 4), TIMER_DMA_COM = (1U << 5), TIMER_DMA_TRIGGER = (1U << 6)
}
TIMER DMA request. More...
enum timer_flag_t {
TIMER_FLAG_UPDATE = (1U << 0), TIMER_FLAG_CC1 = (1U << 1), TIMER_FLAG_CC2 = (1U << 2), TIMER_FLAG_CC3 = (1U << 3),
TIMER_FLAG_CC4 = (1U << 4), TIMER_FLAG_COM = (1U << 5), TIMER_FLAG_TRIGGER = (1U << 6), TIMER_FLAG_BREAK = (1U << 7),
TIMER_FLAG_CC1OF = (1U << 9), TIMER_FLAG_CC2OF = (1U << 10), TIMER_FLAG_CC3OF = (1U << 11), TIMER_FLAG_CC4OF = (1U << 12)
}
TIMER flag definition. More...

Detailed Description

Typedef Documentation

◆ timer_handle_t

typedef struct timer_handle_s timer_handle_t

TIMER time base handle structure definition.

Enumeration Type Documentation

◆ timer_active_channel_t

enum timer_active_channel_t

Active channel structures definition.

Enumerator
TIMER_ACTIVE_CHANNEL_1 | The active channel is 1
TIMER_ACTIVE_CHANNEL_2 | The active channel is 2
TIMER_ACTIVE_CHANNEL_3 | The active channel is 3
TIMER_ACTIVE_CHANNEL_4 | The active channel is 4
TIMER_ACTIVE_CHANNEL_CLEARED | All active channels cleared

Definition at line 171 of file ald_timer.h.

171 {
172 TIMER_ACTIVE_CHANNEL_1 = 0x01U,
173 TIMER_ACTIVE_CHANNEL_2 = 0x02U,
174 TIMER_ACTIVE_CHANNEL_3 = 0x04U,
175 TIMER_ACTIVE_CHANNEL_4 = 0x08U,
176 TIMER_ACTIVE_CHANNEL_CLEARED = 0x00U,
177 } timer_active_channel_t;
TIMER_ACTIVE_CHANNEL_3
Definition: ald_timer.h:174
TIMER_ACTIVE_CHANNEL_2
Definition: ald_timer.h:173
timer_active_channel_t
timer_active_channel_t
Active channel structures definition.
Definition: ald_timer.h:171
TIMER_ACTIVE_CHANNEL_CLEARED
Definition: ald_timer.h:176
TIMER_ACTIVE_CHANNEL_1
Definition: ald_timer.h:172
TIMER_ACTIVE_CHANNEL_4
Definition: ald_timer.h:175

◆ timer_break_polarity_t

enum timer_break_polarity_t

TIMER break polarity.

Enumerator
TIMER_BREAK_POLARITY_LOW | LOW
TIMER_BREAK_POLARITY_HIGH | HIGH

Definition at line 418 of file ald_timer.h.

418 {
419 TIMER_BREAK_POLARITY_LOW = 0U,
420 TIMER_BREAK_POLARITY_HIGH = 1U,
421 } timer_break_polarity_t;
timer_break_polarity_t
timer_break_polarity_t
TIMER break polarity.
Definition: ald_timer.h:418
TIMER_BREAK_POLARITY_LOW
Definition: ald_timer.h:419
TIMER_BREAK_POLARITY_HIGH
Definition: ald_timer.h:420

◆ timer_channel_t

enum timer_channel_t

TIMER channel.

Enumerator
TIMER_CHANNEL_1 | Channel 1
TIMER_CHANNEL_2 | Channel 2
TIMER_CHANNEL_3 | Channel 3
TIMER_CHANNEL_4 | Channel 4
TIMER_CHANNEL_ALL | All channel

Definition at line 109 of file ald_timer.h.

109 {
110 TIMER_CHANNEL_1 = 0U,
111 TIMER_CHANNEL_2 = 1U,
112 TIMER_CHANNEL_3 = 2U,
113 TIMER_CHANNEL_4 = 3U,
114 TIMER_CHANNEL_ALL = 0xFU,
115 } timer_channel_t;
TIMER_CHANNEL_3
Definition: ald_timer.h:112
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_CHANNEL_ALL
Definition: ald_timer.h:114
TIMER_CHANNEL_4
Definition: ald_timer.h:113
timer_channel_t
timer_channel_t
TIMER channel.
Definition: ald_timer.h:109
TIMER_CHANNEL_2
Definition: ald_timer.h:111

◆ timer_chnref_clr_sel_t

enum timer_chnref_clr_sel_t

TIMER CHnREF Clear Select.

Enumerator
TIMER_CHNREF_CLR_CMP_IN | Comparator CMP_IN
TIMER_CHNREF_CLR_ETF | External Trigger Signal ETF

Definition at line 306 of file ald_timer.h.

306 {
307 TIMER_CHNREF_CLR_CMP_IN = 0U,
308 TIMER_CHNREF_CLR_ETF = 1U,
309 }timer_chnref_clr_sel_t;
TIMER_CHNREF_CLR_ETF
Definition: ald_timer.h:308
TIMER_CHNREF_CLR_CMP_IN
Definition: ald_timer.h:307
timer_chnref_clr_sel_t
timer_chnref_clr_sel_t
TIMER CHnREF Clear Select.
Definition: ald_timer.h:306

◆ timer_clear_input_polarity_t

enum timer_clear_input_polarity_t

TIMER clear input polarity.

Enumerator
TIMER_POLARITY_NO_INV | Polarity for ETRx pin
TIMER_POLARITY_INV | Polarity for ETRx pin

Definition at line 290 of file ald_timer.h.

290 {
291 TIMER_POLARITY_NO_INV = 0U,
292 TIMER_POLARITY_INV = 1U,
293 } timer_clear_input_polarity_t;
TIMER_POLARITY_NO_INV
Definition: ald_timer.h:291
TIMER_POLARITY_INV
Definition: ald_timer.h:292
timer_clear_input_polarity_t
timer_clear_input_polarity_t
TIMER clear input polarity.
Definition: ald_timer.h:290

◆ timer_clear_input_source_t

enum timer_clear_input_source_t

TIMER clear input source.

Enumerator
TIMER_INPUT_NONE | Clear input none
TIMER_INPUT_ETR | Clear input etr

Definition at line 283 of file ald_timer.h.

283 {
284 TIMER_INPUT_NONE = 0U,
285 TIMER_INPUT_ETR = 1U,
286 } timer_clear_input_source_t;
TIMER_INPUT_NONE
Definition: ald_timer.h:284
TIMER_INPUT_ETR
Definition: ald_timer.h:285
timer_clear_input_source_t
timer_clear_input_source_t
TIMER clear input source.
Definition: ald_timer.h:283

◆ timer_clock_division_t

enum timer_clock_division_t

TIMER clock division.

Enumerator
TIMER_CLOCK_DIV1 | No prescaler is used
TIMER_CLOCK_DIV2 |
TIMER_CLOCK_DIV4 | Clock is divided by 2

Definition at line 54 of file ald_timer.h.

54 {
55 TIMER_CLOCK_DIV1 = 0U,
56 TIMER_CLOCK_DIV2 = 1U,
57 TIMER_CLOCK_DIV4 = 2U,
58 } timer_clock_division_t;
TIMER_CLOCK_DIV2
Definition: ald_timer.h:56
TIMER_CLOCK_DIV4
Definition: ald_timer.h:57
TIMER_CLOCK_DIV1
Definition: ald_timer.h:55
timer_clock_division_t
timer_clock_division_t
TIMER clock division.
Definition: ald_timer.h:54

◆ timer_clock_polarity_t

enum timer_clock_polarity_t

TIMER clock polarity.

Enumerator
TIMER_CLK_POLARITY_INV | Polarity for ETRx clock sources
TIMER_CLK_POLARITY_NO_INV | Polarity for ETRx clock sources
TIMER_CLK_POLARITY_RISE | Polarity for TIx clock sources
TIMER_CLK_POLARITY_FALL | Polarity for TIx clock sources
TIMER_CLK_POLARITY_BOTH | Polarity for TIx clock sources

Definition at line 338 of file ald_timer.h.

338 {
339 TIMER_CLK_POLARITY_INV = 1U,
340 TIMER_CLK_POLARITY_NO_INV = 0U,
341 TIMER_CLK_POLARITY_RISE = 0U,
342 TIMER_CLK_POLARITY_FALL = 1U,
343 TIMER_CLK_POLARITY_BOTH = 3U,
344 } timer_clock_polarity_t;
TIMER_CLK_POLARITY_INV
Definition: ald_timer.h:339
timer_clock_polarity_t
timer_clock_polarity_t
TIMER clock polarity.
Definition: ald_timer.h:338
TIMER_CLK_POLARITY_FALL
Definition: ald_timer.h:342
TIMER_CLK_POLARITY_RISE
Definition: ald_timer.h:341
TIMER_CLK_POLARITY_NO_INV
Definition: ald_timer.h:340
TIMER_CLK_POLARITY_BOTH
Definition: ald_timer.h:343

◆ timer_clock_source_t

enum timer_clock_source_t

TIMER clock source.

Enumerator
TIMER_SRC_ETRMODE2 | Clock source is etr mode2
TIMER_SRC_INTER | Clock source is etr internal
TIMER_SRC_ITR0 | Clock source is etr itr0
TIMER_SRC_ITR1 | Clock source is etr itr1
TIMER_SRC_ITR2 | Clock source is etr itr2
TIMER_SRC_ITR3 | Clock source is etr itr3
TIMER_SRC_TI1ED | Clock source is etr ti1ed
TIMER_SRC_TI1 | Clock source is etr ti1
TIMER_SRC_TI2 | Clock source is etr ti2
TIMER_SRC_ETRMODE1 | Clock source is etr mode1

Definition at line 323 of file ald_timer.h.

323 {
324 TIMER_SRC_ETRMODE2 = 0U,
325 TIMER_SRC_INTER = 1U,
326 TIMER_SRC_ITR0 = 2U,
327 TIMER_SRC_ITR1 = 3U,
328 TIMER_SRC_ITR2 = 4U,
329 TIMER_SRC_ITR3 = 5U,
330 TIMER_SRC_TI1ED = 6U,
331 TIMER_SRC_TI1 = 7U,
332 TIMER_SRC_TI2 = 8U,
333 TIMER_SRC_ETRMODE1 = 9U,
334 } timer_clock_source_t;
TIMER_SRC_ITR1
Definition: ald_timer.h:327
TIMER_SRC_INTER
Definition: ald_timer.h:325
TIMER_SRC_ETRMODE1
Definition: ald_timer.h:333
timer_clock_source_t
timer_clock_source_t
TIMER clock source.
Definition: ald_timer.h:323
TIMER_SRC_ITR3
Definition: ald_timer.h:329
TIMER_SRC_TI1
Definition: ald_timer.h:331
TIMER_SRC_ITR2
Definition: ald_timer.h:328
TIMER_SRC_TI2
Definition: ald_timer.h:332
TIMER_SRC_ETRMODE2
Definition: ald_timer.h:324
TIMER_SRC_ITR0
Definition: ald_timer.h:326
TIMER_SRC_TI1ED
Definition: ald_timer.h:330

◆ timer_cnt_mode_t

enum timer_cnt_mode_t

TIMER counter mode.

Enumerator
TIMER_CNT_MODE_UP | Counter mode up
TIMER_CNT_MODE_DOWN | Counter mode down
TIMER_CNT_MODE_CENTER1 | Counter mode center1
TIMER_CNT_MODE_CENTER2 | Counter mode center2
TIMER_CNT_MODE_CENTER3 | Counter mode center3

Definition at line 43 of file ald_timer.h.

43 {
44 TIMER_CNT_MODE_UP = 0U,
45 TIMER_CNT_MODE_DOWN = 1U,
46 TIMER_CNT_MODE_CENTER1 = 2U,
47 TIMER_CNT_MODE_CENTER2 = 3U,
48 TIMER_CNT_MODE_CENTER3 = 4U,
49 } timer_cnt_mode_t;
TIMER_CNT_MODE_CENTER2
Definition: ald_timer.h:47
TIMER_CNT_MODE_CENTER3
Definition: ald_timer.h:48
timer_cnt_mode_t
timer_cnt_mode_t
TIMER counter mode.
Definition: ald_timer.h:43
TIMER_CNT_MODE_CENTER1
Definition: ald_timer.h:46
TIMER_CNT_MODE_UP
Definition: ald_timer.h:44
TIMER_CNT_MODE_DOWN
Definition: ald_timer.h:45

◆ timer_dma_req_t

enum timer_dma_req_t

TIMER DMA request.

Enumerator
TIMER_DMA_UPDATE | DMA request from update
TIMER_DMA_CC1 | DMA request from channel1
TIMER_DMA_CC2 | DMA request from channel2
TIMER_DMA_CC3 | DMA request from channel3
TIMER_DMA_CC4 | DMA request from channel4
TIMER_DMA_COM | DMA request from compare
TIMER_DMA_TRIGGER | DMA request from trigger

Definition at line 505 of file ald_timer.h.

505 {
506 TIMER_DMA_UPDATE = (1U << 0),
507 TIMER_DMA_CC1 = (1U << 1),
508 TIMER_DMA_CC2 = (1U << 2),
509 TIMER_DMA_CC3 = (1U << 3),
510 TIMER_DMA_CC4 = (1U << 4),
511 TIMER_DMA_COM = (1U << 5),
512 TIMER_DMA_TRIGGER = (1U << 6),
513 } timer_dma_req_t;
TIMER_DMA_TRIGGER
Definition: ald_timer.h:512
TIMER_DMA_CC2
Definition: ald_timer.h:508
TIMER_DMA_UPDATE
Definition: ald_timer.h:506
timer_dma_req_t
timer_dma_req_t
TIMER DMA request.
Definition: ald_timer.h:505
TIMER_DMA_CC3
Definition: ald_timer.h:509
TIMER_DMA_COM
Definition: ald_timer.h:511
TIMER_DMA_CC1
Definition: ald_timer.h:507
TIMER_DMA_CC4
Definition: ald_timer.h:510

◆ timer_encoder_mode_t

enum timer_encoder_mode_t

TIMER encoder mode.

Enumerator
TIMER_ENC_MODE_TI1 | encoder mode 1
TIMER_ENC_MODE_TI2 | encoder mode 2
TIMER_ENC_MODE_TI12 | encoder mode 3

Definition at line 208 of file ald_timer.h.

208 {
209 TIMER_ENC_MODE_TI1 = 1U,
210 TIMER_ENC_MODE_TI2 = 2U,
211 TIMER_ENC_MODE_TI12 = 3U,
212 } timer_encoder_mode_t;
TIMER_ENC_MODE_TI1
Definition: ald_timer.h:209
timer_encoder_mode_t
timer_encoder_mode_t
TIMER encoder mode.
Definition: ald_timer.h:208
TIMER_ENC_MODE_TI2
Definition: ald_timer.h:210
TIMER_ENC_MODE_TI12
Definition: ald_timer.h:211

◆ timer_etr_psc_t

enum timer_etr_psc_t

TIMER clear input polarity.

Enumerator
TIMER_ETR_PSC_DIV1 | No prescaler is used
TIMER_ETR_PSC_DIV2 | ETR input source is divided by 2
TIMER_ETR_PSC_DIV4 | ETR input source is divided by 4
TIMER_ETR_PSC_DIV8 | ETR input source is divided by 8

Definition at line 297 of file ald_timer.h.

297 {
298 TIMER_ETR_PSC_DIV1 = 0U,
299 TIMER_ETR_PSC_DIV2 = 1U,
300 TIMER_ETR_PSC_DIV4 = 2U,
301 TIMER_ETR_PSC_DIV8 = 3U,
302 } timer_etr_psc_t;
TIMER_ETR_PSC_DIV1
Definition: ald_timer.h:298
timer_etr_psc_t
timer_etr_psc_t
TIMER clear input polarity.
Definition: ald_timer.h:297
TIMER_ETR_PSC_DIV2
Definition: ald_timer.h:299
TIMER_ETR_PSC_DIV4
Definition: ald_timer.h:300
TIMER_ETR_PSC_DIV8
Definition: ald_timer.h:301

◆ timer_event_source_t

enum timer_event_source_t

Specifies the event source.

Enumerator
TIMER_SRC_UPDATE | Event source is update
TIMER_SRC_CC1 | Event source is channel1
TIMER_SRC_CC2 | Event source is channel2
TIMER_SRC_CC3 | Event source is channel3
TIMER_SRC_CC4 | Event source is channel4
TIMER_SRC_COM | Event source is compare
TIMER_SRC_TRIG | Event source is trigger
TIMER_SRC_BREAK | Event source is break

Definition at line 477 of file ald_timer.h.

477 {
478 TIMER_SRC_UPDATE = (1U << 0),
479 TIMER_SRC_CC1 = (1U << 1),
480 TIMER_SRC_CC2 = (1U << 2),
481 TIMER_SRC_CC3 = (1U << 3),
482 TIMER_SRC_CC4 = (1U << 4),
483 TIMER_SRC_COM = (1U << 5),
484 TIMER_SRC_TRIG = (1U << 6),
485 TIMER_SRC_BREAK = (1U << 7),
486 } timer_event_source_t;
TIMER_SRC_UPDATE
Definition: ald_timer.h:478
TIMER_SRC_CC4
Definition: ald_timer.h:482
TIMER_SRC_CC2
Definition: ald_timer.h:480
TIMER_SRC_CC3
Definition: ald_timer.h:481
TIMER_SRC_CC1
Definition: ald_timer.h:479
timer_event_source_t
timer_event_source_t
Specifies the event source.
Definition: ald_timer.h:477
TIMER_SRC_TRIG
Definition: ald_timer.h:484
TIMER_SRC_BREAK
Definition: ald_timer.h:485
TIMER_SRC_COM
Definition: ald_timer.h:483

◆ timer_flag_t

enum timer_flag_t

TIMER flag definition.

Enumerator
TIMER_FLAG_UPDATE | Update interrupt flag
TIMER_FLAG_CC1 | Channel1 interrupt flag
TIMER_FLAG_CC2 | Channel2 interrupt flag
TIMER_FLAG_CC3 | Channel3 interrupt flag
TIMER_FLAG_CC4 | Channel4 interrupt flag
TIMER_FLAG_COM | Compare interrupt flag
TIMER_FLAG_TRIGGER | Trigger interrupt flag
TIMER_FLAG_BREAK | Break interrupt flag
TIMER_FLAG_CC1OF | Channel1 override state flag
TIMER_FLAG_CC2OF | Channel2 override state flag
TIMER_FLAG_CC3OF | Channel3 override state flag
TIMER_FLAG_CC4OF | Channel4 override state flag

Definition at line 518 of file ald_timer.h.

518 {
519 TIMER_FLAG_UPDATE = (1U << 0),
520 TIMER_FLAG_CC1 = (1U << 1),
521 TIMER_FLAG_CC2 = (1U << 2),
522 TIMER_FLAG_CC3 = (1U << 3),
523 TIMER_FLAG_CC4 = (1U << 4),
524 TIMER_FLAG_COM = (1U << 5),
525 TIMER_FLAG_TRIGGER = (1U << 6),
526 TIMER_FLAG_BREAK = (1U << 7),
527 TIMER_FLAG_CC1OF = (1U << 9),
528 TIMER_FLAG_CC2OF = (1U << 10),
529 TIMER_FLAG_CC3OF = (1U << 11),
530 TIMER_FLAG_CC4OF = (1U << 12),
531 } timer_flag_t;
TIMER_FLAG_CC1OF
Definition: ald_timer.h:527
TIMER_FLAG_CC1
Definition: ald_timer.h:520
TIMER_FLAG_CC3
Definition: ald_timer.h:522
TIMER_FLAG_CC4
Definition: ald_timer.h:523
timer_flag_t
timer_flag_t
TIMER flag definition.
Definition: ald_timer.h:518
TIMER_FLAG_TRIGGER
Definition: ald_timer.h:525
TIMER_FLAG_CC3OF
Definition: ald_timer.h:529
TIMER_FLAG_CC2
Definition: ald_timer.h:521
TIMER_FLAG_BREAK
Definition: ald_timer.h:526
TIMER_FLAG_COM
Definition: ald_timer.h:524
TIMER_FLAG_UPDATE
Definition: ald_timer.h:519
TIMER_FLAG_CC2OF
Definition: ald_timer.h:528
TIMER_FLAG_CC4OF
Definition: ald_timer.h:530

◆ timer_ic_polarity_t

enum timer_ic_polarity_t

TIMER input capture polarity.

Enumerator
TIMER_IC_POLARITY_RISE | Input capture polarity rising
TIMER_IC_POLARITY_FALL | Input capture polarity falling

Definition at line 217 of file ald_timer.h.

217 {
218 TIMER_IC_POLARITY_RISE = 0U,
219 TIMER_IC_POLARITY_FALL = 1U,
220 } timer_ic_polarity_t;
timer_ic_polarity_t
timer_ic_polarity_t
TIMER input capture polarity.
Definition: ald_timer.h:217
TIMER_IC_POLARITY_RISE
Definition: ald_timer.h:218
TIMER_IC_POLARITY_FALL
Definition: ald_timer.h:219

◆ timer_ic_prescaler_t

enum timer_ic_prescaler_t

TIMER input capture prescaler.

Enumerator
TIMER_IC_PSC_DIV1 | Capture performed once every 1 events
TIMER_IC_PSC_DIV2 | Capture performed once every 2 events
TIMER_IC_PSC_DIV4 | Capture performed once every 4 events
TIMER_IC_PSC_DIV8 | Capture performed once every 4 events

Definition at line 234 of file ald_timer.h.

234 {
235 TIMER_IC_PSC_DIV1 = 0U,
236 TIMER_IC_PSC_DIV2 = 1U,
237 TIMER_IC_PSC_DIV4 = 2U,
238 TIMER_IC_PSC_DIV8 = 3U,
239 } timer_ic_prescaler_t;
timer_ic_prescaler_t
timer_ic_prescaler_t
TIMER input capture prescaler.
Definition: ald_timer.h:234
TIMER_IC_PSC_DIV4
Definition: ald_timer.h:237
TIMER_IC_PSC_DIV2
Definition: ald_timer.h:236
TIMER_IC_PSC_DIV8
Definition: ald_timer.h:238
TIMER_IC_PSC_DIV1
Definition: ald_timer.h:235

◆ timer_ic_select_t

enum timer_ic_select_t

TIMER input capture selection.

Enumerator
TIMER_IC_SEL_DIRECT | IC1 – TI1
TIMER_IC_SEL_INDIRECT | IC1 – TI2
TIMER_IC_SEL_TRC | IC1 – TRC

Definition at line 225 of file ald_timer.h.

225 {
226 TIMER_IC_SEL_DIRECT = 1U,
227 TIMER_IC_SEL_INDIRECT = 2U,
228 TIMER_IC_SEL_TRC = 3U,
229 } timer_ic_select_t;
TIMER_IC_SEL_DIRECT
Definition: ald_timer.h:226
TIMER_IC_SEL_TRC
Definition: ald_timer.h:228
TIMER_IC_SEL_INDIRECT
Definition: ald_timer.h:227
timer_ic_select_t
timer_ic_select_t
TIMER input capture selection.
Definition: ald_timer.h:225

◆ timer_it_t

enum timer_it_t

TIMER interrupt definition.

Enumerator
TIMER_IT_UPDATE | Update interrupt bit
TIMER_IT_CC1 | Channel1 interrupt bit
TIMER_IT_CC2 | Channel2 interrupt bit
TIMER_IT_CC3 | Channel3 interrupt bit
TIMER_IT_CC4 | Channel4 interrupt bit
TIMER_IT_COM | compare interrupt bit
TIMER_IT_TRIGGER | Trigger interrupt bit
TIMER_IT_BREAK | Break interrupt bit

Definition at line 491 of file ald_timer.h.

491 {
492 TIMER_IT_UPDATE = (1U << 0),
493 TIMER_IT_CC1 = (1U << 1),
494 TIMER_IT_CC2 = (1U << 2),
495 TIMER_IT_CC3 = (1U << 3),
496 TIMER_IT_CC4 = (1U << 4),
497 TIMER_IT_COM = (1U << 5),
498 TIMER_IT_TRIGGER = (1U << 6),
499 TIMER_IT_BREAK = (1U << 7),
500 } timer_it_t;
TIMER_IT_CC1
Definition: ald_timer.h:493
TIMER_IT_CC4
Definition: ald_timer.h:496
TIMER_IT_CC2
Definition: ald_timer.h:494
timer_it_t
timer_it_t
TIMER interrupt definition.
Definition: ald_timer.h:491
TIMER_IT_BREAK
Definition: ald_timer.h:499
TIMER_IT_CC3
Definition: ald_timer.h:495
TIMER_IT_TRIGGER
Definition: ald_timer.h:498
TIMER_IT_UPDATE
Definition: ald_timer.h:492
TIMER_IT_COM
Definition: ald_timer.h:497

◆ timer_lock_level_t

enum timer_lock_level_t

TIMER lock level.

Enumerator
TIMER_LOCK_LEVEL_OFF | Lock off
TIMER_LOCK_LEVEL_1 | Lock level 1
TIMER_LOCK_LEVEL_2 | Lock level 2
TIMER_LOCK_LEVEL_3 | Lock level 3

Definition at line 408 of file ald_timer.h.

408 {
409 TIMER_LOCK_LEVEL_OFF = 0U,
410 TIMER_LOCK_LEVEL_1 = 1U,
411 TIMER_LOCK_LEVEL_2 = 2U,
412 TIMER_LOCK_LEVEL_3 = 3U,
413 } timer_lock_level_t;
timer_lock_level_t
timer_lock_level_t
TIMER lock level.
Definition: ald_timer.h:408
TIMER_LOCK_LEVEL_OFF
Definition: ald_timer.h:409
TIMER_LOCK_LEVEL_3
Definition: ald_timer.h:412
TIMER_LOCK_LEVEL_1
Definition: ald_timer.h:410
TIMER_LOCK_LEVEL_2
Definition: ald_timer.h:411

◆ timer_master_mode_sel_t

enum timer_master_mode_sel_t

TIMER master mode selection.

Enumerator
TIMER_TRGO_RESET | RESET
TIMER_TRGO_ENABLE | ENABLE
TIMER_TRGO_UPDATE | UPDATE
TIMER_TRGO_OC1 | OC1
TIMER_TRGO_OC1REF | OC1REF
TIMER_TRGO_OC2REF | OC2REF
TIMER_TRGO_OC3REF | OC3REF
TIMER_TRGO_OC4REF | OC4REF

Definition at line 455 of file ald_timer.h.

455 {
456 TIMER_TRGO_RESET = 0U,
457 TIMER_TRGO_ENABLE = 1U,
458 TIMER_TRGO_UPDATE = 2U,
459 TIMER_TRGO_OC1 = 3U,
460 TIMER_TRGO_OC1REF = 4U,
461 TIMER_TRGO_OC2REF = 5U,
462 TIMER_TRGO_OC3REF = 6U,
463 TIMER_TRGO_OC4REF = 7U,
464 } timer_master_mode_sel_t;
TIMER_TRGO_OC4REF
Definition: ald_timer.h:463
TIMER_TRGO_OC2REF
Definition: ald_timer.h:461
TIMER_TRGO_UPDATE
Definition: ald_timer.h:458
TIMER_TRGO_RESET
Definition: ald_timer.h:456
TIMER_TRGO_ENABLE
Definition: ald_timer.h:457
TIMER_TRGO_OC1
Definition: ald_timer.h:459
TIMER_TRGO_OC3REF
Definition: ald_timer.h:462
timer_master_mode_sel_t
timer_master_mode_sel_t
TIMER master mode selection.
Definition: ald_timer.h:455
TIMER_TRGO_OC1REF
Definition: ald_timer.h:460

◆ timer_oc_idle_t

enum timer_oc_idle_t

TIMER output compare idle state.

Enumerator
TIMER_OC_IDLE_RESET | Output compare idle state is reset
TIMER_OC_IDLE_SET | Output compare idle state is set

Definition at line 93 of file ald_timer.h.

93 {
94 TIMER_OC_IDLE_RESET = 0U,
95 TIMER_OC_IDLE_SET = 1U,
96 } timer_oc_idle_t;
timer_oc_idle_t
timer_oc_idle_t
TIMER output compare idle state.
Definition: ald_timer.h:93
TIMER_OC_IDLE_RESET
Definition: ald_timer.h:94
TIMER_OC_IDLE_SET
Definition: ald_timer.h:95

◆ timer_oc_mode_t

enum timer_oc_mode_t

TIMER output compare and PWM modes.

Enumerator
TIMER_OC_MODE_TIMERING | Output compare mode is timering
TIMER_OC_MODE_ACTIVE | Output compare mode is active
TIMER_OC_MODE_INACTIVE | Output compare mode is inactive
TIMER_OC_MODE_TOGGLE | Output compare mode is toggle
TIMER_OC_MODE_FORCE_INACTIVE | Output compare mode is force inactive
TIMER_OC_MODE_FORCE_ACTIVE | Output compare mode is force active
TIMER_OC_MODE_PWM1 | Output compare mode is pwm1
TIMER_OC_MODE_PWM2 | Output compare mode is pwm2

Definition at line 63 of file ald_timer.h.

63 {
64 TIMER_OC_MODE_TIMERING = 0U,
65 TIMER_OC_MODE_ACTIVE = 1U,
66 TIMER_OC_MODE_INACTIVE = 2U,
67 TIMER_OC_MODE_TOGGLE = 3U,
68 TIMER_OC_MODE_FORCE_INACTIVE = 4U,
69 TIMER_OC_MODE_FORCE_ACTIVE = 5U,
70 TIMER_OC_MODE_PWM1 = 6U,
71 TIMER_OC_MODE_PWM2 = 7U,
72 } timer_oc_mode_t;
TIMER_OC_MODE_PWM2
Definition: ald_timer.h:71
TIMER_OC_MODE_ACTIVE
Definition: ald_timer.h:65
TIMER_OC_MODE_PWM1
Definition: ald_timer.h:70
TIMER_OC_MODE_INACTIVE
Definition: ald_timer.h:66
TIMER_OC_MODE_FORCE_INACTIVE
Definition: ald_timer.h:68
timer_oc_mode_t
timer_oc_mode_t
TIMER output compare and PWM modes.
Definition: ald_timer.h:63
TIMER_OC_MODE_TOGGLE
Definition: ald_timer.h:67
TIMER_OC_MODE_FORCE_ACTIVE
Definition: ald_timer.h:69
TIMER_OC_MODE_TIMERING
Definition: ald_timer.h:64

◆ timer_oc_polarity_t

enum timer_oc_polarity_t

TIMER output compare polarity.

Enumerator
TIMER_OC_POLARITY_HIGH | Output compare polarity is high
TIMER_OC_POLARITY_LOW | Output compare polarity is low

Definition at line 77 of file ald_timer.h.

77 {
78 TIMER_OC_POLARITY_HIGH = 0U,
79 TIMER_OC_POLARITY_LOW = 1U,
80 } timer_oc_polarity_t;
timer_oc_polarity_t
timer_oc_polarity_t
TIMER output compare polarity.
Definition: ald_timer.h:77
TIMER_OC_POLARITY_HIGH
Definition: ald_timer.h:78
TIMER_OC_POLARITY_LOW
Definition: ald_timer.h:79

◆ timer_ocn_idle_t

enum timer_ocn_idle_t

TIMER complementary output compare idle state.

Enumerator
TIMER_OCN_IDLE_RESET | Complementary output compare idle state is reset
TIMER_OCN_IDLE_SET | Complementary output compare idle state is set

Definition at line 101 of file ald_timer.h.

101 {
102 TIMER_OCN_IDLE_RESET = 0U,
103 TIMER_OCN_IDLE_SET = 1U,
104 } timer_ocn_idle_t;
TIMER_OCN_IDLE_SET
Definition: ald_timer.h:103
timer_ocn_idle_t
timer_ocn_idle_t
TIMER complementary output compare idle state.
Definition: ald_timer.h:101
TIMER_OCN_IDLE_RESET
Definition: ald_timer.h:102

◆ timer_ocn_polarity_t

enum timer_ocn_polarity_t

TIMER complementary output compare polarity.

Enumerator
TIMER_OCN_POLARITY_HIGH | Complementary output compare polarity is high
TIMER_OCN_POLARITY_LOW | Complementary output compare polarity is low

Definition at line 85 of file ald_timer.h.

85 {
86 TIMER_OCN_POLARITY_HIGH = 0U,
87 TIMER_OCN_POLARITY_LOW = 1U,
88 } timer_ocn_polarity_t;
TIMER_OCN_POLARITY_HIGH
Definition: ald_timer.h:86
timer_ocn_polarity_t
timer_ocn_polarity_t
TIMER complementary output compare polarity.
Definition: ald_timer.h:85
TIMER_OCN_POLARITY_LOW
Definition: ald_timer.h:87

◆ timer_op_mode_t

enum timer_op_mode_t

TIMER one pulse mode.

Enumerator
TIMER_OP_MODE_REPEAT | Repetitive
TIMER_OP_MODE_SINGLE | single

Definition at line 120 of file ald_timer.h.

120 {
121 TIMER_OP_MODE_REPEAT = 0U,
122 TIMER_OP_MODE_SINGLE = 1U,
123 } timer_op_mode_t;
timer_op_mode_t
timer_op_mode_t
TIMER one pulse mode.
Definition: ald_timer.h:120
TIMER_OP_MODE_REPEAT
Definition: ald_timer.h:121
TIMER_OP_MODE_SINGLE
Definition: ald_timer.h:122

◆ timer_op_output_channel_t

enum timer_op_output_channel_t

TIMER one pulse output channel.

Enumerator
TIMER_OP_OUTPUT_CHANNEL_1 | One pulse output channal 1
TIMER_OP_OUTPUT_CHANNEL_2 | One pulse output channal 2

Definition at line 128 of file ald_timer.h.

128 {
129 TIMER_OP_OUTPUT_CHANNEL_1 = 0U,
130 TIMER_OP_OUTPUT_CHANNEL_2 = 1U,
131 } timer_op_output_channel_t;
TIMER_OP_OUTPUT_CHANNEL_1
Definition: ald_timer.h:129
timer_op_output_channel_t
timer_op_output_channel_t
TIMER one pulse output channel.
Definition: ald_timer.h:128
TIMER_OP_OUTPUT_CHANNEL_2
Definition: ald_timer.h:130

◆ timer_slave_mode_t

enum timer_slave_mode_t

TIMER slave mode.

Enumerator
TIMER_MODE_DISABLE | Slave mode is disable
TIMER_MODE_ENC1 | Slave mode is encoder1
TIMER_MODE_ENC2 | Slave mode is encoder2
TIMER_MODE_ENC3 | Slave mode is encoder3
TIMER_MODE_RESET | Slave mode is reset
TIMER_MODE_GATED | Slave mode is gated
TIMER_MODE_TRIG | Slave mode is trigger
TIMER_MODE_EXTERNAL1 | Slave mode is external1

Definition at line 359 of file ald_timer.h.

359 {
360 TIMER_MODE_DISABLE = 0U,
361 TIMER_MODE_ENC1 = 1U,
362 TIMER_MODE_ENC2 = 2U,
363 TIMER_MODE_ENC3 = 3U,
364 TIMER_MODE_RESET = 4U,
365 TIMER_MODE_GATED = 5U,
366 TIMER_MODE_TRIG = 6U,
367 TIMER_MODE_EXTERNAL1 = 7U,
368 } timer_slave_mode_t;
timer_slave_mode_t
timer_slave_mode_t
TIMER slave mode.
Definition: ald_timer.h:359
TIMER_MODE_GATED
Definition: ald_timer.h:365
TIMER_MODE_DISABLE
Definition: ald_timer.h:360
TIMER_MODE_RESET
Definition: ald_timer.h:364
TIMER_MODE_TRIG
Definition: ald_timer.h:366
TIMER_MODE_EXTERNAL1
Definition: ald_timer.h:367
TIMER_MODE_ENC3
Definition: ald_timer.h:363
TIMER_MODE_ENC1
Definition: ald_timer.h:361
TIMER_MODE_ENC2
Definition: ald_timer.h:362

◆ timer_state_t

enum timer_state_t

State structures definition.

Enumerator
TIMER_STATE_RESET | Peripheral not yet initialized or disabled
TIMER_STATE_READY | Peripheral Initialized and ready for use
TIMER_STATE_BUSY | An internal process is ongoing
TIMER_STATE_TIMEREOUT | Timeout state
TIMER_STATE_ERROR | Reception process is ongoing

Definition at line 160 of file ald_timer.h.

160 {
161 TIMER_STATE_RESET = 0x00U,
162 TIMER_STATE_READY = 0x01U,
163 TIMER_STATE_BUSY = 0x02U,
164 TIMER_STATE_TIMEREOUT = 0x03U,
165 TIMER_STATE_ERROR = 0x04U,
166 } timer_state_t;
TIMER_STATE_RESET
Definition: ald_timer.h:161
TIMER_STATE_READY
Definition: ald_timer.h:162
TIMER_STATE_BUSY
Definition: ald_timer.h:163
TIMER_STATE_TIMEREOUT
Definition: ald_timer.h:164
timer_state_t
timer_state_t
State structures definition.
Definition: ald_timer.h:160
TIMER_STATE_ERROR
Definition: ald_timer.h:165

◆ timer_ts_t

enum timer_ts_t

TIMER ts definition.

Enumerator
TIMER_TS_ITR0 | ITR0
TIMER_TS_ITR1 | ITR1
TIMER_TS_ITR2 | ITR2
TIMER_TS_ITR3 | ITR3
TIMER_TS_TI1F_ED | TI1F_ED
TIMER_TS_TI1FP1 | TI1FP1
TIMER_TS_TI2FP2 | TI2FP2
TIMER_TS_ETRF | ETRF

Definition at line 373 of file ald_timer.h.

373 {
374 TIMER_TS_ITR0 = 0U,
375 TIMER_TS_ITR1 = 1U,
376 TIMER_TS_ITR2 = 2U,
377 TIMER_TS_ITR3 = 3U,
378 TIMER_TS_TI1F_ED = 4U,
379 TIMER_TS_TI1FP1 = 5U,
380 TIMER_TS_TI2FP2 = 6U,
381 TIMER_TS_ETRF = 7U,
382 } timer_ts_t;
timer_ts_t
timer_ts_t
TIMER ts definition.
Definition: ald_timer.h:373
TIMER_TS_TI1FP1
Definition: ald_timer.h:379
TIMER_TS_TI1F_ED
Definition: ald_timer.h:378
TIMER_TS_ETRF
Definition: ald_timer.h:381
TIMER_TS_TI2FP2
Definition: ald_timer.h:380
TIMER_TS_ITR2
Definition: ald_timer.h:376
TIMER_TS_ITR1
Definition: ald_timer.h:375
TIMER_TS_ITR0
Definition: ald_timer.h:374
TIMER_TS_ITR3
Definition: ald_timer.h:377


ALD User Manual: timer_base_init_t Struct Reference

Data Fields
timer_base_init_t Struct Reference
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Types

TIMER time base configuration structure definition. More...

#include <ald_timer.h>

Data Fields

uint32_t | prescaler
timer_cnt_mode_t mode
uint32_t | period
timer_clock_division_t clk_div
uint32_t | re_cnt

Detailed Description

TIMER time base configuration structure definition.

Definition at line 136 of file ald_timer.h.

Field Documentation

◆ clk_div

timer_clock_division_t clk_div

Specifies the clock division.

Definition at line 140 of file ald_timer.h.

◆ mode

timer_cnt_mode_t mode

Specifies the counter mode.

Definition at line 138 of file ald_timer.h.

◆ period

uint32_t period

Specifies the period value to be loaded into ARR at the next update event.

Definition at line 139 of file ald_timer.h.

◆ prescaler

uint32_t prescaler

Specifies the prescaler value used to divide the TIMER clock.

Definition at line 137 of file ald_timer.h.

◆ re_cnt

uint32_t re_cnt

Specifies the repetition counter value.

Definition at line 141 of file ald_timer.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_timer.h


ALD User Manual: timer_oc_init_t Struct Reference

Data Fields
timer_oc_init_t Struct Reference
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Types

TIMER output compare configuration structure definition. More...

#include <ald_timer.h>

Data Fields

timer_oc_mode_t oc_mode
uint32_t pulse
timer_oc_polarity_t oc_polarity
timer_ocn_polarity_t ocn_polarity
type_func_t oc_fast_en
timer_oc_idle_t oc_idle
timer_ocn_idle_t ocn_idle

Detailed Description

TIMER output compare configuration structure definition.

Definition at line 147 of file ald_timer.h.

Field Documentation

◆ oc_fast_en

type_func_t oc_fast_en

Specifies the Fast mode state.

Definition at line 152 of file ald_timer.h.

◆ oc_idle

timer_oc_idle_t oc_idle

Specifies the TIMER Output Compare pin state during Idle state.

Definition at line 153 of file ald_timer.h.

◆ oc_mode

timer_oc_mode_t oc_mode

Specifies the TIMER mode.

Definition at line 148 of file ald_timer.h.

◆ oc_polarity

timer_oc_polarity_t oc_polarity

Specifies the output polarity.

Definition at line 150 of file ald_timer.h.

◆ ocn_idle

timer_ocn_idle_t ocn_idle

Specifies the TIMER Output Compare pin state during Idle state.

Definition at line 154 of file ald_timer.h.

◆ ocn_polarity

timer_ocn_polarity_t ocn_polarity

Specifies the complementary output polarity.

Definition at line 151 of file ald_timer.h.

◆ pulse

uint32_t pulse

Specifies the pulse value to be loaded into the Capture Compare Register.

Definition at line 149 of file ald_timer.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_timer.h


ALD User Manual: timer_handle_s Struct Reference

Data Fields
timer_handle_s Struct Reference
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Types

TIMER time base handle structure definition. More...

#include <ald_timer.h>

Collaboration diagram for timer_handle_s:
[legend]

Data Fields

TIMER_TypeDef * | perh
timer_base_init_t init
timer_active_channel_t ch
lock_state_t lock
timer_state_t state
dma_handle_t hdma1
dma_handle_t hdma2
void(* | period_elapse_cbk )(struct timer_handle_s *arg)
void(* | delay_elapse_cbk )(struct timer_handle_s *arg)
void(* | capture_cbk )(struct timer_handle_s *arg)
void(* | pwm_pulse_finish_cbk )(struct timer_handle_s *arg)
void(* | trigger_cbk )(struct timer_handle_s *arg)
void(* | break_cbk )(struct timer_handle_s *arg)
void(* | com_cbk )(struct timer_handle_s *arg)
void(* | error_cbk )(struct timer_handle_s *arg)

Detailed Description

TIMER time base handle structure definition.

Definition at line 182 of file ald_timer.h.

Field Documentation

◆ break_cbk

void(* break_cbk) (struct timer_handle_s *arg)

Break callback

Definition at line 199 of file ald_timer.h.

◆ capture_cbk

void(* capture_cbk) (struct timer_handle_s *arg)

Capture callback

Definition at line 196 of file ald_timer.h.

◆ ch

timer_active_channel_t ch

Active channel

Definition at line 185 of file ald_timer.h.

◆ com_cbk

void(* com_cbk) (struct timer_handle_s *arg)

commutation callback

Definition at line 200 of file ald_timer.h.

◆ delay_elapse_cbk

void(* delay_elapse_cbk) (struct timer_handle_s *arg)

Delay_elapse callback

Definition at line 195 of file ald_timer.h.

◆ error_cbk

void(* error_cbk) (struct timer_handle_s *arg)

Error callback

Definition at line 201 of file ald_timer.h.

◆ hdma1

dma_handle_t hdma1

Timer DMA handle parameters

Definition at line 190 of file ald_timer.h.

◆ hdma2

dma_handle_t hdma2

Definition at line 191 of file ald_timer.h.

◆ init

timer_base_init_t init

TIMER Time Base required parameters

Definition at line 184 of file ald_timer.h.

◆ lock

lock_state_t lock

Locking object

Definition at line 186 of file ald_timer.h.

◆ perh

TIMER_TypeDef* perh

Register base address

Definition at line 183 of file ald_timer.h.

◆ period_elapse_cbk

void(* period_elapse_cbk) (struct timer_handle_s *arg)

Period elapse callback

Definition at line 194 of file ald_timer.h.

◆ pwm_pulse_finish_cbk

void(* pwm_pulse_finish_cbk) (struct timer_handle_s *arg)

PWM_pulse_finish callback

Definition at line 197 of file ald_timer.h.

◆ state

timer_state_t state

TIMER operation state

Definition at line 187 of file ald_timer.h.

◆ trigger_cbk

void(* trigger_cbk) (struct timer_handle_s *arg)

Trigger callback

Definition at line 198 of file ald_timer.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_timer.h


ALD User Manual: timer_encoder_init_t Struct Reference

Data Fields
timer_encoder_init_t Struct Reference
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Types

TIMER encoder configuration structure definition. More...

#include <ald_timer.h>

Data Fields

timer_encoder_mode_t mode
timer_ic_polarity_t ic1_polarity
timer_ic_select_t ic1_sel
timer_ic_prescaler_t ic1_psc
uint32_t | ic1_filter
timer_ic_polarity_t ic2_polarity
timer_ic_select_t ic2_sel
timer_ic_prescaler_t ic2_psc
uint32_t | ic2_filter

Detailed Description

TIMER encoder configuration structure definition.

Definition at line 244 of file ald_timer.h.

Field Documentation

◆ ic1_filter

uint32_t ic1_filter

Specifies the input capture filter

Definition at line 249 of file ald_timer.h.

◆ ic1_polarity

timer_ic_polarity_t ic1_polarity

Specifies the active edge of the input signal

Definition at line 246 of file ald_timer.h.

◆ ic1_psc

timer_ic_prescaler_t ic1_psc

Specifies the Input Capture Prescaler

Definition at line 248 of file ald_timer.h.

◆ ic1_sel

timer_ic_select_t ic1_sel

Specifies the input

Definition at line 247 of file ald_timer.h.

◆ ic2_filter

uint32_t ic2_filter

Specifies the input capture filter

Definition at line 253 of file ald_timer.h.

◆ ic2_polarity

timer_ic_polarity_t ic2_polarity

Specifies the active edge of the input signal

Definition at line 250 of file ald_timer.h.

◆ ic2_psc

timer_ic_prescaler_t ic2_psc

Specifies the Input Capture Prescaler

Definition at line 252 of file ald_timer.h.

◆ ic2_sel

timer_ic_select_t ic2_sel

Specifies the input

Definition at line 251 of file ald_timer.h.

◆ mode

timer_encoder_mode_t mode

Specifies the encoder mode

Definition at line 245 of file ald_timer.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_timer.h


ALD User Manual: timer_ic_init_t Struct Reference

Data Fields
timer_ic_init_t Struct Reference
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Types

TIMER input capture configuration structure definition. More...

#include <ald_timer.h>

Data Fields

timer_ic_polarity_t polarity
timer_ic_select_t sel
timer_ic_prescaler_t psc
uint32_t filter

Detailed Description

TIMER input capture configuration structure definition.

Definition at line 259 of file ald_timer.h.

Field Documentation

◆ filter

uint32_t filter

Specifies the input capture filter

Definition at line 263 of file ald_timer.h.

◆ polarity

timer_ic_polarity_t polarity

Specifies the active edge of the input signal

Definition at line 260 of file ald_timer.h.

◆ psc

timer_ic_prescaler_t psc

Specifies the Input Capture Prescaler

Definition at line 262 of file ald_timer.h.

◆ sel

timer_ic_select_t sel

Specifies the input

Definition at line 261 of file ald_timer.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_timer.h


ALD User Manual: timer_one_pulse_init_t Struct Reference

Data Fields
timer_one_pulse_init_t Struct Reference
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Types

TIMER one pulse mode configuration structure definition. More...

#include <ald_timer.h>

Data Fields

timer_oc_mode_t mode
uint16_t | pulse
timer_oc_polarity_t oc_polarity
timer_ocn_polarity_t ocn_polarity
timer_oc_idle_t oc_idle
timer_ocn_idle_t ocn_idle
timer_ic_polarity_t polarity
timer_ic_select_t sel
uint32_t | filter

Detailed Description

TIMER one pulse mode configuration structure definition.

Definition at line 269 of file ald_timer.h.

Field Documentation

◆ filter

uint32_t filter

Specifies the input capture filter

Definition at line 278 of file ald_timer.h.

◆ mode

timer_oc_mode_t mode

Specifies the TIMER mode

Definition at line 270 of file ald_timer.h.

◆ oc_idle

timer_oc_idle_t oc_idle

Specifies the TIMER Output Compare pin state during Idle state

Definition at line 274 of file ald_timer.h.

◆ oc_polarity

timer_oc_polarity_t oc_polarity

Specifies the output polarity

Definition at line 272 of file ald_timer.h.

◆ ocn_idle

timer_ocn_idle_t ocn_idle

Specifies the TIMER Output Compare pin state during Idle state

Definition at line 275 of file ald_timer.h.

◆ ocn_polarity

timer_ocn_polarity_t ocn_polarity

Specifies the complementary output polarity

Definition at line 273 of file ald_timer.h.

◆ polarity

timer_ic_polarity_t polarity

Specifies the active edge of the input signal

Definition at line 276 of file ald_timer.h.

◆ pulse

uint16_t pulse

Specifies the pulse value

Definition at line 271 of file ald_timer.h.

◆ sel

timer_ic_select_t sel

Specifies the input

Definition at line 277 of file ald_timer.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_timer.h


ALD User Manual: timer_clear_input_config_t Struct Reference

Data Fields
timer_clear_input_config_t Struct Reference
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Types

TIMER clear input configuration handle structure definition. More...

#include <ald_timer.h>

Data Fields

type_func_t state
timer_clear_input_source_t source
timer_clear_input_polarity_t polarity
timer_etr_psc_t psc
timer_chnref_clr_sel_t clrsel
uint32_t filter

Detailed Description

TIMER clear input configuration handle structure definition.

Definition at line 312 of file ald_timer.h.

Field Documentation

◆ clrsel

timer_chnref_clr_sel_t clrsel

TIMER CHnREF_Clear

Definition at line 317 of file ald_timer.h.

◆ filter

uint32_t filter

TIMER Clear Input filter

Definition at line 318 of file ald_timer.h.

◆ polarity

timer_clear_input_polarity_t polarity

TIMER Clear Input polarity

Definition at line 315 of file ald_timer.h.

◆ psc

timer_etr_psc_t psc

TIMER Clear Input prescaler

Definition at line 316 of file ald_timer.h.

◆ source

timer_clear_input_source_t source

TIMER clear Input sources

Definition at line 314 of file ald_timer.h.

◆ state

type_func_t state

TIMER clear Input state

Definition at line 313 of file ald_timer.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_timer.h


ALD User Manual: timer_clock_config_t Struct Reference

Data Fields
timer_clock_config_t Struct Reference
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Types

TIMER clock config structure definition. More...

#include <ald_timer.h>

Data Fields

timer_clock_source_t source
timer_clock_polarity_t polarity
timer_etr_psc_t psc
uint32_t filter

Detailed Description

TIMER clock config structure definition.

Definition at line 349 of file ald_timer.h.

Field Documentation

◆ filter

uint32_t filter

TIMER clock filter

Definition at line 353 of file ald_timer.h.

◆ polarity

timer_clock_polarity_t polarity

TIMER clock polarity

Definition at line 351 of file ald_timer.h.

◆ psc

timer_etr_psc_t psc

TIMER clock prescaler

Definition at line 352 of file ald_timer.h.

◆ source

timer_clock_source_t source

TIMER clock sources

Definition at line 350 of file ald_timer.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_timer.h


ALD User Manual: timer_slave_config_t Struct Reference

Data Fields
timer_slave_config_t Struct Reference
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Types

TIMER slave configuration structure definition. More...

#include <ald_timer.h>

Data Fields

timer_slave_mode_t mode
timer_ts_t input
timer_clock_polarity_t polarity
timer_etr_psc_t psc
uint32_t filter

Detailed Description

TIMER slave configuration structure definition.

Definition at line 387 of file ald_timer.h.

Field Documentation

◆ filter

uint32_t filter

Input trigger filter

Definition at line 392 of file ald_timer.h.

◆ input

timer_ts_t input

Input Trigger source

Definition at line 389 of file ald_timer.h.

◆ mode

timer_slave_mode_t mode

Slave mode selection

Definition at line 388 of file ald_timer.h.

◆ polarity

timer_clock_polarity_t polarity

Input Trigger polarity

Definition at line 390 of file ald_timer.h.

◆ psc

timer_etr_psc_t psc

Input trigger prescaler

Definition at line 391 of file ald_timer.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_timer.h


ALD User Manual: timer_hall_sensor_init_t Struct Reference

Data Fields
timer_hall_sensor_init_t Struct Reference
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Types

TIMER hall sensor configuretion structure definition. More...

#include <ald_timer.h>

Data Fields

timer_ic_polarity_t polarity
timer_ic_prescaler_t psc
uint32_t | filter
uint32_t | delay

Detailed Description

TIMER hall sensor configuretion structure definition.

Definition at line 398 of file ald_timer.h.

Field Documentation

◆ delay

uint32_t delay

Specifies the pulse value to be loaded into the register [0x0, 0xFFFF]

Definition at line 402 of file ald_timer.h.

◆ filter

uint32_t filter

Specifies the input capture filter [0x0, 0xF]

Definition at line 401 of file ald_timer.h.

◆ polarity

timer_ic_polarity_t polarity

Specifies the active edge of the input signal

Definition at line 399 of file ald_timer.h.

◆ psc

timer_ic_prescaler_t psc

Specifies the Input Capture Prescaler

Definition at line 400 of file ald_timer.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_timer.h


ALD User Manual: timer_break_dead_time_t Struct Reference

Data Fields
timer_break_dead_time_t Struct Reference
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Types

TIMER break and dead time configuretion structure definition. More...

#include <ald_timer.h>

Data Fields

type_func_t off_run
type_func_t off_idle
timer_lock_level_t lock_level
uint32_t dead_time
type_func_t break_state
timer_break_polarity_t polarity
type_func_t auto_out

Detailed Description

TIMER break and dead time configuretion structure definition.

Definition at line 426 of file ald_timer.h.

Field Documentation

◆ auto_out

type_func_t auto_out

Enalbe/Disable automatic output

Definition at line 433 of file ald_timer.h.

◆ break_state

type_func_t break_state

Break state

Definition at line 431 of file ald_timer.h.

◆ dead_time

uint32_t dead_time

Dead time, [0x0, 0xFF]

Definition at line 430 of file ald_timer.h.

◆ lock_level

timer_lock_level_t lock_level

Lock level

Definition at line 429 of file ald_timer.h.

◆ off_idle

type_func_t off_idle

Enalbe/Disable off state in idle mode

Definition at line 428 of file ald_timer.h.

◆ off_run

type_func_t off_run

Enalbe/Disable off state in run mode

Definition at line 427 of file ald_timer.h.

◆ polarity

timer_break_polarity_t polarity

Break input polarity

Definition at line 432 of file ald_timer.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_timer.h


ALD User Manual: timer_channel_config_t Struct Reference

Data Fields
timer_channel_config_t Struct Reference
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Types

TIMER commutation event channel configuretion structure definition. More...

#include <ald_timer.h>

Data Fields

type_func_t en
type_func_t n_en
timer_oc_mode_t mode

Detailed Description

TIMER commutation event channel configuretion structure definition.

Definition at line 439 of file ald_timer.h.

Field Documentation

◆ en

type_func_t en

Enalbe/Disable the channel

Definition at line 440 of file ald_timer.h.

◆ mode

timer_oc_mode_t mode

Mode of the channel

Definition at line 442 of file ald_timer.h.

◆ n_en

type_func_t n_en

Enalbe/Disable the complementary channel

Definition at line 441 of file ald_timer.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_timer.h


ALD User Manual: timer_com_channel_config_t Struct Reference

Data Fields
timer_com_channel_config_t Struct Reference
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Types

TIMER commutation event configuretion structure definition. More...

#include <ald_timer.h>

Collaboration diagram for timer_com_channel_config_t:
[legend]

Data Fields

timer_channel_config_t ch [3]

Detailed Description

TIMER commutation event configuretion structure definition.

Definition at line 448 of file ald_timer.h.

Field Documentation

◆ ch

timer_channel_config_t ch[3]

Configure of channel

Definition at line 449 of file ald_timer.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_timer.h


ALD User Manual: timer_master_config_t Struct Reference

Data Fields
timer_master_config_t Struct Reference
EASTSOFT ES32F3xx ALD » TIMER » TIMER Public Types

TIMER master configuretion structure definition. More...

#include <ald_timer.h>

Data Fields

timer_master_mode_sel_t sel
type_func_t master_en

Detailed Description

TIMER master configuretion structure definition.

Definition at line 469 of file ald_timer.h.

Field Documentation

◆ master_en

type_func_t master_en

Master/Slave mode selection

Definition at line 471 of file ald_timer.h.

◆ sel

timer_master_mode_sel_t sel

Specifies the active edge of the input signal

Definition at line 470 of file ald_timer.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_timer.h


ALD User Manual: TIMER Public Macros

Macros
TIMER Public Macros
EASTSOFT ES32F3xx ALD » TIMER
Collaboration diagram for TIMER Public Macros:

Macros

#define | CCER_CCxE_MASK ((1U << 0) | (1U << 4) | (1U << 8) | (1U << 12))
#define | CCER_CCxNE_MASK ((1U << 2) | (1U << 6) | (1U << 10))
#define | TIMER_RESET_HANDLE_STATE(hperh) ((hperh)->state = TIMER_STATE_RESET)
Reset TIMER handle state. More...
#define | TIMER_ENABLE(hperh) (SET_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK))
Enable the TIMER peripheral. More...
#define | TIMER_MOE_ENABLE(hperh) (SET_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK))
Enable the TIMER main output. More...
#define | TIMER_DISABLE(hperh)
Disable the TIMER peripheral. More...
#define | TIMER_MOE_DISABLE(hperh)
Disable the TIMER main output. More...
#define | TIMER_SET_AUTORELOAD(handle, AUTORELOAD)
Sets the TIMER autoreload register value on runtime without calling another time any Init function. More...
#define | TIMER_GET_AUTORELOAD(handle) ((handle)->perh->AR)
Gets the TIMER autoreload register value on runtime. More...
#define | TIMER_GET_CNT(handle) ((handle)->perh->COUNT)
Gets the TIMER count register value on runtime. More...
#define | TIMER_GET_DIR(handle) (READ_BITS((handle)->perh->CON1, TIMER_CON1_DIRSEL_MSK, TIMER_CON1_DIRSEL_POS))
Gets the TIMER count direction value on runtime. More...
#define | TIMER_CCx_DMA_REQ_CCx(handle) (CLEAR_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK))
CCx DMA request sent when CCx event occurs. More...
#define | TIMER_CCx_DMA_REQ_UPDATE(handle) (SET_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK))
CCx DMA request sent when update event occurs. More...
#define | TIMER_CCx_ENABLE(handle, ch)
Enable channel. More...
#define | TIMER_CCx_DISABLE(handle, ch)
Disable channel. More...
#define | TIMER_CCxN_ENABLE(handle, ch) ((handle)->perh->CCEP |= (1 << (((ch) << 2) + 2)))
Enable complementary channel. More...
#define | TIMER_CCxN_DISABLE(handle, ch) ((handle)->perh->CCEP &= ~(1 << (((ch) << 2) + 2)))
Disable complementary channel. More...

Detailed Description

Macro Definition Documentation

◆ CCER_CCxE_MASK

#define CCER_CCxE_MASK ((1U << 0) | (1U << 4) | (1U << 8) | (1U << 12))

Definition at line 539 of file ald_timer.h.

◆ CCER_CCxNE_MASK

#define CCER_CCxNE_MASK ((1U << 2) | (1U << 6) | (1U << 10))

Definition at line 540 of file ald_timer.h.

◆ TIMER_CCx_DISABLE

#define TIMER_CCx_DISABLE | ( | handle,
 |  | ch
 | ) |
Value:
(((ch) == TIMER_CHANNEL_4) ? \
(CLEAR_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4EN_MSK)) : ((handle)->perh->CCEP &= ~(1 << ((ch) << 2))))
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
TIMER_CHANNEL_4
Definition: ald_timer.h:113

Disable channel.

Parameters
handle | TIMER handle
ch | Must be one of this: TIMER_CHANNEL_1 TIMER_CHANNEL_2 TIMER_CHANNEL_3 TIMER_CHANNEL_4

Definition at line 635 of file ald_timer.h.

◆ TIMER_CCx_DMA_REQ_CCx

#define TIMER_CCx_DMA_REQ_CCx ( handle ) (CLEAR_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK))

CCx DMA request sent when CCx event occurs.

Definition at line 607 of file ald_timer.h.

◆ TIMER_CCx_DMA_REQ_UPDATE

#define TIMER_CCx_DMA_REQ_UPDATE ( handle ) (SET_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK))

CCx DMA request sent when update event occurs.

Definition at line 612 of file ald_timer.h.

◆ TIMER_CCx_ENABLE

#define TIMER_CCx_ENABLE | ( | handle,
 |  | ch
 | ) |
Value:
(((ch) == TIMER_CHANNEL_4) ? \
(SET_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4POL_MSK)) : (WRITE_REG(((handle)->perh->CCEP), (((handle)->perh->CCEP) | (1 << ((ch) << 2))))))
TIMER_CHANNEL_4
Definition: ald_timer.h:113
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72

Enable channel.

Parameters
handle | TIMER handle
ch | Must be one of this: TIMER_CHANNEL_1 TIMER_CHANNEL_2 TIMER_CHANNEL_3 TIMER_CHANNEL_4

Definition at line 623 of file ald_timer.h.

◆ TIMER_CCxN_DISABLE

#define TIMER_CCxN_DISABLE | ( | handle,
 |  | ch
 | ) | ((handle)->perh->CCEP &= ~(1 << (((ch) << 2) + 2)))

Disable complementary channel.

Parameters
handle | TIMER handle
ch | Must be one of this: TIMER_CHANNEL_1 TIMER_CHANNEL_2 TIMER_CHANNEL_3

Definition at line 656 of file ald_timer.h.

◆ TIMER_CCxN_ENABLE

#define TIMER_CCxN_ENABLE | ( | handle,
 |  | ch
 | ) | ((handle)->perh->CCEP |= (1 << (((ch) << 2) + 2)))

Enable complementary channel.

Parameters
handle | TIMER handle
ch | Must be one of this: TIMER_CHANNEL_1 TIMER_CHANNEL_2 TIMER_CHANNEL_3

Definition at line 646 of file ald_timer.h.

◆ TIMER_DISABLE

#define TIMER_DISABLE ( hperh )
Value:
do { \
if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \
&& (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \
CLEAR_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK); \
} while (0)
CCER_CCxNE_MASK
#define CCER_CCxNE_MASK
Definition: ald_timer.h:540
CCER_CCxE_MASK
#define CCER_CCxE_MASK
Definition: ald_timer.h:539

Disable the TIMER peripheral.

Definition at line 560 of file ald_timer.h.

◆ TIMER_ENABLE

#define TIMER_ENABLE ( hperh ) (SET_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK))

Enable the TIMER peripheral.

Definition at line 550 of file ald_timer.h.

◆ TIMER_GET_AUTORELOAD

#define TIMER_GET_AUTORELOAD ( handle ) ((handle)->perh->AR)

Gets the TIMER autoreload register value on runtime.

Definition at line 592 of file ald_timer.h.

◆ TIMER_GET_CNT

#define TIMER_GET_CNT ( handle ) ((handle)->perh->COUNT)

Gets the TIMER count register value on runtime.

Definition at line 597 of file ald_timer.h.

◆ TIMER_GET_DIR

#define TIMER_GET_DIR ( handle ) (READ_BITS((handle)->perh->CON1, TIMER_CON1_DIRSEL_MSK, TIMER_CON1_DIRSEL_POS))

Gets the TIMER count direction value on runtime.

Definition at line 602 of file ald_timer.h.

◆ TIMER_MOE_DISABLE

#define TIMER_MOE_DISABLE ( hperh )
Value:
do { \
if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \
&& (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \
CLEAR_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK); \
} while (0)
CCER_CCxNE_MASK
#define CCER_CCxNE_MASK
Definition: ald_timer.h:540
CCER_CCxE_MASK
#define CCER_CCxE_MASK
Definition: ald_timer.h:539

Disable the TIMER main output.

Note
The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled

Definition at line 572 of file ald_timer.h.

◆ TIMER_MOE_ENABLE

#define TIMER_MOE_ENABLE ( hperh ) (SET_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK))

Enable the TIMER main output.

Definition at line 555 of file ald_timer.h.

◆ TIMER_RESET_HANDLE_STATE

#define TIMER_RESET_HANDLE_STATE ( hperh ) ((hperh)->state = TIMER_STATE_RESET)

Reset TIMER handle state.

Definition at line 545 of file ald_timer.h.

◆ TIMER_SET_AUTORELOAD

#define TIMER_SET_AUTORELOAD | ( | handle,
 |  | AUTORELOAD
 | ) |
Value:
do { \
(handle)->perh->AR = (AUTORELOAD); \
(handle)->init.period = (AUTORELOAD); \
} while (0)

Sets the TIMER autoreload register value on runtime without calling another time any Init function.

Definition at line 583 of file ald_timer.h.


ALD User Manual: TIMER Private Macros

Macros
TIMER Private Macros
EASTSOFT ES32F3xx ALD » TIMER
Collaboration diagram for TIMER Private Macros:

Macros

#define | IS_TIMER_COUNTER_MODE(x)
#define | IS_TIMER_CLOCK_DIVISION(x)
#define | IS_TIMER_PWM_MODE(x)
#define | IS_TIMER_OC_MODE(x)
#define | IS_TIMER_OC_POLARITY(x)
#define | IS_TIMER_OCN_POLARITY(x)
#define | IS_TIMER_OCIDLE_STATE(x)
#define | IS_TIMER_OCNIDLE_STATE(x)
#define | IS_TIMER_CHANNELS(x)
#define | IS_TIMER_OP_MODE(x)
#define | IS_TIMER_OP_OUTPUT_CH(x)
#define | IS_TIMER_ENCODER_MODE(x)
#define | IS_TIMER_IC_POLARITY(x)
#define | IS_TIMER_IC_SELECT(x)
#define | IS_TIMER_IC_PSC(x)
#define | IS_TIMER_IC_FILTER(x) ((x) <= 0xF)
#define | IS_TIMER_DEAD_TIMERE(x) ((x) <= 0xFF)
#define | IS_TIMER_CLEAR_INPUT_SOURCE(x)
#define | IS_TIMER_CLEAR_INPUT_POLARITY(x)
#define | IS_TIMER_ETR_PSC(x)
#define | IS_TIMER_CHNREF_CLEAR(X)
#define | IS_TIMER_CLOCK_SOURCE(x)
#define | IS_TIMER_CLOCK_POLARITY(x)
#define | IS_TIMER_SLAVE_MODE(x)
#define | IS_TIMER_EVENT_SOURCE(x)
#define | IS_TIMER_TS(x)
#define | IS_TIMER_CLOCK_LEVEL(x)
#define | IS_TIMER_BREAK_POLARITY(x)
#define | IS_TIMER_MASTER_MODE_SEL(x)
#define | IS_TIMER_IT(x)
#define | IS_TIMER_DMA_REQ(x)
#define | IS_TIMER_FLAG(x)

Detailed Description

Macro Definition Documentation

◆ IS_TIMER_BREAK_POLARITY

#define IS_TIMER_BREAK_POLARITY ( x )
Value:
(((x) == TIMER_BREAK_POLARITY_LOW) || \
((x) == TIMER_BREAK_POLARITY_HIGH))
TIMER_BREAK_POLARITY_LOW
Definition: ald_timer.h:419
TIMER_BREAK_POLARITY_HIGH
Definition: ald_timer.h:420

Definition at line 949 of file ald_timer.h.

◆ IS_TIMER_CHANNELS

#define IS_TIMER_CHANNELS ( x )
Value:
(((x) == TIMER_CHANNEL_1) || \
((x) == TIMER_CHANNEL_2) || \
((x) == TIMER_CHANNEL_3) || \
((x) == TIMER_CHANNEL_4) || \
((x) == TIMER_CHANNEL_ALL))
TIMER_CHANNEL_3
Definition: ald_timer.h:112
TIMER_CHANNEL_1
Definition: ald_timer.h:110
TIMER_CHANNEL_ALL
Definition: ald_timer.h:114
TIMER_CHANNEL_4
Definition: ald_timer.h:113
TIMER_CHANNEL_2
Definition: ald_timer.h:111

Definition at line 873 of file ald_timer.h.

◆ IS_TIMER_CHNREF_CLEAR

#define IS_TIMER_CHNREF_CLEAR ( X )
Value:
(((X) == TIMER_CHNREF_CLR_CMP_IN) || \
((X) == TIMER_CHNREF_CLR_ETF))
TIMER_CHNREF_CLR_ETF
Definition: ald_timer.h:308
TIMER_CHNREF_CLR_CMP_IN
Definition: ald_timer.h:307

Definition at line 904 of file ald_timer.h.

◆ IS_TIMER_CLEAR_INPUT_POLARITY

#define IS_TIMER_CLEAR_INPUT_POLARITY ( x )
Value:
(((x) == TIMER_POLARITY_NO_INV) || \
((x) == TIMER_POLARITY_INV))
TIMER_POLARITY_NO_INV
Definition: ald_timer.h:291
TIMER_POLARITY_INV
Definition: ald_timer.h:292

Definition at line 898 of file ald_timer.h.

◆ IS_TIMER_CLEAR_INPUT_SOURCE

#define IS_TIMER_CLEAR_INPUT_SOURCE ( x )
Value:
(((x) == TIMER_INPUT_NONE) || \
((x) == TIMER_INPUT_ETR))
TIMER_INPUT_NONE
Definition: ald_timer.h:284
TIMER_INPUT_ETR
Definition: ald_timer.h:285

Definition at line 896 of file ald_timer.h.

◆ IS_TIMER_CLOCK_DIVISION

#define IS_TIMER_CLOCK_DIVISION ( x )
Value:
(((x) == TIMER_CLOCK_DIV1) || \
((x) == TIMER_CLOCK_DIV2) || \
((x) == TIMER_CLOCK_DIV4))
TIMER_CLOCK_DIV2
Definition: ald_timer.h:56
TIMER_CLOCK_DIV4
Definition: ald_timer.h:57
TIMER_CLOCK_DIV1
Definition: ald_timer.h:55

Definition at line 852 of file ald_timer.h.

◆ IS_TIMER_CLOCK_LEVEL

#define IS_TIMER_CLOCK_LEVEL ( x )
Value:
(((x) == TIMER_LOCK_LEVEL_OFF) || \
((x) == TIMER_LOCK_LEVEL_1) || \
((x) == TIMER_LOCK_LEVEL_2) || \
((x) == TIMER_LOCK_LEVEL_3))
TIMER_LOCK_LEVEL_OFF
Definition: ald_timer.h:409
TIMER_LOCK_LEVEL_3
Definition: ald_timer.h:412
TIMER_LOCK_LEVEL_1
Definition: ald_timer.h:410
TIMER_LOCK_LEVEL_2
Definition: ald_timer.h:411

Definition at line 945 of file ald_timer.h.

◆ IS_TIMER_CLOCK_POLARITY

#define IS_TIMER_CLOCK_POLARITY ( x )
Value:
(((x) == TIMER_CLK_POLARITY_INV) || \
((x) == TIMER_CLK_POLARITY_NO_INV) || \
((x) == TIMER_CLK_POLARITY_RISE) || \
((x) == TIMER_CLK_POLARITY_FALL) || \
((x) == TIMER_CLK_POLARITY_BOTH))
TIMER_CLK_POLARITY_INV
Definition: ald_timer.h:339
TIMER_CLK_POLARITY_FALL
Definition: ald_timer.h:342
TIMER_CLK_POLARITY_RISE
Definition: ald_timer.h:341
TIMER_CLK_POLARITY_NO_INV
Definition: ald_timer.h:340
TIMER_CLK_POLARITY_BOTH
Definition: ald_timer.h:343

Definition at line 916 of file ald_timer.h.

◆ IS_TIMER_CLOCK_SOURCE

#define IS_TIMER_CLOCK_SOURCE ( x )
Value:
(((x) == TIMER_SRC_ETRMODE2) || \
((x) == TIMER_SRC_INTER) || \
((x) == TIMER_SRC_ITR0) || \
((x) == TIMER_SRC_ITR1) || \
((x) == TIMER_SRC_ITR2) || \
((x) == TIMER_SRC_ITR3) || \
((x) == TIMER_SRC_TI1ED) || \
((x) == TIMER_SRC_TI1) || \
((x) == TIMER_SRC_TI2) || \
((x) == TIMER_SRC_ETRMODE1))
TIMER_SRC_ITR1
Definition: ald_timer.h:327
TIMER_SRC_INTER
Definition: ald_timer.h:325
TIMER_SRC_ETRMODE1
Definition: ald_timer.h:333
TIMER_SRC_ITR3
Definition: ald_timer.h:329
TIMER_SRC_TI1
Definition: ald_timer.h:331
TIMER_SRC_ITR2
Definition: ald_timer.h:328
TIMER_SRC_TI2
Definition: ald_timer.h:332
TIMER_SRC_ETRMODE2
Definition: ald_timer.h:324
TIMER_SRC_ITR0
Definition: ald_timer.h:326
TIMER_SRC_TI1ED
Definition: ald_timer.h:330

Definition at line 906 of file ald_timer.h.

◆ IS_TIMER_COUNTER_MODE

#define IS_TIMER_COUNTER_MODE ( x )
Value:
(((x) == TIMER_CNT_MODE_UP) || \
((x) == TIMER_CNT_MODE_DOWN) || \
((x) == TIMER_CNT_MODE_CENTER1) || \
((x) == TIMER_CNT_MODE_CENTER2) || \
((x) == TIMER_CNT_MODE_CENTER3))
TIMER_CNT_MODE_CENTER2
Definition: ald_timer.h:47
TIMER_CNT_MODE_CENTER3
Definition: ald_timer.h:48
TIMER_CNT_MODE_CENTER1
Definition: ald_timer.h:46
TIMER_CNT_MODE_UP
Definition: ald_timer.h:44
TIMER_CNT_MODE_DOWN
Definition: ald_timer.h:45

Definition at line 847 of file ald_timer.h.

◆ IS_TIMER_DEAD_TIMERE

#define IS_TIMER_DEAD_TIMERE ( x ) ((x) <= 0xFF)

Definition at line 895 of file ald_timer.h.

◆ IS_TIMER_DMA_REQ

#define IS_TIMER_DMA_REQ ( x )
Value:
(((x) == TIMER_DMA_UPDATE) || \
((x) == TIMER_DMA_CC1) || \
((x) == TIMER_DMA_CC2) || \
((x) == TIMER_DMA_CC3) || \
((x) == TIMER_DMA_CC4) || \
((x) == TIMER_DMA_COM) || \
((x) == TIMER_DMA_TRIGGER))
TIMER_DMA_TRIGGER
Definition: ald_timer.h:512
TIMER_DMA_CC2
Definition: ald_timer.h:508
TIMER_DMA_UPDATE
Definition: ald_timer.h:506
TIMER_DMA_CC3
Definition: ald_timer.h:509
TIMER_DMA_COM
Definition: ald_timer.h:511
TIMER_DMA_CC1
Definition: ald_timer.h:507
TIMER_DMA_CC4
Definition: ald_timer.h:510

Definition at line 967 of file ald_timer.h.

◆ IS_TIMER_ENCODER_MODE

#define IS_TIMER_ENCODER_MODE ( x )
Value:
(((x) == TIMER_ENC_MODE_TI1) || \
((x) == TIMER_ENC_MODE_TI2) || \
((x) == TIMER_ENC_MODE_TI12))
TIMER_ENC_MODE_TI1
Definition: ald_timer.h:209
TIMER_ENC_MODE_TI2
Definition: ald_timer.h:210
TIMER_ENC_MODE_TI12
Definition: ald_timer.h:211

Definition at line 882 of file ald_timer.h.

◆ IS_TIMER_ETR_PSC

#define IS_TIMER_ETR_PSC ( x )
Value:
(((x) == TIMER_ETR_PSC_DIV1) || \
((x) == TIMER_ETR_PSC_DIV2) || \
((x) == TIMER_ETR_PSC_DIV4) || \
((x) == TIMER_ETR_PSC_DIV8))
TIMER_ETR_PSC_DIV1
Definition: ald_timer.h:298
TIMER_ETR_PSC_DIV2
Definition: ald_timer.h:299
TIMER_ETR_PSC_DIV4
Definition: ald_timer.h:300
TIMER_ETR_PSC_DIV8
Definition: ald_timer.h:301

Definition at line 900 of file ald_timer.h.

◆ IS_TIMER_EVENT_SOURCE

#define IS_TIMER_EVENT_SOURCE ( x )
Value:
(((x) == TIMER_SRC_UPDATE) || \
((x) == TIMER_SRC_CC1) || \
((x) == TIMER_SRC_CC2) || \
((x) == TIMER_SRC_CC3) || \
((x) == TIMER_SRC_CC4) || \
((x) == TIMER_SRC_COM) || \
((x) == TIMER_SRC_TRIG) || \
((x) == TIMER_SRC_BREAK))
TIMER_SRC_UPDATE
Definition: ald_timer.h:478
TIMER_SRC_CC4
Definition: ald_timer.h:482
TIMER_SRC_CC2
Definition: ald_timer.h:480
TIMER_SRC_CC3
Definition: ald_timer.h:481
TIMER_SRC_CC1
Definition: ald_timer.h:479
TIMER_SRC_TRIG
Definition: ald_timer.h:484
TIMER_SRC_BREAK
Definition: ald_timer.h:485
TIMER_SRC_COM
Definition: ald_timer.h:483

Definition at line 929 of file ald_timer.h.

◆ IS_TIMER_FLAG

#define IS_TIMER_FLAG ( x )
Value:
(((x) == TIMER_FLAG_UPDATE) || \
((x) == TIMER_FLAG_CC1) || \
((x) == TIMER_FLAG_CC2) || \
((x) == TIMER_FLAG_CC3) || \
((x) == TIMER_FLAG_CC4) || \
((x) == TIMER_FLAG_COM) || \
((x) == TIMER_FLAG_TRIGGER) || \
((x) == TIMER_FLAG_BREAK) || \
((x) == TIMER_FLAG_CC1OF) || \
((x) == TIMER_FLAG_CC2OF) || \
((x) == TIMER_FLAG_CC3OF) || \
((x) == TIMER_FLAG_CC4OF))
TIMER_FLAG_CC1OF
Definition: ald_timer.h:527
TIMER_FLAG_CC1
Definition: ald_timer.h:520
TIMER_FLAG_CC3
Definition: ald_timer.h:522
TIMER_FLAG_CC4
Definition: ald_timer.h:523
TIMER_FLAG_TRIGGER
Definition: ald_timer.h:525
TIMER_FLAG_CC3OF
Definition: ald_timer.h:529
TIMER_FLAG_CC2
Definition: ald_timer.h:521
TIMER_FLAG_BREAK
Definition: ald_timer.h:526
TIMER_FLAG_COM
Definition: ald_timer.h:524
TIMER_FLAG_UPDATE
Definition: ald_timer.h:519
TIMER_FLAG_CC2OF
Definition: ald_timer.h:528
TIMER_FLAG_CC4OF
Definition: ald_timer.h:530

Definition at line 974 of file ald_timer.h.

◆ IS_TIMER_IC_FILTER

#define IS_TIMER_IC_FILTER ( x ) ((x) <= 0xF)

Definition at line 894 of file ald_timer.h.

◆ IS_TIMER_IC_POLARITY

#define IS_TIMER_IC_POLARITY ( x )
Value:
(((x) == TIMER_IC_POLARITY_RISE) || \
((x) == TIMER_IC_POLARITY_FALL))
TIMER_IC_POLARITY_RISE
Definition: ald_timer.h:218
TIMER_IC_POLARITY_FALL
Definition: ald_timer.h:219

Definition at line 885 of file ald_timer.h.

◆ IS_TIMER_IC_PSC

#define IS_TIMER_IC_PSC ( x )
Value:
(((x) == TIMER_IC_PSC_DIV1) || \
((x) == TIMER_IC_PSC_DIV2) || \
((x) == TIMER_IC_PSC_DIV4) || \
((x) == TIMER_IC_PSC_DIV8))
TIMER_IC_PSC_DIV4
Definition: ald_timer.h:237
TIMER_IC_PSC_DIV2
Definition: ald_timer.h:236
TIMER_IC_PSC_DIV8
Definition: ald_timer.h:238
TIMER_IC_PSC_DIV1
Definition: ald_timer.h:235

Definition at line 890 of file ald_timer.h.

◆ IS_TIMER_IC_SELECT

#define IS_TIMER_IC_SELECT ( x )
Value:
(((x) == TIMER_IC_SEL_DIRECT) || \
((x) == TIMER_IC_SEL_INDIRECT) || \
((x) == TIMER_IC_SEL_TRC))
TIMER_IC_SEL_DIRECT
Definition: ald_timer.h:226
TIMER_IC_SEL_TRC
Definition: ald_timer.h:228
TIMER_IC_SEL_INDIRECT
Definition: ald_timer.h:227

Definition at line 887 of file ald_timer.h.

◆ IS_TIMER_IT

#define IS_TIMER_IT ( x )
Value:
(((x) == TIMER_IT_UPDATE) || \
((x) == TIMER_IT_CC1) || \
((x) == TIMER_IT_CC2) || \
((x) == TIMER_IT_CC3) || \
((x) == TIMER_IT_CC4) || \
((x) == TIMER_IT_COM) || \
((x) == TIMER_IT_TRIGGER) || \
((x) == TIMER_IT_BREAK))
TIMER_IT_CC1
Definition: ald_timer.h:493
TIMER_IT_CC4
Definition: ald_timer.h:496
TIMER_IT_CC2
Definition: ald_timer.h:494
TIMER_IT_BREAK
Definition: ald_timer.h:499
TIMER_IT_CC3
Definition: ald_timer.h:495
TIMER_IT_TRIGGER
Definition: ald_timer.h:498
TIMER_IT_UPDATE
Definition: ald_timer.h:492
TIMER_IT_COM
Definition: ald_timer.h:497

Definition at line 959 of file ald_timer.h.

◆ IS_TIMER_MASTER_MODE_SEL

#define IS_TIMER_MASTER_MODE_SEL ( x )
Value:
(((x) == TIMER_TRGO_RESET) || \
((x) == TIMER_TRGO_ENABLE) || \
((x) == TIMER_TRGO_UPDATE) || \
((x) == TIMER_TRGO_OC1) || \
((x) == TIMER_TRGO_OC1REF) || \
((x) == TIMER_TRGO_OC2REF) || \
((x) == TIMER_TRGO_OC3REF) || \
((x) == TIMER_TRGO_OC4REF))
TIMER_TRGO_OC4REF
Definition: ald_timer.h:463
TIMER_TRGO_OC2REF
Definition: ald_timer.h:461
TIMER_TRGO_UPDATE
Definition: ald_timer.h:458
TIMER_TRGO_RESET
Definition: ald_timer.h:456
TIMER_TRGO_ENABLE
Definition: ald_timer.h:457
TIMER_TRGO_OC1
Definition: ald_timer.h:459
TIMER_TRGO_OC3REF
Definition: ald_timer.h:462
TIMER_TRGO_OC1REF
Definition: ald_timer.h:460

Definition at line 951 of file ald_timer.h.

◆ IS_TIMER_OC_MODE

#define IS_TIMER_OC_MODE ( x )
Value:
(((x) == TIMER_OC_MODE_TIMERING) || \
((x) == TIMER_OC_MODE_ACTIVE) || \
((x) == TIMER_OC_MODE_INACTIVE) || \
((x) == TIMER_OC_MODE_TOGGLE) || \
((x) == TIMER_OC_MODE_FORCE_ACTIVE) || \
((x) == TIMER_OC_MODE_FORCE_INACTIVE) || \
((x) == TIMER_OC_MODE_PWM1) || \
((x) == TIMER_OC_MODE_PWM2))
TIMER_OC_MODE_PWM2
Definition: ald_timer.h:71
TIMER_OC_MODE_ACTIVE
Definition: ald_timer.h:65
TIMER_OC_MODE_PWM1
Definition: ald_timer.h:70
TIMER_OC_MODE_INACTIVE
Definition: ald_timer.h:66
TIMER_OC_MODE_FORCE_INACTIVE
Definition: ald_timer.h:68
TIMER_OC_MODE_TOGGLE
Definition: ald_timer.h:67
TIMER_OC_MODE_FORCE_ACTIVE
Definition: ald_timer.h:69
TIMER_OC_MODE_TIMERING
Definition: ald_timer.h:64

Definition at line 857 of file ald_timer.h.

◆ IS_TIMER_OC_POLARITY

#define IS_TIMER_OC_POLARITY ( x )
Value:
(((x) == TIMER_OC_POLARITY_HIGH) || \
((x) == TIMER_OC_POLARITY_LOW))
TIMER_OC_POLARITY_HIGH
Definition: ald_timer.h:78
TIMER_OC_POLARITY_LOW
Definition: ald_timer.h:79

Definition at line 865 of file ald_timer.h.

◆ IS_TIMER_OCIDLE_STATE

#define IS_TIMER_OCIDLE_STATE ( x )
Value:
(((x) == TIMER_OC_IDLE_RESET) || \
((x) == TIMER_OC_IDLE_SET))
TIMER_OC_IDLE_RESET
Definition: ald_timer.h:94
TIMER_OC_IDLE_SET
Definition: ald_timer.h:95

Definition at line 869 of file ald_timer.h.

◆ IS_TIMER_OCN_POLARITY

#define IS_TIMER_OCN_POLARITY ( x )
Value:
(((x) == TIMER_OCN_POLARITY_HIGH) || \
((x) == TIMER_OCN_POLARITY_LOW))
TIMER_OCN_POLARITY_HIGH
Definition: ald_timer.h:86
TIMER_OCN_POLARITY_LOW
Definition: ald_timer.h:87

Definition at line 867 of file ald_timer.h.

◆ IS_TIMER_OCNIDLE_STATE

#define IS_TIMER_OCNIDLE_STATE ( x )
Value:
(((x) == TIMER_OCN_IDLE_RESET) || \
((x) == TIMER_OCN_IDLE_SET))
TIMER_OCN_IDLE_SET
Definition: ald_timer.h:103
TIMER_OCN_IDLE_RESET
Definition: ald_timer.h:102

Definition at line 871 of file ald_timer.h.

◆ IS_TIMER_OP_MODE

#define IS_TIMER_OP_MODE ( x )
Value:
(((x) == TIMER_OP_MODE_REPEAT) || \
((x) == TIMER_OP_MODE_SINGLE))
TIMER_OP_MODE_REPEAT
Definition: ald_timer.h:121
TIMER_OP_MODE_SINGLE
Definition: ald_timer.h:122

Definition at line 878 of file ald_timer.h.

◆ IS_TIMER_OP_OUTPUT_CH

#define IS_TIMER_OP_OUTPUT_CH ( x )
Value:
(((x) == TIMER_OP_OUTPUT_CHANNEL_1) || \
((x) == TIMER_OP_OUTPUT_CHANNEL_2))
TIMER_OP_OUTPUT_CHANNEL_1
Definition: ald_timer.h:129
TIMER_OP_OUTPUT_CHANNEL_2
Definition: ald_timer.h:130

Definition at line 880 of file ald_timer.h.

◆ IS_TIMER_PWM_MODE

#define IS_TIMER_PWM_MODE ( x )
Value:
(((x) == TIMER_OC_MODE_PWM1) || \
((x) == TIMER_OC_MODE_PWM2))
TIMER_OC_MODE_PWM2
Definition: ald_timer.h:71
TIMER_OC_MODE_PWM1
Definition: ald_timer.h:70

Definition at line 855 of file ald_timer.h.

◆ IS_TIMER_SLAVE_MODE

#define IS_TIMER_SLAVE_MODE ( x )
Value:
(((x) == TIMER_MODE_DISABLE) || \
((x) == TIMER_MODE_ENC1) || \
((x) == TIMER_MODE_ENC2) || \
((x) == TIMER_MODE_ENC3) || \
((x) == TIMER_MODE_RESET) || \
((x) == TIMER_MODE_GATED) || \
((x) == TIMER_MODE_TRIG) || \
((x) == TIMER_MODE_EXTERNAL1))
TIMER_MODE_GATED
Definition: ald_timer.h:365
TIMER_MODE_DISABLE
Definition: ald_timer.h:360
TIMER_MODE_RESET
Definition: ald_timer.h:364
TIMER_MODE_TRIG
Definition: ald_timer.h:366
TIMER_MODE_EXTERNAL1
Definition: ald_timer.h:367
TIMER_MODE_ENC3
Definition: ald_timer.h:363
TIMER_MODE_ENC1
Definition: ald_timer.h:361
TIMER_MODE_ENC2
Definition: ald_timer.h:362

Definition at line 921 of file ald_timer.h.

◆ IS_TIMER_TS

#define IS_TIMER_TS ( x )
Value:
(((x) == TIMER_TS_ITR0) || \
((x) == TIMER_TS_ITR1) || \
((x) == TIMER_TS_ITR2) || \
((x) == TIMER_TS_ITR3) || \
((x) == TIMER_TS_TI1F_ED) || \
((x) == TIMER_TS_TI1FP1) || \
((x) == TIMER_TS_TI2FP2) || \
((x) == TIMER_TS_ETRF))
TIMER_TS_TI1FP1
Definition: ald_timer.h:379
TIMER_TS_TI1F_ED
Definition: ald_timer.h:378
TIMER_TS_ETRF
Definition: ald_timer.h:381
TIMER_TS_TI2FP2
Definition: ald_timer.h:380
TIMER_TS_ITR2
Definition: ald_timer.h:376
TIMER_TS_ITR1
Definition: ald_timer.h:375
TIMER_TS_ITR0
Definition: ald_timer.h:374
TIMER_TS_ITR3
Definition: ald_timer.h:377

Definition at line 937 of file ald_timer.h.


ALD User Manual: TRNG

Modules
TRNG
EASTSOFT ES32F3xx ALD

TRNG module driver. More...

Collaboration diagram for TRNG:

Modules

TRNG Public Functions
TRNG Public Types
TRNG Public Macros
TRNG Private Macros
CRYPT Private Functions
CRYPT Private functions.

Detailed Description

TRNG module driver.


ALD User Manual: TRNG Public Functions

Modules
TRNG Public Functions
EASTSOFT ES32F3xx ALD » TRNG
Collaboration diagram for TRNG Public Functions:

Modules

Initialization functions
Initialization functions.
Peripheral Control functions
Peripheral Control functions.

Detailed Description


ALD User Manual: Initialization functions

Functions
Initialization functions
EASTSOFT ES32F3xx ALD » TRNG » TRNG Public Functions

Initialization functions. More...

Collaboration diagram for Initialization functions:

Functions

ald_status_t ald_trng_init (trng_handle_t *hperh)
Initializes the TRNG according to the specified parameters in the trng_init_t. More...

Detailed Description

Initialization functions.

==============================================================================
            ##### Initialization functions #####
==============================================================================
  [..]  This section provides functions allowing to initialize the TRNG:
    (+) This parameters can be configured:
      (++) Word Width
      (++) Seed Type
      (++) Seed
      (++) Start Time
      (++) Adjust parameter

Function Documentation

◆ ald_trng_init()

ald_status_t ald_trng_init ( trng_handle_t * hperh )

Initializes the TRNG according to the specified parameters in the trng_init_t.

Parameters
hperh Pointer to a trng_handle_t structure that contains the configuration information for the specified TRNG module.
Return values
Status,see ald_status_t.

Definition at line 69 of file ald_trng.c.

70 {
71 uint32_t tmp = 0;
72
73 if (hperh == NULL)
74 return ERROR;
75
76 assert_param(IS_TRNG_DATA_WIDTH(hperh->init.data_width));
77 assert_param(IS_TRNG_SEED_TYPE(hperh->init.seed_type));
78 assert_param(IS_TRNG_ADJC(hperh->init.adjc));
79 assert_param(IS_FUNC_STATE(hperh->init.posten));
80 assert_param(IS_TRNG_T_START(hperh->init.t_start));
81
82 __LOCK(hperh);
83 trng_reset(hperh);
84
85 if (hperh->state == TRNG_STATE_RESET)
86 __UNLOCK(hperh);
87
88 tmp = TRNG->CR;
89
90 if (hperh->init.adjc == 0)
91 tmp = (0 << TRNG_CR_ADJM_POS);
92 else
93 tmp = (1 << TRNG_CR_ADJM_POS);
94
95 tmp |= ((1 << TRNG_CR_TRNGSEL_POS) | (hperh->init.data_width << TRNG_CR_DSEL_POSS) |
96 (hperh->init.seed_type << TRNG_CR_SDSEL_POSS) | (hperh->init.adjc << TRNG_CR_ADJC_POSS) |
97 (hperh->init.posten << TRNG_CR_POSTEN_MSK));
98
99 TRNG->CR = tmp;
100
101 WRITE_REG(TRNG->SEED, hperh->init.seed);
102 MODIFY_REG(TRNG->CFGR, TRNG_CFGR_TSTART_MSK, (hperh->init.t_start) << TRNG_CFGR_TSTART_POSS);
103
104 hperh->state = TRNG_STATE_READY;
105 __UNLOCK(hperh);
106 return OK;
107 }
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
trng_init_t::adjc
uint8_t adjc
Definition: ald_trng.h:66
assert_param
#define assert_param(x)
Definition: type.h:88
IS_TRNG_SEED_TYPE
#define IS_TRNG_SEED_TYPE(x)
Definition: ald_trng.h:144
IS_TRNG_DATA_WIDTH
#define IS_TRNG_DATA_WIDTH(x)
Definition: ald_trng.h:140
IS_TRNG_ADJC
#define IS_TRNG_ADJC(x)
Definition: ald_trng.h:157
TRNG_STATE_READY
Definition: ald_trng.h:75
TRNG_STATE_RESET
Definition: ald_trng.h:74
trng_init_t::posten
type_func_t posten
Definition: ald_trng.h:67
IS_TRNG_T_START
#define IS_TRNG_T_START(x)
Definition: ald_trng.h:158
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
trng_reset
void trng_reset(trng_handle_t *hperh)
Reset the TRNG peripheral.
Definition: ald_trng.c:251
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
trng_init_t::data_width
trng_data_width_t data_width
Definition: ald_trng.h:62
trng_handle_s::init
trng_init_t init
Definition: ald_trng.h:112
trng_handle_s::state
trng_state_t state
Definition: ald_trng.h:115
trng_init_t::seed
uint32_t seed
Definition: ald_trng.h:64
__LOCK
#define __LOCK(x)
Definition: utils.h:92
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
ERROR
Definition: utils.h:56
trng_init_t::seed_type
trng_seed_type_t seed_type
Definition: ald_trng.h:63
trng_init_t::t_start
uint16_t t_start
Definition: ald_trng.h:65


ALD User Manual: Peripheral Control functions

Functions
Peripheral Control functions
EASTSOFT ES32F3xx ALD » TRNG » TRNG Public Functions

Peripheral Control functions. More...

Collaboration diagram for Peripheral Control functions:

Functions

uint32_t | ald_trng_get_result (trng_handle_t *hperh)
Get the result. More...
void | ald_trng_interrupt_config (trng_handle_t *hperh, trng_it_t it, type_func_t state)
Enable/disable the specified interrupts. More...
flag_status_t | ald_trng_get_status (trng_handle_t *hperh, trng_status_t status)
Get the status of SR register. More...
it_status_t | ald_trng_get_it_status (trng_handle_t *hperh, trng_it_t it)
Get the status of interrupt source. More...
flag_status_t | ald_trng_get_flag_status (trng_handle_t *hperh, trng_flag_t flag)
Get the status of interrupt flag. More...
void | ald_trng_clear_flag_status (trng_handle_t *hperh, trng_flag_t flag)
Clear the interrupt flag. More...
void | ald_trng_irq_handler (trng_handle_t *hperh)
This function handles TRNG interrupt request. More...
void | trng_reset (trng_handle_t *hperh)
Reset the TRNG peripheral. More...

Detailed Description

Peripheral Control functions.

==============================================================================
            ##### Peripheral Control functions #####
==============================================================================
[..]  This section provides functions allowing to:
  (+) ald_trng_get_result() API can Get the result.
  (+) ald_trng_interrupt_config() API can be helpful to configure TRNG interrupt source.
  (+) ald_trng_get_it_status() API can get the status of interrupt source.
  (+) ald_trng_get_status() API can get the status of SR register.
  (+) ald_trng_get_flag_status() API can get the status of interrupt flag.
  (+) ald_trng_clear_flag_status() API can clear interrupt flag.

Function Documentation

◆ ald_trng_clear_flag_status()

void ald_trng_clear_flag_status | ( | trng_handle_t * | hperh,
 |  | trng_flag_t | flag
 | ) |  |

Clear the interrupt flag.

Parameters
hperh | Pointer to a trng_handle_t structure that contains the configuration information for the specified TRNG module.
flag | Specifies the interrupt flag. This parameter can be one of the trng_flag_t.
Return values
None

Definition at line 237 of file ald_trng.c.

238 {
239 assert_param(IS_TRNG_FLAG(flag));
240 WRITE_REG(hperh->perh->IFCR, flag);
241
242 return;
243 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_TRNG_FLAG
#define IS_TRNG_FLAG(x)
Definition: ald_trng.h:154
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
trng_handle_s::perh
TRNG_TypeDef * perh
Definition: ald_trng.h:111

◆ ald_trng_get_flag_status()

flag_status_t ald_trng_get_flag_status | ( | trng_handle_t * | hperh,
 |  | trng_flag_t | flag
 | ) |  |

Get the status of interrupt flag.

Parameters
hperh | Pointer to a trng_handle_t structure that contains the configuration information for the specified TRNG module.
flag | Specifies the interrupt flag. This parameter can be one of the trng_flag_t.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 219 of file ald_trng.c.

220 {
221 assert_param(IS_TRNG_FLAG(flag));
222
223 if (READ_BIT(hperh->perh->IFR, flag))
224 return SET;
225
226 return RESET;
227 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
RESET
Definition: type.h:38
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
IS_TRNG_FLAG
#define IS_TRNG_FLAG(x)
Definition: ald_trng.h:154
trng_handle_s::perh
TRNG_TypeDef * perh
Definition: ald_trng.h:111

◆ ald_trng_get_it_status()

it_status_t ald_trng_get_it_status | ( | trng_handle_t * | hperh,
 |  | trng_it_t | it
 | ) |  |

Get the status of interrupt source.

Parameters
hperh | Pointer to a trng_handle_t structure that contains the configuration information for the specified TRNG module.
it | Specifies the interrupt source. This parameter can be one of the trng_it_t.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 199 of file ald_trng.c.

200 {
201 assert_param(IS_TRNG_IT(it));
202
203 if (READ_BIT(hperh->perh->IER, it))
204 return SET;
205
206 return RESET;
207 }
IS_TRNG_IT
#define IS_TRNG_IT(x)
Definition: ald_trng.h:151
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
RESET
Definition: type.h:38
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
trng_handle_s::perh
TRNG_TypeDef * perh
Definition: ald_trng.h:111

◆ ald_trng_get_result()

uint32_t ald_trng_get_result ( trng_handle_t * hperh )

Get the result.

Parameters
hperh Pointer to a trng_handle_t structure that contains the configuration information for the specified TRNG module.
Return values
The resultl

Definition at line 137 of file ald_trng.c.

138 {
139 hperh->state = TRNG_STATE_READY;
140 hperh->data = hperh->perh->DR;
141 return (uint32_t)hperh->perh->DR;
142 }
TRNG_STATE_READY
Definition: ald_trng.h:75
trng_handle_s::data
uint32_t data
Definition: ald_trng.h:113
trng_handle_s::perh
TRNG_TypeDef * perh
Definition: ald_trng.h:111
trng_handle_s::state
trng_state_t state
Definition: ald_trng.h:115

◆ ald_trng_get_status()

flag_status_t ald_trng_get_status | ( | trng_handle_t * | hperh,
 |  | trng_status_t | status
 | ) |  |

Get the status of SR register.

Parameters
hperh | Pointer to a trng_handle_t structure that contains the configuration information for the specified TRNG module.
status | Specifies the TRNG status type. This parameter can be one of the trng_status_t.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 179 of file ald_trng.c.

180 {
181 assert_param(IS_TRNG_STATUS(status));
182
183 if (READ_BIT(hperh->perh->SR, status))
184 return SET;
185
186 return RESET;
187 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
IS_TRNG_STATUS
#define IS_TRNG_STATUS(x)
Definition: ald_trng.h:148
RESET
Definition: type.h:38
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
trng_handle_s::perh
TRNG_TypeDef * perh
Definition: ald_trng.h:111

◆ ald_trng_interrupt_config()

void ald_trng_interrupt_config | ( | trng_handle_t * | hperh,
 |  | trng_it_t | it,
 |  | type_func_t | state
 | ) |  |

Enable/disable the specified interrupts.

Parameters
hperh | Pointer to a trng_handle_t structure that contains the configuration information for the specified TRNG module.
it | Specifies the interrupt sources to be enabled or disabled. This parameter can be one of the trng_it_t.
state New state of the specified interrupts. This parameter can be:
  • ENABLE
  • DISABLE
Return values
None

Definition at line 156 of file ald_trng.c.

157 {
158 assert_param(IS_TRNG_IT(it));
159 assert_param(IS_FUNC_STATE(state));
160
161 if (state)
162 SET_BIT(hperh->perh->IER, it);
163 else
164 CLEAR_BIT(hperh->perh->IER, it);
165
166 return;
167 }
IS_TRNG_IT
#define IS_TRNG_IT(x)
Definition: ald_trng.h:151
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
trng_handle_s::perh
TRNG_TypeDef * perh
Definition: ald_trng.h:111
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_trng_irq_handler()

void ald_trng_irq_handler ( trng_handle_t * hperh )

This function handles TRNG interrupt request.

Parameters
hperh Pointer to a trng_handle_t structure that contains the configuration information for the specified TRNG module.
Return values
None

Definition at line 270 of file ald_trng.c.

271 {
272 if (ald_trng_get_flag_status(hperh, TRNG_IF_SERR) == SET) {
273 hperh->state = TRNG_STATE_ERROR;
274 ald_trng_clear_flag_status(hperh, TRNG_IF_SERR);
275 if (hperh->err_cplt_cbk)
276 hperh->err_cplt_cbk(hperh);
277 return;
278 }
279
280 if (ald_trng_get_flag_status(hperh, TRNG_IF_DAVLD) == SET) {
281 hperh->data = hperh->perh->DR;
282 hperh->state = TRNG_STATE_READY;
283 ald_trng_clear_flag_status(hperh, TRNG_IF_DAVLD);
284 if (hperh->trng_cplt_cbk)
285 hperh->trng_cplt_cbk(hperh);
286 }
287
288 if (ald_trng_get_flag_status(hperh, TRNG_IF_START) == SET) {
289 hperh->state = TRNG_STATE_BUSY;
290 ald_trng_clear_flag_status(hperh, TRNG_IF_START);
291 if (hperh->init_cplt_cbk)
292 hperh->init_cplt_cbk(hperh);
293 }
294 }
SET
Definition: type.h:39
TRNG_STATE_ERROR
Definition: ald_trng.h:77
TRNG_STATE_READY
Definition: ald_trng.h:75
ald_trng_get_flag_status
flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag)
Get the status of interrupt flag.
Definition: ald_trng.c:219
TRNG_IF_START
Definition: ald_trng.h:102
TRNG_IF_DAVLD
Definition: ald_trng.h:103
TRNG_STATE_BUSY
Definition: ald_trng.h:76
trng_handle_s::err_cplt_cbk
void(* err_cplt_cbk)(struct trng_handle_s *arg)
Definition: ald_trng.h:118
trng_handle_s::trng_cplt_cbk
void(* trng_cplt_cbk)(struct trng_handle_s *arg)
Definition: ald_trng.h:117
trng_handle_s::data
uint32_t data
Definition: ald_trng.h:113
ald_trng_clear_flag_status
void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag)
Clear the interrupt flag.
Definition: ald_trng.c:237
trng_handle_s::perh
TRNG_TypeDef * perh
Definition: ald_trng.h:111
trng_handle_s::init_cplt_cbk
void(* init_cplt_cbk)(struct trng_handle_s *arg)
Definition: ald_trng.h:119
trng_handle_s::state
trng_state_t state
Definition: ald_trng.h:115
TRNG_IF_SERR
Definition: ald_trng.h:104

◆ trng_reset()

void trng_reset ( trng_handle_t * hperh )

Reset the TRNG peripheral.

Parameters
hperh Pointer to a trng_handle_t structure that contains the configuration information for the specified TRNG module.
Return values
None

Definition at line 251 of file ald_trng.c.

252 {
253 TRNG->CR = 0;
254 TRNG->SEED = 0;
255 TRNG->CFGR = 0x1FF0707;
256 TRNG->IER = 0;
257 TRNG->IFCR = 0xFFFFFFFF;
258
259 hperh->state = TRNG_STATE_READY;
260 __UNLOCK(hperh);
261 return;
262 }
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
TRNG_STATE_READY
Definition: ald_trng.h:75
trng_handle_s::state
trng_state_t state
Definition: ald_trng.h:115


ALD User Manual: TRNG Public Types

Data Structures | Typedefs | Enumerations
TRNG Public Types
EASTSOFT ES32F3xx ALD » TRNG
Collaboration diagram for TRNG Public Types:

Data Structures

struct | trng_init_t
TRNG init structure definition. More...
struct | trng_handle_s
TRNG Handle Structure definition. More...

Typedefs

typedef struct trng_handle_s trng_handle_t
TRNG Handle Structure definition. More...

Enumerations

enum | trng_data_width_t { TRNG_DSEL_1B = 0x0U, TRNG_DSEL_8B = 0x1U, TRNG_DSEL_16B = 0x2U, TRNG_DSEL_32B = 0x3U }
Data width. More...
enum | trng_seed_type_t { TRNG_SEED_TYPE_0 = 0x0U, TRNG_SEED_TYPE_1 = 0x1U, TRNG_SEED_TYPE_LAST = 0x2U, TRNG_SEED_TYPE_SEED = 0x3U }
seed type More...
enum | trng_state_t { TRNG_STATE_RESET = 0x0U, TRNG_STATE_READY = 0x1U, TRNG_STATE_BUSY = 0x2U, TRNG_STATE_ERROR = 0x4U }
TRNG state structures definition. More...
enum | trng_status_t { TRNG_STATUS_START = (1U << 0), TRNG_STATUS_DAVLD = (1U << 1), TRNG_STATUS_SERR = (1U << 2) }
State type. More...
enum | trng_it_t { TRNG_IT_START = (1U << 0), TRNG_IT_DAVLD = (1U << 1), TRNG_IT_SERR = (1U << 2) }
Interrupt type. More...
enum | trng_flag_t { TRNG_IF_START = (1U << 0), TRNG_IF_DAVLD = (1U << 1), TRNG_IF_SERR = (1U << 2) }
Interrupt flag type. More...

Detailed Description

Typedef Documentation

◆ trng_handle_t

typedef struct trng_handle_s trng_handle_t

TRNG Handle Structure definition.

Enumeration Type Documentation

◆ trng_data_width_t

enum trng_data_width_t

Data width.

Enumerator
TRNG_DSEL_1B | 1-bit
TRNG_DSEL_8B | 8-bits
TRNG_DSEL_16B | 16-bits
TRNG_DSEL_32B | 32-bits

Definition at line 41 of file ald_trng.h.

41 {
42 TRNG_DSEL_1B = 0x0U,
43 TRNG_DSEL_8B = 0x1U,
44 TRNG_DSEL_16B = 0x2U,
45 TRNG_DSEL_32B = 0x3U,
46 } trng_data_width_t;
TRNG_DSEL_8B
Definition: ald_trng.h:43
TRNG_DSEL_32B
Definition: ald_trng.h:45
TRNG_DSEL_16B
Definition: ald_trng.h:44
trng_data_width_t
trng_data_width_t
Data width.
Definition: ald_trng.h:41
TRNG_DSEL_1B
Definition: ald_trng.h:42

◆ trng_flag_t

enum trng_flag_t

Interrupt flag type.

Enumerator
TRNG_IF_START | Start
TRNG_IF_DAVLD | Data valid
TRNG_IF_SERR | Error

Definition at line 101 of file ald_trng.h.

101 {
102 TRNG_IF_START = (1U << 0),
103 TRNG_IF_DAVLD = (1U << 1),
104 TRNG_IF_SERR = (1U << 2),
105 } trng_flag_t;
TRNG_IF_START
Definition: ald_trng.h:102
TRNG_IF_DAVLD
Definition: ald_trng.h:103
trng_flag_t
trng_flag_t
Interrupt flag type.
Definition: ald_trng.h:101
TRNG_IF_SERR
Definition: ald_trng.h:104

◆ trng_it_t

enum trng_it_t

Interrupt type.

Enumerator
TRNG_IT_START | Start
TRNG_IT_DAVLD | Data valid
TRNG_IT_SERR | Error

Definition at line 92 of file ald_trng.h.

92 {
93 TRNG_IT_START = (1U << 0),
94 TRNG_IT_DAVLD = (1U << 1),
95 TRNG_IT_SERR = (1U << 2),
96 } trng_it_t;
trng_it_t
trng_it_t
Interrupt type.
Definition: ald_trng.h:92
TRNG_IT_START
Definition: ald_trng.h:93
TRNG_IT_DAVLD
Definition: ald_trng.h:94
TRNG_IT_SERR
Definition: ald_trng.h:95

◆ trng_seed_type_t

enum trng_seed_type_t

seed type

Enumerator
TRNG_SEED_TYPE_0 | Using 0 as seed
TRNG_SEED_TYPE_1 | Using 1 as seed
TRNG_SEED_TYPE_LAST | Using last seed
TRNG_SEED_TYPE_SEED | Using value of register

Definition at line 51 of file ald_trng.h.

51 {
52 TRNG_SEED_TYPE_0 = 0x0U,
53 TRNG_SEED_TYPE_1 = 0x1U,
54 TRNG_SEED_TYPE_LAST = 0x2U,
55 TRNG_SEED_TYPE_SEED = 0x3U,
56 } trng_seed_type_t;
TRNG_SEED_TYPE_SEED
Definition: ald_trng.h:55
trng_seed_type_t
trng_seed_type_t
seed type
Definition: ald_trng.h:51
TRNG_SEED_TYPE_0
Definition: ald_trng.h:52
TRNG_SEED_TYPE_1
Definition: ald_trng.h:53
TRNG_SEED_TYPE_LAST
Definition: ald_trng.h:54

◆ trng_state_t

enum trng_state_t

TRNG state structures definition.

Enumerator
TRNG_STATE_RESET | Peripheral is not initialized
TRNG_STATE_READY | Peripheral Initialized and ready for use
TRNG_STATE_BUSY | An internal process is ongoing
TRNG_STATE_ERROR | Error

Definition at line 73 of file ald_trng.h.

73 {
74 TRNG_STATE_RESET = 0x0U,
75 TRNG_STATE_READY = 0x1U,
76 TRNG_STATE_BUSY = 0x2U,
77 TRNG_STATE_ERROR = 0x4U,
78 } trng_state_t;
TRNG_STATE_ERROR
Definition: ald_trng.h:77
TRNG_STATE_READY
Definition: ald_trng.h:75
TRNG_STATE_RESET
Definition: ald_trng.h:74
TRNG_STATE_BUSY
Definition: ald_trng.h:76
trng_state_t
trng_state_t
TRNG state structures definition.
Definition: ald_trng.h:73

◆ trng_status_t

enum trng_status_t

State type.

Enumerator
TRNG_STATUS_START | Start state
TRNG_STATUS_DAVLD | Data valid state
TRNG_STATUS_SERR | Error state

Definition at line 83 of file ald_trng.h.

83 {
84 TRNG_STATUS_START = (1U << 0),
85 TRNG_STATUS_DAVLD = (1U << 1),
86 TRNG_STATUS_SERR = (1U << 2),
87 } trng_status_t;
TRNG_STATUS_START
Definition: ald_trng.h:84
TRNG_STATUS_SERR
Definition: ald_trng.h:86
trng_status_t
trng_status_t
State type.
Definition: ald_trng.h:83
TRNG_STATUS_DAVLD
Definition: ald_trng.h:85


ALD User Manual: trng_init_t Struct Reference

Data Fields
trng_init_t Struct Reference
EASTSOFT ES32F3xx ALD » TRNG » TRNG Public Types

TRNG init structure definition. More...

#include <ald_trng.h>

Data Fields

trng_data_width_t data_width
trng_seed_type_t seed_type
uint32_t | seed
uint16_t | t_start
uint8_t | adjc
type_func_t posten

Detailed Description

TRNG init structure definition.

Definition at line 61 of file ald_trng.h.

Field Documentation

◆ adjc

uint8_t adjc

Adjust parameter

Definition at line 66 of file ald_trng.h.

◆ data_width

trng_data_width_t data_width

The width of data

Definition at line 62 of file ald_trng.h.

◆ posten

type_func_t posten

Data back handle function

Definition at line 67 of file ald_trng.h.

◆ seed

uint32_t seed

The value of seed

Definition at line 64 of file ald_trng.h.

◆ seed_type

trng_seed_type_t seed_type

The seed type

Definition at line 63 of file ald_trng.h.

◆ t_start

uint16_t t_start

T(start) = T(trng) * 2 ^ (t_start + 1), T(start) > 1ms

Definition at line 65 of file ald_trng.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_trng.h


ALD User Manual: trng_handle_s Struct Reference

Data Fields
trng_handle_s Struct Reference
EASTSOFT ES32F3xx ALD » TRNG » TRNG Public Types

TRNG Handle Structure definition. More...

#include <ald_trng.h>

Collaboration diagram for trng_handle_s:
[legend]

Data Fields

TRNG_TypeDef * | perh
trng_init_t init
uint32_t | data
lock_state_t lock
trng_state_t state
void(* | trng_cplt_cbk )(struct trng_handle_s *arg)
void(* | err_cplt_cbk )(struct trng_handle_s *arg)
void(* | init_cplt_cbk )(struct trng_handle_s *arg)

Detailed Description

TRNG Handle Structure definition.

Definition at line 110 of file ald_trng.h.

Field Documentation

◆ data

uint32_t data

result data

Definition at line 113 of file ald_trng.h.

◆ err_cplt_cbk

void(* err_cplt_cbk) (struct trng_handle_s *arg)

Trng error callback

Definition at line 118 of file ald_trng.h.

◆ init

trng_init_t init

TRNG required parameters

Definition at line 112 of file ald_trng.h.

◆ init_cplt_cbk

void(* init_cplt_cbk) (struct trng_handle_s *arg)

Trng init completed callback

Definition at line 119 of file ald_trng.h.

◆ lock

lock_state_t lock

Locking object

Definition at line 114 of file ald_trng.h.

◆ perh

TRNG_TypeDef* perh

Register base address

Definition at line 111 of file ald_trng.h.

◆ state

trng_state_t state

TRNG operation state

Definition at line 115 of file ald_trng.h.

◆ trng_cplt_cbk

void(* trng_cplt_cbk) (struct trng_handle_s *arg)

Trng completed callback

Definition at line 117 of file ald_trng.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_trng.h


ALD User Manual: TRNG Public Macros

Macros
TRNG Public Macros
EASTSOFT ES32F3xx ALD » TRNG
Collaboration diagram for TRNG Public Macros:

Macros

#define | TRNG_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))
#define | TRNG_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))
#define | TRNG_ADJM_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))
#define | TRNG_ADJM_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))

Detailed Description

Macro Definition Documentation

◆ TRNG_ADJM_DISABLE

#define TRNG_ADJM_DISABLE ( ) (CLEAR_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))

Definition at line 131 of file ald_trng.h.

◆ TRNG_ADJM_ENABLE

#define TRNG_ADJM_ENABLE ( ) (SET_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))

Definition at line 130 of file ald_trng.h.

◆ TRNG_DISABLE

#define TRNG_DISABLE ( ) (CLEAR_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))

Definition at line 129 of file ald_trng.h.

◆ TRNG_ENABLE

#define TRNG_ENABLE ( ) (SET_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))

Definition at line 128 of file ald_trng.h.


ALD User Manual: TRNG Private Macros

Macros
TRNG Private Macros
EASTSOFT ES32F3xx ALD » TRNG
Collaboration diagram for TRNG Private Macros:

Macros

#define | IS_TRNG_DATA_WIDTH(x)
#define | IS_TRNG_SEED_TYPE(x)
#define | IS_TRNG_STATUS(x)
#define | IS_TRNG_IT(x)
#define | IS_TRNG_FLAG(x)
#define | IS_TRNG_ADJC(x) ((x) < 4)
#define | IS_TRNG_T_START(x) ((x) < 8)

Detailed Description

Macro Definition Documentation

◆ IS_TRNG_ADJC

#define IS_TRNG_ADJC ( x ) ((x) < 4)

Definition at line 157 of file ald_trng.h.

◆ IS_TRNG_DATA_WIDTH

#define IS_TRNG_DATA_WIDTH ( x )
Value:
(((x) == TRNG_DSEL_1B) || \
((x) == TRNG_DSEL_8B) || \
((x) == TRNG_DSEL_16B) || \
((x) == TRNG_DSEL_32B))
TRNG_DSEL_8B
Definition: ald_trng.h:43
TRNG_DSEL_32B
Definition: ald_trng.h:45
TRNG_DSEL_16B
Definition: ald_trng.h:44
TRNG_DSEL_1B
Definition: ald_trng.h:42

Definition at line 140 of file ald_trng.h.

◆ IS_TRNG_FLAG

#define IS_TRNG_FLAG ( x )
Value:
(((x) == TRNG_IF_START) || \
((x) == TRNG_IF_DAVLD) || \
((x) == TRNG_IF_SERR))
TRNG_IF_START
Definition: ald_trng.h:102
TRNG_IF_DAVLD
Definition: ald_trng.h:103
TRNG_IF_SERR
Definition: ald_trng.h:104

Definition at line 154 of file ald_trng.h.

◆ IS_TRNG_IT

#define IS_TRNG_IT ( x )
Value:
(((x) == TRNG_IT_START) || \
((x) == TRNG_IT_DAVLD) || \
((x) == TRNG_IT_SERR))
TRNG_IT_START
Definition: ald_trng.h:93
TRNG_IT_DAVLD
Definition: ald_trng.h:94
TRNG_IT_SERR
Definition: ald_trng.h:95

Definition at line 151 of file ald_trng.h.

◆ IS_TRNG_SEED_TYPE

#define IS_TRNG_SEED_TYPE ( x )
Value:
(((x) == TRNG_SEED_TYPE_0) || \
((x) == TRNG_SEED_TYPE_1) || \
((x) == TRNG_SEED_TYPE_LAST) || \
((x) == TRNG_SEED_TYPE_SEED))
TRNG_SEED_TYPE_SEED
Definition: ald_trng.h:55
TRNG_SEED_TYPE_0
Definition: ald_trng.h:52
TRNG_SEED_TYPE_1
Definition: ald_trng.h:53
TRNG_SEED_TYPE_LAST
Definition: ald_trng.h:54

Definition at line 144 of file ald_trng.h.

◆ IS_TRNG_STATUS

#define IS_TRNG_STATUS ( x )
Value:
(((x) == TRNG_STATUS_START) || \
((x) == TRNG_STATUS_DAVLD) || \
((x) == TRNG_STATUS_SERR))
TRNG_STATUS_START
Definition: ald_trng.h:84
TRNG_STATUS_SERR
Definition: ald_trng.h:86
TRNG_STATUS_DAVLD
Definition: ald_trng.h:85

Definition at line 148 of file ald_trng.h.

◆ IS_TRNG_T_START

#define IS_TRNG_T_START ( x ) ((x) < 8)

Definition at line 158 of file ald_trng.h.


ALD User Manual: TSENSE

Modules
TSENSE
EASTSOFT ES32F3xx ALD

TSENSE module driver. More...

Collaboration diagram for TSENSE:

Modules

TSENSE Private Variables
TSENSE Public Functions
TSENSE Public Macros
TSENSE Public Types
TSENSE Private Macros

Detailed Description

TSENSE module driver.


ALD User Manual: TSENSE Private Variables

Variables
TSENSE Private Variables
EASTSOFT ES32F3xx ALD » TSENSE
Collaboration diagram for TSENSE Private Variables:

Variables

tsense_cbk __tsense_cbk

Detailed Description

Variable Documentation

◆ __tsense_cbk

tsense_cbk __tsense_cbk

Definition at line 35 of file ald_tsense.c.


ALD User Manual: TSENSE Public Functions

Modules
TSENSE Public Functions
EASTSOFT ES32F3xx ALD » TSENSE
Collaboration diagram for TSENSE Public Functions:

Modules

Initialization functions
Initialization functions.
Peripheral Control functions
Peripheral Control functions.

Detailed Description


ALD User Manual: Initialization functions

Functions
Initialization functions
EASTSOFT ES32F3xx ALD » TSENSE » TSENSE Public Functions

Initialization functions. More...

Collaboration diagram for Initialization functions:

Functions

void | ald_tsense_init (void)
Initializes the TSENSE according to the specified. More...
void | ald_tsense_source_select (tsense_source_sel_t sel)
Configure the TSENSE source. More...

Detailed Description

Initialization functions.

==============================================================================
            ##### Initialization functions #####
==============================================================================
  [..]  This section provides functions allowing to initialize the TSENSE:
    (+) This parameters can be configured:
      (++) Update Cycle
      (++) Output Mode
      (++) Perscaler
    (+) Select TSENSE source clock(default LOSC)

Function Documentation

◆ ald_tsense_init()

void ald_tsense_init ( void )

Initializes the TSENSE according to the specified.

Return values
None

Definition at line 66 of file ald_tsense.c.

67 {
68 uint16_t tempt, temptinv;
69 uint32_t tscic, tscicinv;
70
71 TSENSE_UNLOCK();
72 TSENSE->CR = 0;
73
74 SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK);
75 SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK);
76 MODIFY_REG(TSENSE->CR, TSENSE_CR_TSU_MSK, 0x4 << TSENSE_CR_TSU_POSS);
77 MODIFY_REG(TSENSE->CR, TSENSE_CR_TOM_MSK, 0x3 << TSENSE_CR_TOM_POSS);
78 MODIFY_REG(TSENSE->PSR, TSENSE_PSR_PRS_MSK, 0x1 << TSENSE_PSR_PRS_POSS);
79
80 TSENSE->HTGR = 0x1FD0C;
81 TSENSE->LTGR = 0x21BC1;
82 tempt = *(volatile uint16_t *)0x80348;
83 temptinv = *(volatile uint16_t *)0x8034A;
84 tscic = *(volatile uint32_t *)0x80350;
85 tscicinv = *(volatile uint32_t *)0x80358;
86
87 if ((tempt == (uint16_t)(~temptinv)) && (tscic == (~tscicinv))) {
88 TSENSE->TBDR = tempt;
89 TSENSE->TCALBDR = (tscic & 0x1FFFFFF) >> 6;
90 }
91 else {
92 TSENSE->TBDR = 0x1E00;
93 TSENSE->TCALBDR = 0x1FE70;
94 }
95
96 TSENSE_LOCK();
97 return;
98 }
TSENSE_UNLOCK
#define TSENSE_UNLOCK()
Definition: ald_rtchw.h:120
TSENSE_LOCK
#define TSENSE_LOCK()
Definition: ald_rtchw.h:119
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74

◆ ald_tsense_source_select()

void ald_tsense_source_select ( tsense_source_sel_t sel )

Configure the TSENSE source.

Parameters
sel TSENSE source type.
Return values
None

Definition at line 105 of file ald_tsense.c.

106 {
107 assert_param(IS_TSENSE_SOURCE_SEL(sel));
108
109 BKPC_UNLOCK();
110 MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TSENSECS_MSK, sel << BKPC_PCCR_TSENSECS_POSS);
111
112 if (sel == TSENSE_SOURCE_LOSC) {
113 SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);
114 }
115 else if (sel == TSENSE_SOURCE_LRC) {
116 SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);
117 }
118 else {
119 ; /* do nothing */
120 }
121
122 BKPC_LOCK();
123 return;
124 }
assert_param
#define assert_param(x)
Definition: type.h:88
TSENSE_SOURCE_LRC
Definition: ald_tsense.h:140
BKPC_LOCK
#define BKPC_LOCK()
Definition: ald_bkpc.h:38
TSENSE_SOURCE_LOSC
Definition: ald_tsense.h:139
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
BKPC_UNLOCK
#define BKPC_UNLOCK()
Definition: ald_bkpc.h:39
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_TSENSE_SOURCE_SEL
#define IS_TSENSE_SOURCE_SEL(x)
Definition: ald_tsense.h:156


ALD User Manual: Peripheral Control functions

Functions
Peripheral Control functions
EASTSOFT ES32F3xx ALD » TSENSE » TSENSE Public Functions

Peripheral Control functions. More...

Collaboration diagram for Peripheral Control functions:

Functions

ald_status_t | ald_tsense_get_value (uint16_t *tsense)
Get the current temperature. More...
void | ald_tsense_get_value_by_it (tsense_cbk cbk)
Get the current temperature by interrupt. More...
void | ald_tsense_irq_handler (void)
This function handles TSENSE interrupt request. More...

Detailed Description

Peripheral Control functions.

==============================================================================
            ##### Peripheral Control functions #####
==============================================================================
[..]  This section provides functions allowing to:
  (+) ald_tsense_get_value() API can get the current temperature.
  (+) ald_tsense_get_value_by_it() API can get the current temperature by interrupt.
  (+) ald_tsense_irq_handler() API can handle the interrupt request.

Function Documentation

◆ ald_tsense_get_value()

ald_status_t ald_tsense_get_value ( uint16_t * tsense )

Get the current temperature.

Parameters
tsense The value of current temperature.
Return values
ALD status:
  • OK The value is valid
  • ERROR The value is invalid

Definition at line 152 of file ald_tsense.c.

153 {
154 uint32_t tmp = 0;
155
156 TSENSE_UNLOCK();
157 SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
158 SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
159 TSENSE_LOCK();
160
161 while ((!(READ_BIT(TSENSE->IF, TSENSE_IF_TSENSE_MSK))) && (tmp++ < 1000000));
162
163 if (tmp >= 1000000) {
164 TSENSE_UNLOCK();
165 CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
166 TSENSE_LOCK();
167 return TIMEOUT;
168 }
169
170 TSENSE_UNLOCK();
171 SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
172 TSENSE_LOCK();
173
174 if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) {
175 TSENSE_UNLOCK();
176 CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
177 TSENSE_LOCK();
178 return ERROR;
179 }
180
181 *tsense = READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS);
182
183 TSENSE_UNLOCK();
184 CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
185 TSENSE_LOCK();
186
187 return OK;
188 }
OK
Definition: utils.h:55
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
TSENSE_UNLOCK
#define TSENSE_UNLOCK()
Definition: ald_rtchw.h:120
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
TIMEOUT
Definition: utils.h:58
TSENSE_LOCK
#define TSENSE_LOCK()
Definition: ald_rtchw.h:119
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
ERROR
Definition: utils.h:56

◆ ald_tsense_get_value_by_it()

void ald_tsense_get_value_by_it ( tsense_cbk cbk )

Get the current temperature by interrupt.

Parameters
cbk The callback function
Return values
None

Definition at line 195 of file ald_tsense.c.

196 {
197 __tsense_cbk = cbk;
198
199 TSENSE_UNLOCK();
200 SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
201 SET_BIT(TSENSE->IE, TSENSE_IE_TSENSE_MSK);
202 SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
203 TSENSE_LOCK();
204
205 return;
206 }
TSENSE_UNLOCK
#define TSENSE_UNLOCK()
Definition: ald_rtchw.h:120
__tsense_cbk
tsense_cbk __tsense_cbk
Definition: ald_tsense.c:35
TSENSE_LOCK
#define TSENSE_LOCK()
Definition: ald_rtchw.h:119
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67

◆ ald_tsense_irq_handler()

void ald_tsense_irq_handler ( void )

This function handles TSENSE interrupt request.

Return values
None

Definition at line 212 of file ald_tsense.c.

213 {
214 TSENSE_UNLOCK();
215 SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
216 TSENSE_LOCK();
217
218 if (__tsense_cbk == NULL) {
219 TSENSE_UNLOCK();
220 CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
221 TSENSE_LOCK();
222 return;
223 }
224
225 if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) {
226 TSENSE_UNLOCK();
227 CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
228 TSENSE_LOCK();
229 __tsense_cbk(0, ERROR);
230
231 return;
232 }
233
234 __tsense_cbk(READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS), OK);
235
236 TSENSE_UNLOCK();
237 SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
238 CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
239 TSENSE_LOCK();
240
241 return;
242 }
OK
Definition: utils.h:55
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
TSENSE_UNLOCK
#define TSENSE_UNLOCK()
Definition: ald_rtchw.h:120
__tsense_cbk
tsense_cbk __tsense_cbk
Definition: ald_tsense.c:35
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
TSENSE_LOCK
#define TSENSE_LOCK()
Definition: ald_rtchw.h:119
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
ERROR
Definition: utils.h:56


ALD User Manual: TSENSE Public Macros

Macros
TSENSE Public Macros
EASTSOFT ES32F3xx ALD » TSENSE
Collaboration diagram for TSENSE Public Macros:

Macros

#define | TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0U))
#define | TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669U))
#define | TSENSE_ENABLE()
#define | TSENSE_DISABLE()
#define | TSENSE_REQ_ENABLE()
#define | TSENSE_REQ_DISABLE()
#define | TSENSE_CTN_ENABLE()
#define | TSENSE_CTN_DISABLE()
#define | TSENSE_RESET()
#define | TSENSE_LTGR_WR(data)
#define | TSENSE_HTGR_WR(data)
#define | TSENSE_TBDR_WR(data)
#define | TSENSE_TCALBDR_WR(data)

Detailed Description

Macro Definition Documentation

◆ TSENSE_CTN_DISABLE

#define TSENSE_CTN_DISABLE ( )
Value:
do { \
TSENSE_UNLOCK(); \
CLEAR_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \
TSENSE_LOCK(); \
} while (0)

Definition at line 70 of file ald_tsense.h.

◆ TSENSE_CTN_ENABLE

#define TSENSE_CTN_ENABLE ( )
Value:
do { \
TSENSE_UNLOCK(); \
SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \
TSENSE_LOCK(); \
} while (0)

Definition at line 64 of file ald_tsense.h.

◆ TSENSE_DISABLE

#define TSENSE_DISABLE ( )
Value:
do { \
TSENSE_UNLOCK(); \
CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \
TSENSE_LOCK(); \
} while (0)

Definition at line 46 of file ald_tsense.h.

◆ TSENSE_ENABLE

#define TSENSE_ENABLE ( )
Value:
do { \
TSENSE_UNLOCK(); \
SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \
TSENSE_LOCK(); \
} while (0)

Definition at line 40 of file ald_tsense.h.

◆ TSENSE_HTGR_WR

#define TSENSE_HTGR_WR ( data )
Value:
do { \
TSENSE_UNLOCK(); \
WRITE_REG(TSENSE->HTGR, (data)); \
TSENSE_LOCK(); \
} while (0)

Definition at line 88 of file ald_tsense.h.

◆ TSENSE_LOCK

#define TSENSE_LOCK ( ) (WRITE_REG(TSENSE->WPR, 0x0U))

Definition at line 38 of file ald_tsense.h.

◆ TSENSE_LTGR_WR

#define TSENSE_LTGR_WR ( data )
Value:
do { \
TSENSE_UNLOCK(); \
WRITE_REG(TSENSE->LTGR, (data)); \
TSENSE_LOCK(); \
} while (0)

Definition at line 82 of file ald_tsense.h.

◆ TSENSE_REQ_DISABLE

#define TSENSE_REQ_DISABLE ( )
Value:
do { \
TSENSE_UNLOCK(); \
CLEAR_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \
TSENSE_LOCK(); \
} while (0)

Definition at line 58 of file ald_tsense.h.

◆ TSENSE_REQ_ENABLE

#define TSENSE_REQ_ENABLE ( )
Value:
do { \
TSENSE_UNLOCK(); \
SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \
TSENSE_LOCK(); \
} while (0)

Definition at line 52 of file ald_tsense.h.

◆ TSENSE_RESET

#define TSENSE_RESET ( )
Value:
do { \
TSENSE_UNLOCK(); \
SET_BIT(TSENSE->CR, TSENSE_CR_RST_MSK); \
TSENSE_LOCK(); \
} while (0)

Definition at line 76 of file ald_tsense.h.

◆ TSENSE_TBDR_WR

#define TSENSE_TBDR_WR ( data )
Value:
do { \
TSENSE_UNLOCK(); \
WRITE_REG(TSENSE->TBDR, (data)); \
TSENSE_LOCK(); \
} while (0)

Definition at line 94 of file ald_tsense.h.

◆ TSENSE_TCALBDR_WR

#define TSENSE_TCALBDR_WR ( data )
Value:
do { \
TSENSE_UNLOCK(); \
WRITE_REG(TSENSE->TCALBDR, (data)); \
TSENSE_LOCK(); \
} while (0)

Definition at line 100 of file ald_tsense.h.

◆ TSENSE_UNLOCK

#define TSENSE_UNLOCK ( ) (WRITE_REG(TSENSE->WPR, 0xA55A9669U))

Definition at line 39 of file ald_tsense.h.


ALD User Manual: TSENSE Public Types

Typedefs | Enumerations
TSENSE Public Types
EASTSOFT ES32F3xx ALD » TSENSE
Collaboration diagram for TSENSE Public Types:

Typedefs

typedef void(* tsense_cbk) (uint16_t value, ald_status_t status)
Define callback function type. More...

Enumerations

enum tsense_update_cycle_t {
TSENSE_UPDATE_CYCLE_3 = 0x3U, TSENSE_UPDATE_CYCLE_4 = 0x4U, TSENSE_UPDATE_CYCLE_5 = 0x5U, TSENSE_UPDATE_CYCLE_6 = 0x6U,
TSENSE_UPDATE_CYCLE_7 = 0x7U
}
Temperature update time. More...
enum tsense_output_mode_t {
TSENSE_OUTPUT_MODE_200 = 0x0U, TSENSE_OUTPUT_MODE_400 = 0x1U, TSENSE_OUTPUT_MODE_800 = 0x2U, TSENSE_OUTPUT_MODE_1600 = 0x3U,
TSENSE_OUTPUT_MODE_3200 = 0x4U
}
Temperature output mode. More...
enum tsense_source_sel_t { TSENSE_SOURCE_LOSC = 0x0U, TSENSE_SOURCE_LRC = 0x1U }
Source select. More...

Detailed Description

Typedef Documentation

◆ tsense_cbk

typedef void(* tsense_cbk) (uint16_t value, ald_status_t status)

Define callback function type.

Definition at line 147 of file ald_tsense.h.

Enumeration Type Documentation

◆ tsense_output_mode_t

enum tsense_output_mode_t

Temperature output mode.

Enumerator
TSENSE_OUTPUT_MODE_200 | 200 cycles update one temperature
TSENSE_OUTPUT_MODE_400 | 400 cycles update one temperature
TSENSE_OUTPUT_MODE_800 | 800 cycles update one temperature
TSENSE_OUTPUT_MODE_1600 | 1600 cycles update one temperature
TSENSE_OUTPUT_MODE_3200 | 3200 cycles update one temperature

Definition at line 127 of file ald_tsense.h.

127 {
128 TSENSE_OUTPUT_MODE_200 = 0x0U,
129 TSENSE_OUTPUT_MODE_400 = 0x1U,
130 TSENSE_OUTPUT_MODE_800 = 0x2U,
131 TSENSE_OUTPUT_MODE_1600 = 0x3U,
132 TSENSE_OUTPUT_MODE_3200 = 0x4U,
133 } tsense_output_mode_t;
tsense_output_mode_t
tsense_output_mode_t
Temperature output mode.
Definition: ald_tsense.h:127
TSENSE_OUTPUT_MODE_200
Definition: ald_tsense.h:128
TSENSE_OUTPUT_MODE_3200
Definition: ald_tsense.h:132
TSENSE_OUTPUT_MODE_1600
Definition: ald_tsense.h:131
TSENSE_OUTPUT_MODE_400
Definition: ald_tsense.h:129
TSENSE_OUTPUT_MODE_800
Definition: ald_tsense.h:130

◆ tsense_source_sel_t

enum tsense_source_sel_t

Source select.

Enumerator
TSENSE_SOURCE_LOSC | LOSC
TSENSE_SOURCE_LRC | LRC

Definition at line 138 of file ald_tsense.h.

138 {
139 TSENSE_SOURCE_LOSC = 0x0U,
140 TSENSE_SOURCE_LRC = 0x1U,
141 } tsense_source_sel_t;
tsense_source_sel_t
tsense_source_sel_t
Source select.
Definition: ald_tsense.h:138
TSENSE_SOURCE_LRC
Definition: ald_tsense.h:140
TSENSE_SOURCE_LOSC
Definition: ald_tsense.h:139

◆ tsense_update_cycle_t

enum tsense_update_cycle_t

Temperature update time.

Enumerator
TSENSE_UPDATE_CYCLE_3 | 3 Cycles
TSENSE_UPDATE_CYCLE_4 | 4 Cycles
TSENSE_UPDATE_CYCLE_5 | 5 Cycles
TSENSE_UPDATE_CYCLE_6 | 6 Cycles
TSENSE_UPDATE_CYCLE_7 | 7 Cycles

Definition at line 116 of file ald_tsense.h.

116 {
117 TSENSE_UPDATE_CYCLE_3 = 0x3U,
118 TSENSE_UPDATE_CYCLE_4 = 0x4U,
119 TSENSE_UPDATE_CYCLE_5 = 0x5U,
120 TSENSE_UPDATE_CYCLE_6 = 0x6U,
121 TSENSE_UPDATE_CYCLE_7 = 0x7U,
122 } tsense_update_cycle_t;
TSENSE_UPDATE_CYCLE_3
Definition: ald_tsense.h:117
tsense_update_cycle_t
tsense_update_cycle_t
Temperature update time.
Definition: ald_tsense.h:116
TSENSE_UPDATE_CYCLE_5
Definition: ald_tsense.h:119
TSENSE_UPDATE_CYCLE_6
Definition: ald_tsense.h:120
TSENSE_UPDATE_CYCLE_4
Definition: ald_tsense.h:118
TSENSE_UPDATE_CYCLE_7
Definition: ald_tsense.h:121


ALD User Manual: TSENSE Private Macros

Macros
TSENSE Private Macros
EASTSOFT ES32F3xx ALD » TSENSE
Collaboration diagram for TSENSE Private Macros:

Macros

#define IS_TSENSE_SOURCE_SEL(x)

Detailed Description

Macro Definition Documentation

◆ IS_TSENSE_SOURCE_SEL

#define IS_TSENSE_SOURCE_SEL ( x )
Value:
(((x) == TSENSE_SOURCE_LOSC) || \
((x) == TSENSE_SOURCE_LRC))
TSENSE_SOURCE_LRC
Definition: ald_tsense.h:140
TSENSE_SOURCE_LOSC
Definition: ald_tsense.h:139

Definition at line 156 of file ald_tsense.h.


ALD User Manual: UART

Modules
UART
EASTSOFT ES32F3xx ALD

UART module driver. More...

Collaboration diagram for UART:

Modules

UART Private Functions
UART Private functions.
UART Public Functions
UART Public Macros
UART Public Types
UART Private Macros

Detailed Description

UART module driver.


ALD User Manual: UART Private Functions

Functions
UART Private Functions
EASTSOFT ES32F3xx ALD » UART

UART Private functions. More...

Collaboration diagram for UART Private Functions:

Functions

static void | uart_dma_send_cplt (void *arg)
DMA uart transmit process complete callback. More...
static void | uart_dma_recv_cplt (void *arg)
DMA uart receive process complete callback. More...
static void | uart_dma_error (void *arg)
DMA uart communication error callback. More...
static ald_status_t | uart_wait_flag (uart_handle_t *hperh, uart_status_t flag, flag_status_t status, uint32_t timeout)
This function handles uart Communication Timeout. More...
static ald_status_t | __uart_send_by_it (uart_handle_t *hperh)
Sends an amount of data in non blocking mode. More...
static ald_status_t | __uart_end_send_by_it (uart_handle_t *hperh)
Wraps up transmission in non blocking mode. More...
static ald_status_t | __uart_recv_by_it (uart_handle_t *hperh)
Receives an amount of data in non blocking mode. More...

Detailed Description

UART Private functions.

Function Documentation

◆ __uart_end_send_by_it()

static ald_status_t __uart_end_send_by_it ( uart_handle_t * hperh )
static

Wraps up transmission in non blocking mode.

Parameters
hperh pointer to a uart_handle_t structure.
Return values
Status,see ald_status_t.

Definition at line 221 of file ald_uart.c.

222 {
223 uint32_t cnt = 0xFFFFFF;
224
225 ald_uart_interrupt_config(hperh, UART_IT_TSEMPTY, DISABLE);
226 CLEAR_BIT(hperh->state, UART_STATE_TX_MASK);
227
228 while ((hperh->perh->STAT & UART_STATUS_TSBUSY) && (cnt--));
229
230 if (hperh->tx_cplt_cbk)
231 hperh->tx_cplt_cbk(hperh);
232
233 return OK;
234 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
OK
Definition: utils.h:55
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
uart_handle_s::tx_cplt_cbk
void(* tx_cplt_cbk)(struct uart_handle_s *arg)
Definition: ald_uart.h:187
UART_IT_TSEMPTY
Definition: ald_uart.h:320
ald_uart_interrupt_config
void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state)
Enable/disable the specified UART interrupts.
Definition: ald_uart.c:1126
DISABLE
Definition: type.h:48
UART_STATUS_TSBUSY
Definition: ald_uart.h:296
UART_STATE_TX_MASK
#define UART_STATE_TX_MASK
Definition: ald_uart.h:454
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171

◆ __uart_recv_by_it()

static ald_status_t __uart_recv_by_it ( uart_handle_t * hperh )
static

Receives an amount of data in non blocking mode.

Parameters
hperh Pointer to a uart_handle_t structure.
Return values
Status,see ald_status_t.

Definition at line 241 of file ald_uart.c.

242 {
243 if ((hperh->state & UART_STATE_RX_MASK) == 0x0)
244 return BUSY;
245
246 while (READ_BITS(hperh->perh->FCON, UART_FCON_RXFL_MSK, UART_FCON_RXFL_POSS)) {
247 *hperh->rx_buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF);
248 hperh->rx_count++;
249
250 if (hperh->rx_count >= hperh->rx_size)
251 break;
252 }
253
254 if (hperh->rx_count >= hperh->rx_size) {
255 ald_uart_interrupt_config(hperh, UART_IT_RFTH, DISABLE);
256 CLEAR_BIT(hperh->state, UART_STATE_RX_MASK);
257
258 if (hperh->rx_cplt_cbk)
259 hperh->rx_cplt_cbk(hperh);
260 }
261
262 return OK;
263 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
OK
Definition: utils.h:55
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
BUSY
Definition: utils.h:57
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
ald_uart_interrupt_config
void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state)
Enable/disable the specified UART interrupts.
Definition: ald_uart.c:1126
DISABLE
Definition: type.h:48
UART_STATE_RX_MASK
#define UART_STATE_RX_MASK
Definition: ald_uart.h:455
uart_handle_s::rx_cplt_cbk
void(* rx_cplt_cbk)(struct uart_handle_s *arg)
Definition: ald_uart.h:188
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
uart_handle_s::rx_size
uint16_t rx_size
Definition: ald_uart.h:177
UART_IT_RFTH
Definition: ald_uart.h:316
uart_handle_s::rx_count
uint16_t rx_count
Definition: ald_uart.h:178
uart_handle_s::rx_buf
uint8_t * rx_buf
Definition: ald_uart.h:176

◆ __uart_send_by_it()

static ald_status_t __uart_send_by_it ( uart_handle_t * hperh )
static

Sends an amount of data in non blocking mode.

Parameters
hperh Pointer to a uart_handle_t structure.
Return values
Status,see ald_status_t.

Definition at line 200 of file ald_uart.c.

201 {
202 if ((hperh->state & UART_STATE_TX_MASK) == 0x0)
203 return BUSY;
204
205 hperh->perh->TXBUF = (uint8_t)(*hperh->tx_buf++ & 0x00FF);
206 hperh->tx_count++;
207
208 if (hperh->tx_count >= hperh->tx_size) {
209 ald_uart_interrupt_config(hperh, UART_IT_TFTH, DISABLE);
210 ald_uart_interrupt_config(hperh, UART_IT_TSEMPTY, ENABLE);
211 }
212
213 return OK;
214 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
BUSY
Definition: utils.h:57
UART_IT_TSEMPTY
Definition: ald_uart.h:320
ald_uart_interrupt_config
void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state)
Enable/disable the specified UART interrupts.
Definition: ald_uart.c:1126
DISABLE
Definition: type.h:48
uart_handle_s::tx_buf
uint8_t * tx_buf
Definition: ald_uart.h:173
UART_STATE_TX_MASK
#define UART_STATE_TX_MASK
Definition: ald_uart.h:454
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
UART_IT_TFTH
Definition: ald_uart.h:321
uart_handle_s::tx_size
uint16_t tx_size
Definition: ald_uart.h:174
uart_handle_s::tx_count
uint16_t tx_count
Definition: ald_uart.h:175

◆ uart_dma_error()

static void uart_dma_error ( void * arg )
static

DMA uart communication error callback.

Parameters
arg Pointer to a uart_handle_t structure.
Return values
None

Definition at line 151 of file ald_uart.c.

152 {
153 uart_handle_t *hperh = (uart_handle_t *)arg;
154
155 hperh->rx_count = 0;
156 hperh->tx_count = 0;
157 hperh->state = UART_STATE_READY;
158 hperh->err_code |= UART_ERROR_DMA;
159 ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, DISABLE);
160 ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, DISABLE);
161
162 if (hperh->error_cbk)
163 hperh->error_cbk(hperh);
164
165 return;
166 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
uart_handle_s::err_code
uart_error_t err_code
Definition: ald_uart.h:185
DISABLE
Definition: type.h:48
UART_STATE_READY
Definition: ald_uart.h:134
uart_handle_s
UART handle structure definition.
Definition: ald_uart.h:170
UART_DMA_REQ_TX
Definition: ald_uart.h:278
UART_ERROR_DMA
Definition: ald_uart.h:152
UART_DMA_REQ_RX
Definition: ald_uart.h:279
ald_uart_dma_req_config
void ald_uart_dma_req_config(uart_handle_t *hperh, uart_dma_req_t req, type_func_t state)
Configure UART DMA request.
Definition: ald_uart.c:1150
uart_handle_s::rx_count
uint16_t rx_count
Definition: ald_uart.h:178
uart_handle_s::error_cbk
void(* error_cbk)(struct uart_handle_s *arg)
Definition: ald_uart.h:189
uart_handle_s::tx_count
uint16_t tx_count
Definition: ald_uart.h:175

◆ uart_dma_recv_cplt()

static void uart_dma_recv_cplt ( void * arg )
static

DMA uart receive process complete callback.

Parameters
arg Pointer to a uart_handle_t structure.
Return values
None

Definition at line 131 of file ald_uart.c.

132 {
133 uart_handle_t *hperh = (uart_handle_t *)arg;
134 hperh->tx_count = hperh->tx_size;
135
136 ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, DISABLE);
137 hperh->rx_count = 0;
138 CLEAR_BIT(hperh->state, UART_STATE_RX_MASK);
139
140 if (hperh->rx_cplt_cbk)
141 hperh->rx_cplt_cbk(hperh);
142
143 return;
144 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
DISABLE
Definition: type.h:48
UART_STATE_RX_MASK
#define UART_STATE_RX_MASK
Definition: ald_uart.h:455
uart_handle_s::rx_cplt_cbk
void(* rx_cplt_cbk)(struct uart_handle_s *arg)
Definition: ald_uart.h:188
uart_handle_s
UART handle structure definition.
Definition: ald_uart.h:170
UART_DMA_REQ_RX
Definition: ald_uart.h:279
ald_uart_dma_req_config
void ald_uart_dma_req_config(uart_handle_t *hperh, uart_dma_req_t req, type_func_t state)
Configure UART DMA request.
Definition: ald_uart.c:1150
uart_handle_s::rx_count
uint16_t rx_count
Definition: ald_uart.h:178
uart_handle_s::tx_size
uint16_t tx_size
Definition: ald_uart.h:174
uart_handle_s::tx_count
uint16_t tx_count
Definition: ald_uart.h:175

◆ uart_dma_send_cplt()

static void uart_dma_send_cplt ( void * arg )
static

DMA uart transmit process complete callback.

Parameters
arg Pointer to a uart_handle_t structure.
Return values
None

Definition at line 113 of file ald_uart.c.

114 {
115 uart_handle_t *hperh = (uart_handle_t *)arg;
116 hperh->tx_count = hperh->tx_size;
117
118 ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, DISABLE);
119 hperh->tx_count = 0;
120 ald_uart_interrupt_config(hperh, UART_IT_TSEMPTY, ENABLE);
121 CLEAR_BIT(hperh->state, UART_STATE_TX_MASK);
122
123 return;
124 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
ENABLE
Definition: type.h:49
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
UART_IT_TSEMPTY
Definition: ald_uart.h:320
ald_uart_interrupt_config
void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state)
Enable/disable the specified UART interrupts.
Definition: ald_uart.c:1126
DISABLE
Definition: type.h:48
uart_handle_s
UART handle structure definition.
Definition: ald_uart.h:170
UART_STATE_TX_MASK
#define UART_STATE_TX_MASK
Definition: ald_uart.h:454
UART_DMA_REQ_TX
Definition: ald_uart.h:278
ald_uart_dma_req_config
void ald_uart_dma_req_config(uart_handle_t *hperh, uart_dma_req_t req, type_func_t state)
Configure UART DMA request.
Definition: ald_uart.c:1150
uart_handle_s::tx_size
uint16_t tx_size
Definition: ald_uart.h:174
uart_handle_s::tx_count
uint16_t tx_count
Definition: ald_uart.h:175

◆ uart_wait_flag()

static ald_status_t uart_wait_flag | ( | uart_handle_t * | hperh,
 |  | uart_status_t | flag,
 |  | flag_status_t | status,
 |  | uint32_t | timeout
 | ) |  |
static

This function handles uart Communication Timeout.

Parameters
hperh | Pointer to a uart_handle_t structure.
flag | specifies the uart flag to check.
status | The new Flag status (SET or RESET).
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 177 of file ald_uart.c.

178 {
179 uint32_t tick;
180
181 if (timeout == 0)
182 return ERROR;
183
184 tick = ald_get_tick();
185
186 /* Waiting for flag */
187 while ((ald_uart_get_status(hperh, flag)) != status) {
188 if (((ald_get_tick()) - tick) > timeout)
189 return TIMEOUT;
190 }
191
192 return OK;
193 }
OK
Definition: utils.h:55
ald_uart_get_status
flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status)
Get the status of UART_SR register.
Definition: ald_uart.c:1344
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
ERROR
Definition: utils.h:56


ALD User Manual: UART Public Functions

Modules
UART Public Functions
EASTSOFT ES32F3xx ALD » UART
Collaboration diagram for UART Public Functions:

Modules

Initialization and Configuration functions
Initialization and Configuration functions.
IO operation functions
UART Transmit and Receive functions.
Peripheral Control functions
UART control functions.
Peripheral State and Errors functions
UART State and Errors functions.

Detailed Description


ALD User Manual: Initialization and Configuration functions

Functions
Initialization and Configuration functions
EASTSOFT ES32F3xx ALD » UART » UART Public Functions

Initialization and Configuration functions. More...

Collaboration diagram for Initialization and Configuration functions:

Functions

void | ald_uart_reset (uart_handle_t *hperh)
Reset UART peripheral. More...
void | ald_uart_init (uart_handle_t *hperh)
Initializes the UARTx according to the specified parameters in the uart_handle_t. More...
void | ald_uart_rs485_config (uart_handle_t *hperh, uart_rs485_config_t *config)
Configure the RS485 mode according to the specified parameters in the uart_rs485_config_t. More...
void | ald_uart_scard_config (uart_handle_t *hperh, uart_scard_config_t *config)
Configure the smart card mode according to the specified parameters in the uart_scard_config_t. More...

Detailed Description

Initialization and Configuration functions.

===============================================================================
            ##### Initialization and Configuration functions #####
 ===============================================================================
    [..]
    This subsection provides a set of functions allowing to initialize the UARTx
    and configure UARTx param.
      (+) For the UARTx only these parameters can be configured:
        (++) Baud Rate
        (++) Word Length
        (++) Stop Bit
        (++) Parity
        (++) Hardware flow control
      (+) For RS485 mode, user also need configure some parameters by
          ald_uart_rs485_config():
        (++) Enable/disable normal point mode
        (++) Enable/disable auto-direction
        (++) Enable/disable address detection invert
        (++) Enable/disable address for compare

Function Documentation

◆ ald_uart_init()

void ald_uart_init ( uart_handle_t * hperh )

Initializes the UARTx according to the specified parameters in the uart_handle_t.

Parameters
hperh Pointer to a uart_handle_t structure that contains the configuration information for the specified UART module.
Return values
None

Definition at line 331 of file ald_uart.c.

332 {
333 assert_param(IS_UART_ALL(hperh->perh));
334 assert_param(IS_UART_BAUDRATE(hperh->init.baud));
335 assert_param(IS_UART_WORD_LENGTH(hperh->init.word_length));
336 assert_param(IS_UART_STOPBITS(hperh->init.stop_bits));
337 assert_param(IS_UART_PARITY(hperh->init.parity));
338 assert_param(IS_UART_MODE(hperh->init.mode));
339 assert_param(IS_UART_HARDWARE_FLOW_CONTROL(hperh->init.fctl));
340
341 ald_uart_reset(hperh);
342
343 MODIFY_REG(hperh->perh->LCON, UART_LCON_DLS_MSK, hperh->init.word_length << UART_LCON_DLS_POSS);
344 MODIFY_REG(hperh->perh->LCON, UART_LCON_STOP_MSK, hperh->init.stop_bits << UART_LCON_STOP_POS);
345
346 if ((hperh->init.parity) != UART_PARITY_NONE) {
347 SET_BIT(hperh->perh->LCON, UART_LCON_PE_MSK);
348
349 if ((hperh->init.parity) == UART_PARITY_ODD)
350 CLEAR_BIT(hperh->perh->LCON, UART_LCON_PS_MSK);
351
352 if ((hperh->init.parity) == UART_PARITY_EVEN)
353 SET_BIT(hperh->perh->LCON, UART_LCON_PS_MSK);
354 }
355
356 MODIFY_REG(hperh->perh->MCON, UART_MCON_AFCEN_MSK, hperh->init.fctl << UART_MCON_AFCEN_POS);
357 hperh->perh->BRR = (ald_cmu_get_pclk1_clock() + (hperh->init.baud >> 1)) / hperh->init.baud;
358
359 if (hperh->init.mode == UART_MODE_LIN)
360 SET_BIT(hperh->perh->LIN, UART_LIN_LINEN_MSK);
361 else if (hperh->init.mode == UART_MODE_IrDA)
362 SET_BIT(hperh->perh->MCON, UART_MCON_IREN_MSK);
363 else if (hperh->init.mode == UART_MODE_RS485)
364 SET_BIT(hperh->perh->RS485, UART_RS485_AADEN_MSK);
365 else if (hperh->init.mode == UART_MODE_HDSEL)
366 SET_BIT(hperh->perh->MCON, UART_MCON_HDEN_MSK);
367 else if (hperh->init.mode == UART_MODE_SCARD)
368 SET_BIT(hperh->perh->SCARD, UART_SCARD_SCEN_MSK);
369 else
370 ; /* do nothing */
371
372 SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK);
373 SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK);
374 CLEAR_BIT(hperh->perh->FCON, UART_FCON_TXTH_MSK);
375 CLEAR_BIT(hperh->perh->FCON, UART_FCON_RXTH_MSK);
376 SET_BIT(hperh->perh->LCON, UART_LCON_RXEN_MSK);
377 SET_BIT(hperh->perh->LCON, UART_LCON_TXEN_MSK);
378
379 hperh->state = UART_STATE_READY;
380 hperh->err_code = UART_ERROR_NONE;
381 return;
382 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
UART_MODE_LIN
Definition: ald_uart.h:114
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
uart_handle_s::err_code
uart_error_t err_code
Definition: ald_uart.h:185
uart_init_t::baud
uint32_t baud
Definition: ald_uart.h:159
uart_init_t::stop_bits
uart_stop_bits_t stop_bits
Definition: ald_uart.h:161
UART_STATE_READY
Definition: ald_uart.h:134
UART_PARITY_EVEN
Definition: ald_uart.h:106
UART_MODE_SCARD
Definition: ald_uart.h:118
UART_MODE_IrDA
Definition: ald_uart.h:115
uart_init_t::fctl
uart_hw_flow_ctl_t fctl
Definition: ald_uart.h:164
IS_UART_PARITY
#define IS_UART_PARITY(x)
Definition: ald_uart.h:371
UART_MODE_HDSEL
Definition: ald_uart.h:117
UART_ERROR_NONE
Definition: ald_uart.h:147
IS_UART_STOPBITS
#define IS_UART_STOPBITS(x)
Definition: ald_uart.h:367
uart_handle_s::init
uart_init_t init
Definition: ald_uart.h:172
UART_MODE_RS485
Definition: ald_uart.h:116
uart_init_t::mode
uart_mode_t mode
Definition: ald_uart.h:163
IS_UART_HARDWARE_FLOW_CONTROL
#define IS_UART_HARDWARE_FLOW_CONTROL(x)
Definition: ald_uart.h:380
ald_uart_reset
void ald_uart_reset(uart_handle_t *hperh)
Reset UART peripheral.
Definition: ald_uart.c:303
UART_PARITY_ODD
Definition: ald_uart.h:105
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
IS_UART_WORD_LENGTH
#define IS_UART_WORD_LENGTH(x)
Definition: ald_uart.h:363
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
uart_init_t::word_length
uart_word_length_t word_length
Definition: ald_uart.h:160
ald_cmu_get_pclk1_clock
uint32_t ald_cmu_get_pclk1_clock(void)
Get APB1 clock.
Definition: ald_cmu.c:627
uart_init_t::parity
uart_parity_t parity
Definition: ald_uart.h:162
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_UART_BAUDRATE
#define IS_UART_BAUDRATE(x)
Definition: ald_uart.h:451
IS_UART_MODE
#define IS_UART_MODE(x)
Definition: ald_uart.h:374
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
UART_PARITY_NONE
Definition: ald_uart.h:104

◆ ald_uart_reset()

void ald_uart_reset ( uart_handle_t * hperh )

Reset UART peripheral.

Parameters
hperh Pointer to a uart_handle_t structure that contains the configuration information for the specified uart module.
Return values
None

Definition at line 303 of file ald_uart.c.

304 {
305 assert_param(IS_UART_ALL(hperh->perh));
306
307
308 WRITE_REG(hperh->perh->BRR, 0x0);
309 WRITE_REG(hperh->perh->LCON, 0x0);
310 WRITE_REG(hperh->perh->MCON, 0x0);
311 WRITE_REG(hperh->perh->RS485, 0x0);
312 WRITE_REG(hperh->perh->SCARD, 0x0);
313 WRITE_REG(hperh->perh->LIN, 0x0);
314 WRITE_REG(hperh->perh->RTOR, 0x0);
315 WRITE_REG(hperh->perh->FCON, 0x0);
316 WRITE_REG(hperh->perh->IDR, 0xFFF);
317 hperh->err_code = UART_ERROR_NONE;
318 hperh->state = UART_STATE_RESET;
319
320 __UNLOCK(hperh);
321 return;
322 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
uart_handle_s::err_code
uart_error_t err_code
Definition: ald_uart.h:185
UART_ERROR_NONE
Definition: ald_uart.h:147
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
UART_STATE_RESET
Definition: ald_uart.h:133
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72

◆ ald_uart_rs485_config()

void ald_uart_rs485_config | ( | uart_handle_t * | hperh,
 |  | uart_rs485_config_t * | config
 | ) |  |

Configure the RS485 mode according to the specified parameters in the uart_rs485_config_t.

Parameters
hperh | Pointer to a uart_handle_t structure that contains the configuration information for the specified UART module.
config | Specifies the RS485 parameters.
Return values
None

Definition at line 392 of file ald_uart.c.

393 {
394 assert_param(IS_UART_ALL(hperh->perh));
395 assert_param(IS_FUNC_STATE(config->normal));
396 assert_param(IS_FUNC_STATE(config->dir));
397 assert_param(IS_FUNC_STATE(config->invert));
398
399 MODIFY_REG(hperh->perh->RS485, UART_RS485_AADNEN_MSK, config->normal << UART_RS485_AADNEN_POS);
400 MODIFY_REG(hperh->perh->RS485, UART_RS485_AADACEN_MSK, config->dir << UART_RS485_AADACEN_POS);
401 MODIFY_REG(hperh->perh->RS485, UART_RS485_AADINV_MSK, config->invert << UART_RS485_AADINV_POS);
402 MODIFY_REG(hperh->perh->RS485, UART_RS485_ADDR_MSK, config->addr << UART_RS485_ADDR_POSS);
403
404 return;
405 }
assert_param
#define assert_param(x)
Definition: type.h:88
uart_rs485_config_t::invert
type_func_t invert
Definition: ald_uart.h:198
uart_rs485_config_t::addr
uint8_t addr
Definition: ald_uart.h:199
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
uart_rs485_config_t::normal
type_func_t normal
Definition: ald_uart.h:196
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
uart_rs485_config_t::dir
type_func_t dir
Definition: ald_uart.h:197

◆ ald_uart_scard_config()

void ald_uart_scard_config | ( | uart_handle_t * | hperh,
 |  | uart_scard_config_t * | config
 | ) |  |

Configure the smart card mode according to the specified parameters in the uart_scard_config_t.

Parameters
hperh | Pointer to a uart_handle_t structure that contains the configuration information for the specified UART module.
config | Specifies the scard parameters.
Return values
None

Definition at line 415 of file ald_uart.c.

416 {
417 assert_param(IS_UART_SCARD(hperh->perh));
418 assert_param(IS_UART_SCARD_CLK(config->clk_div));
419
420 MODIFY_REG(hperh->perh->SCARD, UART_SCARD_BLEN_MSK, config->block_len << UART_SCARD_BLEN_POSS);
421 MODIFY_REG(hperh->perh->SCARD, UART_SCARD_GT_MSK, config->pt << UART_SCARD_GT_POSS);
422 MODIFY_REG(hperh->perh->SCARD, UART_SCARD_SCCNT_MSK, config->retry << UART_SCARD_SCCNT_POSS);
423 MODIFY_REG(hperh->perh->SCARD, UART_SCARD_PSC_MSK, config->clk_div << UART_SCARD_PSC_POSS);
424 MODIFY_REG(hperh->perh->SCARD, UART_SCARD_SCLKEN_MSK, config->clk_out << UART_SCARD_SCLKEN_POS);
425
426 return;
427 }
assert_param
#define assert_param(x)
Definition: type.h:88
uart_scard_config_t::clk_out
type_func_t clk_out
Definition: ald_uart.h:234
uart_scard_config_t::block_len
uint8_t block_len
Definition: ald_uart.h:230
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
uart_scard_config_t::pt
uint8_t pt
Definition: ald_uart.h:231
IS_UART_SCARD_CLK
#define IS_UART_SCARD_CLK(x)
Definition: ald_uart.h:447
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
uart_scard_config_t::retry
scard_retry_t retry
Definition: ald_uart.h:232
IS_UART_SCARD
#define IS_UART_SCARD(x)
Definition: ald_uart.h:355
uart_scard_config_t::clk_div
scard_clk_div_t clk_div
Definition: ald_uart.h:233


ALD User Manual: IO operation functions

Functions
IO operation functions
EASTSOFT ES32F3xx ALD » UART » UART Public Functions

UART Transmit and Receive functions. More...

Collaboration diagram for IO operation functions:

Functions

ald_status_t | ald_uart_send (uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Sends an amount of data in blocking mode. More...
ald_status_t | ald_uart_recv (uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Receives an amount of data in blocking mode. More...
ald_status_t | ald_uart_send_n_lock (uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Sends an amount of data in blocking mode. Don't care about device lock. This is for RTOS. More...
ald_status_t | ald_uart_recv_n_lock (uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Receives an amount of data in blocking mode. Don't care about device lock. This is for RTOS. More...
ald_status_t | ald_uart_send_by_it (uart_handle_t *hperh, uint8_t *buf, uint16_t size)
Sends an amount of data in non blocking mode. More...
ald_status_t | ald_uart_recv_by_it (uart_handle_t *hperh, uint8_t *buf, uint16_t size)
Receives an amount of data in non blocking mode. More...
ald_status_t | ald_uart_recv_frame_by_it (uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t t_out)
Receives an frame of data in non blocking mode. More...
ald_status_t | ald_uart_send_by_dma (uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
Sends an amount of data in non blocking mode. More...
ald_status_t | ald_uart_recv_by_dma (uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
Receives an amount of data in non blocking mode. More...
ald_status_t | ald_uart_dma_pause (uart_handle_t *hperh)
Pauses the DMA Transfer. More...
ald_status_t | ald_uart_dma_resume (uart_handle_t *hperh)
Resumes the DMA Transfer. More...
ald_status_t | ald_uart_dma_stop (uart_handle_t *hperh)
Stops the DMA Transfer. More...
void | ald_uart_irq_handler (uart_handle_t *hperh)
This function handles UART interrupt request. More...
void | ald_uart_irq_handler_fast (uart_handle_t *hperh)
This function handles UART interrupt request. More...

Detailed Description

UART Transmit and Receive functions.

==============================================================================
                    # IO operation functions #
==============================================================================
[..]
  This subsection provides a set of functions allowing to manage the UART data transfers.

  (#) There are two modes of transfer:
     (++) Blocking mode: The communication is performed in polling mode.
          The Status of all data processing is returned by the same function
          after finishing transfer.
     (++) Non blocking mode: The communication is performed using Interrupts
          or DMA, these APIs return the Status.
          The end of the data processing will be indicated through the
          dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
          using DMA mode.
          The hperh->tx_cplt_cbk(), hperh->rx_cplt_cbk() user callbacks
          will be executed respectively at the end of the transmit or receive process.
          The hperh->error_cbk() user callback will be executed when
          a communication error is detected.

  (#) Blocking mode APIs are:
      (++) ald_uart_send()
      (++) ald_uart_recv()

  (#) Non Blocking mode APIs with Interrupt are:
      (++) ald_uart_send_by_it()
      (++) ald_uart_recv_by_it()
      (++) ald_uart_irq_handler()

  (#) Non Blocking mode functions with DMA are:
      (++) ald_uart_send_by_dma()
      (++) ald_uart_recv_by_dma()
      (++) ald_uart_dma_pause()
      (++) ald_uart_dma_resume()
      (++) ald_uart_dma_stop()

  (#) A set of transfer complete callbacks are provided in non blocking mode:
      (++) hperh->tx_cplt_cbk()
      (++) hperh->rx_cplt_cbk()
      (++) hperh->error_cbk()

Function Documentation

◆ ald_uart_dma_pause()

ald_status_t ald_uart_dma_pause ( uart_handle_t * hperh )

Pauses the DMA Transfer.

Parameters
hperh Pointer to a uart_handle_t structure.
Return values
Status,see ald_status_t.

Definition at line 920 of file ald_uart.c.

921 {
922 assert_param(IS_UART_ALL(hperh->perh));
923
924 ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, DISABLE);
925 ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, DISABLE);
926 return OK;
927 }
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
DISABLE
Definition: type.h:48
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
UART_DMA_REQ_TX
Definition: ald_uart.h:278
UART_DMA_REQ_RX
Definition: ald_uart.h:279
ald_uart_dma_req_config
void ald_uart_dma_req_config(uart_handle_t *hperh, uart_dma_req_t req, type_func_t state)
Configure UART DMA request.
Definition: ald_uart.c:1150

◆ ald_uart_dma_resume()

ald_status_t ald_uart_dma_resume ( uart_handle_t * hperh )

Resumes the DMA Transfer.

Parameters
hperh Pointer to a uart_handle_t structure.
Return values
Status,see ald_status_t.

Definition at line 934 of file ald_uart.c.

935 {
936 assert_param(IS_UART_ALL(hperh->perh));
937
938 ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, ENABLE);
939 ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, ENABLE);
940 return OK;
941 }
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
UART_DMA_REQ_TX
Definition: ald_uart.h:278
UART_DMA_REQ_RX
Definition: ald_uart.h:279
ald_uart_dma_req_config
void ald_uart_dma_req_config(uart_handle_t *hperh, uart_dma_req_t req, type_func_t state)
Configure UART DMA request.
Definition: ald_uart.c:1150

◆ ald_uart_dma_stop()

ald_status_t ald_uart_dma_stop ( uart_handle_t * hperh )

Stops the DMA Transfer.

Parameters
hperh Pointer to a uart_handle_t structure.
Return values
Status,see ald_status_t.

Definition at line 948 of file ald_uart.c.

949 {
950 assert_param(IS_UART_ALL(hperh->perh));
951
952 ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, DISABLE);
953 ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, DISABLE);
954 hperh->state = UART_STATE_READY;
955 return OK;
956 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
DISABLE
Definition: type.h:48
UART_STATE_READY
Definition: ald_uart.h:134
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
UART_DMA_REQ_TX
Definition: ald_uart.h:278
UART_DMA_REQ_RX
Definition: ald_uart.h:279
ald_uart_dma_req_config
void ald_uart_dma_req_config(uart_handle_t *hperh, uart_dma_req_t req, type_func_t state)
Configure UART DMA request.
Definition: ald_uart.c:1150

◆ ald_uart_irq_handler()

void ald_uart_irq_handler ( uart_handle_t * hperh )

This function handles UART interrupt request.

Parameters
hperh Pointer to a uart_handle_t structure.
Return values
None

Definition at line 964 of file ald_uart.c.

965 {
966 assert_param(IS_UART_ALL(hperh->perh));
967
968 /* Handle parity error */
969 if (((ald_uart_get_status(hperh, UART_STATUS_PERR)) != RESET) && \
970 (ald_uart_get_state(hperh)) == UART_STATE_RX_MASK)
971 hperh->err_code |= UART_ERROR_PE;
972
973 /* Handle frame error */
974 if (((ald_uart_get_status(hperh, UART_STATUS_FERR)) != RESET) && \
975 (ald_uart_get_state(hperh)) == UART_STATE_RX_MASK)
976 hperh->err_code |= UART_ERROR_FE;
977
978 /* Handle rx overflow error */
979 if (((ald_uart_get_status(hperh, UART_STATUS_RFOERR)) != RESET) && \
980 (ald_uart_get_state(hperh)) == UART_STATE_RX_MASK)
981 hperh->err_code |= UART_ERROR_ORE;
982
983 /* Handle tx overflow error */
984 if (((ald_uart_get_status(hperh, UART_STATUS_TFOERR)) != RESET) && \
985 (ald_uart_get_state(hperh)) == UART_STATE_TX_MASK)
986 hperh->err_code |= UART_ERROR_ORE;
987
988 /* Receive */
989 if ((ald_uart_get_mask_flag_status(hperh, UART_IF_RFTH)) != RESET) {
990 ald_uart_clear_flag_status(hperh, UART_IF_RFTH);
991 __uart_recv_by_it(hperh);
992 }
993
994 /* Transmit */
995 if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TFTH)) != RESET) {
996 ald_uart_clear_flag_status(hperh, UART_IF_TFTH);
997 __uart_send_by_it(hperh);
998 }
999
1000 /* End Transmit */
1001 if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TFEMPTY)) != RESET) {
1002 ald_uart_clear_flag_status(hperh, UART_IF_TFEMPTY);
1003 __uart_end_send_by_it(hperh);
1004 }
1005
1006 /* Receive frame timeout*/
1007 if ((ald_uart_get_mask_flag_status(hperh, UART_IF_RXTO)) != RESET) {
1008 ald_uart_clear_flag_status(hperh, UART_IF_RXTO);
1009
1010 ald_uart_interrupt_config(hperh, UART_IT_RXTO, DISABLE);
1011 CLEAR_BIT(hperh->state, UART_STATE_RX_MASK);
1012
1013 if (hperh->rx_cplt_cbk)
1014 hperh->rx_cplt_cbk(hperh);
1015 }
1016
1017 /* Handle error state */
1018 if (hperh->err_code != UART_ERROR_NONE) {
1019 hperh->state = UART_STATE_READY;
1020
1021 if (hperh->error_cbk)
1022 hperh->error_cbk(hperh);
1023 }
1024 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
UART_STATUS_TFOERR
Definition: ald_uart.h:300
ald_uart_clear_flag_status
void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag)
Clear the UART interrupt flag.
Definition: ald_uart.c:1403
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
uart_handle_s::err_code
uart_error_t err_code
Definition: ald_uart.h:185
UART_ERROR_PE
Definition: ald_uart.h:148
ald_uart_interrupt_config
void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state)
Enable/disable the specified UART interrupts.
Definition: ald_uart.c:1126
DISABLE
Definition: type.h:48
UART_STATE_RX_MASK
#define UART_STATE_RX_MASK
Definition: ald_uart.h:455
UART_STATE_READY
Definition: ald_uart.h:134
UART_IF_TFTH
Definition: ald_uart.h:344
UART_ERROR_FE
Definition: ald_uart.h:150
ald_uart_get_status
flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status)
Get the status of UART_SR register.
Definition: ald_uart.c:1344
UART_IF_RFTH
Definition: ald_uart.h:339
uart_handle_s::rx_cplt_cbk
void(* rx_cplt_cbk)(struct uart_handle_s *arg)
Definition: ald_uart.h:188
RESET
Definition: type.h:38
ald_uart_get_mask_flag_status
flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag)
Get the status of interrupt flag and interupt source.
Definition: ald_uart.c:1385
UART_IF_TFEMPTY
Definition: ald_uart.h:345
UART_ERROR_NONE
Definition: ald_uart.h:147
UART_STATE_TX_MASK
#define UART_STATE_TX_MASK
Definition: ald_uart.h:454
UART_IT_RXTO
Definition: ald_uart.h:311
UART_STATUS_FERR
Definition: ald_uart.h:287
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
UART_IF_RXTO
Definition: ald_uart.h:334
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
UART_ERROR_ORE
Definition: ald_uart.h:151
ald_uart_get_state
uart_state_t ald_uart_get_state(uart_handle_t *hperh)
Returns the UART state.
Definition: ald_uart.c:1438
UART_STATUS_RFOERR
Definition: ald_uart.h:294
uart_handle_s::error_cbk
void(* error_cbk)(struct uart_handle_s *arg)
Definition: ald_uart.h:189
__uart_recv_by_it
static ald_status_t __uart_recv_by_it(uart_handle_t *hperh)
Receives an amount of data in non blocking mode.
Definition: ald_uart.c:241
__uart_send_by_it
static ald_status_t __uart_send_by_it(uart_handle_t *hperh)
Sends an amount of data in non blocking mode.
Definition: ald_uart.c:200
__uart_end_send_by_it
static ald_status_t __uart_end_send_by_it(uart_handle_t *hperh)
Wraps up transmission in non blocking mode.
Definition: ald_uart.c:221
UART_STATUS_PERR
Definition: ald_uart.h:286

◆ ald_uart_irq_handler_fast()

void ald_uart_irq_handler_fast ( uart_handle_t * hperh )

This function handles UART interrupt request.

Parameters
hperh Pointer to a uart_handle_t structure.
Return values
None

Definition at line 1031 of file ald_uart.c.

1032 {
1033 volatile uint32_t tmp = hperh->perh->IFM;
1034
1035 /* Transmit */
1036 if (tmp & 0x8000) {
1037 hperh->perh->ICR = 0x8000;
1038 hperh->perh->TXBUF = *hperh->tx_buf++;
1039 ++hperh->tx_count;
1040
1041 if (hperh->tx_count >= hperh->tx_size) {
1042 hperh->perh->IDR = 0x8000;
1043 CLEAR_BIT(hperh->state, UART_STATE_TX_MASK);
1044
1045 if (hperh->tx_cplt_cbk)
1046 hperh->tx_cplt_cbk(hperh);
1047 }
1048 }
1049 /* End Transmit */
1050 if (tmp & 0x10000) {
1051 hperh->perh->ICR = 0x10000;
1052 hperh->perh->IDR = 0x10000;
1053 CLEAR_BIT(hperh->state, UART_STATE_TX_MASK);
1054
1055 if (hperh->tx_cplt_cbk)
1056 hperh->tx_cplt_cbk(hperh);
1057 }
1058
1059 /* Receive*/
1060 if (tmp & 0x200) {
1061 hperh->perh->ICR = 0x200;
1062 *hperh->rx_buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF);
1063 ++hperh->rx_count;
1064
1065 if (hperh->rx_count >= hperh->rx_size) {
1066 hperh->perh->IDR = 0x200;
1067 CLEAR_BIT(hperh->state, UART_STATE_RX_MASK);
1068
1069 if (hperh->rx_cplt_cbk)
1070 hperh->rx_cplt_cbk(hperh);
1071 }
1072 }
1073 /* Receive frame */
1074 if (tmp & 0x10) {
1075 hperh->perh->ICR = 0x10;
1076 hperh->perh->IDR = 0x10;
1077 CLEAR_BIT(hperh->state, UART_STATE_RX_MASK);
1078
1079 if (hperh->rx_cplt_cbk)
1080 hperh->rx_cplt_cbk(hperh);
1081 }
1082
1083 return;
1084 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
uart_handle_s::tx_cplt_cbk
void(* tx_cplt_cbk)(struct uart_handle_s *arg)
Definition: ald_uart.h:187
UART_STATE_RX_MASK
#define UART_STATE_RX_MASK
Definition: ald_uart.h:455
uart_handle_s::rx_cplt_cbk
void(* rx_cplt_cbk)(struct uart_handle_s *arg)
Definition: ald_uart.h:188
uart_handle_s::tx_buf
uint8_t * tx_buf
Definition: ald_uart.h:173
UART_STATE_TX_MASK
#define UART_STATE_TX_MASK
Definition: ald_uart.h:454
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
uart_handle_s::rx_size
uint16_t rx_size
Definition: ald_uart.h:177
uart_handle_s::rx_count
uint16_t rx_count
Definition: ald_uart.h:178
uart_handle_s::rx_buf
uint8_t * rx_buf
Definition: ald_uart.h:176
uart_handle_s::tx_size
uint16_t tx_size
Definition: ald_uart.h:174
uart_handle_s::tx_count
uint16_t tx_count
Definition: ald_uart.h:175

◆ ald_uart_recv()

ald_status_t ald_uart_recv | ( | uart_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint16_t | size,
 |  | uint32_t | timeout
 | ) |  |

Receives an amount of data in blocking mode.

Parameters
hperh | Pointer to a uart_handle_t structure.
buf | Pointer to data buffer
size | Amount of data to be received
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 537 of file ald_uart.c.

538 {
539 assert_param(IS_UART_ALL(hperh->perh));
540
541 if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX))
542 return BUSY;
543
544 if ((buf == NULL) || (size == 0))
545 return ERROR;
546
547 __LOCK(hperh);
548 hperh->err_code = UART_ERROR_NONE;
549 SET_BIT(hperh->state, UART_STATE_RX_MASK);
550
551 hperh->rx_size = size;
552 hperh->rx_count = 0;
553 SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK);
554
555 while (size-- > 0) {
556 if (uart_wait_flag(hperh, UART_STATUS_RFTH, SET, timeout) != OK) {
557 __UNLOCK(hperh);
558 hperh->state = UART_STATE_READY;
559 return TIMEOUT;
560 }
561
562 *buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF);
563 hperh->rx_count++;
564 }
565
566 CLEAR_BIT(hperh->state, UART_STATE_RX_MASK);
567 __UNLOCK(hperh);
568
569 return OK;
570
571 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
uart_handle_s::err_code
uart_error_t err_code
Definition: ald_uart.h:185
BUSY
Definition: utils.h:57
SET
Definition: type.h:39
UART_STATE_BUSY_TX
Definition: ald_uart.h:136
UART_STATE_RX_MASK
#define UART_STATE_RX_MASK
Definition: ald_uart.h:455
UART_STATE_READY
Definition: ald_uart.h:134
UART_ERROR_NONE
Definition: ald_uart.h:147
uart_wait_flag
static ald_status_t uart_wait_flag(uart_handle_t *hperh, uart_status_t flag, flag_status_t status, uint32_t timeout)
This function handles uart Communication Timeout.
Definition: ald_uart.c:177
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
uart_handle_s::rx_size
uint16_t rx_size
Definition: ald_uart.h:177
TIMEOUT
Definition: utils.h:58
UART_STATUS_RFTH
Definition: ald_uart.h:291
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
uart_handle_s::rx_count
uint16_t rx_count
Definition: ald_uart.h:178
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56

◆ ald_uart_recv_by_dma()

ald_status_t ald_uart_recv_by_dma | ( | uart_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint16_t | size,
 |  | uint8_t | channel
 | ) |  |

Receives an amount of data in non blocking mode.

Parameters
hperh | Pointer to a uart_handle_t structure.
buf | Pointer to data buffer
size | Amount of data to be received
channel | DMA channel as UART receive
Return values
Status,see ald_status_t.

Definition at line 846 of file ald_uart.c.

847 {
848 assert_param(IS_UART_ALL(hperh->perh));
849
850 if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX))
851 return BUSY;
852
853 if ((buf == NULL) || (size == 0))
854 return ERROR;
855
856 __LOCK(hperh);
857
858 hperh->rx_buf = buf;
859 hperh->rx_size = size;
860 hperh->err_code = UART_ERROR_NONE;
861 SET_BIT(hperh->state, UART_STATE_RX_MASK);
862
863 if (hperh->hdmarx.perh == NULL)
864 hperh->hdmarx.perh = DMA0;
865
866 /* Set the dma parameters */
867 hperh->hdmarx.cplt_cbk = uart_dma_recv_cplt;
868 hperh->hdmarx.cplt_arg = (void *)hperh;
869 hperh->hdmarx.err_cbk = uart_dma_error;
870 hperh->hdmarx.err_arg = (void *)hperh;
871
872 ald_dma_config_struct(&hperh->hdmarx.config);
873 hperh->hdmarx.config.src = (void *)&hperh->perh->RXBUF;
874 hperh->hdmarx.config.dst = (void *)buf;
875 hperh->hdmarx.config.size = size;
876 hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE;
877 hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE;
878 if ((hperh->perh == UART4) || (hperh->perh == UART5)) {
879 hperh->hdmarx.config.msigsel = DMA_MSIGSEL_UART45_RNR;
880 } else {
881 hperh->hdmarx.config.msigsel = DMA_MSIGSEL_UART_RNR;
882 }
883
884 hperh->hdmatx.config.burst = ENABLE;
885 hperh->hdmarx.config.channel = channel;
886
887 if (hperh->init.mode == UART_MODE_RS485) {
888 hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD;
889 hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD;
890 }
891
892 if (hperh->perh == UART0)
893 hperh->hdmarx.config.msel = DMA_MSEL_UART0;
894 else if (hperh->perh == UART1)
895 hperh->hdmarx.config.msel = DMA_MSEL_UART1;
896 else if (hperh->perh == UART2)
897 hperh->hdmarx.config.msel = DMA_MSEL_UART2;
898 else if (hperh->perh == UART3)
899 hperh->hdmarx.config.msel = DMA_MSEL_UART3;
900 else if (hperh->perh == UART4)
901 hperh->hdmatx.config.msel = DMA_MSEL_UART4;
902 else if (hperh->perh == UART5)
903 hperh->hdmatx.config.msel = DMA_MSEL_UART5;
904 else
905 ;
906
907 __UNLOCK(hperh);
908 ald_dma_config_basic(&hperh->hdmarx);
909 SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK);
910 ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, ENABLE);
911
912 return OK;
913 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
DMA_MSEL_UART4
Definition: ald_dma.h:88
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
DMA_MSEL_UART5
Definition: ald_dma.h:89
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
assert_param
#define assert_param(x)
Definition: type.h:88
uart_handle_s::err_code
uart_error_t err_code
Definition: ald_uart.h:185
BUSY
Definition: utils.h:57
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
DMA_MSIGSEL_UART45_RNR
Definition: ald_dma.h:139
UART_STATE_BUSY_TX
Definition: ald_uart.h:136
UART_STATE_RX_MASK
#define UART_STATE_RX_MASK
Definition: ald_uart.h:455
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
UART_STATE_READY
Definition: ald_uart.h:134
DMA_MSEL_UART1
Definition: ald_dma.h:85
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
DMA_MSEL_UART0
Definition: ald_dma.h:84
dma_config_t::src
void * src
Definition: ald_dma.h:278
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
UART_ERROR_NONE
Definition: ald_uart.h:147
uart_handle_s::hdmatx
dma_handle_t hdmatx
Definition: ald_uart.h:180
uart_handle_s::init
uart_init_t init
Definition: ald_uart.h:172
UART_MODE_RS485
Definition: ald_uart.h:116
uart_init_t::mode
uart_mode_t mode
Definition: ald_uart.h:163
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
DMA_MSIGSEL_UART_RNR
Definition: ald_dma.h:138
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
uart_handle_s::rx_size
uint16_t rx_size
Definition: ald_uart.h:177
DMA_DATA_INC_BYTE
Definition: ald_dma.h:217
uart_dma_error
static void uart_dma_error(void *arg)
DMA uart communication error callback.
Definition: ald_uart.c:151
DMA_MSEL_UART3
Definition: ald_dma.h:87
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
UART_DMA_REQ_RX
Definition: ald_uart.h:279
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
ald_uart_dma_req_config
void ald_uart_dma_req_config(uart_handle_t *hperh, uart_dma_req_t req, type_func_t state)
Configure UART DMA request.
Definition: ald_uart.c:1150
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
uart_dma_recv_cplt
static void uart_dma_recv_cplt(void *arg)
DMA uart receive process complete callback.
Definition: ald_uart.c:131
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
uart_handle_s::rx_buf
uint8_t * rx_buf
Definition: ald_uart.h:176
uart_handle_s::hdmarx
dma_handle_t hdmarx
Definition: ald_uart.h:181
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
__LOCK
#define __LOCK(x)
Definition: utils.h:92
DMA_MSEL_UART2
Definition: ald_dma.h:86
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294

◆ ald_uart_recv_by_it()

ald_status_t ald_uart_recv_by_it | ( | uart_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint16_t | size
 | ) |  |

Receives an amount of data in non blocking mode.

Parameters
hperh | Pointer to a uart_handle_t structure.
buf | Pointer to data buffer
size | Amount of data to be received
Return values
Status,see ald_status_t.

Definition at line 697 of file ald_uart.c.

698 {
699 assert_param(IS_UART_ALL(hperh->perh));
700
701 if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX))
702 return BUSY;
703
704 if ((buf == NULL ) || (size == 0))
705 return ERROR;
706
707 __LOCK(hperh);
708 hperh->rx_buf = buf;
709 hperh->rx_size = size;
710 hperh->rx_count = 0;
711 hperh->err_code = UART_ERROR_NONE;
712 SET_BIT(hperh->state, UART_STATE_RX_MASK);
713
714 __UNLOCK(hperh);
715 SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK);
716 SET_BIT(hperh->perh->ICR, UART_ICR_RFTH_MSK);
717 ald_uart_interrupt_config(hperh, UART_IT_RFTH, ENABLE);
718 return OK;
719 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
uart_handle_s::err_code
uart_error_t err_code
Definition: ald_uart.h:185
BUSY
Definition: utils.h:57
UART_STATE_BUSY_TX
Definition: ald_uart.h:136
ald_uart_interrupt_config
void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state)
Enable/disable the specified UART interrupts.
Definition: ald_uart.c:1126
UART_STATE_RX_MASK
#define UART_STATE_RX_MASK
Definition: ald_uart.h:455
UART_STATE_READY
Definition: ald_uart.h:134
UART_ERROR_NONE
Definition: ald_uart.h:147
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
uart_handle_s::rx_size
uint16_t rx_size
Definition: ald_uart.h:177
UART_IT_RFTH
Definition: ald_uart.h:316
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
uart_handle_s::rx_count
uint16_t rx_count
Definition: ald_uart.h:178
uart_handle_s::rx_buf
uint8_t * rx_buf
Definition: ald_uart.h:176
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56

◆ ald_uart_recv_frame_by_it()

ald_status_t ald_uart_recv_frame_by_it | ( | uart_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint16_t | size,
 |  | uint32_t | t_out
 | ) |  |

Receives an frame of data in non blocking mode.

Parameters
hperh | Pointer to a uart_handle_t structure.
buf | Pointer to data buffer
size | Max length of frame.
t_out | Timeout duration.
Return values
Status,see ald_status_t.

Definition at line 730 of file ald_uart.c.

731 {
732 assert_param(IS_UART_ALL(hperh->perh));
733
734 if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX))
735 return BUSY;
736
737 if ((buf == NULL ) || (t_out == 0) || (t_out > 0xFFFFFF) || (size == 0))
738 return ERROR;
739
740 __LOCK(hperh);
741 hperh->rx_buf = buf;
742 hperh->rx_size = size;
743 hperh->rx_count = 0;
744 hperh->err_code = UART_ERROR_NONE;
745 SET_BIT(hperh->state, UART_STATE_RX_MASK);
746
747 __UNLOCK(hperh);
748 SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK);
749 SET_BIT(hperh->perh->ICR, UART_ICR_RFTH_MSK);
750 SET_BIT(hperh->perh->RTOR, UART_RTOR_RTOEN_MSK);
751 MODIFY_REG(hperh->perh->RTOR, UART_RTOR_RTO_MSK, t_out << UART_RTOR_RTO_POSS);
752 ald_uart_interrupt_config(hperh, UART_IT_RFTH, ENABLE);
753 ald_uart_interrupt_config(hperh, UART_IT_RXTO, ENABLE);
754 return OK;
755 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
uart_handle_s::err_code
uart_error_t err_code
Definition: ald_uart.h:185
BUSY
Definition: utils.h:57
UART_STATE_BUSY_TX
Definition: ald_uart.h:136
ald_uart_interrupt_config
void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state)
Enable/disable the specified UART interrupts.
Definition: ald_uart.c:1126
UART_STATE_RX_MASK
#define UART_STATE_RX_MASK
Definition: ald_uart.h:455
UART_STATE_READY
Definition: ald_uart.h:134
UART_ERROR_NONE
Definition: ald_uart.h:147
UART_IT_RXTO
Definition: ald_uart.h:311
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
uart_handle_s::rx_size
uint16_t rx_size
Definition: ald_uart.h:177
UART_IT_RFTH
Definition: ald_uart.h:316
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
uart_handle_s::rx_count
uint16_t rx_count
Definition: ald_uart.h:178
uart_handle_s::rx_buf
uint8_t * rx_buf
Definition: ald_uart.h:176
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56

◆ ald_uart_recv_n_lock()

ald_status_t ald_uart_recv_n_lock | ( | uart_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint16_t | size,
 |  | uint32_t | timeout
 | ) |  |

Receives an amount of data in blocking mode. Don't care about device lock. This is for RTOS.

Parameters
hperh | Pointer to a uart_handle_t structure.
buf | Pointer to data buffer
size | Amount of data to be received
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 626 of file ald_uart.c.

627 {
628 assert_param(IS_UART_ALL(hperh->perh));
629
630 if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX))
631 return BUSY;
632 if ((buf == NULL) || (size == 0))
633 return ERROR;
634
635 hperh->err_code = UART_ERROR_NONE;
636 SET_BIT(hperh->state, UART_STATE_RX_MASK);
637
638 hperh->rx_size = size;
639 hperh->rx_count = 0;
640 SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK);
641
642 while (size-- > 0) {
643 if (uart_wait_flag(hperh, UART_STATUS_RFTH, SET, timeout) != OK) {
644 hperh->state = UART_STATE_READY;
645 return TIMEOUT;
646 }
647
648 *buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF);
649 hperh->rx_count++;
650 }
651
652 CLEAR_BIT(hperh->state, UART_STATE_RX_MASK);
653 return OK;
654
655 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
OK
Definition: utils.h:55
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
uart_handle_s::err_code
uart_error_t err_code
Definition: ald_uart.h:185
BUSY
Definition: utils.h:57
SET
Definition: type.h:39
UART_STATE_BUSY_TX
Definition: ald_uart.h:136
UART_STATE_RX_MASK
#define UART_STATE_RX_MASK
Definition: ald_uart.h:455
UART_STATE_READY
Definition: ald_uart.h:134
UART_ERROR_NONE
Definition: ald_uart.h:147
uart_wait_flag
static ald_status_t uart_wait_flag(uart_handle_t *hperh, uart_status_t flag, flag_status_t status, uint32_t timeout)
This function handles uart Communication Timeout.
Definition: ald_uart.c:177
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
uart_handle_s::rx_size
uint16_t rx_size
Definition: ald_uart.h:177
TIMEOUT
Definition: utils.h:58
UART_STATUS_RFTH
Definition: ald_uart.h:291
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
uart_handle_s::rx_count
uint16_t rx_count
Definition: ald_uart.h:178
ERROR
Definition: utils.h:56

◆ ald_uart_send()

ald_status_t ald_uart_send | ( | uart_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint16_t | size,
 |  | uint32_t | timeout
 | ) |  |

Sends an amount of data in blocking mode.

Parameters
hperh | Pointer to a uart_handle_t structure.
buf | Pointer to data buffer
size | Amount of data to be sent
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 488 of file ald_uart.c.

489 {
490 assert_param(IS_UART_ALL(hperh->perh));
491
492 if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX))
493 return BUSY;
494
495 if ((buf == NULL) || (size == 0))
496 return ERROR;
497
498 __LOCK(hperh);
499 hperh->err_code = UART_ERROR_NONE;
500 SET_BIT(hperh->state, UART_STATE_TX_MASK);
501
502 hperh->tx_size = size;
503 hperh->tx_count = 0;
504 SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK);
505
506 while (size-- > 0) {
507 if (uart_wait_flag(hperh, UART_STATUS_TFTH, SET, timeout) != OK) {
508 __UNLOCK(hperh);
509 hperh->state = UART_STATE_READY;
510 return TIMEOUT;
511 }
512
513 hperh->perh->TXBUF = (*buf++ & 0xFF);
514 hperh->tx_count++;
515 }
516
517 if (uart_wait_flag(hperh, UART_STATUS_TSBUSY, RESET, timeout) != OK) {
518 __UNLOCK(hperh);
519 hperh->state = UART_STATE_READY;
520 return TIMEOUT;
521 }
522
523 CLEAR_BIT(hperh->state, UART_STATE_TX_MASK);
524 __UNLOCK(hperh);
525
526 return OK;
527 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
uart_handle_s::err_code
uart_error_t err_code
Definition: ald_uart.h:185
BUSY
Definition: utils.h:57
SET
Definition: type.h:39
UART_STATE_READY
Definition: ald_uart.h:134
UART_STATUS_TFTH
Definition: ald_uart.h:297
RESET
Definition: type.h:38
UART_STATUS_TSBUSY
Definition: ald_uart.h:296
UART_ERROR_NONE
Definition: ald_uart.h:147
UART_STATE_TX_MASK
#define UART_STATE_TX_MASK
Definition: ald_uart.h:454
uart_wait_flag
static ald_status_t uart_wait_flag(uart_handle_t *hperh, uart_status_t flag, flag_status_t status, uint32_t timeout)
This function handles uart Communication Timeout.
Definition: ald_uart.c:177
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
TIMEOUT
Definition: utils.h:58
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
uart_handle_s::tx_size
uint16_t tx_size
Definition: ald_uart.h:174
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
uart_handle_s::tx_count
uint16_t tx_count
Definition: ald_uart.h:175
UART_STATE_BUSY_RX
Definition: ald_uart.h:137

◆ ald_uart_send_by_dma()

ald_status_t ald_uart_send_by_dma | ( | uart_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint16_t | size,
 |  | uint8_t | channel
 | ) |  |

Sends an amount of data in non blocking mode.

Parameters
hperh | Pointer to a uart_handle_t structure.
buf | Pointer to data buffer
size | Amount of data to be sent
channel | DMA channel as UART transmit
Return values
Status,see ald_status_t.

Definition at line 766 of file ald_uart.c.

767 {
768 assert_param(IS_UART_ALL(hperh->perh));
769
770 if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX))
771 return BUSY;
772
773 if ((buf == NULL ) || (size == 0))
774 return ERROR;
775
776 __LOCK(hperh);
777
778 hperh->tx_buf = buf;
779 hperh->tx_size = size;
780 hperh->tx_count = 0;
781 hperh->err_code = UART_ERROR_NONE;
782 SET_BIT(hperh->state, UART_STATE_TX_MASK);
783
784 if (hperh->hdmatx.perh == NULL)
785 hperh->hdmatx.perh = DMA0;
786
787 /* Set the dma parameters */
788 hperh->hdmatx.cplt_cbk = uart_dma_send_cplt;
789 hperh->hdmatx.cplt_arg = (void *)hperh;
790 hperh->hdmatx.err_cbk = uart_dma_error;
791 hperh->hdmatx.err_arg = (void *)hperh;
792
793 ald_dma_config_struct(&hperh->hdmatx.config);
794 hperh->hdmatx.config.src = (void *)buf;
795 hperh->hdmatx.config.dst = (void *)&hperh->perh->TXBUF;
796 hperh->hdmatx.config.size = size;
797 hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE;
798 hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
799 if ((hperh->perh == UART4) || (hperh->perh == UART5)) {
800 hperh->hdmatx.config.msigsel = DMA_MSIGSEL_UART45_TXEMPTY;
801 } else {
802 hperh->hdmatx.config.msigsel = DMA_MSIGSEL_UART_TXEMPTY;
803 }
804 hperh->hdmatx.config.burst = ENABLE;
805 hperh->hdmatx.config.channel = channel;
806
807 if (hperh->init.mode == UART_MODE_RS485) {
808 hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD;
809 hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD;
810 }
811
812 if (hperh->perh == UART0)
813 hperh->hdmatx.config.msel = DMA_MSEL_UART0;
814 else if (hperh->perh == UART1)
815 hperh->hdmatx.config.msel = DMA_MSEL_UART1;
816 else if (hperh->perh == UART2)
817 hperh->hdmatx.config.msel = DMA_MSEL_UART2;
818 else if (hperh->perh == UART3)
819 hperh->hdmatx.config.msel = DMA_MSEL_UART3;
820 else if (hperh->perh == UART4)
821 hperh->hdmatx.config.msel = DMA_MSEL_UART4;
822 else if (hperh->perh == UART5)
823 hperh->hdmatx.config.msel = DMA_MSEL_UART5;
824 else
825 ; /* do nothing */
826
827 ald_dma_config_basic(&hperh->hdmatx);
828
829 __UNLOCK(hperh);
830 SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK);
831 ald_uart_clear_flag_status(hperh, UART_IF_TBC);
832 ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, ENABLE);
833
834
835 return OK;
836 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
DMA_MSEL_UART4
Definition: ald_dma.h:88
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
DMA_MSEL_UART5
Definition: ald_dma.h:89
ald_uart_clear_flag_status
void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag)
Clear the UART interrupt flag.
Definition: ald_uart.c:1403
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
assert_param
#define assert_param(x)
Definition: type.h:88
uart_handle_s::err_code
uart_error_t err_code
Definition: ald_uart.h:185
BUSY
Definition: utils.h:57
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
UART_STATE_READY
Definition: ald_uart.h:134
DMA_MSEL_UART1
Definition: ald_dma.h:85
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
DMA_MSEL_UART0
Definition: ald_dma.h:84
dma_config_t::src
void * src
Definition: ald_dma.h:278
DMA_MSIGSEL_UART_TXEMPTY
Definition: ald_dma.h:137
uart_dma_send_cplt
static void uart_dma_send_cplt(void *arg)
DMA uart transmit process complete callback.
Definition: ald_uart.c:113
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
uart_handle_s::tx_buf
uint8_t * tx_buf
Definition: ald_uart.h:173
UART_ERROR_NONE
Definition: ald_uart.h:147
uart_handle_s::hdmatx
dma_handle_t hdmatx
Definition: ald_uart.h:180
UART_STATE_TX_MASK
#define UART_STATE_TX_MASK
Definition: ald_uart.h:454
uart_handle_s::init
uart_init_t init
Definition: ald_uart.h:172
UART_MODE_RS485
Definition: ald_uart.h:116
uart_init_t::mode
uart_mode_t mode
Definition: ald_uart.h:163
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
DMA_MSIGSEL_UART45_TXEMPTY
Definition: ald_dma.h:140
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
DMA_DATA_INC_BYTE
Definition: ald_dma.h:217
uart_dma_error
static void uart_dma_error(void *arg)
DMA uart communication error callback.
Definition: ald_uart.c:151
UART_DMA_REQ_TX
Definition: ald_uart.h:278
DMA_MSEL_UART3
Definition: ald_dma.h:87
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
UART_IF_TBC
Definition: ald_uart.h:343
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
ald_uart_dma_req_config
void ald_uart_dma_req_config(uart_handle_t *hperh, uart_dma_req_t req, type_func_t state)
Configure UART DMA request.
Definition: ald_uart.c:1150
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
uart_handle_s::tx_size
uint16_t tx_size
Definition: ald_uart.h:174
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
__LOCK
#define __LOCK(x)
Definition: utils.h:92
DMA_MSEL_UART2
Definition: ald_dma.h:86
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
uart_handle_s::tx_count
uint16_t tx_count
Definition: ald_uart.h:175
UART_STATE_BUSY_RX
Definition: ald_uart.h:137

◆ ald_uart_send_by_it()

ald_status_t ald_uart_send_by_it | ( | uart_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint16_t | size
 | ) |  |

Sends an amount of data in non blocking mode.

Parameters
hperh | Pointer to a uart_handle_t structure.
buf | Pointer to data buffer
size | Amount of data to be sent
Return values
Status,see ald_status_t.

Definition at line 664 of file ald_uart.c.

665 {
666 assert_param(IS_UART_ALL(hperh->perh));
667
668 if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX))
669 return BUSY;
670
671 if ((buf == NULL ) || (size == 0))
672 return ERROR;
673
674 __LOCK(hperh);
675
676 hperh->tx_buf = buf;
677 hperh->tx_size = size;
678 hperh->tx_count = 0;
679 hperh->err_code = UART_ERROR_NONE;
680 SET_BIT(hperh->state, UART_STATE_TX_MASK);
681
682 __UNLOCK(hperh);
683 SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK);
684 SET_BIT(hperh->perh->ICR, UART_ICR_TFTH_MSK);
685 ald_uart_interrupt_config(hperh, UART_IT_TFTH, ENABLE);
686
687 return OK;
688 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
assert_param
#define assert_param(x)
Definition: type.h:88
uart_handle_s::err_code
uart_error_t err_code
Definition: ald_uart.h:185
BUSY
Definition: utils.h:57
ald_uart_interrupt_config
void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state)
Enable/disable the specified UART interrupts.
Definition: ald_uart.c:1126
UART_STATE_READY
Definition: ald_uart.h:134
uart_handle_s::tx_buf
uint8_t * tx_buf
Definition: ald_uart.h:173
UART_ERROR_NONE
Definition: ald_uart.h:147
UART_STATE_TX_MASK
#define UART_STATE_TX_MASK
Definition: ald_uart.h:454
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
UART_IT_TFTH
Definition: ald_uart.h:321
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
uart_handle_s::tx_size
uint16_t tx_size
Definition: ald_uart.h:174
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
uart_handle_s::tx_count
uint16_t tx_count
Definition: ald_uart.h:175
UART_STATE_BUSY_RX
Definition: ald_uart.h:137

◆ ald_uart_send_n_lock()

ald_status_t ald_uart_send_n_lock | ( | uart_handle_t * | hperh,
 |  | uint8_t * | buf,
 |  | uint16_t | size,
 |  | uint32_t | timeout
 | ) |  |

Sends an amount of data in blocking mode. Don't care about device lock. This is for RTOS.

Parameters
hperh | Pointer to a uart_handle_t structure.
buf | Pointer to data buffer
size | Amount of data to be sent
timeout | Timeout duration
Return values
Status,see ald_status_t.

Definition at line 582 of file ald_uart.c.

583 {
584 assert_param(IS_UART_ALL(hperh->perh));
585
586 if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX))
587 return BUSY;
588 if ((buf == NULL) || (size == 0))
589 return ERROR;
590
591 hperh->err_code = UART_ERROR_NONE;
592 SET_BIT(hperh->state, UART_STATE_TX_MASK);
593
594 hperh->tx_size = size;
595 hperh->tx_count = 0;
596 SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK);
597
598 while (size-- > 0) {
599 if (uart_wait_flag(hperh, UART_STATUS_TFTH, SET, timeout) != OK) {
600 hperh->state = UART_STATE_READY;
601 return TIMEOUT;
602 }
603
604 hperh->perh->TXBUF = (*buf++ & 0xFF);
605 hperh->tx_count++;
606 }
607
608 if (uart_wait_flag(hperh, UART_STATUS_TSBUSY, RESET, timeout) != OK) {
609 hperh->state = UART_STATE_READY;
610 return TIMEOUT;
611 }
612
613 CLEAR_BIT(hperh->state, UART_STATE_TX_MASK);
614 return OK;
615 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
OK
Definition: utils.h:55
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
uart_handle_s::err_code
uart_error_t err_code
Definition: ald_uart.h:185
BUSY
Definition: utils.h:57
SET
Definition: type.h:39
UART_STATE_READY
Definition: ald_uart.h:134
UART_STATUS_TFTH
Definition: ald_uart.h:297
RESET
Definition: type.h:38
UART_STATUS_TSBUSY
Definition: ald_uart.h:296
UART_ERROR_NONE
Definition: ald_uart.h:147
UART_STATE_TX_MASK
#define UART_STATE_TX_MASK
Definition: ald_uart.h:454
uart_wait_flag
static ald_status_t uart_wait_flag(uart_handle_t *hperh, uart_status_t flag, flag_status_t status, uint32_t timeout)
This function handles uart Communication Timeout.
Definition: ald_uart.c:177
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
TIMEOUT
Definition: utils.h:58
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
uart_handle_s::tx_size
uint16_t tx_size
Definition: ald_uart.h:174
ERROR
Definition: utils.h:56
uart_handle_s::tx_count
uint16_t tx_count
Definition: ald_uart.h:175
UART_STATE_BUSY_RX
Definition: ald_uart.h:137


ALD User Manual: Peripheral Control functions

Functions
Peripheral Control functions
EASTSOFT ES32F3xx ALD » UART » UART Public Functions

UART control functions. More...

Collaboration diagram for Peripheral Control functions:

Functions

void | ald_uart_interrupt_config (uart_handle_t *hperh, uart_it_t it, type_func_t state)
Enable/disable the specified UART interrupts. More...
void | ald_uart_dma_req_config (uart_handle_t *hperh, uart_dma_req_t req, type_func_t state)
Configure UART DMA request. More...
void | ald_uart_tx_fifo_config (uart_handle_t *hperh, uart_txfifo_t config)
Configure transmit fifo parameters. More...
void | ald_uart_rx_fifo_config (uart_handle_t *hperh, uart_rxfifo_t config)
Configure receive fifo parameters. More...
void | uart_lin_break_detect_irq (uart_handle_t *hperh, type_func_t status)
Enable/Disable break signal detect interrup. More...
void | ald_uart_lin_send_break (uart_handle_t *hperh)
request to send a frame of break. More...
void | ald_uart_lin_detect_break_len_config (uart_handle_t *hperh, uart_lin_break_len_t len)
Configure the length of break frame to be detect. More...
void | ald_uart_auto_baud_config (uart_handle_t *hperh, uart_auto_baud_mode_t mode)
Configure the mode of auto-baud-rate detect. More...
ald_status_t | ald_uart_rs485_send_addr (uart_handle_t *hperh, uint16_t addr, uint32_t timeout)
Send address in RS485 mode. More...
it_status_t | ald_uart_get_it_status (uart_handle_t *hperh, uart_it_t it)
Get the status of UART interrupt source. More...
flag_status_t | ald_uart_get_status (uart_handle_t *hperh, uart_status_t status)
Get the status of UART_SR register. More...
flag_status_t | ald_uart_get_flag_status (uart_handle_t *hperh, uart_flag_t flag)
Get the status of UART interrupt flag. More...
flag_status_t | ald_uart_get_mask_flag_status (uart_handle_t *hperh, uart_flag_t flag)
Get the status of interrupt flag and interupt source. More...
void | ald_uart_clear_flag_status (uart_handle_t *hperh, uart_flag_t flag)
Clear the UART interrupt flag. More...

Detailed Description

UART control functions.

==============================================================================
                    ##### Peripheral Control functions #####
==============================================================================
[..]
  This subsection provides a set of functions allowing to control the UART:
  (+) ald_uart_interrupt_config() API can be helpful to configure UART interrupt source.
  (+) ald_uart_dma_req_config() API can be helpful to configure UART DMA request.
  (+) ald_uart_tx_fifo_config() API can be helpful to configure UART TX FIFO paramters.
  (+) ald_uart_rx_fifo_config() API can be helpful to configure UART RX FIFO paramters.
  (+) ald_uart_lin_send_break() API can send a frame of break in LIN mode.
  (+) ald_uart_lin_detect_break_len_config() API can be helpful to configure the length of break frame.
  (+) ald_uart_auto_baud_config() API can be helpful to configure detection data mode.
  (+) ald_uart_get_it_status() API can get the status of interrupt source.
  (+) ald_uart_get_status() API can get the status of UART_SR register.
  (+) ald_uart_get_flag_status() API can get the status of UART flag.
  (+) ald_uart_get_mask_flag_status() API can get status os flag and interrupt source.
  (+) ald_uart_clear_flag_status() API can clear UART flag.

Function Documentation

◆ ald_uart_auto_baud_config()

void ald_uart_auto_baud_config | ( | uart_handle_t * | hperh,
 |  | uart_auto_baud_mode_t | mode
 | ) |  |

Configure the mode of auto-baud-rate detect.

Parameters
hperh Pointer to a uart_handle_t structure.
mode The mode of auto-baud-rate detect.
  • UART_ABRMOD_1_TO_0
  • UART_ABRMOD_1
  • UART_ABRMOD_0_TO_1
Return values
None

Definition at line 1269 of file ald_uart.c.

1270 {
1271 assert_param(IS_UART_ALL(hperh->perh));
1272 assert_param(IS_UART_AUTO_BAUD_MODE(mode));
1273
1274 MODIFY_REG(hperh->perh->MCON, UART_MCON_ABRMOD_MSK, mode << UART_MCON_ABRMOD_POSS);
1275
1276 return;
1277 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
IS_UART_AUTO_BAUD_MODE
#define IS_UART_AUTO_BAUD_MODE(x)
Definition: ald_uart.h:393
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74

◆ ald_uart_clear_flag_status()

void ald_uart_clear_flag_status | ( | uart_handle_t * | hperh,
 |  | uart_flag_t | flag
 | ) |  |

Clear the UART interrupt flag.

Parameters
hperh | Pointer to a uart_handle_t structure.
flag | Specifies the UART interrupt flag. This parameter can be one of the uart_flag_t.
Return values
None

Definition at line 1403 of file ald_uart.c.

1404 {
1405 assert_param(IS_UART_ALL(hperh->perh));
1406 assert_param(IS_UART_IF(flag));
1407
1408 hperh->perh->ICR = flag;
1409 return;
1410 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_UART_IF
#define IS_UART_IF(x)
Definition: ald_uart.h:430
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171

◆ ald_uart_dma_req_config()

void ald_uart_dma_req_config | ( | uart_handle_t * | hperh,
 |  | uart_dma_req_t | req,
 |  | type_func_t | state
 | ) |  |

Configure UART DMA request.

Parameters
hperh | Pointer to a uart_handle_t structure.
req | The type of DMA request.
state New state of the specified DMA request. This parameter can be:
  • ENABLE
  • DISABLE
Return values
None

Definition at line 1150 of file ald_uart.c.

1151 {
1152 assert_param(IS_UART_ALL(hperh->perh));
1153 assert_param(IS_UART_DMA_REQ(req));
1154 assert_param(IS_FUNC_STATE(state));
1155
1156 if (req == UART_DMA_REQ_TX) {
1157 if (state == ENABLE)
1158 SET_BIT(hperh->perh->MCON, UART_MCON_TXDMAEN_MSK);
1159 else
1160 CLEAR_BIT(hperh->perh->MCON, UART_MCON_TXDMAEN_MSK);
1161 }
1162 else {
1163 if (state == ENABLE)
1164 SET_BIT(hperh->perh->MCON, UART_MCON_RXDMAEN_MSK);
1165 else
1166 CLEAR_BIT(hperh->perh->MCON, UART_MCON_RXDMAEN_MSK);
1167 }
1168
1169 return;
1170 }
ENABLE
Definition: type.h:49
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_UART_DMA_REQ
#define IS_UART_DMA_REQ(x)
Definition: ald_uart.h:396
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
UART_DMA_REQ_TX
Definition: ald_uart.h:278
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_uart_get_flag_status()

flag_status_t ald_uart_get_flag_status | ( | uart_handle_t * | hperh,
 |  | uart_flag_t | flag
 | ) |  |

Get the status of UART interrupt flag.

Parameters
hperh | Pointer to a uart_handle_t structure.
flag | Specifies the UART interrupt flag. This parameter can be one of the uart_flag_t.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 1365 of file ald_uart.c.

1366 {
1367 assert_param(IS_UART_ALL(hperh->perh));
1368 assert_param(IS_UART_IF(flag));
1369
1370 if (hperh->perh->RIF & flag)
1371 return SET;
1372
1373 return RESET;
1374 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
RESET
Definition: type.h:38
IS_UART_IF
#define IS_UART_IF(x)
Definition: ald_uart.h:430
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171

◆ ald_uart_get_it_status()

it_status_t ald_uart_get_it_status | ( | uart_handle_t * | hperh,
 |  | uart_it_t | it
 | ) |  |

Get the status of UART interrupt source.

Parameters
hperh | Pointer to a uart_handle_t structure.
it | Specifies the UART interrupt source. This parameter can be one of the uart_it_t.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 1322 of file ald_uart.c.

1323 {
1324 it_status_t status = RESET;
1325
1326 assert_param(IS_UART_ALL(hperh->perh));
1327 assert_param(IS_UART_IT(it));
1328
1329 if (hperh->perh->IVS & it)
1330 status = SET;
1331
1332 return status;
1333 }
IS_UART_IT
#define IS_UART_IT(x)
Definition: ald_uart.h:413
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
RESET
Definition: type.h:38
it_status_t
enum flag_status_t it_status_t
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171

◆ ald_uart_get_mask_flag_status()

flag_status_t ald_uart_get_mask_flag_status | ( | uart_handle_t * | hperh,
 |  | uart_flag_t | flag
 | ) |  |

Get the status of interrupt flag and interupt source.

Parameters
hperh | Pointer to a uart_handle_t structure.
flag | Specifies the UART interrupt flag. This parameter can be one of the uart_flag_t.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 1385 of file ald_uart.c.

1386 {
1387 assert_param(IS_UART_ALL(hperh->perh));
1388 assert_param(IS_UART_IF(flag));
1389
1390 if (hperh->perh->IFM & flag)
1391 return SET;
1392
1393 return RESET;
1394 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
RESET
Definition: type.h:38
IS_UART_IF
#define IS_UART_IF(x)
Definition: ald_uart.h:430
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171

◆ ald_uart_get_status()

flag_status_t ald_uart_get_status | ( | uart_handle_t * | hperh,
 |  | uart_status_t | status
 | ) |  |

Get the status of UART_SR register.

Parameters
hperh | Pointer to a uart_handle_t structure.
status | Specifies the UART status type. This parameter can be one of the uart_status_t.
Return values
Status
  • 0: RESET
  • 1: SET

Definition at line 1344 of file ald_uart.c.

1345 {
1346 assert_param(IS_UART_ALL(hperh->perh));
1347 assert_param(IS_UART_STATUS(status));
1348
1349 if (hperh->perh->STAT & status)
1350 return SET;
1351
1352 return RESET;
1353 }
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
RESET
Definition: type.h:38
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
IS_UART_STATUS
#define IS_UART_STATUS(x)
Definition: ald_uart.h:398

◆ ald_uart_interrupt_config()

void ald_uart_interrupt_config | ( | uart_handle_t * | hperh,
 |  | uart_it_t | it,
 |  | type_func_t | state
 | ) |  |

Enable/disable the specified UART interrupts.

Parameters
hperh | Pointer to a uart_handle_t structure.
it | Specifies the UART interrupt sources to be enabled or disabled. This parameter can be one of the uart_it_t.
state New state of the specified UART interrupts. This parameter can be:
  • ENABLE
  • DISABLE
Return values
None

Definition at line 1126 of file ald_uart.c.

1127 {
1128 assert_param(IS_UART_ALL(hperh->perh));
1129 assert_param(IS_UART_IT(it));
1130 assert_param(IS_FUNC_STATE(state));
1131
1132 if (state == ENABLE)
1133 hperh->perh->IER = it;
1134 else
1135 hperh->perh->IDR = it;
1136
1137 return;
1138 }
ENABLE
Definition: type.h:49
IS_UART_IT
#define IS_UART_IT(x)
Definition: ald_uart.h:413
assert_param
#define assert_param(x)
Definition: type.h:88
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_uart_lin_detect_break_len_config()

void ald_uart_lin_detect_break_len_config | ( | uart_handle_t * | hperh,
 |  | uart_lin_break_len_t | len
 | ) |  |

Configure the length of break frame to be detect.

Parameters
hperh Pointer to a uart_handle_t structure.
len Length of break frame.
  • LIN_BREAK_LEN_10B
  • LIN_BREAK_LEN_11B
Return values
None

Definition at line 1250 of file ald_uart.c.

1251 {
1252 assert_param(IS_UART_ALL(hperh->perh));
1253 assert_param(IS_UART_LIN_BREAK_LEN(len));
1254
1255 MODIFY_REG(hperh->perh->LIN, UART_LIN_LINBDL_MSK, len << UART_LIN_LINBDL_POS);
1256
1257 return;
1258 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
IS_UART_LIN_BREAK_LEN
#define IS_UART_LIN_BREAK_LEN(x)
Definition: ald_uart.h:383
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74

◆ ald_uart_lin_send_break()

void ald_uart_lin_send_break ( uart_handle_t * hperh )

request to send a frame of break.

Parameters
hperh Pointer to a uart_handle_t structure.
Return values
None

Definition at line 1231 of file ald_uart.c.

1232 {
1233 assert_param(IS_UART_ALL(hperh->perh));
1234
1235 SET_BIT(hperh->perh->LIN, UART_LIN_LINBKREQ_MSK);
1236
1237 hperh->perh->TXBUF = (0x55);
1238
1239 return;
1240 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67

◆ ald_uart_rs485_send_addr()

ald_status_t ald_uart_rs485_send_addr | ( | uart_handle_t * | hperh,
 |  | uint16_t | addr,
 |  | uint32_t | timeout
 | ) |  |

Send address in RS485 mode.

Parameters
hperh | Pointer to a uart_handle_t structure that contains the configuration information for the specified UART module.
addr | the address of RS485 device.
timeout | Timeout duration
Return values
The ALD status.

Definition at line 1287 of file ald_uart.c.

1288 {
1289 assert_param(IS_UART_ALL(hperh->perh));
1290
1291 if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX))
1292 return BUSY;
1293
1294 SET_BIT(hperh->state, UART_STATE_TX_MASK);
1295
1296 if (uart_wait_flag(hperh, UART_STATUS_TFEMPTY, SET, timeout) != OK) {
1297 hperh->state = UART_STATE_READY;
1298 return TIMEOUT;
1299 }
1300
1301 WRITE_REG(hperh->perh->TXBUF, (addr | 0x100));
1302
1303 if (uart_wait_flag(hperh, UART_STATUS_TFEMPTY, SET, timeout) != OK) {
1304 hperh->state = UART_STATE_READY;
1305 return TIMEOUT;
1306 }
1307
1308 CLEAR_BIT(hperh->state, UART_STATE_TX_MASK);
1309
1310 return OK;
1311 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
OK
Definition: utils.h:55
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
SET
Definition: type.h:39
UART_STATE_READY
Definition: ald_uart.h:134
UART_STATE_TX_MASK
#define UART_STATE_TX_MASK
Definition: ald_uart.h:454
uart_wait_flag
static ald_status_t uart_wait_flag(uart_handle_t *hperh, uart_status_t flag, flag_status_t status, uint32_t timeout)
This function handles uart Communication Timeout.
Definition: ald_uart.c:177
UART_STATUS_TFEMPTY
Definition: ald_uart.h:298
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
TIMEOUT
Definition: utils.h:58
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
UART_STATE_BUSY_RX
Definition: ald_uart.h:137

◆ ald_uart_rx_fifo_config()

void ald_uart_rx_fifo_config | ( | uart_handle_t * | hperh,
 |  | uart_rxfifo_t | config
 | ) |  |

Configure receive fifo parameters.

Parameters
hperh | Pointer to a uart_handle_t structure.
config | Receive fifo trigger level.
Return values
None

Definition at line 1195 of file ald_uart.c.

1196 {
1197 assert_param(IS_UART_ALL(hperh->perh));
1198 assert_param(IS_UART_RXFIFO_TYPE(config));
1199
1200 SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK);
1201 MODIFY_REG(hperh->perh->FCON, UART_FCON_RXTH_MSK, config << UART_FCON_RXTH_POSS);
1202
1203 return;
1204 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_UART_RXFIFO_TYPE
#define IS_UART_RXFIFO_TYPE(x)
Definition: ald_uart.h:389
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74

◆ ald_uart_tx_fifo_config()

void ald_uart_tx_fifo_config | ( | uart_handle_t * | hperh,
 |  | uart_txfifo_t | config
 | ) |  |

Configure transmit fifo parameters.

Parameters
hperh | Pointer to a uart_handle_t structure.
config | Transmit fifo trigger level.
Return values
None

Definition at line 1178 of file ald_uart.c.

1179 {
1180 assert_param(IS_UART_ALL(hperh->perh));
1181 assert_param(IS_UART_TXFIFO_TYPE(config));
1182
1183 SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK);
1184 MODIFY_REG(hperh->perh->FCON, UART_FCON_TXTH_MSK, config << UART_FCON_TXTH_POSS);
1185
1186 return;
1187 }
assert_param
#define assert_param(x)
Definition: type.h:88
IS_UART_TXFIFO_TYPE
#define IS_UART_TXFIFO_TYPE(x)
Definition: ald_uart.h:385
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74

◆ uart_lin_break_detect_irq()

void uart_lin_break_detect_irq | ( | uart_handle_t * | hperh,
 |  | type_func_t | status
 | ) |  |

Enable/Disable break signal detect interrup.

Parameters
hperh | Pointer to a uart_handle_t structure.
status | The new status.
Return values
None

Definition at line 1212 of file ald_uart.c.

1213 {
1214 assert_param(IS_UART_ALL(hperh->perh));
1215
1216 if (status == ENABLE) {
1217 SET_BIT(hperh->perh->IER, UART_IER_LINBK_MSK);
1218 }
1219 else {
1220 CLEAR_BIT(hperh->perh->IER, UART_IER_LINBK_MSK);
1221 }
1222
1223 return;
1224 }
ENABLE
Definition: type.h:49
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67


ALD User Manual: Peripheral State and Errors functions

Functions
Peripheral State and Errors functions
EASTSOFT ES32F3xx ALD » UART » UART Public Functions

UART State and Errors functions. More...

Collaboration diagram for Peripheral State and Errors functions:

Functions

uart_state_t | ald_uart_get_state (uart_handle_t *hperh)
Returns the UART state. More...
uint32_t | ald_uart_get_error (uart_handle_t *hperh)
Return the UART error code. More...

Detailed Description

UART State and Errors functions.

  ==============================================================================
                 ##### Peripheral State and Errors functions #####
  ==============================================================================
 [..]
   This subsection provides a set of functions allowing to return the State of
   UART communication process, return Peripheral Errors occurred during communication
   process
   (+) ald_uart_get_state() API can be helpful to check in run-time the state of the UART peripheral.
   (+) ald_uart_get_error() check in run-time errors that could be occurred during communication.

Function Documentation

◆ ald_uart_get_error()

uint32_t ald_uart_get_error ( uart_handle_t * hperh )

Return the UART error code.

Parameters
hperh Pointer to a uart_handle_t structure.
Return values
UART Error Code

Definition at line 1448 of file ald_uart.c.

1449 {
1450 return hperh->err_code;
1451 }
uart_handle_s::err_code
uart_error_t err_code
Definition: ald_uart.h:185

◆ ald_uart_get_state()

uart_state_t ald_uart_get_state ( uart_handle_t * hperh )

Returns the UART state.

Parameters
hperh Pointer to a uart_handle_t structure.
Return values
ALD state

Definition at line 1438 of file ald_uart.c.

1439 {
1440 return hperh->state;
1441 }
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184


ALD User Manual: UART Public Macros

Macros
UART Public Macros
EASTSOFT ES32F3xx ALD » UART
Collaboration diagram for UART Public Macros:

Macros

#define | UART_RX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_RXEN_MSK))
#define | UART_RX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RXEN_MSK))
#define | UART_TX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK))
#define | UART_TX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK))
#define | UART_RX_TIMEOUT_ENABLE(hperh) (SET_BIT((hperh)->perh->RTOR, UART_RTOR_RTOEN_MSK))
#define | UART_RX_TIMEOUT_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->RTOR, UART_RTOR_RTOEN_MSK))
#define | UART_MSB_FIRST_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK))
#define | UART_MSB_FIRST_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK))
#define | UART_DATA_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_DATAINV_MSK))
#define | UART_DATA_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_DATAINV_MSK))
#define | UART_RX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_RXINV_MSK))
#define | UART_RX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RXINV_MSK))
#define | UART_TX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_TXINV_MSK))
#define | UART_TX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_TXINV_MSK))
#define | UART_TX_RX_SWAP_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_SWAP_MSK))
#define | UART_TX_RX_SWAP_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_SWAP_MSK))
#define | UART_HDSEL_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_HDEN_MSK))
#define | UART_HDSEL_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_HDEN_MSK))
#define | UART_FIFO_TX_RESET(hperh) (SET_BIT((hperh)->perh->FCON, UART_FCON_TFRST_MSK))
#define | UART_FIFO_RX_RESET(hperh) (SET_BIT((hperh)->perh->FCON, UART_FCON_RFRST_MSK))
#define | UART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_LPBKEN_MSK))
#define | UART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_LPBKEN_MSK))
#define | UART_AUTOBR_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK))
#define | UART_AUTOBR_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK))
#define | UART_AUTOBR_REPT(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_ABRREPT_MSK))
#define | UART_GET_BRR_VALUE(hperh) (READ_REG((hperh)->perh->BRR))
#define | UART_SET_TIMEOUT_VALUE(x, y) (MODIFY_REG((x)->perh->RTOR, UART_RTOR_RTO_MSK, (y) << UART_RTOR_RTO_POSS))
#define | UART_ENABLE_SCARD_CLK(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCLKEN_MSK))
#define | UART_DISABLE_SCARD_CLK(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCLKEN_MSK))
#define | UART_ENABLE_SCARD_NACK(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCNACK_MSK))
#define | UART_DISABLE_SCARD_NACK(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCNACK_MSK))
#define | UART_SCARD_ENABLE(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCEN_MSK))
#define | UART_SCARD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCEN_MSK))

Detailed Description

Macro Definition Documentation

◆ UART_AUTOBR_DISABLE

#define UART_AUTOBR_DISABLE ( hperh ) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK))

Definition at line 63 of file ald_uart.h.

◆ UART_AUTOBR_ENABLE

#define UART_AUTOBR_ENABLE ( hperh ) (SET_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK))

Definition at line 62 of file ald_uart.h.

◆ UART_AUTOBR_REPT

#define UART_AUTOBR_REPT ( hperh ) (SET_BIT((hperh)->perh->MCON, UART_MCON_ABRREPT_MSK))

Definition at line 64 of file ald_uart.h.

◆ UART_DATA_INV_DISABLE

#define UART_DATA_INV_DISABLE ( hperh ) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_DATAINV_MSK))

Definition at line 49 of file ald_uart.h.

◆ UART_DATA_INV_ENABLE

#define UART_DATA_INV_ENABLE ( hperh ) (SET_BIT((hperh)->perh->LCON, UART_LCON_DATAINV_MSK))

Definition at line 48 of file ald_uart.h.

◆ UART_DISABLE_SCARD_CLK

#define UART_DISABLE_SCARD_CLK ( hperh ) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCLKEN_MSK))

Definition at line 68 of file ald_uart.h.

◆ UART_DISABLE_SCARD_NACK

#define UART_DISABLE_SCARD_NACK ( hperh ) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCNACK_MSK))

Definition at line 70 of file ald_uart.h.

◆ UART_ENABLE_SCARD_CLK

#define UART_ENABLE_SCARD_CLK ( hperh ) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCLKEN_MSK))

Definition at line 67 of file ald_uart.h.

◆ UART_ENABLE_SCARD_NACK

#define UART_ENABLE_SCARD_NACK ( hperh ) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCNACK_MSK))

Definition at line 69 of file ald_uart.h.

◆ UART_FIFO_RX_RESET

#define UART_FIFO_RX_RESET ( hperh ) (SET_BIT((hperh)->perh->FCON, UART_FCON_RFRST_MSK))

Definition at line 59 of file ald_uart.h.

◆ UART_FIFO_TX_RESET

#define UART_FIFO_TX_RESET ( hperh ) (SET_BIT((hperh)->perh->FCON, UART_FCON_TFRST_MSK))

Definition at line 58 of file ald_uart.h.

◆ UART_GET_BRR_VALUE

#define UART_GET_BRR_VALUE ( hperh ) (READ_REG((hperh)->perh->BRR))

Definition at line 65 of file ald_uart.h.

◆ UART_HDSEL_DISABLE

#define UART_HDSEL_DISABLE ( hperh ) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_HDEN_MSK))

Definition at line 57 of file ald_uart.h.

◆ UART_HDSEL_ENABLE

#define UART_HDSEL_ENABLE ( hperh ) (SET_BIT((hperh)->perh->MCON, UART_MCON_HDEN_MSK))

Definition at line 56 of file ald_uart.h.

◆ UART_LPBMOD_DISABLE

#define UART_LPBMOD_DISABLE ( hperh ) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_LPBKEN_MSK))

Definition at line 61 of file ald_uart.h.

◆ UART_LPBMOD_ENABLE

#define UART_LPBMOD_ENABLE ( hperh ) (SET_BIT((hperh)->perh->MCON, UART_MCON_LPBKEN_MSK))

Definition at line 60 of file ald_uart.h.

◆ UART_MSB_FIRST_DISABLE

#define UART_MSB_FIRST_DISABLE ( hperh ) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK))

Definition at line 47 of file ald_uart.h.

◆ UART_MSB_FIRST_ENABLE

#define UART_MSB_FIRST_ENABLE ( hperh ) (SET_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK))

Definition at line 46 of file ald_uart.h.

◆ UART_RX_DISABLE

#define UART_RX_DISABLE ( hperh ) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RXEN_MSK))

Definition at line 41 of file ald_uart.h.

◆ UART_RX_ENABLE

#define UART_RX_ENABLE ( hperh ) (SET_BIT((hperh)->perh->LCON, UART_LCON_RXEN_MSK))

Definition at line 40 of file ald_uart.h.

◆ UART_RX_INV_DISABLE

#define UART_RX_INV_DISABLE ( hperh ) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RXINV_MSK))

Definition at line 51 of file ald_uart.h.

◆ UART_RX_INV_ENABLE

#define UART_RX_INV_ENABLE ( hperh ) (SET_BIT((hperh)->perh->LCON, UART_LCON_RXINV_MSK))

Definition at line 50 of file ald_uart.h.

◆ UART_RX_TIMEOUT_DISABLE

#define UART_RX_TIMEOUT_DISABLE ( hperh ) (CLEAR_BIT((hperh)->perh->RTOR, UART_RTOR_RTOEN_MSK))

Definition at line 45 of file ald_uart.h.

◆ UART_RX_TIMEOUT_ENABLE

#define UART_RX_TIMEOUT_ENABLE ( hperh ) (SET_BIT((hperh)->perh->RTOR, UART_RTOR_RTOEN_MSK))

Definition at line 44 of file ald_uart.h.

◆ UART_SCARD_DISABLE

#define UART_SCARD_DISABLE ( hperh ) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCEN_MSK))

Definition at line 72 of file ald_uart.h.

◆ UART_SCARD_ENABLE

#define UART_SCARD_ENABLE ( hperh ) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCEN_MSK))

Definition at line 71 of file ald_uart.h.

◆ UART_SET_TIMEOUT_VALUE

#define UART_SET_TIMEOUT_VALUE | ( | x,
 |  | y
 | ) | (MODIFY_REG((x)->perh->RTOR, UART_RTOR_RTO_MSK, (y) << UART_RTOR_RTO_POSS))

Definition at line 66 of file ald_uart.h.

◆ UART_TX_DISABLE

#define UART_TX_DISABLE ( hperh ) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK))

Definition at line 43 of file ald_uart.h.

◆ UART_TX_ENABLE

#define UART_TX_ENABLE ( hperh ) (SET_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK))

Definition at line 42 of file ald_uart.h.

◆ UART_TX_INV_DISABLE

#define UART_TX_INV_DISABLE ( hperh ) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_TXINV_MSK))

Definition at line 53 of file ald_uart.h.

◆ UART_TX_INV_ENABLE

#define UART_TX_INV_ENABLE ( hperh ) (SET_BIT((hperh)->perh->LCON, UART_LCON_TXINV_MSK))

Definition at line 52 of file ald_uart.h.

◆ UART_TX_RX_SWAP_DISABLE

#define UART_TX_RX_SWAP_DISABLE ( hperh ) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_SWAP_MSK))

Definition at line 55 of file ald_uart.h.

◆ UART_TX_RX_SWAP_ENABLE

#define UART_TX_RX_SWAP_ENABLE ( hperh ) (SET_BIT((hperh)->perh->LCON, UART_LCON_SWAP_MSK))

Definition at line 54 of file ald_uart.h.


ALD User Manual: UART Public Types

Data Structures | Typedefs | Enumerations
UART Public Types
EASTSOFT ES32F3xx ALD » UART
Collaboration diagram for UART Public Types:

Data Structures

struct | uart_init_t
UART init structure definition. More...
struct | uart_handle_s
UART handle structure definition. More...
struct | uart_rs485_config_t
UART RS485 configure structure definition. More...
struct | uart_scard_config_t
UART Smart card configure structure definition. More...

Typedefs

typedef struct uart_handle_s uart_handle_t
UART handle structure definition. More...

Enumerations

enum | uart_word_length_t { UART_WORD_LENGTH_8B = 0x0U, UART_WORD_LENGTH_7B = 0x1U, UART_WORD_LENGTH_6B = 0x2U, UART_WORD_LENGTH_5B = 0x3U }
UART word length. More...
enum | uart_stop_bits_t { UART_STOP_BITS_1 = 0x0U, UART_STOP_BITS_2 = 0x1U, UART_STOP_BITS_0_5 = 0x0U, UART_STOP_BITS_1_5 = 0x1U }
UART stop bits. More...
enum | uart_parity_t { UART_PARITY_NONE = 0x0U, UART_PARITY_ODD = 0x1U, UART_PARITY_EVEN = 0x3U }
UART parity. More...
enum uart_mode_t {
UART_MODE_UART = 0x0U, UART_MODE_LIN = 0x1U, UART_MODE_IrDA = 0x2U, UART_MODE_RS485 = 0x3U,
UART_MODE_HDSEL = 0x4U, UART_MODE_SCARD = 0x5U
}
UART mode. More...
enum | uart_hw_flow_ctl_t { UART_HW_FLOW_CTL_DISABLE = 0x0U, UART_HW_FLOW_CTL_ENABLE = 0x1U }
UART hardware flow control. More...
enum uart_state_t {
UART_STATE_RESET = 0x00U, UART_STATE_READY = 0x01U, UART_STATE_BUSY = 0x02U, UART_STATE_BUSY_TX = 0x11U,
UART_STATE_BUSY_RX = 0x21U, UART_STATE_BUSY_TX_RX = 0x31U, UART_STATE_TIMEOUT = 0x03U, UART_STATE_ERROR = 0x04U
}
ALD UART state. More...
enum uart_error_t {
UART_ERROR_NONE = ((uint32_t)0x00U), UART_ERROR_PE = ((uint32_t)0x01U), UART_ERROR_NE = ((uint32_t)0x02U), UART_ERROR_FE = ((uint32_t)0x04U),
UART_ERROR_ORE = ((uint32_t)0x08U), UART_ERROR_DMA = ((uint32_t)0x10U)
}
UART error codes. More...
enum | scard_clk_div_t { SCARD_CLOCK_DIV1 = 0x0U, SCARD_CLOCK_DIV2 = 0x1U, SCARD_CLOCK_DIV4 = 0x2U, SCARD_CLOCK_DIV6 = 0x3U }
Smart_card clock division. More...
enum scard_retry_t {
SCARD_RETRY_CNT0 = 0x0U, SCARD_RETRY_CNT1 = 0x1U, SCARD_RETRY_CNT2 = 0x2U, SCARD_RETRY_CNT3 = 0x3U,
SCARD_RETRY_CNT4 = 0x4U, SCARD_RETRY_CNT5 = 0x5U, SCARD_RETRY_CNT6 = 0x6U, SCARD_RETRY_CNT7 = 0x7U
}
Smart_card Rx/Tx handle retry time. More...
enum | uart_lin_break_len_t { LIN_BREAK_LEN_10B = 0x0U, LIN_BREAK_LEN_11B = 0x1U }
LIN detection break length. More...
enum | uart_txfifo_t { UART_TXFIFO_EMPTY = 0x0U, UART_TXFIFO_2BYTE = 0x1U, UART_TXFIFO_4BYTE = 0x2U, UART_TXFIFO_8BYTE = 0x3U }
UART TXFIFO size. More...
enum | uart_rxfifo_t { UART_RXFIFO_1BYTE = 0x0U, UART_RXFIFO_4BYTE = 0x1U, UART_RXFIFO_8BYTE = 0x2U, UART_RXFIFO_14BYTE = 0x3U }
UART RXFIFO size. More...
enum | uart_auto_baud_mode_t { UART_ABRMOD_1_TO_0 = 0x0U, UART_ABRMOD_1 = 0x1U, UART_ABRMOD_0_TO_1 = 0x2U }
UART auto-baud mode. More...
enum | uart_dma_req_t { UART_DMA_REQ_TX = 0x0U, UART_DMA_REQ_RX = 0x1U }
UART DMA Requests. More...
enum uart_status_t {
UART_STATUS_PERR = (1U << 0), UART_STATUS_FERR = (1U << 1), UART_STATUS_BKERR = (1U << 2), UART_STATUS_CTSSTA = (1U << 3),
UART_STATUS_RSBUSY = (1U << 8), UART_STATUS_RFTH = (1U << 9), UART_STATUS_RFEMPTY = (1U << 10), UART_STATUS_RFFULL = (1U << 11),
UART_STATUS_RFOERR = (1U << 12), UART_STATUS_RFUERR = (1U << 13), UART_STATUS_TSBUSY = (1U << 14), UART_STATUS_TFTH = (1U << 15),
UART_STATUS_TFEMPTY = (1U << 16), UART_STATUS_TFFULL = (1U << 17), UART_STATUS_TFOERR = (1U << 18)
}
UART status types. More...
enum uart_it_t {
UART_IT_RXBERR = (1U << 0), UART_IT_ABEND = (1U << 1), UART_IT_ABTO = (1U << 2), UART_IT_DCTS = (1U << 3),
UART_IT_RXTO = (1U << 4), UART_IT_ADDRM = (1U << 5), UART_IT_LINBK = (1U << 6), UART_IT_EOB = (1U << 7),
UART_IT_NOISE = (1U << 8), UART_IT_RFTH = (1U << 9), UART_IT_RFFULL = (1U << 11), UART_IT_RFOERR = (1U << 12),
UART_IT_RFUERR = (1U << 13), UART_IT_TSEMPTY = (1U << 14), UART_IT_TFTH = (1U << 15), UART_IT_TFEMPTY = (1U << 16),
UART_IT_TFOVER = (1U << 18)
}
UART interrupt types. More...
enum uart_flag_t {
UART_IF_RXBERR = (1U << 0), UART_IF_ABEND = (1U << 1), UART_IF_ABTO = (1U << 2), UART_IF_DCTS = (1U << 3),
UART_IF_RXTO = (1U << 4), UART_IF_ADDRM = (1U << 5), UART_IF_LINBK = (1U << 6), UART_IF_EOB = (1U << 7),
UART_IF_NOISE = (1U << 8), UART_IF_RFTH = (1U << 9), UART_IF_RFFULL = (1U << 11), UART_IF_RFOERR = (1U << 12),
UART_IF_RFUERR = (1U << 13), UART_IF_TBC = (1U << 14), UART_IF_TFTH = (1U << 15), UART_IF_TFEMPTY = (1U << 16),
UART_IF_TFOVER = (1U << 18)
}
UART flags types. More...

Detailed Description

Typedef Documentation

◆ uart_handle_t

typedef struct uart_handle_s uart_handle_t

UART handle structure definition.

Enumeration Type Documentation

◆ scard_clk_div_t

enum scard_clk_div_t

Smart_card clock division.

Enumerator
SCARD_CLOCK_DIV1 | No prescaler is used
SCARD_CLOCK_DIV2 |
SCARD_CLOCK_DIV4 | Clock is divided by 2
SCARD_CLOCK_DIV6 | Clock is divided by 4

Definition at line 205 of file ald_uart.h.

205 {
206 SCARD_CLOCK_DIV1 = 0x0U,
207 SCARD_CLOCK_DIV2 = 0x1U,
208 SCARD_CLOCK_DIV4 = 0x2U,
209 SCARD_CLOCK_DIV6 = 0x3U,
210 } scard_clk_div_t;
SCARD_CLOCK_DIV2
Definition: ald_uart.h:207
SCARD_CLOCK_DIV1
Definition: ald_uart.h:206
scard_clk_div_t
scard_clk_div_t
Smart_card clock division.
Definition: ald_uart.h:205
SCARD_CLOCK_DIV6
Definition: ald_uart.h:209
SCARD_CLOCK_DIV4
Definition: ald_uart.h:208

◆ scard_retry_t

enum scard_retry_t

Smart_card Rx/Tx handle retry time.

Enumerator
SCARD_RETRY_CNT0 | retry time 0
SCARD_RETRY_CNT1 | retry time 1
SCARD_RETRY_CNT2 | retry time 2
SCARD_RETRY_CNT3 | retry time 3
SCARD_RETRY_CNT4 | retry time 4
SCARD_RETRY_CNT5 | retry time 5
SCARD_RETRY_CNT6 | retry time 6
SCARD_RETRY_CNT7 | retry time 7

Definition at line 215 of file ald_uart.h.

215 {
216 SCARD_RETRY_CNT0 = 0x0U,
217 SCARD_RETRY_CNT1 = 0x1U,
218 SCARD_RETRY_CNT2 = 0x2U,
219 SCARD_RETRY_CNT3 = 0x3U,
220 SCARD_RETRY_CNT4 = 0x4U,
221 SCARD_RETRY_CNT5 = 0x5U,
222 SCARD_RETRY_CNT6 = 0x6U,
223 SCARD_RETRY_CNT7 = 0x7U,
224 } scard_retry_t;
SCARD_RETRY_CNT4
Definition: ald_uart.h:220
SCARD_RETRY_CNT5
Definition: ald_uart.h:221
SCARD_RETRY_CNT7
Definition: ald_uart.h:223
SCARD_RETRY_CNT0
Definition: ald_uart.h:216
scard_retry_t
scard_retry_t
Smart_card Rx/Tx handle retry time.
Definition: ald_uart.h:215
SCARD_RETRY_CNT6
Definition: ald_uart.h:222
SCARD_RETRY_CNT2
Definition: ald_uart.h:218
SCARD_RETRY_CNT1
Definition: ald_uart.h:217
SCARD_RETRY_CNT3
Definition: ald_uart.h:219

◆ uart_auto_baud_mode_t

enum uart_auto_baud_mode_t

UART auto-baud mode.

Enumerator
UART_ABRMOD_1_TO_0 | Detect bit0:1, bit1:0
UART_ABRMOD_1 | Detect bit0:1
UART_ABRMOD_0_TO_1 | Detect bit0:0, bit1:1

Definition at line 268 of file ald_uart.h.

268 {
269 UART_ABRMOD_1_TO_0 = 0x0U,
270 UART_ABRMOD_1 = 0x1U,
271 UART_ABRMOD_0_TO_1 = 0x2U,
272 } uart_auto_baud_mode_t;
uart_auto_baud_mode_t
uart_auto_baud_mode_t
UART auto-baud mode.
Definition: ald_uart.h:268
UART_ABRMOD_1_TO_0
Definition: ald_uart.h:269
UART_ABRMOD_0_TO_1
Definition: ald_uart.h:271
UART_ABRMOD_1
Definition: ald_uart.h:270

◆ uart_dma_req_t

enum uart_dma_req_t

UART DMA Requests.

Enumerator
UART_DMA_REQ_TX | TX dma
UART_DMA_REQ_RX | RX dma

Definition at line 277 of file ald_uart.h.

277 {
278 UART_DMA_REQ_TX = 0x0U,
279 UART_DMA_REQ_RX = 0x1U,
280 } uart_dma_req_t;
uart_dma_req_t
uart_dma_req_t
UART DMA Requests.
Definition: ald_uart.h:277
UART_DMA_REQ_TX
Definition: ald_uart.h:278
UART_DMA_REQ_RX
Definition: ald_uart.h:279

◆ uart_error_t

enum uart_error_t

UART error codes.

Enumerator
UART_ERROR_NONE | No error
UART_ERROR_PE | Parity error
UART_ERROR_NE | Noise error
UART_ERROR_FE | frame error
UART_ERROR_ORE | Overrun error
UART_ERROR_DMA | DMA transfer error

Definition at line 146 of file ald_uart.h.

146 {
147 UART_ERROR_NONE = ((uint32_t)0x00U),
148 UART_ERROR_PE = ((uint32_t)0x01U),
149 UART_ERROR_NE = ((uint32_t)0x02U),
150 UART_ERROR_FE = ((uint32_t)0x04U),
151 UART_ERROR_ORE = ((uint32_t)0x08U),
152 UART_ERROR_DMA = ((uint32_t)0x10U),
153 } uart_error_t;
UART_ERROR_PE
Definition: ald_uart.h:148
uart_error_t
uart_error_t
UART error codes.
Definition: ald_uart.h:146
UART_ERROR_FE
Definition: ald_uart.h:150
UART_ERROR_NONE
Definition: ald_uart.h:147
UART_ERROR_NE
Definition: ald_uart.h:149
UART_ERROR_ORE
Definition: ald_uart.h:151
UART_ERROR_DMA
Definition: ald_uart.h:152

◆ uart_flag_t

enum uart_flag_t

UART flags types.

Enumerator
UART_IF_RXBERR | Receiver byte error
UART_IF_ABEND | Auto-Baud rate detection end
UART_IF_ABTO | Auto-Baud rate detection timeout
UART_IF_DCTS | Delta CTS status
UART_IF_RXTO | Receiver timeout
UART_IF_ADDRM | Addredd match
UART_IF_LINBK | Lin break detection
UART_IF_EOB | End of block
UART_IF_NOISE | Start bit noise detection
UART_IF_RFTH | Receive FIFO trigger threshold
UART_IF_RFFULL | Receive FIFO full
UART_IF_RFOERR | Receive FIFO overrun
UART_IF_RFUERR | Reveive FIFO underrun
UART_IF_TBC | Transmit shift register empty
UART_IF_TFTH | Transmit FIFO trigger threshold
UART_IF_TFEMPTY | Transmit FIFO empty
UART_IF_TFOVER | Transmit FIFO overrun

Definition at line 329 of file ald_uart.h.

329 {
330 UART_IF_RXBERR = (1U << 0),
331 UART_IF_ABEND = (1U << 1),
332 UART_IF_ABTO = (1U << 2),
333 UART_IF_DCTS = (1U << 3),
334 UART_IF_RXTO = (1U << 4),
335 UART_IF_ADDRM = (1U << 5),
336 UART_IF_LINBK = (1U << 6),
337 UART_IF_EOB = (1U << 7),
338 UART_IF_NOISE = (1U << 8),
339 UART_IF_RFTH = (1U << 9),
340 UART_IF_RFFULL = (1U << 11),
341 UART_IF_RFOERR = (1U << 12),
342 UART_IF_RFUERR = (1U << 13),
343 UART_IF_TBC = (1U << 14),
344 UART_IF_TFTH = (1U << 15),
345 UART_IF_TFEMPTY = (1U << 16),
346 UART_IF_TFOVER = (1U << 18),
347 } uart_flag_t;
UART_IF_ABTO
Definition: ald_uart.h:332
UART_IF_RXBERR
Definition: ald_uart.h:330
UART_IF_TFTH
Definition: ald_uart.h:344
UART_IF_RFTH
Definition: ald_uart.h:339
UART_IF_RFOERR
Definition: ald_uart.h:341
UART_IF_ADDRM
Definition: ald_uart.h:335
UART_IF_TFEMPTY
Definition: ald_uart.h:345
UART_IF_RFUERR
Definition: ald_uart.h:342
UART_IF_DCTS
Definition: ald_uart.h:333
UART_IF_RXTO
Definition: ald_uart.h:334
UART_IF_TBC
Definition: ald_uart.h:343
uart_flag_t
uart_flag_t
UART flags types.
Definition: ald_uart.h:329
UART_IF_RFFULL
Definition: ald_uart.h:340
UART_IF_EOB
Definition: ald_uart.h:337
UART_IF_LINBK
Definition: ald_uart.h:336
UART_IF_TFOVER
Definition: ald_uart.h:346
UART_IF_NOISE
Definition: ald_uart.h:338
UART_IF_ABEND
Definition: ald_uart.h:331

◆ uart_hw_flow_ctl_t

enum uart_hw_flow_ctl_t

UART hardware flow control.

Enumerator
UART_HW_FLOW_CTL_DISABLE | Auto-flow-control disable
UART_HW_FLOW_CTL_ENABLE | Auto-flow-control enable

Definition at line 124 of file ald_uart.h.

124 {
125 UART_HW_FLOW_CTL_DISABLE = 0x0U,
126 UART_HW_FLOW_CTL_ENABLE = 0x1U,
127 } uart_hw_flow_ctl_t;
UART_HW_FLOW_CTL_ENABLE
Definition: ald_uart.h:126
uart_hw_flow_ctl_t
uart_hw_flow_ctl_t
UART hardware flow control.
Definition: ald_uart.h:124
UART_HW_FLOW_CTL_DISABLE
Definition: ald_uart.h:125

◆ uart_it_t

enum uart_it_t

UART interrupt types.

Enumerator
UART_IT_RXBERR | Receiver byte error
UART_IT_ABEND | Auto-Baud rate detection end
UART_IT_ABTO | Auto-Baud rate detection timeout
UART_IT_DCTS | Delta CTS status
UART_IT_RXTO | Receiver timeout
UART_IT_ADDRM | Addredd match
UART_IT_LINBK | Lin break detection
UART_IT_EOB | End of block
UART_IT_NOISE | Start bit noise detection
UART_IT_RFTH | Receive FIFO trigger threshold
UART_IT_RFFULL | Receive FIFO full
UART_IT_RFOERR | Receive FIFO overrun
UART_IT_RFUERR | Reveive FIFO underrun
UART_IT_TSEMPTY | Transmit shift register empty
UART_IT_TFTH | Transmit FIFO trigger threshold
UART_IT_TFEMPTY | Transmit FIFO empty
UART_IT_TFOVER | Transmit FIFO overrun

Definition at line 306 of file ald_uart.h.

306 {
307 UART_IT_RXBERR = (1U << 0),
308 UART_IT_ABEND = (1U << 1),
309 UART_IT_ABTO = (1U << 2),
310 UART_IT_DCTS = (1U << 3),
311 UART_IT_RXTO = (1U << 4),
312 UART_IT_ADDRM = (1U << 5),
313 UART_IT_LINBK = (1U << 6),
314 UART_IT_EOB = (1U << 7),
315 UART_IT_NOISE = (1U << 8),
316 UART_IT_RFTH = (1U << 9),
317 UART_IT_RFFULL = (1U << 11),
318 UART_IT_RFOERR = (1U << 12),
319 UART_IT_RFUERR = (1U << 13),
320 UART_IT_TSEMPTY = (1U << 14),
321 UART_IT_TFTH = (1U << 15),
322 UART_IT_TFEMPTY = (1U << 16),
323 UART_IT_TFOVER = (1U << 18),
324 } uart_it_t;
UART_IT_DCTS
Definition: ald_uart.h:310
UART_IT_TFEMPTY
Definition: ald_uart.h:322
UART_IT_TSEMPTY
Definition: ald_uart.h:320
UART_IT_RFFULL
Definition: ald_uart.h:317
uart_it_t
uart_it_t
UART interrupt types.
Definition: ald_uart.h:306
UART_IT_LINBK
Definition: ald_uart.h:313
UART_IT_RXBERR
Definition: ald_uart.h:307
UART_IT_ABTO
Definition: ald_uart.h:309
UART_IT_TFOVER
Definition: ald_uart.h:323
UART_IT_EOB
Definition: ald_uart.h:314
UART_IT_RXTO
Definition: ald_uart.h:311
UART_IT_TFTH
Definition: ald_uart.h:321
UART_IT_RFTH
Definition: ald_uart.h:316
UART_IT_RFUERR
Definition: ald_uart.h:319
UART_IT_NOISE
Definition: ald_uart.h:315
UART_IT_ADDRM
Definition: ald_uart.h:312
UART_IT_RFOERR
Definition: ald_uart.h:318
UART_IT_ABEND
Definition: ald_uart.h:308

◆ uart_lin_break_len_t

enum uart_lin_break_len_t

LIN detection break length.

Enumerator
LIN_BREAK_LEN_10B | 10-bit break
LIN_BREAK_LEN_11B | 11-bit break

Definition at line 240 of file ald_uart.h.

240 {
241 LIN_BREAK_LEN_10B = 0x0U,
242 LIN_BREAK_LEN_11B = 0x1U,
243 } uart_lin_break_len_t;
uart_lin_break_len_t
uart_lin_break_len_t
LIN detection break length.
Definition: ald_uart.h:240
LIN_BREAK_LEN_11B
Definition: ald_uart.h:242
LIN_BREAK_LEN_10B
Definition: ald_uart.h:241

◆ uart_mode_t

enum uart_mode_t

UART mode.

Enumerator
UART_MODE_UART | UART
UART_MODE_LIN | LIN
UART_MODE_IrDA | IrDA
UART_MODE_RS485 | RS485
UART_MODE_HDSEL | Single-wire half-duplex
UART_MODE_SCARD | Smart card

Definition at line 112 of file ald_uart.h.

112 {
113 UART_MODE_UART = 0x0U,
114 UART_MODE_LIN = 0x1U,
115 UART_MODE_IrDA = 0x2U,
116 UART_MODE_RS485 = 0x3U,
117 UART_MODE_HDSEL = 0x4U,
118 UART_MODE_SCARD = 0x5U,
119 } uart_mode_t;
uart_mode_t
uart_mode_t
UART mode.
Definition: ald_uart.h:112
UART_MODE_LIN
Definition: ald_uart.h:114
UART_MODE_SCARD
Definition: ald_uart.h:118
UART_MODE_IrDA
Definition: ald_uart.h:115
UART_MODE_HDSEL
Definition: ald_uart.h:117
UART_MODE_RS485
Definition: ald_uart.h:116
UART_MODE_UART
Definition: ald_uart.h:113

◆ uart_parity_t

enum uart_parity_t

UART parity.

Enumerator
UART_PARITY_NONE | Not parity
UART_PARITY_ODD | Odd parity
UART_PARITY_EVEN | Even parity

Definition at line 103 of file ald_uart.h.

103 {
104 UART_PARITY_NONE = 0x0U,
105 UART_PARITY_ODD = 0x1U,
106 UART_PARITY_EVEN = 0x3U,
107 } uart_parity_t;
UART_PARITY_EVEN
Definition: ald_uart.h:106
uart_parity_t
uart_parity_t
UART parity.
Definition: ald_uart.h:103
UART_PARITY_ODD
Definition: ald_uart.h:105
UART_PARITY_NONE
Definition: ald_uart.h:104

◆ uart_rxfifo_t

enum uart_rxfifo_t

UART RXFIFO size.

Enumerator
UART_RXFIFO_1BYTE | 1-Byte
UART_RXFIFO_4BYTE | 4-Bytes
UART_RXFIFO_8BYTE | 8-Bytes
UART_RXFIFO_14BYTE | 14-Bytes

Definition at line 258 of file ald_uart.h.

258 {
259 UART_RXFIFO_1BYTE = 0x0U,
260 UART_RXFIFO_4BYTE = 0x1U,
261 UART_RXFIFO_8BYTE = 0x2U,
262 UART_RXFIFO_14BYTE = 0x3U,
263 } uart_rxfifo_t;
UART_RXFIFO_1BYTE
Definition: ald_uart.h:259
UART_RXFIFO_4BYTE
Definition: ald_uart.h:260
UART_RXFIFO_8BYTE
Definition: ald_uart.h:261
UART_RXFIFO_14BYTE
Definition: ald_uart.h:262
uart_rxfifo_t
uart_rxfifo_t
UART RXFIFO size.
Definition: ald_uart.h:258

◆ uart_state_t

enum uart_state_t

ALD UART state.

Enumerator
UART_STATE_RESET | Peripheral is not initialized
UART_STATE_READY | Peripheral Initialized and ready for use
UART_STATE_BUSY | an internal process is ongoing
UART_STATE_BUSY_TX | Data Transmission process is ongoing
UART_STATE_BUSY_RX | Data Reception process is ongoing
UART_STATE_BUSY_TX_RX | Data Transmission Reception process is ongoing
UART_STATE_TIMEOUT | Timeout state
UART_STATE_ERROR | Error

Definition at line 132 of file ald_uart.h.

132 {
133 UART_STATE_RESET = 0x00U,
134 UART_STATE_READY = 0x01U,
135 UART_STATE_BUSY = 0x02U,
136 UART_STATE_BUSY_TX = 0x11U,
137 UART_STATE_BUSY_RX = 0x21U,
138 UART_STATE_BUSY_TX_RX = 0x31U,
139 UART_STATE_TIMEOUT = 0x03U,
140 UART_STATE_ERROR = 0x04U,
141 } uart_state_t;
UART_STATE_BUSY_TX
Definition: ald_uart.h:136
UART_STATE_READY
Definition: ald_uart.h:134
UART_STATE_TIMEOUT
Definition: ald_uart.h:139
uart_state_t
uart_state_t
ALD UART state.
Definition: ald_uart.h:132
UART_STATE_RESET
Definition: ald_uart.h:133
UART_STATE_BUSY_TX_RX
Definition: ald_uart.h:138
UART_STATE_BUSY
Definition: ald_uart.h:135
UART_STATE_ERROR
Definition: ald_uart.h:140
UART_STATE_BUSY_RX
Definition: ald_uart.h:137

◆ uart_status_t

enum uart_status_t

UART status types.

Enumerator
UART_STATUS_PERR | Parity error
UART_STATUS_FERR | Framing error
UART_STATUS_BKERR | Break error
UART_STATUS_CTSSTA | Clear to send status
UART_STATUS_RSBUSY | Receive shif register busy
UART_STATUS_RFTH | Receive FIFO trigger threshold
UART_STATUS_RFEMPTY | Receive FIFO empty
UART_STATUS_RFFULL | Receive FIFO full
UART_STATUS_RFOERR | Reveive FIFO overrun error
UART_STATUS_RFUERR | Receive FIFO underrun error
UART_STATUS_TSBUSY | Transmit shit register busy
UART_STATUS_TFTH | Transmit FIFO trigger threshold
UART_STATUS_TFEMPTY | Transmit FIFO empty
UART_STATUS_TFFULL | Transmit FIFO full
UART_STATUS_TFOERR | Transmit FIFO overrun error

Definition at line 285 of file ald_uart.h.

285 {
286 UART_STATUS_PERR = (1U << 0),
287 UART_STATUS_FERR = (1U << 1),
288 UART_STATUS_BKERR = (1U << 2),
289 UART_STATUS_CTSSTA = (1U << 3),
290 UART_STATUS_RSBUSY = (1U << 8),
291 UART_STATUS_RFTH = (1U << 9),
292 UART_STATUS_RFEMPTY = (1U << 10),
293 UART_STATUS_RFFULL = (1U << 11),
294 UART_STATUS_RFOERR = (1U << 12),
295 UART_STATUS_RFUERR = (1U << 13),
296 UART_STATUS_TSBUSY = (1U << 14),
297 UART_STATUS_TFTH = (1U << 15),
298 UART_STATUS_TFEMPTY = (1U << 16),
299 UART_STATUS_TFFULL = (1U << 17),
300 UART_STATUS_TFOERR = (1U << 18),
301 } uart_status_t;
UART_STATUS_TFOERR
Definition: ald_uart.h:300
UART_STATUS_RFEMPTY
Definition: ald_uart.h:292
UART_STATUS_RFFULL
Definition: ald_uart.h:293
UART_STATUS_TFTH
Definition: ald_uart.h:297
UART_STATUS_TSBUSY
Definition: ald_uart.h:296
UART_STATUS_RSBUSY
Definition: ald_uart.h:290
UART_STATUS_TFEMPTY
Definition: ald_uart.h:298
UART_STATUS_FERR
Definition: ald_uart.h:287
UART_STATUS_RFTH
Definition: ald_uart.h:291
uart_status_t
uart_status_t
UART status types.
Definition: ald_uart.h:285
UART_STATUS_BKERR
Definition: ald_uart.h:288
UART_STATUS_RFOERR
Definition: ald_uart.h:294
UART_STATUS_CTSSTA
Definition: ald_uart.h:289
UART_STATUS_RFUERR
Definition: ald_uart.h:295
UART_STATUS_TFFULL
Definition: ald_uart.h:299
UART_STATUS_PERR
Definition: ald_uart.h:286

◆ uart_stop_bits_t

enum uart_stop_bits_t

UART stop bits.

Enumerator
UART_STOP_BITS_1 | 1-bits
UART_STOP_BITS_2 | 2-bits
UART_STOP_BITS_0_5 | 0.5-bits, using smartcard mode
UART_STOP_BITS_1_5 | 1.5-bits, using smartcard mode

Definition at line 93 of file ald_uart.h.

93 {
94 UART_STOP_BITS_1 = 0x0U,
95 UART_STOP_BITS_2 = 0x1U,
96 UART_STOP_BITS_0_5 = 0x0U,
97 UART_STOP_BITS_1_5 = 0x1U,
98 } uart_stop_bits_t;
UART_STOP_BITS_1_5
Definition: ald_uart.h:97
UART_STOP_BITS_1
Definition: ald_uart.h:94
uart_stop_bits_t
uart_stop_bits_t
UART stop bits.
Definition: ald_uart.h:93
UART_STOP_BITS_2
Definition: ald_uart.h:95
UART_STOP_BITS_0_5
Definition: ald_uart.h:96

◆ uart_txfifo_t

enum uart_txfifo_t

UART TXFIFO size.

Enumerator
UART_TXFIFO_EMPTY | Empty
UART_TXFIFO_2BYTE | 2-Bytes
UART_TXFIFO_4BYTE | 4-Bytes
UART_TXFIFO_8BYTE | 8-Bytes

Definition at line 248 of file ald_uart.h.

248 {
249 UART_TXFIFO_EMPTY = 0x0U,
250 UART_TXFIFO_2BYTE = 0x1U,
251 UART_TXFIFO_4BYTE = 0x2U,
252 UART_TXFIFO_8BYTE = 0x3U,
253 } uart_txfifo_t;
UART_TXFIFO_4BYTE
Definition: ald_uart.h:251
uart_txfifo_t
uart_txfifo_t
UART TXFIFO size.
Definition: ald_uart.h:248
UART_TXFIFO_8BYTE
Definition: ald_uart.h:252
UART_TXFIFO_2BYTE
Definition: ald_uart.h:250
UART_TXFIFO_EMPTY
Definition: ald_uart.h:249

◆ uart_word_length_t

enum uart_word_length_t

UART word length.

Enumerator
UART_WORD_LENGTH_8B | 8-bits
UART_WORD_LENGTH_7B | 7-bits
UART_WORD_LENGTH_6B | 6-bits
UART_WORD_LENGTH_5B | 5-bits

Definition at line 83 of file ald_uart.h.

83 {
84 UART_WORD_LENGTH_8B = 0x0U,
85 UART_WORD_LENGTH_7B = 0x1U,
86 UART_WORD_LENGTH_6B = 0x2U,
87 UART_WORD_LENGTH_5B = 0x3U,
88 } uart_word_length_t;
UART_WORD_LENGTH_8B
Definition: ald_uart.h:84
UART_WORD_LENGTH_6B
Definition: ald_uart.h:86
uart_word_length_t
uart_word_length_t
UART word length.
Definition: ald_uart.h:83
UART_WORD_LENGTH_5B
Definition: ald_uart.h:87
UART_WORD_LENGTH_7B
Definition: ald_uart.h:85


ALD User Manual: uart_init_t Struct Reference

Data Fields
uart_init_t Struct Reference
EASTSOFT ES32F3xx ALD » UART » UART Public Types

UART init structure definition. More...

#include <ald_uart.h>

Data Fields

uint32_t baud
uart_word_length_t word_length
uart_stop_bits_t stop_bits
uart_parity_t parity
uart_mode_t mode
uart_hw_flow_ctl_t fctl

Detailed Description

UART init structure definition.

Definition at line 158 of file ald_uart.h.

Field Documentation

◆ baud

uint32_t baud

Specifies the uart communication baud rate

Definition at line 159 of file ald_uart.h.

◆ fctl

uart_hw_flow_ctl_t fctl

Specifies wether the hardware flow control mode is enabled or disabled

Definition at line 164 of file ald_uart.h.

◆ mode

uart_mode_t mode

Specifies uart mode

Definition at line 163 of file ald_uart.h.

◆ parity

uart_parity_t parity

Specifies the parity mode

Definition at line 162 of file ald_uart.h.

◆ stop_bits

uart_stop_bits_t stop_bits

Specifies the number of stop bits transmitted

Definition at line 161 of file ald_uart.h.

◆ word_length

uart_word_length_t word_length

Specifies the number of data bits transmitted or received in a frame

Definition at line 160 of file ald_uart.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_uart.h


ALD User Manual: uart_handle_s Struct Reference

Data Fields
uart_handle_s Struct Reference
EASTSOFT ES32F3xx ALD » UART » UART Public Types

UART handle structure definition. More...

#include <ald_uart.h>

Collaboration diagram for uart_handle_s:
[legend]

Data Fields

UART_TypeDef * | perh
uart_init_t init
uint8_t * | tx_buf
uint16_t | tx_size
uint16_t | tx_count
uint8_t * | rx_buf
uint16_t | rx_size
uint16_t | rx_count
dma_handle_t hdmatx
dma_handle_t hdmarx
lock_state_t lock
uart_state_t state
uart_error_t err_code
void(* | tx_cplt_cbk )(struct uart_handle_s *arg)
void(* | rx_cplt_cbk )(struct uart_handle_s *arg)
void(* | error_cbk )(struct uart_handle_s *arg)

Detailed Description

UART handle structure definition.

Definition at line 170 of file ald_uart.h.

Field Documentation

◆ err_code

uart_error_t err_code

UART Error code

Definition at line 185 of file ald_uart.h.

◆ error_cbk

void(* error_cbk) (struct uart_handle_s *arg)

error callback

Definition at line 189 of file ald_uart.h.

◆ hdmarx

dma_handle_t hdmarx

UART Rx DMA Handle parameters

Definition at line 181 of file ald_uart.h.

◆ hdmatx

dma_handle_t hdmatx

UART Tx DMA Handle parameters

Definition at line 180 of file ald_uart.h.

◆ init

uart_init_t init

UART communication parameters

Definition at line 172 of file ald_uart.h.

◆ lock

lock_state_t lock

Locking object

Definition at line 183 of file ald_uart.h.

◆ perh

UART_TypeDef* perh

UART registers base address

Definition at line 171 of file ald_uart.h.

◆ rx_buf

uint8_t* rx_buf

Pointer to UART Rx transfer Buffer

Definition at line 176 of file ald_uart.h.

◆ rx_count

uint16_t rx_count

UART Rx Transfer Counter

Definition at line 178 of file ald_uart.h.

◆ rx_cplt_cbk

void(* rx_cplt_cbk) (struct uart_handle_s *arg)

Rx completed callback

Definition at line 188 of file ald_uart.h.

◆ rx_size

uint16_t rx_size

UART Rx Transfer size

Definition at line 177 of file ald_uart.h.

◆ state

uart_state_t state

UART communication state

Definition at line 184 of file ald_uart.h.

◆ tx_buf

uint8_t* tx_buf

Pointer to UART Tx transfer Buffer

Definition at line 173 of file ald_uart.h.

◆ tx_count

uint16_t tx_count

UART Tx Transfer Counter

Definition at line 175 of file ald_uart.h.

◆ tx_cplt_cbk

void(* tx_cplt_cbk) (struct uart_handle_s *arg)

Tx completed callback

Definition at line 187 of file ald_uart.h.

◆ tx_size

uint16_t tx_size

UART Tx Transfer size

Definition at line 174 of file ald_uart.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_uart.h


ALD User Manual: uart_rs485_config_t Struct Reference

Data Fields
uart_rs485_config_t Struct Reference
EASTSOFT ES32F3xx ALD » UART » UART Public Types

UART RS485 configure structure definition. More...

#include <ald_uart.h>

Data Fields

type_func_t normal
type_func_t dir
type_func_t invert
uint8_t addr

Detailed Description

UART RS485 configure structure definition.

Definition at line 195 of file ald_uart.h.

Field Documentation

◆ addr

uint8_t addr

Address for compare

Definition at line 199 of file ald_uart.h.

◆ dir

type_func_t dir

Auto-direction mode

Definition at line 197 of file ald_uart.h.

◆ invert

type_func_t invert

Address detection invert

Definition at line 198 of file ald_uart.h.

◆ normal

type_func_t normal

Normal mode

Definition at line 196 of file ald_uart.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_uart.h


ALD User Manual: uart_scard_config_t Struct Reference

Data Fields
uart_scard_config_t Struct Reference
EASTSOFT ES32F3xx ALD » UART » UART Public Types

UART Smart card configure structure definition. More...

#include <ald_uart.h>

Data Fields

uint8_t | block_len
uint8_t | pt
scard_retry_t retry
scard_clk_div_t clk_div
type_func_t clk_out

Detailed Description

UART Smart card configure structure definition.

Definition at line 229 of file ald_uart.h.

Field Documentation

◆ block_len

uint8_t block_len

Specifies the data block length.

Definition at line 230 of file ald_uart.h.

◆ clk_div

scard_clk_div_t clk_div

Specifies the clock division.

Definition at line 233 of file ald_uart.h.

◆ clk_out

type_func_t clk_out

Specifies the clock out

Definition at line 234 of file ald_uart.h.

◆ pt

uint8_t pt

Specifies the protect time

Definition at line 231 of file ald_uart.h.

◆ retry

scard_retry_t retry

Specifies retry time.

Definition at line 232 of file ald_uart.h.

The documentation for this struct was generated from the following file:
  • D:/svn/src/ald_uart.h


ALD User Manual: UART Private Macros

Macros
UART Private Macros
EASTSOFT ES32F3xx ALD » UART
Collaboration diagram for UART Private Macros:

Macros

#define | IS_UART_SCARD(x)
#define | IS_UART_ALL(x)
#define | IS_UART_WORD_LENGTH(x)
#define | IS_UART_STOPBITS(x)
#define | IS_UART_PARITY(x)
#define | IS_UART_MODE(x)
#define | IS_UART_HARDWARE_FLOW_CONTROL(x)
#define | IS_UART_LIN_BREAK_LEN(x)
#define | IS_UART_TXFIFO_TYPE(x)
#define | IS_UART_RXFIFO_TYPE(x)
#define | IS_UART_AUTO_BAUD_MODE(x)
#define | IS_UART_DMA_REQ(x)
#define | IS_UART_STATUS(x)
#define | IS_UART_IT(x)
#define | IS_UART_IF(x)
#define | IS_UART_SCARD_CLK(x)
#define | IS_UART_BAUDRATE(x) (((x) > 0) && ((x) < 0x44AA21))
#define | IS_UART_DATA(x) ((x) <= 0x1FF)
#define | UART_STATE_TX_MASK (1U << 4)
#define | UART_STATE_RX_MASK (1U << 5)

Detailed Description

Macro Definition Documentation

◆ IS_UART_ALL

#define IS_UART_ALL ( x )
Value:
(((x) == UART0) || \
((x) == UART1) || \
((x) == UART2) || \
((x) == UART3) || \
((x) == UART4) || \
((x) == UART5))

Definition at line 357 of file ald_uart.h.

◆ IS_UART_AUTO_BAUD_MODE

#define IS_UART_AUTO_BAUD_MODE ( x )
Value:
(((x) == UART_ABRMOD_1_TO_0) || \
((x) == UART_ABRMOD_1) || \
((x) == UART_ABRMOD_0_TO_1))
UART_ABRMOD_1_TO_0
Definition: ald_uart.h:269
UART_ABRMOD_0_TO_1
Definition: ald_uart.h:271
UART_ABRMOD_1
Definition: ald_uart.h:270

Definition at line 393 of file ald_uart.h.

◆ IS_UART_BAUDRATE

#define IS_UART_BAUDRATE ( x ) (((x) > 0) && ((x) < 0x44AA21))

Definition at line 451 of file ald_uart.h.

◆ IS_UART_DATA

#define IS_UART_DATA ( x ) ((x) <= 0x1FF)

Definition at line 452 of file ald_uart.h.

◆ IS_UART_DMA_REQ

#define IS_UART_DMA_REQ ( x )
Value:
(((x) == UART_DMA_REQ_TX) || \
((x) == UART_DMA_REQ_RX))
UART_DMA_REQ_TX
Definition: ald_uart.h:278
UART_DMA_REQ_RX
Definition: ald_uart.h:279

Definition at line 396 of file ald_uart.h.

◆ IS_UART_HARDWARE_FLOW_CONTROL

#define IS_UART_HARDWARE_FLOW_CONTROL ( x )
Value:
(((x) == UART_HW_FLOW_CTL_DISABLE) || \
((x) == UART_HW_FLOW_CTL_ENABLE))
UART_HW_FLOW_CTL_ENABLE
Definition: ald_uart.h:126
UART_HW_FLOW_CTL_DISABLE
Definition: ald_uart.h:125

Definition at line 380 of file ald_uart.h.

◆ IS_UART_IF

#define IS_UART_IF ( x )
Value:
(((x) == UART_IF_RXBERR) || \
((x) == UART_IF_ABEND) || \
((x) == UART_IF_ABTO) || \
((x) == UART_IF_DCTS) || \
((x) == UART_IF_RXTO) || \
((x) == UART_IF_ADDRM) || \
((x) == UART_IF_LINBK) || \
((x) == UART_IF_EOB) || \
((x) == UART_IF_NOISE) || \
((x) == UART_IF_RFTH) || \
((x) == UART_IF_RFFULL) || \
((x) == UART_IF_RFOERR) || \
((x) == UART_IF_RFUERR) || \
((x) == UART_IF_TBC) || \
((x) == UART_IF_TFTH) || \
((x) == UART_IF_TFEMPTY) || \
((x) == UART_IF_TFOVER))
UART_IF_ABTO
Definition: ald_uart.h:332
UART_IF_RXBERR
Definition: ald_uart.h:330
UART_IF_TFTH
Definition: ald_uart.h:344
UART_IF_RFTH
Definition: ald_uart.h:339
UART_IF_RFOERR
Definition: ald_uart.h:341
UART_IF_ADDRM
Definition: ald_uart.h:335
UART_IF_TFEMPTY
Definition: ald_uart.h:345
UART_IF_RFUERR
Definition: ald_uart.h:342
UART_IF_DCTS
Definition: ald_uart.h:333
UART_IF_RXTO
Definition: ald_uart.h:334
UART_IF_TBC
Definition: ald_uart.h:343
UART_IF_RFFULL
Definition: ald_uart.h:340
UART_IF_EOB
Definition: ald_uart.h:337
UART_IF_LINBK
Definition: ald_uart.h:336
UART_IF_TFOVER
Definition: ald_uart.h:346
UART_IF_NOISE
Definition: ald_uart.h:338
UART_IF_ABEND
Definition: ald_uart.h:331

Definition at line 430 of file ald_uart.h.

◆ IS_UART_IT

#define IS_UART_IT ( x )
Value:
(((x) == UART_IT_RXBERR) || \
((x) == UART_IT_ABEND) || \
((x) == UART_IT_ABTO) || \
((x) == UART_IT_DCTS) || \
((x) == UART_IT_RXTO) || \
((x) == UART_IT_ADDRM) || \
((x) == UART_IT_LINBK) || \
((x) == UART_IT_EOB) || \
((x) == UART_IT_NOISE) || \
((x) == UART_IT_RFTH) || \
((x) == UART_IT_RFFULL) || \
((x) == UART_IT_RFOERR) || \
((x) == UART_IT_RFUERR) || \
((x) == UART_IT_TSEMPTY) || \
((x) == UART_IT_TFTH) || \
((x) == UART_IT_TFEMPTY) || \
((x) == UART_IT_TFOVER))
UART_IT_DCTS
Definition: ald_uart.h:310
UART_IT_TFEMPTY
Definition: ald_uart.h:322
UART_IT_TSEMPTY
Definition: ald_uart.h:320
UART_IT_RFFULL
Definition: ald_uart.h:317
UART_IT_LINBK
Definition: ald_uart.h:313
UART_IT_RXBERR
Definition: ald_uart.h:307
UART_IT_ABTO
Definition: ald_uart.h:309
UART_IT_TFOVER
Definition: ald_uart.h:323
UART_IT_EOB
Definition: ald_uart.h:314
UART_IT_RXTO
Definition: ald_uart.h:311
UART_IT_TFTH
Definition: ald_uart.h:321
UART_IT_RFTH
Definition: ald_uart.h:316
UART_IT_RFUERR
Definition: ald_uart.h:319
UART_IT_NOISE
Definition: ald_uart.h:315
UART_IT_ADDRM
Definition: ald_uart.h:312
UART_IT_RFOERR
Definition: ald_uart.h:318
UART_IT_ABEND
Definition: ald_uart.h:308

Definition at line 413 of file ald_uart.h.

◆ IS_UART_LIN_BREAK_LEN

#define IS_UART_LIN_BREAK_LEN ( x )
Value:
(((x) == LIN_BREAK_LEN_10B) || \
((x) == LIN_BREAK_LEN_11B))
LIN_BREAK_LEN_11B
Definition: ald_uart.h:242
LIN_BREAK_LEN_10B
Definition: ald_uart.h:241

Definition at line 383 of file ald_uart.h.

◆ IS_UART_MODE

#define IS_UART_MODE ( x )
Value:
(((x) == UART_MODE_UART) || \
((x) == UART_MODE_LIN) || \
((x) == UART_MODE_IrDA) || \
((x) == UART_MODE_HDSEL) || \
((x) == UART_MODE_SCARD) || \
((x) == UART_MODE_RS485))
UART_MODE_LIN
Definition: ald_uart.h:114
UART_MODE_SCARD
Definition: ald_uart.h:118
UART_MODE_IrDA
Definition: ald_uart.h:115
UART_MODE_HDSEL
Definition: ald_uart.h:117
UART_MODE_RS485
Definition: ald_uart.h:116
UART_MODE_UART
Definition: ald_uart.h:113

Definition at line 374 of file ald_uart.h.

◆ IS_UART_PARITY

#define IS_UART_PARITY ( x )
Value:
(((x) == UART_PARITY_NONE) || \
((x) == UART_PARITY_ODD) || \
((x) == UART_PARITY_EVEN))
UART_PARITY_EVEN
Definition: ald_uart.h:106
UART_PARITY_ODD
Definition: ald_uart.h:105
UART_PARITY_NONE
Definition: ald_uart.h:104

Definition at line 371 of file ald_uart.h.

◆ IS_UART_RXFIFO_TYPE

#define IS_UART_RXFIFO_TYPE ( x )
Value:
(((x) == UART_RXFIFO_1BYTE) || \
((x) == UART_RXFIFO_4BYTE) || \
((x) == UART_RXFIFO_8BYTE) || \
((x) == UART_RXFIFO_14BYTE))
UART_RXFIFO_1BYTE
Definition: ald_uart.h:259
UART_RXFIFO_4BYTE
Definition: ald_uart.h:260
UART_RXFIFO_8BYTE
Definition: ald_uart.h:261
UART_RXFIFO_14BYTE
Definition: ald_uart.h:262

Definition at line 389 of file ald_uart.h.

◆ IS_UART_SCARD

#define IS_UART_SCARD ( x )
Value:
(((x) == UART4) || \
((x) == UART5))

Definition at line 355 of file ald_uart.h.

◆ IS_UART_SCARD_CLK

#define IS_UART_SCARD_CLK ( x )
Value:
(((x) == SCARD_CLOCK_DIV1) || \
((x) == SCARD_CLOCK_DIV2) || \
((x) == SCARD_CLOCK_DIV4) || \
((x) == SCARD_CLOCK_DIV6))
SCARD_CLOCK_DIV2
Definition: ald_uart.h:207
SCARD_CLOCK_DIV1
Definition: ald_uart.h:206
SCARD_CLOCK_DIV6
Definition: ald_uart.h:209
SCARD_CLOCK_DIV4
Definition: ald_uart.h:208

Definition at line 447 of file ald_uart.h.

◆ IS_UART_STATUS

#define IS_UART_STATUS ( x )
Value:
(((x) == UART_STATUS_PERR) || \
((x) == UART_STATUS_FERR) || \
((x) == UART_STATUS_BKERR) || \
((x) == UART_STATUS_CTSSTA) || \
((x) == UART_STATUS_RSBUSY) || \
((x) == UART_STATUS_RFEMPTY) || \
((x) == UART_STATUS_RFFULL) || \
((x) == UART_STATUS_RFOERR) || \
((x) == UART_STATUS_RFUERR) || \
((x) == UART_STATUS_TSBUSY) || \
((x) == UART_STATUS_RFTH) || \
((x) == UART_STATUS_TFTH) || \
((x) == UART_STATUS_TFEMPTY) || \
((x) == UART_STATUS_TFFULL) || \
((x) == UART_STATUS_TFOERR))
UART_STATUS_TFOERR
Definition: ald_uart.h:300
UART_STATUS_RFEMPTY
Definition: ald_uart.h:292
UART_STATUS_RFFULL
Definition: ald_uart.h:293
UART_STATUS_TFTH
Definition: ald_uart.h:297
UART_STATUS_TSBUSY
Definition: ald_uart.h:296
UART_STATUS_RSBUSY
Definition: ald_uart.h:290
UART_STATUS_TFEMPTY
Definition: ald_uart.h:298
UART_STATUS_FERR
Definition: ald_uart.h:287
UART_STATUS_RFTH
Definition: ald_uart.h:291
UART_STATUS_BKERR
Definition: ald_uart.h:288
UART_STATUS_RFOERR
Definition: ald_uart.h:294
UART_STATUS_CTSSTA
Definition: ald_uart.h:289
UART_STATUS_RFUERR
Definition: ald_uart.h:295
UART_STATUS_TFFULL
Definition: ald_uart.h:299
UART_STATUS_PERR
Definition: ald_uart.h:286

Definition at line 398 of file ald_uart.h.

◆ IS_UART_STOPBITS

#define IS_UART_STOPBITS ( x )
Value:
(((x) == UART_STOP_BITS_1) || \
((x) == UART_STOP_BITS_2) || \
((x) == UART_STOP_BITS_0_5) || \
((x) == UART_STOP_BITS_1_5))
UART_STOP_BITS_1_5
Definition: ald_uart.h:97
UART_STOP_BITS_1
Definition: ald_uart.h:94
UART_STOP_BITS_2
Definition: ald_uart.h:95
UART_STOP_BITS_0_5
Definition: ald_uart.h:96

Definition at line 367 of file ald_uart.h.

◆ IS_UART_TXFIFO_TYPE

#define IS_UART_TXFIFO_TYPE ( x )
Value:
(((x) == UART_TXFIFO_EMPTY) || \
((x) == UART_TXFIFO_2BYTE) || \
((x) == UART_TXFIFO_4BYTE) || \
((x) == UART_TXFIFO_8BYTE))
UART_TXFIFO_4BYTE
Definition: ald_uart.h:251
UART_TXFIFO_8BYTE
Definition: ald_uart.h:252
UART_TXFIFO_2BYTE
Definition: ald_uart.h:250
UART_TXFIFO_EMPTY
Definition: ald_uart.h:249

Definition at line 385 of file ald_uart.h.

◆ IS_UART_WORD_LENGTH

#define IS_UART_WORD_LENGTH ( x )
Value:
(((x) == UART_WORD_LENGTH_5B) || \
((x) == UART_WORD_LENGTH_6B) || \
((x) == UART_WORD_LENGTH_7B) || \
((x) == UART_WORD_LENGTH_8B))
UART_WORD_LENGTH_8B
Definition: ald_uart.h:84
UART_WORD_LENGTH_6B
Definition: ald_uart.h:86
UART_WORD_LENGTH_5B
Definition: ald_uart.h:87
UART_WORD_LENGTH_7B
Definition: ald_uart.h:85

Definition at line 363 of file ald_uart.h.

◆ UART_STATE_RX_MASK

#define UART_STATE_RX_MASK (1U << 5)

Definition at line 455 of file ald_uart.h.

◆ UART_STATE_TX_MASK

#define UART_STATE_TX_MASK (1U << 4)

Definition at line 454 of file ald_uart.h.


ALD User Manual: USB

Modules
USB
EASTSOFT ES32F3xx ALD

USB module driver. More...

Collaboration diagram for USB:

Modules

USB Public Function
USB Public Macros

Detailed Description

USB module driver.


ALD User Manual: USB Public Function

Modules
USB Public Function
EASTSOFT ES32F3xx ALD » USB
Collaboration diagram for USB Public Function:

Modules

Base functions
Base functions.
Device functions
Device functions.
Host functions
Host functions.
Endpoint functions
Endpoint functions.
FIFO functions
FIFO functions.
Interrupt functions
Interrupt functions.
DMA functions
DMA functions.
LPM functions
LPM functions.

Detailed Description


ALD User Manual: Base functions

Functions
Base functions
EASTSOFT ES32F3xx ALD » USB » USB Public Function

Base functions. More...

Collaboration diagram for Base functions:

Functions

uint32_t | ald_usb_frame_number_get (void)
Gets the number of current frame. More...
void | ald_usb_otg_session_request (bool start)
Request the session. More...
uint32_t | ald_usb_mode_get (void)
Gets the mode. More...
void | ald_usb_high_speed_enable (bool enable)
Enable/Disable the high mode. More...
uint32_t | ald_usb_device_speed_get (void)
Gets the speed of the device. More...
uint32_t | ald_usb_num_ep_get (void)
Gets the number of the endpoint. More...
void | ald_usb_control_reset (void)
Reset USB Control. More...
void | ald_usb_clock_output (void)
Output USB clock via PA15, 60MHz/256=234.375KHz. More...
int | ald_usb_eye_diagram_start (uint8_t *buf, uint16_t len)
Starts eye diagram for high-speed host. More...

Detailed Description

Base functions.

Function Documentation

◆ ald_usb_clock_output()

void ald_usb_clock_output ( void )

Output USB clock via PA15, 60MHz/256=234.375KHz.

Return values
None

Definition at line 117 of file ald_usb.c.

118 {
119 SYSCFG_UNLOCK();
120 SYSCFG->TESTKEY = 0x5A962814;
121 SYSCFG->TESTKEY = 0xE7CB69A5;
122 SYSCFG->USBTEST = 0x43;
123
124 return;
125 }
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40

◆ ald_usb_control_reset()

void ald_usb_control_reset ( void )

Reset USB Control.

Return values
None

Definition at line 108 of file ald_usb.c.

109 {
110 ald_rmu_reset_periperal(RMU_PERH_USB);
111 }
ald_rmu_reset_periperal
void ald_rmu_reset_periperal(rmu_peripheral_t perh)
Reset peripheral device.
Definition: ald_rmu.c:101
RMU_PERH_USB
Definition: ald_rmu.h:125

◆ ald_usb_device_speed_get()

uint32_t ald_usb_device_speed_get ( void )

Gets the speed of the device.

Return values
Type of the speed.

Definition at line 87 of file ald_usb.c.

88 {
89 if (USB0->POWER & USB_POWER_HS_EN)
90 return USB_HIGH_SPEED;
91
92 return USB_FULL_SPEED;
93 }
USB_HIGH_SPEED
#define USB_HIGH_SPEED
Definition: ald_usb.h:242
USB_POWER_HS_EN
#define USB_POWER_HS_EN
Definition: ald_usb.h:43
USB_FULL_SPEED
#define USB_FULL_SPEED
Definition: ald_usb.h:243

◆ ald_usb_eye_diagram_start()

int ald_usb_eye_diagram_start | ( | uint8_t * | buf,
 |  | uint16_t | len
 | ) |  |

Starts eye diagram for high-speed host.

Parameters
buf | Buffer for eye diagram.
len | Length of the buffer.
Return values
Status,0 means success, other values means failure.

Definition at line 133 of file ald_usb.c.

134 {
135 if (len < 53)
136 return -1;
137
138 ald_usb_ep_data_put(0, buf, 53);
139 USB0->TEST = 0x08 | 0x90;
140 ald_delay_ms(20);
141 USB0->CSR0L = USB_CSRL0_TXRDY;
142
143 return 0;
144 }
ald_usb_ep_data_put
int32_t ald_usb_ep_data_put(uint32_t ep_idx, uint8_t *data, uint32_t size)
Puts data to the FIFO.
Definition: ald_usb.c:797
USB_CSRL0_TXRDY
#define USB_CSRL0_TXRDY
Definition: ald_usb.h:121
ald_delay_ms
__weak void ald_delay_ms(__IO uint32_t delay)
This function provides accurate delay (in milliseconds) based on variable incremented.
Definition: utils.c:247

◆ ald_usb_frame_number_get()

uint32_t ald_usb_frame_number_get ( void )

Gets the number of current frame.

Return values
Number of the frame.

Definition at line 42 of file ald_usb.c.

43 {
44 return USB0->FRAME;
45 }

◆ ald_usb_high_speed_enable()

void ald_usb_high_speed_enable ( bool enable )

Enable/Disable the high mode.

Parameters
enable ENABLE/DISABLE.
Return values
None

Definition at line 75 of file ald_usb.c.

76 {
77 if (enable)
78 USB0->POWER |= USB_POWER_HS_EN;
79 else
80 USB0->POWER &= ~(USB_POWER_HS_EN);
81 }
USB_POWER_HS_EN
#define USB_POWER_HS_EN
Definition: ald_usb.h:43

◆ ald_usb_mode_get()

uint32_t ald_usb_mode_get ( void )

Gets the mode.

Return values
Mode

Definition at line 64 of file ald_usb.c.

65 {
66 return USB0->DEVCTL & (USB_DEVCTL_DEV | USB_DEVCTL_HOST
67 | USB_DEVCTL_SESSION | USB_DEVCTL_VBUS_M);
68 }
USB_DEVCTL_DEV
#define USB_DEVCTL_DEV
Definition: ald_usb.h:50
USB_DEVCTL_VBUS_M
#define USB_DEVCTL_VBUS_M
Definition: ald_usb.h:53
USB_DEVCTL_SESSION
#define USB_DEVCTL_SESSION
Definition: ald_usb.h:60
USB_DEVCTL_HOST
#define USB_DEVCTL_HOST
Definition: ald_usb.h:58

◆ ald_usb_num_ep_get()

uint32_t ald_usb_num_ep_get ( void )

Gets the number of the endpoint.

Return values
Number of the endpoint.

Definition at line 99 of file ald_usb.c.

100 {
101 return NUM_USB_EP;
102 }
NUM_USB_EP
#define NUM_USB_EP
Definition: ald_usb.h:353

◆ ald_usb_otg_session_request()

void ald_usb_otg_session_request ( bool start )

Request the session.

Parameters
start true/false.
Return values
None

Definition at line 52 of file ald_usb.c.

53 {
54 if (start)
55 USB0->DEVCTL |= USB_DEVCTL_SESSION;
56 else
57 USB0->DEVCTL &= ~(USB_DEVCTL_SESSION);
58 }
USB_DEVCTL_SESSION
#define USB_DEVCTL_SESSION
Definition: ald_usb.h:60


ALD User Manual: Device functions

Functions
Device functions
EASTSOFT ES32F3xx ALD » USB » USB Public Function

Device functions. More...

Collaboration diagram for Device functions:

Functions

uint8_t | ald_usb_dev_get_addr (void)
Gets the address. More...
void | ald_usb_dev_set_addr (uint8_t addr)
Sets the address. More...
void | ald_usb_dev_connect (void)
Enable connection. More...
void | ald_usb_dev_disconnect (void)
Disable connection. More...
void | ald_usb_dev_ep_config (uint32_t ep_idx, uint32_t p_max, uint32_t flags)
Configure the endpoint in device mode. More...
void | ald_usb_dev_ep_get_config (uint32_t ep_idx, uint32_t *p_max, uint32_t *flags)
Gets the parameters of the endpoint. More...
void | ald_usb_dev_ep_data_ack (uint32_t ep_idx, bool last)
Acknowledge the data from the host. More...
void | ald_usb_dev_ep_stall (uint32_t ep_idx, uint32_t flags)
Stall the endpoint. More...
void | ald_usb_dev_ep_stall_clear (uint32_t ep_idx, uint32_t flags)
Cancel the stall status. More...
void | ald_usb_dev_ep_status_clear (uint32_t ep_idx, uint32_t flags)
Clear the status of the endpoint. More...

Detailed Description

Device functions.

Function Documentation

◆ ald_usb_dev_connect()

void ald_usb_dev_connect ( void )

Enable connection.

Return values
None

Definition at line 177 of file ald_usb.c.

178 {
179 USB0->POWER |= USB_POWER_SOFTCONN;
180 }
USB_POWER_SOFTCONN
#define USB_POWER_SOFTCONN
Definition: ald_usb.h:42

◆ ald_usb_dev_disconnect()

void ald_usb_dev_disconnect ( void )

Disable connection.

Return values
None

Definition at line 186 of file ald_usb.c.

187 {
188 USB0->POWER &= ~(USB_POWER_SOFTCONN);
189 }
USB_POWER_SOFTCONN
#define USB_POWER_SOFTCONN
Definition: ald_usb.h:42

◆ ald_usb_dev_ep_config()

void ald_usb_dev_ep_config | ( | uint32_t | ep_idx,
 |  | uint32_t | p_max,
 |  | uint32_t | flags
 | ) |  |

Configure the endpoint in device mode.

Parameters
ep_idx | Index of the endpoint
p_max | Size of the maximum package.
flags | Flags of the endpoint.
Return values
None

Definition at line 198 of file ald_usb.c.

199 {
200 uint32_t tmp = 0;
201
202 if (flags & USB_EP_DEV_IN) {
203 USB0->CSR[ep_idx - 1].TXxMAXP = p_max;
204 if (flags & USB_EP_AUTO_SET)
205 tmp |= USB_TXCSRH1_AUTOSET;
206 if ((flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC)
207 tmp |= USB_TXCSRH1_ISO;
208
209 USB0->CSR[ep_idx - 1].TXxCSRH = (uint8_t)tmp;
210 USB0->CSR[ep_idx - 1].TXxCSRL = USB_TXCSRL1_CLRDT;
211 }
212 else {
213 USB0->CSR[ep_idx - 1].RXxMAXP = p_max;
214 if (flags & USB_EP_AUTO_CLEAR)
215 tmp = USB_RXCSRH1_AUTOCL;
216 if (flags & USB_EP_DIS_NYET)
217 tmp |= USB_RXCSRH1_DISNYET;
218
219 if ((flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC)
220 tmp |= USB_RXCSRH1_ISO;
221
222 USB0->CSR[ep_idx - 1].RXxCSRH = (uint8_t)tmp;
223 USB0->CSR[ep_idx - 1].RXxCSRL = USB_RXCSRL1_CLRDT;
224 }
225 }
USB_EP_DEV_IN
#define USB_EP_DEV_IN
Definition: ald_usb.h:313
USB_EP_AUTO_SET
#define USB_EP_AUTO_SET
Definition: ald_usb.h:295
USB_RXCSRH1_AUTOCL
#define USB_RXCSRH1_AUTOCL
Definition: ald_usb.h:62
USB_EP_DIS_NYET
#define USB_EP_DIS_NYET
Definition: ald_usb.h:300
USB_TXCSRH1_AUTOSET
#define USB_TXCSRH1_AUTOSET
Definition: ald_usb.h:78
USB_TXCSRH1_ISO
#define USB_TXCSRH1_ISO
Definition: ald_usb.h:79
USB_RXCSRH1_DISNYET
#define USB_RXCSRH1_DISNYET
Definition: ald_usb.h:66
USB_EP_MODE_MASK
#define USB_EP_MODE_MASK
Definition: ald_usb.h:307
USB_RXCSRL1_CLRDT
#define USB_RXCSRL1_CLRDT
Definition: ald_usb.h:98
USB_EP_AUTO_CLEAR
#define USB_EP_AUTO_CLEAR
Definition: ald_usb.h:297
USB_TXCSRL1_CLRDT
#define USB_TXCSRL1_CLRDT
Definition: ald_usb.h:88
USB_RXCSRH1_ISO
#define USB_RXCSRH1_ISO
Definition: ald_usb.h:64
USB_EP_MODE_ISOC
#define USB_EP_MODE_ISOC
Definition: ald_usb.h:303

◆ ald_usb_dev_ep_data_ack()

void ald_usb_dev_ep_data_ack | ( | uint32_t | ep_idx,
 |  | bool | last
 | ) |  |

Acknowledge the data from the host.

Parameters
ep_idx | Index of the endpoint
last | true/false
Return values
None

Definition at line 270 of file ald_usb.c.

271 {
272 if (ep_idx == USB_EP_0)
273 USB0->CSR0L = USB_CSRL0_RXRDYC | (last ? USB_CSRL0_DATAEND : 0);
274 else
275 USB0->CSR[ep_idx - 1].RXxCSRL &= ~(USB_RXCSRL1_RXRDY);
276 }
USB_CSRL0_RXRDYC
#define USB_CSRL0_RXRDYC
Definition: ald_usb.h:113
USB_EP_0
#define USB_EP_0
Definition: ald_usb.h:347
USB_RXCSRL1_RXRDY
#define USB_RXCSRL1_RXRDY
Definition: ald_usb.h:108
USB_CSRL0_DATAEND
#define USB_CSRL0_DATAEND
Definition: ald_usb.h:118

◆ ald_usb_dev_ep_get_config()

void ald_usb_dev_ep_get_config | ( | uint32_t | ep_idx,
 |  | uint32_t * | p_max,
 |  | uint32_t * | flags
 | ) |  |

Gets the parameters of the endpoint.

Parameters
ep_idx | Index of the endpoint
p_max | Size of the maximum package.
flags | Flags of the endpoint.
Return values
None

Definition at line 234 of file ald_usb.c.

235 {
236 uint32_t tmp;
237
238 if (*flags & USB_EP_DEV_IN) {
239 *flags = USB_EP_DEV_IN;
240 *p_max = (uint32_t)USB0->CSR[ep_idx - 1].TXxMAXP;
241 tmp = (uint32_t)USB0->CSR[ep_idx - 1].TXxCSRH;
242
243 if (tmp & USB_TXCSRH1_AUTOSET)
244 *flags |= USB_EP_AUTO_SET;
245 if (tmp & USB_TXCSRH1_ISO)
246 *flags |= USB_EP_MODE_ISOC;
247 else
248 *flags |= USB_EP_MODE_BULK;
249 }
250 else {
251 *flags = USB_EP_DEV_OUT;
252 *p_max = (uint32_t)USB0->CSR[ep_idx - 1].RXxMAXP;
253 tmp = (uint32_t)USB0->CSR[ep_idx - 1].RXxCSRH;
254
255 if (tmp & USB_RXCSRH1_AUTOCL)
256 *flags |= USB_EP_AUTO_CLEAR;
257 if (tmp & USB_RXCSRH1_ISO)
258 *flags |= USB_EP_MODE_ISOC;
259 else
260 *flags |= USB_EP_MODE_BULK;
261 }
262 }
USB_EP_DEV_IN
#define USB_EP_DEV_IN
Definition: ald_usb.h:313
USB_EP_DEV_OUT
#define USB_EP_DEV_OUT
Definition: ald_usb.h:314
USB_EP_AUTO_SET
#define USB_EP_AUTO_SET
Definition: ald_usb.h:295
USB_RXCSRH1_AUTOCL
#define USB_RXCSRH1_AUTOCL
Definition: ald_usb.h:62
USB_TXCSRH1_AUTOSET
#define USB_TXCSRH1_AUTOSET
Definition: ald_usb.h:78
USB_TXCSRH1_ISO
#define USB_TXCSRH1_ISO
Definition: ald_usb.h:79
USB_EP_AUTO_CLEAR
#define USB_EP_AUTO_CLEAR
Definition: ald_usb.h:297
USB_RXCSRH1_ISO
#define USB_RXCSRH1_ISO
Definition: ald_usb.h:64
USB_EP_MODE_ISOC
#define USB_EP_MODE_ISOC
Definition: ald_usb.h:303
USB_EP_MODE_BULK
#define USB_EP_MODE_BULK
Definition: ald_usb.h:304

◆ ald_usb_dev_ep_stall()

void ald_usb_dev_ep_stall | ( | uint32_t | ep_idx,
 |  | uint32_t | flags
 | ) |  |

Stall the endpoint.

Parameters
ep_idx | Index of the endpoint
flags | Flags.
Return values
None

Definition at line 284 of file ald_usb.c.

285 {
286 if (ep_idx == USB_EP_0)
287 USB0->CSR0L |= (USB_CSRL0_STALL | USB_CSRL0_RXRDYC);
288 else if (flags == USB_EP_DEV_IN)
289 USB0->CSR[ep_idx - 1].TXxCSRL |= USB_TXCSRL1_STALL;
290 else
291 USB0->CSR[ep_idx - 1].RXxCSRL |= USB_RXCSRL1_STALL;
292 }
USB_CSRL0_RXRDYC
#define USB_CSRL0_RXRDYC
Definition: ald_usb.h:113
USB_EP_DEV_IN
#define USB_EP_DEV_IN
Definition: ald_usb.h:313
USB_RXCSRL1_STALL
#define USB_RXCSRL1_STALL
Definition: ald_usb.h:100
USB_EP_0
#define USB_EP_0
Definition: ald_usb.h:347
USB_TXCSRL1_STALL
#define USB_TXCSRL1_STALL
Definition: ald_usb.h:90
USB_CSRL0_STALL
#define USB_CSRL0_STALL
Definition: ald_usb.h:115

◆ ald_usb_dev_ep_stall_clear()

void ald_usb_dev_ep_stall_clear | ( | uint32_t | ep_idx,
 |  | uint32_t | flags
 | ) |  |

Cancel the stall status.

Parameters
ep_idx | Index of the endpoint
flags | Flags.
Return values
None

Definition at line 300 of file ald_usb.c.

301 {
302 if (ep_idx == USB_EP_0)
303 USB0->CSR0L &= ~USB_CSRL0_STALLED;
304 else if (flags == USB_EP_DEV_IN) {
305 USB0->CSR[ep_idx - 1].TXxCSRL &= ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED);
306 USB0->CSR[ep_idx - 1].TXxCSRL |= USB_TXCSRL1_CLRDT;
307 }
308 else {
309 USB0->CSR[ep_idx - 1].RXxCSRL &= ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED);
310 USB0->CSR[ep_idx - 1].RXxCSRL |= USB_RXCSRL1_CLRDT;
311 }
312 }
USB_CSRL0_STALLED
#define USB_CSRL0_STALLED
Definition: ald_usb.h:120
USB_EP_DEV_IN
#define USB_EP_DEV_IN
Definition: ald_usb.h:313
USB_RXCSRL1_STALL
#define USB_RXCSRL1_STALL
Definition: ald_usb.h:100
USB_EP_0
#define USB_EP_0
Definition: ald_usb.h:347
USB_TXCSRL1_STALL
#define USB_TXCSRL1_STALL
Definition: ald_usb.h:90
USB_RXCSRL1_CLRDT
#define USB_RXCSRL1_CLRDT
Definition: ald_usb.h:98
USB_TXCSRL1_CLRDT
#define USB_TXCSRL1_CLRDT
Definition: ald_usb.h:88
USB_TXCSRL1_STALLED
#define USB_TXCSRL1_STALLED
Definition: ald_usb.h:89
USB_RXCSRL1_STALLED
#define USB_RXCSRL1_STALLED
Definition: ald_usb.h:99

◆ ald_usb_dev_ep_status_clear()

void ald_usb_dev_ep_status_clear | ( | uint32_t | ep_idx,
 |  | uint32_t | flags
 | ) |  |

Clear the status of the endpoint.

Parameters
ep_idx | Index of the endpoint
flags | Flags.
Return values
None

Definition at line 320 of file ald_usb.c.

321 {
322 if (ep_idx == USB_EP_0) {
323 if (flags & USB_DEV_EP0_OUT_PKTRDY)
324 USB0->CSR0L |= USB_CSRL0_RXRDYC;
325 if (flags & USB_DEV_EP0_SETUP_END)
326 USB0->CSR0L |= USB_CSRL0_SETENDC;
327 if (flags & USB_DEV_EP0_SENT_STALL)
328 USB0->CSR0L &= ~(USB_DEV_EP0_SENT_STALL);
329 }
330 else {
331 USB0->CSR[ep_idx - 1].TXxCSRL &= ~(flags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN));
332 USB0->CSR[ep_idx - 1].RXxCSRL &= ~((flags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR
333 | USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT);
334 }
335 }
USB_CSRL0_RXRDYC
#define USB_CSRL0_RXRDYC
Definition: ald_usb.h:113
USB_EP_0
#define USB_EP_0
Definition: ald_usb.h:347
USB_RX_EPSTATUS_SHIFT
#define USB_RX_EPSTATUS_SHIFT
Definition: ald_usb.h:409
USB_DEV_EP0_OUT_PKTRDY
#define USB_DEV_EP0_OUT_PKTRDY
Definition: ald_usb.h:293
USB_DEV_TX_SENT_STALL
#define USB_DEV_TX_SENT_STALL
Definition: ald_usb.h:285
USB_DEV_EP0_SETUP_END
#define USB_DEV_EP0_SETUP_END
Definition: ald_usb.h:289
USB_DEV_RX_OVERRUN
#define USB_DEV_RX_OVERRUN
Definition: ald_usb.h:279
USB_DEV_TX_UNDERRUN
#define USB_DEV_TX_UNDERRUN
Definition: ald_usb.h:286
USB_CSRL0_SETENDC
#define USB_CSRL0_SETENDC
Definition: ald_usb.h:111
USB_DEV_RX_DATA_ERROR
#define USB_DEV_RX_DATA_ERROR
Definition: ald_usb.h:278
USB_DEV_EP0_SENT_STALL
#define USB_DEV_EP0_SENT_STALL
Definition: ald_usb.h:291
USB_DEV_RX_SENT_STALL
#define USB_DEV_RX_SENT_STALL
Definition: ald_usb.h:277

◆ ald_usb_dev_get_addr()

uint8_t ald_usb_dev_get_addr ( void )

Gets the address.

Return values
Address.

Definition at line 158 of file ald_usb.c.

159 {
160 return USB0->FADDR;
161 }

◆ ald_usb_dev_set_addr()

void ald_usb_dev_set_addr ( uint8_t addr )

Sets the address.

Parameters
addr The address which will be set.
Return values
None

Definition at line 168 of file ald_usb.c.

169 {
170 USB0->FADDR = addr;
171 }


ALD User Manual: Host functions

Functions
Host functions
EASTSOFT ES32F3xx ALD » USB » USB Public Function

Host functions. More...

Collaboration diagram for Host functions:

Functions

uint32_t | ald_usb_host_addr_get (uint32_t ep_idx, uint32_t flags)
Gets the device's address. More...
void | ald_usb_host_addr_set (uint32_t ep_idx, uint32_t addr, uint32_t flags)
Sets the device's address. More...
void | ald_usb_host_ep_config (uint32_t ep_idx, uint32_t p_max, uint32_t nak_val, uint32_t t_ep, uint32_t flags)
Configure the endpoint in host mode. More...
void | ald_usb_host_ep_data_ack (uint32_t ep_idx)
Acknowledge the data in host mode. More...
void | ald_usb_host_ep_data_toggle (uint32_t ep_idx, bool toggle, uint32_t flags)
Toggle the data in host mode. More...
void | ald_usb_host_ep_status_clear (uint32_t ep_idx, uint32_t flags)
Clear the status of endpoint in host mode. More...
uint32_t | ald_usb_host_hub_addr_get (uint32_t ep_idx, uint32_t flags)
Gets the HUB's address. More...
void | ald_usb_host_hub_addr_set (uint32_t ep_idx, uint32_t addr, uint32_t flags)
Sets the HUB's address. More...
void | ald_usb_host_pwr_disable (void)
Disable power. More...
void | ald_usb_host_pwr_enable (void)
Enable power. More...
void | ald_usb_host_pwr_config (uint32_t flags)
Configure power in host mode. More...
void | ald_usb_host_pwr_fault_disable (void)
Disable the fault parameters of the power. More...
void | ald_usb_host_pwr_fault_enable (void)
Enable the fault parameters of the power. More...
void | ald_usb_host_request_in (uint32_t ep_idx)
Request data IN(from device to host) More...
void | ald_usb_host_request_in_clear (uint32_t ep_idx)
Clear the status of request IN. More...
void | ald_usb_host_request_status (void)
Request data IN at endpoint 0. More...
void | ald_usb_host_reset (bool start)
Reset the USB's bus. More...
void | ald_usb_host_resume (bool start)
Resume the devices. More...
void | ald_usb_host_suspend (void)
Suspend the devices. More...
uint32_t | ald_usb_host_speed_get (void)
Gets the device's speed. More...
void | ald_usb_host_ep_speed_set (uint32_t ep_idx, uint32_t flags)
Sets the endpoint speed. More...
void | ald_usb_host_ep_ping (uint32_t ep_idx, bool enable)
Ping the endpoint. More...

Detailed Description

Host functions.

Function Documentation

◆ ald_usb_host_addr_get()

uint32_t ald_usb_host_addr_get | ( | uint32_t | ep_idx,
 |  | uint32_t | flags
 | ) |  |

Gets the device's address.

Parameters
ep_idx | Index of the endpoint
flags | Flags.
Return values
Address

Definition at line 350 of file ald_usb.c.

351 {
352 if (flags & USB_EP_HOST_OUT)
353 return USB0->ADDR[ep_idx].TXxFUNCADDR;
354 else
355 return USB0->ADDR[ep_idx].RXxFUNCADDR;
356 }
USB_EP_HOST_OUT
#define USB_EP_HOST_OUT
Definition: ald_usb.h:312

◆ ald_usb_host_addr_set()

void ald_usb_host_addr_set | ( | uint32_t | ep_idx,
 |  | uint32_t | addr,
 |  | uint32_t | flags
 | ) |  |

Sets the device's address.

Parameters
ep_idx | Index of the endpoint.
addr | The device's address.
flags | Flags.
Return values
None

Definition at line 365 of file ald_usb.c.

366 {
367 if (flags & USB_EP_HOST_OUT)
368 USB0->ADDR[ep_idx].TXxFUNCADDR = addr;
369 else
370 USB0->ADDR[ep_idx].RXxFUNCADDR = addr;
371 }
USB_EP_HOST_OUT
#define USB_EP_HOST_OUT
Definition: ald_usb.h:312

◆ ald_usb_host_ep_config()

void ald_usb_host_ep_config | ( | uint32_t | ep_idx,
 |  | uint32_t | p_max,
 |  | uint32_t | nak_val,
 |  | uint32_t | t_ep,
 |  | uint32_t | flags
 | ) |  |

Configure the endpoint in host mode.

Parameters
ep_idx | Index of the endpoint.
p_max | Size of the maximum package.
nak_val | Value of the nack.
t_ep | Target endpoint.
flags | Flags.
Return values
None

Definition at line 382 of file ald_usb.c.

383 {
384 uint32_t tmp;
385
386 if (ep_idx == USB_EP_0) {
387 USB0->NACK = nak_val;
388
389 if (flags & USB_EP_SPEED_HIGH)
390 USB0->TYPE0 = USB_TYPE0_SPEED_HIGH;
391 else if (flags & USB_EP_SPEED_FULL)
392 USB0->TYPE0 = USB_TYPE0_SPEED_FULL;
393 else
394 USB0->TYPE0 = USB_TYPE0_SPEED_LOW;
395 }
396 else {
397 tmp = t_ep;
398
399 if (flags & USB_EP_SPEED_HIGH)
400 tmp |= USB_TXTYPE1_SPEED_HIGH;
401 else if (flags & USB_EP_SPEED_FULL)
402 tmp |= USB_TXTYPE1_SPEED_FULL;
403 else
404 tmp |= USB_TXTYPE1_SPEED_LOW;
405
406 switch (flags & USB_EP_MODE_MASK) {
407 case USB_EP_MODE_BULK:
408 tmp |= USB_TXTYPE1_PROTO_BULK;
409 break;
410
411 case USB_EP_MODE_ISOC:
412 tmp |= USB_TXTYPE1_PROTO_ISOC;
413 break;
414
415 case USB_EP_MODE_INT:
416 tmp |= USB_TXTYPE1_PROTO_INT;
417 break;
418
419 case USB_EP_MODE_CTRL:
420 tmp |= USB_TXTYPE1_PROTO_CTRL;
421 break;
422 }
423
424 if (flags & USB_EP_HOST_OUT) {
425 USB0->CSR[ep_idx - 1].TXxTYPE = tmp;
426 USB0->CSR[ep_idx - 1].TXxINTERVAL = nak_val;
427 USB0->CSR[ep_idx - 1].TXxMAXP = p_max;
428
429 tmp = 0;
430 if (flags & USB_EP_AUTO_SET)
431 tmp |= USB_TXCSRH1_AUTOSET;
432 USB0->CSR[ep_idx - 1].TXxCSRH = (uint8_t)tmp;
433 }
434 else {
435 USB0->CSR[ep_idx - 1].RXxTYPE = tmp;
436 USB0->CSR[ep_idx - 1].RXxINTERVAL = nak_val;
437 USB0->CSR[ep_idx - 1].RXxMAXP = p_max;
438
439 tmp = 0;
440 if (flags & USB_EP_AUTO_CLEAR)
441 tmp |= USB_RXCSRH1_AUTOCL;
442 if (flags & USB_EP_AUTO_REQUEST)
443 tmp |= USB_RXCSRH1_AUTORQ;
444
445 USB0->CSR[ep_idx - 1].RXxCSRH = (uint8_t)tmp;
446 }
447 }
448 }
USB_EP_MODE_INT
#define USB_EP_MODE_INT
Definition: ald_usb.h:305
USB_EP_MODE_CTRL
#define USB_EP_MODE_CTRL
Definition: ald_usb.h:306
USB_TYPE0_SPEED_HIGH
#define USB_TYPE0_SPEED_HIGH
Definition: ald_usb.h:125
USB_TXTYPE1_PROTO_BULK
#define USB_TXTYPE1_PROTO_BULK
Definition: ald_usb.h:137
USB_TYPE0_SPEED_FULL
#define USB_TYPE0_SPEED_FULL
Definition: ald_usb.h:126
USB_EP_HOST_OUT
#define USB_EP_HOST_OUT
Definition: ald_usb.h:312
USB_EP_0
#define USB_EP_0
Definition: ald_usb.h:347
USB_EP_AUTO_SET
#define USB_EP_AUTO_SET
Definition: ald_usb.h:295
USB_EP_SPEED_HIGH
#define USB_EP_SPEED_HIGH
Definition: ald_usb.h:310
USB_RXCSRH1_AUTOCL
#define USB_RXCSRH1_AUTOCL
Definition: ald_usb.h:62
USB_TXTYPE1_SPEED_FULL
#define USB_TXTYPE1_SPEED_FULL
Definition: ald_usb.h:132
USB_TXCSRH1_AUTOSET
#define USB_TXCSRH1_AUTOSET
Definition: ald_usb.h:78
USB_EP_MODE_MASK
#define USB_EP_MODE_MASK
Definition: ald_usb.h:307
USB_EP_AUTO_CLEAR
#define USB_EP_AUTO_CLEAR
Definition: ald_usb.h:297
USB_RXCSRH1_AUTORQ
#define USB_RXCSRH1_AUTORQ
Definition: ald_usb.h:63
USB_EP_AUTO_REQUEST
#define USB_EP_AUTO_REQUEST
Definition: ald_usb.h:296
USB_TXTYPE1_SPEED_HIGH
#define USB_TXTYPE1_SPEED_HIGH
Definition: ald_usb.h:131
USB_TXTYPE1_PROTO_INT
#define USB_TXTYPE1_PROTO_INT
Definition: ald_usb.h:138
USB_TYPE0_SPEED_LOW
#define USB_TYPE0_SPEED_LOW
Definition: ald_usb.h:127
USB_TXTYPE1_SPEED_LOW
#define USB_TXTYPE1_SPEED_LOW
Definition: ald_usb.h:133
USB_TXTYPE1_PROTO_CTRL
#define USB_TXTYPE1_PROTO_CTRL
Definition: ald_usb.h:135
USB_EP_MODE_ISOC
#define USB_EP_MODE_ISOC
Definition: ald_usb.h:303
USB_TXTYPE1_PROTO_ISOC
#define USB_TXTYPE1_PROTO_ISOC
Definition: ald_usb.h:136
USB_EP_SPEED_FULL
#define USB_EP_SPEED_FULL
Definition: ald_usb.h:309
USB_EP_MODE_BULK
#define USB_EP_MODE_BULK
Definition: ald_usb.h:304

◆ ald_usb_host_ep_data_ack()

void ald_usb_host_ep_data_ack ( uint32_t ep_idx )

Acknowledge the data in host mode.

Parameters
ep_idx Index of the endpoint.
Return values
None

Definition at line 455 of file ald_usb.c.

456 {
457 if (ep_idx == USB_EP_0)
458 USB0->CSR0L &= ~(USB_CSRL0_RXRDY);
459 else
460 USB0->CSR[ep_idx - 1].RXxCSRL &= ~(USB_RXCSRL1_RXRDY);
461 }
USB_EP_0
#define USB_EP_0
Definition: ald_usb.h:347
USB_CSRL0_RXRDY
#define USB_CSRL0_RXRDY
Definition: ald_usb.h:122
USB_RXCSRL1_RXRDY
#define USB_RXCSRL1_RXRDY
Definition: ald_usb.h:108

◆ ald_usb_host_ep_data_toggle()

void ald_usb_host_ep_data_toggle | ( | uint32_t | ep_idx,
 |  | bool | toggle,
 |  | uint32_t | flags
 | ) |  |

Toggle the data in host mode.

Parameters
ep_idx | Index of the endpoint.
toggle | true/false.
flags | Flags.
Return values
None

Definition at line 470 of file ald_usb.c.

471 {
472 uint32_t tmp = 0;
473
474 if (toggle) {
475 if (ep_idx == USB_EP_0)
476 tmp = USB_CSRH0_DT;
477 else if (flags == USB_EP_HOST_IN)
478 tmp = USB_RXCSRH1_DT;
479 else
480 tmp = USB_TXCSRH1_DT;
481 }
482
483 if (ep_idx == USB_EP_0) {
484 USB0->CSR0H = (uint8_t)((USB0->CSR0H & ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) |
485 (tmp | USB_CSRH0_DTWE));
486 }
487 else if (flags == USB_EP_HOST_IN) {
488 USB0->CSR[ep_idx - 1].RXxCSRH = (uint8_t)((USB0->CSR[ep_idx - 1].RXxCSRH &
489 ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) |
490 (tmp | USB_RXCSRH1_DTWE));
491 }
492 else {
493 USB0->CSR[ep_idx - 1].TXxCSRH = (uint8_t)((USB0->CSR[ep_idx - 1].TXxCSRH &
494 ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) |
495 (tmp | USB_TXCSRH1_DTWE));
496 }
497 }
USB_EP_HOST_IN
#define USB_EP_HOST_IN
Definition: ald_usb.h:311
USB_EP_0
#define USB_EP_0
Definition: ald_usb.h:347
USB_CSRH0_DTWE
#define USB_CSRH0_DTWE
Definition: ald_usb.h:74
USB_CSRH0_DT
#define USB_CSRH0_DT
Definition: ald_usb.h:75
USB_RXCSRH1_DT
#define USB_RXCSRH1_DT
Definition: ald_usb.h:70
USB_TXCSRH1_DT
#define USB_TXCSRH1_DT
Definition: ald_usb.h:85
USB_RXCSRH1_DTWE
#define USB_RXCSRH1_DTWE
Definition: ald_usb.h:69
USB_TXCSRH1_DTWE
#define USB_TXCSRH1_DTWE
Definition: ald_usb.h:84

◆ ald_usb_host_ep_ping()

void ald_usb_host_ep_ping | ( | uint32_t | ep_idx,
 |  | bool | enable
 | ) |  |

Ping the endpoint.

Parameters
ep_idx | Index of the endpoint.
enable | ENABLE/DISABLE.
Return values
None

Definition at line 719 of file ald_usb.c.

720 {
721 if (enable)
722 USB0->CSR0H &= ~(USB_CSRH0_DISPING);
723 else
724 USB0->CSR0H |= USB_CSRH0_DISPING;
725 }
USB_CSRH0_DISPING
#define USB_CSRH0_DISPING
Definition: ald_usb.h:73

◆ ald_usb_host_ep_speed_set()

void ald_usb_host_ep_speed_set | ( | uint32_t | ep_idx,
 |  | uint32_t | flags
 | ) |  |

Sets the endpoint speed.

Parameters
ep_idx | Index of the endpoint.
flags | Type of the speed.
Return values
None

Definition at line 694 of file ald_usb.c.

695 {
696 uint32_t tmp;
697
698 if (flags & USB_EP_SPEED_HIGH)
699 tmp = USB_TYPE0_SPEED_HIGH;
700 else if (flags & USB_EP_SPEED_FULL)
701 tmp = USB_TYPE0_SPEED_FULL;
702 else
703 tmp = USB_TYPE0_SPEED_LOW;
704
705 if (ep_idx == USB_EP_0)
706 USB0->TYPE0 |= tmp;
707 else if (flags & USB_EP_HOST_OUT)
708 USB0->CSR[ep_idx - 1].TXxTYPE |= tmp;
709 else
710 USB0->CSR[ep_idx - 1].RXxTYPE |= tmp;
711 }
USB_TYPE0_SPEED_HIGH
#define USB_TYPE0_SPEED_HIGH
Definition: ald_usb.h:125
USB_TYPE0_SPEED_FULL
#define USB_TYPE0_SPEED_FULL
Definition: ald_usb.h:126
USB_EP_HOST_OUT
#define USB_EP_HOST_OUT
Definition: ald_usb.h:312
USB_EP_0
#define USB_EP_0
Definition: ald_usb.h:347
USB_EP_SPEED_HIGH
#define USB_EP_SPEED_HIGH
Definition: ald_usb.h:310
USB_TYPE0_SPEED_LOW
#define USB_TYPE0_SPEED_LOW
Definition: ald_usb.h:127
USB_EP_SPEED_FULL
#define USB_EP_SPEED_FULL
Definition: ald_usb.h:309

◆ ald_usb_host_ep_status_clear()

void ald_usb_host_ep_status_clear | ( | uint32_t | ep_idx,
 |  | uint32_t | flags
 | ) |  |

Clear the status of endpoint in host mode.

Parameters
ep_idx | Index of the endpoint.
flags | Flags.
Return values
None

Definition at line 505 of file ald_usb.c.

506 {
507 if (ep_idx == USB_EP_0) {
508 USB0->CSR0L &= ~flags;
509 }
510 else {
511 USB0->CSR[ep_idx - 1].TXxCSRL &= ~flags;
512 USB0->CSR[ep_idx - 1].RXxCSRL &= ~flags;
513 }
514 }
USB_EP_0
#define USB_EP_0
Definition: ald_usb.h:347

◆ ald_usb_host_hub_addr_get()

uint32_t ald_usb_host_hub_addr_get | ( | uint32_t | ep_idx,
 |  | uint32_t | flags
 | ) |  |

Gets the HUB's address.

Parameters
ep_idx | Index of the endpoint.
flags | Flags.
Return values
Address

Definition at line 522 of file ald_usb.c.

523 {
524 if (flags & USB_EP_HOST_OUT)
525 return USB0->ADDR[ep_idx].TXxHUBADDR;
526 else
527 return USB0->ADDR[ep_idx].RXxHUBADDR;
528 }
USB_EP_HOST_OUT
#define USB_EP_HOST_OUT
Definition: ald_usb.h:312

◆ ald_usb_host_hub_addr_set()

void ald_usb_host_hub_addr_set | ( | uint32_t | ep_idx,
 |  | uint32_t | addr,
 |  | uint32_t | flags
 | ) |  |

Sets the HUB's address.

Parameters
ep_idx | Index of the endpoint.
addr | HUB's address which will be set.
flags | Flags.
Return values
Address

Definition at line 537 of file ald_usb.c.

538 {
539 if (flags & USB_EP_HOST_OUT)
540 USB0->ADDR[ep_idx].TXxHUBADDR = addr;
541 else
542 USB0->ADDR[ep_idx].RXxHUBADDR = addr;
543
544 if (ep_idx == USB_EP_0) {
545 if (flags & USB_EP_SPEED_FULL)
546 USB0->TYPE0 |= USB_TYPE0_SPEED_FULL;
547 else if (flags & USB_EP_SPEED_HIGH)
548 USB0->TYPE0 |= USB_TYPE0_SPEED_HIGH;
549 else
550 USB0->TYPE0 |= USB_TYPE0_SPEED_LOW;
551 }
552 }
USB_TYPE0_SPEED_HIGH
#define USB_TYPE0_SPEED_HIGH
Definition: ald_usb.h:125
USB_TYPE0_SPEED_FULL
#define USB_TYPE0_SPEED_FULL
Definition: ald_usb.h:126
USB_EP_HOST_OUT
#define USB_EP_HOST_OUT
Definition: ald_usb.h:312
USB_EP_0
#define USB_EP_0
Definition: ald_usb.h:347
USB_EP_SPEED_HIGH
#define USB_EP_SPEED_HIGH
Definition: ald_usb.h:310
USB_TYPE0_SPEED_LOW
#define USB_TYPE0_SPEED_LOW
Definition: ald_usb.h:127
USB_EP_SPEED_FULL
#define USB_EP_SPEED_FULL
Definition: ald_usb.h:309

◆ ald_usb_host_pwr_config()

void ald_usb_host_pwr_config ( uint32_t flags )

Configure power in host mode.

Parameters
flags Flags
Return values
None

Definition at line 577 of file ald_usb.c.

578 {
579 return;
580 }

◆ ald_usb_host_pwr_disable()

void ald_usb_host_pwr_disable ( void )

Disable power.

Return values
None

Definition at line 558 of file ald_usb.c.

559 {
560 return;
561 }

◆ ald_usb_host_pwr_enable()

void ald_usb_host_pwr_enable ( void )

Enable power.

Return values
None

Definition at line 567 of file ald_usb.c.

568 {
569 return;
570 }

◆ ald_usb_host_pwr_fault_disable()

void ald_usb_host_pwr_fault_disable ( void )

Disable the fault parameters of the power.

Return values
None

Definition at line 586 of file ald_usb.c.

587 {
588 return;
589 }

◆ ald_usb_host_pwr_fault_enable()

void ald_usb_host_pwr_fault_enable ( void )

Enable the fault parameters of the power.

Return values
None

Definition at line 595 of file ald_usb.c.

596 {
597 return;
598 }

◆ ald_usb_host_request_in()

void ald_usb_host_request_in ( uint32_t ep_idx )

Request data IN(from device to host)

Parameters
ep_idx Index of the endpoint.
Return values
None

Definition at line 605 of file ald_usb.c.

606 {
607 if (ep_idx == USB_EP_0)
608 USB0->CSR0L = USB_RXCSRL1_REQPKT;
609 else
610 USB0->CSR[ep_idx - 1].RXxCSRL = USB_RXCSRL1_REQPKT;
611 }
USB_EP_0
#define USB_EP_0
Definition: ald_usb.h:347
USB_RXCSRL1_REQPKT
#define USB_RXCSRL1_REQPKT
Definition: ald_usb.h:101

◆ ald_usb_host_request_in_clear()

void ald_usb_host_request_in_clear ( uint32_t ep_idx )

Clear the status of request IN.

Parameters
ep_idx Index of the endpoint.
Return values
None

Definition at line 618 of file ald_usb.c.

619 {
620 if (ep_idx == USB_EP_0)
621 USB0->CSR0L &= ~(USB_RXCSRL1_REQPKT);
622 else
623 USB0->CSR[ep_idx - 1].RXxCSRL &= ~(USB_RXCSRL1_REQPKT);
624 }
USB_EP_0
#define USB_EP_0
Definition: ald_usb.h:347
USB_RXCSRL1_REQPKT
#define USB_RXCSRL1_REQPKT
Definition: ald_usb.h:101

◆ ald_usb_host_request_status()

void ald_usb_host_request_status ( void )

Request data IN at endpoint 0.

Return values
None

Definition at line 630 of file ald_usb.c.

631 {
632 USB0->CSR0L = USB_CSRL0_REQPKT | USB_CSRL0_STATUS;
633 }
USB_CSRL0_STATUS
#define USB_CSRL0_STATUS
Definition: ald_usb.h:112
USB_CSRL0_REQPKT
#define USB_CSRL0_REQPKT
Definition: ald_usb.h:114

◆ ald_usb_host_reset()

void ald_usb_host_reset ( bool start )

Reset the USB's bus.

Parameters
start true/false.
Return values
None

Definition at line 640 of file ald_usb.c.

641 {
642 if (start)
643 USB0->POWER |= USB_POWER_RESET;
644 else
645 USB0->POWER &= ~(USB_POWER_RESET);
646 }
USB_POWER_RESET
#define USB_POWER_RESET
Definition: ald_usb.h:45

◆ ald_usb_host_resume()

void ald_usb_host_resume ( bool start )

Resume the devices.

Parameters
start true/false.
Return values
None

Definition at line 653 of file ald_usb.c.

654 {
655 if (start)
656 USB0->POWER |= USB_POWER_RESUME;
657 else
658 USB0->POWER &= ~(USB_POWER_RESUME);
659 }
USB_POWER_RESUME
#define USB_POWER_RESUME
Definition: ald_usb.h:46

◆ ald_usb_host_speed_get()

uint32_t ald_usb_host_speed_get ( void )

Gets the device's speed.

Return values
Type of the speed.

Definition at line 674 of file ald_usb.c.

675 {
676 if (USB0->POWER & USB_POWER_HS_M)
677 return USB_HIGH_SPEED;
678
679 if (USB0->DEVCTL & USB_DEVCTL_FSDEV)
680 return USB_FULL_SPEED;
681
682 if (USB0->DEVCTL & USB_DEVCTL_LSDEV)
683 return USB_LOW_SPEED;
684
685 return USB_UNDEF_SPEED;
686 }
USB_HIGH_SPEED
#define USB_HIGH_SPEED
Definition: ald_usb.h:242
USB_DEVCTL_LSDEV
#define USB_DEVCTL_LSDEV
Definition: ald_usb.h:52
USB_FULL_SPEED
#define USB_FULL_SPEED
Definition: ald_usb.h:243
USB_POWER_HS_M
#define USB_POWER_HS_M
Definition: ald_usb.h:44
USB_UNDEF_SPEED
#define USB_UNDEF_SPEED
Definition: ald_usb.h:241
USB_DEVCTL_FSDEV
#define USB_DEVCTL_FSDEV
Definition: ald_usb.h:51
USB_LOW_SPEED
#define USB_LOW_SPEED
Definition: ald_usb.h:244

◆ ald_usb_host_suspend()

void ald_usb_host_suspend ( void )

Suspend the devices.

Return values
None

Definition at line 665 of file ald_usb.c.

666 {
667 USB0->POWER |= USB_POWER_SUSPEND;
668 }
USB_POWER_SUSPEND
#define USB_POWER_SUSPEND
Definition: ald_usb.h:47


ALD User Manual: Endpoint functions

Functions
Endpoint functions
EASTSOFT ES32F3xx ALD » USB » USB Public Function

Endpoint functions. More...

Collaboration diagram for Endpoint functions:

Functions

uint32_t | ald_usb_ep_data_avail (uint32_t ep_idx)
Gets the size of the available data. More...
int32_t | ald_usb_ep_data_get (uint32_t ep_idx, uint8_t *data, uint32_t *size)
Gets the data from FIFO. More...
int32_t | ald_usb_ep_data_put (uint32_t ep_idx, uint8_t *data, uint32_t size)
Puts data to the FIFO. More...
int32_t | ald_usb_ep_data_send (uint32_t ep_idx, uint32_t tx_type)
Send data. More...
void | ald_usb_ep_data_toggle_clear (uint32_t ep_idx, uint32_t flags)
Clear the status of the toggle. More...
void | ald_usb_ep_req_packet_count (uint32_t ep_idx, uint32_t count)
Sets the size of request data IN. More...
uint32_t | ald_usb_ep_status (uint32_t ep_idx)
Gets the status of the endpoint. More...
void | ald_usb_ep_dma_config (uint32_t ep_idx, uint32_t flag, type_func_t en)
Configure the endpoint in DMA mode. More...

Detailed Description

Endpoint functions.

Function Documentation

◆ ald_usb_ep_data_avail()

uint32_t ald_usb_ep_data_avail ( uint32_t ep_idx )

Gets the size of the available data.

Parameters
ep_idx Index of the endpoint
Return values
Size in bytes.

Definition at line 739 of file ald_usb.c.

740 {
741 if (ep_idx == USB_EP_0) {
742 if ((USB0->CSR0L & USB_CSRL0_RXRDY) == 0)
743 return 0;
744
745 return USB0->COUNT0;
746 }
747 else {
748 if ((USB0->CSR[ep_idx - 1].RXxCSRL & USB_CSRL0_RXRDY) == 0)
749 return 0;
750
751 return USB0->CSR[ep_idx - 1].RXxCOUNT;
752 }
753 }
USB_EP_0
#define USB_EP_0
Definition: ald_usb.h:347
USB_CSRL0_RXRDY
#define USB_CSRL0_RXRDY
Definition: ald_usb.h:122

◆ ald_usb_ep_data_get()

int32_t ald_usb_ep_data_get | ( | uint32_t | ep_idx,
 |  | uint8_t * | data,
 |  | uint32_t * | size
 | ) |  |

Gets the data from FIFO.

Parameters
ep_idx | Index of the endpoint
data | Pointer to the buffer.
size | Size of the data.
Return values
Status.

Definition at line 762 of file ald_usb.c.

763 {
764 uint32_t i;
765
766 if (ep_idx == USB_EP_0) {
767 if ((USB0->CSR0L & USB_CSRL0_RXRDY) == 0) {
768 *size = 0;
769 return -1;
770 }
771 i = USB0->COUNT0;
772 }
773 else {
774 if ((USB0->CSR[ep_idx - 1].RXxCSRL & USB_CSRL0_RXRDY) == 0) {
775 *size = 0;
776 return -1;
777 }
778 i = USB0->CSR[ep_idx - 1].RXxCOUNT;
779 }
780
781 i = (i < *size) ? i : *size;
782 *size = i;
783
784 for (; i > 0; i--)
785 *data++ = USB0->FIFO[ep_idx].Byte[0];
786
787 return 0;
788 }
USB_EP_0
#define USB_EP_0
Definition: ald_usb.h:347
USB_CSRL0_RXRDY
#define USB_CSRL0_RXRDY
Definition: ald_usb.h:122

◆ ald_usb_ep_data_put()

int32_t ald_usb_ep_data_put | ( | uint32_t | ep_idx,
 |  | uint8_t * | data,
 |  | uint32_t | size
 | ) |  |

Puts data to the FIFO.

Parameters
ep_idx | Index of the endpoint
data | Pointer to the data.
size | Size of the data.
Return values
Status.

Definition at line 797 of file ald_usb.c.

798 {
799 if (ep_idx == USB_EP_0) {
800 if (USB0->CSR0L & USB_CSRL0_TXRDY)
801 return -1;
802 }
803 else {
804 if (USB0->CSR[ep_idx - 1].TXxCSRL & USB_TXCSRL1_TXRDY)
805 return -1;
806 }
807
808 for (; size > 0; size--)
809 USB0->FIFO[ep_idx].Byte[0] = *data++;
810
811 return 0;
812 }
USB_EP_0
#define USB_EP_0
Definition: ald_usb.h:347
USB_TXCSRL1_TXRDY
#define USB_TXCSRL1_TXRDY
Definition: ald_usb.h:96
USB_CSRL0_TXRDY
#define USB_CSRL0_TXRDY
Definition: ald_usb.h:121

◆ ald_usb_ep_data_send()

int32_t ald_usb_ep_data_send | ( | uint32_t | ep_idx,
 |  | uint32_t | tx_type
 | ) |  |

Send data.

Parameters
ep_idx | Index of the endpoint
tx_type | Type.
Return values
Status.

Definition at line 820 of file ald_usb.c.

821 {
822 uint32_t tmp;
823
824 if (ep_idx == USB_EP_0) {
825 if (USB0->CSR0L & USB_CSRL0_TXRDY)
826 return -1;
827
828 tmp = tx_type & 0xff;
829 USB0->CSR0L = tmp;
830 }
831 else {
832 if (USB0->CSR[ep_idx - 1].TXxCSRL & USB_TXCSRL1_TXRDY)
833 return -1;
834
835 tmp = (tx_type >> 8) & 0xff;
836 USB0->CSR[ep_idx - 1].TXxCSRL = tmp;
837 }
838
839 return 0;
840 }
USB_EP_0
#define USB_EP_0
Definition: ald_usb.h:347
USB_TXCSRL1_TXRDY
#define USB_TXCSRL1_TXRDY
Definition: ald_usb.h:96
USB_CSRL0_TXRDY
#define USB_CSRL0_TXRDY
Definition: ald_usb.h:121

◆ ald_usb_ep_data_toggle_clear()

void ald_usb_ep_data_toggle_clear | ( | uint32_t | ep_idx,
 |  | uint32_t | flags
 | ) |  |

Clear the status of the toggle.

Parameters
ep_idx | Index of the endpoint
flags | Flags.
Return values
None

Definition at line 848 of file ald_usb.c.

849 {
850 if (flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
851 USB0->CSR[ep_idx - 1].TXxCSRL |= USB_TXCSRL1_CLRDT;
852 else
853 USB0->CSR[ep_idx - 1].RXxCSRL |= USB_RXCSRL1_CLRDT;
854 }
USB_EP_DEV_IN
#define USB_EP_DEV_IN
Definition: ald_usb.h:313
USB_EP_HOST_OUT
#define USB_EP_HOST_OUT
Definition: ald_usb.h:312
USB_RXCSRL1_CLRDT
#define USB_RXCSRL1_CLRDT
Definition: ald_usb.h:98
USB_TXCSRL1_CLRDT
#define USB_TXCSRL1_CLRDT
Definition: ald_usb.h:88

◆ ald_usb_ep_dma_config()

void ald_usb_ep_dma_config | ( | uint32_t | ep_idx,
 |  | uint32_t | flag,
 |  | type_func_t | en
 | ) |  |

Configure the endpoint in DMA mode.

Parameters
ep_idx | Index of the endpoint
flag | Flags.
en | ENABLE/DISABLE.
Return values
None

Definition at line 897 of file ald_usb.c.

898 {
899 if (ep_idx == USB_EP_0)
900 return;
901
902 if (en) {
903 switch (flag) {
904 case USB_DMA_EP_CFG_TX:
905 USB0->CSR[ep_idx - 1].TXxCSRH |= USB_DMA_EP_TX_MSK;
906 break;
907 case USB_DMA_EP_CFG_RX_DEV:
908 USB0->CSR[ep_idx - 1].RXxCSRH |= USB_DMA_EP_RX_DEV_MSK;
909 break;
910 case USB_DMA_EP_CFG_RX_HOST:
911 USB0->CSR[ep_idx - 1].RXxCSRH |= USB_DMA_EP_RX_HOST_MSK;
912 break;
913 default:
914 break;
915 }
916 }
917 else {
918 switch (flag) {
919 case USB_DMA_EP_CFG_TX:
920 USB0->CSR[ep_idx - 1].TXxCSRH &= ~(USB_DMA_EP_TX_MSK);
921 break;
922 case USB_DMA_EP_CFG_RX_DEV:
923 USB0->CSR[ep_idx - 1].RXxCSRH &= ~(USB_DMA_EP_RX_DEV_MSK);
924 break;
925 case USB_DMA_EP_CFG_RX_HOST:
926 USB0->CSR[ep_idx - 1].RXxCSRH &= ~(USB_DMA_EP_RX_HOST_MSK);
927 break;
928 default:
929 break;
930 }
931 }
932
933 return;
934 }
USB_EP_0
#define USB_EP_0
Definition: ald_usb.h:347
USB_DMA_EP_RX_DEV_MSK
#define USB_DMA_EP_RX_DEV_MSK
Definition: ald_usb.h:399
USB_DMA_EP_CFG_TX
#define USB_DMA_EP_CFG_TX
Definition: ald_usb.h:395
USB_DMA_EP_RX_HOST_MSK
#define USB_DMA_EP_RX_HOST_MSK
Definition: ald_usb.h:400
USB_DMA_EP_CFG_RX_DEV
#define USB_DMA_EP_CFG_RX_DEV
Definition: ald_usb.h:396
USB_DMA_EP_CFG_RX_HOST
#define USB_DMA_EP_CFG_RX_HOST
Definition: ald_usb.h:397
USB_DMA_EP_TX_MSK
#define USB_DMA_EP_TX_MSK
Definition: ald_usb.h:398

◆ ald_usb_ep_req_packet_count()

void ald_usb_ep_req_packet_count | ( | uint32_t | ep_idx,
 |  | uint32_t | count
 | ) |  |

Sets the size of request data IN.

Parameters
ep_idx | Index of the endpoint
count | Size of request data IN.
Return values
None

Definition at line 862 of file ald_usb.c.

863 {
864 USB0->EP_RQPKTCOUNT[ep_idx - 1] = count;
865 }

◆ ald_usb_ep_status()

uint32_t ald_usb_ep_status ( uint32_t ep_idx )

Gets the status of the endpoint.

Parameters
ep_idx Index of the endpoint
Return values
Status.

Definition at line 872 of file ald_usb.c.

873 {
874 uint32_t status;
875
876 if (ep_idx == USB_EP_0) {
877 status = USB0->CSR0L;
878 status |= (USB0->CSR0H) << USB_RX_EPSTATUS_SHIFT;
879 }
880 else {
881 status = USB0->CSR[ep_idx - 1].TXxCSRL;
882 status |= USB0->CSR[ep_idx - 1].TXxCSRH << 8;
883 status |= USB0->CSR[ep_idx - 1].RXxCSRL << 16;
884 status |= USB0->CSR[ep_idx - 1].RXxCSRH << 24;
885 }
886
887 return status;
888 }
USB_EP_0
#define USB_EP_0
Definition: ald_usb.h:347
USB_RX_EPSTATUS_SHIFT
#define USB_RX_EPSTATUS_SHIFT
Definition: ald_usb.h:409


ALD User Manual: FIFO functions

Functions
FIFO functions
EASTSOFT ES32F3xx ALD » USB » USB Public Function

FIFO functions. More...

Collaboration diagram for FIFO functions:

Functions

uint32_t | ald_usb_fifo_addr_get (uint32_t ep_idx)
Gets the address of the FIFO. More...
void | ald_usb_fifo_config_get (uint32_t ep_idx, uint32_t *addr, uint32_t *size, uint32_t flags)
Gets the parameters of the FIFO. More...
void | ald_usb_fifo_config_set (uint32_t ep_idx, uint32_t addr, uint32_t size, uint32_t flags)
Sets the parameters of the FIFO. More...
void | ald_usb_fifo_flush (uint32_t ep_idx, uint32_t flags)
Flush the FIFO. More...

Detailed Description

FIFO functions.

Function Documentation

◆ ald_usb_fifo_addr_get()

uint32_t ald_usb_fifo_addr_get ( uint32_t ep_idx )

Gets the address of the FIFO.

Parameters
ep_idx Index of the endpoint
Return values
Address

Definition at line 948 of file ald_usb.c.

949 {
950 return (uint32_t)&USB0->FIFO[ep_idx].Word;
951 }

◆ ald_usb_fifo_config_get()

void ald_usb_fifo_config_get | ( | uint32_t | ep_idx,
 |  | uint32_t * | addr,
 |  | uint32_t * | size,
 |  | uint32_t | flags
 | ) |  |

Gets the parameters of the FIFO.

Parameters
ep_idx | Index of the endpoint
addr | Address.
size | Size of FIFO.
flags | Flags.
Return values
None

Definition at line 961 of file ald_usb.c.

962 {
963 uint32_t tmp = USB0->INDEX;
964
965 USB0->INDEX = ep_idx;
966
967 if (flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) {
968 *addr = (USB0->TXFIFOADD << 3);
969 *size = (USB0->TXFIFOSIZE & 0xF);
970 }
971 else {
972 *addr = (USB0->RXFIFOADD << 3);
973 *size = (USB0->RXFIFOSIZE & 0xF);
974 }
975
976 USB0->INDEX = tmp;
977 return;
978 }
USB_EP_DEV_IN
#define USB_EP_DEV_IN
Definition: ald_usb.h:313
USB_EP_HOST_OUT
#define USB_EP_HOST_OUT
Definition: ald_usb.h:312

◆ ald_usb_fifo_config_set()

void ald_usb_fifo_config_set | ( | uint32_t | ep_idx,
 |  | uint32_t | addr,
 |  | uint32_t | size,
 |  | uint32_t | flags
 | ) |  |

Sets the parameters of the FIFO.

Parameters
ep_idx | Index of the endpoint
addr | Address.
size | Size of FIFO.
flags | Flags.
Return values
None

Definition at line 988 of file ald_usb.c.

989 {
990 uint32_t tmp = USB0->INDEX;
991
992 USB0->INDEX = ep_idx;
993
994 if (flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) {
995 USB0->TXFIFOADD = (addr >> 3);
996 USB0->TXFIFOSIZE = (size & 0xF);
997 }
998 else {
999 USB0->RXFIFOADD = (addr >> 3);
1000 USB0->RXFIFOSIZE = (size & 0xF);
1001 }
1002
1003 USB0->INDEX = tmp;
1004 return;
1005 }
USB_EP_DEV_IN
#define USB_EP_DEV_IN
Definition: ald_usb.h:313
USB_EP_HOST_OUT
#define USB_EP_HOST_OUT
Definition: ald_usb.h:312

◆ ald_usb_fifo_flush()

void ald_usb_fifo_flush | ( | uint32_t | ep_idx,
 |  | uint32_t | flags
 | ) |  |

Flush the FIFO.

Parameters
ep_idx | Index of the endpoint
flags | Flags.
Return values
None

Definition at line 1013 of file ald_usb.c.

1014 {
1015 if (ep_idx == USB_EP_0) {
1016 if ((USB0->CSR0L & (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0)
1017 USB0->CSR0H |= USB_CSRH0_FLUSH;
1018 }
1019 else {
1020 if (flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) {
1021 if (USB0->CSR[ep_idx - 1].TXxCSRL & USB_TXCSRL1_TXRDY)
1022 USB0->CSR[ep_idx - 1].TXxCSRL |= USB_TXCSRL1_FLUSH;
1023 }
1024 else {
1025 if (USB0->CSR[ep_idx - 1].RXxCSRL & USB_RXCSRL1_RXRDY)
1026 USB0->CSR[ep_idx - 1].RXxCSRL |= USB_RXCSRL1_FLUSH;
1027 }
1028 }
1029 }
USB_EP_DEV_IN
#define USB_EP_DEV_IN
Definition: ald_usb.h:313
USB_EP_HOST_OUT
#define USB_EP_HOST_OUT
Definition: ald_usb.h:312
USB_EP_0
#define USB_EP_0
Definition: ald_usb.h:347
USB_TXCSRL1_TXRDY
#define USB_TXCSRL1_TXRDY
Definition: ald_usb.h:96
USB_RXCSRL1_FLUSH
#define USB_RXCSRL1_FLUSH
Definition: ald_usb.h:102
USB_TXCSRL1_FLUSH
#define USB_TXCSRL1_FLUSH
Definition: ald_usb.h:92
USB_CSRL0_RXRDY
#define USB_CSRL0_RXRDY
Definition: ald_usb.h:122
USB_CSRL0_TXRDY
#define USB_CSRL0_TXRDY
Definition: ald_usb.h:121
USB_RXCSRL1_RXRDY
#define USB_RXCSRL1_RXRDY
Definition: ald_usb.h:108
USB_CSRH0_FLUSH
#define USB_CSRH0_FLUSH
Definition: ald_usb.h:76


ALD User Manual: Interrupt functions

Functions
Interrupt functions
EASTSOFT ES32F3xx ALD » USB » USB Public Function

Interrupt functions. More...

Collaboration diagram for Interrupt functions:

Functions

void | ald_usb_int_disable (uint32_t flags)
Disable interrupt. More...
void | ald_usb_int_enable (uint32_t flags)
Enable interrupt. More...
uint32_t | ald_usb_int_status_get (void)
Gets the status of the interrupt. More...
void | ald_usb_int_disable_ep (uint32_t flags)
Disable interrupt of the endpoint. More...
void | ald_usb_int_enable_ep (uint32_t flags)
Enable interrupt of the endpoint. More...
uint32_t | ald_usb_int_status_ep_get (void)
Gets the ststus of the endpoint interrupt. More...
void | ald_usb_int_register (void)
Register USB's interrupt. More...
void | ald_usb_int_unregister (void)
Unregister USB's interrupt. More...
uint32_t | ald_usb_int_num_get (void)
Get USB's interrupt number. More...

Detailed Description

Interrupt functions.

Function Documentation

◆ ald_usb_int_disable()

void ald_usb_int_disable ( uint32_t flags )

Disable interrupt.

Parameters
flags Type of the interrupt.
Return values
None

Definition at line 1043 of file ald_usb.c.

1044 {
1045 if (flags & USB_INTCTRL_STATUS)
1046 USB0->USBIE &= ~(flags & USB_INTCTRL_STATUS);
1047 }
USB_INTCTRL_STATUS
#define USB_INTCTRL_STATUS
Definition: ald_usb.h:156

◆ ald_usb_int_disable_ep()

void ald_usb_int_disable_ep ( uint32_t flags )

Disable interrupt of the endpoint.

Parameters
flags Type of the interrupt.
Return values
None

Definition at line 1074 of file ald_usb.c.

1075 {
1076 USB0->TXIE &= ~(flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0));
1077 USB0->RXIE &= ~((flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> USB_INTEP_RX_SHIFT);
1078 }
USB_INTEP_HOST_IN
#define USB_INTEP_HOST_IN
Definition: ald_usb.h:171
USB_INTEP_RX_SHIFT
#define USB_INTEP_RX_SHIFT
Definition: ald_usb.h:410
USB_INTEP_0
#define USB_INTEP_0
Definition: ald_usb.h:239
USB_INTEP_HOST_OUT
#define USB_INTEP_HOST_OUT
Definition: ald_usb.h:205
USB_INTEP_DEV_IN
#define USB_INTEP_DEV_IN
Definition: ald_usb.h:222
USB_INTEP_DEV_OUT
#define USB_INTEP_DEV_OUT
Definition: ald_usb.h:188

◆ ald_usb_int_enable()

void ald_usb_int_enable ( uint32_t flags )

Enable interrupt.

Parameters
flags Type of the interrupt.
Return values
None

Definition at line 1054 of file ald_usb.c.

1055 {
1056 if (flags & USB_INTCTRL_STATUS)
1057 USB0->USBIE |= flags ;
1058 }
USB_INTCTRL_STATUS
#define USB_INTCTRL_STATUS
Definition: ald_usb.h:156

◆ ald_usb_int_enable_ep()

void ald_usb_int_enable_ep ( uint32_t flags )

Enable interrupt of the endpoint.

Parameters
flags Type of the interrupt.
Return values
None

Definition at line 1085 of file ald_usb.c.

1086 {
1087
1088 USB0->TXIE |= flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0);
1089 USB0->RXIE |= ((flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> USB_INTEP_RX_SHIFT);
1090 }
USB_INTEP_HOST_IN
#define USB_INTEP_HOST_IN
Definition: ald_usb.h:171
USB_INTEP_RX_SHIFT
#define USB_INTEP_RX_SHIFT
Definition: ald_usb.h:410
USB_INTEP_0
#define USB_INTEP_0
Definition: ald_usb.h:239
USB_INTEP_HOST_OUT
#define USB_INTEP_HOST_OUT
Definition: ald_usb.h:205
USB_INTEP_DEV_IN
#define USB_INTEP_DEV_IN
Definition: ald_usb.h:222
USB_INTEP_DEV_OUT
#define USB_INTEP_DEV_OUT
Definition: ald_usb.h:188

◆ ald_usb_int_num_get()

uint32_t ald_usb_int_num_get ( void )

Get USB's interrupt number.

Return values
None

Definition at line 1129 of file ald_usb.c.

1130 {
1131 return USB_INT_IRQn;
1132 }

◆ ald_usb_int_register()

void ald_usb_int_register ( void )

Register USB's interrupt.

Return values
None

Definition at line 1110 of file ald_usb.c.

1111 {
1112 ald_mcu_irq_config(USB_INT_IRQn, 2, 2, ENABLE);
1113
1114 }
ENABLE
Definition: type.h:49
ald_mcu_irq_config
void ald_mcu_irq_config(IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, type_func_t status)
Configure interrupt.
Definition: utils.c:375

◆ ald_usb_int_status_ep_get()

uint32_t ald_usb_int_status_ep_get ( void )

Gets the ststus of the endpoint interrupt.

Return values
Status.

Definition at line 1096 of file ald_usb.c.

1097 {
1098 uint32_t status;
1099
1100 status = USB0->TXIS;
1101 status |= (USB0->RXIS << USB_INTEP_RX_SHIFT);
1102
1103 return status;
1104 }
USB_INTEP_RX_SHIFT
#define USB_INTEP_RX_SHIFT
Definition: ald_usb.h:410

◆ ald_usb_int_status_get()

uint32_t ald_usb_int_status_get ( void )

Gets the status of the interrupt.

Return values
Status.

Definition at line 1064 of file ald_usb.c.

1065 {
1066 return USB0->USBIS;
1067 }

◆ ald_usb_int_unregister()

void ald_usb_int_unregister ( void )

Unregister USB's interrupt.

Return values
None

Definition at line 1120 of file ald_usb.c.

1121 {
1122 ald_mcu_irq_config(USB_INT_IRQn, 2, 2, DISABLE);
1123 }
DISABLE
Definition: type.h:48
ald_mcu_irq_config
void ald_mcu_irq_config(IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, type_func_t status)
Configure interrupt.
Definition: utils.c:375


ALD User Manual: DMA functions

Functions
DMA functions
EASTSOFT ES32F3xx ALD » USB » USB Public Function

DMA functions. More...

Collaboration diagram for DMA functions:

Functions

void | ald_usb_dma_channel_config (uint8_t ch, uint32_t addr, uint32_t count, uint32_t ctrl)
Configure DMA's channel. More...
void | ald_usb_dma_mult_recv_start (uint32_t ep_idx)
Start multiple receive. More...
void | ald_usb_dma_channel_start (uint8_t ch)
Start DMA's machine. More...
void | ald_usb_dma_channel_stop (uint8_t ch)
Stop DMA's machine. More...
uint32_t | ald_usb_dma_get_interrupt_flag (void)
Gets flags of the interrupt. More...
uint32_t | ald_usb_dma_get_channel_error (uint8_t ch)
Gets the status of the error. More...
void | ald_usb_dma_clear_channel_error (uint8_t ch)
Clear the status of the error. More...

Detailed Description

DMA functions.

Function Documentation

◆ ald_usb_dma_channel_config()

void ald_usb_dma_channel_config | ( | uint8_t | ch,
 |  | uint32_t | addr,
 |  | uint32_t | count,
 |  | uint32_t | ctrl
 | ) |  |

Configure DMA's channel.

Parameters
ch | Channel.
addr | Address.
count | Size of the data to be moved.
ctrl | Parameters of the DMA's controler
Return values
None

Definition at line 1149 of file ald_usb.c.

1150 {
1151 USB0->DMA_CH[ch].DMA_ADDR = addr;
1152 USB0->DMA_CH[ch].DMA_COUNT = count;
1153 USB0->DMA_CH[ch].DMA_CNTL = ctrl;
1154 return;
1155 }

◆ ald_usb_dma_channel_start()

void ald_usb_dma_channel_start ( uint8_t ch )

Start DMA's machine.

Parameters
ch Channel.
Return values
None

Definition at line 1174 of file ald_usb.c.

1175 {
1176 USB0->DMA_CH[ch].DMA_CNTL |= 0x1;
1177 return;
1178 }

◆ ald_usb_dma_channel_stop()

void ald_usb_dma_channel_stop ( uint8_t ch )

Stop DMA's machine.

Parameters
ch Channel.
Return values
None

Definition at line 1185 of file ald_usb.c.

1186 {
1187 USB0->DMA_CH[ch].DMA_CNTL &= (uint32_t)(~0x1);
1188 return;
1189 }

◆ ald_usb_dma_clear_channel_error()

void ald_usb_dma_clear_channel_error ( uint8_t ch )

Clear the status of the error.

Parameters
ch Channel.
Return values
None

Definition at line 1218 of file ald_usb.c.

1219 {
1220 USB0->DMA_CH[ch].DMA_CNTL &= ~(USB_DMA_CH_ERR_MSK);
1221 }
USB_DMA_CH_ERR_MSK
#define USB_DMA_CH_ERR_MSK
Definition: ald_usb.h:432

◆ ald_usb_dma_get_channel_error()

uint32_t ald_usb_dma_get_channel_error ( uint8_t ch )

Gets the status of the error.

Parameters
ch Channel.
Return values
Status.

Definition at line 1205 of file ald_usb.c.

1206 {
1207 if (USB0->DMA_CH[ch].DMA_CNTL & USB_DMA_CH_ERR_MSK)
1208 return 1;
1209
1210 return 0;
1211 }
USB_DMA_CH_ERR_MSK
#define USB_DMA_CH_ERR_MSK
Definition: ald_usb.h:432

◆ ald_usb_dma_get_interrupt_flag()

uint32_t ald_usb_dma_get_interrupt_flag ( void )

Gets flags of the interrupt.

Return values
Flags of the interrupt.

Definition at line 1195 of file ald_usb.c.

1196 {
1197 return USB0->DMA_INTR;
1198 }

◆ ald_usb_dma_mult_recv_start()

void ald_usb_dma_mult_recv_start ( uint32_t ep_idx )

Start multiple receive.

Parameters
ep_idx Index of the endpoint
Return values
None

Definition at line 1162 of file ald_usb.c.

1163 {
1164 USB0->CSR[ep_idx - 1].RXxCSRH &= ~(USB_RXCSRH1_DMAMOD);
1165 return;
1166 }
USB_RXCSRH1_DMAMOD
#define USB_RXCSRH1_DMAMOD
Definition: ald_usb.h:68


ALD User Manual: LPM functions

Functions
LPM functions
EASTSOFT ES32F3xx ALD » USB » USB Public Function

LPM functions. More...

Collaboration diagram for LPM functions:

Functions

void | ald_usb_host_lpm_send (uint32_t addr, uint32_t ep_idx)
Transmit a LPM transaction in host mode. More...
void | ald_usb_host_lpm_config (uint32_t resume_time, uint32_t config)
Configure the LPM parameters in host mode. More...
uint32_t | ald_usb_lpm_remote_wake_is_enable (void)
Gets status of remote wakeup. More...
void | ald_usb_host_lpm_resume (void)
Initiate a RESUME from the L1 state in host mode. More...
void | ald_usb_dev_lpm_remote_wake (void)
Enable remote wakeup in device mode. More...
void | ald_usb_dev_lpm_config (uint32_t config)
Enable remote wakeup in device mode. More...
void | ald_usb_dev_lpm_enable (void)
Enable LPM in device mode. More...
void | ald_usb_dev_lpm_disable (void)
Disable LPM in device mode. More...
uint32_t | ald_usb_lpm_link_status_get (void)
Gets the link status. More...
uint32_t | ald_usb_lpm_ep_get (void)
Gets the index of the endpoint. More...
uint32_t | ald_usb_lpm_int_status_get (void)
Gets the status of the interrupt. More...
void | ald_usb_lpm_int_disable (uint32_t ints)
Disable the LPM interrupt. More...
void | ald_usb_lpm_int_enable (uint32_t ints)
Enable the LPM interrupt. More...

Detailed Description

LPM functions.

Function Documentation

◆ ald_usb_dev_lpm_config()

void ald_usb_dev_lpm_config ( uint32_t config )

Enable remote wakeup in device mode.

Return values
None

Definition at line 1300 of file ald_usb.c.

1301 {
1302 USB0->LPM_CNTRL = config;
1303 }

◆ ald_usb_dev_lpm_disable()

void ald_usb_dev_lpm_disable ( void )

Disable LPM in device mode.

Return values
None

Definition at line 1318 of file ald_usb.c.

1319 {
1320 USB0->LPM_CNTRL &= ~(USB_LPMCNTRL_LPMXMT);
1321 }
USB_LPMCNTRL_LPMXMT
#define USB_LPMCNTRL_LPMXMT
Definition: ald_usb.h:151

◆ ald_usb_dev_lpm_enable()

void ald_usb_dev_lpm_enable ( void )

Enable LPM in device mode.

Return values
None

Definition at line 1309 of file ald_usb.c.

1310 {
1311 USB0->LPM_CNTRL |= (USB_LPMCNTRL_LPMXMT | USB_LPMCNTRL_ENABLE);
1312 }
USB_LPMCNTRL_LPMXMT
#define USB_LPMCNTRL_LPMXMT
Definition: ald_usb.h:151
USB_LPMCNTRL_ENABLE
#define USB_LPMCNTRL_ENABLE
Definition: ald_usb.h:152

◆ ald_usb_dev_lpm_remote_wake()

void ald_usb_dev_lpm_remote_wake ( void )

Enable remote wakeup in device mode.

Return values
None

Definition at line 1291 of file ald_usb.c.

1292 {
1293 USB0->LPM_CNTRL |= USB_LPMCNTRL_LPMRES;
1294 }
USB_LPMCNTRL_LPMRES
#define USB_LPMCNTRL_LPMRES
Definition: ald_usb.h:150

◆ ald_usb_host_lpm_config()

void ald_usb_host_lpm_config | ( | uint32_t | resume_time,
 |  | uint32_t | config
 | ) |  |

Configure the LPM parameters in host mode.

Parameters
resume_time | Resume time.
config | Parameters
Return values
None

Definition at line 1255 of file ald_usb.c.

1256 {
1257 uint32_t tmp;
1258
1259 tmp = USB0->LPM_ATTR;
1260 tmp &= ~(USB_LPMATTR_HIRD_M);
1261 tmp |= ((((resume_time - 50) / 75) & 0xF) << USB_LPMATTR_HIRD_S);
1262 tmp |= config;
1263 USB0->LPM_ATTR = tmp;
1264 }
USB_LPMATTR_HIRD_S
#define USB_LPMATTR_HIRD_S
Definition: ald_usb.h:148
USB_LPMATTR_HIRD_M
#define USB_LPMATTR_HIRD_M
Definition: ald_usb.h:144

◆ ald_usb_host_lpm_resume()

void ald_usb_host_lpm_resume ( void )

Initiate a RESUME from the L1 state in host mode.

Return values
None

Definition at line 1282 of file ald_usb.c.

1283 {
1284 USB0->LPM_CNTRL |= USB_LPMCNTRL_LPMRES;
1285 }
USB_LPMCNTRL_LPMRES
#define USB_LPMCNTRL_LPMRES
Definition: ald_usb.h:150

◆ ald_usb_host_lpm_send()

void ald_usb_host_lpm_send | ( | uint32_t | addr,
 |  | uint32_t | ep_idx
 | ) |  |

Transmit a LPM transaction in host mode.

Parameters
addr | Address.
ep_idx | Index of the endpoint.
Return values
None

Definition at line 1236 of file ald_usb.c.

1237 {
1238 uint32_t tmp;
1239
1240 USB0->LPM_FADDR = addr;
1241
1242 tmp = USB0->LPM_ATTR & ~(USB_LPMATTR_ENDPT_M);
1243 tmp |= ep_idx << USB_LPMATTR_ENDPT_S;
1244
1245 USB0->LPM_ATTR = tmp;
1246 USB0->LPM_CNTRL |= USB_LPMCNTRL_LPMXMT;
1247 }
USB_LPMATTR_ENDPT_M
#define USB_LPMATTR_ENDPT_M
Definition: ald_usb.h:142
USB_LPMCNTRL_LPMXMT
#define USB_LPMCNTRL_LPMXMT
Definition: ald_usb.h:151
USB_LPMATTR_ENDPT_S
#define USB_LPMATTR_ENDPT_S
Definition: ald_usb.h:147

◆ ald_usb_lpm_ep_get()

uint32_t ald_usb_lpm_ep_get ( void )

Gets the index of the endpoint.

Return values
Index of the endpoint.

Definition at line 1336 of file ald_usb.c.

1337 {
1338 uint32_t tmp;
1339
1340 tmp = USB0->LPM_ATTR;
1341 tmp &= USB_LPMATTR_ENDPT_M;
1342 tmp = tmp >> USB_LPMATTR_ENDPT_S;
1343
1344 return tmp;
1345 }
USB_LPMATTR_ENDPT_M
#define USB_LPMATTR_ENDPT_M
Definition: ald_usb.h:142
USB_LPMATTR_ENDPT_S
#define USB_LPMATTR_ENDPT_S
Definition: ald_usb.h:147

◆ ald_usb_lpm_int_disable()

void ald_usb_lpm_int_disable ( uint32_t ints )

Disable the LPM interrupt.

Return values
None

Definition at line 1360 of file ald_usb.c.

1361 {
1362 USB0->LPM_INTREN &= ~ints;
1363 }

◆ ald_usb_lpm_int_enable()

void ald_usb_lpm_int_enable ( uint32_t ints )

Enable the LPM interrupt.

Return values
None

Definition at line 1369 of file ald_usb.c.

1370 {
1371 USB0->LPM_INTREN |= ints;
1372 }

◆ ald_usb_lpm_int_status_get()

uint32_t ald_usb_lpm_int_status_get ( void )

Gets the status of the interrupt.

Return values
Status.

Definition at line 1351 of file ald_usb.c.

1352 {
1353 return USB0->LPM_INTR;
1354 }

◆ ald_usb_lpm_link_status_get()

uint32_t ald_usb_lpm_link_status_get ( void )

Gets the link status.

Return values
Status

Definition at line 1327 of file ald_usb.c.

1328 {
1329 return (USB0->LPM_ATTR & USB_LPMATTR_LS_M);
1330 }
USB_LPMATTR_LS_M
#define USB_LPMATTR_LS_M
Definition: ald_usb.h:145

◆ ald_usb_lpm_remote_wake_is_enable()

uint32_t ald_usb_lpm_remote_wake_is_enable ( void )

Gets status of remote wakeup.

Return values
Status.

Definition at line 1270 of file ald_usb.c.

1271 {
1272 if (USB0->LPM_ATTR & USB_LPMATTR_RMTWAK)
1273 return 1;
1274
1275 return 0;
1276 }
USB_LPMATTR_RMTWAK
#define USB_LPMATTR_RMTWAK
Definition: ald_usb.h:143


ALD User Manual: USB Public Macros

Macros
USB Public Macros
EASTSOFT ES32F3xx ALD » USB
Collaboration diagram for USB Public Macros:

Macros

#define | USB_POWER_ISOUP 0x00000080U
#define | USB_POWER_SOFTCONN 0x00000040U
#define | USB_POWER_HS_EN 0x00000020U
#define | USB_POWER_HS_M 0x00000010U
#define | USB_POWER_RESET 0x00000008U
#define | USB_POWER_RESUME 0x00000004U
#define | USB_POWER_SUSPEND 0x00000002U
#define | USB_POWER_PWRDNPHY 0x00000001U
#define | USB_DEVCTL_DEV 0x00000080U
#define | USB_DEVCTL_FSDEV 0x00000040U
#define | USB_DEVCTL_LSDEV 0x00000020U
#define | USB_DEVCTL_VBUS_M 0x00000018U
#define | USB_DEVCTL_VBUS_NONE 0x00000000U
#define | USB_DEVCTL_VBUS_SEND 0x00000008U
#define | USB_DEVCTL_VBUS_AVALID 0x00000010U
#define | USB_DEVCTL_VBUS_VALID 0x00000018U
#define | USB_DEVCTL_HOST 0x00000004U
#define | USB_DEVCTL_HOSTREQ 0x00000002U
#define | USB_DEVCTL_SESSION 0x00000001U
#define | USB_RXCSRH1_AUTOCL 0x00000080U
#define | USB_RXCSRH1_AUTORQ 0x00000040U
#define | USB_RXCSRH1_ISO 0x00000040U
#define | USB_RXCSRH1_DMAEN 0x00000020U
#define | USB_RXCSRH1_DISNYET 0x00000010U
#define | USB_RXCSRH1_PIDERR 0x00000010U
#define | USB_RXCSRH1_DMAMOD 0x00000008U
#define | USB_RXCSRH1_DTWE 0x00000004U
#define | USB_RXCSRH1_DT 0x00000002U
#define | USB_RXCSRH1_INCOMPRX 0x00000001U
#define | USB_CSRH0_DISPING 0x00000008U
#define | USB_CSRH0_DTWE 0x00000004U
#define | USB_CSRH0_DT 0x00000002U
#define | USB_CSRH0_FLUSH 0x00000001U
#define | USB_TXCSRH1_AUTOSET 0x00000080U
#define | USB_TXCSRH1_ISO 0x00000040U
#define | USB_TXCSRH1_MODE 0x00000020U
#define | USB_TXCSRH1_DMAEN 0x00000010U
#define | USB_TXCSRH1_FDT 0x00000008U
#define | USB_TXCSRH1_DMAMOD 0x00000004U
#define | USB_TXCSRH1_DTWE 0x00000002U
#define | USB_TXCSRH1_DT 0x00000001U
#define | USB_TXCSRL1_NAKTO 0x00000080U
#define | USB_TXCSRL1_CLRDT 0x00000040U
#define | USB_TXCSRL1_STALLED 0x00000020U
#define | USB_TXCSRL1_STALL 0x00000010U
#define | USB_TXCSRL1_SETUP 0x00000010U
#define | USB_TXCSRL1_FLUSH 0x00000008U
#define | USB_TXCSRL1_ERROR 0x00000004U
#define | USB_TXCSRL1_UNDRN 0x00000004U
#define | USB_TXCSRL1_FIFONE 0x00000002U
#define | USB_TXCSRL1_TXRDY 0x00000001U
#define | USB_RXCSRL1_CLRDT 0x00000080U
#define | USB_RXCSRL1_STALLED 0x00000040U
#define | USB_RXCSRL1_STALL 0x00000020U
#define | USB_RXCSRL1_REQPKT 0x00000020U
#define | USB_RXCSRL1_FLUSH 0x00000010U
#define | USB_RXCSRL1_DATAERR 0x00000008U
#define | USB_RXCSRL1_NAKTO 0x00000008U
#define | USB_RXCSRL1_OVER 0x00000004U
#define | USB_RXCSRL1_ERROR 0x00000004U
#define | USB_RXCSRL1_FULL 0x00000002U
#define | USB_RXCSRL1_RXRDY 0x00000001U
#define | USB_CSRL0_NAKTO 0x00000080U
#define | USB_CSRL0_SETENDC 0x00000080U
#define | USB_CSRL0_STATUS 0x00000040U
#define | USB_CSRL0_RXRDYC 0x00000040U
#define | USB_CSRL0_REQPKT 0x00000020U
#define | USB_CSRL0_STALL 0x00000020U
#define | USB_CSRL0_SETEND 0x00000010U
#define | USB_CSRL0_ERROR 0x00000010U
#define | USB_CSRL0_DATAEND 0x00000008U
#define | USB_CSRL0_SETUP 0x00000008U
#define | USB_CSRL0_STALLED 0x00000004U
#define | USB_CSRL0_TXRDY 0x00000002U
#define | USB_CSRL0_RXRDY 0x00000001U
#define | USB_TYPE0_SPEED_M 0x000000C0U
#define | USB_TYPE0_SPEED_HIGH 0x00000040U
#define | USB_TYPE0_SPEED_FULL 0x00000080U
#define | USB_TYPE0_SPEED_LOW 0x000000C0U
#define | USB_TXTYPE1_SPEED_M 0x000000C0U
#define | USB_TXTYPE1_SPEED_DFLT 0x00000000U
#define | USB_TXTYPE1_SPEED_HIGH 0x00000040U
#define | USB_TXTYPE1_SPEED_FULL 0x00000080U
#define | USB_TXTYPE1_SPEED_LOW 0x000000C0U
#define | USB_TXTYPE1_PROTO_M 0x00000030U
#define | USB_TXTYPE1_PROTO_CTRL 0x00000000U
#define | USB_TXTYPE1_PROTO_ISOC 0x00000010U
#define | USB_TXTYPE1_PROTO_BULK 0x00000020U
#define | USB_TXTYPE1_PROTO_INT 0x00000030U
#define | USB_TXTYPE1_TEP_M 0x0000000FU
#define | USB_TXTYPE1_TEP_S 0U
#define | USB_LPMATTR_ENDPT_M 0x0000F000U
#define | USB_LPMATTR_RMTWAK 0x00000100U
#define | USB_LPMATTR_HIRD_M 0x000000F0U
#define | USB_LPMATTR_LS_M 0x0000000FU
#define | USB_LPMATTR_LS_L1 0x00000001U
#define | USB_LPMATTR_ENDPT_S 12U
#define | USB_LPMATTR_HIRD_S 4U
#define | USB_LPMCNTRL_LPMRES 0x00000002U
#define | USB_LPMCNTRL_LPMXMT 0x00000001U
#define | USB_LPMCNTRL_ENABLE 0x00000006U
#define | USB_LPMCNTRL_DISABLE 0x00000000U
#define | USB_INTCTRL_ALL 0x000003FFU
#define | USB_INTCTRL_STATUS 0x000000FFU
#define | USB_INTCTRL_VBUS_ERR 0x00000080U
#define | USB_INTCTRL_SESSION 0x00000040U
#define | USB_INTCTRL_SESSION_END 0x00000040U
#define | USB_INTCTRL_DISCONNECT 0x00000020U
#define | USB_INTCTRL_CONNECT 0x00000010U
#define | USB_INTCTRL_SOF 0x00000008U
#define | USB_INTCTRL_BABBLE 0x00000004U
#define | USB_INTCTRL_RESET 0x00000004U
#define | USB_INTCTRL_RESUME 0x00000002U
#define | USB_INTCTRL_SUSPEND 0x00000001U
#define | USB_INTCTRL_MODE_DETECT 0x00000200U
#define | USB_INTCTRL_POWER_FAULT 0x00000100U
#define | USB_INTEP_ALL 0xFFFFFFFFU
#define | USB_INTEP_HOST_IN 0xFFFE0000U
#define | USB_INTEP_HOST_IN_15 0x80000000U
#define | USB_INTEP_HOST_IN_14 0x40000000U
#define | USB_INTEP_HOST_IN_13 0x20000000U
#define | USB_INTEP_HOST_IN_12 0x10000000U
#define | USB_INTEP_HOST_IN_11 0x08000000U
#define | USB_INTEP_HOST_IN_10 0x04000000U
#define | USB_INTEP_HOST_IN_9 0x02000000U
#define | USB_INTEP_HOST_IN_8 0x01000000U
#define | USB_INTEP_HOST_IN_7 0x00800000U
#define | USB_INTEP_HOST_IN_6 0x00400000U
#define | USB_INTEP_HOST_IN_5 0x00200000U
#define | USB_INTEP_HOST_IN_4 0x00100000U
#define | USB_INTEP_HOST_IN_3 0x00080000U
#define | USB_INTEP_HOST_IN_2 0x00040000U
#define | USB_INTEP_HOST_IN_1 0x00020000U
#define | USB_INTEP_DEV_OUT 0xFFFE0000U
#define | USB_INTEP_DEV_OUT_15 0x80000000U
#define | USB_INTEP_DEV_OUT_14 0x40000000U
#define | USB_INTEP_DEV_OUT_13 0x20000000U
#define | USB_INTEP_DEV_OUT_12 0x10000000U
#define | USB_INTEP_DEV_OUT_11 0x08000000U
#define | USB_INTEP_DEV_OUT_10 0x04000000U
#define | USB_INTEP_DEV_OUT_9 0x02000000U
#define | USB_INTEP_DEV_OUT_8 0x01000000U
#define | USB_INTEP_DEV_OUT_7 0x00800000U
#define | USB_INTEP_DEV_OUT_6 0x00400000U
#define | USB_INTEP_DEV_OUT_5 0x00200000U
#define | USB_INTEP_DEV_OUT_4 0x00100000U
#define | USB_INTEP_DEV_OUT_3 0x00080000U
#define | USB_INTEP_DEV_OUT_2 0x00040000U
#define | USB_INTEP_DEV_OUT_1 0x00020000U
#define | USB_INTEP_HOST_OUT 0x0000FFFEU
#define | USB_INTEP_HOST_OUT_15 0x00008000U
#define | USB_INTEP_HOST_OUT_14 0x00004000U
#define | USB_INTEP_HOST_OUT_13 0x00002000U
#define | USB_INTEP_HOST_OUT_12 0x00001000U
#define | USB_INTEP_HOST_OUT_11 0x00000800U
#define | USB_INTEP_HOST_OUT_10 0x00000400U
#define | USB_INTEP_HOST_OUT_9 0x00000200U
#define | USB_INTEP_HOST_OUT_8 0x00000100U
#define | USB_INTEP_HOST_OUT_7 0x00000080U
#define | USB_INTEP_HOST_OUT_6 0x00000040U
#define | USB_INTEP_HOST_OUT_5 0x00000020U
#define | USB_INTEP_HOST_OUT_4 0x00000010U
#define | USB_INTEP_HOST_OUT_3 0x00000008U
#define | USB_INTEP_HOST_OUT_2 0x00000004U
#define | USB_INTEP_HOST_OUT_1 0x00000002U
#define | USB_INTEP_DEV_IN 0x0000FFFEU
#define | USB_INTEP_DEV_IN_15 0x00008000U
#define | USB_INTEP_DEV_IN_14 0x00004000U
#define | USB_INTEP_DEV_IN_13 0x00002000U
#define | USB_INTEP_DEV_IN_12 0x00001000U
#define | USB_INTEP_DEV_IN_11 0x00000800U
#define | USB_INTEP_DEV_IN_10 0x00000400U
#define | USB_INTEP_DEV_IN_9 0x00000200U
#define | USB_INTEP_DEV_IN_8 0x00000100U
#define | USB_INTEP_DEV_IN_7 0x00000080U
#define | USB_INTEP_DEV_IN_6 0x00000040U
#define | USB_INTEP_DEV_IN_5 0x00000020U
#define | USB_INTEP_DEV_IN_4 0x00000010U
#define | USB_INTEP_DEV_IN_3 0x00000008U
#define | USB_INTEP_DEV_IN_2 0x00000004U
#define | USB_INTEP_DEV_IN_1 0x00000002U
#define | USB_INTEP_0 0x00000001U
#define | USB_UNDEF_SPEED 0x80000000U
#define | USB_HIGH_SPEED 0x00000002U
#define | USB_FULL_SPEED 0x00000001U
#define | USB_LOW_SPEED 0x00000000U
#define | USB_HOST_IN_STATUS 0x114F0000U
#define | USB_HOST_IN_PID_ERROR 0x10000000U
#define | USB_HOST_IN_NOT_COMP 0x01000000U
#define | USB_HOST_IN_STALL 0x00400000U
#define | USB_HOST_IN_DATA_ERROR 0x00080000U
#define | USB_HOST_IN_NAK_TO 0x00080000U
#define | USB_HOST_IN_ERROR 0x00040000U
#define | USB_HOST_IN_FIFO_FULL 0x00020000U
#define | USB_HOST_IN_PKTRDY 0x00010000U
#define | USB_HOST_OUT_STATUS 0x000000A7U
#define | USB_HOST_OUT_NAK_TO 0x00000080U
#define | USB_HOST_OUT_NOT_COMP 0x00000080U
#define | USB_HOST_OUT_STALL 0x00000020U
#define | USB_HOST_OUT_ERROR 0x00000004U
#define | USB_HOST_OUT_FIFO_NE 0x00000002U
#define | USB_HOST_OUT_PKTPEND 0x00000001U
#define | USB_HOST_EP0_NAK_TO 0x00000080U
#define | USB_HOST_EP0_STATUS 0x00000040U
#define | USB_HOST_EP0_ERROR 0x00000010U
#define | USB_HOST_EP0_RX_STALL 0x00000004U
#define | USB_HOST_EP0_RXPKTRDY 0x00000001U
#define | USB_DEV_RX_PID_ERROR 0x01000000U
#define | USB_DEV_RX_SENT_STALL 0x00400000U
#define | USB_DEV_RX_DATA_ERROR 0x00080000U
#define | USB_DEV_RX_OVERRUN 0x00040000U
#define | USB_DEV_RX_FIFO_FULL 0x00020000U
#define | USB_DEV_RX_PKT_RDY 0x00010000U
#define | USB_DEV_TX_NOT_COMP 0x00000080U
#define | USB_DEV_TX_SENT_STALL 0x00000020U
#define | USB_DEV_TX_UNDERRUN 0x00000004U
#define | USB_DEV_TX_FIFO_NE 0x00000002U
#define | USB_DEV_TX_TXPKTRDY 0x00000001U
#define | USB_DEV_EP0_SETUP_END 0x00000010U
#define | USB_DEV_EP0_SENT_STALL 0x00000004U
#define | USB_DEV_EP0_IN_PKTPEND 0x00000002U
#define | USB_DEV_EP0_OUT_PKTRDY 0x00000001U
#define | USB_EP_AUTO_SET 0x00000001U
#define | USB_EP_AUTO_REQUEST 0x00000002U
#define | USB_EP_AUTO_CLEAR 0x00000004U
#define | USB_EP_DMA_MODE_0 0x00000008U
#define | USB_EP_DMA_MODE_1 0x00000010U
#define | USB_EP_DIS_NYET 0x00000020U
#define | USB_EP_MODE_ISOC 0x00000000U
#define | USB_EP_MODE_BULK 0x00000100U
#define | USB_EP_MODE_INT 0x00000200U
#define | USB_EP_MODE_CTRL 0x00000300U
#define | USB_EP_MODE_MASK 0x00000300U
#define | USB_EP_SPEED_LOW 0x00000000U
#define | USB_EP_SPEED_FULL 0x00001000U
#define | USB_EP_SPEED_HIGH 0x00004000U
#define | USB_EP_HOST_IN 0x00000000U
#define | USB_EP_HOST_OUT 0x00002000U
#define | USB_EP_DEV_IN 0x00002000U
#define | USB_EP_DEV_OUT 0x00000000U
#define | USB_HOST_PWRFLT_LOW 0x00000010U
#define | USB_HOST_PWRFLT_HIGH 0x00000030U
#define | USB_HOST_PWRFLT_EP_NONE 0x00000000U
#define | USB_HOST_PWRFLT_EP_TRI 0x00000140U
#define | USB_HOST_PWRFLT_EP_LOW 0x00000240U
#define | USB_HOST_PWRFLT_EP_HIGH 0x00000340U
#define | USB_HOST_PWREN_MAN_LOW 0x00000000U
#define | USB_HOST_PWREN_MAN_HIGH 0x00000001U
#define | USB_HOST_PWREN_AUTOLOW 0x00000002U
#define | USB_HOST_PWREN_AUTOHIGH 0x00000003U
#define | USB_HOST_PWREN_FILTER 0x00010000U
#define | USB_HOST_LPM_RMTWAKE 0x00000100U
#define | USB_HOST_LPM_L1 0x00000001U
#define | USB_DEV_LPM_NAK 0x00000010U
#define | USB_DEV_LPM_NONE 0x00000000U
#define | USB_DEV_LPM_EN 0x0000000cU
#define | USB_DEV_LPM_EXTONLY 0x00000004U
#define | USB_DEV_LPM_LS_RMTWAKE 0x00000100U
#define | USB_DEV_LPM_LS_L1 0x00000001U
#define | USB_INTLPM_ERROR 0x00000020U
#define | USB_INTLPM_RESUME 0x00000010U
#define | USB_INTLPM_INCOMPLETE 0x00000008U
#define | USB_INTLPM_ACK 0x00000004U
#define | USB_INTLPM_NYET 0x00000002U
#define | USB_INTLPM_STALL 0x00000001U
#define | MAX_NAK_LIMIT 31U
#define | DISABLE_NAK_LIMIT 0U
#define | MAX_PACKET_SIZE_EP0 64U
#define | USB_EP_0 0U
#define | USB_EP_1 1U
#define | USB_EP_2 2U
#define | USB_EP_3 3U
#define | USB_EP_4 4U
#define | USB_EP_5 5U
#define | NUM_USB_EP 6U
#define | IndexToUSBEP(x) ((x))
#define | USBEPToIndex(x) ((x))
#define | USB_FIFO_SZ_8 0x00000000U
#define | USB_FIFO_SZ_16 0x00000001U
#define | USB_FIFO_SZ_32 0x00000002U
#define | USB_FIFO_SZ_64 0x00000003U
#define | USB_FIFO_SZ_128 0x00000004U
#define | USB_FIFO_SZ_256 0x00000005U
#define | USB_FIFO_SZ_512 0x00000006U
#define | USB_FIFO_SZ_1024 0x00000007U
#define | USB_FIFO_SZ_2048 0x00000008U
#define | USBFIFOSizeToBytes(x) (8 << (x))
#define | USB_TRANS_OUT 0x00000102U
#define | USB_TRANS_IN 0x00000102U
#define | USB_TRANS_IN_LAST 0x0000010aU
#define | USB_TRANS_SETUP 0x0000110aU
#define | USB_TRANS_STATUS 0x00000142U
#define | USB_DUAL_MODE_HOST 0x00000001U
#define | USB_DUAL_MODE_DEVICE 0x00000081U
#define | USB_DUAL_MODE_NONE 0x00000080U
#define | USB_OTG_MODE_ASIDE_HOST 0x0000001dU
#define | USB_OTG_MODE_ASIDE_NPWR 0x00000001U
#define | USB_OTG_MODE_ASIDE_SESS 0x00000009U
#define | USB_OTG_MODE_ASIDE_AVAL 0x00000011U
#define | USB_OTG_MODE_ASIDE_DEV 0x00000019U
#define | USB_OTG_MODE_BSIDE_HOST 0x0000009dU
#define | USB_OTG_MODE_BSIDE_DEV 0x00000099U
#define | USB_OTG_MODE_BSIDE_NPWR 0x00000081U
#define | USB_OTG_MODE_NONE 0x00000080U
#define | USB_DMA_INT_CH8 0x00000080U
#define | USB_DMA_INT_CH7 0x00000040U
#define | USB_DMA_INT_CH6 0x00000020U
#define | USB_DMA_INT_CH5 0x00000010U
#define | USB_DMA_INT_CH4 0x00000008U
#define | USB_DMA_INT_CH3 0x00000004U
#define | USB_DMA_INT_CH2 0x00000002U
#define | USB_DMA_INT_CH1 0x00000001U
#define | USB_DMA_EP_CFG_TX 0x00000001U
#define | USB_DMA_EP_CFG_RX_DEV 0x00000002U
#define | USB_DMA_EP_CFG_RX_HOST 0x00000004U
#define | USB_DMA_EP_TX_MSK 0x94U
#define | USB_DMA_EP_RX_DEV_MSK 0xA8U
#define | USB_DMA_EP_RX_HOST_MSK 0xE8U
#define | USB_DMA_STATUS_ERROR 0x00000100U
#define | USB_MODE_HOST_VBUS 0x00000004U
#define | USB_MODE_HOST 0x00000002U
#define | USB_MODE_DEV_VBUS 0x00000005U
#define | USB_MODE_DEV 0x00000003U
#define | USB_MODE_OTG 0x00000000U
#define | USB_RX_EPSTATUS_SHIFT 16U
#define | USB_INTEP_RX_SHIFT 16U
#define | USB_DMA_CFG_START 0x00000001U
#define | USB_DMA_CFG_START_NO 0x00000000U
#define | USB_DMA_CFG_DIR_WR 0x00000000U
#define | USB_DMA_CFG_DIR_RD 0x00000002U
#define | USB_DMA_CFG_MODE_0 0x00000000U
#define | USB_DMA_CFG_MODE_1 0x00000004U
#define | USB_DMA_CFG_IE_DIS 0x00000000U
#define | USB_DMA_CFG_IE_EN 0x00000008U
#define | USB_DMA_CFG_EP_1 0x00000010U
#define | USB_DMA_CFG_EP_2 0x00000020U
#define | USB_DMA_CFG_EP_3 0x00000030U
#define | USB_DMA_CFG_EP_4 0x00000040U
#define | USB_DMA_CFG_EP_5 0x00000050U
#define | USB_DMA_CFG_BURST_NONE 0x00000000U
#define | USB_DMA_CFG_BURST_4 0x00000200U
#define | USB_DMA_CFG_BURST_8 0x00000400U
#define | USB_DMA_CFG_BURST_16 0x00000600U
#define | USB_DMA_CFG_MODE_MSK 0x00000004U
#define | USB_DMA_CFG_EP_POS 0x00000004U
#define | USB_DMA_CFG_EP_MSK 0x000000F0U
#define | USB_DMA_CH_ERR_MSK 0x100U

Detailed Description

Macro Definition Documentation

◆ DISABLE_NAK_LIMIT

#define DISABLE_NAK_LIMIT 0U

Definition at line 344 of file ald_usb.h.

◆ IndexToUSBEP

#define IndexToUSBEP ( x ) ((x))

Definition at line 354 of file ald_usb.h.

◆ MAX_NAK_LIMIT

#define MAX_NAK_LIMIT 31U

Definition at line 343 of file ald_usb.h.

◆ MAX_PACKET_SIZE_EP0

#define MAX_PACKET_SIZE_EP0 64U

Definition at line 346 of file ald_usb.h.

◆ NUM_USB_EP

#define NUM_USB_EP 6U

Definition at line 353 of file ald_usb.h.

◆ USB_CSRH0_DISPING

#define USB_CSRH0_DISPING 0x00000008U

Definition at line 73 of file ald_usb.h.

◆ USB_CSRH0_DT

#define USB_CSRH0_DT 0x00000002U

Definition at line 75 of file ald_usb.h.

◆ USB_CSRH0_DTWE

#define USB_CSRH0_DTWE 0x00000004U

Definition at line 74 of file ald_usb.h.

◆ USB_CSRH0_FLUSH

#define USB_CSRH0_FLUSH 0x00000001U

Definition at line 76 of file ald_usb.h.

◆ USB_CSRL0_DATAEND

#define USB_CSRL0_DATAEND 0x00000008U

Definition at line 118 of file ald_usb.h.

◆ USB_CSRL0_ERROR

#define USB_CSRL0_ERROR 0x00000010U

Definition at line 117 of file ald_usb.h.

◆ USB_CSRL0_NAKTO

#define USB_CSRL0_NAKTO 0x00000080U

Definition at line 110 of file ald_usb.h.

◆ USB_CSRL0_REQPKT

#define USB_CSRL0_REQPKT 0x00000020U

Definition at line 114 of file ald_usb.h.

◆ USB_CSRL0_RXRDY

#define USB_CSRL0_RXRDY 0x00000001U

Definition at line 122 of file ald_usb.h.

◆ USB_CSRL0_RXRDYC

#define USB_CSRL0_RXRDYC 0x00000040U

Definition at line 113 of file ald_usb.h.

◆ USB_CSRL0_SETEND

#define USB_CSRL0_SETEND 0x00000010U

Definition at line 116 of file ald_usb.h.

◆ USB_CSRL0_SETENDC

#define USB_CSRL0_SETENDC 0x00000080U

Definition at line 111 of file ald_usb.h.

◆ USB_CSRL0_SETUP

#define USB_CSRL0_SETUP 0x00000008U

Definition at line 119 of file ald_usb.h.

◆ USB_CSRL0_STALL

#define USB_CSRL0_STALL 0x00000020U

Definition at line 115 of file ald_usb.h.

◆ USB_CSRL0_STALLED

#define USB_CSRL0_STALLED 0x00000004U

Definition at line 120 of file ald_usb.h.

◆ USB_CSRL0_STATUS

#define USB_CSRL0_STATUS 0x00000040U

Definition at line 112 of file ald_usb.h.

◆ USB_CSRL0_TXRDY

#define USB_CSRL0_TXRDY 0x00000002U

Definition at line 121 of file ald_usb.h.

◆ USB_DEV_EP0_IN_PKTPEND

#define USB_DEV_EP0_IN_PKTPEND 0x00000002U

Definition at line 292 of file ald_usb.h.

◆ USB_DEV_EP0_OUT_PKTRDY

#define USB_DEV_EP0_OUT_PKTRDY 0x00000001U

Definition at line 293 of file ald_usb.h.

◆ USB_DEV_EP0_SENT_STALL

#define USB_DEV_EP0_SENT_STALL 0x00000004U

Definition at line 291 of file ald_usb.h.

◆ USB_DEV_EP0_SETUP_END

#define USB_DEV_EP0_SETUP_END 0x00000010U

Definition at line 289 of file ald_usb.h.

◆ USB_DEV_LPM_EN

#define USB_DEV_LPM_EN 0x0000000cU

Definition at line 332 of file ald_usb.h.

◆ USB_DEV_LPM_EXTONLY

#define USB_DEV_LPM_EXTONLY 0x00000004U

Definition at line 333 of file ald_usb.h.

◆ USB_DEV_LPM_LS_L1

#define USB_DEV_LPM_LS_L1 0x00000001U

Definition at line 335 of file ald_usb.h.

◆ USB_DEV_LPM_LS_RMTWAKE

#define USB_DEV_LPM_LS_RMTWAKE 0x00000100U

Definition at line 334 of file ald_usb.h.

◆ USB_DEV_LPM_NAK

#define USB_DEV_LPM_NAK 0x00000010U

Definition at line 330 of file ald_usb.h.

◆ USB_DEV_LPM_NONE

#define USB_DEV_LPM_NONE 0x00000000U

Definition at line 331 of file ald_usb.h.

◆ USB_DEV_RX_DATA_ERROR

#define USB_DEV_RX_DATA_ERROR 0x00080000U

Definition at line 278 of file ald_usb.h.

◆ USB_DEV_RX_FIFO_FULL

#define USB_DEV_RX_FIFO_FULL 0x00020000U

Definition at line 281 of file ald_usb.h.

◆ USB_DEV_RX_OVERRUN

#define USB_DEV_RX_OVERRUN 0x00040000U

Definition at line 279 of file ald_usb.h.

◆ USB_DEV_RX_PID_ERROR

#define USB_DEV_RX_PID_ERROR 0x01000000U

Definition at line 275 of file ald_usb.h.

◆ USB_DEV_RX_PKT_RDY

#define USB_DEV_RX_PKT_RDY 0x00010000U

Definition at line 282 of file ald_usb.h.

◆ USB_DEV_RX_SENT_STALL

#define USB_DEV_RX_SENT_STALL 0x00400000U

Definition at line 277 of file ald_usb.h.

◆ USB_DEV_TX_FIFO_NE

#define USB_DEV_TX_FIFO_NE 0x00000002U

Definition at line 287 of file ald_usb.h.

◆ USB_DEV_TX_NOT_COMP

#define USB_DEV_TX_NOT_COMP 0x00000080U

Definition at line 283 of file ald_usb.h.

◆ USB_DEV_TX_SENT_STALL

#define USB_DEV_TX_SENT_STALL 0x00000020U

Definition at line 285 of file ald_usb.h.

◆ USB_DEV_TX_TXPKTRDY

#define USB_DEV_TX_TXPKTRDY 0x00000001U

Definition at line 288 of file ald_usb.h.

◆ USB_DEV_TX_UNDERRUN

#define USB_DEV_TX_UNDERRUN 0x00000004U

Definition at line 286 of file ald_usb.h.

◆ USB_DEVCTL_DEV

#define USB_DEVCTL_DEV 0x00000080U

Definition at line 50 of file ald_usb.h.

◆ USB_DEVCTL_FSDEV

#define USB_DEVCTL_FSDEV 0x00000040U

Definition at line 51 of file ald_usb.h.

◆ USB_DEVCTL_HOST

#define USB_DEVCTL_HOST 0x00000004U

Definition at line 58 of file ald_usb.h.

◆ USB_DEVCTL_HOSTREQ

#define USB_DEVCTL_HOSTREQ 0x00000002U

Definition at line 59 of file ald_usb.h.

◆ USB_DEVCTL_LSDEV

#define USB_DEVCTL_LSDEV 0x00000020U

Definition at line 52 of file ald_usb.h.

◆ USB_DEVCTL_SESSION

#define USB_DEVCTL_SESSION 0x00000001U

Definition at line 60 of file ald_usb.h.

◆ USB_DEVCTL_VBUS_AVALID

#define USB_DEVCTL_VBUS_AVALID 0x00000010U

Definition at line 56 of file ald_usb.h.

◆ USB_DEVCTL_VBUS_M

#define USB_DEVCTL_VBUS_M 0x00000018U

Definition at line 53 of file ald_usb.h.

◆ USB_DEVCTL_VBUS_NONE

#define USB_DEVCTL_VBUS_NONE 0x00000000U

Definition at line 54 of file ald_usb.h.

◆ USB_DEVCTL_VBUS_SEND

#define USB_DEVCTL_VBUS_SEND 0x00000008U

Definition at line 55 of file ald_usb.h.

◆ USB_DEVCTL_VBUS_VALID

#define USB_DEVCTL_VBUS_VALID 0x00000018U

Definition at line 57 of file ald_usb.h.

◆ USB_DMA_CFG_BURST_16

#define USB_DMA_CFG_BURST_16 0x00000600U

Definition at line 428 of file ald_usb.h.

◆ USB_DMA_CFG_BURST_4

#define USB_DMA_CFG_BURST_4 0x00000200U

Definition at line 426 of file ald_usb.h.

◆ USB_DMA_CFG_BURST_8

#define USB_DMA_CFG_BURST_8 0x00000400U

Definition at line 427 of file ald_usb.h.

◆ USB_DMA_CFG_BURST_NONE

#define USB_DMA_CFG_BURST_NONE 0x00000000U

Definition at line 425 of file ald_usb.h.

◆ USB_DMA_CFG_DIR_RD

#define USB_DMA_CFG_DIR_RD 0x00000002U

Definition at line 415 of file ald_usb.h.

◆ USB_DMA_CFG_DIR_WR

#define USB_DMA_CFG_DIR_WR 0x00000000U

Definition at line 414 of file ald_usb.h.

◆ USB_DMA_CFG_EP_1

#define USB_DMA_CFG_EP_1 0x00000010U

Definition at line 420 of file ald_usb.h.

◆ USB_DMA_CFG_EP_2

#define USB_DMA_CFG_EP_2 0x00000020U

Definition at line 421 of file ald_usb.h.

◆ USB_DMA_CFG_EP_3

#define USB_DMA_CFG_EP_3 0x00000030U

Definition at line 422 of file ald_usb.h.

◆ USB_DMA_CFG_EP_4

#define USB_DMA_CFG_EP_4 0x00000040U

Definition at line 423 of file ald_usb.h.

◆ USB_DMA_CFG_EP_5

#define USB_DMA_CFG_EP_5 0x00000050U

Definition at line 424 of file ald_usb.h.

◆ USB_DMA_CFG_EP_MSK

#define USB_DMA_CFG_EP_MSK 0x000000F0U

Definition at line 431 of file ald_usb.h.

◆ USB_DMA_CFG_EP_POS

#define USB_DMA_CFG_EP_POS 0x00000004U

Definition at line 430 of file ald_usb.h.

◆ USB_DMA_CFG_IE_DIS

#define USB_DMA_CFG_IE_DIS 0x00000000U

Definition at line 418 of file ald_usb.h.

◆ USB_DMA_CFG_IE_EN

#define USB_DMA_CFG_IE_EN 0x00000008U

Definition at line 419 of file ald_usb.h.

◆ USB_DMA_CFG_MODE_0

#define USB_DMA_CFG_MODE_0 0x00000000U

Definition at line 416 of file ald_usb.h.

◆ USB_DMA_CFG_MODE_1

#define USB_DMA_CFG_MODE_1 0x00000004U

Definition at line 417 of file ald_usb.h.

◆ USB_DMA_CFG_MODE_MSK

#define USB_DMA_CFG_MODE_MSK 0x00000004U

Definition at line 429 of file ald_usb.h.

◆ USB_DMA_CFG_START

#define USB_DMA_CFG_START 0x00000001U

Definition at line 412 of file ald_usb.h.

◆ USB_DMA_CFG_START_NO

#define USB_DMA_CFG_START_NO 0x00000000U

Definition at line 413 of file ald_usb.h.

◆ USB_DMA_CH_ERR_MSK

#define USB_DMA_CH_ERR_MSK 0x100U

Definition at line 432 of file ald_usb.h.

◆ USB_DMA_EP_CFG_RX_DEV

#define USB_DMA_EP_CFG_RX_DEV 0x00000002U

Definition at line 396 of file ald_usb.h.

◆ USB_DMA_EP_CFG_RX_HOST

#define USB_DMA_EP_CFG_RX_HOST 0x00000004U

Definition at line 397 of file ald_usb.h.

◆ USB_DMA_EP_CFG_TX

#define USB_DMA_EP_CFG_TX 0x00000001U

Definition at line 395 of file ald_usb.h.

◆ USB_DMA_EP_RX_DEV_MSK

#define USB_DMA_EP_RX_DEV_MSK 0xA8U

Definition at line 399 of file ald_usb.h.

◆ USB_DMA_EP_RX_HOST_MSK

#define USB_DMA_EP_RX_HOST_MSK 0xE8U

Definition at line 400 of file ald_usb.h.

◆ USB_DMA_EP_TX_MSK

#define USB_DMA_EP_TX_MSK 0x94U

Definition at line 398 of file ald_usb.h.

◆ USB_DMA_INT_CH1

#define USB_DMA_INT_CH1 0x00000001U

Definition at line 394 of file ald_usb.h.

◆ USB_DMA_INT_CH2

#define USB_DMA_INT_CH2 0x00000002U

Definition at line 393 of file ald_usb.h.

◆ USB_DMA_INT_CH3

#define USB_DMA_INT_CH3 0x00000004U

Definition at line 392 of file ald_usb.h.

◆ USB_DMA_INT_CH4

#define USB_DMA_INT_CH4 0x00000008U

Definition at line 391 of file ald_usb.h.

◆ USB_DMA_INT_CH5

#define USB_DMA_INT_CH5 0x00000010U

Definition at line 390 of file ald_usb.h.

◆ USB_DMA_INT_CH6

#define USB_DMA_INT_CH6 0x00000020U

Definition at line 389 of file ald_usb.h.

◆ USB_DMA_INT_CH7

#define USB_DMA_INT_CH7 0x00000040U

Definition at line 388 of file ald_usb.h.

◆ USB_DMA_INT_CH8

#define USB_DMA_INT_CH8 0x00000080U

Definition at line 387 of file ald_usb.h.

◆ USB_DMA_STATUS_ERROR

#define USB_DMA_STATUS_ERROR 0x00000100U

Definition at line 401 of file ald_usb.h.

◆ USB_DUAL_MODE_DEVICE

#define USB_DUAL_MODE_DEVICE 0x00000081U

Definition at line 375 of file ald_usb.h.

◆ USB_DUAL_MODE_HOST

#define USB_DUAL_MODE_HOST 0x00000001U

Definition at line 374 of file ald_usb.h.

◆ USB_DUAL_MODE_NONE

#define USB_DUAL_MODE_NONE 0x00000080U

Definition at line 376 of file ald_usb.h.

◆ USB_EP_0

#define USB_EP_0 0U

Definition at line 347 of file ald_usb.h.

◆ USB_EP_1

#define USB_EP_1 1U

Definition at line 348 of file ald_usb.h.

◆ USB_EP_2

#define USB_EP_2 2U

Definition at line 349 of file ald_usb.h.

◆ USB_EP_3

#define USB_EP_3 3U

Definition at line 350 of file ald_usb.h.

◆ USB_EP_4

#define USB_EP_4 4U

Definition at line 351 of file ald_usb.h.

◆ USB_EP_5

#define USB_EP_5 5U

Definition at line 352 of file ald_usb.h.

◆ USB_EP_AUTO_CLEAR

#define USB_EP_AUTO_CLEAR 0x00000004U

Definition at line 297 of file ald_usb.h.

◆ USB_EP_AUTO_REQUEST

#define USB_EP_AUTO_REQUEST 0x00000002U

Definition at line 296 of file ald_usb.h.

◆ USB_EP_AUTO_SET

#define USB_EP_AUTO_SET 0x00000001U

Definition at line 295 of file ald_usb.h.

◆ USB_EP_DEV_IN

#define USB_EP_DEV_IN 0x00002000U

Definition at line 313 of file ald_usb.h.

◆ USB_EP_DEV_OUT

#define USB_EP_DEV_OUT 0x00000000U

Definition at line 314 of file ald_usb.h.

◆ USB_EP_DIS_NYET

#define USB_EP_DIS_NYET 0x00000020U

Definition at line 300 of file ald_usb.h.

◆ USB_EP_DMA_MODE_0

#define USB_EP_DMA_MODE_0 0x00000008U

Definition at line 298 of file ald_usb.h.

◆ USB_EP_DMA_MODE_1

#define USB_EP_DMA_MODE_1 0x00000010U

Definition at line 299 of file ald_usb.h.

◆ USB_EP_HOST_IN

#define USB_EP_HOST_IN 0x00000000U

Definition at line 311 of file ald_usb.h.

◆ USB_EP_HOST_OUT

#define USB_EP_HOST_OUT 0x00002000U

Definition at line 312 of file ald_usb.h.

◆ USB_EP_MODE_BULK

#define USB_EP_MODE_BULK 0x00000100U

Definition at line 304 of file ald_usb.h.

◆ USB_EP_MODE_CTRL

#define USB_EP_MODE_CTRL 0x00000300U

Definition at line 306 of file ald_usb.h.

◆ USB_EP_MODE_INT

#define USB_EP_MODE_INT 0x00000200U

Definition at line 305 of file ald_usb.h.

◆ USB_EP_MODE_ISOC

#define USB_EP_MODE_ISOC 0x00000000U

Definition at line 303 of file ald_usb.h.

◆ USB_EP_MODE_MASK

#define USB_EP_MODE_MASK 0x00000300U

Definition at line 307 of file ald_usb.h.

◆ USB_EP_SPEED_FULL

#define USB_EP_SPEED_FULL 0x00001000U

Definition at line 309 of file ald_usb.h.

◆ USB_EP_SPEED_HIGH

#define USB_EP_SPEED_HIGH 0x00004000U

Definition at line 310 of file ald_usb.h.

◆ USB_EP_SPEED_LOW

#define USB_EP_SPEED_LOW 0x00000000U

Definition at line 308 of file ald_usb.h.

◆ USB_FIFO_SZ_1024

#define USB_FIFO_SZ_1024 0x00000007U

Definition at line 364 of file ald_usb.h.

◆ USB_FIFO_SZ_128

#define USB_FIFO_SZ_128 0x00000004U

Definition at line 361 of file ald_usb.h.

◆ USB_FIFO_SZ_16

#define USB_FIFO_SZ_16 0x00000001U

Definition at line 358 of file ald_usb.h.

◆ USB_FIFO_SZ_2048

#define USB_FIFO_SZ_2048 0x00000008U

Definition at line 365 of file ald_usb.h.

◆ USB_FIFO_SZ_256

#define USB_FIFO_SZ_256 0x00000005U

Definition at line 362 of file ald_usb.h.

◆ USB_FIFO_SZ_32

#define USB_FIFO_SZ_32 0x00000002U

Definition at line 359 of file ald_usb.h.

◆ USB_FIFO_SZ_512

#define USB_FIFO_SZ_512 0x00000006U

Definition at line 363 of file ald_usb.h.

◆ USB_FIFO_SZ_64

#define USB_FIFO_SZ_64 0x00000003U

Definition at line 360 of file ald_usb.h.

◆ USB_FIFO_SZ_8

#define USB_FIFO_SZ_8 0x00000000U

Definition at line 357 of file ald_usb.h.

◆ USB_FULL_SPEED

#define USB_FULL_SPEED 0x00000001U

Definition at line 243 of file ald_usb.h.

◆ USB_HIGH_SPEED

#define USB_HIGH_SPEED 0x00000002U

Definition at line 242 of file ald_usb.h.

◆ USB_HOST_EP0_ERROR

#define USB_HOST_EP0_ERROR 0x00000010U

Definition at line 271 of file ald_usb.h.

◆ USB_HOST_EP0_NAK_TO

#define USB_HOST_EP0_NAK_TO 0x00000080U

Definition at line 268 of file ald_usb.h.

◆ USB_HOST_EP0_RX_STALL

#define USB_HOST_EP0_RX_STALL 0x00000004U

Definition at line 273 of file ald_usb.h.

◆ USB_HOST_EP0_RXPKTRDY

#define USB_HOST_EP0_RXPKTRDY 0x00000001U

Definition at line 274 of file ald_usb.h.

◆ USB_HOST_EP0_STATUS

#define USB_HOST_EP0_STATUS 0x00000040U

Definition at line 270 of file ald_usb.h.

◆ USB_HOST_IN_DATA_ERROR

#define USB_HOST_IN_DATA_ERROR 0x00080000U

Definition at line 250 of file ald_usb.h.

◆ USB_HOST_IN_ERROR

#define USB_HOST_IN_ERROR 0x00040000U

Definition at line 254 of file ald_usb.h.

◆ USB_HOST_IN_FIFO_FULL

#define USB_HOST_IN_FIFO_FULL 0x00020000U

Definition at line 256 of file ald_usb.h.

◆ USB_HOST_IN_NAK_TO

#define USB_HOST_IN_NAK_TO 0x00080000U

Definition at line 252 of file ald_usb.h.

◆ USB_HOST_IN_NOT_COMP

#define USB_HOST_IN_NOT_COMP 0x01000000U

Definition at line 248 of file ald_usb.h.

◆ USB_HOST_IN_PID_ERROR

#define USB_HOST_IN_PID_ERROR 0x10000000U

Definition at line 247 of file ald_usb.h.

◆ USB_HOST_IN_PKTRDY

#define USB_HOST_IN_PKTRDY 0x00010000U

Definition at line 257 of file ald_usb.h.

◆ USB_HOST_IN_STALL

#define USB_HOST_IN_STALL 0x00400000U

Definition at line 249 of file ald_usb.h.

◆ USB_HOST_IN_STATUS

#define USB_HOST_IN_STATUS 0x114F0000U

Definition at line 246 of file ald_usb.h.

◆ USB_HOST_LPM_L1

#define USB_HOST_LPM_L1 0x00000001U

Definition at line 329 of file ald_usb.h.

◆ USB_HOST_LPM_RMTWAKE

#define USB_HOST_LPM_RMTWAKE 0x00000100U

Definition at line 328 of file ald_usb.h.

◆ USB_HOST_OUT_ERROR

#define USB_HOST_OUT_ERROR 0x00000004U

Definition at line 264 of file ald_usb.h.

◆ USB_HOST_OUT_FIFO_NE

#define USB_HOST_OUT_FIFO_NE 0x00000002U

Definition at line 266 of file ald_usb.h.

◆ USB_HOST_OUT_NAK_TO

#define USB_HOST_OUT_NAK_TO 0x00000080U

Definition at line 259 of file ald_usb.h.

◆ USB_HOST_OUT_NOT_COMP

#define USB_HOST_OUT_NOT_COMP 0x00000080U

Definition at line 261 of file ald_usb.h.

◆ USB_HOST_OUT_PKTPEND

#define USB_HOST_OUT_PKTPEND 0x00000001U

Definition at line 267 of file ald_usb.h.

◆ USB_HOST_OUT_STALL

#define USB_HOST_OUT_STALL 0x00000020U

Definition at line 263 of file ald_usb.h.

◆ USB_HOST_OUT_STATUS

#define USB_HOST_OUT_STATUS 0x000000A7U

Definition at line 258 of file ald_usb.h.

◆ USB_HOST_PWREN_AUTOHIGH

#define USB_HOST_PWREN_AUTOHIGH 0x00000003U

Definition at line 325 of file ald_usb.h.

◆ USB_HOST_PWREN_AUTOLOW

#define USB_HOST_PWREN_AUTOLOW 0x00000002U

Definition at line 324 of file ald_usb.h.

◆ USB_HOST_PWREN_FILTER

#define USB_HOST_PWREN_FILTER 0x00010000U

Definition at line 326 of file ald_usb.h.

◆ USB_HOST_PWREN_MAN_HIGH

#define USB_HOST_PWREN_MAN_HIGH 0x00000001U

Definition at line 323 of file ald_usb.h.

◆ USB_HOST_PWREN_MAN_LOW

#define USB_HOST_PWREN_MAN_LOW 0x00000000U

Definition at line 322 of file ald_usb.h.

◆ USB_HOST_PWRFLT_EP_HIGH

#define USB_HOST_PWRFLT_EP_HIGH 0x00000340U

Definition at line 321 of file ald_usb.h.

◆ USB_HOST_PWRFLT_EP_LOW

#define USB_HOST_PWRFLT_EP_LOW 0x00000240U

Definition at line 320 of file ald_usb.h.

◆ USB_HOST_PWRFLT_EP_NONE

#define USB_HOST_PWRFLT_EP_NONE 0x00000000U

Definition at line 318 of file ald_usb.h.

◆ USB_HOST_PWRFLT_EP_TRI

#define USB_HOST_PWRFLT_EP_TRI 0x00000140U

Definition at line 319 of file ald_usb.h.

◆ USB_HOST_PWRFLT_HIGH

#define USB_HOST_PWRFLT_HIGH 0x00000030U

Definition at line 317 of file ald_usb.h.

◆ USB_HOST_PWRFLT_LOW

#define USB_HOST_PWRFLT_LOW 0x00000010U

Definition at line 316 of file ald_usb.h.

◆ USB_INTCTRL_ALL

#define USB_INTCTRL_ALL 0x000003FFU

Definition at line 155 of file ald_usb.h.

◆ USB_INTCTRL_BABBLE

#define USB_INTCTRL_BABBLE 0x00000004U

Definition at line 163 of file ald_usb.h.

◆ USB_INTCTRL_CONNECT

#define USB_INTCTRL_CONNECT 0x00000010U

Definition at line 161 of file ald_usb.h.

◆ USB_INTCTRL_DISCONNECT

#define USB_INTCTRL_DISCONNECT 0x00000020U

Definition at line 160 of file ald_usb.h.

◆ USB_INTCTRL_MODE_DETECT

#define USB_INTCTRL_MODE_DETECT 0x00000200U

Definition at line 167 of file ald_usb.h.

◆ USB_INTCTRL_POWER_FAULT

#define USB_INTCTRL_POWER_FAULT 0x00000100U

Definition at line 168 of file ald_usb.h.

◆ USB_INTCTRL_RESET

#define USB_INTCTRL_RESET 0x00000004U

Definition at line 164 of file ald_usb.h.

◆ USB_INTCTRL_RESUME

#define USB_INTCTRL_RESUME 0x00000002U

Definition at line 165 of file ald_usb.h.

◆ USB_INTCTRL_SESSION

#define USB_INTCTRL_SESSION 0x00000040U

Definition at line 158 of file ald_usb.h.

◆ USB_INTCTRL_SESSION_END

#define USB_INTCTRL_SESSION_END 0x00000040U

Definition at line 159 of file ald_usb.h.

◆ USB_INTCTRL_SOF

#define USB_INTCTRL_SOF 0x00000008U

Definition at line 162 of file ald_usb.h.

◆ USB_INTCTRL_STATUS

#define USB_INTCTRL_STATUS 0x000000FFU

Definition at line 156 of file ald_usb.h.

◆ USB_INTCTRL_SUSPEND

#define USB_INTCTRL_SUSPEND 0x00000001U

Definition at line 166 of file ald_usb.h.

◆ USB_INTCTRL_VBUS_ERR

#define USB_INTCTRL_VBUS_ERR 0x00000080U

Definition at line 157 of file ald_usb.h.

◆ USB_INTEP_0

#define USB_INTEP_0 0x00000001U

Definition at line 239 of file ald_usb.h.

◆ USB_INTEP_ALL

#define USB_INTEP_ALL 0xFFFFFFFFU

Definition at line 170 of file ald_usb.h.

◆ USB_INTEP_DEV_IN

#define USB_INTEP_DEV_IN 0x0000FFFEU

Definition at line 222 of file ald_usb.h.

◆ USB_INTEP_DEV_IN_1

#define USB_INTEP_DEV_IN_1 0x00000002U

Definition at line 237 of file ald_usb.h.

◆ USB_INTEP_DEV_IN_10

#define USB_INTEP_DEV_IN_10 0x00000400U

Definition at line 228 of file ald_usb.h.

◆ USB_INTEP_DEV_IN_11

#define USB_INTEP_DEV_IN_11 0x00000800U

Definition at line 227 of file ald_usb.h.

◆ USB_INTEP_DEV_IN_12

#define USB_INTEP_DEV_IN_12 0x00001000U

Definition at line 226 of file ald_usb.h.

◆ USB_INTEP_DEV_IN_13

#define USB_INTEP_DEV_IN_13 0x00002000U

Definition at line 225 of file ald_usb.h.

◆ USB_INTEP_DEV_IN_14

#define USB_INTEP_DEV_IN_14 0x00004000U

Definition at line 224 of file ald_usb.h.

◆ USB_INTEP_DEV_IN_15

#define USB_INTEP_DEV_IN_15 0x00008000U

Definition at line 223 of file ald_usb.h.

◆ USB_INTEP_DEV_IN_2

#define USB_INTEP_DEV_IN_2 0x00000004U

Definition at line 236 of file ald_usb.h.

◆ USB_INTEP_DEV_IN_3

#define USB_INTEP_DEV_IN_3 0x00000008U

Definition at line 235 of file ald_usb.h.

◆ USB_INTEP_DEV_IN_4

#define USB_INTEP_DEV_IN_4 0x00000010U

Definition at line 234 of file ald_usb.h.

◆ USB_INTEP_DEV_IN_5

#define USB_INTEP_DEV_IN_5 0x00000020U

Definition at line 233 of file ald_usb.h.

◆ USB_INTEP_DEV_IN_6

#define USB_INTEP_DEV_IN_6 0x00000040U

Definition at line 232 of file ald_usb.h.

◆ USB_INTEP_DEV_IN_7

#define USB_INTEP_DEV_IN_7 0x00000080U

Definition at line 231 of file ald_usb.h.

◆ USB_INTEP_DEV_IN_8

#define USB_INTEP_DEV_IN_8 0x00000100U

Definition at line 230 of file ald_usb.h.

◆ USB_INTEP_DEV_IN_9

#define USB_INTEP_DEV_IN_9 0x00000200U

Definition at line 229 of file ald_usb.h.

◆ USB_INTEP_DEV_OUT

#define USB_INTEP_DEV_OUT 0xFFFE0000U

Definition at line 188 of file ald_usb.h.

◆ USB_INTEP_DEV_OUT_1

#define USB_INTEP_DEV_OUT_1 0x00020000U

Definition at line 203 of file ald_usb.h.

◆ USB_INTEP_DEV_OUT_10

#define USB_INTEP_DEV_OUT_10 0x04000000U

Definition at line 194 of file ald_usb.h.

◆ USB_INTEP_DEV_OUT_11

#define USB_INTEP_DEV_OUT_11 0x08000000U

Definition at line 193 of file ald_usb.h.

◆ USB_INTEP_DEV_OUT_12

#define USB_INTEP_DEV_OUT_12 0x10000000U

Definition at line 192 of file ald_usb.h.

◆ USB_INTEP_DEV_OUT_13

#define USB_INTEP_DEV_OUT_13 0x20000000U

Definition at line 191 of file ald_usb.h.

◆ USB_INTEP_DEV_OUT_14

#define USB_INTEP_DEV_OUT_14 0x40000000U

Definition at line 190 of file ald_usb.h.

◆ USB_INTEP_DEV_OUT_15

#define USB_INTEP_DEV_OUT_15 0x80000000U

Definition at line 189 of file ald_usb.h.

◆ USB_INTEP_DEV_OUT_2

#define USB_INTEP_DEV_OUT_2 0x00040000U

Definition at line 202 of file ald_usb.h.

◆ USB_INTEP_DEV_OUT_3

#define USB_INTEP_DEV_OUT_3 0x00080000U

Definition at line 201 of file ald_usb.h.

◆ USB_INTEP_DEV_OUT_4

#define USB_INTEP_DEV_OUT_4 0x00100000U

Definition at line 200 of file ald_usb.h.

◆ USB_INTEP_DEV_OUT_5

#define USB_INTEP_DEV_OUT_5 0x00200000U

Definition at line 199 of file ald_usb.h.

◆ USB_INTEP_DEV_OUT_6

#define USB_INTEP_DEV_OUT_6 0x00400000U

Definition at line 198 of file ald_usb.h.

◆ USB_INTEP_DEV_OUT_7

#define USB_INTEP_DEV_OUT_7 0x00800000U

Definition at line 197 of file ald_usb.h.

◆ USB_INTEP_DEV_OUT_8

#define USB_INTEP_DEV_OUT_8 0x01000000U

Definition at line 196 of file ald_usb.h.

◆ USB_INTEP_DEV_OUT_9

#define USB_INTEP_DEV_OUT_9 0x02000000U

Definition at line 195 of file ald_usb.h.

◆ USB_INTEP_HOST_IN

#define USB_INTEP_HOST_IN 0xFFFE0000U

Definition at line 171 of file ald_usb.h.

◆ USB_INTEP_HOST_IN_1

#define USB_INTEP_HOST_IN_1 0x00020000U

Definition at line 186 of file ald_usb.h.

◆ USB_INTEP_HOST_IN_10

#define USB_INTEP_HOST_IN_10 0x04000000U

Definition at line 177 of file ald_usb.h.

◆ USB_INTEP_HOST_IN_11

#define USB_INTEP_HOST_IN_11 0x08000000U

Definition at line 176 of file ald_usb.h.

◆ USB_INTEP_HOST_IN_12

#define USB_INTEP_HOST_IN_12 0x10000000U

Definition at line 175 of file ald_usb.h.

◆ USB_INTEP_HOST_IN_13

#define USB_INTEP_HOST_IN_13 0x20000000U

Definition at line 174 of file ald_usb.h.

◆ USB_INTEP_HOST_IN_14

#define USB_INTEP_HOST_IN_14 0x40000000U

Definition at line 173 of file ald_usb.h.

◆ USB_INTEP_HOST_IN_15

#define USB_INTEP_HOST_IN_15 0x80000000U

Definition at line 172 of file ald_usb.h.

◆ USB_INTEP_HOST_IN_2

#define USB_INTEP_HOST_IN_2 0x00040000U

Definition at line 185 of file ald_usb.h.

◆ USB_INTEP_HOST_IN_3

#define USB_INTEP_HOST_IN_3 0x00080000U

Definition at line 184 of file ald_usb.h.

◆ USB_INTEP_HOST_IN_4

#define USB_INTEP_HOST_IN_4 0x00100000U

Definition at line 183 of file ald_usb.h.

◆ USB_INTEP_HOST_IN_5

#define USB_INTEP_HOST_IN_5 0x00200000U

Definition at line 182 of file ald_usb.h.

◆ USB_INTEP_HOST_IN_6

#define USB_INTEP_HOST_IN_6 0x00400000U

Definition at line 181 of file ald_usb.h.

◆ USB_INTEP_HOST_IN_7

#define USB_INTEP_HOST_IN_7 0x00800000U

Definition at line 180 of file ald_usb.h.

◆ USB_INTEP_HOST_IN_8

#define USB_INTEP_HOST_IN_8 0x01000000U

Definition at line 179 of file ald_usb.h.

◆ USB_INTEP_HOST_IN_9

#define USB_INTEP_HOST_IN_9 0x02000000U

Definition at line 178 of file ald_usb.h.

◆ USB_INTEP_HOST_OUT

#define USB_INTEP_HOST_OUT 0x0000FFFEU

Definition at line 205 of file ald_usb.h.

◆ USB_INTEP_HOST_OUT_1

#define USB_INTEP_HOST_OUT_1 0x00000002U

Definition at line 220 of file ald_usb.h.

◆ USB_INTEP_HOST_OUT_10

#define USB_INTEP_HOST_OUT_10 0x00000400U

Definition at line 211 of file ald_usb.h.

◆ USB_INTEP_HOST_OUT_11

#define USB_INTEP_HOST_OUT_11 0x00000800U

Definition at line 210 of file ald_usb.h.

◆ USB_INTEP_HOST_OUT_12

#define USB_INTEP_HOST_OUT_12 0x00001000U

Definition at line 209 of file ald_usb.h.

◆ USB_INTEP_HOST_OUT_13

#define USB_INTEP_HOST_OUT_13 0x00002000U

Definition at line 208 of file ald_usb.h.

◆ USB_INTEP_HOST_OUT_14

#define USB_INTEP_HOST_OUT_14 0x00004000U

Definition at line 207 of file ald_usb.h.

◆ USB_INTEP_HOST_OUT_15

#define USB_INTEP_HOST_OUT_15 0x00008000U

Definition at line 206 of file ald_usb.h.

◆ USB_INTEP_HOST_OUT_2

#define USB_INTEP_HOST_OUT_2 0x00000004U

Definition at line 219 of file ald_usb.h.

◆ USB_INTEP_HOST_OUT_3

#define USB_INTEP_HOST_OUT_3 0x00000008U

Definition at line 218 of file ald_usb.h.

◆ USB_INTEP_HOST_OUT_4

#define USB_INTEP_HOST_OUT_4 0x00000010U

Definition at line 217 of file ald_usb.h.

◆ USB_INTEP_HOST_OUT_5

#define USB_INTEP_HOST_OUT_5 0x00000020U

Definition at line 216 of file ald_usb.h.

◆ USB_INTEP_HOST_OUT_6

#define USB_INTEP_HOST_OUT_6 0x00000040U

Definition at line 215 of file ald_usb.h.

◆ USB_INTEP_HOST_OUT_7

#define USB_INTEP_HOST_OUT_7 0x00000080U

Definition at line 214 of file ald_usb.h.

◆ USB_INTEP_HOST_OUT_8

#define USB_INTEP_HOST_OUT_8 0x00000100U

Definition at line 213 of file ald_usb.h.

◆ USB_INTEP_HOST_OUT_9

#define USB_INTEP_HOST_OUT_9 0x00000200U

Definition at line 212 of file ald_usb.h.

◆ USB_INTEP_RX_SHIFT

#define USB_INTEP_RX_SHIFT 16U

Definition at line 410 of file ald_usb.h.

◆ USB_INTLPM_ACK

#define USB_INTLPM_ACK 0x00000004U

Definition at line 339 of file ald_usb.h.

◆ USB_INTLPM_ERROR

#define USB_INTLPM_ERROR 0x00000020U

Definition at line 336 of file ald_usb.h.

◆ USB_INTLPM_INCOMPLETE

#define USB_INTLPM_INCOMPLETE 0x00000008U

Definition at line 338 of file ald_usb.h.

◆ USB_INTLPM_NYET

#define USB_INTLPM_NYET 0x00000002U

Definition at line 340 of file ald_usb.h.

◆ USB_INTLPM_RESUME

#define USB_INTLPM_RESUME 0x00000010U

Definition at line 337 of file ald_usb.h.

◆ USB_INTLPM_STALL

#define USB_INTLPM_STALL 0x00000001U

Definition at line 341 of file ald_usb.h.

◆ USB_LOW_SPEED

#define USB_LOW_SPEED 0x00000000U

Definition at line 244 of file ald_usb.h.

◆ USB_LPMATTR_ENDPT_M

#define USB_LPMATTR_ENDPT_M 0x0000F000U

Definition at line 142 of file ald_usb.h.

◆ USB_LPMATTR_ENDPT_S

#define USB_LPMATTR_ENDPT_S 12U

Definition at line 147 of file ald_usb.h.

◆ USB_LPMATTR_HIRD_M

#define USB_LPMATTR_HIRD_M 0x000000F0U

Definition at line 144 of file ald_usb.h.

◆ USB_LPMATTR_HIRD_S

#define USB_LPMATTR_HIRD_S 4U

Definition at line 148 of file ald_usb.h.

◆ USB_LPMATTR_LS_L1

#define USB_LPMATTR_LS_L1 0x00000001U

Definition at line 146 of file ald_usb.h.

◆ USB_LPMATTR_LS_M

#define USB_LPMATTR_LS_M 0x0000000FU

Definition at line 145 of file ald_usb.h.

◆ USB_LPMATTR_RMTWAK

#define USB_LPMATTR_RMTWAK 0x00000100U

Definition at line 143 of file ald_usb.h.

◆ USB_LPMCNTRL_DISABLE

#define USB_LPMCNTRL_DISABLE 0x00000000U

Definition at line 153 of file ald_usb.h.

◆ USB_LPMCNTRL_ENABLE

#define USB_LPMCNTRL_ENABLE 0x00000006U

Definition at line 152 of file ald_usb.h.

◆ USB_LPMCNTRL_LPMRES

#define USB_LPMCNTRL_LPMRES 0x00000002U

Definition at line 150 of file ald_usb.h.

◆ USB_LPMCNTRL_LPMXMT

#define USB_LPMCNTRL_LPMXMT 0x00000001U

Definition at line 151 of file ald_usb.h.

◆ USB_MODE_DEV

#define USB_MODE_DEV 0x00000003U

Definition at line 406 of file ald_usb.h.

◆ USB_MODE_DEV_VBUS

#define USB_MODE_DEV_VBUS 0x00000005U

Definition at line 405 of file ald_usb.h.

◆ USB_MODE_HOST

#define USB_MODE_HOST 0x00000002U

Definition at line 404 of file ald_usb.h.

◆ USB_MODE_HOST_VBUS

#define USB_MODE_HOST_VBUS 0x00000004U

Definition at line 403 of file ald_usb.h.

◆ USB_MODE_OTG

#define USB_MODE_OTG 0x00000000U

Definition at line 407 of file ald_usb.h.

◆ USB_OTG_MODE_ASIDE_AVAL

#define USB_OTG_MODE_ASIDE_AVAL 0x00000011U

Definition at line 380 of file ald_usb.h.

◆ USB_OTG_MODE_ASIDE_DEV

#define USB_OTG_MODE_ASIDE_DEV 0x00000019U

Definition at line 381 of file ald_usb.h.

◆ USB_OTG_MODE_ASIDE_HOST

#define USB_OTG_MODE_ASIDE_HOST 0x0000001dU

Definition at line 377 of file ald_usb.h.

◆ USB_OTG_MODE_ASIDE_NPWR

#define USB_OTG_MODE_ASIDE_NPWR 0x00000001U

Definition at line 378 of file ald_usb.h.

◆ USB_OTG_MODE_ASIDE_SESS

#define USB_OTG_MODE_ASIDE_SESS 0x00000009U

Definition at line 379 of file ald_usb.h.

◆ USB_OTG_MODE_BSIDE_DEV

#define USB_OTG_MODE_BSIDE_DEV 0x00000099U

Definition at line 383 of file ald_usb.h.

◆ USB_OTG_MODE_BSIDE_HOST

#define USB_OTG_MODE_BSIDE_HOST 0x0000009dU

Definition at line 382 of file ald_usb.h.

◆ USB_OTG_MODE_BSIDE_NPWR

#define USB_OTG_MODE_BSIDE_NPWR 0x00000081U

Definition at line 384 of file ald_usb.h.

◆ USB_OTG_MODE_NONE

#define USB_OTG_MODE_NONE 0x00000080U

Definition at line 385 of file ald_usb.h.

◆ USB_POWER_HS_EN

#define USB_POWER_HS_EN 0x00000020U

Definition at line 43 of file ald_usb.h.

◆ USB_POWER_HS_M

#define USB_POWER_HS_M 0x00000010U

Definition at line 44 of file ald_usb.h.

◆ USB_POWER_ISOUP

#define USB_POWER_ISOUP 0x00000080U

Definition at line 41 of file ald_usb.h.

◆ USB_POWER_PWRDNPHY

#define USB_POWER_PWRDNPHY 0x00000001U

Definition at line 48 of file ald_usb.h.

◆ USB_POWER_RESET

#define USB_POWER_RESET 0x00000008U

Definition at line 45 of file ald_usb.h.

◆ USB_POWER_RESUME

#define USB_POWER_RESUME 0x00000004U

Definition at line 46 of file ald_usb.h.

◆ USB_POWER_SOFTCONN

#define USB_POWER_SOFTCONN 0x00000040U

Definition at line 42 of file ald_usb.h.

◆ USB_POWER_SUSPEND

#define USB_POWER_SUSPEND 0x00000002U

Definition at line 47 of file ald_usb.h.

◆ USB_RX_EPSTATUS_SHIFT

#define USB_RX_EPSTATUS_SHIFT 16U

Definition at line 409 of file ald_usb.h.

◆ USB_RXCSRH1_AUTOCL

#define USB_RXCSRH1_AUTOCL 0x00000080U

Definition at line 62 of file ald_usb.h.

◆ USB_RXCSRH1_AUTORQ

#define USB_RXCSRH1_AUTORQ 0x00000040U

Definition at line 63 of file ald_usb.h.

◆ USB_RXCSRH1_DISNYET

#define USB_RXCSRH1_DISNYET 0x00000010U

Definition at line 66 of file ald_usb.h.

◆ USB_RXCSRH1_DMAEN

#define USB_RXCSRH1_DMAEN 0x00000020U

Definition at line 65 of file ald_usb.h.

◆ USB_RXCSRH1_DMAMOD

#define USB_RXCSRH1_DMAMOD 0x00000008U

Definition at line 68 of file ald_usb.h.

◆ USB_RXCSRH1_DT

#define USB_RXCSRH1_DT 0x00000002U

Definition at line 70 of file ald_usb.h.

◆ USB_RXCSRH1_DTWE

#define USB_RXCSRH1_DTWE 0x00000004U

Definition at line 69 of file ald_usb.h.

◆ USB_RXCSRH1_INCOMPRX

#define USB_RXCSRH1_INCOMPRX 0x00000001U

Definition at line 71 of file ald_usb.h.

◆ USB_RXCSRH1_ISO

#define USB_RXCSRH1_ISO 0x00000040U

Definition at line 64 of file ald_usb.h.

◆ USB_RXCSRH1_PIDERR

#define USB_RXCSRH1_PIDERR 0x00000010U

Definition at line 67 of file ald_usb.h.

◆ USB_RXCSRL1_CLRDT

#define USB_RXCSRL1_CLRDT 0x00000080U

Definition at line 98 of file ald_usb.h.

◆ USB_RXCSRL1_DATAERR

#define USB_RXCSRL1_DATAERR 0x00000008U

Definition at line 103 of file ald_usb.h.

◆ USB_RXCSRL1_ERROR

#define USB_RXCSRL1_ERROR 0x00000004U

Definition at line 106 of file ald_usb.h.

◆ USB_RXCSRL1_FLUSH

#define USB_RXCSRL1_FLUSH 0x00000010U

Definition at line 102 of file ald_usb.h.

◆ USB_RXCSRL1_FULL

#define USB_RXCSRL1_FULL 0x00000002U

Definition at line 107 of file ald_usb.h.

◆ USB_RXCSRL1_NAKTO

#define USB_RXCSRL1_NAKTO 0x00000008U

Definition at line 104 of file ald_usb.h.

◆ USB_RXCSRL1_OVER

#define USB_RXCSRL1_OVER 0x00000004U

Definition at line 105 of file ald_usb.h.

◆ USB_RXCSRL1_REQPKT

#define USB_RXCSRL1_REQPKT 0x00000020U

Definition at line 101 of file ald_usb.h.

◆ USB_RXCSRL1_RXRDY

#define USB_RXCSRL1_RXRDY 0x00000001U

Definition at line 108 of file ald_usb.h.

◆ USB_RXCSRL1_STALL

#define USB_RXCSRL1_STALL 0x00000020U

Definition at line 100 of file ald_usb.h.

◆ USB_RXCSRL1_STALLED

#define USB_RXCSRL1_STALLED 0x00000040U

Definition at line 99 of file ald_usb.h.

◆ USB_TRANS_IN

#define USB_TRANS_IN 0x00000102U

Definition at line 369 of file ald_usb.h.

◆ USB_TRANS_IN_LAST

#define USB_TRANS_IN_LAST 0x0000010aU

Definition at line 370 of file ald_usb.h.

◆ USB_TRANS_OUT

#define USB_TRANS_OUT 0x00000102U

Definition at line 368 of file ald_usb.h.

◆ USB_TRANS_SETUP

#define USB_TRANS_SETUP 0x0000110aU

Definition at line 371 of file ald_usb.h.

◆ USB_TRANS_STATUS

#define USB_TRANS_STATUS 0x00000142U

Definition at line 372 of file ald_usb.h.

◆ USB_TXCSRH1_AUTOSET

#define USB_TXCSRH1_AUTOSET 0x00000080U

Definition at line 78 of file ald_usb.h.

◆ USB_TXCSRH1_DMAEN

#define USB_TXCSRH1_DMAEN 0x00000010U

Definition at line 81 of file ald_usb.h.

◆ USB_TXCSRH1_DMAMOD

#define USB_TXCSRH1_DMAMOD 0x00000004U

Definition at line 83 of file ald_usb.h.

◆ USB_TXCSRH1_DT

#define USB_TXCSRH1_DT 0x00000001U

Definition at line 85 of file ald_usb.h.

◆ USB_TXCSRH1_DTWE

#define USB_TXCSRH1_DTWE 0x00000002U

Definition at line 84 of file ald_usb.h.

◆ USB_TXCSRH1_FDT

#define USB_TXCSRH1_FDT 0x00000008U

Definition at line 82 of file ald_usb.h.

◆ USB_TXCSRH1_ISO

#define USB_TXCSRH1_ISO 0x00000040U

Definition at line 79 of file ald_usb.h.

◆ USB_TXCSRH1_MODE

#define USB_TXCSRH1_MODE 0x00000020U

Definition at line 80 of file ald_usb.h.

◆ USB_TXCSRL1_CLRDT

#define USB_TXCSRL1_CLRDT 0x00000040U

Definition at line 88 of file ald_usb.h.

◆ USB_TXCSRL1_ERROR

#define USB_TXCSRL1_ERROR 0x00000004U

Definition at line 93 of file ald_usb.h.

◆ USB_TXCSRL1_FIFONE

#define USB_TXCSRL1_FIFONE 0x00000002U

Definition at line 95 of file ald_usb.h.

◆ USB_TXCSRL1_FLUSH

#define USB_TXCSRL1_FLUSH 0x00000008U

Definition at line 92 of file ald_usb.h.

◆ USB_TXCSRL1_NAKTO

#define USB_TXCSRL1_NAKTO 0x00000080U

Definition at line 87 of file ald_usb.h.

◆ USB_TXCSRL1_SETUP

#define USB_TXCSRL1_SETUP 0x00000010U

Definition at line 91 of file ald_usb.h.

◆ USB_TXCSRL1_STALL

#define USB_TXCSRL1_STALL 0x00000010U

Definition at line 90 of file ald_usb.h.

◆ USB_TXCSRL1_STALLED

#define USB_TXCSRL1_STALLED 0x00000020U

Definition at line 89 of file ald_usb.h.

◆ USB_TXCSRL1_TXRDY

#define USB_TXCSRL1_TXRDY 0x00000001U

Definition at line 96 of file ald_usb.h.

◆ USB_TXCSRL1_UNDRN

#define USB_TXCSRL1_UNDRN 0x00000004U

Definition at line 94 of file ald_usb.h.

◆ USB_TXTYPE1_PROTO_BULK

#define USB_TXTYPE1_PROTO_BULK 0x00000020U

Definition at line 137 of file ald_usb.h.

◆ USB_TXTYPE1_PROTO_CTRL

#define USB_TXTYPE1_PROTO_CTRL 0x00000000U

Definition at line 135 of file ald_usb.h.

◆ USB_TXTYPE1_PROTO_INT

#define USB_TXTYPE1_PROTO_INT 0x00000030U

Definition at line 138 of file ald_usb.h.

◆ USB_TXTYPE1_PROTO_ISOC

#define USB_TXTYPE1_PROTO_ISOC 0x00000010U

Definition at line 136 of file ald_usb.h.

◆ USB_TXTYPE1_PROTO_M

#define USB_TXTYPE1_PROTO_M 0x00000030U

Definition at line 134 of file ald_usb.h.

◆ USB_TXTYPE1_SPEED_DFLT

#define USB_TXTYPE1_SPEED_DFLT 0x00000000U

Definition at line 130 of file ald_usb.h.

◆ USB_TXTYPE1_SPEED_FULL

#define USB_TXTYPE1_SPEED_FULL 0x00000080U

Definition at line 132 of file ald_usb.h.

◆ USB_TXTYPE1_SPEED_HIGH

#define USB_TXTYPE1_SPEED_HIGH 0x00000040U

Definition at line 131 of file ald_usb.h.

◆ USB_TXTYPE1_SPEED_LOW

#define USB_TXTYPE1_SPEED_LOW 0x000000C0U

Definition at line 133 of file ald_usb.h.

◆ USB_TXTYPE1_SPEED_M

#define USB_TXTYPE1_SPEED_M 0x000000C0U

Definition at line 129 of file ald_usb.h.

◆ USB_TXTYPE1_TEP_M

#define USB_TXTYPE1_TEP_M 0x0000000FU

Definition at line 139 of file ald_usb.h.

◆ USB_TXTYPE1_TEP_S

#define USB_TXTYPE1_TEP_S 0U

Definition at line 140 of file ald_usb.h.

◆ USB_TYPE0_SPEED_FULL

#define USB_TYPE0_SPEED_FULL 0x00000080U

Definition at line 126 of file ald_usb.h.

◆ USB_TYPE0_SPEED_HIGH

#define USB_TYPE0_SPEED_HIGH 0x00000040U

Definition at line 125 of file ald_usb.h.

◆ USB_TYPE0_SPEED_LOW

#define USB_TYPE0_SPEED_LOW 0x000000C0U

Definition at line 127 of file ald_usb.h.

◆ USB_TYPE0_SPEED_M

#define USB_TYPE0_SPEED_M 0x000000C0U

Definition at line 124 of file ald_usb.h.

◆ USB_UNDEF_SPEED

#define USB_UNDEF_SPEED 0x80000000U

Definition at line 241 of file ald_usb.h.

◆ USBEPToIndex

#define USBEPToIndex ( x ) ((x))

Definition at line 355 of file ald_usb.h.

◆ USBFIFOSizeToBytes

#define USBFIFOSizeToBytes ( x ) (8 << (x))

Definition at line 366 of file ald_usb.h.


ALD User Manual: WDT

Modules
WDT
EASTSOFT ES32F3xx ALD

WDT module driver. More...

Collaboration diagram for WDT:

Modules

WWDT Public Functions
Init and configure WWDT function.
IWDT Public Functions
Init and configure IWDT function.
WDT Public Types
WDT Private Macros

Detailed Description

WDT module driver.


ALD User Manual: WWDT Public Functions

Functions
WWDT Public Functions
EASTSOFT ES32F3xx ALD » WDT

Init and configure WWDT function. More...

Collaboration diagram for WWDT Public Functions:

Functions

void | ald_wwdt_init (uint32_t load, wwdt_win_t win, type_func_t interrupt)
Initializes the WWDT according to the specified parameters. More...
void | ald_wwdt_start (void)
Start the WWDT. More...
uint32_t | ald_wwdt_get_value (void)
Get the free-running downcounter value. More...
it_status_t | ald_wwdt_get_flag_status (void)
Get interrupt state. More...
void | ald_wwdt_clear_flag_status (void)
Clear interrupt state. More...
void | ald_wwdt_feed_dog (void)
Refreshes the WWDT. More...

Detailed Description

Init and configure WWDT function.

Function Documentation

◆ ald_wwdt_clear_flag_status()

void ald_wwdt_clear_flag_status ( void )

Clear interrupt state.

Return values
None

Definition at line 101 of file ald_wdt.c.

102 {
103 WRITE_REG(WWDT->INTCLR, 1);
104 return;
105 }
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72

◆ ald_wwdt_feed_dog()

void ald_wwdt_feed_dog ( void )

Refreshes the WWDT.

Return values
None

Definition at line 111 of file ald_wdt.c.

112 {
113 WWDT_UNLOCK();
114 WRITE_REG(WWDT->INTCLR, 0x1);
115 WWDT_LOCK();
116
117 return;
118 }
WWDT_LOCK
#define WWDT_LOCK()
Definition: ald_wdt.h:57
WWDT_UNLOCK
#define WWDT_UNLOCK()
Definition: ald_wdt.h:56
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72

◆ ald_wwdt_get_flag_status()

it_status_t ald_wwdt_get_flag_status ( void )

Get interrupt state.

Return values
Value

Definition at line 89 of file ald_wdt.c.

90 {
91 if (READ_BIT(WWDT->RIS, WWDT_RIS_WWDTIF_MSK))
92 return SET;
93
94 return RESET;
95 }
SET
Definition: type.h:39
RESET
Definition: type.h:38
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69

◆ ald_wwdt_get_value()

uint32_t ald_wwdt_get_value ( void )

Get the free-running downcounter value.

Return values
Value

Definition at line 80 of file ald_wdt.c.

81 {
82 return WWDT->VALUE;
83 }

◆ ald_wwdt_init()

void ald_wwdt_init | ( | uint32_t | load,
 |  | wwdt_win_t | win,
 |  | type_func_t | interrupt
 | ) |  |

Initializes the WWDT according to the specified parameters.

Parameters
load | Specifies the free-running downcounter value.
win specifics the no dog windows, the parameter can be one of the following values:
  • WWDT_WIN_25 No dog window size: 25%
  • WWDT_WIN_50 No dog window size: 50%
  • WWDT_WIN_75 No dog window size: 75%
  • WWDT_WIN_00 No dog window size: 0%
interrupt | Enable or disable interrupt.
Return values
None

Definition at line 47 of file ald_wdt.c.

48 {
49 assert_param(IS_WWDT_WIN_TYPE(win));
50 assert_param(IS_FUNC_STATE(interrupt));
51
52 WWDT_UNLOCK();
53 WRITE_REG(WWDT->LOAD, load);
54 MODIFY_REG(WWDT->CON, WWDT_CON_WWDTWIN_MSK, win << WWDT_CON_WWDTWIN_POSS);
55 SET_BIT(WWDT->CON, WWDT_CON_CLKS_MSK);
56 SET_BIT(WWDT->CON, WWDT_CON_RSTEN_MSK);
57 MODIFY_REG(WWDT->CON, WWDT_CON_IE_MSK, interrupt << WWDT_CON_IE_POS);
58 WWDT_LOCK();
59
60 return;
61 }
WWDT_LOCK
#define WWDT_LOCK()
Definition: ald_wdt.h:57
assert_param
#define assert_param(x)
Definition: type.h:88
IS_WWDT_WIN_TYPE
#define IS_WWDT_WIN_TYPE(x)
Definition: ald_wdt.h:69
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
WWDT_UNLOCK
#define WWDT_UNLOCK()
Definition: ald_wdt.h:56
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_wwdt_start()

void ald_wwdt_start ( void )

Start the WWDT.

Return values
None

Definition at line 67 of file ald_wdt.c.

68 {
69 WWDT_UNLOCK();
70 SET_BIT(WWDT->CON, WWDT_CON_EN_MSK);
71 WWDT_LOCK();
72
73 return;
74 }
WWDT_LOCK
#define WWDT_LOCK()
Definition: ald_wdt.h:57
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
WWDT_UNLOCK
#define WWDT_UNLOCK()
Definition: ald_wdt.h:56


ALD User Manual: IWDT Public Functions

Functions
IWDT Public Functions
EASTSOFT ES32F3xx ALD » WDT

Init and configure IWDT function. More...

Collaboration diagram for IWDT Public Functions:

Functions

void | ald_iwdt_init (uint32_t load, type_func_t interrupt)
Initializes the IWDG according to the specified parameters. More...
void | ald_iwdt_start (void)
Start the IWDT. More...
uint32_t | ald_iwdt_get_value (void)
Get the free-running downcounter value. More...
it_status_t | ald_iwdt_get_flag_status (void)
Get interrupt state. More...
void | ald_iwdt_clear_flag_status (void)
Clear interrupt state. More...
void | ald_iwdt_feed_dog (void)
Refreshes the WWDT. More...

Detailed Description

Init and configure IWDT function.

Function Documentation

◆ ald_iwdt_clear_flag_status()

void ald_iwdt_clear_flag_status ( void )

Clear interrupt state.

Return values
None

Definition at line 185 of file ald_wdt.c.

186 {
187 WRITE_REG(IWDT->INTCLR, 1);
188 return;
189 }
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72

◆ ald_iwdt_feed_dog()

void ald_iwdt_feed_dog ( void )

Refreshes the WWDT.

Return values
None

Definition at line 195 of file ald_wdt.c.

196 {
197 IWDT_UNLOCK();
198 WRITE_REG(IWDT->INTCLR, 1);
199 IWDT_LOCK();
200
201 return;
202 }
IWDT_UNLOCK
#define IWDT_UNLOCK()
Definition: ald_wdt.h:58
IWDT_LOCK
#define IWDT_LOCK()
Definition: ald_wdt.h:59
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72

◆ ald_iwdt_get_flag_status()

it_status_t ald_iwdt_get_flag_status ( void )

Get interrupt state.

Return values
Value

Definition at line 173 of file ald_wdt.c.

174 {
175 if (READ_BIT(IWDT->RIS, IWDT_RIS_WDTIF_MSK))
176 return SET;
177
178 return RESET;
179 }
SET
Definition: type.h:39
RESET
Definition: type.h:38
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69

◆ ald_iwdt_get_value()

uint32_t ald_iwdt_get_value ( void )

Get the free-running downcounter value.

Return values
Value

Definition at line 164 of file ald_wdt.c.

165 {
166 return IWDT->VALUE;
167 }

◆ ald_iwdt_init()

void ald_iwdt_init | ( | uint32_t | load,
 |  | type_func_t | interrupt
 | ) |  |

Initializes the IWDG according to the specified parameters.

Parameters
load | Specifies the free-running downcounter value.
interrupt | Enable or disable interrupt.
Return values
None

Definition at line 133 of file ald_wdt.c.

134 {
135 assert_param(IS_FUNC_STATE(interrupt));
136
137 IWDT_UNLOCK();
138 WRITE_REG(IWDT->LOAD, load);
139 SET_BIT(IWDT->CON, IWDT_CON_CLKS_MSK);
140 SET_BIT(IWDT->CON, IWDT_CON_RSTEN_MSK);
141 MODIFY_REG(IWDT->CON, IWDT_CON_IE_MSK, interrupt << IWDT_CON_IE_POS);
142 IWDT_LOCK();
143
144 return;
145 }
assert_param
#define assert_param(x)
Definition: type.h:88
IWDT_UNLOCK
#define IWDT_UNLOCK()
Definition: ald_wdt.h:58
IWDT_LOCK
#define IWDT_LOCK()
Definition: ald_wdt.h:59
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_iwdt_start()

void ald_iwdt_start ( void )

Start the IWDT.

Return values
None

Definition at line 151 of file ald_wdt.c.

152 {
153 IWDT_UNLOCK();
154 SET_BIT(IWDT->CON, IWDT_CON_EN_MSK);
155 IWDT_LOCK();
156
157 return;
158 }
IWDT_UNLOCK
#define IWDT_UNLOCK()
Definition: ald_wdt.h:58
IWDT_LOCK
#define IWDT_LOCK()
Definition: ald_wdt.h:59
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67


ALD User Manual: WDT Public Types

Enumerations
WDT Public Types
EASTSOFT ES32F3xx ALD » WDT
Collaboration diagram for WDT Public Types:

Enumerations

enum wwdt_win_t { WWDT_WIN_25 = 0x0U, WWDT_WIN_50 = 0x1U, WWDT_WIN_75 = 0x2U, WWDT_WIN_00 = 0x3U }
Wwdt no dog window. More...

Detailed Description

Enumeration Type Documentation

◆ wwdt_win_t

enum wwdt_win_t

Wwdt no dog window.

Enumerator
WWDT_WIN_25 | No dog window size: 25%
WWDT_WIN_50 | No dog window size: 50%
WWDT_WIN_75 | No dog window size: 75%
WWDT_WIN_00 | No dog window size: 0%

Definition at line 41 of file ald_wdt.h.

41 {
42 WWDT_WIN_25 = 0x0U,
43 WWDT_WIN_50 = 0x1U,
44 WWDT_WIN_75 = 0x2U,
45 WWDT_WIN_00 = 0x3U,
46 } wwdt_win_t;
wwdt_win_t
wwdt_win_t
Wwdt no dog window.
Definition: ald_wdt.h:41
WWDT_WIN_00
Definition: ald_wdt.h:45
WWDT_WIN_50
Definition: ald_wdt.h:43
WWDT_WIN_75
Definition: ald_wdt.h:44
WWDT_WIN_25
Definition: ald_wdt.h:42


ALD User Manual: WDT Private Macros

Macros
WDT Private Macros
EASTSOFT ES32F3xx ALD » WDT
Collaboration diagram for WDT Private Macros:

Macros

#define | WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551U);}
#define | WWDT_LOCK() {WRITE_REG(WWDT->LOCK, 0xFFFFFFFFU);}
#define | IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551U);}
#define | IWDT_LOCK() {WRITE_REG(IWDT->LOCK, 0xFFFFFFFFU);}
#define | IS_WWDT_WIN_TYPE(x)
#define | IS_FUNC_STATE(x)

Detailed Description

Macro Definition Documentation

◆ IS_FUNC_STATE

#define IS_FUNC_STATE ( x )
Value:
(((x) == DISABLE) || \
((x) == ENABLE))
ENABLE
Definition: type.h:49
DISABLE
Definition: type.h:48

Definition at line 73 of file ald_wdt.h.

◆ IS_WWDT_WIN_TYPE

#define IS_WWDT_WIN_TYPE ( x )
Value:
((x == WWDT_WIN_25) || \
(x == WWDT_WIN_50) || \
(x == WWDT_WIN_75) || \
(x == WWDT_WIN_00))
WWDT_WIN_00
Definition: ald_wdt.h:45
WWDT_WIN_50
Definition: ald_wdt.h:43
WWDT_WIN_75
Definition: ald_wdt.h:44
WWDT_WIN_25
Definition: ald_wdt.h:42

Definition at line 69 of file ald_wdt.h.

◆ IWDT_LOCK

#define IWDT_LOCK ( ) {WRITE_REG(IWDT->LOCK, 0xFFFFFFFFU);}

Definition at line 59 of file ald_wdt.h.

◆ IWDT_UNLOCK

#define IWDT_UNLOCK ( ) {WRITE_REG(IWDT->LOCK, 0x1ACCE551U);}

Definition at line 58 of file ald_wdt.h.

◆ WWDT_LOCK

#define WWDT_LOCK ( ) {WRITE_REG(WWDT->LOCK, 0xFFFFFFFFU);}

Definition at line 57 of file ald_wdt.h.

◆ WWDT_UNLOCK

#define WWDT_UNLOCK ( ) {WRITE_REG(WWDT->LOCK, 0x1ACCE551U);}

Definition at line 56 of file ald_wdt.h.


ALD User Manual: Utils

Modules
Utils
EASTSOFT ES32F3xx ALD

Utils module driver. More...

Collaboration diagram for Utils:

Modules

Private Constants
ALD Private Constants.
Private Variables
Public Functions
Public Types
Public Macros
Private Macros

Detailed Description

Utils module driver.


ALD User Manual: Private Constants

Macros
Private Constants
EASTSOFT ES32F3xx ALD » Utils

ALD Private Constants. More...

Collaboration diagram for Private Constants:

Macros

#define | __ALD_VERSION_MAIN (0x01)
ALD version number. More...
#define | __ALD_VERSION_SUB1 (0x00)
#define | __ALD_VERSION_SUB2 (0x00)
#define | __ALD_VERSION_RC (0x00)
#define | __ALD_VERSION

Detailed Description

ALD Private Constants.

Macro Definition Documentation

◆ __ALD_VERSION

#define __ALD_VERSION
Value:
((__ALD_VERSION_MAIN << 24) | \
(__ALD_VERSION_SUB1 << 16) | \
(__ALD_VERSION_SUB2 << 8 ) | \
(__ALD_VERSION_RC))
__ALD_VERSION_SUB1
#define __ALD_VERSION_SUB1
Definition: utils.c:42
__ALD_VERSION_SUB2
#define __ALD_VERSION_SUB2
Definition: utils.c:43
__ALD_VERSION_RC
#define __ALD_VERSION_RC
Definition: utils.c:44
__ALD_VERSION_MAIN
#define __ALD_VERSION_MAIN
ALD version number.
Definition: utils.c:41

Definition at line 45 of file utils.c.

◆ __ALD_VERSION_MAIN

#define __ALD_VERSION_MAIN (0x01)

ALD version number.

[31:24] main version

Definition at line 41 of file utils.c.

◆ __ALD_VERSION_RC

#define __ALD_VERSION_RC (0x00)

[7:0] release candidate

Definition at line 44 of file utils.c.

◆ __ALD_VERSION_SUB1

#define __ALD_VERSION_SUB1 (0x00)

[23:16] sub1 version

Definition at line 42 of file utils.c.

◆ __ALD_VERSION_SUB2

#define __ALD_VERSION_SUB2 (0x00)

[15:8] sub2 version

Definition at line 43 of file utils.c.


ALD User Manual: Private Variables

Variables
Private Variables
EASTSOFT ES32F3xx ALD » Utils
Collaboration diagram for Private Variables:

Variables

static __IO uint32_t | lib_tick
lib_tick: Increase by one millisecond More...
uint32_t | __systick_interval = SYSTICK_INTERVAL_1MS
SysTick interval. More...

Detailed Description

Variable Documentation

◆ __systick_interval

uint32_t __systick_interval = SYSTICK_INTERVAL_1MS

SysTick interval.

Definition at line 59 of file utils.c.

◆ lib_tick

__IO uint32_t lib_tick
static

lib_tick: Increase by one millisecond

Definition at line 58 of file utils.c.


ALD User Manual: Public Functions

Modules
Public Functions
EASTSOFT ES32F3xx ALD » Utils
Collaboration diagram for Public Functions:

Modules

Initialization Function
Initialization functions.
Control functions
Control functions.

Detailed Description


ALD User Manual: Initialization Function

Functions
Initialization Function
EASTSOFT ES32F3xx ALD » Utils » Public Functions

Initialization functions. More...

Collaboration diagram for Initialization Function:

Functions

void | ald_cmu_init (void)
This function Configures time base source, NVIC and DMA. More...
__weak void | ald_tick_init (uint32_t prio)
This function configures the source of the time base. The time source is configured to have 1ms time base with a dedicated Tick interrupt priority. More...
void | ald_systick_interval_select (systick_interval_t value)
Selects the interval of systick interrupt. More...

Detailed Description

Initialization functions.

===============================================================================
             ##### Initialization functions #####
===============================================================================
  [..]  This section provides functions allowing to:
     (+) Initializes interface, the NVIC allocation and initial clock
         configuration. It initializes the source of time base also when timeout
         is needed and the backup domain when enabled.
     (+) Configure The time base source to have 1ms time base with a dedicated
         Tick interrupt priority.
       (++) Systick timer is used by default as source of time base, but user
            can eventually implement his proper time base source (a general purpose
            timer for example or other time source), keeping in mind that Time base
            duration should be kept 1ms.
       (++) Time base configuration function (ald_tick_init()) is called automatically
            at the beginning of the program after reset by ald_cmu_init() or at
            any time when clock is configured.
       (++) Source of time base is configured  to generate interrupts at regular
            time intervals. Care must be taken if ald_delay_ms() is called from a
            peripheral ISR process, the Tick interrupt line must have higher priority
           (numerically lower) than the peripheral interrupt. Otherwise the caller
           ISR process will be blocked.
      (++) functions affecting time base configurations are declared as __weak
            to make  override possible  in case of other implementations in user file.
     (+) Configure the interval of Systick interrupt.

Function Documentation

◆ ald_cmu_init()

void ald_cmu_init ( void )

This function Configures time base source, NVIC and DMA.

Note
This function is called at the beginning of program after reset and before the clock configuration.
The time base configuration is based on MSI clock when exiting from Reset. Once done, time base tick start incrementing. In the default implementation, Systick is used as source of time base. The tick variable is incremented each 1ms in its ISR.
Return values
None

Definition at line 112 of file utils.c.

113 {
114 NVIC_SetPriorityGrouping(NVIC_PRIORITY_GROUP_2);
115 ald_cmu_clock_config_default();
116 ald_tick_init(TICK_INT_PRIORITY);
117 #ifdef ALD_DMA
118 ald_cmu_perh_clock_config(CMU_PERH_DMA, ENABLE);
119 ald_dma_init(DMA0);
120 #endif
121 return;
122 }
ENABLE
Definition: type.h:49
ald_dma_init
void ald_dma_init(DMA_TypeDef *DMAx)
DMA module initialization, this function is invoked by ald_cmu_init().
Definition: ald_dma.c:270
ald_cmu_clock_config_default
ald_status_t ald_cmu_clock_config_default(void)
Configure system clock using default. Select CMU_CLOCK_HRC(24MHz) as system clock and enable CMU_CLOC...
Definition: ald_cmu.c:263
ald_tick_init
__weak void ald_tick_init(uint32_t prio)
This function configures the source of the time base. The time source is configured to have 1ms time ...
Definition: utils.c:138
NVIC_PRIORITY_GROUP_2
Definition: utils.h:67
CMU_PERH_DMA
Definition: ald_cmu.h:417
TICK_INT_PRIORITY
#define TICK_INT_PRIORITY
Definition: ald_conf.h:62
ald_cmu_perh_clock_config
void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status)
Enable/Disable peripheral clock.
Definition: ald_cmu.c:1071

◆ ald_systick_interval_select()

void ald_systick_interval_select ( systick_interval_t value )

Selects the interval of systick interrupt.

Parameters
value The value of interval:
  • SYSTICK_INTERVAL_1MS 1 millisecond
  • SYSTICK_INTERVAL_10MS 10 milliseconds
  • SYSTICK_INTERVAL_100MS 100 milliseconds
  • SYSTICK_INTERVAL_1000MS 1 second
Return values
None

Definition at line 156 of file utils.c.

157 {
158 assert_param(IS_SYSTICK_INTERVAL(value));
159
160 SysTick_Config(ald_cmu_get_sys_clock() / value);
161 __systick_interval = value;
162
163 if (TICK_INT_PRIORITY != 15)
164 NVIC_SetPriority(SysTick_IRQn, TICK_INT_PRIORITY);
165
166 return;
167 }
assert_param
#define assert_param(x)
Definition: type.h:88
ald_cmu_get_sys_clock
uint32_t ald_cmu_get_sys_clock(void)
Get SYS clock.
Definition: ald_cmu.c:616
__systick_interval
uint32_t __systick_interval
SysTick interval.
Definition: utils.c:59
IS_SYSTICK_INTERVAL
#define IS_SYSTICK_INTERVAL(x)
Definition: utils.h:128
TICK_INT_PRIORITY
#define TICK_INT_PRIORITY
Definition: ald_conf.h:62

◆ ald_tick_init()

void ald_tick_init ( uint32_t prio )

This function configures the source of the time base. The time source is configured to have 1ms time base with a dedicated Tick interrupt priority.

Note
In the default implementation, SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Care must be taken if ald_delay_ms() is called from a peripheral ISR process, The SysTick interrupt must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. The function is declared as __weak to be overwritten in case of other implementation in user file.
Parameters
prio Tick interrupt priority.
Return values
None

Definition at line 138 of file utils.c.

139 {
140 /* Configure the SysTick IRQ */
141 NVIC_SetPriority(SysTick_IRQn, prio);
142 SysTick_Config(ald_cmu_get_sys_clock() / SYSTICK_INTERVAL_1MS);
143
144 return;
145 }
ald_cmu_get_sys_clock
uint32_t ald_cmu_get_sys_clock(void)
Get SYS clock.
Definition: ald_cmu.c:616
SYSTICK_INTERVAL_1MS
Definition: utils.h:76


ALD User Manual: Control functions

Functions
Control functions
EASTSOFT ES32F3xx ALD » Utils » Public Functions

Control functions. More...

Collaboration diagram for Control functions:

Functions

__weak void | ald_systick_irq_cbk (void)
This function invoked by Systick ISR. More...
__weak void | ald_inc_tick (void)
This function is called to increment a global variable "lib_tick" used as application time base. More...
__weak uint32_t | ald_get_tick (void)
Provides a tick value in millisecond. More...
__weak void | ald_delay_ms (__IO uint32_t delay)
This function provides accurate delay (in milliseconds) based on variable incremented. More...
__weak void | ald_suspend_tick (void)
Suspend Tick increment. More...
__weak void | ald_resume_tick (void)
Resume Tick increment. More...
uint32_t | ald_get_ald_version (void)
This method returns the ALD revision. More...
void | ald_flash_wait_config (uint8_t cycle)
Configure the flash wait period. More...
ald_status_t | ald_wait_flag (uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout)
Waiting the specified bit in the register change to SET/RESET. More...
void | ald_mcu_irq_config (IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, type_func_t status)
Configure interrupt. More...
void | ald_mcu_timestamp_init (void)
Initialize core timestamp. More...
uint32_t | ald_mcu_get_timestamp (void)
Get core timestamp. More...
uint32_t | ald_mcu_get_cpu_id (void)
Get the CPU ID. More...
void | ald_mcu_get_uid (uint8_t *buf)
Get the UID. More...
uint32_t | ald_mcu_get_chipid (void)
Get the CHIPID. More...

Detailed Description

Control functions.

===============================================================================
                     ##### Control functions #####
===============================================================================
   [..]  This section provides functions allowing to:
     (+) Provide a tick value in millisecond
     (+) Provide a blocking delay in millisecond
     (+) Suspend the time base source interrupt
     (+) Resume the time base source interrupt
     (+) Get the ALD version
     (+) Waiting for flag
     (+) Configure the interrupt
     (+) Provide system tick value
     (+) Initialize core timestamp
     (+) Get core timestamp
     (+) Get CPU ID
     (+) Get UID
     (+) Get CHIPID

Function Documentation

◆ ald_delay_ms()

void ald_delay_ms ( __IO uint32_t delay )

This function provides accurate delay (in milliseconds) based on variable incremented.

Note
In the default implementation, SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals where lib_tick is incremented.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Parameters
delay specifies the delay time length, in milliseconds.
Return values
None

Definition at line 247 of file utils.c.

248 {
249 uint32_t tick, __delay;
250
251 switch (__systick_interval) {
252 case SYSTICK_INTERVAL_1MS:
253 __delay = delay;
254 break;
255
256 case SYSTICK_INTERVAL_10MS:
257 __delay = delay / 10;
258 break;
259
260 case SYSTICK_INTERVAL_100MS:
261 __delay = delay / 100;
262 break;
263
264 case SYSTICK_INTERVAL_1000MS:
265 __delay = delay / 1000;
266 break;
267
268 default:
269 __delay = delay;
270 break;
271 }
272
273 tick = ald_get_tick();
274 __delay = __delay == 0 ? 1 : __delay;
275
276 while ((ald_get_tick() - tick) < __delay)
277 ;
278 }
SYSTICK_INTERVAL_10MS
Definition: utils.h:77
SYSTICK_INTERVAL_1MS
Definition: utils.h:76
SYSTICK_INTERVAL_100MS
Definition: utils.h:78
__systick_interval
uint32_t __systick_interval
SysTick interval.
Definition: utils.c:59
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
SYSTICK_INTERVAL_1000MS
Definition: utils.h:79

◆ ald_flash_wait_config()

void ald_flash_wait_config ( uint8_t cycle )

Configure the flash wait period.

Parameters
cycle The period.
Return values
None

Definition at line 324 of file utils.c.

325 {
326 uint32_t tmp;
327
328 tmp = MSC->MEMWAIT;
329 MODIFY_REG(tmp, MSC_MEMWAIT_FLASH_W_MSK, (0x30U | cycle) << MSC_MEMWAIT_FLASH_W_POSS);
330 MSC->MEMWAIT = tmp;
331
332 return;
333 }
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74

◆ ald_get_ald_version()

uint32_t ald_get_ald_version ( void )

This method returns the ALD revision.

Return values
version 0xXYZR (8bits for each decimal, R for RC)

Definition at line 314 of file utils.c.

315 {
316 return __ALD_VERSION;
317 }
__ALD_VERSION
#define __ALD_VERSION
Definition: utils.c:45

◆ ald_get_tick()

uint32_t ald_get_tick ( void )

Provides a tick value in millisecond.

Note
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values
tick value

Definition at line 231 of file utils.c.

232 {
233 return lib_tick;
234 }
lib_tick
static __IO uint32_t lib_tick
lib_tick: Increase by one millisecond
Definition: utils.c:58

◆ ald_inc_tick()

void ald_inc_tick ( void )

This function is called to increment a global variable "lib_tick" used as application time base.

Note
In the default implementation, this variable is incremented each 1ms in Systick ISR.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values
None

Definition at line 219 of file utils.c.

220 {
221 ++lib_tick;
222 ald_systick_irq_cbk();
223 }
lib_tick
static __IO uint32_t lib_tick
lib_tick: Increase by one millisecond
Definition: utils.c:58
ald_systick_irq_cbk
__weak void ald_systick_irq_cbk(void)
This function invoked by Systick ISR.
Definition: utils.c:204

◆ ald_mcu_get_chipid()

uint32_t ald_mcu_get_chipid ( void )

Get the CHIPID.

Return values
CHPID

Definition at line 452 of file utils.c.

453 {
454 return (uint32_t)*(uint32_t *)MCU_CHIPID_ADDR;
455 }
MCU_CHIPID_ADDR
#define MCU_CHIPID_ADDR
Definition: utils.h:120

◆ ald_mcu_get_cpu_id()

uint32_t ald_mcu_get_cpu_id ( void )

Get the CPU ID.

Return values
CPU ID.

Definition at line 429 of file utils.c.

430 {
431 return SCB->CPUID;
432 }

◆ ald_mcu_get_timestamp()

uint32_t ald_mcu_get_timestamp ( void )

Get core timestamp.

Return values
None

Definition at line 420 of file utils.c.

421 {
422 return (uint32_t)DWT_CYCCNT;
423 }
DWT_CYCCNT
#define DWT_CYCCNT
Definition: utils.h:122

◆ ald_mcu_get_uid()

void ald_mcu_get_uid ( uint8_t * buf )

Get the UID.

Parameters
buf Pointer to UID, len: 12Bytes(96-bits)
Return values
None

Definition at line 439 of file utils.c.

440 {
441 memcpy(&buf[0], (void *)MCU_UID0_ADDR, 4);
442 memcpy(&buf[4], (void *)MCU_UID1_ADDR, 4);
443 memcpy(&buf[8], (void *)MCU_UID2_ADDR, 4);
444
445 return;
446 }
MCU_UID2_ADDR
#define MCU_UID2_ADDR
Definition: utils.h:119
MCU_UID1_ADDR
#define MCU_UID1_ADDR
Definition: utils.h:118
MCU_UID0_ADDR
#define MCU_UID0_ADDR
Definition: utils.h:117

◆ ald_mcu_irq_config()

void ald_mcu_irq_config | ( | IRQn_Type | irq,
 |  | uint8_t | preempt_prio,
 |  | uint8_t | sub_prio,
 |  | type_func_t | status
 | ) |  |

Configure interrupt.

Parameters
irq | Interrunpt type.
preempt_prio | preempt priority(0-3).
sub_prio | sub-priority(0-3).
status Status.
  • ENABLE
  • DISABLE
Return values
None

Definition at line 375 of file utils.c.

376 {
377 uint32_t pri;
378 uint8_t sub_bw, pre_bw;
379 uint8_t sub_mask = 0xF;
380
381 assert_param(IS_FUNC_STATE(status));
382 assert_param(IS_PREEMPT_PRIO(preempt_prio));
383 assert_param(IS_SUB_PRIO(sub_prio));
384
385 if (status == ENABLE) {
386 pre_bw = 7 - (((SCB->AIRCR) >> 8) & 7);
387 sub_bw = 4 - pre_bw;
388 sub_mask >>= pre_bw;
389
390 pri = preempt_prio << sub_bw;
391 pri |= sub_prio & sub_mask;
392
393 NVIC_SetPriority(irq, pri);
394 NVIC_EnableIRQ(irq);
395 }
396 else {
397 NVIC_DisableIRQ(irq);
398 }
399
400 return;
401 }
ENABLE
Definition: type.h:49
assert_param
#define assert_param(x)
Definition: type.h:88
IS_SUB_PRIO
#define IS_SUB_PRIO(x)
Definition: utils.h:127
IS_PREEMPT_PRIO
#define IS_PREEMPT_PRIO(x)
Definition: utils.h:126
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73

◆ ald_mcu_timestamp_init()

void ald_mcu_timestamp_init ( void )

Initialize core timestamp.

Return values
None

Definition at line 407 of file utils.c.

408 {
409 DEM_CR |= (uint32_t)DEM_CR_TRCENA;
410 DWT_CYCCNT = 0x0;
411 DWT_CR |= (uint32_t)DWT_CR_CYCCNTEA;
412
413 return;
414 }
DWT_CR
#define DWT_CR
Definition: utils.h:121
DEM_CR_TRCENA
#define DEM_CR_TRCENA
Definition: utils.h:124
DWT_CYCCNT
#define DWT_CYCCNT
Definition: utils.h:122
DWT_CR_CYCCNTEA
#define DWT_CR_CYCCNTEA
Definition: utils.h:125
DEM_CR
#define DEM_CR
Definition: utils.h:123

◆ ald_resume_tick()

void ald_resume_tick ( void )

Resume Tick increment.

Note
In the default implementation, SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once ald_resume_tick() is called, the the SysTick interrupt will be enabled and so Tick increment is resumed.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values
None

Definition at line 305 of file utils.c.

306 {
307 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
308 }
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67

◆ ald_suspend_tick()

void ald_suspend_tick ( void )

Suspend Tick increment.

Note
In the default implementation, SysTick timer is the source of time base. It is used to generate interrupts at regular time intervals. Once ald_suspend_tick() is called, the the SysTick interrupt will be disabled and so Tick increment is suspended.
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values
None

Definition at line 290 of file utils.c.

291 {
292 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
293 }
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68

◆ ald_systick_irq_cbk()

void ald_systick_irq_cbk ( void )

This function invoked by Systick ISR.

Note
This function is declared as __weak to be overwritten in case of other implementations in user file.
Return values
None

Definition at line 204 of file utils.c.

205 {
206 /* do nothing */
207 return;
208 }

◆ ald_wait_flag()

ald_status_t ald_wait_flag | ( | uint32_t * | reg,
 |  | uint32_t | bit,
 |  | flag_status_t | status,
 |  | uint32_t | timeout
 | ) |  |

Waiting the specified bit in the register change to SET/RESET.

Parameters
reg | The register address.
bit | The specified bit.
status | The status for waiting.
timeout | Timeout duration.
Return values
Status,see ald_status_t.

Definition at line 343 of file utils.c.

344 {
345 uint32_t tick = ald_get_tick();
346
347 assert_param(timeout > 0);
348
349 if (status == SET) {
350 while (!(IS_BIT_SET(*reg, bit))) {
351 if (((ald_get_tick()) - tick) > timeout)
352 return TIMEOUT;
353 }
354 }
355 else {
356 while ((IS_BIT_SET(*reg, bit))) {
357 if (((ald_get_tick()) - tick) > timeout)
358 return TIMEOUT;
359 }
360 }
361
362 return OK;
363 }
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
IS_BIT_SET
#define IS_BIT_SET(reg, bit)
Definition: utils.h:89
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58


ALD User Manual: Public Types

Enumerations | Variables
Public Types
EASTSOFT ES32F3xx ALD » Utils
Collaboration diagram for Public Types:

Enumerations

enum | ald_status_t { OK = 0x0U, ERROR = 0x1U, BUSY = 0x2U, TIMEOUT = 0x3U }
ALD Status structures definition. More...
enum nvic_priority_group_t {
NVIC_PRIORITY_GROUP_0 = 0x7U, NVIC_PRIORITY_GROUP_1 = 0x6U, NVIC_PRIORITY_GROUP_2 = 0x5U, NVIC_PRIORITY_GROUP_3 = 0x4U,
NVIC_PRIORITY_GROUP_4 = 0x3U
}
NVIC Preemption Priority Group. More...
enum | systick_interval_t { SYSTICK_INTERVAL_1MS = 1000U, SYSTICK_INTERVAL_10MS = 100U, SYSTICK_INTERVAL_100MS = 10U, SYSTICK_INTERVAL_1000MS = 1U }
SysTick interval definition. More...

Variables

uint32_t __systick_interval
SysTick interval. More...

Detailed Description

Enumeration Type Documentation

◆ ald_status_t

enum ald_status_t

ALD Status structures definition.

Enumerator
OK | OK
ERROR | ERROR
BUSY | BUSY
TIMEOUT | TIMEOUT

Definition at line 54 of file utils.h.

54 {
55 OK = 0x0U,
56 ERROR = 0x1U,
57 BUSY = 0x2U,
58 TIMEOUT = 0x3U,
59 } ald_status_t;
OK
Definition: utils.h:55
BUSY
Definition: utils.h:57
TIMEOUT
Definition: utils.h:58
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
ERROR
Definition: utils.h:56

◆ nvic_priority_group_t

enum nvic_priority_group_t

NVIC Preemption Priority Group.

Enumerator
NVIC_PRIORITY_GROUP_0 | 0-bits for pre-emption priority 4-bits for subpriority
NVIC_PRIORITY_GROUP_1 | 1-bits for pre-emption priority 3-bits for subpriority
NVIC_PRIORITY_GROUP_2 | 2-bits for pre-emption priority 2-bits for subpriority
NVIC_PRIORITY_GROUP_3 | 3-bits for pre-emption priority 1-bits for subpriority
NVIC_PRIORITY_GROUP_4 | 4-bits for pre-emption priority 0-bits for subpriority

Definition at line 64 of file utils.h.

64 {
65 NVIC_PRIORITY_GROUP_0 = 0x7U,
66 NVIC_PRIORITY_GROUP_1 = 0x6U,
67 NVIC_PRIORITY_GROUP_2 = 0x5U,
68 NVIC_PRIORITY_GROUP_3 = 0x4U,
69 NVIC_PRIORITY_GROUP_4 = 0x3U,
70 } nvic_priority_group_t;
nvic_priority_group_t
nvic_priority_group_t
NVIC Preemption Priority Group.
Definition: utils.h:64
NVIC_PRIORITY_GROUP_4
Definition: utils.h:69
NVIC_PRIORITY_GROUP_0
Definition: utils.h:65
NVIC_PRIORITY_GROUP_2
Definition: utils.h:67
NVIC_PRIORITY_GROUP_1
Definition: utils.h:66
NVIC_PRIORITY_GROUP_3
Definition: utils.h:68

◆ systick_interval_t

enum systick_interval_t

SysTick interval definition.

Enumerator
SYSTICK_INTERVAL_1MS | Interval is 1ms
SYSTICK_INTERVAL_10MS | Interval is 10ms
SYSTICK_INTERVAL_100MS | Interval is 100ms
SYSTICK_INTERVAL_1000MS | Interval is 1s

Definition at line 75 of file utils.h.

75 {
76 SYSTICK_INTERVAL_1MS = 1000U,
77 SYSTICK_INTERVAL_10MS = 100U,
78 SYSTICK_INTERVAL_100MS = 10U,
79 SYSTICK_INTERVAL_1000MS = 1U,
80 } systick_interval_t;
SYSTICK_INTERVAL_10MS
Definition: utils.h:77
SYSTICK_INTERVAL_1MS
Definition: utils.h:76
SYSTICK_INTERVAL_100MS
Definition: utils.h:78
systick_interval_t
systick_interval_t
SysTick interval definition.
Definition: utils.h:75
SYSTICK_INTERVAL_1000MS
Definition: utils.h:79

Variable Documentation

◆ __systick_interval

uint32_t __systick_interval

SysTick interval.

Definition at line 59 of file utils.c.


ALD User Manual: Public Macros

Macros
Public Macros
EASTSOFT ES32F3xx ALD » Utils
Collaboration diagram for Public Macros:

Macros

#define | ALD_MAX_DELAY 0xFFFFFFFFU
#define | IS_BIT_SET(reg, bit) (((reg) & (bit)) != RESET)
#define | IS_BIT_CLR(reg, bit) (((reg) & (bit)) == RESET)
#define | RESET_HANDLE_STATE(x) ((x)->state = 0)
#define | __LOCK(x)
#define | __UNLOCK(x)
#define | ALD_PANIC()

Detailed Description

Macro Definition Documentation

◆ __LOCK

#define __LOCK ( x )
Value:
do { \
if ((x)->lock == LOCK) { \
return BUSY; \
} \
else { \
(x)->lock = LOCK; \
} \
} while (0)
BUSY
Definition: utils.h:57
LOCK
Definition: type.h:60

Definition at line 92 of file utils.h.

◆ __UNLOCK

#define __UNLOCK ( x )
Value:
do { \
(x)->lock = UNLOCK; \
} while (0)
UNLOCK
Definition: type.h:59

Definition at line 101 of file utils.h.

◆ ALD_MAX_DELAY

#define ALD_MAX_DELAY 0xFFFFFFFFU

Definition at line 88 of file utils.h.

◆ ALD_PANIC

#define ALD_PANIC ( )
Value:
do { \
while (1) \
; \
} while (0)

Definition at line 105 of file utils.h.

◆ IS_BIT_CLR

#define IS_BIT_CLR | ( | reg,
 |  | bit
 | ) | (((reg) & (bit)) == RESET)

Definition at line 90 of file utils.h.

◆ IS_BIT_SET

#define IS_BIT_SET | ( | reg,
 |  | bit
 | ) | (((reg) & (bit)) != RESET)

Definition at line 89 of file utils.h.

◆ RESET_HANDLE_STATE

#define RESET_HANDLE_STATE ( x ) ((x)->state = 0)

Definition at line 91 of file utils.h.


ALD User Manual: Private Macros

Macros
Private Macros
EASTSOFT ES32F3xx ALD » Utils
Collaboration diagram for Private Macros:

Macros

#define | MCU_UID0_ADDR 0x000803E0U
#define | MCU_UID1_ADDR 0x000803E8U
#define | MCU_UID2_ADDR 0x000803F0U
#define | MCU_CHIPID_ADDR 0x000803F8U
#define | DWT_CR *(uint32_t *)0xE0001000U
#define | DWT_CYCCNT *(volatile uint32_t *)0xE0001004U
#define | DEM_CR *(uint32_t *)0xE000EDFCU
#define | DEM_CR_TRCENA (1U << 24)
#define | DWT_CR_CYCCNTEA (1U << 0)
#define | IS_PREEMPT_PRIO(x) ((x) < 16)
#define | IS_SUB_PRIO(x) ((x) < 16)
#define | IS_SYSTICK_INTERVAL(x)

Detailed Description

Macro Definition Documentation

◆ DEM_CR

#define DEM_CR *(uint32_t *)0xE000EDFCU

Definition at line 123 of file utils.h.

◆ DEM_CR_TRCENA

#define DEM_CR_TRCENA (1U << 24)

Definition at line 124 of file utils.h.

◆ DWT_CR

#define DWT_CR *(uint32_t *)0xE0001000U

Definition at line 121 of file utils.h.

◆ DWT_CR_CYCCNTEA

#define DWT_CR_CYCCNTEA (1U << 0)

Definition at line 125 of file utils.h.

◆ DWT_CYCCNT

#define DWT_CYCCNT *(volatile uint32_t *)0xE0001004U

Definition at line 122 of file utils.h.

◆ IS_PREEMPT_PRIO

#define IS_PREEMPT_PRIO ( x ) ((x) < 16)

Definition at line 126 of file utils.h.

◆ IS_SUB_PRIO

#define IS_SUB_PRIO ( x ) ((x) < 16)

Definition at line 127 of file utils.h.

◆ IS_SYSTICK_INTERVAL

#define IS_SYSTICK_INTERVAL ( x )
Value:
(((x) == SYSTICK_INTERVAL_1MS) || \
((x) == SYSTICK_INTERVAL_10MS) || \
((x) == SYSTICK_INTERVAL_100MS) || \
((x) == SYSTICK_INTERVAL_1000MS))
SYSTICK_INTERVAL_10MS
Definition: utils.h:77
SYSTICK_INTERVAL_1MS
Definition: utils.h:76
SYSTICK_INTERVAL_100MS
Definition: utils.h:78
SYSTICK_INTERVAL_1000MS
Definition: utils.h:79

Definition at line 128 of file utils.h.

◆ MCU_CHIPID_ADDR

#define MCU_CHIPID_ADDR 0x000803F8U

Definition at line 120 of file utils.h.

◆ MCU_UID0_ADDR

#define MCU_UID0_ADDR 0x000803E0U

Definition at line 117 of file utils.h.

◆ MCU_UID1_ADDR

#define MCU_UID1_ADDR 0x000803E8U

Definition at line 118 of file utils.h.

◆ MCU_UID2_ADDR

#define MCU_UID2_ADDR 0x000803F0U

Definition at line 119 of file utils.h.


ALD User Manual: Data Structures

Data Structures
Here are the data structures with brief descriptions:
C acmp_handle_s | ACMP Handle Structure definition
C acmp_init_t | ACMP init structure definition
C adc_analog_wdg_conf_t | ADC Configuration analog watchdog definition
C adc_handle_s | ADC handle Structure definition
C adc_ich_conf_t | ADC Configuration insert Channel structure definition
C adc_init_t | ADC trigger conversion mode
C adc_nch_conf_t | Structure definition of ADC channel for normal group
C adc_timer_config_t | Timer trigger adc config structure definition
C ald_ebi_nand_init_t | EBI NAND Configuration Structure definition
C ald_ebi_nand_timing_t | EBI NAND Timing parameters structure definition
C ald_ebi_nor_sram_init_t | EBI NORSRAM Configuration Structure definition
C ald_ebi_nor_sram_timing_t | EBI NORSRAM Timing parameters structure definition
C can_filter_t | CAN filter configuration structure definition
C can_handle_s | CAN handle Structure definition
C can_init_t | CAN init structure definition
C can_rx_msg_t | CAN Rx message structure definition
C can_tx_msg_t | CAN Tx message structure definition
C crc_handle_s | CRC Handle Structure definition
C crc_init_t | CRC init structure definition
C crypt_handle_s | CRYPT Handle Structure definition
C crypt_init_t | CRYPT init structure definition
C dac_channel_config_t | DAC channel initialize structure definition
C dac_handle_s | DAC handle Structure definition
C dac_init_t | DAC init structure definition
C dma_call_back_t | Callback function pointer and param
C dma_config_t | DMA channal configure structure
C dma_ctrl_t | DMA Descriptor control type
C dma_descriptor_t | Channel control data structure
C dma_handle_t | DMA handle structure definition
C ebi_lcd_handle_t | NOR LCD handle Structure definition
C ebi_lcd_init_t | EBI LCD parameters structure definition
C exti_init_t | EXTI Init Structure definition
C gpio_init_t | GPIO Init Structure definition
C i2c_handle_s | I2C handle Structure definition
C i2c_init_t | I2C Configuration Structure definition
C i2s_handle_s | I2S handle structure definition
C i2s_init_t | I2S init structure definition
C nand_address_t | NAND Memory address Structure definition
C nand_device_cfg_t | NAND Memory info Structure definition
C nand_handle_t | NAND handle Structure definition
C nand_id_t | NAND Memory electronic signature Structure definition
C nor_cfi_t | EBI NOR CFI typedef
C nor_handle_t | NOR handle Structure definition
C nor_id_t | EBI NOR ID typedef
C pis_handle_s | PIS Handle Structure definition
C pis_init_t | PIS init structure definition
C pis_modulate_config_t | PIS modulate config structure definition
C qspi_auto_poll_t | QSPI Auto Poll Configuration Struction
C qspi_dac_cfg_t | QSPI DAC configuration
C qspi_data_capture_cfg_t | QSPI Read Data Capture Configuration
C qspi_device_size_t | Qspi external flash device configuration
C qspi_dly_cfg_t | Defines command to be executed using STIG mechanism
C qspi_handle_t | QSPI Handle Structure definition
C qspi_indac_cfg_t |
C qspi_indac_rd_cfg_t |
C qspi_indac_wr_cfg_t | QSPI Indirect Configuration structure.involatile parameters
C qspi_init_t | QSPI base initialization structure
C qspi_legacy_cfg_t | QSPI legacy initialization structure
C qspi_read_cfg_t | QSPI Device Read Instruction Configuration structure
C qspi_stig_cmd_t | QSPI STIG Command Structure
C qspi_wr_protect_t | Flash write-protected blocks configuration
C qspi_write_cfg_t | QSPI Device Write Instruction Configuration structure
C rtc_alarm_t | Alarm structure
C rtc_cali_t | Calibration structure
C rtc_date_t | Date structure
C rtc_hw_cali_offset_t | Hardware calibration structure
C rtc_init_t | Initialization structure
C rtc_tamper_t | Tamper structure
C rtc_time_t | Time structure
C RTCINFO_TypeDef | Parameters table of rtc calibration
C spi_handle_s | SPI handle structure definition
C spi_init_t | SPI init structure definition
C sram_handle_t | SRAM handle Structure definition
C timer_base_init_t | TIMER time base configuration structure definition
C timer_break_dead_time_t | TIMER break and dead time configuretion structure definition
C timer_channel_config_t | TIMER commutation event channel configuretion structure definition
C timer_clear_input_config_t | TIMER clear input configuration handle structure definition
C timer_clock_config_t | TIMER clock config structure definition
C timer_com_channel_config_t | TIMER commutation event configuretion structure definition
C timer_encoder_init_t | TIMER encoder configuration structure definition
C timer_hall_sensor_init_t | TIMER hall sensor configuretion structure definition
C timer_handle_s | TIMER time base handle structure definition
C timer_ic_init_t | TIMER input capture configuration structure definition
C timer_master_config_t | TIMER master configuretion structure definition
C timer_oc_init_t | TIMER output compare configuration structure definition
C timer_one_pulse_init_t | TIMER one pulse mode configuration structure definition
C timer_slave_config_t | TIMER slave configuration structure definition
C trng_handle_s | TRNG Handle Structure definition
C trng_init_t | TRNG init structure definition
C uart_handle_s | UART handle structure definition
C uart_init_t | UART init structure definition
C uart_rs485_config_t | UART RS485 configure structure definition
C uart_scard_config_t | UART Smart card configure structure definition


ALD User Manual: Data Structure Index

Data Structure Index
a | c | d | e | g | i | n | p | q | r | s | t | u
a
crypt_init_t i2s_init_t qspi_indac_rd_cfg_t timer_break_dead_time_t
d
n
qspi_indac_wr_cfg_t timer_channel_config_t
acmp_handle_s qspi_init_t timer_clear_input_config_t
acmp_init_t dac_channel_config_t nand_address_t qspi_legacy_cfg_t timer_clock_config_t
adc_analog_wdg_conf_t dac_handle_s nand_device_cfg_t qspi_read_cfg_t timer_com_channel_config_t
adc_handle_s dac_init_t nand_handle_t qspi_stig_cmd_t timer_encoder_init_t
adc_ich_conf_t dma_call_back_t nand_id_t qspi_wr_protect_t timer_hall_sensor_init_t
adc_init_t dma_config_t nor_cfi_t qspi_write_cfg_t timer_handle_s
adc_nch_conf_t dma_ctrl_t nor_handle_t
r
timer_ic_init_t
adc_timer_config_t dma_descriptor_t nor_id_t timer_master_config_t
ald_ebi_nand_init_t dma_handle_t
p
rtc_alarm_t timer_oc_init_t
ald_ebi_nand_timing_t
e
rtc_cali_t timer_one_pulse_init_t
ald_ebi_nor_sram_init_t pis_handle_s rtc_date_t timer_slave_config_t
ald_ebi_nor_sram_timing_t ebi_lcd_handle_t pis_init_t rtc_hw_cali_offset_t trng_handle_s
c
ebi_lcd_init_t pis_modulate_config_t rtc_init_t trng_init_t
exti_init_t
q
rtc_tamper_t
u
can_filter_t
g
rtc_time_t
can_handle_s qspi_auto_poll_t RTCINFO_TypeDef uart_handle_s
can_init_t gpio_init_t qspi_dac_cfg_t
s
uart_init_t
can_rx_msg_t
i
qspi_data_capture_cfg_t uart_rs485_config_t
can_tx_msg_t qspi_device_size_t spi_handle_s uart_scard_config_t
crc_handle_s i2c_handle_s qspi_dly_cfg_t spi_init_t
crc_init_t i2c_init_t qspi_handle_t sram_handle_t
crypt_handle_s i2s_handle_s qspi_indac_cfg_t
t
timer_base_init_t


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- a -

  • abom : can_init_t
  • acc : rtc_cali_t
  • acc_mode : ald_ebi_nor_sram_init_t
  • acmp_edge_cplt_cbk : acmp_handle_s
  • acmp_warmup_cplt_cbk : acmp_handle_s
  • active : ald_ebi_nor_sram_init_t , can_filter_t
  • adc_ch : adc_timer_config_t
  • addr : qspi_device_size_t , qspi_stig_cmd_t , uart_rs485_config_t
  • addr_hold : ald_ebi_nor_sram_timing_t
  • addr_len : qspi_stig_cmd_t
  • addr_mode : i2c_init_t
  • addr_setup : ald_ebi_nor_sram_timing_t
  • addrremap : qspi_dac_cfg_t
  • addxfer : qspi_read_cfg_t , qspi_write_cfg_t
  • adjc : trng_init_t
  • ahbdecoder : qspi_dac_cfg_t
  • ale_time : ald_ebi_nand_init_t
  • align : adc_init_t
  • artx : can_init_t
  • asynch_pre_div : rtc_init_t
  • auto_m : adc_ich_conf_t
  • auto_out : timer_break_dead_time_t
  • autowel : qspi_write_cfg_t
  • awk : can_init_t


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- b -

  • bank : ald_ebi_nand_init_t , ald_ebi_nor_sram_init_t , ebi_lcd_init_t
  • baud : spi_init_t , uart_init_t
  • blk : qspi_device_size_t
  • block : nand_address_t
  • block_len : uart_scard_config_t
  • block_nbr : nand_device_cfg_t
  • block_size : nand_device_cfg_t
  • break_cbk : timer_handle_s
  • break_state : timer_break_dead_time_t
  • buf : adc_timer_config_t
  • burst : ald_ebi_nor_sram_init_t , dma_config_t
  • bus_dur : ald_ebi_nor_sram_timing_t
  • bypsalcc : qspi_data_capture_cfg_t


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- c -

  • cal_buf : crc_handle_s
  • cal_cplt_cbk : crc_handle_s
  • cal_res : crc_handle_s
  • calc : rtc_cali_t
  • calc_freq : rtc_cali_t
  • cali_freq : rtc_cali_t
  • capture_cbk : timer_handle_s
  • cbk : dac_handle_s
  • ccsot : qspi_dly_cfg_t
  • cfi_1 : nor_cfi_t
  • cfi_2 : nor_cfi_t
  • cfi_3 : nor_cfi_t
  • cfi_4 : nor_cfi_t
  • ch : adc_analog_wdg_conf_t , adc_ich_conf_t , adc_nch_conf_t , timer_com_channel_config_t , timer_handle_s
  • ch0_reset : dac_init_t
  • ch_len : i2s_init_t
  • channel : dma_config_t , pis_modulate_config_t
  • check_info : pis_handle_s
  • chipsel : qspi_init_t
  • chpa : qspi_init_t
  • chs_inv : crc_init_t
  • chs_rev : crc_init_t
  • cipher_text : crypt_handle_s
  • cks : exti_init_t
  • cle_time : ald_ebi_nand_init_t
  • clk_div : timer_base_init_t , uart_scard_config_t
  • clk_out : uart_scard_config_t
  • clk_polarity : ebi_lcd_init_t
  • clk_speed : i2c_init_t
  • clkdiv : qspi_init_t
  • clrsel : timer_clear_input_config_t
  • code : qspi_stig_cmd_t
  • com_cbk : timer_handle_s
  • config : adc_timer_config_t , dma_handle_t , nand_handle_t
  • consumer_ch : pis_handle_s
  • consumer_clk : pis_init_t
  • consumer_con : pis_handle_s
  • consumer_pos : pis_handle_s
  • consumer_trig : pis_init_t
  • cont : adc_init_t
  • conv_mode : dac_init_t
  • count : crypt_handle_s
  • cplt_arg : dma_call_back_t , dma_handle_t
  • cplt_cbk : adc_timer_config_t , dma_call_back_t , dma_handle_t , sram_handle_t
  • cpol : qspi_init_t
  • crc : rtc_hw_cali_offset_t
  • crc_calc : spi_init_t
  • crc_poly : spi_init_t
  • crypt_cplt_cbk : crypt_handle_s
  • cs0 : qspi_device_size_t
  • cs1 : qspi_device_size_t
  • cs2 : qspi_device_size_t
  • cs3 : qspi_device_size_t
  • csda : qspi_dly_cfg_t
  • csdads : qspi_dly_cfg_t
  • cseot : qspi_dly_cfg_t
  • ctrl : dma_descriptor_t
  • cycle_ctrl : dma_ctrl_t


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- d -

  • d_sycle : qspi_stig_cmd_t
  • data : can_rx_msg_t , can_tx_msg_t , trng_handle_s
  • data_bit : adc_init_t
  • data_inv : crc_init_t
  • data_len : i2s_init_t
  • data_polarity : ebi_lcd_init_t
  • data_rev : crc_init_t
  • data_setup : ald_ebi_nor_sram_timing_t
  • data_size : spi_init_t
  • data_width : dma_config_t , trng_init_t
  • datxfer : qspi_read_cfg_t , qspi_write_cfg_t
  • day : rtc_alarm_t , rtc_date_t
  • dcyles : qspi_read_cfg_t , qspi_write_cfg_t
  • ddrbit : qspi_read_cfg_t
  • dead_time : timer_break_dead_time_t
  • delay : timer_hall_sensor_init_t
  • delay_elapse_cbk : timer_handle_s
  • device_code1 : nor_id_t
  • device_code2 : nor_id_t
  • device_code3 : nor_id_t
  • device_id : nand_id_t
  • diff : dac_init_t
  • dir : crypt_handle_s , spi_init_t , uart_rs485_config_t
  • disc : adc_init_t
  • disc_nr : adc_init_t
  • div : adc_init_t , ald_ebi_nor_sram_timing_t , dac_init_t
  • dlydcl : qspi_data_capture_cfg_t
  • dlytd : qspi_data_capture_cfg_t
  • dma_ch : adc_timer_config_t
  • dmaperh : qspi_dac_cfg_t
  • dst : dma_config_t , dma_descriptor_t
  • dst_inc : dma_config_t , dma_ctrl_t
  • dst_prot_ctrl : dma_ctrl_t
  • dst_size : dma_ctrl_t
  • dtrprtcol : qspi_dac_cfg_t
  • dual_addr : i2c_init_t
  • dur : rtc_tamper_t


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- e -

  • ecc : ald_ebi_nand_init_t
  • edge : acmp_init_t
  • en : timer_channel_config_t
  • enable : dac_channel_config_t , ebi_lcd_init_t
  • err : can_handle_s
  • err_arg : dma_call_back_t , dma_handle_t
  • err_cbk : dma_call_back_t , dma_handle_t , i2s_handle_s , spi_handle_s
  • err_code : i2s_handle_s , spi_handle_s , uart_handle_s
  • err_cplt_cbk : crc_handle_s , crypt_handle_s , trng_handle_s
  • error_callback : i2c_handle_s
  • error_cbk : adc_handle_s , can_handle_s , timer_handle_s , uart_handle_s
  • error_code : adc_handle_s , i2c_handle_s
  • ext : can_rx_msg_t , can_tx_msg_t , nor_handle_t , sram_handle_t
  • ext_clk : i2s_init_t
  • ext_clk_en : i2s_init_t
  • ext_mode : ald_ebi_nor_sram_init_t
  • extra_cmd : nand_device_cfg_t


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- f -

  • fctl : uart_init_t
  • fifo : can_filter_t
  • filter : exti_init_t , timer_clear_input_config_t , timer_clock_config_t , timer_hall_sensor_init_t , timer_ic_init_t , timer_one_pulse_init_t , timer_slave_config_t
  • filter_time : exti_init_t
  • first_bit : spi_init_t
  • flt : gpio_init_t
  • fmi : can_rx_msg_t
  • fourth_id : nand_id_t
  • frame : spi_init_t
  • freq : rtc_tamper_t
  • FREQ_PEAK : RTCINFO_TypeDef
  • func : gpio_init_t


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- g -

  • general_call : i2c_init_t


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- h -

  • h_adc : adc_timer_config_t
  • h_dma : adc_timer_config_t
  • h_pis : adc_timer_config_t
  • h_polarity : ebi_lcd_init_t
  • h_timer : adc_timer_config_t
  • h_width : ebi_lcd_init_t
  • hdma : adc_handle_s , crc_handle_s , qspi_handle_t , sram_handle_t
  • hdma1 : timer_handle_s
  • hdma2 : timer_handle_s
  • hdma_m2p : crypt_handle_s
  • hdma_p2m : crypt_handle_s
  • hdmarx : i2c_handle_s , i2s_handle_s , spi_handle_s , uart_handle_s
  • hdmatx : i2c_handle_s , i2s_handle_s , spi_handle_s , uart_handle_s
  • high_prio : dma_config_t
  • high_thrd : adc_analog_wdg_conf_t
  • hiz_time : ald_ebi_nand_timing_t
  • hold_time : ald_ebi_nand_timing_t
  • hour : rtc_time_t
  • hour_format : rtc_init_t
  • hpis : adc_handle_s
  • hystsel : acmp_init_t


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- i -

  • ic1_filter : timer_encoder_init_t
  • ic1_polarity : timer_encoder_init_t
  • ic1_psc : timer_encoder_init_t
  • ic1_sel : timer_encoder_init_t
  • ic2_filter : timer_encoder_init_t
  • ic2_polarity : timer_encoder_init_t
  • ic2_psc : timer_encoder_init_t
  • ic2_sel : timer_encoder_init_t
  • id_high : can_filter_t
  • id_low : can_filter_t
  • idx : adc_ich_conf_t , adc_nch_conf_t , rtc_alarm_t , rtc_tamper_t
  • inactval : acmp_init_t
  • indx : qspi_auto_poll_t
  • init : acmp_handle_s , adc_handle_s , can_handle_s , crc_handle_s , crypt_handle_s , dac_handle_s , ebi_lcd_handle_t , i2c_handle_s , i2s_handle_s , nand_handle_t , nor_handle_t , pis_handle_s , qspi_handle_t , spi_handle_s , sram_handle_t , timer_handle_s , trng_handle_s , uart_handle_s
  • init_cplt_cbk : trng_handle_s
  • input : timer_slave_config_t
  • input_chan : pis_init_t
  • insert_cplt_cbk : adc_handle_s
  • inst : ebi_lcd_handle_t
  • instance : nand_handle_t , nor_handle_t , sram_handle_t
  • instxfer : qspi_read_cfg_t , qspi_write_cfg_t
  • interrupt : adc_analog_wdg_conf_t , dma_config_t
  • invert : uart_rs485_config_t
  • iv : crypt_handle_s
  • iv_size : crypt_handle_s


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- k -

  • key : crypt_handle_s , crypt_init_t
  • key_size : crypt_handle_s


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- l -

  • latency : ald_ebi_nor_sram_timing_t
  • len : can_rx_msg_t , can_tx_msg_t
  • level : pis_modulate_config_t
  • lock : acmp_handle_s , adc_handle_s , adc_timer_config_t , can_handle_s , crc_handle_s , crypt_handle_s , dac_handle_s , i2c_handle_s , i2s_handle_s , nand_handle_t , nor_handle_t , pis_handle_s , qspi_handle_t , spi_handle_s , sram_handle_t , timer_handle_s , trng_handle_s , uart_handle_s
  • lock_level : timer_break_dead_time_t
  • low_thrd : adc_analog_wdg_conf_t
  • lowblk : qspi_wr_protect_t


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- m -

  • m_code : nor_id_t
  • maker_id : nand_id_t
  • mask : rtc_alarm_t
  • mask_id_high : can_filter_t
  • mask_id_low : can_filter_t
  • master_en : timer_master_config_t
  • master_rx_cplt_cbk : i2c_handle_s
  • master_tx_cplt_cbk : i2c_handle_s
  • mbitval : qspi_read_cfg_t
  • mck_en : i2s_init_t
  • mem_rx_cplt_cbk : i2c_handle_s
  • mem_tx_cplt_cbk : i2c_handle_s
  • minute : rtc_time_t
  • mode : acmp_init_t , adc_analog_wdg_conf_t , ald_ebi_nor_sram_timing_t , can_filter_t , can_init_t , crc_init_t , crypt_init_t , gpio_init_t , i2c_handle_s , spi_init_t , timer_base_init_t , timer_channel_config_t , timer_encoder_init_t , timer_one_pulse_init_t , timer_slave_config_t , uart_init_t
  • mode_bit : qspi_stig_cmd_t
  • MODE_CALI : RTCINFO_TypeDef
  • modebit : qspi_read_cfg_t
  • module : i2c_init_t
  • month : rtc_date_t
  • msel : dma_config_t
  • msigsel : dma_config_t
  • mux : ald_ebi_nor_sram_init_t


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- n -

  • n_en : timer_channel_config_t
  • n_minus_1 : dma_ctrl_t
  • n_port : acmp_init_t
  • n_ref : adc_init_t , adc_timer_config_t , dac_init_t
  • nch_nr : adc_init_t
  • nche_sel : adc_init_t
  • next_useburst : dma_ctrl_t
  • no_stretch : i2c_init_t
  • nodrv : gpio_init_t
  • normal : uart_rs485_config_t
  • normal_cplt_cbk : adc_handle_s
  • nr : adc_ich_conf_t
  • nr_line : ebi_lcd_init_t
  • nr_pixel : ebi_lcd_init_t
  • nssdcode : qspi_init_t
  • num : can_rx_msg_t
  • number : can_filter_t


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- o -

  • o_ctrl_pis : dac_init_t
  • oc_fast_en : timer_oc_init_t
  • oc_idle : timer_oc_init_t , timer_one_pulse_init_t
  • oc_mode : timer_oc_init_t
  • oc_polarity : timer_oc_init_t , timer_one_pulse_init_t
  • ocn_idle : timer_oc_init_t , timer_one_pulse_init_t
  • ocn_polarity : timer_oc_init_t , timer_one_pulse_init_t
  • odos : gpio_init_t
  • off_idle : timer_break_dead_time_t
  • off_run : timer_break_dead_time_t
  • offset : adc_ich_conf_t
  • offset_freq_peak : rtc_hw_cali_offset_t
  • offset_htaxr : rtc_hw_cali_offset_t
  • offset_htcar : rtc_hw_cali_offset_t
  • offset_htcbr : rtc_hw_cali_offset_t
  • offset_htccr : rtc_hw_cali_offset_t
  • offset_htcdr : rtc_hw_cali_offset_t
  • offset_htcer : rtc_hw_cali_offset_t
  • offset_htgr : rtc_hw_cali_offset_t
  • offset_ltaxr : rtc_hw_cali_offset_t
  • offset_ltcar : rtc_hw_cali_offset_t
  • offset_ltcbr : rtc_hw_cali_offset_t
  • offset_ltccr : rtc_hw_cali_offset_t
  • offset_ltcdr : rtc_hw_cali_offset_t
  • offset_ltcer : rtc_hw_cali_offset_t
  • offset_ltgr : rtc_hw_cali_offset_t
  • offset_rtc_bdr : rtc_hw_cali_offset_t
  • offset_tcalbdr : rtc_hw_cali_offset_t
  • offset_temp_bdr : rtc_hw_cali_offset_t
  • offset_temp_peak : rtc_hw_cali_offset_t
  • op_addr : qspi_stig_cmd_t
  • opcode : qspi_auto_poll_t
  • out_inv : acmp_init_t
  • out_mode : dac_init_t
  • output : rtc_init_t
  • output_polarity : rtc_init_t
  • ovr_cbk : adc_handle_s
  • own_addr1 : i2c_init_t
  • own_addr2 : i2c_init_t


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- p -

  • p_adc : adc_timer_config_t
  • p_buff : i2c_handle_s
  • p_port : acmp_init_t
  • p_ref : adc_init_t , adc_timer_config_t , dac_init_t
  • p_timer : adc_timer_config_t
  • page : nand_address_t , qspi_device_size_t
  • page_size : nand_device_cfg_t
  • parity : uart_init_t
  • pcm_frame : i2s_init_t
  • perh : acmp_handle_s , adc_handle_s , can_handle_s , crc_handle_s , crypt_handle_s , dac_handle_s , dma_handle_t , i2c_handle_s , i2s_handle_s , pis_handle_s , qspi_handle_t , spi_handle_s , timer_handle_s , trng_handle_s , uart_handle_s
  • period : timer_base_init_t
  • period_elapse_cbk : timer_handle_s
  • phase : spi_init_t
  • pis_ch : dac_channel_config_t
  • plain_text : crypt_handle_s
  • plane : nand_address_t
  • plane_nbr : nand_device_cfg_t
  • plane_size : nand_device_cfg_t
  • podrv : gpio_init_t
  • polarity : ald_ebi_nor_sram_init_t , i2s_init_t , qspi_auto_poll_t , spi_init_t , timer_break_dead_time_t , timer_clear_input_config_t , timer_clock_config_t , timer_hall_sensor_init_t , timer_ic_init_t , timer_one_pulse_init_t , timer_slave_config_t
  • polexpcnt : qspi_auto_poll_t
  • posten : trng_init_t
  • prescaler : timer_base_init_t
  • primary : dma_config_t
  • producer_clk : pis_init_t
  • producer_edge : pis_init_t
  • producer_signal : pis_init_t
  • producer_src : pis_init_t
  • psc : can_init_t , timer_clear_input_config_t , timer_clock_config_t , timer_hall_sensor_init_t , timer_ic_init_t , timer_slave_config_t
  • pt : uart_scard_config_t
  • pulse : timer_oc_init_t , timer_one_pulse_init_t
  • pupd : gpio_init_t
  • pwm_pulse_finish_cbk : timer_handle_s


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- r -

  • R_power : dma_config_t , dma_ctrl_t
  • rd_buf : qspi_stig_cmd_t
  • rd_len : qspi_stig_cmd_t
  • rdcde : qspi_read_cfg_t
  • rdinit : qspi_dac_cfg_t
  • rdlen : qspi_indac_rd_cfg_t
  • rdwmark : qspi_indac_cfg_t
  • re_cnt : timer_base_init_t
  • refresh : dac_init_t
  • refresh_en : dac_channel_config_t
  • remapaddr : qspi_dac_cfg_t
  • repdly : qspi_auto_poll_t
  • reset : ebi_lcd_init_t
  • retry : uart_scard_config_t
  • rfom : can_init_t
  • rsv : rtc_hw_cali_offset_t
  • rsv0 : RTCINFO_TypeDef
  • rsv1 : RTCINFO_TypeDef
  • RTC_CALCR : RTCINFO_TypeDef
  • RTC_HTAXR : RTCINFO_TypeDef
  • RTC_HTCAR : RTCINFO_TypeDef
  • RTC_HTCBR : RTCINFO_TypeDef
  • RTC_HTCCR : RTCINFO_TypeDef
  • RTC_HTCDR : RTCINFO_TypeDef
  • RTC_HTCER : RTCINFO_TypeDef
  • RTC_LTAXR : RTCINFO_TypeDef
  • RTC_LTCAR : RTCINFO_TypeDef
  • RTC_LTCBR : RTCINFO_TypeDef
  • RTC_LTCCR : RTCINFO_TypeDef
  • RTC_LTCDR : RTCINFO_TypeDef
  • RTC_LTCER : RTCINFO_TypeDef
  • RTC_TEMPBDR : RTCINFO_TypeDef
  • rtr : can_rx_msg_t , can_tx_msg_t
  • rx0_msg : can_handle_s
  • rx1_msg : can_handle_s
  • rx_buf : i2s_handle_s , qspi_handle_t , spi_handle_s , uart_handle_s
  • rx_cnt : qspi_handle_t
  • rx_count : i2s_handle_s , spi_handle_s , uart_handle_s
  • rx_cplt_cbk : can_handle_s , i2s_handle_s , spi_handle_s , uart_handle_s
  • rx_size : i2s_handle_s , qspi_handle_t , spi_handle_s , uart_handle_s
  • rx_thrd : qspi_legacy_cfg_t


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- s -

  • saddr : qspi_indac_rd_cfg_t , qspi_indac_wr_cfg_t
  • samp : adc_ich_conf_t , adc_nch_conf_t
  • sampling : i2s_init_t
  • scale : can_filter_t
  • scan : adc_init_t
  • second : rtc_time_t
  • seed : crc_init_t , trng_init_t
  • seed_type : trng_init_t
  • seg1 : can_init_t
  • seg2 : can_init_t
  • sel : rtc_alarm_t , timer_ic_init_t , timer_master_config_t , timer_one_pulse_init_t
  • setup : ebi_lcd_init_t
  • side : i2s_handle_s
  • signal : ald_ebi_nor_sram_init_t
  • sine : dac_init_t
  • size : adc_timer_config_t , ald_ebi_nand_init_t , crypt_handle_s , dma_config_t
  • sjw : can_init_t
  • slave_rx_cplt_cbk : i2c_handle_s
  • slave_tx_cplt_cbk : i2c_handle_s
  • smpledge : qspi_data_capture_cfg_t
  • source : timer_clear_input_config_t , timer_clock_config_t
  • spare_size : nand_device_cfg_t
  • srampt : qspi_indac_cfg_t
  • src : dma_config_t , dma_descriptor_t , pis_modulate_config_t
  • src_inc : dma_config_t , dma_ctrl_t
  • src_prot_ctrl : dma_ctrl_t
  • src_size : dma_ctrl_t
  • ss_en : spi_init_t
  • ss_mask : rtc_alarm_t
  • standard : i2s_init_t
  • state : adc_handle_s , can_handle_s , crc_handle_s , crypt_handle_s , i2c_handle_s , i2s_handle_s , nand_handle_t , nor_handle_t , pis_handle_s , qspi_handle_t , spi_handle_s , sram_handle_t , timer_clear_input_config_t , timer_handle_s , trng_handle_s , uart_handle_s
  • std : can_rx_msg_t , can_tx_msg_t
  • step : crypt_handle_s
  • stop_bits : uart_init_t
  • sub_sec : rtc_time_t
  • SUM : RTCINFO_TypeDef
  • SUM_MINUS : RTCINFO_TypeDef
  • synch_pre_div : rtc_init_t


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- t -

  • t_start : trng_init_t
  • target : pis_modulate_config_t
  • tc : rtc_cali_t
  • TEMP_CALI : RTCINFO_TypeDef
  • TEMP_CALI_AFTER : RTCINFO_TypeDef
  • TEMP_CR : RTCINFO_TypeDef
  • TEMP_HTGR : RTCINFO_TypeDef
  • TEMP_LTGR : RTCINFO_TypeDef
  • TEMP_PEAK : RTCINFO_TypeDef
  • TEMP_TBDR : RTCINFO_TypeDef
  • TEMP_TCALBDR : RTCINFO_TypeDef
  • TEMP_TCALBDR_MINUS : RTCINFO_TypeDef
  • third_id : nand_id_t
  • time : adc_timer_config_t , ald_ebi_nand_timing_t , rtc_alarm_t
  • trgaddr : qspi_indac_cfg_t
  • trgrng : qspi_indac_cfg_t
  • trig : rtc_tamper_t
  • trigger : dac_channel_config_t
  • trigger_cbk : timer_handle_s
  • trng_cplt_cbk : trng_handle_s
  • ts : rtc_tamper_t
  • ttcm : can_init_t
  • tx_buf : i2s_handle_s , qspi_handle_t , spi_handle_s , uart_handle_s
  • tx_cnt : qspi_handle_t
  • tx_count : i2s_handle_s , spi_handle_s , uart_handle_s
  • tx_cplt_cbk : can_handle_s , i2s_handle_s , spi_handle_s , uart_handle_s
  • tx_rx_cplt_cbk : spi_handle_s
  • tx_size : i2s_handle_s , qspi_handle_t , spi_handle_s , uart_handle_s
  • tx_thrd : qspi_legacy_cfg_t
  • txmp : can_init_t
  • type : ald_ebi_nor_sram_init_t , can_rx_msg_t , can_tx_msg_t , crypt_init_t , gpio_init_t


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- u -

  • upblk : qspi_wr_protect_t
  • use : dma_descriptor_t


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- v -

  • v_polarity : ebi_lcd_init_t
  • v_width : ebi_lcd_init_t
  • val : qspi_stig_cmd_t
  • validcnt : qspi_auto_poll_t
  • vdd_level : acmp_init_t


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- w -

  • wait : ald_ebi_nand_init_t , ald_ebi_nor_sram_init_t
  • wait_time : ald_ebi_nand_timing_t
  • warm_time : acmp_init_t
  • wdg_cbk : adc_handle_s
  • week : rtc_alarm_t , rtc_date_t
  • width : ald_ebi_nand_init_t , ald_ebi_nor_sram_init_t
  • word : dma_ctrl_t
  • word_length : uart_init_t
  • wr_buf : qspi_stig_cmd_t
  • wr_len : qspi_stig_cmd_t
  • wrap_mode : ald_ebi_nor_sram_init_t
  • wrcde : qspi_write_cfg_t
  • wrinit : qspi_dac_cfg_t
  • write : ald_ebi_nor_sram_init_t
  • wrlen : qspi_indac_wr_cfg_t
  • wrppin : qspi_init_t
  • wrwmark : qspi_indac_cfg_t


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- x -

  • xfer_count : i2c_handle_s
  • xfer_size : i2c_handle_s
  • xipimmed : qspi_dac_cfg_t
  • xipnextrd : qspi_dac_cfg_t


ALD User Manual: Data Fields

Here is a list of all struct and union fields with links to the structures/unions they belong to:

- y -

  • year : rtc_date_t


ALD User Manual: Data Fields - Variables

- a -

  • abom : can_init_t
  • acc : rtc_cali_t
  • acc_mode : ald_ebi_nor_sram_init_t
  • acmp_edge_cplt_cbk : acmp_handle_s
  • acmp_warmup_cplt_cbk : acmp_handle_s
  • active : ald_ebi_nor_sram_init_t , can_filter_t
  • adc_ch : adc_timer_config_t
  • addr : qspi_device_size_t , qspi_stig_cmd_t , uart_rs485_config_t
  • addr_hold : ald_ebi_nor_sram_timing_t
  • addr_len : qspi_stig_cmd_t
  • addr_mode : i2c_init_t
  • addr_setup : ald_ebi_nor_sram_timing_t
  • addrremap : qspi_dac_cfg_t
  • addxfer : qspi_read_cfg_t , qspi_write_cfg_t
  • adjc : trng_init_t
  • ahbdecoder : qspi_dac_cfg_t
  • ale_time : ald_ebi_nand_init_t
  • align : adc_init_t
  • artx : can_init_t
  • asynch_pre_div : rtc_init_t
  • auto_m : adc_ich_conf_t
  • auto_out : timer_break_dead_time_t
  • autowel : qspi_write_cfg_t
  • awk : can_init_t


ALD User Manual: Data Fields - Variables

- b -

  • bank : ald_ebi_nand_init_t , ald_ebi_nor_sram_init_t , ebi_lcd_init_t
  • baud : spi_init_t , uart_init_t
  • blk : qspi_device_size_t
  • block : nand_address_t
  • block_len : uart_scard_config_t
  • block_nbr : nand_device_cfg_t
  • block_size : nand_device_cfg_t
  • break_cbk : timer_handle_s
  • break_state : timer_break_dead_time_t
  • buf : adc_timer_config_t
  • burst : ald_ebi_nor_sram_init_t , dma_config_t
  • bus_dur : ald_ebi_nor_sram_timing_t
  • bypsalcc : qspi_data_capture_cfg_t


ALD User Manual: Data Fields - Variables

- c -

  • cal_buf : crc_handle_s
  • cal_cplt_cbk : crc_handle_s
  • cal_res : crc_handle_s
  • calc : rtc_cali_t
  • calc_freq : rtc_cali_t
  • cali_freq : rtc_cali_t
  • capture_cbk : timer_handle_s
  • cbk : dac_handle_s
  • ccsot : qspi_dly_cfg_t
  • cfi_1 : nor_cfi_t
  • cfi_2 : nor_cfi_t
  • cfi_3 : nor_cfi_t
  • cfi_4 : nor_cfi_t
  • ch : adc_analog_wdg_conf_t , adc_ich_conf_t , adc_nch_conf_t , timer_com_channel_config_t , timer_handle_s
  • ch0_reset : dac_init_t
  • ch_len : i2s_init_t
  • channel : dma_config_t , pis_modulate_config_t
  • check_info : pis_handle_s
  • chipsel : qspi_init_t
  • chpa : qspi_init_t
  • chs_inv : crc_init_t
  • chs_rev : crc_init_t
  • cipher_text : crypt_handle_s
  • cks : exti_init_t
  • cle_time : ald_ebi_nand_init_t
  • clk_div : timer_base_init_t , uart_scard_config_t
  • clk_out : uart_scard_config_t
  • clk_polarity : ebi_lcd_init_t
  • clk_speed : i2c_init_t
  • clkdiv : qspi_init_t
  • clrsel : timer_clear_input_config_t
  • code : qspi_stig_cmd_t
  • com_cbk : timer_handle_s
  • config : adc_timer_config_t , dma_handle_t , nand_handle_t
  • consumer_ch : pis_handle_s
  • consumer_clk : pis_init_t
  • consumer_con : pis_handle_s
  • consumer_pos : pis_handle_s
  • consumer_trig : pis_init_t
  • cont : adc_init_t
  • conv_mode : dac_init_t
  • count : crypt_handle_s
  • cplt_arg : dma_call_back_t , dma_handle_t
  • cplt_cbk : adc_timer_config_t , dma_call_back_t , dma_handle_t , sram_handle_t
  • cpol : qspi_init_t
  • crc : rtc_hw_cali_offset_t
  • crc_calc : spi_init_t
  • crc_poly : spi_init_t
  • crypt_cplt_cbk : crypt_handle_s
  • cs0 : qspi_device_size_t
  • cs1 : qspi_device_size_t
  • cs2 : qspi_device_size_t
  • cs3 : qspi_device_size_t
  • csda : qspi_dly_cfg_t
  • csdads : qspi_dly_cfg_t
  • cseot : qspi_dly_cfg_t
  • ctrl : dma_descriptor_t
  • cycle_ctrl : dma_ctrl_t


ALD User Manual: Data Fields - Variables

- d -

  • d_sycle : qspi_stig_cmd_t
  • data : can_rx_msg_t , can_tx_msg_t , trng_handle_s
  • data_bit : adc_init_t
  • data_inv : crc_init_t
  • data_len : i2s_init_t
  • data_polarity : ebi_lcd_init_t
  • data_rev : crc_init_t
  • data_setup : ald_ebi_nor_sram_timing_t
  • data_size : spi_init_t
  • data_width : dma_config_t , trng_init_t
  • datxfer : qspi_read_cfg_t , qspi_write_cfg_t
  • day : rtc_alarm_t , rtc_date_t
  • dcyles : qspi_read_cfg_t , qspi_write_cfg_t
  • ddrbit : qspi_read_cfg_t
  • dead_time : timer_break_dead_time_t
  • delay : timer_hall_sensor_init_t
  • delay_elapse_cbk : timer_handle_s
  • device_code1 : nor_id_t
  • device_code2 : nor_id_t
  • device_code3 : nor_id_t
  • device_id : nand_id_t
  • diff : dac_init_t
  • dir : crypt_handle_s , spi_init_t , uart_rs485_config_t
  • disc : adc_init_t
  • disc_nr : adc_init_t
  • div : adc_init_t , ald_ebi_nor_sram_timing_t , dac_init_t
  • dlydcl : qspi_data_capture_cfg_t
  • dlytd : qspi_data_capture_cfg_t
  • dma_ch : adc_timer_config_t
  • dmaperh : qspi_dac_cfg_t
  • dst : dma_config_t , dma_descriptor_t
  • dst_inc : dma_config_t , dma_ctrl_t
  • dst_prot_ctrl : dma_ctrl_t
  • dst_size : dma_ctrl_t
  • dtrprtcol : qspi_dac_cfg_t
  • dual_addr : i2c_init_t
  • dur : rtc_tamper_t


ALD User Manual: Data Fields - Variables

- e -

  • ecc : ald_ebi_nand_init_t
  • edge : acmp_init_t
  • en : timer_channel_config_t
  • enable : dac_channel_config_t , ebi_lcd_init_t
  • err : can_handle_s
  • err_arg : dma_call_back_t , dma_handle_t
  • err_cbk : dma_call_back_t , dma_handle_t , i2s_handle_s , spi_handle_s
  • err_code : i2s_handle_s , spi_handle_s , uart_handle_s
  • err_cplt_cbk : crc_handle_s , crypt_handle_s , trng_handle_s
  • error_callback : i2c_handle_s
  • error_cbk : adc_handle_s , can_handle_s , timer_handle_s , uart_handle_s
  • error_code : adc_handle_s , i2c_handle_s
  • ext : can_rx_msg_t , can_tx_msg_t , nor_handle_t , sram_handle_t
  • ext_clk : i2s_init_t
  • ext_clk_en : i2s_init_t
  • ext_mode : ald_ebi_nor_sram_init_t
  • extra_cmd : nand_device_cfg_t


ALD User Manual: Data Fields - Variables

- f -

  • fctl : uart_init_t
  • fifo : can_filter_t
  • filter : exti_init_t , timer_clear_input_config_t , timer_clock_config_t , timer_hall_sensor_init_t , timer_ic_init_t , timer_one_pulse_init_t , timer_slave_config_t
  • filter_time : exti_init_t
  • first_bit : spi_init_t
  • flt : gpio_init_t
  • fmi : can_rx_msg_t
  • fourth_id : nand_id_t
  • frame : spi_init_t
  • freq : rtc_tamper_t
  • FREQ_PEAK : RTCINFO_TypeDef
  • func : gpio_init_t


ALD User Manual: Data Fields - Variables

- g -

  • general_call : i2c_init_t


ALD User Manual: Data Fields - Variables

- h -

  • h_adc : adc_timer_config_t
  • h_dma : adc_timer_config_t
  • h_pis : adc_timer_config_t
  • h_polarity : ebi_lcd_init_t
  • h_timer : adc_timer_config_t
  • h_width : ebi_lcd_init_t
  • hdma : adc_handle_s , crc_handle_s , qspi_handle_t , sram_handle_t
  • hdma1 : timer_handle_s
  • hdma2 : timer_handle_s
  • hdma_m2p : crypt_handle_s
  • hdma_p2m : crypt_handle_s
  • hdmarx : i2c_handle_s , i2s_handle_s , spi_handle_s , uart_handle_s
  • hdmatx : i2c_handle_s , i2s_handle_s , spi_handle_s , uart_handle_s
  • high_prio : dma_config_t
  • high_thrd : adc_analog_wdg_conf_t
  • hiz_time : ald_ebi_nand_timing_t
  • hold_time : ald_ebi_nand_timing_t
  • hour : rtc_time_t
  • hour_format : rtc_init_t
  • hpis : adc_handle_s
  • hystsel : acmp_init_t


ALD User Manual: Data Fields - Variables

- i -

  • ic1_filter : timer_encoder_init_t
  • ic1_polarity : timer_encoder_init_t
  • ic1_psc : timer_encoder_init_t
  • ic1_sel : timer_encoder_init_t
  • ic2_filter : timer_encoder_init_t
  • ic2_polarity : timer_encoder_init_t
  • ic2_psc : timer_encoder_init_t
  • ic2_sel : timer_encoder_init_t
  • id_high : can_filter_t
  • id_low : can_filter_t
  • idx : adc_ich_conf_t , adc_nch_conf_t , rtc_alarm_t , rtc_tamper_t
  • inactval : acmp_init_t
  • indx : qspi_auto_poll_t
  • init : acmp_handle_s , adc_handle_s , can_handle_s , crc_handle_s , crypt_handle_s , dac_handle_s , ebi_lcd_handle_t , i2c_handle_s , i2s_handle_s , nand_handle_t , nor_handle_t , pis_handle_s , qspi_handle_t , spi_handle_s , sram_handle_t , timer_handle_s , trng_handle_s , uart_handle_s
  • init_cplt_cbk : trng_handle_s
  • input : timer_slave_config_t
  • input_chan : pis_init_t
  • insert_cplt_cbk : adc_handle_s
  • inst : ebi_lcd_handle_t
  • instance : nand_handle_t , nor_handle_t , sram_handle_t
  • instxfer : qspi_read_cfg_t , qspi_write_cfg_t
  • interrupt : adc_analog_wdg_conf_t , dma_config_t
  • invert : uart_rs485_config_t
  • iv : crypt_handle_s
  • iv_size : crypt_handle_s


ALD User Manual: Data Fields - Variables

- k -

  • key : crypt_handle_s , crypt_init_t
  • key_size : crypt_handle_s


ALD User Manual: Data Fields - Variables

- l -

  • latency : ald_ebi_nor_sram_timing_t
  • len : can_rx_msg_t , can_tx_msg_t
  • level : pis_modulate_config_t
  • lock : acmp_handle_s , adc_handle_s , adc_timer_config_t , can_handle_s , crc_handle_s , crypt_handle_s , dac_handle_s , i2c_handle_s , i2s_handle_s , nand_handle_t , nor_handle_t , pis_handle_s , qspi_handle_t , spi_handle_s , sram_handle_t , timer_handle_s , trng_handle_s , uart_handle_s
  • lock_level : timer_break_dead_time_t
  • low_thrd : adc_analog_wdg_conf_t
  • lowblk : qspi_wr_protect_t


ALD User Manual: Data Fields - Variables

- m -

  • m_code : nor_id_t
  • maker_id : nand_id_t
  • mask : rtc_alarm_t
  • mask_id_high : can_filter_t
  • mask_id_low : can_filter_t
  • master_en : timer_master_config_t
  • master_rx_cplt_cbk : i2c_handle_s
  • master_tx_cplt_cbk : i2c_handle_s
  • mbitval : qspi_read_cfg_t
  • mck_en : i2s_init_t
  • mem_rx_cplt_cbk : i2c_handle_s
  • mem_tx_cplt_cbk : i2c_handle_s
  • minute : rtc_time_t
  • mode : acmp_init_t , adc_analog_wdg_conf_t , ald_ebi_nor_sram_timing_t , can_filter_t , can_init_t , crc_init_t , crypt_init_t , gpio_init_t , i2c_handle_s , spi_init_t , timer_base_init_t , timer_channel_config_t , timer_encoder_init_t , timer_one_pulse_init_t , timer_slave_config_t , uart_init_t
  • mode_bit : qspi_stig_cmd_t
  • MODE_CALI : RTCINFO_TypeDef
  • modebit : qspi_read_cfg_t
  • module : i2c_init_t
  • month : rtc_date_t
  • msel : dma_config_t
  • msigsel : dma_config_t
  • mux : ald_ebi_nor_sram_init_t


ALD User Manual: Data Fields - Variables

- n -

  • n_en : timer_channel_config_t
  • n_minus_1 : dma_ctrl_t
  • n_port : acmp_init_t
  • n_ref : adc_init_t , adc_timer_config_t , dac_init_t
  • nch_nr : adc_init_t
  • nche_sel : adc_init_t
  • next_useburst : dma_ctrl_t
  • no_stretch : i2c_init_t
  • nodrv : gpio_init_t
  • normal : uart_rs485_config_t
  • normal_cplt_cbk : adc_handle_s
  • nr : adc_ich_conf_t
  • nr_line : ebi_lcd_init_t
  • nr_pixel : ebi_lcd_init_t
  • nssdcode : qspi_init_t
  • num : can_rx_msg_t
  • number : can_filter_t


ALD User Manual: Data Fields - Variables

- o -

  • o_ctrl_pis : dac_init_t
  • oc_fast_en : timer_oc_init_t
  • oc_idle : timer_oc_init_t , timer_one_pulse_init_t
  • oc_mode : timer_oc_init_t
  • oc_polarity : timer_oc_init_t , timer_one_pulse_init_t
  • ocn_idle : timer_oc_init_t , timer_one_pulse_init_t
  • ocn_polarity : timer_oc_init_t , timer_one_pulse_init_t
  • odos : gpio_init_t
  • off_idle : timer_break_dead_time_t
  • off_run : timer_break_dead_time_t
  • offset : adc_ich_conf_t
  • offset_freq_peak : rtc_hw_cali_offset_t
  • offset_htaxr : rtc_hw_cali_offset_t
  • offset_htcar : rtc_hw_cali_offset_t
  • offset_htcbr : rtc_hw_cali_offset_t
  • offset_htccr : rtc_hw_cali_offset_t
  • offset_htcdr : rtc_hw_cali_offset_t
  • offset_htcer : rtc_hw_cali_offset_t
  • offset_htgr : rtc_hw_cali_offset_t
  • offset_ltaxr : rtc_hw_cali_offset_t
  • offset_ltcar : rtc_hw_cali_offset_t
  • offset_ltcbr : rtc_hw_cali_offset_t
  • offset_ltccr : rtc_hw_cali_offset_t
  • offset_ltcdr : rtc_hw_cali_offset_t
  • offset_ltcer : rtc_hw_cali_offset_t
  • offset_ltgr : rtc_hw_cali_offset_t
  • offset_rtc_bdr : rtc_hw_cali_offset_t
  • offset_tcalbdr : rtc_hw_cali_offset_t
  • offset_temp_bdr : rtc_hw_cali_offset_t
  • offset_temp_peak : rtc_hw_cali_offset_t
  • op_addr : qspi_stig_cmd_t
  • opcode : qspi_auto_poll_t
  • out_inv : acmp_init_t
  • out_mode : dac_init_t
  • output : rtc_init_t
  • output_polarity : rtc_init_t
  • ovr_cbk : adc_handle_s
  • own_addr1 : i2c_init_t
  • own_addr2 : i2c_init_t


ALD User Manual: Data Fields - Variables

- p -

  • p_adc : adc_timer_config_t
  • p_buff : i2c_handle_s
  • p_port : acmp_init_t
  • p_ref : adc_init_t , adc_timer_config_t , dac_init_t
  • p_timer : adc_timer_config_t
  • page : nand_address_t , qspi_device_size_t
  • page_size : nand_device_cfg_t
  • parity : uart_init_t
  • pcm_frame : i2s_init_t
  • perh : acmp_handle_s , adc_handle_s , can_handle_s , crc_handle_s , crypt_handle_s , dac_handle_s , dma_handle_t , i2c_handle_s , i2s_handle_s , pis_handle_s , qspi_handle_t , spi_handle_s , timer_handle_s , trng_handle_s , uart_handle_s
  • period : timer_base_init_t
  • period_elapse_cbk : timer_handle_s
  • phase : spi_init_t
  • pis_ch : dac_channel_config_t
  • plain_text : crypt_handle_s
  • plane : nand_address_t
  • plane_nbr : nand_device_cfg_t
  • plane_size : nand_device_cfg_t
  • podrv : gpio_init_t
  • polarity : ald_ebi_nor_sram_init_t , i2s_init_t , qspi_auto_poll_t , spi_init_t , timer_break_dead_time_t , timer_clear_input_config_t , timer_clock_config_t , timer_hall_sensor_init_t , timer_ic_init_t , timer_one_pulse_init_t , timer_slave_config_t
  • polexpcnt : qspi_auto_poll_t
  • posten : trng_init_t
  • prescaler : timer_base_init_t
  • primary : dma_config_t
  • producer_clk : pis_init_t
  • producer_edge : pis_init_t
  • producer_signal : pis_init_t
  • producer_src : pis_init_t
  • psc : can_init_t , timer_clear_input_config_t , timer_clock_config_t , timer_hall_sensor_init_t , timer_ic_init_t , timer_slave_config_t
  • pt : uart_scard_config_t
  • pulse : timer_oc_init_t , timer_one_pulse_init_t
  • pupd : gpio_init_t
  • pwm_pulse_finish_cbk : timer_handle_s


ALD User Manual: Data Fields - Variables

- r -

  • R_power : dma_config_t , dma_ctrl_t
  • rd_buf : qspi_stig_cmd_t
  • rd_len : qspi_stig_cmd_t
  • rdcde : qspi_read_cfg_t
  • rdinit : qspi_dac_cfg_t
  • rdlen : qspi_indac_rd_cfg_t
  • rdwmark : qspi_indac_cfg_t
  • re_cnt : timer_base_init_t
  • refresh : dac_init_t
  • refresh_en : dac_channel_config_t
  • remapaddr : qspi_dac_cfg_t
  • repdly : qspi_auto_poll_t
  • reset : ebi_lcd_init_t
  • retry : uart_scard_config_t
  • rfom : can_init_t
  • rsv : rtc_hw_cali_offset_t
  • rsv0 : RTCINFO_TypeDef
  • rsv1 : RTCINFO_TypeDef
  • RTC_CALCR : RTCINFO_TypeDef
  • RTC_HTAXR : RTCINFO_TypeDef
  • RTC_HTCAR : RTCINFO_TypeDef
  • RTC_HTCBR : RTCINFO_TypeDef
  • RTC_HTCCR : RTCINFO_TypeDef
  • RTC_HTCDR : RTCINFO_TypeDef
  • RTC_HTCER : RTCINFO_TypeDef
  • RTC_LTAXR : RTCINFO_TypeDef
  • RTC_LTCAR : RTCINFO_TypeDef
  • RTC_LTCBR : RTCINFO_TypeDef
  • RTC_LTCCR : RTCINFO_TypeDef
  • RTC_LTCDR : RTCINFO_TypeDef
  • RTC_LTCER : RTCINFO_TypeDef
  • RTC_TEMPBDR : RTCINFO_TypeDef
  • rtr : can_rx_msg_t , can_tx_msg_t
  • rx0_msg : can_handle_s
  • rx1_msg : can_handle_s
  • rx_buf : i2s_handle_s , qspi_handle_t , spi_handle_s , uart_handle_s
  • rx_cnt : qspi_handle_t
  • rx_count : i2s_handle_s , spi_handle_s , uart_handle_s
  • rx_cplt_cbk : can_handle_s , i2s_handle_s , spi_handle_s , uart_handle_s
  • rx_size : i2s_handle_s , qspi_handle_t , spi_handle_s , uart_handle_s
  • rx_thrd : qspi_legacy_cfg_t


ALD User Manual: Data Fields - Variables

- s -

  • saddr : qspi_indac_rd_cfg_t , qspi_indac_wr_cfg_t
  • samp : adc_ich_conf_t , adc_nch_conf_t
  • sampling : i2s_init_t
  • scale : can_filter_t
  • scan : adc_init_t
  • second : rtc_time_t
  • seed : crc_init_t , trng_init_t
  • seed_type : trng_init_t
  • seg1 : can_init_t
  • seg2 : can_init_t
  • sel : rtc_alarm_t , timer_ic_init_t , timer_master_config_t , timer_one_pulse_init_t
  • setup : ebi_lcd_init_t
  • side : i2s_handle_s
  • signal : ald_ebi_nor_sram_init_t
  • sine : dac_init_t
  • size : adc_timer_config_t , ald_ebi_nand_init_t , crypt_handle_s , dma_config_t
  • sjw : can_init_t
  • slave_rx_cplt_cbk : i2c_handle_s
  • slave_tx_cplt_cbk : i2c_handle_s
  • smpledge : qspi_data_capture_cfg_t
  • source : timer_clear_input_config_t , timer_clock_config_t
  • spare_size : nand_device_cfg_t
  • srampt : qspi_indac_cfg_t
  • src : dma_config_t , dma_descriptor_t , pis_modulate_config_t
  • src_inc : dma_config_t , dma_ctrl_t
  • src_prot_ctrl : dma_ctrl_t
  • src_size : dma_ctrl_t
  • ss_en : spi_init_t
  • ss_mask : rtc_alarm_t
  • standard : i2s_init_t
  • state : adc_handle_s , can_handle_s , crc_handle_s , crypt_handle_s , i2c_handle_s , i2s_handle_s , nand_handle_t , nor_handle_t , pis_handle_s , qspi_handle_t , spi_handle_s , sram_handle_t , timer_clear_input_config_t , timer_handle_s , trng_handle_s , uart_handle_s
  • std : can_rx_msg_t , can_tx_msg_t
  • step : crypt_handle_s
  • stop_bits : uart_init_t
  • sub_sec : rtc_time_t
  • SUM : RTCINFO_TypeDef
  • SUM_MINUS : RTCINFO_TypeDef
  • synch_pre_div : rtc_init_t


ALD User Manual: Data Fields - Variables

- t -

  • t_start : trng_init_t
  • target : pis_modulate_config_t
  • tc : rtc_cali_t
  • TEMP_CALI : RTCINFO_TypeDef
  • TEMP_CALI_AFTER : RTCINFO_TypeDef
  • TEMP_CR : RTCINFO_TypeDef
  • TEMP_HTGR : RTCINFO_TypeDef
  • TEMP_LTGR : RTCINFO_TypeDef
  • TEMP_PEAK : RTCINFO_TypeDef
  • TEMP_TBDR : RTCINFO_TypeDef
  • TEMP_TCALBDR : RTCINFO_TypeDef
  • TEMP_TCALBDR_MINUS : RTCINFO_TypeDef
  • third_id : nand_id_t
  • time : adc_timer_config_t , ald_ebi_nand_timing_t , rtc_alarm_t
  • trgaddr : qspi_indac_cfg_t
  • trgrng : qspi_indac_cfg_t
  • trig : rtc_tamper_t
  • trigger : dac_channel_config_t
  • trigger_cbk : timer_handle_s
  • trng_cplt_cbk : trng_handle_s
  • ts : rtc_tamper_t
  • ttcm : can_init_t
  • tx_buf : i2s_handle_s , qspi_handle_t , spi_handle_s , uart_handle_s
  • tx_cnt : qspi_handle_t
  • tx_count : i2s_handle_s , spi_handle_s , uart_handle_s
  • tx_cplt_cbk : can_handle_s , i2s_handle_s , spi_handle_s , uart_handle_s
  • tx_rx_cplt_cbk : spi_handle_s
  • tx_size : i2s_handle_s , qspi_handle_t , spi_handle_s , uart_handle_s
  • tx_thrd : qspi_legacy_cfg_t
  • txmp : can_init_t
  • type : ald_ebi_nor_sram_init_t , can_rx_msg_t , can_tx_msg_t , crypt_init_t , gpio_init_t


ALD User Manual: Data Fields - Variables

- u -

  • upblk : qspi_wr_protect_t
  • use : dma_descriptor_t


ALD User Manual: Data Fields - Variables

- v -

  • v_polarity : ebi_lcd_init_t
  • v_width : ebi_lcd_init_t
  • val : qspi_stig_cmd_t
  • validcnt : qspi_auto_poll_t
  • vdd_level : acmp_init_t


ALD User Manual: Data Fields - Variables

- w -

  • wait : ald_ebi_nand_init_t , ald_ebi_nor_sram_init_t
  • wait_time : ald_ebi_nand_timing_t
  • warm_time : acmp_init_t
  • wdg_cbk : adc_handle_s
  • week : rtc_alarm_t , rtc_date_t
  • width : ald_ebi_nand_init_t , ald_ebi_nor_sram_init_t
  • word : dma_ctrl_t
  • word_length : uart_init_t
  • wr_buf : qspi_stig_cmd_t
  • wr_len : qspi_stig_cmd_t
  • wrap_mode : ald_ebi_nor_sram_init_t
  • wrcde : qspi_write_cfg_t
  • wrinit : qspi_dac_cfg_t
  • write : ald_ebi_nor_sram_init_t
  • wrlen : qspi_indac_wr_cfg_t
  • wrppin : qspi_init_t
  • wrwmark : qspi_indac_cfg_t


ALD User Manual: Data Fields - Variables

- x -

  • xfer_count : i2c_handle_s
  • xfer_size : i2c_handle_s
  • xipimmed : qspi_dac_cfg_t
  • xipnextrd : qspi_dac_cfg_t


ALD User Manual: Data Fields - Variables

- y -

  • year : rtc_date_t


ALD User Manual: File List

File List
Here is a list of all files with brief descriptions:
[detail level 1234]
▼ D: |
▼ svn |
▼ src |
ald_acmp.c | ACMP module driver
ald_acmp.h | Header file of ACMP module driver
ald_adc.c | This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral:
ald_adc.h | Header file of ADC Module library
ald_bkpc.c | BKPC module driver
ald_bkpc.h | Header file of BKPC module driver
ald_calc.c | CALC module driver
ald_calc.h | Header file of CALC module driver
ald_can.c | CAN module driver. This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral:
ald_can.h | Header file of CAN Module driver
ald_cmu.c | CMU module driver
ald_cmu.h | Header file of CMU module driver
ald_conf.h | Enable/Disable the peripheral module
ald_crc.c | CRC module driver
ald_crc.h | Header file of CRC module driver
ald_crypt.c | CRYPT module driver. This is the common part of the CRYPT initialization
ald_crypt.h | Header file of CRYPT module driver
ald_dac.c | DAC module driver
ald_dac.h | Header file of DAC Module library
ald_dbgc.h | DEBUGCON module driver
ald_dma.c | DMA module driver
ald_dma.h | DMA module Library
ald_ebi.c | EBI module driver
ald_ebi.h | Header file of EBI module driver
ald_flash.c | FLASH module driver
ald_flash.h | Header file of FLASH driver
ald_flash_ext.c | FLASH extra module driver
ald_gpio.c | GPIO module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral:
ald_gpio.h | Header file of GPIO module driver
ald_i2c.c | I2C module driver
ald_i2c.h | Header file of I2C driver
ald_i2s.c | I2S module driver. This file provides firmware functions to manage the following functionalities of I2S peripheral:
ald_i2s.h |
ald_iap.c | IAP module driver
ald_iap.h | Header file of IAP module driver
ald_nand.c | NAND module driver
ald_nand.h | Header file of EBI_NAND module driver
ald_nor_lcd.c | EBI_NOR_LCD module driver
ald_nor_lcd.h | Header file of EBI_NOR_LCD module driver
ald_pis.c | PIS module driver
ald_pis.h | Header file of PIS driver
ald_pmu.c | PMU module driver
ald_pmu.h | Header file of PMU module driver
ald_qspi.c | QSPI module driver
ald_qspi.h | Header file of QSPI module driver
ald_rmu.c | RMU module driver
ald_rmu.h | Header file of RMU module driver
ald_rtc.c | RTC module driver. This file provides firmware functions to manage the following functionalities of the RTC peripheral:
ald_rtc.h | Header file of RTC Module driver
ald_rtchw.c | RTCHW module driver. This file provides firmware functions to manage the following functionalities of the RTC peripheral:
ald_rtchw.h | Header file of RTCHW Module driver
ald_spi.c | SPI module driver. This file provides firmware functions to manage the following functionalities of SPI peripheral:
ald_spi.h |
ald_sram.c | SRAM module driver
ald_sram.h | Header file of EBI_SRAM driver
ald_syscfg.h | SYSCFG module driver
ald_timer.c | TIMER module driver. This is the common part of the TIMER initialization
ald_timer.h | TIMER module driver. This is the common part of the TIMER initialization
ald_trng.c | TRNG module driver
ald_trng.h | Header file of TRNG module driver
ald_tsense.c | TSENSE module driver
ald_tsense.h | Header file of TSENSE module driver
ald_uart.c | UART module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
ald_uart.h | Header file of UART module library
ald_usb.c | USB module driver
ald_usb.h | Header file of USB module driver
ald_wdt.c | WDT module driver
ald_wdt.h | Header file of WDT module driver
type.h | Define type
utils.c | This file contains the Utilities functions/types for the driver
utils.h | This file contains the Utilities functions/types for the driver


ALD User Manual: D: Directory Reference

  • D:
D: Directory Reference

Directories

directory svn


ALD User Manual: D:/svn Directory Reference

  • D:
  • svn
svn Directory Reference

Directories

directory src


ALD User Manual: D:/svn/src Directory Reference

  • D:
  • svn
  • src
src Directory Reference

Files

file | ald_acmp.c [code]
ACMP module driver.
file | ald_acmp.h [code]
Header file of ACMP module driver.
file | ald_adc.c [code]
This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral:
file | ald_adc.h [code]
Header file of ADC Module library.
file | ald_bkpc.c [code]
BKPC module driver.
file | ald_bkpc.h [code]
Header file of BKPC module driver.
file | ald_calc.c [code]
CALC module driver.
file | ald_calc.h [code]
Header file of CALC module driver.
file | ald_can.c [code]
CAN module driver. This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral:
file | ald_can.h [code]
Header file of CAN Module driver.
file | ald_cmu.c [code]
CMU module driver.
file | ald_cmu.h [code]
Header file of CMU module driver.
file | ald_conf.h [code]
Enable/Disable the peripheral module.
file | ald_crc.c [code]
CRC module driver.
file | ald_crc.h [code]
Header file of CRC module driver.
file | ald_crypt.c [code]
CRYPT module driver. This is the common part of the CRYPT initialization.
file | ald_crypt.h [code]
Header file of CRYPT module driver.
file | ald_dac.c [code]
DAC module driver.
file | ald_dac.h [code]
Header file of DAC Module library.
file | ald_dbgc.h [code]
DEBUGCON module driver.
file | ald_dma.c [code]
DMA module driver.
file | ald_dma.h [code]
DMA module Library.
file | ald_ebi.c [code]
EBI module driver.
file | ald_ebi.h [code]
Header file of EBI module driver.
file | ald_flash.c [code]
FLASH module driver.
file | ald_flash.h [code]
Header file of FLASH driver.
file | ald_flash_ext.c [code]
FLASH extra module driver.
file | ald_gpio.c [code]
GPIO module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral:
file | ald_gpio.h [code]
Header file of GPIO module driver.
file | ald_i2c.c [code]
I2C module driver.
file | ald_i2c.h [code]
Header file of I2C driver.
file | ald_i2s.c [code]
I2S module driver. This file provides firmware functions to manage the following functionalities of I2S peripheral:
file | ald_i2s.h [code]
file | ald_iap.c [code]
IAP module driver.
file | ald_iap.h [code]
Header file of IAP module driver.
file | ald_nand.c [code]
NAND module driver.
file | ald_nand.h [code]
Header file of EBI_NAND module driver.
file | ald_nor_lcd.c [code]
EBI_NOR_LCD module driver.
file | ald_nor_lcd.h [code]
Header file of EBI_NOR_LCD module driver.
file | ald_pis.c [code]
PIS module driver.
file | ald_pis.h [code]
Header file of PIS driver.
file | ald_pmu.c [code]
PMU module driver.
file | ald_pmu.h [code]
Header file of PMU module driver.
file | ald_qspi.c [code]
QSPI module driver.
file | ald_qspi.h [code]
Header file of QSPI module driver.
file | ald_rmu.c [code]
RMU module driver.
file | ald_rmu.h [code]
Header file of RMU module driver.
file | ald_rtc.c [code]
RTC module driver. This file provides firmware functions to manage the following functionalities of the RTC peripheral:
file | ald_rtc.h [code]
Header file of RTC Module driver.
file | ald_rtchw.c [code]
RTCHW module driver. This file provides firmware functions to manage the following functionalities of the RTC peripheral:
file | ald_rtchw.h [code]
Header file of RTCHW Module driver.
file | ald_spi.c [code]
SPI module driver. This file provides firmware functions to manage the following functionalities of SPI peripheral:
file | ald_spi.h [code]
file | ald_sram.c [code]
SRAM module driver.
file | ald_sram.h [code]
Header file of EBI_SRAM driver.
file | ald_syscfg.h [code]
SYSCFG module driver.
file | ald_timer.c [code]
TIMER module driver. This is the common part of the TIMER initialization.
file | ald_timer.h [code]
TIMER module driver. This is the common part of the TIMER initialization.
file | ald_trng.c [code]
TRNG module driver.
file | ald_trng.h [code]
Header file of TRNG module driver.
file | ald_tsense.c [code]
TSENSE module driver.
file | ald_tsense.h [code]
Header file of TSENSE module driver.
file | ald_uart.c [code]
UART module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
file | ald_uart.h [code]
Header file of UART module library.
file | ald_usb.c [code]
USB module driver.
file | ald_usb.h [code]
Header file of USB module driver.
file | ald_wdt.c [code]
WDT module driver.
file | ald_wdt.h [code]
Header file of WDT module driver.
file | type.h [code]
define type
file | utils.c [code]
This file contains the Utilities functions/types for the driver.
file | utils.h [code]
This file contains the Utilities functions/types for the driver.


ALD User Manual: D:/svn/src/ald_acmp.c File Reference

  • D:
  • svn
  • src
Functions
ald_acmp.c File Reference

ACMP module driver. More...

#include "ald_acmp.h"
Include dependency graph for ald_acmp.c:

Go to the source code of this file.

Functions

ald_status_t | ald_acmp_init (acmp_handle_t *hperh)
Initializes the ACMP mode according to the specified parameters in the acmp_init_t and create the associated handle. More...
void | ald_acmp_interrupt_config (acmp_handle_t *hperh, acmp_it_t it, type_func_t state)
Enables or disables the specified ACMP interrupts. More...
it_status_t | ald_acmp_get_it_status (acmp_handle_t *hperh, acmp_it_t it)
Checks whether the specified ACMP interrupt has set or not. More...
flag_status_t | ald_acmp_get_flag_status (acmp_handle_t *hperh, acmp_flag_t flag)
Checks whether the specified ACMP interrupt has occurred or not. More...
flag_status_t | ald_acmp_get_mask_flag_status (acmp_handle_t *hperh, acmp_flag_t flag)
Get the status of interrupt flag and interupt source. More...
void | ald_acmp_clear_flag_status (acmp_handle_t *hperh, acmp_flag_t flag)
Clear the specified ACMP it flags. More...
void | ald_acmp_irq_handler (acmp_handle_t *hperh)
This function handles ACMP interrupt request. More...
void | ald_acmp_out_config (acmp_handle_t *hperh, type_func_t state)
This function config acmp output. More...
uint8_t | ald_acmp_out_result (acmp_handle_t *hperh)
This function output acmp result. More...
flag_status_t | ald_acmp_get_status (acmp_handle_t *hperh, acmp_status_t status)
Check whether the specified ACMP flag is set or not. More...

Detailed Description

ACMP module driver.

Version
V1.0
Date
26 Jun 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_acmp.c.


ALD User Manual: D:/svn/src/ald_acmp.h File Reference

  • D:
  • svn
  • src
Data Structures | Macros | Typedefs | Enumerations | Functions
ald_acmp.h File Reference

Header file of ACMP module driver. More...

#include "utils.h"
Include dependency graph for ald_acmp.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Data Structures

struct | acmp_init_t
ACMP init structure definition. More...
struct | acmp_handle_s
ACMP Handle Structure definition. More...

Macros

#define | ACMP_ENABLE(handle) (SET_BIT((handle)->perh->CON, ACMP_CON_EN_MSK))
#define | ACMP_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, ACMP_CON_EN_MSK))
#define | IS_ACMP_TYPE(x)
#define | IS_ACMP_MODE_TYPE(x)
#define | IS_ACMP_IT_TYPE(x)
#define | IS_ACMP_FLAG_TYPE(x)
#define | IS_ACMP_STATUS_TYPE(x)
#define | IS_ACMP_POS_INPUT_TYPE(x)
#define | IS_ACMP_NEG_INPUT_TYPE(x)
#define | IS_ACMP_WARM_UP_TIME_TYPE(x)
#define | IS_ACMP_HYSTSEL_TYPE(x)
#define | IS_ACMP_INACTVAL_TYPE(x)
#define | IS_ACMP_EDGE_TYPE(x)

Typedefs

typedef struct acmp_handle_s acmp_handle_t
ACMP Handle Structure definition. More...

Enumerations

enum | acmp_it_t { ACMP_IT_EDGE = (1U << 0), ACMP_IT_WARMUP = (1U << 1) }
ACMP interrupt. More...
enum | acmp_flag_t { ACMP_FLAG_EDGE = (1U << 0), ACMP_FLAG_WARMUP = (1U << 1) }
ACMP interrupt flag. More...
enum | acmp_status_t { ACMP_STATUS_ACT = (1U << 0), ACMP_STATUS_OUT = (1U << 1) }
ACMP status flag. More...
enum acmp_pos_input_t {
ACMP_POS_CH0 = 0x0U, ACMP_POS_CH1 = 0x1U, ACMP_POS_CH2 = 0x2U, ACMP_POS_CH3 = 0x3U,
ACMP_POS_CH4 = 0x4U, ACMP_POS_CH5 = 0x5U, ACMP_POS_CH6 = 0x6U, ACMP_POS_CH7 = 0x7U
}
ACMP positive input. More...
enum acmp_neg_input_t {
ACMP_NEG_CH0 = 0x0U, ACMP_NEG_CH1 = 0x1U, ACMP_NEG_CH2 = 0x2U, ACMP_NEG_CH3 = 0x3U,
ACMP_NEG_CH4 = 0x4U, ACMP_NEG_CH5 = 0x5U, ACMP_NEG_CH6 = 0x6U, ACMP_NEG_CH7 = 0x7U,
ACMP_NEG_1V25 = 0x8U, ACMP_NEG_2V5 = 0x9U, ACMP_NEG_VDD = 0xAU
}
ACMP negative input. More...
enum | acmp_mode_t { ACMP_ULTRA_LOW_POWER = 0x0U, ACMP_LOW_POWER = 0x1U, ACMP_MIDDLE_POWER = 0x2U, ACMP_HIGH_POWER = 0x3U }
ACMP mode. More...
enum acmp_warm_time_t {
ACMP_4_PCLK = 0x0U, ACMP_8_PCLK = 0x1U, ACMP_16_PCLK = 0x2U, ACMP_32_PCLK = 0x3U,
ACMP_64_PCLK = 0x4U, ACMP_128_PCLK = 0x5U, ACMP_256_PCLK = 0x6U, ACMP_512_PCLK = 0x7U
}
ACMP warm-up time. More...
enum acmp_hystsel_t {
ACMP_HYST_0 = 0x0U, ACMP_HYST_15 = 0x1U, ACMP_HYST_22 = 0x2U, ACMP_HYST_29 = 0x3U,
ACMP_HYST_36 = 0x4U, ACMP_HYST_43 = 0x5U, ACMP_HYST_50 = 0x6U, ACMP_HYST_57 = 0x7U
}
ACMP hysteresis level. More...
enum | acmp_inactval_t { ACMP_INACTVAL_LOW = 0x0U, ACMP_INACTVAL_HIGH = 0x1U }
ACMP inactive state. More...
enum | acmp_edge_t { ACMP_EDGE_NONE = 0x0U, ACMP_EDGE_FALL = 0x1U, ACMP_EDGE_RISE = 0x2U, ACMP_EDGE_ALL = 0x3U }
which edges set up interrupt More...
enum | acmp_out_func_t { ACMP_OUT_DISABLE = 0x0U, ACMP_OUT_ENABLE = 0x1U }
ACMP output function. More...

Functions

ald_status_t | ald_acmp_init (acmp_handle_t *hperh)
Initializes the ACMP mode according to the specified parameters in the acmp_init_t and create the associated handle. More...
void | ald_acmp_interrupt_config (acmp_handle_t *hperh, acmp_it_t it, type_func_t state)
Enables or disables the specified ACMP interrupts. More...
it_status_t | ald_acmp_get_it_status (acmp_handle_t *hperh, acmp_it_t it)
Checks whether the specified ACMP interrupt has set or not. More...
flag_status_t | ald_acmp_get_flag_status (acmp_handle_t *hperh, acmp_flag_t flag)
Checks whether the specified ACMP interrupt has occurred or not. More...
flag_status_t | ald_acmp_get_mask_flag_status (acmp_handle_t *hperh, acmp_flag_t flag)
Get the status of interrupt flag and interupt source. More...
void | ald_acmp_clear_flag_status (acmp_handle_t *hperh, acmp_flag_t flag)
Clear the specified ACMP it flags. More...
void | ald_acmp_irq_handler (acmp_handle_t *hperh)
This function handles ACMP interrupt request. More...
void | ald_acmp_out_config (acmp_handle_t *hperh, type_func_t state)
This function config acmp output. More...
uint8_t | ald_acmp_out_result (acmp_handle_t *hperh)
This function output acmp result. More...
flag_status_t | ald_acmp_get_status (acmp_handle_t *hperh, acmp_status_t status)
Check whether the specified ACMP flag is set or not. More...

Detailed Description

Header file of ACMP module driver.

Version
V1.0
Date
26 Jun 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_acmp.h.


ALD User Manual: D:/svn/src/ald_adc.c File Reference

  • D:
  • svn
  • src
Functions
ald_adc.c File Reference

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral: More...

#include "ald_cmu.h"
#include "ald_adc.h"
Include dependency graph for ald_adc.c:

Go to the source code of this file.

Functions

static void | adc_dma_normal_conv_cplt (void *arg)
DMA transfer complete callback. More...
static void | adc_dma_error (void *arg)
DMA error callback. More...
ald_status_t | ald_adc_init (adc_handle_t *hperh)
Initializes the ADC peripheral and normal group according to parameters specified in structure "adc_handle_t". More...
ald_status_t | ald_adc_reset (adc_handle_t *hperh)
Deinitialize the ADC peripheral registers to their default reset values. More...
ald_status_t | ald_adc_normal_start (adc_handle_t *hperh)
Enables ADC, starts conversion of normal group. More...
ald_status_t | ald_adc_normal_stop (adc_handle_t *hperh)
Stop ADC conversion of normal group (and insert channels in case of auto_injection mode), disable ADC peripheral. More...
ald_status_t | ald_adc_normal_poll_for_conversion (adc_handle_t *hperh, uint32_t timeout)
Wait for normal group conversion to be completed. More...
ald_status_t | ald_adc_poll_for_event (adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout)
Poll for conversion event. More...
ald_status_t | ald_adc_normal_start_by_it (adc_handle_t *hperh)
Enables ADC, starts conversion of normal group with interruption. Interruptions enabled in this function: More...
ald_status_t | ald_adc_normal_stop_by_it (adc_handle_t *hperh)
Stop ADC conversion of normal group (and insert group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral. More...
ald_status_t | ald_adc_start_by_dma (adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel)
Enables ADC, starts conversion of normal group and transfers result through DMA. More...
ald_status_t | ald_adc_stop_by_dma (adc_handle_t *hperh, uint8_t channel)
Stop ADC conversion of normal group (and insert group in case of auto_insert mode), disable ADC DMA transfer, disable ADC peripheral. More...
static void | adc_dma_timer_trigger_cplt (void *arg)
DMA transfer complete callback. More...
ald_status_t | ald_adc_timer_trigger_adc_by_dma (adc_timer_config_t *config)
Config Timer trigger adc function. More...
uint32_t | ald_adc_normal_get_value (adc_handle_t *hperh)
Get ADC normal group conversion result. More...
ald_status_t | ald_adc_insert_start (adc_handle_t *hperh)
Enables ADC, starts conversion of insert group. Interruptions enabled in this function: None. More...
ald_status_t | ald_adc_insert_stop (adc_handle_t *hperh)
Stop conversion of insert channels. Disable ADC peripheral if no normal conversion is on going. More...
ald_status_t | ald_adc_insert_poll_for_conversion (adc_handle_t *hperh, uint32_t timeout)
Wait for insert group conversion to be completed. More...
ald_status_t | ald_adc_insert_start_by_it (adc_handle_t *hperh)
Enables ADC, starts conversion of insert group with interruption. More...
ald_status_t | ald_adc_insert_stop_by_it (adc_handle_t *hperh)
Stop conversion of insert channels, disable interruption of end-of-conversion. Disable ADC peripheral if no normal conversion is on going. More...
uint32_t | ald_adc_insert_get_value (adc_handle_t *hperh, adc_ich_idx_t idx)
Get ADC insert group conversion result. More...
void | ald_adc_irq_handler (adc_handle_t *hperh)
Handles ADC interrupt request. More...
ald_status_t | ald_adc_normal_channel_config (adc_handle_t *hperh, adc_nch_conf_t *config)
Configures the the selected channel to be linked to the normal group. More...
ald_status_t | ald_adc_insert_channel_config (adc_handle_t *hperh, adc_ich_conf_t *config)
Configures the the selected channel to be linked to the insert group. More...
ald_status_t | ald_adc_analog_wdg_config (adc_handle_t *hperh, adc_analog_wdg_conf_t *config)
Configures the analog watchdog. More...
void | ald_adc_interrupt_config (adc_handle_t *hperh, adc_it_t it, type_func_t state)
Enables or disables the specified ADC interrupts. More...
it_status_t | ald_adc_get_it_status (adc_handle_t *hperh, adc_it_t it)
Checks whether the specified ADC interrupt has occurred or not. More...
flag_status_t | ald_adc_get_flag_status (adc_handle_t *hperh, adc_flag_t flag)
Check whether the specified ADC flag is set or not. More...
void | ald_adc_clear_flag_status (adc_handle_t *hperh, adc_flag_t flag)
Clear the specified ADC pending flags. More...
uint32_t | ald_adc_get_state (adc_handle_t *hperh)
return the ADC state More...
uint32_t | ald_adc_get_error (adc_handle_t *hperh)
Return the ADC error code. More...

Detailed Description

This file provides firmware functions to manage the following functionalities of the Analog to Digital Convertor (ADC) peripheral:

  • Initialization functions ++ Initialization and Configuration of ADC
  • Operation functions ++ Start, stop, get result of conversions of normal group, using 3 possible modes: polling, interruption or DMA.
  • Control functions ++ Channels configuration on normal group ++ Channels configuration on insert group ++ Analog Watchdog configuration
  • State functions ++ ADC state machine management ++ Interrupts and flags management
Version
V1.0
Date
28 Jun 2019
Author
AE Team.
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_adc.c.


ALD User Manual: D:/svn/src/ald_adc.h File Reference

  • D:
  • svn
  • src
Data Structures | Macros | Typedefs | Enumerations | Functions
ald_adc.h File Reference

Header file of ADC Module library. More...

#include "utils.h"
#include "ald_dma.h"
#include "ald_pis.h"
#include "ald_timer.h"
Include dependency graph for ald_adc.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Data Structures

struct | adc_init_t
ADC trigger conversion mode. More...
struct | adc_nch_conf_t
Structure definition of ADC channel for normal group. More...
struct | adc_analog_wdg_conf_t
ADC Configuration analog watchdog definition. More...
struct | adc_ich_conf_t
ADC Configuration insert Channel structure definition. More...
struct | adc_handle_s
ADC handle Structure definition. More...
struct | adc_timer_config_t
Timer trigger adc config structure definition. More...

Macros

#define | ADC_ENABLE(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK))
#define | ADC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK))
#define | ADC_NH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK))
#define | ADC_IH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK))
#define | ADC_RESET_HANDLE_STATE(handle) ((handle)->state = ADC_STATE_RESET)
#define | ADC_VREF_OUT_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK))
#define | ADC_VREF_OUT_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK))
#define | ADC_NETS_ENABLE(handle, mode) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, (mode) << ADC_CON1_NETS_POSS))
#define | ADC_IETS_ENABLE(handle, mode) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, (mode) << ADC_CON1_IETS_POSS))
#define | ADC_NETS_DISABLE(handle) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, 0 << ADC_CON1_NETS_POSS))
#define | ADC_IETS_DISABLE(handle) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, 0 << ADC_CON1_IETS_POSS))
#define | ADC_SPEED_HIGH_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK))
#define | ADC_SPEED_HIGH_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK))
#define | ADC_CALIBRATE_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK))
#define | ADC_CALIBRATE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK))
#define | IS_ADC_ICH_IDX_TYPE(x) ((x) <= ADC_ICH_IDX_4)
#define | IS_ADC_NCH_IDX_TYPE(x) ((x) <= ADC_NCH_IDX_16)
#define | IS_ADC_SAMPLING_TIMES_TYPE(x)
#define | IS_ADC_CHANNELS_TYPE(x) ((x) <= ADC_CHANNEL_18)
#define | IS_ADC_DATA_ALIGN_TYPE(x)
#define | IS_ADC_ANALOG_WTD_MODE_TYPE(x)
#define | IS_ADC_IT_TYPE(x)
#define | IS_ADC_FLAGS_TYPE(x)
#define | IS_ADC_CLK_DIV_TYPE(x)
#define | IS_ADC_NEG_REF_VOLTAGE_TYPE(x)
#define | IS_POS_REF_VOLTAGE_TYPE(x)
#define | IS_ADC_NCH_NR_TYPE(x) ((x) <= ADC_NCH_NR_16)
#define | IS_ADC_ICH_NR_TYPE(x) ((x) <= ADC_ICH_NR_4)
#define | IS_ADC_DISC_NR_TYPE(x) ((x) <= ADC_DISC_NR_8)
#define | IS_ADC_CONV_BIT_TYPE(x)
#define | IS_ADC_TYPE(x)
#define | IS_ADC_NCHESEL_MODE_TYPE(x)
#define | IS_ADC_EVENT_TYPE(x) ((x) == ADC_AWD_EVENT)
#define | IS_ADC_IST_OFFSET_TYPE(x) ((x) <= 0xfff)
#define | IS_HTR_TYPE(x) ((x) <= 0xfff)
#define | IS_LTR_TYPE(x) ((x) <= 0xfff)

Typedefs

typedef struct adc_handle_s adc_handle_t
ADC handle Structure definition. More...

Enumerations

enum adc_state_t {
ADC_STATE_RESET = 0x0U, ADC_STATE_READY = 0x1U, ADC_STATE_BUSY = 0x2U, ADC_STATE_TIMEOUT = 0x4U,
ADC_STATE_ERROR = 0x8U, ADC_STATE_BUSY_N = 0x10U, ADC_STATE_BUSY_I = 0x20U, ADC_STATE_BUSY_WDG = 0x40U
}
ADC State structures definition. More...
enum | adc_error_t { ADC_ERROR_NONE = 0x0U, ADC_ERROR_INTERNAL = 0x1U, ADC_ERROR_OVR = 0x2U, ADC_ERROR_DMA = 0x4U }
ADC Error Code. More...
enum | adc_align_t { ADC_DATAALIGN_RIGHT = 0x0U, ADC_DATAALIGN_LEFT = 0x1U }
ADC data alignment. More...
enum | adc_nchesel_t { ADC_NCHESEL_MODE_ALL = 0x0U, ADC_NCHESEL_MODE_ONE = 0x1U }
ADC config hannal trigger the EOC IT mode. More...
enum adc_channel_t {
ADC_CHANNEL_0 = 0x0U, ADC_CHANNEL_1 = 0x1U, ADC_CHANNEL_2 = 0x2U, ADC_CHANNEL_3 = 0x3U,
ADC_CHANNEL_4 = 0x4U, ADC_CHANNEL_5 = 0x5U, ADC_CHANNEL_6 = 0x6U, ADC_CHANNEL_7 = 0x7U,
ADC_CHANNEL_8 = 0x8U, ADC_CHANNEL_9 = 0x9U, ADC_CHANNEL_10 = 0xAU, ADC_CHANNEL_11 = 0xBU,
ADC_CHANNEL_12 = 0xCU, ADC_CHANNEL_13 = 0xDU, ADC_CHANNEL_14 = 0xEU, ADC_CHANNEL_15 = 0xFU,
ADC_CHANNEL_16 = 0x10U, ADC_CHANNEL_17 = 0x11U, ADC_CHANNEL_18 = 0x12U
}
ADC channels. More...
enum | adc_samp_t { ADC_SAMPLETIME_1 = 0x0U, ADC_SAMPLETIME_2 = 0x1U, ADC_SAMPLETIME_4 = 0x2U, ADC_SAMPLETIME_15 = 0x3U }
ADC sampling times. More...
enum adc_nch_idx_t {
ADC_NCH_IDX_1 = 0x1U, ADC_NCH_IDX_2 = 0x2U, ADC_NCH_IDX_3 = 0x3U, ADC_NCH_IDX_4 = 0x4U,
ADC_NCH_IDX_5 = 0x5U, ADC_NCH_IDX_6 = 0x6U, ADC_NCH_IDX_7 = 0x7U, ADC_NCH_IDX_8 = 0x8U,
ADC_NCH_IDX_9 = 0x9U, ADC_NCH_IDX_10 = 0xAU, ADC_NCH_IDX_11 = 0xBU, ADC_NCH_IDX_12 = 0xCU,
ADC_NCH_IDX_13 = 0xDU, ADC_NCH_IDX_14 = 0xEU, ADC_NCH_IDX_15 = 0xFU, ADC_NCH_IDX_16 = 0x10U
}
ADC index channel in normal group. More...
enum | adc_ich_idx_t { ADC_ICH_IDX_1 = 0x1U, ADC_ICH_IDX_2 = 0x2U, ADC_ICH_IDX_3 = 0x3U, ADC_ICH_IDX_4 = 0x4U }
ADC index channel in insert group. More...
enum adc_ana_wdg_t {
ADC_ANAWTD_NONE = 0x0U, ADC_ANAWTD_SING_NM = 0x800200U, ADC_ANAWTD_SING_IST = 0x400200U, ADC_ANAWTD_SING_NMIST = 0xC00200U,
ADC_ANAWTD_ALL_NM = 0x800000U, ADC_ANAWTD_ALL_IST = 0x400000U, ADC_ANAWTD_ALL_NMIST = 0xC00000U
}
ADC analog watchdog mode. More...
enum | adc_event_type_t { ADC_AWD_EVENT = (1U << 0) }
ADC Event type. More...
enum | adc_it_t { ADC_IT_NCH = (1U << 5), ADC_IT_AWD = (1U << 6), ADC_IT_ICH = (1U << 7), ADC_IT_OVR = (1U << 26) }
ADC interrupts definition. More...
enum adc_flag_t {
ADC_FLAG_AWD = (1U << 0), ADC_FLAG_NCH = (1U << 1), ADC_FLAG_ICH = (1U << 2), ADC_FLAG_OVR = (1U << 3),
ADC_FLAG_NCHS = (1U << 8), ADC_FLAG_ICHS = (1U << 9)
}
ADC flags definition. More...
enum adc_clk_div_t {
ADC_CKDIV_1 = 0x0U, ADC_CKDIV_2 = 0x1U, ADC_CKDIV_4 = 0x2U, ADC_CKDIV_8 = 0x3U,
ADC_CKDIV_16 = 0x4U, ADC_CKDIV_32 = 0x5U, ADC_CKDIV_64 = 0x6U, ADC_CKDIV_128 = 0x7U
}
ADC CLD DIV definition. More...
enum | adc_neg_ref_t { ADC_NEG_REF_VSS = 0x0U, ADC_NEG_REF_VREFN = 0x1U }
ADC negative reference voltage definition. More...
enum | adc_pos_ref_t { ADC_POS_REF_VDD = 0x0U, ADC_POS_REF_2V = 0x1U, ADC_POS_REF_VREEFP = 0x2U, ADC_POS_REF_VREEFP_BUF = 0x3U }
ADC positive reference voltage definition. More...
enum adc_nch_nr_t {
ADC_NCH_NR_1 = 0x0U, ADC_NCH_NR_2 = 0x1U, ADC_NCH_NR_3 = 0x2U, ADC_NCH_NR_4 = 0x3U,
ADC_NCH_NR_5 = 0x4U, ADC_NCH_NR_6 = 0x5U, ADC_NCH_NR_7 = 0x6U, ADC_NCH_NR_8 = 0x7U,
ADC_NCH_NR_9 = 0x8U, ADC_NCH_NR_10 = 0x9U, ADC_NCH_NR_11 = 0xAU, ADC_NCH_NR_12 = 0xBU,
ADC_NCH_NR_13 = 0xCU, ADC_NCH_NR_14 = 0xDU, ADC_NCH_NR_15 = 0xEU, ADC_NCH_NR_16 = 0xFU
}
ADC numbers of normal conversion channals. More...
enum | adc_ich_nr_t { ADC_ICH_NR_1 = 0x0U, ADC_ICH_NR_2 = 0x1U, ADC_ICH_NR_3 = 0x2U, ADC_ICH_NR_4 = 0x3U }
ADC numbers of insert conversion channals. More...
enum | adc_disc_mode_t { ADC_ALL_DISABLE = 0x0U, ADC_NCH_DISC_EN = 0x1U, ADC_ICH_DISC_EN = 0x2U }
ADC discontinuous mode choose. More...
enum adc_disc_nr_t {
ADC_DISC_NR_1 = 0x0U, ADC_DISC_NR_2 = 0x1U, ADC_DISC_NR_3 = 0x2U, ADC_DISC_NR_4 = 0x3U,
ADC_DISC_NR_5 = 0x4U, ADC_DISC_NR_6 = 0x5U, ADC_DISC_NR_7 = 0x6U, ADC_DISC_NR_8 = 0x7U
}
ADC numbers of channals in discontinuous conversion mode. More...
enum | adc_conv_bit_t { ADC_CONV_BIT_6 = 0x0U, ADC_CONV_BIT_8 = 0x1U, ADC_CONV_BIT_10 = 0x2U, ADC_CONV_BIT_12 = 0x3U }
ADC resolution of conversion. More...
enum | adc_ets_t { ADC_ETS_DISABLE = 0x0U, ADC_ETS_RISE = 0x1U, ADC_ETS_FALL = 0x2U, ADC_ETS_RISE_FALL = 0x3U }
ADC external trigger mode choose. More...

Functions

ald_status_t | ald_adc_init (adc_handle_t *hperh)
Initializes the ADC peripheral and normal group according to parameters specified in structure "adc_handle_t". More...
ald_status_t | ald_adc_reset (adc_handle_t *hperh)
Deinitialize the ADC peripheral registers to their default reset values. More...
ald_status_t | ald_adc_normal_start (adc_handle_t *hperh)
Enables ADC, starts conversion of normal group. More...
ald_status_t | ald_adc_normal_stop (adc_handle_t *hperh)
Stop ADC conversion of normal group (and insert channels in case of auto_injection mode), disable ADC peripheral. More...
ald_status_t | ald_adc_normal_poll_for_conversion (adc_handle_t *hperh, uint32_t timeout)
Wait for normal group conversion to be completed. More...
ald_status_t | ald_adc_poll_for_event (adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout)
Poll for conversion event. More...
ald_status_t | ald_adc_normal_start_by_it (adc_handle_t *hperh)
Enables ADC, starts conversion of normal group with interruption. Interruptions enabled in this function: More...
ald_status_t | ald_adc_normal_stop_by_it (adc_handle_t *hperh)
Stop ADC conversion of normal group (and insert group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral. More...
ald_status_t | ald_adc_start_by_dma (adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel)
Enables ADC, starts conversion of normal group and transfers result through DMA. More...
ald_status_t | ald_adc_stop_by_dma (adc_handle_t *hperh, uint8_t channel)
Stop ADC conversion of normal group (and insert group in case of auto_insert mode), disable ADC DMA transfer, disable ADC peripheral. More...
ald_status_t | ald_adc_timer_trigger_adc_by_dma (adc_timer_config_t *config)
Config Timer trigger adc function. More...
uint32_t | ald_adc_normal_get_value (adc_handle_t *hperh)
Get ADC normal group conversion result. More...
ald_status_t | ald_adc_insert_start (adc_handle_t *hperh)
Enables ADC, starts conversion of insert group. Interruptions enabled in this function: None. More...
ald_status_t | ald_adc_insert_stop (adc_handle_t *hperh)
Stop conversion of insert channels. Disable ADC peripheral if no normal conversion is on going. More...
ald_status_t | ald_adc_insert_poll_for_conversion (adc_handle_t *hperh, uint32_t timeout)
Wait for insert group conversion to be completed. More...
ald_status_t | ald_adc_insert_start_by_it (adc_handle_t *hperh)
Enables ADC, starts conversion of insert group with interruption. More...
ald_status_t | ald_adc_insert_stop_by_it (adc_handle_t *hperh)
Stop conversion of insert channels, disable interruption of end-of-conversion. Disable ADC peripheral if no normal conversion is on going. More...
uint32_t | ald_adc_insert_get_value (adc_handle_t *hperh, adc_ich_idx_t idx)
Get ADC insert group conversion result. More...
void | ald_adc_irq_handler (adc_handle_t *hperh)
Handles ADC interrupt request. More...
ald_status_t | ald_adc_normal_channel_config (adc_handle_t *hperh, adc_nch_conf_t *config)
Configures the the selected channel to be linked to the normal group. More...
ald_status_t | ald_adc_insert_channel_config (adc_handle_t *hperh, adc_ich_conf_t *config)
Configures the the selected channel to be linked to the insert group. More...
ald_status_t | ald_adc_analog_wdg_config (adc_handle_t *hperh, adc_analog_wdg_conf_t *config)
Configures the analog watchdog. More...
void | ald_adc_interrupt_config (adc_handle_t *hperh, adc_it_t it, type_func_t state)
Enables or disables the specified ADC interrupts. More...
it_status_t | ald_adc_get_it_status (adc_handle_t *hperh, adc_it_t it)
Checks whether the specified ADC interrupt has occurred or not. More...
flag_status_t | ald_adc_get_flag_status (adc_handle_t *hperh, adc_flag_t flag)
Check whether the specified ADC flag is set or not. More...
void | ald_adc_clear_flag_status (adc_handle_t *hperh, adc_flag_t flag)
Clear the specified ADC pending flags. More...
uint32_t | ald_adc_get_state (adc_handle_t *hperh)
return the ADC state More...
uint32_t | ald_adc_get_error (adc_handle_t *hperh)
Return the ADC error code. More...

Detailed Description

Header file of ADC Module library.

Version
V1.0
Date
28 Jun 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_adc.h.


ALD User Manual: D:/svn/src/ald_bkpc.c File Reference

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  • svn
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Functions
ald_bkpc.c File Reference

BKPC module driver. More...

#include "ald_bkpc.h"
#include "ald_rtc.h"
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Functions

void | ald_bkpc_standby_wakeup_config (bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
Configure standby wakeup in backup field. More...
void | ald_bkpc_rtc_clock_config (bkpc_preh_clk_t clock)
Configure rtc clock in backup field. More...
void | ald_bkpc_tsense_clock_config (bkpc_preh_clk_t clock)
Configure tsense clock in backup field. More...
void | ald_bkpc_write_ram (uint8_t idx, uint32_t value)
Write data into backup ram. More...
uint32_t | ald_bkpc_read_ram (uint8_t idx)
Read data from backup ram. More...

Detailed Description

BKPC module driver.

Version
V1.0
Date
15 Dec 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_bkpc.c.


ALD User Manual: D:/svn/src/ald_bkpc.h File Reference

  • D:
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  • src
Macros | Enumerations | Functions
ald_bkpc.h File Reference

Header file of BKPC module driver. More...

#include "utils.h"
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Macros

#define | BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0U))
#define | BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55U))
#define | BKPC_LRC_ENABLE()
#define | BKPC_LRC_DISABLE()
#define | BKPC_LOSM_ENABLE()
#define | BKPC_LOSM_DISABLE()
#define | BKPC_LOSC_ENABLE()
#define | BKPC_LOSC_DISABLE()
#define | BKPC_MRST_WAKEUP_ENABLE()
#define | BKPC_MRST_WAKEUP_DISABLE()
#define | IS_BKPC_WAKEUP_PORT(x)
#define | IS_BKPC_WAKEUP_LEVEL(x)
#define | IS_BKPC_PREH_CLOCK(x)
#define | IS_BKPC_RAM_IDX(x) ((x) < 32)

Enumerations

enum | bkpc_preh_clk_t { BKPC_PREH_CLK_LOSM = 0x0U, BKPC_PREH_CLK_LRC = 0x1U, BKPC_PREH_CLK_HRC_1M = 0x2U, BKPC_PREH_CLK_HOSC_1M = 0x3U }
BKPC preipheral clock select. More...
enum bkpc_wakeup_port_t {
PMU_STANDBY_PORT_SEL_PA0 = 0x0U, PMU_STANDBY_PORT_SEL_PA1 = 0x1U, PMU_STANDBY_PORT_SEL_PA2 = 0x2U, PMU_STANDBY_PORT_SEL_PA3 = 0x3U,
PMU_STANDBY_PORT_SEL_PA4 = 0x4U, PMU_STANDBY_PORT_SEL_PA5 = 0x5U, PMU_STANDBY_PORT_SEL_PA6 = 0x6U, PMU_STANDBY_PORT_SEL_PA7 = 0x7U,
PMU_STANDBY_PORT_SEL_NONE = 0xFU
}
Standby wakeup port select. More...
enum | bkpc_wakeup_level_t { PMU_STANDBY_LEVEL_HIGH = 0x0U, PMU_STANDBY_LEVEL_LOW = 0x1U }
Standby wakeup level. More...

Functions

void | ald_bkpc_standby_wakeup_config (bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
Configure standby wakeup in backup field. More...
void | ald_bkpc_rtc_clock_config (bkpc_preh_clk_t clock)
Configure rtc clock in backup field. More...
void | ald_bkpc_tsense_clock_config (bkpc_preh_clk_t clock)
Configure tsense clock in backup field. More...
void | ald_bkpc_write_ram (uint8_t idx, uint32_t value)
Write data into backup ram. More...
uint32_t | ald_bkpc_read_ram (uint8_t idx)
Read data from backup ram. More...

Detailed Description

Header file of BKPC module driver.

Version
V1.0
Date
15 Dec 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_bkpc.h.


ALD User Manual: D:/svn/src/ald_calc.c File Reference

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  • svn
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Functions
ald_calc.c File Reference

CALC module driver. More...

#include "ald_calc.h"
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Functions

uint32_t | ald_calc_sqrt (uint32_t data)
Square root operation. More...
uint32_t | ald_calc_div (uint32_t dividend, uint32_t divisor, uint32_t *remainder)
Calculating division. More...
int32_t | ald_calc_div_sign (int32_t dividend, int32_t divisor, int32_t *remainder)
Calculating division. More...
flag_status_t | ald_calc_get_dz_status (void)
Get the flag of divisor is zero. More...

Detailed Description

CALC module driver.

Version
V1.0
Date
26 Jun 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_calc.c.


ALD User Manual: D:/svn/src/ald_calc.h File Reference

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  • svn
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Functions
ald_calc.h File Reference

Header file of CALC module driver. More...

#include "utils.h"
Include dependency graph for ald_calc.h:
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Functions

uint32_t | ald_calc_sqrt (uint32_t data)
Square root operation. More...
uint32_t | ald_calc_div (uint32_t dividend, uint32_t divisor, uint32_t *remainder)
Calculating division. More...
int32_t | ald_calc_div_sign (int32_t dividend, int32_t divisor, int32_t *remainder)
Calculating division. More...
flag_status_t | ald_calc_get_dz_status (void)
Get the flag of divisor is zero. More...

Detailed Description

Header file of CALC module driver.

Version
V1.0
Date
26 Jun 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_calc.h.


ALD User Manual: D:/svn/src/ald_can.c File Reference

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  • svn
  • src
Functions
ald_can.c File Reference

CAN module driver. This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral: More...

#include "ald_can.h"
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Functions

static void | can_rx_fifo_release (can_handle_t *hperh, can_rx_fifo_t num)
Release rx FIFO. More...
static ald_status_t | __can_send_by_it (can_handle_t *hperh, uint8_t err)
transmits a CAN frame message using interrupt. More...
static ald_status_t | __can_recv_by_it (can_handle_t *hperh, can_rx_fifo_t num)
Receives a correct CAN frame using interrupt. More...
ald_status_t | ald_can_init (can_handle_t *hperh)
Initializes the CAN peripheral according to the specified parameters in the CAN_init_t. More...
ald_status_t | ald_can_filter_config (can_handle_t *hperh, can_filter_t *config)
Configures the CAN reception filter according to the specified parameters in the can_filter_t. More...
void | ald_can_reset (can_handle_t *hperh)
Reset the CAN peripheral. More...
ald_status_t | ald_can_send (can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout)
Send a CAN frame message. More...
ald_status_t | ald_can_send_by_it (can_handle_t *hperh, can_tx_msg_t *msg)
Send a CAN frame message using interrupt. More...
ald_status_t | ald_can_recv (can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout)
Receives a correct CAN frame. More...
ald_status_t | ald_can_recv_by_it (can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg)
Receives a correct CAN frame using interrupt. More...
ald_status_t | ald_can_sleep (can_handle_t *hperh)
Enters the Sleep(low power) mode. More...
ald_status_t | ald_can_wake_up (can_handle_t *hperh)
Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral is in the normal mode. More...
void | ald_can_irq_handler (can_handle_t *hperh)
Handles CAN interrupt request. More...
type_bool_t | ald_can_get_tx_status (can_handle_t *hperh, can_tx_mailbox_t box)
Check the transmission status of a CAN Frame. More...
void | ald_can_cancel_send (can_handle_t *hperh, can_tx_mailbox_t box)
Cancel transmission. More...
void | ald_can_interrupt_config (can_handle_t *hperh, can_it_t it, type_func_t state)
Enable/disable the specified CAN interrupts. More...
it_status_t | ald_can_get_it_status (can_handle_t *hperh, can_it_t it)
Get the status of CAN interrupt source. More...
flag_status_t | ald_can_get_flag_status (can_handle_t *hperh, can_flag_t flag)
Get the status of CAN interrupt flag. More...
void | can_clear_flag (can_handle_t *hperh, can_flag_t flag)
Clear the specified CAN pending flag. More...
can_state_t | ald_can_get_state (can_handle_t *hperh)
return the CAN state More...
can_error_t | ald_can_get_error (can_handle_t *hperh)
Return the CAN error code. More...
static int | __can_rx_check (can_handle_t *hperh, can_rx_fifo_t num)
Check whether the data in the mailbox is contaminated. More...

Detailed Description

CAN module driver. This file provides firmware functions to manage the following functionalities of the Controller Area Network (CAN) peripheral:

  • Initialization functions
  • IO operation functions
  • Peripheral Control functions
  • Peripheral State and Error functions
    Version
    V1.0
    Date
    25 Apr 2019
    Author
    AE Team
    Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
==============================================================================
                      ##### How to use this driver #####
==============================================================================
  [..]
    (#) Enable the CAN controller interface clock.
    (#) CAN pins configuration
      (++) Enable the clock for the CAN GPIOs;
      (++) Connect and configure the involved CAN pins using the
           following function ald_gpio_init();
    (#) Initialise and configure the CAN using ald_can_init() function.
    (#) Transmit the CAN frame using ald_can_send()/ald_can_send_by_it() function.
    (#) Receive a CAN frame using ald_can_recv()/ald_can_recv_by_it function.

   *** Polling mode IO operation ***
   =================================
   [..]
     (+) Start the CAN peripheral transmission and wait the end of this operation
         using ald_can_send(), at this stage user can specify the value of timeout
         according to his end application.
     (+) Start the CAN peripheral reception and wait the end of this operation
         using ald_can_recv(), at this stage user can specify the value of timeout
         according to his end application

   *** Interrupt mode IO operation ***
   ===================================
   [..]
     (+) Start the CAN peripheral transmission using ald_can_send_by_it()
     (+) Start the CAN peripheral reception using ald_can_recv_by_it()
     (+) Use ald_can_irq_handler() called under the used CAN Interrupt subroutine
     (+) At CAN end of transmission pherh->tx_cplt_cbk() function is executed and user can
          add his own code by customization of function pointer pherh->tx_cplt_cbk()
     (+) In case of CAN Error, pherh->rx_cplt_cbk() function is executed and user can
          add his own code by customization of function pointer pherh->rx_cplt_cbk()

   *** CAN ALD driver macros list ***
   =============================================
   [..]
     Below the list of most used macros in CAN driver.

    (+) CAN_RESET_HANDLE_STATE(): Reset CAN handle state.
    (+) CAN_RX_MSG_PENDING(): Return the number of pending received messages.
    (+) CAN_DBG_FREEZE(): Enable or disables the DBG Freeze for CAN.

   [..]
    (@) You can refer to the CAN driver header file for used the macros

Definition in file ald_can.c.


ALD User Manual: D:/svn/src/ald_can.h File Reference

  • D:
  • svn
  • src
Data Structures | Macros | Typedefs | Enumerations | Functions
ald_can.h File Reference

Header file of CAN Module driver. More...

#include "utils.h"
Include dependency graph for ald_can.h:
This graph shows which files directly or indirectly include this file:

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Data Structures

struct | can_filter_t
CAN filter configuration structure definition. More...
struct | can_init_t
CAN init structure definition. More...
struct | can_tx_msg_t
CAN Tx message structure definition. More...
struct | can_rx_msg_t
CAN Rx message structure definition. More...
struct | can_handle_s
CAN handle Structure definition. More...

Macros

#define | CAN_RESET_HANDLE_STATE(x) ((x)->state = CAN_STATE_RESET)
#define | CAN_RX_MSG_PENDING(x, y)
#define | CAN_DBG_FREEZE(x, y) (MODIFY_REG((x)->perh->CON, CAN_CON_DBGSTP_MSK, (y) << CAN_CON_DBGSTP_POS))
#define | CAN_TX_STAMP_ENABLE(x, y) (SET_BIT((x)->perh->TxMailBox[(y)].TXFCON, CAN_TXFCON0_TXGT_MSK))
#define | CAN_TX_STAMP_DISABLE(x, y) (CLEAR_BIT((x)->perh->TxMailBox[(y)].TXFCON, CAN_TXFCON0_TXGT_MSK))
#define | IS_CAN_ALL(x) ((x) == CAN0)
#define | IS_CAN_FILTER_NUMBER(x) ((x) <= 13)
#define | IS_CAN_MODE(x)
#define | IS_CAN_SJW(x)
#define | IS_CAN_BS1(x) ((x) <= CAN_SEG1_16)
#define | IS_CAN_BS2(x) ((x) <= CAN_SEG2_8)
#define | IS_CAN_FILTER_MODE(x)
#define | IS_CAN_FILTER_SCALE(x)
#define | IS_CAN_FILTER_FIFO(x)
#define | IS_CAN_IDTYPE(x)
#define | IS_CAN_RTR(x) (((x) == CAN_RTR_DATA) || ((x) == CAN_RTR_REMOTE))
#define | IS_CAN_FIFO(x) (((x) == CAN_RX_FIFO0) || ((x) == CAN_RX_FIFO1))
#define | IS_CAN_TX_MAILBOX(x) ((x) <= CAN_TX_MAILBOX_NONE)
#define | IS_CAN_STDID(x) ((x) <= ((uint32_t)0x7FF))
#define | IS_CAN_EXTID(x) ((x) <= ((uint32_t)0x1FFFFFFF))
#define | IS_CAN_DATA_LEN(x) ((x) <= ((uint8_t)0x08))
#define | IS_CAN_PRESCALER(x) (((x) >= 1) && ((x) <= 1024))
#define | IS_CAN_GET_FLAG(x)
#define | IS_CAN_CLEAR_FLAG(x)
#define | IS_CAN_IT(x)
#define | CAN_TIMEOUT_VALUE 100
#define | CAN_STATE_TX_MASK (1U << 4)
#define | CAN_STATE_RX0_MASK (1U << 5)
#define | CAN_STATE_RX1_MASK (1U << 6)

Typedefs

typedef struct can_handle_s can_handle_t
CAN handle Structure definition. More...

Enumerations

enum can_state_t {
CAN_STATE_RESET = 0x00U, CAN_STATE_READY = 0x01U, CAN_STATE_BUSY = 0x02U, CAN_STATE_BUSY_TX = 0x11U,
CAN_STATE_BUSY_RX0 = 0x21U, CAN_STATE_BUSY_RX1 = 0x41U, CAN_STATE_BUSY_TX_RX0 = 0x31U, CAN_STATE_BUSY_TX_RX1 = 0x51U,
CAN_STATE_BUSY_RX0_RX1 = 0x61U, CAN_STATE_BUSY_TX_RX0_RX1 = 0x71U, CAN_STATE_TIMEOUT = 0x04U, CAN_STATE_ERROR = 0x08U
}
ALD State structures definition. More...
enum can_error_t {
CAN_ERROR_NONE = 0x00U, CAN_ERROR_EWG = 0x01U, CAN_ERROR_EPV = 0x02U, CAN_ERROR_BOF = 0x04U,
CAN_ERROR_STF = 0x08U, CAN_ERROR_FOR = 0x10U, CAN_ERROR_ACK = 0x20U, CAN_ERROR_BR = 0x40U,
CAN_ERROR_BD = 0x80U, CAN_ERROR_CRC = 0x100U, CAN_ERROR_UNK = 0x200U
}
CAN Error Code. More...
enum | can_operate_mode_t { CAN_MODE_NORMAL = 0x00U, CAN_MODE_LOOPBACK = 0x01U, CAN_MODE_SILENT = 0x02U, CAN_MODE_SILENT_LOOPBACK = 0x03U }
CAN Operating Mode. More...
enum | can_sjw_t { CAN_SJW_1 = 0x0U, CAN_SJW_2 = 0x1U, CAN_SJW_3 = 0x2U, CAN_SJW_4 = 0x3U }
CAN Synchronization Jump Width. More...
enum can_seg1_t {
CAN_SEG1_1 = 0x0U, CAN_SEG1_2 = 0x1U, CAN_SEG1_3 = 0x2U, CAN_SEG1_4 = 0x3U,
CAN_SEG1_5 = 0x4U, CAN_SEG1_6 = 0x5U, CAN_SEG1_7 = 0x6U, CAN_SEG1_8 = 0x7U,
CAN_SEG1_9 = 0x8U, CAN_SEG1_10 = 0x9U, CAN_SEG1_11 = 0xAU, CAN_SEG1_12 = 0xBU,
CAN_SEG1_13 = 0xCU, CAN_SEG1_14 = 0xDU, CAN_SEG1_15 = 0xEU, CAN_SEG1_16 = 0xFU
}
CAN Time Quantum in Bit Segment 1. More...
enum can_seg2_t {
CAN_SEG2_1 = 0x0U, CAN_SEG2_2 = 0x1U, CAN_SEG2_3 = 0x2U, CAN_SEG2_4 = 0x3U,
CAN_SEG2_5 = 0x4U, CAN_SEG2_6 = 0x5U, CAN_SEG2_7 = 0x6U, CAN_SEG2_8 = 0x7U
}
CAN Time Quantum in Bit Segment 2. More...
enum | can_filter_mode_t { CAN_FILTER_MODE_MASK = 0x0U, CAN_FILTER_MODE_LIST = 0x1U }
CAN Filter Mode. More...
enum | can_filter_scale_t { CAN_FILTER_SCALE_16 = 0x0U, CAN_FILTER_SCALE_32 = 0x1U }
CAN Filter Scale. More...
enum | can_filter_fifo_t { CAN_FILTER_FIFO0 = 0x0U, CAN_FILTER_FIFO1 = 0x1U }
CAN Filter fifo. More...
enum | can_id_type_t { CAN_ID_STD = 0x0U, CAN_ID_EXT = 0x1U }
CAN Identifier Type. More...
enum | can_remote_req_t { CAN_RTR_DATA = 0x0U, CAN_RTR_REMOTE = 0x1U }
CAN Remote Transmission Request. More...
enum | can_tx_mailbox_t { CAN_TX_MAILBOX_0 = 0x0U, CAN_TX_MAILBOX_1 = 0x1U, CAN_TX_MAILBOX_2 = 0x2U, CAN_TX_MAILBOX_NONE = 0x3U }
CAN Transmit Constants. More...
enum | can_rx_fifo_t { CAN_RX_FIFO0 = 0x0U, CAN_RX_FIFO1 = 0x1U }
CAN Receive fifo Number. More...
enum can_flag_t {
CAN_FLAG_SLPS = (1U << 1), CAN_FLAG_ERR = (1U << 2), CAN_FLAG_WK = (1U << 3), CAN_FLAG_SLP = (1U << 4),
CAN_FLAG_M0REQC = (1U << 20) | (1U << 0), CAN_FLAG_M0TXC = (1U << 20) | (1U << 1), CAN_FLAG_M1REQC = (1U << 20) | (1U << 8), CAN_FLAG_M1TXC = (1U << 20) | (1U << 9),
CAN_FLAG_M2REQC = (1U << 20) | (1U << 16), CAN_FLAG_M2TXC = (1U << 20) | (1U << 17), CAN_FLAG_TXM0 = (1U << 20) | (1U << 26), CAN_FLAG_TXM1 = (1U << 20) | (1U << 27),
CAN_FLAG_TXM2 = (1U << 20) | (1U << 28), CAN_FLAG_FF0 = (2U << 20) | (1U << 3), CAN_FLAG_FOV0 = (2U << 20) | (1U << 4), CAN_FLAG_FF1 = (3U << 20) | (1U << 3),
CAN_FLAG_FOV1 = (3U << 20) | (1U << 4), CAN_FLAG_WARN = (4U << 20) | (1U << 0), CAN_FLAG_PERR = (4U << 20) | (1U << 1), CAN_FLAG_BOF = (4U << 20) | (1U << 2)
}
CAN Flags. More...
enum can_it_t {
CAN_IT_TXM = (1U << 0), CAN_IT_FP0 = (1U << 1), CAN_IT_FF0 = (1U << 2), CAN_IT_FOV0 = (1U << 3),
CAN_IT_FP1 = (1U << 4), CAN_IT_FF1 = (1U << 5), CAN_IT_FOV1 = (1U << 6), CAN_IT_WARN = (1U << 8),
CAN_IT_PERR = (1U << 9), CAN_IT_BOF = (1U << 10), CAN_IT_PRERR = (1U << 11), CAN_IT_ERR = (1U << 15),
CAN_IT_WK = (1U << 16), CAN_IT_SLP = (1U << 17)
}
CAN Interrupts. More...

Functions

void | ald_can_reset (can_handle_t *hperh)
Reset the CAN peripheral. More...
ald_status_t | ald_can_init (can_handle_t *hperh)
Initializes the CAN peripheral according to the specified parameters in the CAN_init_t. More...
ald_status_t | ald_can_filter_config (can_handle_t *hperh, can_filter_t *config)
Configures the CAN reception filter according to the specified parameters in the can_filter_t. More...
ald_status_t | ald_can_send (can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout)
Send a CAN frame message. More...
ald_status_t | ald_can_send_by_it (can_handle_t *hperh, can_tx_msg_t *msg)
Send a CAN frame message using interrupt. More...
ald_status_t | ald_can_recv (can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout)
Receives a correct CAN frame. More...
ald_status_t | ald_can_recv_by_it (can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg)
Receives a correct CAN frame using interrupt. More...
ald_status_t | ald_can_sleep (can_handle_t *hperh)
Enters the Sleep(low power) mode. More...
ald_status_t | ald_can_wake_up (can_handle_t *hperh)
Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral is in the normal mode. More...
void | ald_can_cancel_send (can_handle_t *hperh, can_tx_mailbox_t box)
Cancel transmission. More...
void | ald_can_irq_handler (can_handle_t *hperh)
Handles CAN interrupt request. More...
type_bool_t | ald_can_get_tx_status (can_handle_t *hperh, can_tx_mailbox_t box)
Check the transmission status of a CAN Frame. More...
void | ald_can_interrupt_config (can_handle_t *hperh, can_it_t it, type_func_t state)
Enable/disable the specified CAN interrupts. More...
it_status_t | ald_can_get_it_status (can_handle_t *hperh, can_it_t it)
Get the status of CAN interrupt source. More...
flag_status_t | ald_can_get_flag_status (can_handle_t *hperh, can_flag_t flag)
Get the status of CAN interrupt flag. More...
void | ald_can_clear_flag_status (can_handle_t *hperh, can_flag_t flag)
can_state_t | ald_can_get_state (can_handle_t *hperh)
return the CAN state More...
can_error_t | ald_can_get_error (can_handle_t *hperh)
Return the CAN error code. More...

Detailed Description

Header file of CAN Module driver.

Version
V1.0
Date
16 Apr 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_can.h.


ALD User Manual: D:/svn/src/ald_cmu.c File Reference

  • D:
  • svn
  • src
Functions | Variables
ald_cmu.c File Reference

CMU module driver. More...

#include "ald_cmu.h"
#include "ald_flash.h"
Include dependency graph for ald_cmu.c:

Go to the source code of this file.

Functions

static void | cmu_clock_update (uint32_t clock)
Update the current system clock. This function will be invoked, when system clock has changed. More...
void | ald_cmu_irq_handler (void)
CMU module interrupt handler. More...
ald_status_t | ald_cmu_clock_config_default (void)
Configure system clock using default. Select CMU_CLOCK_HRC(24MHz) as system clock and enable CMU_CLOCK_LRC(32768Hz). More...
ald_status_t | ald_cmu_clock_config (cmu_clock_t clk, uint32_t clock)
Configure system clock using specified parameters. More...
void | ald_cmu_pll1_config (cmu_pll1_input_t input, cmu_pll1_output_t output)
Configure PLL1 using specified parameters. More...
uint32_t | ald_cmu_get_clock (void)
Gets current system clock. More...
void | ald_cmu_div_config (cmu_bus_t bus, cmu_div_t div)
Configure the bus division. More...
uint32_t | ald_cmu_get_hclk1_clock (void)
Get AHB1 clock. More...
uint32_t | ald_cmu_get_hclk2_clock (void)
Get AHB2 clock. More...
uint32_t | ald_cmu_get_sys_clock (void)
Get SYS clock. More...
uint32_t | ald_cmu_get_pclk1_clock (void)
Get APB1 clock. More...
uint32_t | ald_cmu_get_pclk2_clock (void)
Get APB2 clock. More...
void | ald_cmu_hosc_safe_config (cmu_hosc_range_t clock, type_func_t status)
Enable/Disable outer high crystal safe mode. More...
void | ald_cmu_losc_safe_config (type_func_t status)
Enable/Disable outer low crystal safe mode. More...
void | ald_cmu_pll_safe_config (type_func_t status)
Enable/Disable PLL1 safe mode. More...
uint32_t | ald_cmu_current_clock_source_get (cmu_clock_safe_type_t type)
Get current clock source. More...
flag_status_t | ald_cmu_get_clock_state (cmu_clock_state_t sr)
Get clock state. More...
__weak void | ald_cmu_irq_cbk (cmu_security_t se)
Interrupt callback function. More...
void | ald_cmu_output_high_clock_config (cmu_output_high_sel_t sel, cmu_output_high_div_t div, type_func_t status)
Configure the high-speed clock output. More...
void | ald_cmu_output_low_clock_config (cmu_output_low_sel_t sel, type_func_t status)
Configure the low-speed clock output. More...
void | ald_cmu_buzz_config (cmu_buzz_div_t div, uint16_t dat, type_func_t status)
Configure buzz clock. freq = sysclk / (2^(div + 1) * (dat + 1)) More...
void | ald_cmu_lptim0_clock_select (cmu_lp_perh_clock_sel_t clock)
Select lptim0 clock source. More...
void | ald_cmu_lpuart0_clock_select (cmu_lp_perh_clock_sel_t clock)
Select lpuart0 clock source. More...
void | ald_cmu_lcd_clock_select (cmu_lcd_clock_sel_t clock)
Select lcd clock source. More...
void | ald_cmu_qspi_clock_select (cmu_qspi_clock_sel_t clock)
Select QSPI clock source. More...
void | ald_cmu_usb_clock_config (cmu_usb_clock_sel_t clock, cmu_usb_div_t div)
Configure USB clock source. More...
void | ald_cmu_perh_clock_config (cmu_perh_t perh, type_func_t status)
Enable/Disable peripheral clock. More...
void | ald_cmu_stop1_clock_sel (cmu_stop1_clock_t clock)
Select stop1 clock. More...

Variables

uint32_t __system_clock = 24000000U

Detailed Description

CMU module driver.

Version
V1.0
Date
22 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

==============================================================================
                      ##### How to use this driver #####
==============================================================================
  [..]
   *** System clock configure ***
   =================================
   [..]
     (+) If you don't change system clock, you can using ald_cmu_clock_config_default() API.
         It will select HRC as system clock. The system clock is 24MHz.
     (+) If you want to change system clock, you can using ald_cmu_clock_config() API.
         You can select one of the following as system clock:
           @ref CMU_CLOCK_HRC   2MHz or 24MHz
           @ref CMU_CLOCK_LRC   32768Hz
           @ref CMU_CLOCK_LOSC  32768Hz
           @ref CMU_CLOCK_PLL1  36MHz/48MHz/72MHz/96MHz
           @ref CMU_CLOCK_HOSC  1MHz -- 24MHz
     (+) If you select CMU_CLOCK_PLL1 as system clock, it must config the PLL1
         using ald_cmu_pll1_config() API. The input of clock must be 4MHz.
     (+) If you get current clock, you can using ald_cmu_get_clock() API.

   *** BUS division control ***
   ===================================

   MCLK            sys_clk
   -------DIV_SYS-----------+--------------------------System(Core, DMA, Systick ... etc.)
                            |
                            |                  hclk1
                            +------DIV_AHB1------------Peripheral(GPIO, CRC, ... etc.)
                            |
                            |                  hclk2
                            +------DIV_AHB2------------Peripheral(EBI, QSPI, ... etc.)
                            |
                            |                  pclk1
                            +------DIV_APB1------------Peripheral(TIM, UART, ... etc.)
                            |
                            |                  pclk2
                            +------DIV_APB2------------Peripheral(ADC, WWDT, ... etc.)

   [..]
     (+) Configure the division using ald_cmu_div_config() API.
     (+) Get sys_clk using ald_cmu_get_sys_clock() API.
     (+) Get hclk1 using ald_cmu_get_hclk1_clock() API.
     (+) Get pclk1 using ald_cmu_get_pclk1_clock() API.
     (+) Get pclk2 using ald_cmu_get_pclk2_clock() API.

   *** Clock safe configure ***
   ===================================
   [..]
     (+) If you select CMU_CLOCK_HOSC as system clock, you need enable
         clock safe using ald_cmu_hosc_safe_config() API. It will change
         CMU_CLOCK_HRC as system clock, when the outer crystal stoped.
     (+) If you select CMU_CLOCK_LOSC as system clock, you need enable
         clock safe using ald_cmu_losc_safe_config() API. It will change
         CMU_CLOCK_LRC as system clock, when the outer crystal stoped.
     (+) If you select CMU_CLOCK_PLL1 as system clock, you need enable
         clock safe using ald_cmu_pll_safe_config() API. It will change
         CMU_CLOCK_HRC as system clock, when the pll1 is lose.
     (+) The ald_cmu_irq_cbk() will be invoked, when CMU interrupt has
         been occurred. You can overwrite this function in application.

   *** Clock output configure ***
   ===================================
   [..]
     (+) Output high-speed clock using ald_cmu_output_high_clock_config() API.
     (+) Output low-speed clock using ald_cmu_output_low_clock_config() API.

   *** Peripheral clock configure ***
   ===================================
   [..]
     (+) Configure buzz clock using ald_cmu_buzz_config() API.
     (+) Selected lptim0 clock using ald_cmu_lptim0_clock_select() API.
     (+) Selected lpuart clock using ald_cmu_lpuart0_clock_select() API.
     (+) Selected lcd clock using ald_cmu_lcd_clock_select() API.
     (+) Selected qspi clock using ald_cmu_qspi_clock_select() API.
     (+) Configure usb clock using ald_cmu_usb_clock_config() API.
     (+) Enable/Disable peripheral clock using ald_cmu_perh_clock_config() API.
     (+) Selected stop1 clock using ald_cmu_stop1_clock_sel() API.

   *** CMU ALD driver macros list ***
   =============================================
   [..]
     Below the list of most used macros in CMU driver.

    (+) CMU_HRC_SEL_BY_SW():         HRC clock config by software.
    (+) CMU_HRC_SEL_BY_CFGW():       HRC clock config by CFG Word.
    (+) CMU_HRC_DIV_1MHZ_ENABLE():   Enable HRC divider to 1MHz.
    (+) CMU_HRC_DIV_1MHZ_DISABLE():  Disable HRC divider to 1MHz.
    (+) CMU_HOSC_DIV_1MHZ_ENABLE():  Enable HOSC divider to 1MHz.
    (+) CMU_HOSC_DIV_1MHZ_DISABLE(): Disable HOSC divider to 1MHz.
    (+) CMU_LOSC_ENABLE():           Enable outer low crystal(32768Hz).
    (+) CMU_LOSC_DISABLE():          Disable outer low crystal(32768Hz).
    (+) CMU_LRC_ENABLE():            Enable LRC(32768Hz).
    (+) CMU_LRC_DISABLE():           Disable LRC(32768Hz).
    (+) CMU_ULRC_ENABLE():           Enable ULRC(10KHz).
    (+) CMU_ULRC_DISABLE():          Disable ULRC(10KHz).
    (+) CMU_LP_LRC_ENABLE():         Enable low power LRC(32768Hz).
    (+) CMU_LP_LRC_DISABLE():        Disable low power LRC(32768Hz).
    (+) CMU_LP_LOSC_ENABLE():        Enable low power LOSC(32768Hz).
    (+) CMU_LP_LOSC_DISABLE():       Disable low power LOSC(32768Hz).
    (+) CMU_LP_HRC_ENABLE():         Enable low power HRC(2MHz or 24MHz).
    (+) CMU_LP_HRC_DISABLE():        Disable low power HRC(2MHz OR 24MHz).
    (+) CMU_LP_HOSC_ENABLE():        Enable low power HOSC(1MHz -- 24MHz).
    (+) CMU_LP_HOSC_DISABLE():       Disable low power HOSC(1MHz -- 24MHz).

   [..]
    (@) You can refer to the CMU driver header file for used the macros

Definition in file ald_cmu.c.


ALD User Manual: D:/svn/src/ald_cmu.h File Reference

  • D:
  • svn
  • src
Macros | Enumerations | Functions
ald_cmu.h File Reference

Header file of CMU module driver. More...

#include "utils.h"
#include "ald_syscfg.h"
Include dependency graph for ald_cmu.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | CMU_HRC_SEL_BY_SW()
#define | CMU_HRC_SEL_BY_CFGW()
#define | CMU_HRC_DIV_1MHZ_ENABLE()
#define | CMU_HRC_DIV_1MHZ_DISABLE()
#define | CMU_HOSC_DIV_1MHZ_ENABLE()
#define | CMU_HOSC_DIV_1MHZ_DISABLE()
#define | CMU_LOSC_ENABLE()
#define | CMU_LOSC_DISABLE()
#define | CMU_LRC_ENABLE()
#define | CMU_LRC_DISABLE()
#define | CMU_ULRC_ENABLE()
#define | CMU_ULRC_DISABLE()
#define | CMU_LP_LRC_ENABLE()
#define | CMU_LP_LRC_DISABLE()
#define | CMU_LP_LOSC_ENABLE()
#define | CMU_LP_LOSC_DISABLE()
#define | CMU_LP_HRC_ENABLE()
#define | CMU_LP_HRC_DISABLE()
#define | CMU_LP_HOSC_ENABLE()
#define | CMU_LP_HOSC_DISABLE()
#define | IS_CMU_CLOCK(x)
#define | IS_CMU_PLL1_INPUT(x)
#define | IS_CMU_HOSC_RANGE(x)
#define | IS_CMU_DIV(x)
#define | IS_CMU_BUS(x)
#define | IS_CMU_OUTPUT_HIGH_SEL(x)
#define | IS_CMU_OUTPUT_HIGH_DIV(x)
#define | IS_CMU_OUTPUT_LOW_SEL(x)
#define | IS_CMU_SAFE_CLOCK_TYPE(x)
#define | IS_CMU_BUZZ_DIV(x)
#define | IS_CMU_LP_PERH_CLOCK_SEL(x)
#define | IS_CMU_LCD_CLOCK_SEL(x)
#define | IS_CMU_QSPI_CLOCK_SEL(x)
#define | IS_CMU_USB_CLOCK_SEL(x)
#define | IS_CMU_USB_DIV(x)
#define | IS_CMU_PERH(x)
#define | IS_CMU_CLOCK_STATE(x)
#define | IS_CMU_STOP1_CLOCK(x)

Enumerations

enum cmu_clock_t {
CMU_CLOCK_HRC = 0x1U, CMU_CLOCK_LRC = 0x2U, CMU_CLOCK_LOSC = 0x3U, CMU_CLOCK_PLL1 = 0x4U,
CMU_CLOCK_HOSC = 0x5U
}
CMU state structure definition. More...
enum | cmu_pll1_output_t { CMU_PLL1_OUTPUT_36M = 0x0U, CMU_PLL1_OUTPUT_48M = 0x1U }
PLL1 output clock. More...
enum cmu_pll1_input_t {
CMU_PLL1_INPUT_HRC_6 = 0x0U, CMU_PLL1_INPUT_PLL2 = 0x1U, CMU_PLL1_INPUT_HOSC = 0x2U, CMU_PLL1_INPUT_HOSC_2 = 0x3U,
CMU_PLL1_INPUT_HOSC_3 = 0x4U, CMU_PLL1_INPUT_HOSC_4 = 0x5U, CMU_PLL1_INPUT_HOSC_5 = 0x6U, CMU_PLL1_INPUT_HOSC_6 = 0x7U
}
PLL1 referance clock. More...
enum cmu_hosc_range_t {
CMU_HOSC_2M = 0x0U, CMU_HOSC_4M = 0x1U, CMU_HOSC_8M = 0x2U, CMU_HOSC_16M = 0x3U,
CMU_HOSC_24M = 0x4U
}
HOSC range. More...
enum | cmu_clock_safe_type_t { CMU_SAFE_CLK_HOSC = 0x0U, CMU_SAFE_CLK_LOSC = 0x1U, CMU_SAFE_CLK_PLL = 0x2U }
Safe clock source type. More...
enum cmu_div_t {
CMU_DIV_1 = 0x0U, CMU_DIV_2 = 0x1U, CMU_DIV_4 = 0x2U, CMU_DIV_8 = 0x3U,
CMU_DIV_16 = 0x4U, CMU_DIV_32 = 0x5U, CMU_DIV_64 = 0x6U, CMU_DIV_128 = 0x7U,
CMU_DIV_256 = 0x8U, CMU_DIV_512 = 0x9U, CMU_DIV_1024 = 0xAU, CMU_DIV_2048 = 0xBU,
CMU_DIV_4096 = 0xCU
}
Frequency division select bit. More...
enum cmu_bus_t {
CMU_HCLK_1 = 0x0U, CMU_HCLK_2 = 0x1U, CMU_SYS = 0x2U, CMU_PCLK_1 = 0x3U,
CMU_PCLK_2 = 0x4U
}
Bus type. More...
enum cmu_output_high_sel_t {
CMU_OUTPUT_HIGH_SEL_HOSC = 0x0U, CMU_OUTPUT_HIGH_SEL_LOSC = 0x1U, CMU_OUTPUT_HIGH_SEL_HRC = 0x2U, CMU_OUTPUT_HIGH_SEL_LRC = 0x3U,
CMU_OUTPUT_HIGH_SEL_HOSM = 0x4U, CMU_OUTPUT_HIGH_SEL_PLL1 = 0x5U, CMU_OUTPUT_HIGH_SEL_PLL2 = 0x6U, CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7U
}
Output high clock select. More...
enum cmu_output_high_div_t {
CMU_OUTPUT_DIV_1 = 0x0U, CMU_OUTPUT_DIV_2 = 0x1U, CMU_OUTPUT_DIV_4 = 0x2U, CMU_OUTPUT_DIV_8 = 0x3U,
CMU_OUTPUT_DIV_16 = 0x4U, CMU_OUTPUT_DIV_32 = 0x5U, CMU_OUTPUT_DIV_64 = 0x6U, CMU_OUTPUT_DIV_128 = 0x7U
}
Output frequency division. More...
enum cmu_output_low_sel_t {
CMU_OUTPUT_LOW_SEL_LOSC = 0x0U, CMU_OUTPUT_LOW_SEL_LRC = 0x1U, CMU_OUTPUT_LOW_SEL_LOSM = 0x2U, CMU_OUTPUT_LOW_SEL_BUZZ = 0x3U,
CMU_OUTPUT_LOW_SEL_ULRC = 0x4U
}
Output low clock select. More...
enum cmu_buzz_div_t {
CMU_BUZZ_DIV_2 = 0x0U, CMU_BUZZ_DIV_4 = 0x1U, CMU_BUZZ_DIV_8 = 0x2U, CMU_BUZZ_DIV_16 = 0x3U,
CMU_BUZZ_DIV_32 = 0x4U, CMU_BUZZ_DIV_64 = 0x5U, CMU_BUZZ_DIV_128 = 0x6U, CMU_BUZZ_DIV_256 = 0x7U
}
BUZZ frequency division. More...
enum cmu_lp_perh_clock_sel_t {
CMU_LP_PERH_CLOCK_SEL_PCLK2 = 0x0U, CMU_LP_PERH_CLOCK_SEL_PLL1 = 0x1U, CMU_LP_PERH_CLOCK_SEL_PLL2 = 0x2U, CMU_LP_PERH_CLOCK_SEL_HRC = 0x3U,
CMU_LP_PERH_CLOCK_SEL_HOSC = 0x4U, CMU_LP_PERH_CLOCK_SEL_LRC = 0x5U, CMU_LP_PERH_CLOCK_SEL_LOSC = 0x6U, CMU_LP_PERH_CLOCK_SEL_ULRC = 0x7U,
CMU_LP_PERH_CLOCK_SEL_HRC_1M = 0x8U, CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9U, CMU_LP_PERH_CLOCK_SEL_LOSM = 0xAU, CMU_LP_PERH_CLOCK_SEL_HOSM = 0xBU
}
Low power peripheral clock select. More...
enum cmu_lcd_clock_sel_t {
CMU_LCD_SEL_LOSM = 0x0U, CMU_LCD_SEL_LOSC = 0x1U, CMU_LCD_SEL_LRC = 0x2U, CMU_LCD_SEL_ULRC = 0x3U,
CMU_LCD_SEL_HRC_1M = 0x4U, CMU_LCD_SEL_HOSC_1M = 0x5U
}
LCD clock select. More...
enum cmu_qspi_clock_sel_t {
CMU_QSPI_CLOCK_SEL_PCLK1 = 0x0U, CMU_QSPI_CLOCK_SEL_HCLK2 = 0x1U, CMU_QSPI_CLOCK_SEL_HRC = 0x2U, CMU_QSPI_CLOCK_SEL_HOSC = 0x3U,
CMU_QSPI_CLOCK_SEL_PLL1 = 0x4U, CMU_QSPI_CLOCK_SEL_HOSM = 0x5U
}
QSPI clock select. More...
enum cmu_usb_clock_sel_t {
CMU_USB_CLOCK_SEL_HOSC = 0x0U, CMU_USB_CLOCK_SEL_HRC = 0x1U, CMU_USB_CLOCK_SEL_PCLK1 = 0x2U, CMU_USB_CLOCK_SEL_PLL1 = 0x3U,
CMU_USB_CLOCK_SEL_HOSM = 0x4U
}
USB clock select. More...
enum cmu_usb_div_t {
CMU_USB_DIV_1 = 0x0U, CMU_USB_DIV_2 = 0x1U, CMU_USB_DIV_4 = 0x2U, CMU_USB_DIV_8 = 0x3U,
CMU_USB_DIV_16 = 0x4U, CMU_USB_DIV_32 = 0x5U, CMU_USB_DIV_64 = 0x6U, CMU_USB_DIV_128 = 0x7U,
CMU_USB_DIV_256 = 0x8U, CMU_USB_DIV_512 = 0x9U, CMU_USB_DIV_1024 = 0xAU, CMU_USB_DIV_2048 = 0xBU,
CMU_USB_DIV_4096 = 0xCU
}
USB clock division. More...
enum cmu_perh_t {
CMU_PERH_GPIO = (1U << 0), CMU_PERH_CRC = (1U << 1), CMU_PERH_CALC = (1U << 2), CMU_PERH_CRYPT = (1U << 3),
CMU_PERH_TRNG = (1U << 4), CMU_PERH_PIS = (1U << 5), CMU_PERH_EBI = (1U << 6), CMU_PERH_QSPI_H = (1U << 7),
CMU_PERH_DMA = (1U << 8), CMU_PERH_USB = (1U << 10), CMU_PERH_ECC = (1U << 11), CMU_PERH_TIMER0 = (1U << 0) | (1U << 27),
CMU_PERH_TIMER1 = (1U << 1) | (1U << 27), CMU_PERH_TIMER2 = (1U << 2) | (1U << 27), CMU_PERH_TIMER3 = (1U << 3) | (1U << 27), CMU_PERH_TIMER4 = (1U << 4) | (1U << 27),
CMU_PERH_TIMER5 = (1U << 5) | (1U << 27), CMU_PERH_TIMER6 = (1U << 6) | (1U << 27), CMU_PERH_TIMER7 = (1U << 7) | (1U << 27), CMU_PERH_UART0 = (1U << 8) | (1U << 27),
CMU_PERH_UART1 = (1U << 9) | (1U << 27), CMU_PERH_UART2 = (1U << 10) | (1U << 27), CMU_PERH_UART3 = (1U << 11) | (1U << 27), CMU_PERH_UART4 = (1U << 12) | (1U << 27),
CMU_PERH_UART5 = (1U << 13) | (1U << 27), CMU_PERH_SPI0 = (1U << 16) | (1U << 27), CMU_PERH_SPI1 = (1U << 17) | (1U << 27), CMU_PERH_SPI2 = (1U << 18) | (1U << 27),
CMU_PERH_I2C0 = (1U << 20) | (1U << 27), CMU_PERH_I2C1 = (1U << 21) | (1U << 27), CMU_PERH_CAN = (1U << 24) | (1U << 27), CMU_PERH_QSPI_P = (1U << 25) | (1U << 27),
CMU_PERH_LPTIM0 = (1U << 0) | (1U << 28), CMU_PERH_LPUART0 = (1U << 2) | (1U << 28), CMU_PERH_ADC0 = (1U << 4) | (1U << 28), CMU_PERH_ADC1 = (1U << 5) | (1U << 28),
CMU_PERH_ACMP0 = (1U << 6) | (1U << 28), CMU_PERH_ACMP1 = (1U << 7) | (1U << 28), CMU_PERH_OPAMP = (1U << 8) | (1U << 28), CMU_PERH_DAC0 = (1U << 9) | (1U << 28),
CMU_PERH_ACMP2 = (1U << 11) | (1U << 28), CMU_PERH_WWDT = (1U << 12) | (1U << 28), CMU_PERH_LCD = (1U << 13) | (1U << 28), CMU_PERH_IWDT = (1U << 14) | (1U << 28),
CMU_PERH_RTC = (1U << 15) | (1U << 28), CMU_PERH_TSENSE = (1U << 16) | (1U << 28), CMU_PERH_BKPC = (1U << 17) | (1U << 28), CMU_PERH_DBGC = (1U << 19) | (1U << 28),
CMU_PERH_ALL = (0x7FFFFFFFU)
}
Peripheral clock enable/disable. More...
enum cmu_security_t {
CMU_LOSC_STOP = 0x0U, CMU_HOSC_STOP = 0x1U, CMU_PLL1_UNLOCK = 0x2U, CMU_LOSC_START = 0x3U,
CMU_HOSC_START = 0x4U
}
CMU interrupt type. More...
enum cmu_clock_state_t {
CMU_CLOCK_STATE_HOSCACT = (1U << 0), CMU_CLOCK_STATE_LOSCACT = (1U << 1), CMU_CLOCK_STATE_HRCACT = (1U << 2), CMU_CLOCK_STATE_LRCACT = (1U << 3),
CMU_CLOCK_STATE_ULRCACT = (1U << 4), CMU_CLOCK_STATE_PLL1ACT = (1U << 8), CMU_CLOCK_STATE_PLL2ACT = (1U << 9), CMU_CLOCK_STATE_HOSCRDY = (1U << 16),
CMU_CLOCK_STATE_LOSCRDY = (1U << 17), CMU_CLOCK_STATE_HRCRDY = (1U << 18), CMU_CLOCK_STATE_LRCRDY = (1U << 19), CMU_CLOCK_STATE_PLL1RDY = (1U << 24),
CMU_CLOCK_STATE_PLL2RDY = (1U << 25)
}
CMU clock state type. More...
enum cmu_stop1_clock_t {
CMU_STOP1_CLOCK_LRC = 0x0U, CMU_STOP1_CLOCK_HRC_24M = 0x1U, CMU_STOP1_CLOCK_HRC_2M = 0x2U, CMU_STOP1_CLOCK_HRC_1M = 0x3U,
CMU_STOP1_CLOCK_HOSC = 0x4U, CMU_STOP1_CLOCK_HOSC_1M = 0x5U, CMU_STOP1_CLOCK_HOSCM = 0x6U
}
Stop1 clock select type. More...

Functions

ald_status_t | ald_cmu_clock_config_default (void)
Configure system clock using default. Select CMU_CLOCK_HRC(24MHz) as system clock and enable CMU_CLOCK_LRC(32768Hz). More...
ald_status_t | ald_cmu_clock_config (cmu_clock_t clk, uint32_t clock)
Configure system clock using specified parameters. More...
void | ald_cmu_pll1_config (cmu_pll1_input_t input, cmu_pll1_output_t output)
Configure PLL1 using specified parameters. More...
uint32_t | ald_cmu_get_clock (void)
Gets current system clock. More...
void | ald_cmu_div_config (cmu_bus_t bus, cmu_div_t div)
Configure the bus division. More...
uint32_t | ald_cmu_get_hclk1_clock (void)
Get AHB1 clock. More...
uint32_t | ald_cmu_get_hclk2_clock (void)
Get AHB2 clock. More...
uint32_t | ald_cmu_get_sys_clock (void)
Get SYS clock. More...
uint32_t | ald_cmu_get_pclk1_clock (void)
Get APB1 clock. More...
uint32_t | ald_cmu_get_pclk2_clock (void)
Get APB2 clock. More...
void | ald_cmu_hosc_safe_config (cmu_hosc_range_t clock, type_func_t status)
Enable/Disable outer high crystal safe mode. More...
void | ald_cmu_losc_safe_config (type_func_t status)
Enable/Disable outer low crystal safe mode. More...
void | ald_cmu_pll_safe_config (type_func_t status)
Enable/Disable PLL1 safe mode. More...
uint32_t | ald_cmu_current_clock_source_get (cmu_clock_safe_type_t type)
Get current clock source. More...
flag_status_t | ald_cmu_get_clock_state (cmu_clock_state_t sr)
Get clock state. More...
void | ald_cmu_irq_handler (void)
CMU module interrupt handler. More...
__weak void | ald_cmu_irq_cbk (cmu_security_t se)
Interrupt callback function. More...
void | ald_cmu_output_high_clock_config (cmu_output_high_sel_t sel, cmu_output_high_div_t div, type_func_t status)
Configure the high-speed clock output. More...
void | ald_cmu_output_low_clock_config (cmu_output_low_sel_t sel, type_func_t status)
Configure the low-speed clock output. More...
void | ald_cmu_buzz_config (cmu_buzz_div_t div, uint16_t dat, type_func_t status)
Configure buzz clock. freq = sysclk / (2^(div + 1) * (dat + 1)) More...
void | ald_cmu_lptim0_clock_select (cmu_lp_perh_clock_sel_t clock)
Select lptim0 clock source. More...
void | ald_cmu_lpuart0_clock_select (cmu_lp_perh_clock_sel_t clock)
Select lpuart0 clock source. More...
void | ald_cmu_lcd_clock_select (cmu_lcd_clock_sel_t clock)
Select lcd clock source. More...
void | ald_cmu_qspi_clock_select (cmu_qspi_clock_sel_t clock)
Select QSPI clock source. More...
void | ald_cmu_usb_clock_config (cmu_usb_clock_sel_t clock, cmu_usb_div_t div)
Configure USB clock source. More...
void | ald_cmu_perh_clock_config (cmu_perh_t perh, type_func_t status)
Enable/Disable peripheral clock. More...
void | ald_cmu_stop1_clock_sel (cmu_stop1_clock_t clock)
Select stop1 clock. More...

Detailed Description

Header file of CMU module driver.

Version
V1.0
Date
22 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_cmu.h.


ALD User Manual: D:/svn/src/ald_conf.h File Reference

  • D:
  • svn
  • src
Macros
ald_conf.h File Reference

Enable/Disable the peripheral module. More...

This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | ALD_DMA
#define | ALD_GPIO
#define | ALD_UART
#define | ALD_LPUART
#define | ALD_I2C
#define | ALD_CMU
#define | ALD_RMU
#define | ALD_PMU
#define | ALD_WDT
#define | ALD_LCD
#define | ALD_RTC
#define | ALD_CAN
#define | ALD_FLASH
#define | ALD_ADC
#define | ALD_CRC
#define | ALD_CRYPT
#define | ALD_TIMER
#define | ALD_LPTIM
#define | ALD_PIS
#define | ALD_SPI
#define | ALD_CALC
#define | ALD_ACMP
#define | ALD_OPAMP
#define | ALD_TRNG
#define | ALD_TSENSE
#define | ALD_BKPC
#define | ALD_DAC
#define | ALD_IAP
#define | ALD_I2S
#define | ALD_ECC
#define | ALD_NAND
#define | ALD_QSPI
#define | ALD_NOR
#define | ALD_SRAM
#define | ALD_USB
#define | ALD_EBI
#define | TICK_INT_PRIORITY 3

Detailed Description

Enable/Disable the peripheral module.

Version
V1.0
Date
01 Jul 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_conf.h.

Macro Definition Documentation

◆ ALD_ACMP

#define ALD_ACMP

Definition at line 43 of file ald_conf.h.

◆ ALD_ADC

#define ALD_ADC

Definition at line 35 of file ald_conf.h.

◆ ALD_BKPC

#define ALD_BKPC

Definition at line 47 of file ald_conf.h.

◆ ALD_CALC

#define ALD_CALC

Definition at line 42 of file ald_conf.h.

◆ ALD_CAN

#define ALD_CAN

Definition at line 33 of file ald_conf.h.

◆ ALD_CMU

#define ALD_CMU

Definition at line 27 of file ald_conf.h.

◆ ALD_CRC

#define ALD_CRC

Definition at line 36 of file ald_conf.h.

◆ ALD_CRYPT

#define ALD_CRYPT

Definition at line 37 of file ald_conf.h.

◆ ALD_DAC

#define ALD_DAC

Definition at line 48 of file ald_conf.h.

◆ ALD_DMA

#define ALD_DMA

Definition at line 22 of file ald_conf.h.

◆ ALD_EBI

#define ALD_EBI

Definition at line 59 of file ald_conf.h.

◆ ALD_ECC

#define ALD_ECC

Definition at line 51 of file ald_conf.h.

◆ ALD_FLASH

#define ALD_FLASH

Definition at line 34 of file ald_conf.h.

◆ ALD_GPIO

#define ALD_GPIO

Definition at line 23 of file ald_conf.h.

◆ ALD_I2C

#define ALD_I2C

Definition at line 26 of file ald_conf.h.

◆ ALD_I2S

#define ALD_I2S

Definition at line 50 of file ald_conf.h.

◆ ALD_IAP

#define ALD_IAP

Definition at line 49 of file ald_conf.h.

◆ ALD_LCD

#define ALD_LCD

Definition at line 31 of file ald_conf.h.

◆ ALD_LPTIM

#define ALD_LPTIM

Definition at line 39 of file ald_conf.h.

◆ ALD_LPUART

#define ALD_LPUART

Definition at line 25 of file ald_conf.h.

◆ ALD_NAND

#define ALD_NAND

Definition at line 52 of file ald_conf.h.

◆ ALD_NOR

#define ALD_NOR

Definition at line 54 of file ald_conf.h.

◆ ALD_OPAMP

#define ALD_OPAMP

Definition at line 44 of file ald_conf.h.

◆ ALD_PIS

#define ALD_PIS

Definition at line 40 of file ald_conf.h.

◆ ALD_PMU

#define ALD_PMU

Definition at line 29 of file ald_conf.h.

◆ ALD_QSPI

#define ALD_QSPI

Definition at line 53 of file ald_conf.h.

◆ ALD_RMU

#define ALD_RMU

Definition at line 28 of file ald_conf.h.

◆ ALD_RTC

#define ALD_RTC

Definition at line 32 of file ald_conf.h.

◆ ALD_SPI

#define ALD_SPI

Definition at line 41 of file ald_conf.h.

◆ ALD_SRAM

#define ALD_SRAM

Definition at line 55 of file ald_conf.h.

◆ ALD_TIMER

#define ALD_TIMER

Definition at line 38 of file ald_conf.h.

◆ ALD_TRNG

#define ALD_TRNG

Definition at line 45 of file ald_conf.h.

◆ ALD_TSENSE

#define ALD_TSENSE

Definition at line 46 of file ald_conf.h.

◆ ALD_UART

#define ALD_UART

Definition at line 24 of file ald_conf.h.

◆ ALD_USB

#define ALD_USB

Definition at line 56 of file ald_conf.h.

◆ ALD_WDT

#define ALD_WDT

Definition at line 30 of file ald_conf.h.

◆ TICK_INT_PRIORITY

#define TICK_INT_PRIORITY 3

Definition at line 62 of file ald_conf.h.


ALD User Manual: D:/svn/src/ald_crc.c File Reference

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  • svn
  • src
Functions
ald_crc.c File Reference

CRC module driver. More...

#include "ald_crc.h"
Include dependency graph for ald_crc.c:

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Functions

void | ald_crc_reset (crc_handle_t *hperh)
Reset the CRC peripheral. More...
static void | crc_dma_calculate_cplt (void *arg)
DMA CRC calculate process complete callback. More...
static void | crc_dma_error (void *arg)
DMA CRC communication error callback. More...
ald_status_t | ald_crc_init (crc_handle_t *hperh)
Initializes the CRC mode according to the specified parameters in the crc_handle_t and create the associated handle. More...
uint32_t | ald_crc_calculate (crc_handle_t *hperh, uint8_t *buf, uint32_t size)
Calculate the crc value of data by byte. More...
uint32_t | ald_crc_calculate_halfword (crc_handle_t *hperh, uint16_t *buf, uint32_t size)
Calculate the crc value of data by halfword. More...
uint32_t | ald_crc_calculate_word (crc_handle_t *hperh, uint32_t *buf, uint32_t size)
Calculate the crc value of data by word. More...
ald_status_t | ald_crc_calculate_by_dma (crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
Calculate an amount of data used dma channel. More...
ald_status_t | ald_crc_calculate_halfword_by_dma (crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
Calculate an amount of data used dma channel,data width is half-word. More...
ald_status_t | ald_crc_calculate_word_by_dma (crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
Calculate an amount of data used dma channel,data width is word. More...
ald_status_t | ald_crc_dma_pause (crc_handle_t *hperh)
Pauses the DMA Transfer. More...
ald_status_t | ald_crc_dma_resume (crc_handle_t *hperh)
Resumes the DMA Transfer. More...
ald_status_t | ald_crc_dma_stop (crc_handle_t *hperh)
Stops the DMA Transfer. More...
crc_state_t | ald_crc_get_state (crc_handle_t *hperh)
Returns the CRC state. More...

Detailed Description

CRC module driver.

Version
V1.0
Date
18 Jun 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_crc.c.


ALD User Manual: D:/svn/src/ald_crc.h File Reference

  • D:
  • svn
  • src
Data Structures | Macros | Typedefs | Enumerations | Functions
ald_crc.h File Reference

Header file of CRC module driver. More...

#include "utils.h"
#include "ald_dma.h"
Include dependency graph for ald_crc.h:
This graph shows which files directly or indirectly include this file:

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Data Structures

struct | crc_init_t
CRC init structure definition. More...
struct | crc_handle_s
CRC Handle Structure definition. More...

Macros

#define | CRC_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
#define | CRC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
#define | CRC_RESET(handle) (SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK))
#define | CRC_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
#define | CRC_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
#define | CRC_CLEAR_ERROR_FLAG(handle) (SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK))
#define | IS_CRC(x) ((x) == CRC)
#define | IS_CRC_MODE(x)

Typedefs

typedef struct crc_handle_s crc_handle_t
CRC Handle Structure definition. More...

Enumerations

enum | crc_mode_t { CRC_MODE_CCITT = 0U, CRC_MODE_8 = 1U, CRC_MODE_16 = 2U, CRC_MODE_32 = 3U }
CRC mode. More...
enum | crc_datasize_t { CRC_LEN_AUTO = 0U, CRC_DATASIZE_8 = 1U, CRC_DATASIZE_16 = 2U, CRC_DATASIZE_32 = 3U }
CRC input length. More...
enum | crc_werr_t { CRC_WERR_NO = 0U, CRC_WERR_ERR = 1U }
CRC whether write error or no. More...
enum | crc_state_t { CRC_STATE_RESET = 0x0U, CRC_STATE_READY = 0x1U, CRC_STATE_BUSY = 0x2U, CRC_STATE_ERROR = 0x4U }
CRC state structures definition. More...

Functions

ald_status_t | ald_crc_init (crc_handle_t *hperh)
Initializes the CRC mode according to the specified parameters in the crc_handle_t and create the associated handle. More...
void | ald_crc_reset (crc_handle_t *hperh)
Reset the CRC peripheral. More...
uint32_t | ald_crc_calculate (crc_handle_t *hperh, uint8_t *buf, uint32_t size)
Calculate the crc value of data by byte. More...
uint32_t | ald_crc_calculate_halfword (crc_handle_t *hperh, uint16_t *buf, uint32_t size)
Calculate the crc value of data by halfword. More...
uint32_t | ald_crc_calculate_word (crc_handle_t *hperh, uint32_t *buf, uint32_t size)
Calculate the crc value of data by word. More...
ald_status_t | ald_crc_calculate_by_dma (crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
Calculate an amount of data used dma channel. More...
ald_status_t | ald_crc_calculate_halfword_by_dma (crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
Calculate an amount of data used dma channel,data width is half-word. More...
ald_status_t | ald_crc_calculate_word_by_dma (crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
Calculate an amount of data used dma channel,data width is word. More...
ald_status_t | ald_crc_dma_pause (crc_handle_t *hperh)
Pauses the DMA Transfer. More...
ald_status_t | ald_crc_dma_resume (crc_handle_t *hperh)
Resumes the DMA Transfer. More...
ald_status_t | ald_crc_dma_stop (crc_handle_t *hperh)
Stops the DMA Transfer. More...
crc_state_t | ald_crc_get_state (crc_handle_t *hperh)
Returns the CRC state. More...

Detailed Description

Header file of CRC module driver.

Version
V1.0
Date
18 Jun 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_crc.h.


ALD User Manual: D:/svn/src/ald_crypt.c File Reference

  • D:
  • svn
  • src
Functions
ald_crypt.c File Reference

CRYPT module driver. This is the common part of the CRYPT initialization. More...

#include "ald_crypt.h"
Include dependency graph for ald_crypt.c:

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Functions

void | crypt_reset (crypt_handle_t *hperh)
Reset the CRYPT peripheral. More...
static void | crypt_dma_crypt_cplt (void *arg)
DMA CRYPT encrypt or decrypt process complete callback. More...
static void | crypt_dma_error (void *arg)
DMA CRYPT communication error callback. More...
ald_status_t | ald_crypt_init (crypt_handle_t *hperh)
Initializes the CRYPT mode according to the specified parameters in the crypt_init_t and create the associated handle. More...
ald_status_t | ald_crypt_write_key (crypt_handle_t *hperh, uint32_t *key, crypt_key_len_t len)
Write the Content of KEY. More...
ald_status_t | ald_crypt_read_key (crypt_handle_t *hperh, uint32_t *key, crypt_key_len_t len)
Read the Content of KEY. More...
ald_status_t | ald_crypt_write_ivr (crypt_handle_t *hperh, uint32_t *iv, crypt_ivr_len_t len)
Write the Content of IV if you use CBC mode. More...
ald_status_t | ald_crypt_read_ivr (crypt_handle_t *hperh, uint32_t *iv, crypt_ivr_len_t len)
Read the Content of IV. More...
ald_status_t | ald_crypt_encrypt (crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size)
Encrypt an amount of data in blocking mode. More...
ald_status_t | ald_crypt_decrypt (crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size)
Decrypt an amount of data in blocking mode. More...
void | gcm_mul (uint32_t *res, uint32_t *data, uint32_t *iv)
ald_status_t | ald_crypt_gcm_verify (crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag)
verify an amount of data in gcm mode. More...
ald_status_t | ald_crypt_encrypt_by_it (crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size)
Encrypt an amount of data in non-blocking mode. More...
ald_status_t | ald_crypt_decrypt_by_it (crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size)
Decrypt an amount of data in non-blocking mode. More...
ald_status_t | ald_crypt_encrypt_by_dma (crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m)
Encrypt an amount of data in non-blocking mode. More...
ald_status_t | ald_crypt_decrypt_by_dma (crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m)
Decrypt an amount of data in non-blocking mode. More...
ald_status_t | ald_crypt_dma_pause (crypt_handle_t *hperh)
Pauses the DMA Transfer. More...
ald_status_t | ald_crypt_dma_resume (crypt_handle_t *hperh)
Resumes the DMA Transfer. More...
ald_status_t | ald_crypt_dma_stop (crypt_handle_t *hperh)
Stops the DMA Transfer. More...
void | ald_crypt_irq_handler (crypt_handle_t *hperh)
This function handles CRYPT interrupt request. More...
void | ald_crypt_interrupt_config (crypt_handle_t *hperh, crypt_it_t it, type_func_t state)
Enables or disables the specified CRYPT interrupts. More...
flag_status_t | ald_crypt_get_flag_status (crypt_handle_t *hperh, crypt_flag_t flag)
Check whether the specified CRYPT flag is set or not. More...
void | ald_crypt_clear_flag_status (crypt_handle_t *hperh, crypt_flag_t flag)
Clear the specified CRYPT pending flags. More...
it_status_t | ald_crypt_get_it_status (crypt_handle_t *hperh, crypt_it_t it)
Checks whether the specified CRYPT interrupt has occurred or not. More...
crypt_state_t | ald_crypt_get_state (crypt_handle_t *hperh)
Returns the CRYPT state. More...

Detailed Description

CRYPT module driver. This is the common part of the CRYPT initialization.

Version
V1.0
Date
19 Jun 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_crypt.c.


ALD User Manual: D:/svn/src/ald_crypt.h File Reference

  • D:
  • svn
  • src
Data Structures | Macros | Typedefs | Enumerations | Functions
ald_crypt.h File Reference

Header file of CRYPT module driver. More...

#include "utils.h"
#include "ald_dma.h"
Include dependency graph for ald_crypt.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Data Structures

struct | crypt_init_t
CRYPT init structure definition. More...
struct | crypt_handle_s
CRYPT Handle Structure definition. More...

Macros

#define | CRYPT_GO(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK))
#define | CRYPT_FIFOEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
#define | CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
#define | CRYPT_IVEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
#define | CRYPT_IVEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
#define | CRYPT_IE_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK))
#define | CRYPT_IE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK))
#define | CRYPT_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))
#define | CRYPT_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))
#define | CRYPT_SETDIR(handle, dir)
#define | CRYPT_WRITE_FIFO(handle, data) ((handle)->perh->FIFO = (data))
#define | CRYPT_READ_FIFO(handle) ((handle)->perh->FIFO)
#define | IS_CRYPT(x) ((x) == CRYPT)
#define | IS_CRYPT_MODE(x)
#define | IS_CRYPT_KS(x)
#define | IS_CRYPT_IT(x) ((x) == CRYPT_IT_IT)
#define | IS_CRYPT_FLAG(x)
#define | IS_CRYPT_IV_LEN(x)
#define | IS_CRYPT_KEY_LEN(x)

Typedefs

typedef struct crypt_handle_s crypt_handle_t
CRYPT Handle Structure definition. More...

Enumerations

enum | crypt_encs_t { CRYPT_DECRYPT = 0U, CRYPT_ENCRYPT = 1U }
CRYPT encrypt or decrypt select. More...
enum | crypt_aesks_t { CRYPT_BITS_128 = 0U, CRYPT_BITS_192 = 1U, CRYPT_BITS_256 = 2U }
CRYPT aes key select. More...
enum | crypt_mode_t { CRYPT_MODE_ECB = 0U, CRYPT_MODE_CBC = 1U, CRYPT_MODE_CTR = 2U }
CRYPT mode select. More...
enum | crypt_datatype_t { CRYPT_DATA_CHANGE_NO = 0U, CRYPT_DATA_CHANGE_16 = 1U, CRYPT_DATA_CHANGE_8 = 2U, CRYPT_DATA_CHANGE_1 = 3U }
CRYPT data type. More...
enum | crypt_desks_t { CRYPT_KEYS_2 = 0U, CRYPT_KEYS_3 = 1U, CRYPT_KEYS_1 = 2U }
CRYPT des key select. More...
enum | crypt_crysel_t { CRYPT_CRYSEL_AES = 0U, CRYPT_CRYSEL_DES = 1U }
CRYPT crypt select. More...
enum | crypt_it_t { CRYPT_IT_IT = 0x80U }
CRYPT interrupt. More...
enum | crypt_flag_t { CRYPT_FLAG_AESIF = 0x1U, CRYPT_FLAG_DESIF = 0x2U, CRYPT_FLAG_DONE = 0x100U }
CRYPT interrupt flag. More...
enum crypt_ks_t {
CRYPT_AES_BITS_128 = 0x4U, CRYPT_AES_BITS_192 = 0x6U, CRYPT_AES_BITS_256 = 0x8U, CRYPT_DES_KEYS_1 = 0x12U,
CRYPT_DES_KEYS_2 = 0x14U, CRYPT_DES_KEYS_3 = 0x16U
}
CRYPT key select. More...
enum | crypt_state_t { CRYPT_STATE_RESET = 0x0U, CRYPT_STATE_READY = 0x1U, CRYPT_STATE_BUSY = 0x2U, CRYPT_STATE_ERROR = 0x4U }
CRYPT state structures definition. More...
enum | crypt_key_len_t { KEY_2_LEN = 2U, KEY_4_LEN = 4U, KEY_6_LEN = 6U, KEY_8_LEN = 8U }
CRYPT key length. More...
enum | crypt_ivr_len_t { IV_2_LEN = 2U, IV_4_LEN = 4U }
CRYPT iv length. More...
enum | crypt_data_t { DATA_32_BIT = 0U, DATA_16_BIT = 1U, DATA_8_BIT = 2U, DATA_1_BIT = 3U }
CRYPT data type. More...

Functions

ald_status_t | ald_crypt_init (crypt_handle_t *hperh)
Initializes the CRYPT mode according to the specified parameters in the crypt_init_t and create the associated handle. More...
ald_status_t | ald_crypt_write_key (crypt_handle_t *hperh, uint32_t *key, crypt_key_len_t len)
Write the Content of KEY. More...
ald_status_t | ald_crypt_read_key (crypt_handle_t *hperh, uint32_t *key, crypt_key_len_t len)
Read the Content of KEY. More...
ald_status_t | ald_crypt_write_ivr (crypt_handle_t *hperh, uint32_t *iv, crypt_ivr_len_t len)
Write the Content of IV if you use CBC mode. More...
ald_status_t | ald_crypt_read_ivr (crypt_handle_t *hperh, uint32_t *iv, crypt_ivr_len_t len)
Read the Content of IV. More...
ald_status_t | ald_crypt_encrypt (crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size)
Encrypt an amount of data in blocking mode. More...
ald_status_t | ald_crypt_decrypt (crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size)
Decrypt an amount of data in blocking mode. More...
ald_status_t | ald_crypt_gcm_verify (crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag)
verify an amount of data in gcm mode. More...
ald_status_t | ald_crypt_encrypt_by_it (crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size)
Encrypt an amount of data in non-blocking mode. More...
ald_status_t | ald_crypt_decrypt_by_it (crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size)
Decrypt an amount of data in non-blocking mode. More...
ald_status_t | ald_crypt_encrypt_by_dma (crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m)
Encrypt an amount of data in non-blocking mode. More...
ald_status_t | ald_crypt_decrypt_by_dma (crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m)
Decrypt an amount of data in non-blocking mode. More...
ald_status_t | ald_crypt_dma_pause (crypt_handle_t *hperh)
Pauses the DMA Transfer. More...
ald_status_t | ald_crypt_dma_resume (crypt_handle_t *hperh)
Resumes the DMA Transfer. More...
ald_status_t | ald_crypt_dma_stop (crypt_handle_t *hperh)
Stops the DMA Transfer. More...
void | ald_crypt_irq_handler (crypt_handle_t *hperh)
This function handles CRYPT interrupt request. More...
void | ald_crypt_interrupt_config (crypt_handle_t *hperh, crypt_it_t it, type_func_t state)
Enables or disables the specified CRYPT interrupts. More...
flag_status_t | ald_crypt_get_flag_status (crypt_handle_t *hperh, crypt_flag_t flag)
Check whether the specified CRYPT flag is set or not. More...
void | ald_crypt_clear_flag_status (crypt_handle_t *hperh, crypt_flag_t flag)
Clear the specified CRYPT pending flags. More...
it_status_t | ald_crypt_get_it_status (crypt_handle_t *hperh, crypt_it_t it)
Checks whether the specified CRYPT interrupt has occurred or not. More...
crypt_state_t | ald_crypt_get_state (crypt_handle_t *hperh)
Returns the CRYPT state. More...

Detailed Description

Header file of CRYPT module driver.

Version
V1.0
Date
19 Jun 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_crypt.h.


ALD User Manual: D:/svn/src/ald_dac.c File Reference

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  • svn
  • src
Functions
ald_dac.c File Reference

DAC module driver. More...

#include "ald_dac.h"
Include dependency graph for ald_dac.c:

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Functions

ald_status_t | ald_dac_reset (dac_handle_t *hperh)
Reset the dac mode. More...
ald_status_t | ald_dac_init (dac_handle_t *hperh)
Initializes the DAC peripheral. More...
ald_status_t | ald_dac_channel_config (dac_handle_t *hperh, dac_channel_config_t *config, dac_channel_t ch)
Configure dac channel. More...
void | ald_dac_output_set (dac_handle_t *hperh, dac_channel_t ch, uint32_t value)
Set dac channel output value. More...
flag_status_t | ald_dac_get_status (dac_handle_t *hperh, dac_status_t status)
Checks whether the specified DAC flag is set or not. More...
void | ald_dac_interrupt_config (dac_handle_t *hperh, dac_it_t it, type_func_t state)
Enable or disable the specified interrupt. More...
it_status_t | ald_dac_get_it_status (dac_handle_t *hperh, dac_it_t it)
Get the status of DAC interrupt source. More...
flag_status_t | ald_dac_get_flag_status (dac_handle_t *hperh, dac_flag_t flag)
Checks whether the specified interrupt has occurred or not. More...
flag_status_t | ald_dac_get_mask_flag_status (dac_handle_t *hperh, dac_flag_t flag)
Get the status of interrupt flag and interupt source. More...
void | ald_dac_clear_flag_status (dac_handle_t *hperh, dac_flag_t flag)
Clear interrupt state flag. More...
void | ald_dac_irq_handler (dac_handle_t *hperh)
This function handles DAC event interrupt request. More...

Detailed Description

DAC module driver.

Version
V1.0
Date
28 Jun 2019
Author
AE Team.
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_dac.c.


ALD User Manual: D:/svn/src/ald_dac.h File Reference

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  • src
Data Structures | Macros | Typedefs | Enumerations | Functions
ald_dac.h File Reference

Header file of DAC Module library. More...

#include "utils.h"
#include "ald_dma.h"
#include "ald_pis.h"
Include dependency graph for ald_dac.h:
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Data Structures

struct | dac_init_t
DAC init structure definition. More...
struct | dac_channel_config_t
DAC channel initialize structure definition. More...
struct | dac_handle_s
DAC handle Structure definition. More...

Macros

#define | DAC_CH0_ENABLE() (SET_BIT(DAC0->CH0CTRL, DAC_CH0CTRL_EN_MSK))
#define | DAC_CH1_ENABLE() (SET_BIT(DAC0->CH1CTRL, DAC_CH1CTRL_EN_MSK))
#define | DAC_CH0_DISABLE() (CLEAR_BIT(DAC0->CH0CTRL, DAC_CH0CTRL_EN_MSK))
#define | DAC_CH1_DISABLE() (CLEAR_BIT(DAC0->CH1CTRL, DAC_CH1CTRL_EN_MSK))
#define | DAC_EVENT_CH0_CPLT 0x0
#define | DAC_EVENT_CH1_CPLT 0x1
#define | DAC_EVENT_CH0_UF 0x2
#define | DAC_EVENT_CH1_UF 0x3
#define | IS_DAC_TYPE(x) ((x) == DAC0)
#define | IS_DAC_CONVERT_TYPE(x)
#define | IS_DAC_OUTPUT_TYPE(x)
#define | IS_DAC_NEG_REFRESH_TYPE(x)
#define | IS_DAC_POS_REFRESH_TYPE(x)
#define | IS_DAC_REFRESH_TYPE(x)
#define | IS_DAC_CHANNEL_TYPE(x)
#define | IS_DAC_PRESCALE_TYPE(x)
#define | IS_DAC_INTERRUPT_TYPE(x)
#define | IS_DAC_FLAG_TYPE(x)
#define | IS_DAC_PISSEL_CH_TYPE(x)
#define | IS_DAC_STATUS_TYPE(x)
#define | IS_DAC_TRIGGER_TYPE(x)

Typedefs

typedef struct dac_handle_s dac_handle_t
DAC handle Structure definition. More...

Enumerations

enum | dac_channel_t { DAC_CHANNEL_0 = 1U, DAC_CHANNEL_1 = 2U, DAC_CHANNEL_COMB = 3U }
DAC channel. More...
enum | dac_conv_mode_t { DAC_CONV_MODE_CONTINUOUS = 0U, DAC_CONV_MODE_SAMPLEHOLD = 1U, DAC_CONV_MODE_SAMPLEOFF = 2U }
DAC convert mode. More...
enum | dac_out_mode_t { DAC_OUTPUT_DISABLE = 0U, DAC_OUTPUT_PIN = 1U, DAC_OUTPUT_ADC = 2U, DAC_OUTPUT_PIN_ADC = 3U }
DAC out mode. More...
enum dac_pissel_t {
DAC_PIS_CH_0 = 0U, DAC_PIS_CH_1 = 1U, DAC_PIS_CH_2 = 2U, DAC_PIS_CH_3 = 3U,
DAC_PIS_CH_4 = 4U, DAC_PIS_CH_5 = 5U, DAC_PIS_CH_6 = 6U, DAC_PIS_CH_7 = 7U,
DAC_PIS_CH_8 = 8U, DAC_PIS_CH_9 = 9U, DAC_PIS_CH_10 = 10U, DAC_PIS_CH_11 = 11U
}
DAC pis input channel. More...
enum | dac_neg_ref_t { DAC_NEG_REF_VSS = 0x0U, DAC_NEG_REF_VREFN = 0x1U }
DAC negative reference voltage definition. More...
enum | dac_pos_ref_t { DAC_POS_REF_VDD = 0x0U, DAC_POS_REF_2V = 0x1U, DAC_POS_REF_VREEFP = 0x2U, DAC_POS_REF_VREEFP_BUF = 0x3U }
DAC positive reference voltage definition. More...
enum | dac_refresh_t { DAC_REFRESH_8 = 0U, DAC_REFRESH_16 = 1U, DAC_REFRESH_32 = 2U, DAC_REFRESH_64 = 3U }
Refresh interval select. More...
enum dac_prescale_div_t {
DAC_PRES_DIV_1 = 0U, DAC_PRES_DIV_2 = 1U, DAC_PRES_DIV_4 = 2U, DAC_PRES_DIV_8 = 3U,
DAC_PRES_DIV_16 = 4U, DAC_PRES_DIV_32 = 5U, DAC_PRES_DIV_64 = 6U, DAC_PRES_DIV_128 = 7U
}
DAC prescale. More...
enum | dac_trigger_t { DAC_TRIGGER_BY_DATA = 0U, DAC_TRIGGER_BY_PIS = 1U }
DAC output trigger select. More...
enum | dac_it_t { DAC_IT_CH0 = (1U << 0), DAC_IT_CH1 = (1U << 1), DAC_IT_CH0_UF = (1U << 4), DAC_IT_CH1_UF = (1U << 5) }
DAC interrupt type. More...
enum | dac_flag_t { DAC_FLAG_CH0 = (1U << 0), DAC_FLAG_CH1 = (1U << 1), DAC_FLAG_CH0_UF = (1U << 4), DAC_FLAG_CH1_UF = (1U << 5) }
DAC interrupt flag type. More...
enum | dac_status_t { DAC_CH0_BSY = (1U << 0), DAC_CH1_BSY = (1U << 1) }
DAC state flag. More...

Functions

ald_status_t | ald_dac_reset (dac_handle_t *hperh)
Reset the dac mode. More...
ald_status_t | ald_dac_init (dac_handle_t *hperh)
Initializes the DAC peripheral. More...
ald_status_t | ald_dac_channel_config (dac_handle_t *hperh, dac_channel_config_t *config, dac_channel_t ch)
Configure dac channel. More...
void | ald_dac_output_set (dac_handle_t *hperh, dac_channel_t ch, uint32_t value)
Set dac channel output value. More...
flag_status_t | ald_dac_get_status (dac_handle_t *hperh, dac_status_t status)
Checks whether the specified DAC flag is set or not. More...
void | ald_dac_interrupt_config (dac_handle_t *hperh, dac_it_t it, type_func_t state)
Enable or disable the specified interrupt. More...
it_status_t | ald_dac_get_it_status (dac_handle_t *hperh, dac_it_t it)
Get the status of DAC interrupt source. More...
flag_status_t | ald_dac_get_flag_status (dac_handle_t *hperh, dac_flag_t flag)
Checks whether the specified interrupt has occurred or not. More...
flag_status_t | ald_dac_get_mask_flag_status (dac_handle_t *hperh, dac_flag_t flag)
Get the status of interrupt flag and interupt source. More...
void | ald_dac_clear_flag_status (dac_handle_t *hperh, dac_flag_t flag)
Clear interrupt state flag. More...
void | ald_dac_irq_handler (dac_handle_t *hperh)
This function handles DAC event interrupt request. More...

Detailed Description

Header file of DAC Module library.

Version
V1.0
Date
28 Jun 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_dac.h.


ALD User Manual: D:/svn/src/ald_dbgc.h File Reference

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Enumerations | Functions
ald_dbgc.h File Reference

DEBUGCON module driver. More...

#include "utils.h"
Include dependency graph for ald_dbgc.h:

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Enumerations

enum dbgc_mode_t { DEBC_MODE_SLEEP = (1U << 0), DEBC_MODE_STOP1 = (1U << 1), DEBC_MODE_STOP2 = (1U << 2), DEBC_MODE_STANDBY = (1U << 3) }
Debug mode select. More...
enum dbgc_perh_t {
DEBC_PERH_TIMER0 = (1U << 0), DEBC_PERH_TIMER1 = (1U << 1), DEBC_PERH_TIMER2 = (1U << 2), DEBC_PERH_TIMER3 = (1U << 3),
DEBC_PERH_TIMER4 = (1U << 4), DEBC_PERH_TIMER5 = (1U << 5), DEBC_PERH_TIMER6 = (1U << 6), DEBC_PERH_TIMER7 = (1U << 7),
DEBC_PERH_I2C0 = (1U << 8), DEBC_PERH_I2C1 = (1U << 9), DEBC_PERH_CAN = (1U << 12), DEBC_PERH_LPTIM0 = (1U << 0) | (1U << 16),
DEBC_PERH_IWDT = (1U << 8) | (1U << 16), DEBC_PERH_WWDT = (1U << 9) | (1U << 16), DEBC_PERH_RTC = (1U << 10) | (1U << 16)
}
Debug peripheral select. More...

Functions

__INLINE uint32_t | ald_dbgc_get_rev_id (void)
Gets version. More...
__INLINE uint32_t | ald_dbgc_get_core_id (void)
Gets core id. More...
__INLINE uint32_t | ald_dbgc_get_device_id (void)
Gets device id. More...
__INLINE void | ald_dbgc_mode_config (dbgc_mode_t mode, type_func_t state)
Configures low power debug mode. More...
__INLINE void | ald_dbgc_perh_config (dbgc_perh_t perh, type_func_t state)
Configures peripheral debug mode. More...

Detailed Description

DEBUGCON module driver.

Version
V1.0
Date
04 Jun 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_dbgc.h.


ALD User Manual: D:/svn/src/ald_dma.c File Reference

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  • svn
  • src
Functions | Variables
ald_dma.c File Reference

DMA module driver. More...

#include <string.h>
#include "ald_conf.h"
#include "ald_dma.h"
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Functions

dma_descriptor_t dma0_ctrl_base [28] | __attribute__ ((aligned(512)))
static void | dma_config_base (DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config_t *p)
Configure DMA channel using dma_config_t structure. More...
void | ald_dma_irq_handler (void)
Handle DMA interrupt. More...
void | ald_dma_reset (DMA_TypeDef *DMAx)
Reset the DMA register. More...
void | ald_dma_init (DMA_TypeDef *DMAx)
DMA module initialization, this function is invoked by ald_cmu_init(). More...
void | ald_dma_config_struct (dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t. More...
void | ald_dma_config_sg_alt_desc (dma_descriptor_t *desc, dma_config_t *config, uint8_t memory)
Configure dma_descriptor_t structure using specified parameter. More...
void | ald_dma_config_auto (dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is automatic. This mode is used to carry data from memory to memory. More...
void | ald_dma_restart_auto (dma_handle_t *hperh, void *src, void *dst, uint16_t size)
Restart DMA transmitted. The DMA mode is automatic. The other parameters have not changed except 'size' and 'addr'. More...
void | ald_dma_config_auto_easy (DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, uint8_t channel, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is automatic. This mode is used to carry data from memory to memory. If User want use the dma easily, they can invoke this function. More...
void | ald_dma_config_basic (dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral. More...
void | ald_dma_restart_basic (dma_handle_t *hperh, void *src, void *dst, uint16_t size)
Restart DMA transmitted. The DMA mode is basic. The other parameters have not changed except 'size' and 'addr'. More...
void | ald_dma_config_basic_easy (DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is basic. This mode is used to carry data from peripheral to memory or negative direction. If user want use the dma easily, they can invoke this function. More...
void | ald_dma_config_ping_pong (DMA_TypeDef *DMAx, dma_config_t *config, uint8_t first, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is ping-pong. More...
void | ald_dma_config_sg_mem (DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t channel, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is memory scatter-gather. More...
void | ald_dma_config_sg_per (DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst, dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is peripheral scatter-gather. More...
void | ald_dma_channel_config (DMA_TypeDef *DMAx, uint8_t channel, type_func_t state)
Configure channel enable or disable. It will unbind descriptor with channel, when channel has been disable. More...
void | ald_dma_interrupt_config (DMA_TypeDef *DMAx, uint8_t channel, type_func_t state)
Configure the interrupt enable or disable. More...
it_status_t | ald_dma_get_it_status (DMA_TypeDef *DMAx, uint8_t channel)
Check whether the specified channel interrupt is set or reset. More...
flag_status_t | ald_dma_get_flag_status (DMA_TypeDef *DMAx, uint8_t channel)
Check whether the specified channel flag is set or reset. More...
void | ald_dma_clear_flag_status (DMA_TypeDef *DMAx, uint8_t channel)
Clear the specified channel pending flag. More...
dma_descrp_cplt_t | ald_dma_descriptor_cplt_get (DMA_TypeDef *DMAx, uint8_t channel)
Get the completion status of the descriptor. More...

Variables

dma_call_back_t dma0_cbk [12]

Detailed Description

DMA module driver.

Version
V1.0
Date
09 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

==============================================================================
                      ##### How to use this driver #####
==============================================================================
[..]
  The DMA driver can be used as follows:

  (#) System initialization invokes ald_dma_init(), ald_cmu_init() --> ald_dma_init().

  (#) Declare a dma_handle_t handle structure.

  (#) Configure the dma_handle_t structure, you can configure the
      dma_config_t structure with the help of ald_dma_config_struct().

  (#) Enable the DMA Configure:
      (##) Memory     -- memory: call ald_dma_config_auto().
      (##) Peripheral -- memory: call ald_dma_config_basic().
      (##) If you want use the dma easily, you can do this:
          (+++) Memory     -- memory: call ald_dma_config_auto_easy().
          (+++) Peripheral -- memory: call ald_dma_config_basic_easy().

  (#) Enable the DMA request signal:
      (##) Memory     -- memory: the DMA request signal is request automatic.
      (##) Peripheral -- memory: you need enable peripheral request signal.

  (#) If you enable DMA interrupt, the callback will be invoked:
      (##) When DMA transfer is completed, the cplt_cbk() will be invoked.
      (##) When DMA bus occurs error, the err_cbk() will be invoked.

  (#) If you don't enable the DMA interrupt, you need do this:
      (##) Polling the ald_dma_get_flag_status(), this function's parameter is channel
           or DMA_ERR.
          (+++) When the function's Parameter is channel, if retval is SET, it means
                the DMA transfer is completed. at this moment, you can do something,
          and then, you need invoke ald_dma_clear_flag_status() to clear flag.

          (+++) When the function's Parameter is DMA_ERR, if retval is SET, it means
                the DMA bus occurs error. at this moment, you can do something,
          and then, you need invoke ald_dma_clear_flag_status() to clear flag.

Definition in file ald_dma.c.


ALD User Manual: D:/svn/src/ald_dma.h File Reference

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  • svn
  • src
Data Structures | Macros | Enumerations | Functions
ald_dma.h File Reference

DMA module Library. More...

#include "utils.h"
Include dependency graph for ald_dma.h:
This graph shows which files directly or indirectly include this file:

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Data Structures

union | dma_ctrl_t
DMA Descriptor control type. More...
struct | dma_descriptor_t
Channel control data structure. More...
struct | dma_call_back_t
Callback function pointer and param. More...
struct | dma_config_t
DMA channal configure structure. More...
struct | dma_handle_t
DMA handle structure definition. More...

Macros

#define | DMA_CH_COUNT 12U
#define | DMA_ERR 31U
#define | IS_DMA_MSEL_TYPE(x) ((x) <= DMA_MSEL_USB)
#define | IS_DMA_MSIGSEL_TYPE(x) ((x) <= 0xF)
#define | IS_DMA_DATAINC_TYPE(x)
#define | IS_DMA_DATASIZE_TYPE(x)
#define | IS_CYCLECTRL_TYPE(x)
#define | IS_DMA_ARBITERCONFIG_TYPE(x)
#define | IS_DMA(x) ((x) == DMA0)
#define | IS_DMA_CHANNEL(x) ((x) <= 11)
#define | IS_DMA_DATA_SIZE(x) ((x) <= 1024)
#define | IS_DMA_IT_TYPE(x) (((x) <= 11) || ((x) == 31))

Enumerations

enum dma_msel_t {
DMA_MSEL_NONE = 0x0U, DMA_MSEL_GPIO = 0x1U, DMA_MSEL_CRYPT = 0x2U, DMA_MSEL_DAC0 = 0x4U,
DMA_MSEL_ADC0 = 0x6U, DMA_MSEL_CRC = 0x7U, DMA_MSEL_UART0 = 0x8U, DMA_MSEL_UART1 = 0x9U,
DMA_MSEL_UART2 = 0xAU, DMA_MSEL_UART3 = 0xBU, DMA_MSEL_UART4 = 0xCU, DMA_MSEL_UART5 = 0xDU,
DMA_MSEL_SPI0 = 0xEU, DMA_MSEL_SPI1 = 0xFU, DMA_MSEL_I2C0 = 0x10U, DMA_MSEL_I2C1 = 0x11U,
DMA_MSEL_TIMER0 = 0x12U, DMA_MSEL_TIMER1 = 0x13U, DMA_MSEL_TIMER2 = 0x14U, DMA_MSEL_TIMER3 = 0x15U,
DMA_MSEL_LPUART0 = 0x18U, DMA_MSEL_SPI2 = 0x1AU, DMA_MSEL_TIMER4 = 0x1BU, DMA_MSEL_TIMER5 = 0x1CU,
DMA_MSEL_TIMER6 = 0x1DU, DMA_MSEL_TIMER7 = 0x1EU, DMA_MSEL_ADC1 = 0x1FU, DMA_MSEL_PIS = 0x20U,
DMA_MSEL_TRNG = 0x21U, DMA_MSEL_QSPI = 0x22U, DMA_MSEL_USB = 0x23U
}
Input source to DMA channel. More...
enum dma_msigsel_t {
DMA_MSIGSEL_NONE = 0x0U, DMA_MSIGSEL_EXTI_0 = 0x0U, DMA_MSIGSEL_EXTI_1 = 0x1U, DMA_MSIGSEL_EXTI_2 = 0x2U,
DMA_MSIGSEL_EXTI_3 = 0x3U, DMA_MSIGSEL_EXTI_4 = 0x4U, DMA_MSIGSEL_EXTI_5 = 0x5U, DMA_MSIGSEL_EXTI_6 = 0x6U,
DMA_MSIGSEL_EXTI_7 = 0x7U, DMA_MSIGSEL_EXTI_8 = 0x8U, DMA_MSIGSEL_EXTI_9 = 0x9U, DMA_MSIGSEL_EXTI_10 = 0xAU,
DMA_MSIGSEL_EXTI_11 = 0xBU, DMA_MSIGSEL_EXTI_12 = 0xCU, DMA_MSIGSEL_EXTI_13 = 0xDU, DMA_MSIGSEL_EXTI_14 = 0xEU,
DMA_MSIGSEL_EXTI_15 = 0xFU, DMA_MSIGSEL_CRYPT_WRITE = 0x0U, DMA_MSIGSEL_CRYPT_READ = 0x1U, DMA_MSIGSEL_DAC0_CH0 = 0x0U,
DMA_MSIGSEL_DAC0_CH1 = 0x1U, DMA_MSIGSEL_ADC = 0x0U, DMA_MSIGSEL_UART_TXEMPTY = 0x0U, DMA_MSIGSEL_UART_RNR = 0x1U,
DMA_MSIGSEL_UART45_RNR = 0x0U, DMA_MSIGSEL_UART45_TXEMPTY = 0x1U, DMA_MSIGSEL_SPI_RNR = 0x0U, DMA_MSIGSEL_SPI_TXEMPTY = 0x1U,
DMA_MSIGSEL_I2C_RNR = 0x0U, DMA_MSIGSEL_I2C_TXEMPTY = 0x1U, DMA_MSIGSEL_TIMER_CH1 = 0x0U, DMA_MSIGSEL_TIMER_CH2 = 0x1U,
DMA_MSIGSEL_TIMER_CH3 = 0x2U, DMA_MSIGSEL_TIMER_CH4 = 0x3U, DMA_MSIGSEL_TIMER_TRI = 0x4U, DMA_MSIGSEL_TIMER_COMP = 0x5U,
DMA_MSIGSEL_TIMER_UPDATE = 0x6U, DMA_MSIGSEL_LPUART_RNR = 0x0U, DMA_MSIGSEL_LPUART_TXEMPTY = 0x1U, DMA_MSIGSEL_PIS_CH0 = 0x0U,
DMA_MSIGSEL_PIS_CH1 = 0x1U, DMA_MSIGSEL_PIS_CH2 = 0x2U, DMA_MSIGSEL_PIS_CH3 = 0x3U, DMA_MSIGSEL_PIS_CH4 = 0x4U,
DMA_MSIGSEL_PIS_CH5 = 0x5U, DMA_MSIGSEL_PIS_CH6 = 0x6U, DMA_MSIGSEL_PIS_CH7 = 0x7U, DMA_MSIGSEL_PIS_CH8 = 0x8U,
DMA_MSIGSEL_PIS_CH9 = 0x9U, DMA_MSIGSEL_PIS_CH10 = 0xAU, DMA_MSIGSEL_PIS_CH11 = 0xBU, DMA_MSIGSEL_PIS_CH12 = 0xCU,
DMA_MSIGSEL_PIS_CH13 = 0xDU, DMA_MSIGSEL_PIS_CH14 = 0xEU, DMA_MSIGSEL_PIS_CH15 = 0xFU, DMA_MSIGSEL_QSPI_WRITE = 0x0U,
DMA_MSIGSEL_QSPI_READ = 0x1U, DMA_MSIGSEL_EP_TX1 = 0x0U, DMA_MSIGSEL_EP_TX2 = 0x1U, DMA_MSIGSEL_EP_TX3 = 0x2U,
DMA_MSIGSEL_EP_TX4 = 0x3U, DMA_MSIGSEL_EP_TX5 = 0x4U, DMA_MSIGSEL_EP_RX1 = 0x8U, DMA_MSIGSEL_EP_RX2 = 0x9U,
DMA_MSIGSEL_EP_RX3 = 0xAU, DMA_MSIGSEL_EP_RX4 = 0xBU, DMA_MSIGSEL_EP_RX5 = 0xCU
}
Input signal to DMA channel. More...
enum | dma_data_inc_t { DMA_DATA_INC_BYTE = 0x0U, DMA_DATA_INC_HALFWORD = 0x1U, DMA_DATA_INC_WORD = 0x2U, DMA_DATA_INC_NONE = 0x3U }
data increment More...
enum | dma_data_size_t { DMA_DATA_SIZE_BYTE = 0x0U, DMA_DATA_SIZE_HALFWORD = 0x1U, DMA_DATA_SIZE_WORD = 0x2U }
Data size. More...
enum dma_cycle_ctrl_t {
DMA_CYCLE_CTRL_NONE = 0x0U, DMA_CYCLE_CTRL_BASIC = 0x1U, DMA_CYCLE_CTRL_AUTO = 0x2U, DMA_CYCLE_CTRL_PINGPONG = 0x3U,
DMA_CYCLE_CTRL_MEM_SG_PRIMARY = 0x4U, DMA_CYCLE_CTRL_MEM_SG_ALTERNATE = 0x5U, DMA_CYCLE_CTRL_PER_SG_PRIMARY = 0x6U, DMA_CYCLE_CTRL_PER_SG_ALTERNATE = 0x7U
}
The operating mode of the DMA cycle. More...
enum dma_arbiter_config_t {
DMA_R_POWER_1 = 0x0U, DMA_R_POWER_2 = 0x1U, DMA_R_POWER_4 = 0x2U, DMA_R_POWER_8 = 0x3U,
DMA_R_POWER_16 = 0x4U, DMA_R_POWER_32 = 0x5U, DMA_R_POWER_64 = 0x6U, DMA_R_POWER_128 = 0x7U,
DMA_R_POWER_256 = 0x8U, DMA_R_POWER_512 = 0x9U, DMA_R_POWER_1024 = 0xAU
}
Control how many DMA transfers can occur before the controller re-arbitrates. More...
enum | dma_descrp_cplt_t { DMA_DESCP_CPLT_PRI = 0x0U, DMA_DESCP_CPLT_ALT = 0x1U, DMA_DESCP_CPLT_ALL = 0x2U }
Descriptor complete state. More...

Functions

void | ald_dma_reset (DMA_TypeDef *DMAx)
Reset the DMA register. More...
void | ald_dma_init (DMA_TypeDef *DMAx)
DMA module initialization, this function is invoked by ald_cmu_init(). More...
void | ald_dma_config_struct (dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t. More...
void | ald_dma_config_sg_alt_desc (dma_descriptor_t *desc, dma_config_t *config, uint8_t memory)
Configure dma_descriptor_t structure using specified parameter. More...
void | ald_dma_config_auto (dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is automatic. This mode is used to carry data from memory to memory. More...
void | ald_dma_restart_auto (dma_handle_t *hperh, void *src, void *dst, uint16_t size)
Restart DMA transmitted. The DMA mode is automatic. The other parameters have not changed except 'size' and 'addr'. More...
void | ald_dma_config_auto_easy (DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, uint8_t channel, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is automatic. This mode is used to carry data from memory to memory. If User want use the dma easily, they can invoke this function. More...
void | ald_dma_config_basic (dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral. More...
void | ald_dma_restart_basic (dma_handle_t *hperh, void *src, void *dst, uint16_t size)
Restart DMA transmitted. The DMA mode is basic. The other parameters have not changed except 'size' and 'addr'. More...
void | ald_dma_config_basic_easy (DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is basic. This mode is used to carry data from peripheral to memory or negative direction. If user want use the dma easily, they can invoke this function. More...
void | ald_dma_config_ping_pong (DMA_TypeDef *DMAx, dma_config_t *config, uint8_t first, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is ping-pong. More...
void | ald_dma_config_sg_mem (DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t channel, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is memory scatter-gather. More...
void | ald_dma_config_sg_per (DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst, dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is peripheral scatter-gather. More...
void | ald_dma_channel_config (DMA_TypeDef *DMAx, uint8_t channel, type_func_t state)
Configure channel enable or disable. It will unbind descriptor with channel, when channel has been disable. More...
void | ald_dma_interrupt_config (DMA_TypeDef *DMAx, uint8_t channel, type_func_t state)
Configure the interrupt enable or disable. More...
it_status_t | ald_dma_get_it_status (DMA_TypeDef *DMAx, uint8_t channel)
Check whether the specified channel interrupt is set or reset. More...
flag_status_t | ald_dma_get_flag_status (DMA_TypeDef *DMAx, uint8_t channel)
Check whether the specified channel flag is set or reset. More...
void | ald_dma_clear_flag_status (DMA_TypeDef *DMAx, uint8_t channel)
Clear the specified channel pending flag. More...
dma_descrp_cplt_t | ald_dma_descriptor_cplt_get (DMA_TypeDef *DMAx, uint8_t channel)
Get the completion status of the descriptor. More...
void | ald_dma_irq_handler (void)
Handle DMA interrupt. More...

Detailed Description

DMA module Library.

Version
V1.0
Date
09 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_dma.h.


ALD User Manual: D:/svn/src/ald_ebi.c File Reference

  • D:
  • svn
  • src
Functions
ald_ebi.c File Reference

EBI module driver. More...

#include "ald_ebi.h"
Include dependency graph for ald_ebi.c:

Go to the source code of this file.

Functions

void | ald_ebi_nor_sram_init (EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_init_t *init)
Initialize the EBI_NOR_SRAM device according to the specified control parameters in the EBI_NOR_SRAM_InitTypeDef. More...
void | ald_ebi_nor_sram_timing_init (EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank)
Initialize the EBI_NOR_SRAM Timing according to the specified parameters in the EBI_NOR_SRAM_TimingTypeDef. More...
void | ald_ebi_nor_sram_ext_timing_init (EBI_NOR_SRAM_EXTENDED_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank, uint32_t mode)
Initialize the EBI_NOR_SRAM Extended mode Timing according to the specified parameters in the EBI_NOR_SRAM_TimingTypeDef. More...
ald_status_t | ald_ebi_nor_sram_deinit (EBI_NOR_SRAM_TypeDef *dev, EBI_NOR_SRAM_EXTENDED_TypeDef *e_dev, uint32_t bank)
DeInitialize the EBI_NOR_SRAM peripheral. More...
void | ald_ebi_nor_sram_enable (EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Enable the NOR/SRAM device access. More...
void | ald_ebi_nor_sram_disable (EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Disable the NORSRAM device access. More...
void | ald_ebi_nor_sram_write_enable (EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Enables dynamically NOR-FLASH/SRAM write operation. More...
void | ald_ebi_nor_sram_write_disable (EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Disables dynamically EBI_NORSRAM write operation. More...
void | ald_ebi_nand_init (EBI_NAND_TypeDef *dev, ald_ebi_nand_init_t *init)
Initializes the EBI_NAND device according to the specified control parameters in the EBI_NAND_HandleTypeDef. More...
void | ald_ebi_nand_comm_timing_init (EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
Initializes the EBI_NAND Common space Timing according to the specified parameters in the EBI_NAND_TimingTypeDef. More...
void | ald_ebi_nand_attr_timing_init (EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
Initializes the EBI_NAND Attribute space Timing according to the specified parameters in the EBI_NAND_TimingTypeDef. More...
void | ald_ebi_nand_deinit (EBI_NAND_TypeDef *dev, uint32_t bank)
DeInitializes the EBI_NAND device. More...
void | ald_ebi_nand_enable (EBI_NAND_TypeDef *dev, uint32_t bank)
Enable the NAND device access. More...
void | ald_ebi_nand_disable (EBI_NAND_TypeDef *dev, uint32_t bank)
Disable the NAND device access. More...
void | ald_ebi_nand_enable_it (EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it)
Enable the NAND device interrupt. More...
void | ald_ebi_nand_disable_it (EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it)
Disable the NAND device interrupt. More...
void | ald_ebi_nand_ecc_enable (EBI_NAND_TypeDef *dev, uint32_t bank)
Enables dynamically EBI_NAND ECC feature. More...
void | ald_ebi_nand_ecc_disable (EBI_NAND_TypeDef *dev, uint32_t bank)
Disables dynamically EBI_NAND ECC feature. More...
ald_status_t | ald_ebi_nand_get_ecc (EBI_NAND_TypeDef *dev, uint32_t *val, uint32_t bank, uint32_t timeout)
Disables dynamically EBI_NAND ECC feature. More...
flag_status_t | ald_ebi_nand_get_flag (EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
Get flag status of the NAND device. More...
void | ald_ebi_nand_clear_flag (EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
Clear flag status of the NAND device. More...
void | ald_ebi_lcd_init (ebi_lcd_handle_t *hlcd)
Initializes the EBI_LCD device according to the specified control parameters in the nor_lcd_handle_t. More...
void | ald_ebi_lcd_reset (ebi_lcd_handle_t *hlcd)
Reset the EBI_LCD. More...

Detailed Description

EBI module driver.

Version
V1.0
Date
20 Jan 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_ebi.c.


ALD User Manual: D:/svn/src/ald_ebi.h File Reference

  • D:
  • svn
  • src
Data Structures | Macros | Enumerations | Functions
ald_ebi.h File Reference

Header file of EBI module driver. More...

#include "utils.h"
Include dependency graph for ald_ebi.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Data Structures

struct | ald_ebi_nor_sram_timing_t
EBI NORSRAM Timing parameters structure definition. More...
struct | ald_ebi_nand_init_t
EBI NAND Configuration Structure definition. More...
struct | ald_ebi_nand_timing_t
EBI NAND Timing parameters structure definition. More...
struct | ebi_lcd_init_t
EBI LCD parameters structure definition. More...
struct | ebi_lcd_handle_t
NOR LCD handle Structure definition. More...
struct | ald_ebi_nor_sram_init_t
EBI NORSRAM Configuration Structure definition. More...

Macros

#define | EBI_NOR_SRAM_TypeDef EBI_Bank1_TypeDef
#define | EBI_NOR_SRAM_EXTENDED_TypeDef EBI_Bank1E_TypeDef
#define | EBI_NAND_TypeDef EBI_Bank2_3_TypeDef
#define | EBI_LCD_TypeDef EBI_Bank1_LCD_TypeDef
#define | EBI_NOR_SRAM_DEVICE EBI_Bank1
#define | EBI_NOR_SRAM_EXTENDED_DEVICE EBI_Bank1E
#define | EBI_NAND_DEVICE EBI_Bank2_3
#define | EBI_LCD_DEVICE EBI_Bank1_LCD
#define | EBI_NAND_BANK2 0x00000010U
#define | EBI_NAND_BANK3 0x00000100U
#define | PCTRLR_CLEAR_MASK
#define | PMEMR_CLEAR_MASK
#define | PATTR_CLEAR_MASK
#define | BCTRLR_CLEAR_MASK
#define | BTR_CLEAR_MASK
#define | BWTR_CLEAR_MASK
#define | LCDCTRL_CLEAR_MASK
#define | IS_EBI_NORSRAM_BANK(x)
#define | IS_EBI_MUX(x)
#define | IS_EBI_MEMORY(x)
#define | IS_EBI_NORSRAM_MEMORY_WIDTH(x)
#define | IS_EBI_WRITE_BURST(x)
#define | IS_EBI_ACCESS_MODE(x)
#define | IS_EBI_NAND_BANK(x)
#define | IS_EBI_WAIT_FEATURE(x)
#define | IS_EBI_NAND_MEMORY_WIDTH(x)
#define | IS_EBI_ECC_STATE(x)
#define | IS_EBI_ECCPAGE_SIZE(x)
#define | IS_EBI_LCD_DEVICE(x) ((x) == EBI_LCD_DEVICE)
#define | IS_EBI_HORIZONTAL_SYNCH(x)
#define | IS_EBI_VERTICAL_SYNCH(x)
#define | IS_EBI_DATA_ENABLE(x)
#define | IS_EBI_LCD_ENABLE(x)
#define | IS_EBI_LCD_RESET(x)
#define | IS_EBI_DATA_CLOCK(x)
#define | IS_EBI_LCD_DATASETUP_TIME(x) ((x) < 255U)
#define | IS_EBI_HYSNC_PULSE_WIDTH(x) ((x) < 255U)
#define | IS_EBI_VSYNC_PULSE_WIDTH(x) ((x) < 255U)
#define | IS_EBI_FRAME_LINE_NUMBER(x) (((x) >= 1U) && ((x) < 65535))
#define | IS_EBI_FRAME_PIXEL_NUMBER(x) (((x) >= 1U) && ((x) < 65535))
#define | IS_EBI_TCLR_TIME(x) ((x) <= 255U)
#define | IS_EBI_TAR_TIME(x) ((x) <= 255U)
#define | IS_EBI_SETUP_TIME(x) ((x) <= 255U)
#define | IS_EBI_WAIT_TIME(x) ((x) <= 255U)
#define | IS_EBI_HOLD_TIME(x) ((x) <= 255U)
#define | IS_EBI_HIZ_TIME(x) ((x) <= 255U)
#define | IS_EBI_NORSRAM_DEVICE(x) ((x) == EBI_NOR_SRAM_DEVICE)
#define | IS_EBI_NORSRAM_EXTENDED_DEVICE(x) ((x) == EBI_NOR_SRAM_EXTENDED_DEVICE)
#define | IS_EBI_NAND_DEVICE(x) ((x) == EBI_NAND_DEVICE)
#define | IS_EBI_BURSTMODE(x)
#define | IS_EBI_WAIT_POLARITY(x)
#define | IS_EBI_WRAP_MODE(x)
#define | IS_EBI_WAIT_SIGNAL_ACTIVE(x)
#define | IS_EBI_WRITE_OPERATION(x)
#define | IS_EBI_WAITE_SIGNAL(x)
#define | IS_EBI_EXTENDED_MODE(x)
#define | IS_EBI_ASYNWAIT(x)
#define | IS_EBI_CLK_DIV(x) (((x) >= 1U) && ((x) <= 16U))
#define | IS_EBI_DATA_LATENCY(x) (((x) >= 1U) && ((x) <= 17U))
#define | IS_EBI_ADDRESS_SETUP_TIME(x) ((x) <= 15U)
#define | IS_EBI_ADDRESS_HOLD_TIME(x) (((x) > 0U) && ((x) <= 15U))
#define | IS_EBI_DATASETUP_TIME(x) (((x) > 0U) && ((x) <= 255U))
#define | IS_EBI_TURNAROUND_TIME(x) ((x) <= 15U)
#define | IS_EBI_BANK_NUMBER(x) (((x) > 0U) && ((x) <= 4U))

Enumerations

enum | ebi_access_mode_t { EBI_ACCESS_MODE_A = 0x0U, EBI_ACCESS_MODE_B = (0x1U << 28), EBI_ACCESS_MODE_C = (0x2U << 28), EBI_ACCESS_MODE_D = (0x3U << 28) }
EBI Access Mode. More...
enum | ebi_nand_wait_feature_t { EBI_NAND_WAIT_FEATURE_DISABLE = 0x0U, EBI_NAND_WAIT_FEATURE_ENABLE = (0x1U << 1) }
EBI_Wait_feature EBI Wait feature. More...
enum | ebi_nand_mem_bus_width_t { EBI_NAND_MEM_BUS_WIDTH_8 = 0x0U, EBI_NAND_MEM_BUS_WIDTH_16 = (0x3U << 4) }
EBI NAND Data Width. More...
enum | ebi_nand_ecc_t { EBI_NAND_ECC_DISABLE = 0U, EBI_NAND_ECC_ENABLE = (0x1U << 6) }
EBI NAND ECC STATE. More...
enum ebi_md_ecc_page_size_t {
EBI_NAND_ECC_PAGE_SIZE_256BYTE = 0U, EBI_NAND_ECC_PAGE_SIZE_512BYTE = (0x1U << 17), EBI_NAND_ECC_PAGE_SIZE_1024BYTE = (0x2U << 17), EBI_NAND_ECC_PAGE_SIZE_2048BYTE = (0x3U << 17),
EBI_NAND_ECC_PAGE_SIZE_4096BYTE = (0x4U << 17), EBI_NAND_ECC_PAGE_SIZE_8192BYTE = (0x5U << 17)
}
EBI ECC Page Size. More...
enum | ebi_data_address_mux_t { EBI_DATA_ADDRESS_MUX_DISABLE = 0x0U, EBI_DATA_ADDRESS_MUX_ENABLE = (0x1U << 1) }
EBI Data Address Bus Multiplexing. More...
enum | ebi_norsram_bank_t { EBI_NORSRAM_BANK1 = 0x0U, EBI_NORSRAM_BANK2 = 0x2U, EBI_NORSRAM_BANK3 = 0x4U, EBI_NORSRAM_BANK4 = 0x6U }
EBI NOR/SRAM Bank. More...
enum | ebi_memory_type_t { EBI_MEMORY_TYPE_SRAM = 0x0U, EBI_MEMORY_TYPE_PSRAM = (0x1U << 2), EBI_MEMORY_TYPE_NOR = (0x2U << 2) }
EBI Memory Type. More...
enum | ebi_norsram_mem_bus_width_t { EBI_NORSRAM_MEM_BUS_WIDTH_8 = 0x0U, EBI_NORSRAM_MEM_BUS_WIDTH_16 = (0x1U << 4), EBI_NORSRAM_MEM_BUS_WIDTH_32 = (0x2U << 4) }
EBI NOR/SRAM Data Width. More...
enum | ebi_norsram_flash_access_t { EBI_NORSRAM_FLASH_ACCESS_DISABLE = 0x0U, EBI_NORSRAM_FLASH_ACCESS_ENABLE = (0x1U << 6) }
EBI NOR/SRAM Flash Access. More...
enum | ebi_burst_access_mode_t { EBI_BURST_ACCESS_MODE_DISABLE = 0x0U, EBI_BURST_ACCESS_MODE_ENABLE = (0x1U << 8) }
EBI Burst Access Mode. More...
enum | ebi_wait_signal_polarity_t { EBI_WAIT_SIGNAL_POLARITY_LOW = 0x0U, EBI_WAIT_SIGNAL_POLARITY_HIGH = (0x1U << 9) }
EBI Wait Signal Polarity. More...
enum | ebi_wrap_mode_t { EBI_WRAP_MODE_DISABLE = 0x0U, EBI_WRAP_MODE_ENABLE = (0x1U << 10) }
EBI Wrap Mode. More...
enum | ebi_wait_timing_t { EBI_WAIT_TIMING_BEFORE_WS = 0x0U, EBI_WAIT_TIMING_DURING_WS = (0x1U << 11) }
EBI Wait Timing. More...
enum | ebi_write_operation_t { EBI_WRITE_OPERATION_DISABLE = 0x0U, EBI_WRITE_OPERATION_ENABLE = (0x1U << 12) }
EBI Write Operation State. More...
enum | ebi_wait_signal_t { EBI_WAIT_SIGNAL_DISABLE = 0x0U, EBI_WAIT_SIGNAL_ENABLE = (0x1U << 13) }
EBI Wait Signal. More...
enum | ebi_extended_mode_t { EBI_EXTENDED_MODE_DISABLE = 0x0U, EBI_EXTENDED_MODE_ENABLE = (0x1U << 14) }
EBI Extended Mode. More...
enum | ebi_asynchronous_wait_t { EBI_ASYNCHRONOUS_WAIT_DISABLE = 0x0U, EBI_ASYNCHRONOUS_WAIT_ENABLE = (0x1U << 15) }
EBI Asynchronous Wait. More...
enum | ebi_write_burst_t { EBI_WRITE_BURST_DISABLE = 0x0U, EBI_WRITE_BURST_ENABLE = (0x1U << 19) }
EBI Write Burst. More...
enum | ebi_pctrlr_memory_type_t { EBI_PCTRLR_MEMORY_TYPE_None = 0x0U, EBI_PCTRLR_MEMORY_TYPE_NAND = (0x1U << 3) }
EBI PCR Memory Type. More...
enum | ebi_it_t { EBI_IT_RISING_EDGE = (1U << 3), EBI_IT_LEVEL = (1U << 4), EBI_IT_FALLING_EDGE = (1U << 5) }
EBI Interrupt definition. More...
enum | ebi_flag_t { EBI_FLAG_RISING_EDGE = (1U << 0), EBI_FLAG_LEVEL = (1U << 1), EBI_FLAG_FALLING_EDGE = (1U << 2), EBI_FLAG_FEMPT = (1U << 6) }
EBI Flag definition. More...
enum | ebi_lcd_hsyncpol_t { EBI_LCD_HSYNCPOL_LOW = 0x0U, EBI_LCD_HSYNCPOL_HIGH = (0x1U << 29) }
EBI LCD_Horizontal Synch Polarity definition. More...
enum | ebi_lcd_vsyncpol_t { EBI_LCD_VSYNCPOL_LOW = 0x0U, EBI_LCD_VSYNCPOL_HIGH = (0x1U << 28) }
EBI LCD Vertical Synch Polarity definition. More...
enum | ebi_lcd_denpol_t { EBI_LCD_DENPOL_LOW = 0x0U, EBI_LCD_DENPOL_HIGH = (0x1U << 27) }
EBI LCD Data Enable Polarity definition. More...
enum | ebi_lcd_lcden_t { EBI_LCD_LCDEN_DISABLE = 0x0U, EBI_LCD_LCDEN_ENABLE = (0x1U << 26) }
EBI LCD Enable definition. More...
enum | ebi_lcd_lcdint_t { EBI_LCD_LCDINT_DISABLE = 0x0U, EBI_LCD_LCDINT_ENABLE = (0x1 << 25) }
EBI LCD Init Enable definition. More...
enum | ebi_lcd_dclkpol_t { EBI_LCD_DCLKPOL_FALLING = 0x0U, EBI_LCD_DCLKPOL_RISING = (0x1U << 24) }
EBI LCD Data Clock definition. More...

Functions

void | ald_ebi_nor_sram_init (EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_init_t *init)
Initialize the EBI_NOR_SRAM device according to the specified control parameters in the EBI_NOR_SRAM_InitTypeDef. More...
void | ald_ebi_nor_sram_timing_init (EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank)
Initialize the EBI_NOR_SRAM Timing according to the specified parameters in the EBI_NOR_SRAM_TimingTypeDef. More...
void | ald_ebi_nor_sram_ext_timing_init (EBI_NOR_SRAM_EXTENDED_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank, uint32_t mode)
Initialize the EBI_NOR_SRAM Extended mode Timing according to the specified parameters in the EBI_NOR_SRAM_TimingTypeDef. More...
ald_status_t | ald_ebi_nor_sram_deinit (EBI_NOR_SRAM_TypeDef *dev, EBI_NOR_SRAM_EXTENDED_TypeDef *e_dev, uint32_t bank)
DeInitialize the EBI_NOR_SRAM peripheral. More...
void | ald_ebi_nor_sram_enable (EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Enable the NOR/SRAM device access. More...
void | ald_ebi_nor_sram_disable (EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Disable the NORSRAM device access. More...
void | ald_ebi_nor_sram_write_enable (EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Enables dynamically NOR-FLASH/SRAM write operation. More...
void | ald_ebi_nor_sram_write_disable (EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Disables dynamically EBI_NORSRAM write operation. More...
void | ald_ebi_nand_init (EBI_NAND_TypeDef *dev, ald_ebi_nand_init_t *init)
Initializes the EBI_NAND device according to the specified control parameters in the EBI_NAND_HandleTypeDef. More...
void | ald_ebi_nand_comm_timing_init (EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
Initializes the EBI_NAND Common space Timing according to the specified parameters in the EBI_NAND_TimingTypeDef. More...
void | ald_ebi_nand_attr_timing_init (EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
Initializes the EBI_NAND Attribute space Timing according to the specified parameters in the EBI_NAND_TimingTypeDef. More...
void | ald_ebi_nand_deinit (EBI_NAND_TypeDef *dev, uint32_t bank)
DeInitializes the EBI_NAND device. More...
void | ald_ebi_nand_enable (EBI_NAND_TypeDef *dev, uint32_t bank)
Enable the NAND device access. More...
void | ald_ebi_nand_disable (EBI_NAND_TypeDef *dev, uint32_t bank)
Disable the NAND device access. More...
void | ald_ebi_nand_enable_it (EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it)
Enable the NAND device interrupt. More...
void | ald_ebi_nand_disable_it (EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it)
Disable the NAND device interrupt. More...
void | ald_ebi_nand_ecc_enable (EBI_NAND_TypeDef *dev, uint32_t bank)
Enables dynamically EBI_NAND ECC feature. More...
void | ald_ebi_nand_ecc_disable (EBI_NAND_TypeDef *dev, uint32_t bank)
Disables dynamically EBI_NAND ECC feature. More...
ald_status_t | ald_ebi_nand_get_ecc (EBI_NAND_TypeDef *dev, uint32_t *val, uint32_t bank, uint32_t timeout)
Disables dynamically EBI_NAND ECC feature. More...
flag_status_t | ald_ebi_nand_get_flag (EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
Get flag status of the NAND device. More...
void | ald_ebi_nand_clear_flag (EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
Clear flag status of the NAND device. More...
void | ald_ebi_lcd_init (ebi_lcd_handle_t *hlcd)
Initializes the EBI_LCD device according to the specified control parameters in the nor_lcd_handle_t. More...
void | ald_ebi_lcd_reset (ebi_lcd_handle_t *hlcd)
Reset the EBI_LCD. More...

Detailed Description

Header file of EBI module driver.

Version
V1.0
Date
20 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_ebi.h.


ALD User Manual: D:/svn/src/ald_flash.c File Reference

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  • svn
  • src
Macros | Functions | Variables
ald_flash.c File Reference

FLASH module driver. More...

#include "ald_flash.h"
Include dependency graph for ald_flash.c:

Go to the source code of this file.

Macros

#define __RAMFUNC

Functions

static __RAMFUNC ald_status_t | flash_unlock (void)
Unlock the flash. More...
static __RAMFUNC ald_status_t | flash_lock (void)
Lock the flash. More...
__RAMFUNC ald_status_t | flash_page_erase (uint32_t addr)
Erase one page. More...
__RAMFUNC ald_status_t | flash_word_program (uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo)
Programme a word. More...

Variables

static op_cmd_type OP_CMD = OP_FLASH

Detailed Description

FLASH module driver.

Version
V1.0
Date
17 Jun 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

==============================================================================
                  ##### FLASH Peripheral features #####
==============================================================================
[..]
Base address is 0x00000000

[..]
FLASH have just one programme mode , word programme.
word programme can programme 8 bytes once ;

==============================================================================
                      ##### How to use this driver #####
==============================================================================
[..]
This driver provide private functions for ald_flash_ext.c to use

Definition in file ald_flash.c.


ALD User Manual: D:/svn/src/ald_flash.h File Reference

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Macros | Enumerations | Functions
ald_flash.h File Reference

Header file of FLASH driver. More...

#include "utils.h"
Include dependency graph for ald_flash.h:
This graph shows which files directly or indirectly include this file:

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Macros

#define | FLASH_REG_UNLOCK()
#define | FLASH_REQ() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
#define | FLASH_REQ_FIN() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
#define | FLASH_IAP_ENABLE() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
#define | FLASH_IAP_DISABLE() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
#define | FLASH_BASE_ADDR 0x00000000
#define | FLASH_PAGE_SIZE 1024UL
#define | FLASH_WORD_SIZE 8UL
#define | FLASH_TOTAL_SIZE 512UL
#define | FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1)
#define | FLASH_WORD_MASK (FLASH_WORD_SIZE - 1)
#define | IS_FLASH_ADDRESS(ADDR) ((ADDR) < (FLASH_BASE_ADDR + FLASH_PAGE_SIZE * FLASH_TOTAL_SIZE))
#define | IS_4BYTES_ALIGN(ADDR) (((uint32_t)(ADDR) & 0x3) == 0 ? 1 : 0)
#define | FLASH_PAGE_ADDR(ADDR) ((ADDR) & (~FLASH_PAGE_MASK))
#define | FLASH_PAGEEND_ADDR(ADDR) ((ADDR) | FLASH_PAGE_MASK)
#define | FLASH_WORD_ADDR(ADDR) ((ADDR) & (~FLASH_WORD_MASK))
#define | FLASH_WORDEND_ADDR(ADDR) ((ADDR) | FLASH_WORD_MASK)
#define | INFO_PAGE_SIZE 1024UL
#define | INFO_PAGE_MASK (INFO_PAGE_SIZE - 1)
#define | INFO_PAGE_ADDR(ADDR) ((ADDR) & (~INFO_PAGE_MASK))
#define | FLASH_FIFO 0

Enumerations

enum flash_cmd_type {
FLASH_CMD_AE = 0x000051AEU, FLASH_CMD_PE = 0x00005EA1U, FLASH_CMD_WP = 0x00005DA2U, FLASH_CMD_WP_FAST = 0x00005CA3U,
FLASH_CMD_DATAPE = 0x00005BA4U, FLASH_CMD_DATAWP = 0x00005AA5U, FLASH_CMD_DATAWP_FAST = 0x000059A6U, FLASH_CMD_NP_AE = 0x000050AFU
}
enum op_cmd_type { OP_FLASH = 0U, OP_INFO = 1U }

Functions

__RAMFUNC ald_status_t | flash_page_erase (uint32_t addr)
Erase one page. More...
__RAMFUNC ald_status_t | flash_word_program (uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo)
Programme a word. More...
ald_status_t | ald_flash_read (uint32_t *ram_addr, uint32_t addr, uint16_t len)
read the specified length bytes from flash, and store to the specified area. More...
ald_status_t | ald_flash_write (uint32_t addr, uint8_t *buf, uint16_t len)
Write the give bytes to the given address section. More...
ald_status_t | ald_flash_erase (uint32_t addr, uint16_t len)
erase The flash between the given address section. More...

Detailed Description

Header file of FLASH driver.

Version
V1.0
Date
17 Jun 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_flash.h.


ALD User Manual: D:/svn/src/ald_flash_ext.c File Reference

  • D:
  • svn
  • src
Functions | Variables
ald_flash_ext.c File Reference

FLASH extra module driver. More...

#include "ald_flash.h"
Include dependency graph for ald_flash_ext.c:

Go to the source code of this file.

Functions

static type_bool_t | page_have_writen (uint32_t begin_addr, uint32_t end_addr)
Check whether the flash between the given address section have been writen, if it have been writen, return TRUE, else return FALSE. More...
ald_status_t | ald_flash_read (uint32_t *ram_addr, uint32_t addr, uint16_t len)
read the specified length bytes from flash, and store to the specified area. More...
ald_status_t | ald_flash_write (uint32_t addr, uint8_t *buf, uint16_t len)
Write the give bytes to the given address section. More...
ald_status_t | ald_flash_erase (uint32_t addr, uint16_t len)
erase The flash between the given address section. More...

Variables

static uint8_t write_buf [FLASH_PAGE_SIZE]

Detailed Description

FLASH extra module driver.

Version
V1.0
Date
17 Jun 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

==============================================================================
                  ##### FLASH Peripheral features #####
==============================================================================
[..]
Base address is 0x00000000

[..]
FLASH have just one programme mode , word programme.
word programme can programme 8 bytes once ;

==============================================================================
                      ##### How to use this driver #####
==============================================================================
[..]
 (#) programme flash using ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len)
     (++) call the function and supply all the three paraments is needs, addr means
          the first address to write in this operation, buf is a pointer to the data which
          need writing to flash.

 (#) erase flash using ald_flash_erase(uint32_t addr, uint16_t len)
     (++) call the function and supply two paraments, addr is the first address to erase,
          len is the length to erase

 (#) read flash using ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len)
     (++) read the flash and save to a buffer, ram_addr is the buffer's first address,
          addr is the start reading address in flash, len is the length need read

Definition in file ald_flash_ext.c.


ALD User Manual: D:/svn/src/ald_gpio.c File Reference

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  • svn
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Functions
ald_gpio.c File Reference

GPIO module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral: More...

#include "ald_conf.h"
#include "ald_gpio.h"
Include dependency graph for ald_gpio.c:

Go to the source code of this file.

Functions

void | ald_gpio_init (GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init)
Initialize the GPIOx peripheral according to the specified parameters in the gpio_init_t. More...
void | ald_gpio_init_default (GPIO_TypeDef *GPIOx, uint16_t pin)
Initialize the GPIOx peripheral using the default parameters. More...
void | ald_gpio_func_default (GPIO_TypeDef *GPIOx)
Sets GPIO function to default(func0). More...
void | ald_gpio_exti_init (GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init)
Initialize the external interrupt according to the specified parameters in the exti_init_t. More...
uint8_t | ald_gpio_read_pin (GPIO_TypeDef *GPIOx, uint16_t pin)
Read the specified input port pin. More...
void | ald_gpio_write_pin (GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val)
Set or clear the select Pin data. More...
void | ald_gpio_toggle_pin (GPIO_TypeDef *GPIOx, uint16_t pin)
Turn over the select data. More...
void | ald_gpio_toggle_dir (GPIO_TypeDef *GPIOx, uint16_t pin)
Turn over the direction. More...
void | ald_gpio_lock_pin (GPIO_TypeDef *GPIOx, uint16_t pin)
Lock the GPIO prot. Once locked, can only change the output data. Only when the CPU reset to unlock the GPIO port. More...
uint16_t | ald_gpio_read_port (GPIO_TypeDef *GPIOx)
Read the specified input port pin. More...
void | ald_gpio_write_port (GPIO_TypeDef *GPIOx, uint16_t val)
Set or clear the select Pin data. More...
void | ald_gpio_exti_interrupt_config (uint16_t pin, exti_trigger_style_t style, type_func_t status)
Configure the interrupt according to the specified parameter. More...
flag_status_t | ald_gpio_exti_get_flag_status (uint16_t pin)
Get the Flag about external interrupt. More...
void | ald_gpio_exti_clear_flag_status (uint16_t pin)
Clear the external interrupt flag. More...

Detailed Description

GPIO module driver. This file provides firmware functions to manage the following functionalities of the General Purpose Input/Output (GPIO) peripheral:

  • Initialization functions
  • IO operation functions
  • Control functions
Version
V1.0
Date
07 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

==============================================================================
                  ##### GPIO Peripheral features #####
==============================================================================
[..]
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
in several modes:
(+) Input mode
(+) Analog mode
(+) Output mode
(+) External interrupt/event lines

[..]
During and just after reset, the external interrupt lines are not active and
the I/O ports are configured Analog mode.

[..]
All GPIO pins have weak internal pull-up and pull-down resistors, which can be
activated or not.

[..]
In Output mode, each IO can be configured on open-drain or push-pull
type and the Output driver can be selected depending on ODRV register.

[..]
In Input mode, each IO can select filter function.

[..]
Each IO can select TTL or SMIT type.

[..]
Each IO have up to eight functions, user can configure the functions depend
on the user's environment.

[..]
Each IO can be locked. Once locked, uesr can only change the output data.
Only when the CPU reset to unlock the GPIO port.

[..]
All ports have external interrupt/event capability. To use external interrupt
lines, the port must be configured in input mode. All available GPIO pins are
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.

[..]
Each input line can be independently configured to select the type (event or interrupt) and
the corresponding trigger event (rising or falling). Each line can also masked
independently. A pending register maintains the status line of the interrupt requests.

==============================================================================
                      ##### How to use this driver #####
==============================================================================
[..]
 (#) Enable the GPIO clock.

 (#) Configure the GPIO pin(s) using ald_gpio_init().
     (++) Configure the IO mode using "mode" member from gpio_init_t structure
     (++) Activate Pull-up, Pull-down resistor using "pupd" member from gpio_init_t
          structure.
     (++) In Output mode, configured on open-drain or push-pull using "odos"
          member from gpio_init_t structure.
     (++) In Output mode, configured output driver using "odrv" member
          from gpio_init_t structure.
     (++) In Input mode, configured filter function using "flt" member
          from gpio_init_t structure.
     (++) Configured type using "type" member from gpio_init_t structure.
     (++) Configured functions using "func" member from gpio_init_t structure.
     (++) Analog mode is required when a pin is to be used as ADC channel
          or DAC output.

 (#) Configure the GPIO pin(s) using ald_gpio_init_default().
     (++) Configure GPIO pin using default param:
          init.mode  = GPIO_MODE_OUTPUT;
          init.odos  = GPIO_PUSH_PULL;
          init.pupd  = GPIO_PUSH_UP;
          init.podrv = GPIO_OUT_DRIVE_6;
          init.nodrv = GPIO_OUT_DRIVE_6;
          init.flt   = GPIO_FILTER_DISABLE;
          init.type  = GPIO_TYPE_CMOS;
          init.func  = GPIO_FUNC_1;

 (#) In case of external interrupt/event mode selection, user need invoke
     ald_gpio_exti_init() to configure some param. And then invoke
     ald_gpio_exti_interrupt_config() to enable/disable external interrupt/event.

 (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
     mapped to the EXTI line using NVIC_SetPriority() and enable it using
     NVIC_EnableIRQ().

 (#) To get the level of a pin configured in input mode use GPIO_read_pin().

 (#) To set/reset the level of a pin configured in output mode use
     ald_gpio_write_pin()/ald_gpio_toggle_pin().

 (#) To lock pin configuration until next reset use ald_gpio_lock_pin().

 (#) Configure external interrupt mode and enable/disable using
     ald_gpio_exti_interrupt_config().

 (#) Get external interrupt flag status using ald_gpio_exti_get_flag_status().

 (#) Clear pending external interrupt flag status using
     ald_gpio_exti_clear_flag_status().

Definition in file ald_gpio.c.


ALD User Manual: D:/svn/src/ald_gpio.h File Reference

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  • svn
  • src
Data Structures | Macros | Enumerations | Functions
ald_gpio.h File Reference

Header file of GPIO module driver. More...

#include "utils.h"
Include dependency graph for ald_gpio.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Data Structures

struct | gpio_init_t
GPIO Init Structure definition. More...
struct | exti_init_t
EXTI Init Structure definition. More...

Macros

#define | GPIO_PIN_0 (1U << 0)
#define | GPIO_PIN_1 (1U << 1)
#define | GPIO_PIN_2 (1U << 2)
#define | GPIO_PIN_3 (1U << 3)
#define | GPIO_PIN_4 (1U << 4)
#define | GPIO_PIN_5 (1U << 5)
#define | GPIO_PIN_6 (1U << 6)
#define | GPIO_PIN_7 (1U << 7)
#define | GPIO_PIN_8 (1U << 8)
#define | GPIO_PIN_9 (1U << 9)
#define | GPIO_PIN_10 (1U << 10)
#define | GPIO_PIN_11 (1U << 11)
#define | GPIO_PIN_12 (1U << 12)
#define | GPIO_PIN_13 (1U << 13)
#define | GPIO_PIN_14 (1U << 14)
#define | GPIO_PIN_15 (1U << 15)
#define | GPIO_PIN_ALL (0xFFFF)
#define | PIN_MASK 0xFFFFU
#define | UNLOCK_KEY 0x55AAU
#define | IS_GPIO_PIN(x) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0))
#define | IS_GPIO_PORT(GPIOx)
#define | IS_GPIO_MODE(x)
#define | IS_GPIO_ODOS(x)
#define | IS_GPIO_PUPD(x)
#define | IS_GPIO_ODRV(x)
#define | IS_GPIO_FLT(x)
#define | IS_GPIO_TYPE(x)
#define | IS_TRIGGER_STYLE(x)
#define | IS_EXTI_FLTCKS_TYPE(x)
#define | IS_GPIO_FUNC(x) ((x) <= 7)

Enumerations

enum | gpio_mode_t { GPIO_MODE_CLOSE = 0x0U, GPIO_MODE_INPUT = 0x1U, GPIO_MODE_OUTPUT = 0x2U }
GPIO mode. More...
enum | gpio_odos_t { GPIO_PUSH_PULL = 0x0U, GPIO_OPEN_DRAIN = 0x2U, GPIO_OPEN_SOURCE = 0x3U }
GPIO open-drain or push-pull. More...
enum | gpio_push_t { GPIO_FLOATING = 0x0U, GPIO_PUSH_UP = 0x1U, GPIO_PUSH_DOWN = 0x2U, GPIO_PUSH_UP_DOWN = 0x3U }
GPIO push-up or push-down. More...
enum | gpio_out_drive_t { GPIO_OUT_DRIVE_0_1 = 0x0U, GPIO_OUT_DRIVE_1 = 0x1U, GPIO_OUT_DRIVE_6 = 0x2U, GPIO_OUT_DRIVE_20 = 0x3U }
GPIO output drive. More...
enum | gpio_filter_t { GPIO_FILTER_DISABLE = 0x0U, GPIO_FILTER_ENABLE = 0x1U }
GPIO filter. More...
enum | gpio_type_t { GPIO_TYPE_CMOS = 0x0U, GPIO_TYPE_TTL = 0x1U }
GPIO type. More...
enum gpio_func_t {
GPIO_FUNC_0 = 0U, GPIO_FUNC_1 = 1U, GPIO_FUNC_2 = 2U, GPIO_FUNC_3 = 3U,
GPIO_FUNC_4 = 4U, GPIO_FUNC_5 = 5U, GPIO_FUNC_6 = 6U, GPIO_FUNC_7 = 7U
}
GPIO functions. More...
enum | exti_trigger_style_t { EXTI_TRIGGER_RISING_EDGE = 0U, EXTI_TRIGGER_TRAILING_EDGE = 1U, EXTI_TRIGGER_BOTH_EDGE = 2U }
EXTI trigger style. More...
enum | exti_filter_clock_t { EXTI_FILTER_CLOCK_10K = 0U, EXTI_FILTER_CLOCK_32K = 1U }
EXTI filter clock select. More...

Functions

void | ald_gpio_init (GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init)
Initialize the GPIOx peripheral according to the specified parameters in the gpio_init_t. More...
void | ald_gpio_init_default (GPIO_TypeDef *GPIOx, uint16_t pin)
Initialize the GPIOx peripheral using the default parameters. More...
void | ald_gpio_func_default (GPIO_TypeDef *GPIOx)
Sets GPIO function to default(func0). More...
void | ald_gpio_exti_init (GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init)
Initialize the external interrupt according to the specified parameters in the exti_init_t. More...
uint8_t | ald_gpio_read_pin (GPIO_TypeDef *GPIOx, uint16_t pin)
Read the specified input port pin. More...
void | ald_gpio_write_pin (GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val)
Set or clear the select Pin data. More...
void | ald_gpio_toggle_pin (GPIO_TypeDef *GPIOx, uint16_t pin)
Turn over the select data. More...
void | ald_gpio_toggle_dir (GPIO_TypeDef *GPIOx, uint16_t pin)
Turn over the direction. More...
void | ald_gpio_lock_pin (GPIO_TypeDef *GPIOx, uint16_t pin)
Lock the GPIO prot. Once locked, can only change the output data. Only when the CPU reset to unlock the GPIO port. More...
uint16_t | ald_gpio_read_port (GPIO_TypeDef *GPIOx)
Read the specified input port pin. More...
void | ald_gpio_write_port (GPIO_TypeDef *GPIOx, uint16_t val)
Set or clear the select Pin data. More...
void | ald_gpio_exti_interrupt_config (uint16_t pin, exti_trigger_style_t style, type_func_t status)
Configure the interrupt according to the specified parameter. More...
flag_status_t | ald_gpio_exti_get_flag_status (uint16_t pin)
Get the Flag about external interrupt. More...
void | ald_gpio_exti_clear_flag_status (uint16_t pin)
Clear the external interrupt flag. More...

Detailed Description

Header file of GPIO module driver.

Version
V1.0
Date
07 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_gpio.h.


ALD User Manual: D:/svn/src/ald_i2c.c File Reference

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  • svn
  • src
Macros | Functions
ald_i2c.c File Reference

I2C module driver. More...

#include "ald_i2c.h"
Include dependency graph for ald_i2c.c:

Go to the source code of this file.

Macros

#define | I2C_TIMEOUT_FLAG (__systick_interval / 20 + 1)
#define | I2C_TIMEOUT_ADDR_SLAVE (__systick_interval * 10)
#define | I2C_TIMEOUT_BUSY_FLAG (__systick_interval * 10)
#define | I2C_MAX_DELAY 0xFFFFFFFF

Functions

static void | i2c_dma_master_send_cplt (void *argv)
DMA I2C master transmit process complete callback. More...
static void | i2c_dma_master_recv_cplt (void *argv)
DMA I2C master receive process complete callback. More...
static void | i2c_dma_slave_send_cplt (void *argv)
DMA I2C slave transmit process complete callback. More...
static void | i2c_dma_slave_recv_cplt (void *argv)
DMA I2C slave receive process complete callback. More...
static void | i2c_dma_mem_send_cplt (void *argv)
DMA I2C Memory Write process complete callback. More...
static void | i2c_dma_mem_recv_cplt (void *argv)
DMA I2C Memory Read process complete callback. More...
static void | i2c_dma_error (void *argv)
DMA I2C communication error callback. More...
static ald_status_t | i2c_req_mem_read (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout)
Master sends target device address followed by internal memory address for read request. More...
static ald_status_t | i2c_master_req_write (i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout)
Master sends target device address followed by internal memory address for write request. More...
static ald_status_t | i2c_master_req_read (i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout)
Master sends target device address followed by internal memory address for read request. More...
static ald_status_t | i2c_req_mem_write (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout)
Master sends target device address followed by internal memory address for write request. More...
static ald_status_t | i2c_wait_flag_change_to_timeout (i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout. More...
static ald_status_t | i2c_wait_master_addr_to_timeout (i2c_handle_t *hperh, uint32_t flag, uint32_t timeout)
This function handles I2C Communication timeout for Master addressing phase. More...
static ald_status_t | i2c_wait_txe_to_timeout (i2c_handle_t *hperh, uint32_t timeout)
This function handles I2C Communication timeout for specific usage of TXE flag. More...
static ald_status_t | i2c_wait_rxne_to_timeout (i2c_handle_t *hperh, uint32_t timeout)
This function handles I2C Communication timeout for specific usage of RXNE flag. More...
static ald_status_t | i2c_master_send_tc (i2c_handle_t *hperh)
Handle transmit complete flag for Master Transmit mode. More...
static ald_status_t | i2c_master_send_txe (i2c_handle_t *hperh)
Handle transmit empty flag for Master Transmit mode. More...
static ald_status_t | i2c_master_recv_tc (i2c_handle_t *hperh)
Handle receive complete for Master Receive mode. More...
static ald_status_t | i2c_master_recv_rxne (i2c_handle_t *hperh)
Handle receive not empty for Master Receive mode. More...
static ald_status_t | i2c_slave_send_txe (i2c_handle_t *hperh)
Handle TXE flag for Slave Transmit mode. More...
static ald_status_t | i2c_slave_recv_rxne (i2c_handle_t *hperh)
Handle RXNE flag for Slave Receive mode. More...
static ald_status_t | i2c_slave_stopf (i2c_handle_t *hperh)
Handle STOPF flag for Slave mode. More...
ald_status_t | i2c_speed_init (i2c_handle_t *hperh, uint32_t freqrange)
I2C Configuration Speed function. More...
ald_status_t | ald_i2c_init (i2c_handle_t *hperh)
Initializes the I2C according to the specified parameters in the i2c_init_t and initialize the associated handle. More...
ald_status_t | ald_i2c_reset (i2c_handle_t *hperh)
DeInitialize the I2C peripheral. More...
ald_status_t | ald_i2c_master_send (i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size, uint32_t timeout)
Transmits in master mode an amount of data in blocking mode. More...
ald_status_t | ald_i2c_master_recv (i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size, uint32_t timeout)
Receives in master mode an amount of data in blocking mode. More...
ald_status_t | ald_i2c_slave_send (i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Transmits in slave mode an amount of data in blocking mode. More...
ald_status_t | ald_i2c_slave_recv (i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Receive in slave mode an amount of data in blocking mode. More...
ald_status_t | ald_i2c_master_send_by_it (i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt. More...
ald_status_t | ald_i2c_master_recv_by_it (i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size)
Receive in master mode an amount of data in non-blocking mode with Interrupt. More...
ald_status_t | ald_i2c_slave_send_by_it (i2c_handle_t *hperh, uint8_t *buf, uint32_t size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt. More...
ald_status_t | ald_i2c_slave_recv_by_it (i2c_handle_t *hperh, uint8_t *buf, uint32_t size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt. More...
ald_status_t | ald_i2c_master_send_by_dma (i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint8_t size, uint8_t channel)
Transmit in master mode an amount of data in non-blocking mode with DMA. More...
ald_status_t | ald_i2c_master_recv_by_dma (i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint8_t size, uint8_t channel)
Receive in master mode an amount of data in non-blocking mode with DMA. More...
ald_status_t | ald_i2c_slave_send_by_dma (i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel)
Transmit in slave mode an amount of data in non-blocking mode with DMA. More...
ald_status_t | ald_i2c_slave_recv_by_dma (i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel)
Receive in slave mode an amount of data in non-blocking mode with DMA. More...
ald_status_t | ald_i2c_mem_write (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout)
Write an amount of data in blocking mode to a specific memory address. More...
ald_status_t | ald_i2c_mem_read (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout)
Read an amount of data in blocking mode from a specific memory address. More...
ald_status_t | ald_i2c_mem_write_by_it (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint32_t size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address. More...
ald_status_t | ald_i2c_mem_read_by_it (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint32_t size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address. More...
ald_status_t | ald_i2c_mem_write_by_dma (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint8_t size, uint8_t channel)
Write an amount of data in non-blocking mode with DMA to a specific memory address. More...
ald_status_t | ald_i2c_mem_read_by_dma (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint8_t size, uint8_t channel)
Reads an amount of data in non-blocking mode with DMA from a specific memory address. More...
i2c_state_t | ald_i2c_get_state (i2c_handle_t *hperh)
Return the I2C handle state. More...
uint32_t | ald_i2c_get_error (i2c_handle_t *hperh)
Return the I2C error code. More...
void | ald_i2c_ev_irq_handler (i2c_handle_t *hperh)
This function handles I2C event interrupt request. More...
void | ald_i2c_er_irq_handler (i2c_handle_t *hperh)
This function handles I2C error interrupt request. More...
void | ald_i2c_interrupt_config (i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state)
Enable/disable the specified I2C interrupts. More...
it_status_t | ald_i2c_get_it_status (i2c_handle_t *hperh, i2c_interrupt_t it)
Get the status of I2C interrupt source. More...
flag_status_t | ald_i2c_get_flag_status (i2c_handle_t *hperh, i2c_interrupt_t flag)
Get the status of I2C interrupt flag. More...
flag_status_t | ald_i2c_get_mask_flag_status (i2c_handle_t *hperh, i2c_interrupt_t flag)
Get the status of interrupt flag and interupt source. More...
void | ald_i2c_clear_flag_status (i2c_handle_t *hperh, i2c_interrupt_t flag)
Clear the I2C interrupt flag. More...

Detailed Description

I2C module driver.

Version
V1.0
Date
15 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

==============================================================================
                      ##### How to use this driver #####
==============================================================================
[..]
  The I2C driver can be used as follows:

  (#) Declare a i2c_handle_t handle structure, for example:
      i2c_handle_t  hperh;

  (#) Configure the Communication Speed, Addressing mode, Own Address1,
      Dual Addressing mode, Own Address2, General call and Nostretch mode in the hperh init structure.

  (#) Initialize the I2C registers by calling the ald_i2c_init().

  (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :

  *** Polling mode IO operation ***
  =================================
  [..]
    (+) Transmit in master mode an amount of data in blocking mode using ald_i2c_master_send()
    (+) Receive in master mode an amount of data in blocking mode using ald_i2c_master_recv()
    (+) Transmit in slave mode an amount of data in blocking mode using ald_i2c_slave_send()
    (+) Receive in slave mode an amount of data in blocking mode using ald_i2c_slave_recv()

  *** Polling mode IO MEM operation ***
  =====================================
  [..]
    (+) Write an amount of data in blocking mode to a specific memory address using ald_i2c_mem_write()
    (+) Read an amount of data in blocking mode from a specific memory address using ald_i2c_mem_read()

  *** Interrupt mode IO operation ***
  ===================================
  [..]
    (+) The I2C interrupts should have the highest priority in the application in order
        to make them uninterruptible.
    (+) Transmit in master mode an amount of data in non-blocking mode using ald_i2c_master_send_by_it()
    (+) At transmission end of transfer, hperh->master_tx_cplt_cbk() is executed and user can
         add his own code by customization of function pointer hperh->master_tx_cplt_cbk()
    (+) Receive in master mode an amount of data in non-blocking mode using ald_i2c_master_recv_by_it()
    (+) At reception end of transfer, hperh->master_rx_cplt_cbk() is executed and user can
         add his own code by customization of function pointer hperh->master_rx_cplt_cbk()
    (+) Transmit in slave mode an amount of data in non-blocking mode using ald_i2c_slave_send_by_it()
    (+) At transmission end of transfer, hperh->slave_tx_cplt_cbk() is executed and user can
         add his own code by customization of function pointer hperh->slave_tx_cplt_cbk()
    (+) Receive in slave mode an amount of data in non-blocking mode using ald_i2c_slave_recv_by_it()
    (+) At reception end of transfer, hperh->slave_rx_cplt_cbk() is executed and user can
         add his own code by customization of function pointer hperh->slave_rx_cplt_cbk()
    (+) In case of transfer Error, hperh->error_callback() function is executed and user can
         add his own code by customization of function pointer hperh->error_callback()

  *** Interrupt mode IO MEM operation ***
  =======================================
  [..]
    (+) The I2C interrupts should have the highest priority in the application in order
        to make them uninterruptible.
    (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
        ald_i2c_mem_write_by_it()
    (+) At Memory end of write transfer, hperh->mem_tx_cplt_cbk() is executed and user can
         add his own code by customization of function pointer hperh->mem_tx_cplt_cbk()
    (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
        ald_i2c_mem_read_by_it()
    (+) At Memory end of read transfer, hperh->mem_rx_cplt_cbk() is executed and user can
         add his own code by customization of function pointer hperh->mem_rx_cplt_cbk()
    (+) In case of transfer Error, hperh->error_callback() function is executed and user can
         add his own code by customization of function pointer hperh->error_callback()

  *** DMA mode IO operation ***
  ==============================
  [..]
    (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
        ald_i2c_master_send_by_dma()
    (+) At transmission end of transfer, hperh->master_tx_cplt_cbk() is executed and user can
         add his own code by customization of function pointer hperh->master_tx_cplt_cbk()
    (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
        ald_i2c_master_recv_by_dma()
    (+) At reception end of transfer, hperh->master_rx_cplt_cbk() is executed and user can
         add his own code by customization of function pointer hperh->master_rx_cplt_cbk()
    (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
        ald_i2c_slave_send_by_dma()
    (+) At transmission end of transfer, hperh->slave_tx_cplt_cbk() is executed and user can
         add his own code by customization of function pointer hperh->slave_tx_cplt_cbk()
    (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
        ald_i2c_slave_recv_by_dma()
    (+) At reception end of transfer, hperh->slave_rx_cplt_cbk() is executed and user can
         add his own code by customization of function pointer hperh->slave_rx_cplt_cbk()
    (+) In case of transfer Error, hperh->error_callback() function is executed and user can
         add his own code by customization of function pointer hperh->error_callback()

  *** DMA mode IO MEM operation ***
  =================================
  [..]
    (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
        ald_i2c_mem_write_by_dma()
    (+) At Memory end of write transfer, hperh->mem_tx_cplt_cbk() is executed and user can
         add his own code by customization of function pointer hperh->mem_tx_cplt_cbk()
    (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
        ald_i2c_mem_read_by_dma()
    (+) At Memory end of read transfer, hperh->mem_rx_cplt_cbk() is executed and user can
         add his own code by customization of function pointer hperh->mem_rx_cplt_cbk()
    (+) In case of transfer Error, hperh->error_callback() function is executed and user can
         add his own code by customization of function pointer hperh->error_callback()

   *** I2C ald_status_t driver macros list ***
   ==================================
   [..]
     Below the list of most used macros in I2C ald_status_t driver.

    (+) __I2C_ENABLE: Enable the I2C peripheral
    (+) __I2C_DISABLE: Disable the I2C peripheral
    (+) I2C_GET_FLAG: Check whether the specified I2C flag is set or not
    (+) I2C_ENABLE_IT: Enable the specified I2C interrupt
    (+) I2C_DISABLE_IT: Disable the specified I2C interrupt
     (@) You can refer to the I2C ald_status_t driver header file for more useful macros

   *** I2C Workarounds linked to Silicon Limitation ***
   ====================================================
   [..]
     Below the list of all silicon limitations implemented for library on our product.
     (@) See ErrataSheet to know full silicon limitation list of your product.

     (#) Workarounds Implemented inside I2C library
        (##) Wrong data read into data register (Polling and Interrupt mode)
        (##) Start cannot be generated after a misplaced Stop
        (##) Some software events must be managed before the current byte is being transferred:
             Workaround: Use DMA in general, except when the Master is receiving a single byte.
             For Interupt mode, I2C should have the highest priority in the application.
        (##) Mismatch on the "Setup time for a repeated Start condition" timing parameter:
             Workaround: Reduce the frequency down to 88 kHz or use the I2C Fast-mode if
             supported by the slave.
        (##) Data valid time (tVD;DAT) violated without the OVR flag being set:
             Workaround: If the slave device allows it, use the clock stretching mechanism
             by programming no_stretch = I2C_NOSTRETCH_DISABLE in ald_i2c_init.

Definition in file ald_i2c.c.


ALD User Manual: D:/svn/src/ald_i2c.h File Reference

  • D:
  • svn
  • src
Data Structures | Macros | Typedefs | Enumerations | Functions
ald_i2c.h File Reference

Header file of I2C driver. More...

#include "utils.h"
#include "ald_dma.h"
#include "ald_cmu.h"
#include <string.h>
Include dependency graph for ald_i2c.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Data Structures

struct | i2c_init_t
I2C Configuration Structure definition. More...
struct | i2c_handle_s
I2C handle Structure definition. More...

Macros

#define | I2C_FLAG_MASK (0xFFFFFFFFU)
#define | I2C_RESET_HANDLE_STATE(x) ((x)->state = I2C_STATE_RESET)
#define | I2C_ENABLE_IT(x, y) (SET_BIT((x)->perh->IER, (y)))
#define | I2C_DISABLE_IT(x, y) (SET_BIT((x)->perh->IDR, (y)))
#define | I2C_CLEAR_IT(x, y) (SET_BIT((x)->perh->ICR, (y)))
#define | I2C_GET_IT_FLAG(x, y) (READ_BIT((x)->perh->RIF, (y)))
#define | I2C_GET_IT_SOURCE(x, y) ((((x)->perh->IFM & (y)) == (y)) ? SET : RESET)
#define | I2C_GET_FLAG(x, y) ((((x)->perh->STAT) & ((y) & I2C_FLAG_MASK)) != RESET)
#define | I2C_MASTER_GET_DIR(x) (READ_BIT(((x)->perh->CON2), I2C_CON2_RD_WRN_MSK))
#define | I2C_SLAVE_GET_DIR(x) (READ_BIT(hperh->perh->STAT, I2C_STAT_DIR_MSK))
#define | I2C_ENABLE(x) (SET_BIT((x)->perh->CON1, I2C_CON1_PE_MSK))
#define | I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PE_MSK))
#define | IS_I2C_TYPE(x) (((x) == I2C0) || ((x) == I2C1))
#define | IS_I2C_MODULE(x) (((x) == I2C_MODULE_MASTER) || ((x) == I2C_MODULE_SLAVE))
#define | IS_I2C_ADDRESSING_MODE(ADDRESS)
#define | IS_I2C_DUAL_ADDRESS(ADDRESS)
#define | IS_I2C_GENERAL_CALL(CALL)
#define | IS_I2C_MEMADD_size(size)
#define | IS_I2C_NO_STRETCH(STRETCH)
#define | IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= I2C_EXTREME_FAST_MODE_MAX_CLK) )
#define | I2C_FREQ_RANGE(__PCLK__) ((__PCLK__) / 1000000)
#define | I2C_MEM_ADD_MSB(__ADDRESS__)
#define | I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
#define | IS_I2C_IT(x)

Typedefs

typedef struct i2c_handle_s i2c_handle_t
I2C handle Structure definition. More...

Enumerations

enum i2c_error_t {
I2C_ERROR_NONE = 0x0U, I2C_ERROR_BERR = 0x1U, I2C_ERROR_ARLO = 0x2U, I2C_ERROR_RUD = 0x4U,
I2C_ERROR_AF = 0x8U, I2C_ERROR_ROV = 0x10U, I2C_ERROR_RF = 0x20U, I2C_ERROR_TUD = 0x40U,
I2C_ERROR_TOV = 0x80U, I2C_ERROR_TE = 0x100U, I2C_ERROR_DMA = 0x200U, I2C_ERROR_TIMEOUT = 0x400U
}
I2C Error Code. More...
enum i2c_state_t {
I2C_STATE_RESET = 0x0U, I2C_STATE_READY = 0x20U, I2C_STATE_BUSY = 0x24U, I2C_STATE_BUSY_TX = 0x21U,
I2C_STATE_BUSY_RX = 0x22U, I2C_STATE_TIMEOUT = 0xA0U, I2C_STATE_ERROR = 0xE0U
}
I2C state structure definition. More...
enum | i2c_addr_t { I2C_ADDR_7BIT = 0x0U, I2C_ADDR_10BIT = 0x1U }
I2C Addressing Mode. More...
enum | i2c_dual_addr_t { I2C_DUALADDR_DISABLE = 0x0U, I2C_DUALADDR_ENABLE = 0x1U }
I2C Dual Addressing Mode. More...
enum | i2c_general_addr_t { I2C_GENERALCALL_DISABLE = 0x0U, I2C_GENERALCALL_ENABLE = 0x1U }
I2C General Call Addressing mode. More...
enum | i2c_nostretch_t { I2C_NOSTRETCH_DISABLE = 0x0U, I2C_NOSTRETCH_ENABLE = 0x1U }
I2C Nostretch Mode. More...
enum | i2c_addr_size_t { I2C_MEMADD_SIZE_8BIT = 0x8U, I2C_MEMADD_SIZE_16BIT = 0x10U }
I2C Memory Address Size. More...
enum | i2c_mode_t { I2C_MODE_NONE = 0x0U, I2C_MODE_MASTER = 0x10U, I2C_MODE_SLAVE = 0x20U, I2C_MODE_MEM = 0x40U }
I2C mode structure definition. More...
enum | i2c_clock_t { I2C_STANDARD_MODE_MAX_CLK = 100000U, I2C_FAST_MODE_MAX_CLK = 400000U, I2C_EXTREME_FAST_MODE_MAX_CLK = 1000000U }
I2C Clock. More...
enum | i2c_oar2_t { I2C_OAR2_ENDUAL = (1U << 0), I2C_OAR2_ADD2 = (1U << 1) }
I2C OAR2 Register. More...
enum i2c_con1_t {
I2C_CON1_PE = (1U << 0), I2C_CON1_TXDMA = (1U << 14), I2C_CON1_RXDMA = (1U << 15), I2C_CON1_SBC = (1U << 16),
I2C_CON1_NOSTRETCH = (1U << 17), I2C_CON1_GCEN = (1U << 19), I2C_CON1_SMBHEN = (1U << 20), I2C_CON1_SMBDEN = (1U << 21),
I2C_CON1_ALERTEN = (1U << 22), I2C_CON1_PECEN = (1U << 23)
}
I2C CON1 Register. More...
enum i2c_con2_t {
I2C_CON2_RD_WRN = (1U << 10), I2C_CON2_ADD10 = (1U << 11), I2C_CON2_HEAD10R = (1U << 12), I2C_CON2_START = (1U << 13),
I2C_CON2_STOP = (1U << 14), I2C_CON2_NACK = (1U << 15), I2C_CON2_RELOAD = (1U << 24), I2C_CON2_AUTOEND = (1U << 25),
I2C_CON2_PECBYTE = (1U << 26), I2C_CON2_HOLDACK = (1U << 28)
}
I2C CON2 Register. More...
enum | i2c_addr1_t { I2C_OA1MODE = (1U << 10), I2C_OA1EN = (1U << 15) }
I2C ADDR1 Register. More...
enum | i2c_addr2_t { I2C_OA2EN = (1U << 15) }
I2C ADDR2 Register. More...
enum | i2c_timoutr_t { I2C_TIMEOUTR_TIDLE = (1U << 12), I2C_TIMEOUTR_TIMEOUTEN = (1U << 15) }
I2C TIMEOUTR Register. More...
enum | i2c_module_t { I2C_MODULE_MASTER = (1U << 0), I2C_MODULE_SLAVE = (1U << 1) }
I2C peripherals module. More...
enum i2c_stat_t {
I2C_STAT_TXE = (1U << 0), I2C_STAT_TXF = (1U << 1), I2C_STAT_TXOV = (1U << 2), I2C_STAT_TXUD = (1U << 3),
I2C_STAT_THTH = (1U << 4), I2C_STAT_RXE = (1U << 5), I2C_STAT_RXF = (1U << 6), I2C_STAT_RXOV = (1U << 7),
I2C_STAT_RXUD = (1U << 8), I2C_STAT_RXTH = (1U << 9), I2C_STAT_TC = (1U << 10), I2C_STAT_TCR = (1U << 11),
I2C_STAT_BUSY = (1U << 15), I2C_STAT_DIR = (1U << 16)
}
I2C STAT Register. More...
enum i2c_interrupt_t {
I2C_IT_TXE = (1U << 0), I2C_IT_TXOV = (1U << 2), I2C_IT_TXUD = (1U << 3), I2C_IT_TXTH = (1U << 4),
I2C_IT_RXF = (1U << 6), I2C_IT_RXOV = (1U << 7), I2C_IT_RXUD = (1U << 8), I2C_IT_RXTH = (1U << 9),
I2C_IT_TC = (1U << 10), I2C_IT_TCR = (1U << 11), I2C_IT_ADDR = (1U << 12), I2C_IT_NACK = (1U << 13),
I2C_IT_STOP = (1U << 14), I2C_IT_BERR = (1U << 16), I2C_IT_ARLO = (1U << 17), I2C_IT_PECE = (1U << 18),
I2C_IT_TOUT = (1U << 19), I2C_IT_ALERT = (1U << 20)
}
Interrupt Configuration Definition. More...
enum | i2c_trise_t { I2C_TRISE_TRISE = 0x3FU }
I2C TRISE Register. More...

Functions

ald_status_t | ald_i2c_init (i2c_handle_t *hperh)
Initializes the I2C according to the specified parameters in the i2c_init_t and initialize the associated handle. More...
ald_status_t | ald_i2c_reset (i2c_handle_t *hperh)
DeInitialize the I2C peripheral. More...
ald_status_t | ald_i2c_master_send (i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size, uint32_t timeout)
Transmits in master mode an amount of data in blocking mode. More...
ald_status_t | ald_i2c_master_recv (i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size, uint32_t timeout)
Receives in master mode an amount of data in blocking mode. More...
ald_status_t | ald_i2c_slave_send (i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Transmits in slave mode an amount of data in blocking mode. More...
ald_status_t | ald_i2c_slave_recv (i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Receive in slave mode an amount of data in blocking mode. More...
ald_status_t | ald_i2c_mem_write (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout)
Write an amount of data in blocking mode to a specific memory address. More...
ald_status_t | ald_i2c_mem_read (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout)
Read an amount of data in blocking mode from a specific memory address. More...
ald_status_t | ald_i2c_master_send_by_it (i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt. More...
ald_status_t | ald_i2c_master_recv_by_it (i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size)
Receive in master mode an amount of data in non-blocking mode with Interrupt. More...
ald_status_t | ald_i2c_slave_send_by_it (i2c_handle_t *hperh, uint8_t *buf, uint32_t size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt. More...
ald_status_t | ald_i2c_slave_recv_by_it (i2c_handle_t *hperh, uint8_t *buf, uint32_t size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt. More...
ald_status_t | ald_i2c_mem_write_by_it (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint32_t size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address. More...
ald_status_t | ald_i2c_mem_read_by_it (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint32_t size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address. More...
ald_status_t | ald_i2c_master_send_by_dma (i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint8_t size, uint8_t channel)
Transmit in master mode an amount of data in non-blocking mode with DMA. More...
ald_status_t | ald_i2c_master_recv_by_dma (i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint8_t size, uint8_t channel)
Receive in master mode an amount of data in non-blocking mode with DMA. More...
ald_status_t | ald_i2c_slave_send_by_dma (i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel)
Transmit in slave mode an amount of data in non-blocking mode with DMA. More...
ald_status_t | ald_i2c_slave_recv_by_dma (i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel)
Receive in slave mode an amount of data in non-blocking mode with DMA. More...
ald_status_t | ald_i2c_mem_write_by_dma (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint8_t size, uint8_t channel)
Write an amount of data in non-blocking mode with DMA to a specific memory address. More...
ald_status_t | ald_i2c_mem_read_by_dma (i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint8_t size, uint8_t channel)
Reads an amount of data in non-blocking mode with DMA from a specific memory address. More...
i2c_state_t | ald_i2c_get_state (i2c_handle_t *hperh)
Return the I2C handle state. More...
uint32_t | ald_i2c_get_error (i2c_handle_t *hperh)
Return the I2C error code. More...
void | ald_i2c_clear_flag_status (i2c_handle_t *hperh, i2c_interrupt_t flag)
Clear the I2C interrupt flag. More...
flag_status_t | ald_i2c_get_mask_flag_status (i2c_handle_t *hperh, i2c_interrupt_t flag)
Get the status of interrupt flag and interupt source. More...
flag_status_t | ald_i2c_get_flag_status (i2c_handle_t *hperh, i2c_interrupt_t flag)
Get the status of I2C interrupt flag. More...
it_status_t | ald_i2c_get_it_status (i2c_handle_t *hperh, i2c_interrupt_t it)
Get the status of I2C interrupt source. More...
void | ald_i2c_ev_irq_handler (i2c_handle_t *hperh)
This function handles I2C event interrupt request. More...
void | ald_i2c_er_irq_handler (i2c_handle_t *hperh)
This function handles I2C error interrupt request. More...
void | ald_i2c_interrupt_config (i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state)
Enable/disable the specified I2C interrupts. More...

Detailed Description

Header file of I2C driver.

Version
V1.0
Date
15 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_i2c.h.


ALD User Manual: D:/svn/src/ald_i2s.c File Reference

  • D:
  • svn
  • src
Functions
ald_i2s.c File Reference

I2S module driver. This file provides firmware functions to manage the following functionalities of I2S peripheral: More...

#include "ald_i2s.h"
#include "ald_cmu.h"
Include dependency graph for ald_i2s.c:

Go to the source code of this file.

Functions

static ald_status_t | i2s_wait_status (i2s_handle_t *hperh, i2s_status_t flag, flag_status_t status, uint32_t timeout)
This function wait I2S status until timeout. More...
static void | __i2s_send_by_it (i2s_handle_t *hperh)
handle program when an tx empty interrupt flag arrived in non block mode More...
static void | __i2s_recv_by_it (i2s_handle_t *hperh)
handle program when an rx no empty interrupt flag arrived in non block mode More...
static void | __i2s_tx_recv_by_it (i2s_handle_t *hperh)
handle program when an rx no empty interrupt flag arrived in non block mode More...
static void | i2s_dma_send_cplt (void *arg)
DMA I2S transmit process complete callback. More...
static void | i2s_dma_recv_cplt (void *arg)
DMA I2S receive process complete callback. More...
static void | i2s_dma_error (void *arg)
DMA I2S communication error callback. More...
void | ald_i2s_reset (i2s_handle_t *hperh)
Reset the I2S peripheral. More...
ald_status_t | ald_i2s_init (i2s_handle_t *hperh)
Initializes the I2S mode according to the specified parameters in the i2s_init_t and create the associated handle. More...
ald_status_t | ald_i2s_master_send (i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout)
Master mode transmit an amount of data in blocking mode. More...
ald_status_t | ald_i2s_master_recv (i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout)
Master mode receive an amount of data in blocking mode. More...
ald_status_t | ald_i2s_master_send_by_it (i2s_handle_t *hperh, uint16_t *buf, uint32_t size)
Wraps up master mode transmission in non blocking mode. More...
ald_status_t | ald_i2s_master_recv_by_it (i2s_handle_t *hperh, uint16_t *buf, uint32_t size)
Master mode receives an amount of data in non blocking mode. More...
ald_status_t | ald_i2s_master_send_by_dma (i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t channel)
Master mode transmit an amount of data used dma channel. More...
ald_status_t | ald_i2s_master_recv_by_dma (i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t dma_ch, uint8_t _dma_ch)
Master mode receive an amount of data used dma channel. More...
ald_status_t | ald_i2s_dma_pause (i2s_handle_t *hperh)
Pauses the DMA Transfer. More...
ald_status_t | ald_i2s_dma_resume (i2s_handle_t *hperh)
Resumes the DMA Transfer. More...
ald_status_t | ald_i2s_dma_stop (i2s_handle_t *hperh)
Stops the DMA Transfer. More...
void | ald_i2s_irq_handler (i2s_handle_t *hperh)
This function handles I2S interrupt request. More...
void | ald_i2s_interrupt_config (i2s_handle_t *hperh, i2s_it_t it, type_func_t state)
Enables or disables the specified I2S interrupts. More...
void | ald_i2s_dma_req_config (i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t state)
Enables or disables the dma request. More...
flag_status_t | ald_i2s_get_status (i2s_handle_t *hperh, i2s_status_t status)
Check whether the specified I2S flag is set or not. More...
it_status_t | ald_i2s_get_it_status (i2s_handle_t *hperh, i2s_it_t it)
Checks whether the specified I2S interrupt has occurred or not. More...
flag_status_t | ald_i2s_get_flag_status (i2s_handle_t *hperh, i2s_flag_t flag)
Check whether the specified I2S interrupt flag is set or not. More...
flag_status_t | ald_i2s_get_mask_flag_status (i2s_handle_t *hperh, i2s_flag_t flag)
Check whether the specified I2S interrupt flag is set or not. More...
void | ald_i2s_clear_flag_status (i2s_handle_t *hperh, i2s_flag_t flag)
Clear the specified I2S interrupt flags. More...
i2s_state_t | ald_i2s_get_state (i2s_handle_t *hperh)
Returns the I2S state. More...
uint32_t | ald_i2s_get_error (i2s_handle_t *hperh)
Return the I2S error code. More...

Detailed Description

I2S module driver. This file provides firmware functions to manage the following functionalities of I2S peripheral:

Header file of I2S module driver.

  • Initialization functions
  • IO operation functions
  • Peripheral Control functions
  • Peripheral State functions
Version
V1.0
Date
13 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

==============================================================================
                      ##### How to use this driver #####
==============================================================================
  [..]
    The I2S driver can be used as follows:

    (#) Declare a i2s_handle_t structure, for example:
        i2s_handle_t hperh;

    (#) Initialize the I2S low level resources:
        (##) Enable the I2Sx interface clock
        (##) I2S pins configuration
            (+++) Enable the clock for the I2S GPIOs
            (+++) Configure these I2S pins as push-pull
        (##) NVIC configuration if you need to use interrupt process
             by implementing the ald_mcu_irq_config() API.
             Invoked ald_i2s_irq_handler() function in I2S-IRQ function
        (##) DMA Configuration if you need to use DMA process
            (+++) Define ALD_DMA in ald_conf.h
            (+++) Enable the DMAx clock

    (#) Program the Channel length, Data length, Polarity, Standard, Pcm frame,
        external clock and Main clock output, Odd factor and Divide clock in the i2s_init_t structure.

    (#) Initialize the I2S module by invoking the ald_i2s_init() API.

   [..]
     Circular mode restriction:
    (#) When the I2S DMA Pause/Stop features are used, we must use the following APIs
        the ald_i2s_dma_pause()/ ald_i2s_dma_stop().

*
Version
V1.0
Date
13 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_i2s.c.


ALD User Manual: D:/svn/src/ald_i2s.h File Reference

  • D:
  • svn
  • src
Data Structures | Macros | Typedefs | Enumerations | Functions
ald_i2s.h File Reference
#include "utils.h"
#include "ald_dma.h"
Include dependency graph for ald_i2s.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Data Structures

struct | i2s_init_t
I2S init structure definition. More...
struct | i2s_handle_s
I2S handle structure definition. More...

Macros

#define | I2S_RESET_HANDLE_STATE(x) ((x)->state = I2S_STATE_RESET)
#define | I2S_ENABLE(x) (SET_BIT((x)->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK))
#define | I2S_DISABLE(x) (CLEAR_BIT((x)->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK))
#define | IS_I2S(x)
#define | IS_I2S_CH_LEN(x)
#define | IS_I2S_DATE_LEN(x)
#define | IS_I2S_CPOL(x)
#define | IS_I2S_STANDARD(x)
#define | IS_I2S_PCMS(x)
#define | IS_I2S_IT(x)
#define | IS_I2S_IF(x)
#define | IS_I2S_FLAG(x)
#define | IS_I2S_STATUS(x)
#define | IS_I2S_DMA_REQ(x)

Typedefs

typedef struct i2s_handle_s i2s_handle_t
I2S handle structure definition. More...

Enumerations

enum | i2s_chlen_t { I2S_WIDE_16 = 0x0U, I2S_WIDE_32 = 0x1U }
Channel length. More...
enum | i2s_datalen_t { I2S_LEN_16 = 0x0U, I2S_LEN_24 = 0x1U, I2S_LEN_32 = 0x2U }
Data length. More...
enum | i2s_cpol_t { I2S_INACTIVE_LOW = 0x0U, I2S_INACTIVE_HIGH = 0x1U }
Inactive state clock polarity. More...
enum | i2s_standard_t { I2S_STD_PHI = 0x0U, I2S_STD_MSB = 0x1U, I2S_STD_LSB = 0x2U, I2S_STD_PCM = 0x3U }
I2s standard. More...
enum | i2s_cfg_t { I2S_MASTER_TRANSMIT = 0x2U, I2S_MASTER_RECEIVE = 0x3U }
I2s configuration mode. More...
enum | i2s_pcms_t { I2S_FRAME_SHORT = 0x0U, I2S_FRAME_LONG = 0x1U }
Pcm frame synchronization. More...
enum i2s_error_t {
I2S_ERROR_NONE = 0x0U, I2S_ERROR_MODF = 0x1U, I2S_ERROR_DMA = 0x2U, I2S_ERROR_FRE = 0x4U,
I2S_ERROR_RXOV = 0x8U, I2S_ERROR_TXOV = 0x10U, I2S_ERROR_FLAG = 0x20U
}
I2S error status. More...
enum i2s_it_t {
I2S_IT_TXE = (1U << 0), I2S_IT_TXOV = (1U << 2), I2S_IT_TXUD = (1U << 3), I2S_IT_RXF = (1U << 9),
I2S_IT_RXOV = (1U << 10), I2S_IT_RXUD = (1U << 11), I2S_IT_RXTH = (1U << 12), I2S_IT_CRCERR = (1U << 16),
I2S_IT_MODF = (1U << 17), I2S_IT_FRE = (1U << 18)
}
interrupt control More...
enum | i2s_dma_req_t { I2S_DMA_REQ_TX = 0U, I2S_DMA_REQ_RX = 1U }
I2S dma request definition. More...
enum i2s_flag_t {
I2S_IF_TXE = (1U << 0), I2S_IF_TXOV = (1U << 2), I2S_IF_TXUD = (1U << 3), I2S_IF_RXF = (1U << 9),
I2S_IF_RXOV = (1U << 10), I2S_IF_RXUD = (1U << 11), I2S_IF_RXTH = (1U << 12), I2S_IF_FRE = (1U << 18)
}
interrupt flag More...
enum i2s_state_t {
I2S_STATE_RESET = 0x00U, I2S_STATE_READY = 0x01U, I2S_STATE_BUSY = 0x02U, I2S_STATE_BUSY_TX = 0x11U,
I2S_STATE_BUSY_RX = 0x21U, I2S_STATE_BUSY_TX_RX = 0x31U, I2S_STATE_TIMEOUT = 0x03U, I2S_STATE_ERROR = 0x04U
}
I2S state structures definition. More...
enum i2s_status_t {
I2S_STATUS_TXE = (1U << 0), I2S_STATUS_TXF = (1U << 1), I2S_STATUS_TXOV = (1U << 2), I2S_STATUS_TXUD = (1U << 3),
I2S_STATUS_RXE = (1U << 8), I2S_STATUS_RXF = (1U << 9), I2S_STATUS_RXOV = (1U << 10), I2S_STATUS_RXUD = (1U << 11),
I2S_STATUS_CHSIDE = (1U << 14), I2S_STATUS_BUSY = (1U << 15)
}
I2S status definition. More...
enum | i2s_ch_side_t { I2S_SIDE_LEFT = 0U, I2S_SIDE_RIGHT = 1U }
Channel side. More...
enum | i2s_sr_status_t { I2S_SR_TXE = 0U, I2S_SR_RXNE = 1U, I2S_SR_TXE_RXNE = 2U }
I2S TXE/RXNE status definition. More...

Functions

ald_status_t | ald_i2s_init (i2s_handle_t *hperh)
Initializes the I2S mode according to the specified parameters in the i2s_init_t and create the associated handle. More...
void | ald_i2s_reset (i2s_handle_t *hperh)
Reset the I2S peripheral. More...
ald_status_t | ald_i2s_master_send (i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout)
Master mode transmit an amount of data in blocking mode. More...
ald_status_t | ald_i2s_master_recv (i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout)
Master mode receive an amount of data in blocking mode. More...
ald_status_t | ald_i2s_master_send_by_it (i2s_handle_t *hperh, uint16_t *buf, uint32_t size)
Wraps up master mode transmission in non blocking mode. More...
ald_status_t | ald_i2s_master_recv_by_it (i2s_handle_t *hperh, uint16_t *buf, uint32_t size)
Master mode receives an amount of data in non blocking mode. More...
ald_status_t | ald_i2s_master_send_by_dma (i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t channel)
Master mode transmit an amount of data used dma channel. More...
ald_status_t | ald_i2s_master_recv_by_dma (i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t dma_ch, uint8_t _dma_ch)
Master mode receive an amount of data used dma channel. More...
ald_status_t | ald_i2s_dma_pause (i2s_handle_t *hperh)
Pauses the DMA Transfer. More...
ald_status_t | ald_i2s_dma_resume (i2s_handle_t *hperh)
Resumes the DMA Transfer. More...
ald_status_t | ald_i2s_dma_stop (i2s_handle_t *hperh)
Stops the DMA Transfer. More...
void | ald_i2s_irq_handler (i2s_handle_t *hperh)
This function handles I2S interrupt request. More...
void | ald_i2s_interrupt_config (i2s_handle_t *hperh, i2s_it_t it, type_func_t state)
Enables or disables the specified I2S interrupts. More...
void | ald_i2s_dma_req_config (i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t state)
Enables or disables the dma request. More...
flag_status_t | ald_i2s_get_status (i2s_handle_t *hperh, i2s_status_t status)
Check whether the specified I2S flag is set or not. More...
it_status_t | ald_i2s_get_it_status (i2s_handle_t *hperh, i2s_it_t it)
Checks whether the specified I2S interrupt has occurred or not. More...
flag_status_t | ald_i2s_get_flag_status (i2s_handle_t *hperh, i2s_flag_t flag)
Check whether the specified I2S interrupt flag is set or not. More...
flag_status_t | ald_i2s_get_mask_flag_status (i2s_handle_t *hperh, i2s_flag_t flag)
Check whether the specified I2S interrupt flag is set or not. More...
void | ald_i2s_clear_flag_status (i2s_handle_t *hperh, i2s_flag_t flag)
Clear the specified I2S interrupt flags. More...
i2s_state_t | ald_i2s_get_state (i2s_handle_t *hperh)
Returns the I2S state. More...
uint32_t | ald_i2s_get_error (i2s_handle_t *hperh)
Return the I2S error code. More...


ALD User Manual: D:/svn/src/ald_iap.c File Reference

  • D:
  • svn
  • src
Functions
ald_iap.c File Reference

IAP module driver. More...

#include "ald_iap.h"
Include dependency graph for ald_iap.c:

Go to the source code of this file.

Functions

uint32_t | ald_iap_erase_page (uint32_t addr)
Erases a specified page. More...
uint32_t | ald_iap_program_word (uint32_t addr, uint32_t data)
Programs a word at a specified address. More...
uint32_t | ald_iap_program_dword (uint32_t addr, uint32_t data_l, uint32_t data_h)
Programs double words at a specified address. More...
uint32_t | ald_iap_program_words (uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase)
Programs datas at a specified address. More...

Detailed Description

IAP module driver.

Version
V1.0
Date
04 Dec 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_iap.c.


ALD User Manual: D:/svn/src/ald_iap.h File Reference

  • D:
  • svn
  • src
Macros | Typedefs | Functions
ald_iap.h File Reference

Header file of IAP module driver. More...

#include "utils.h"
Include dependency graph for ald_iap.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | IAP_WSP_ADDR 0x10000000U
#define | IAP_PE_ADDR 0x10000004U
#define | IAP_WP_ADDR 0x10000008U
#define | IAP_DWP_ADDR 0x1000000cU

Typedefs

typedef uint32_t(* | IAP_PE) (uint32_t addr)
typedef uint32_t(* | IAP_WP) (uint32_t addr, uint32_t data)
typedef uint32_t(* | IAP_DWP) (uint32_t addr, uint32_t data_l, uint32_t data_h)
typedef uint32_t(* | IAP_WSP) (uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase)

Functions

uint32_t | ald_iap_erase_page (uint32_t addr)
Erases a specified page. More...
uint32_t | ald_iap_program_word (uint32_t addr, uint32_t data)
Programs a word at a specified address. More...
uint32_t | ald_iap_program_dword (uint32_t addr, uint32_t data_l, uint32_t data_h)
Programs double words at a specified address. More...
uint32_t | ald_iap_program_words (uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase)
Programs datas at a specified address. More...

Detailed Description

Header file of IAP module driver.

Version
V1.0
Date
04 Dec 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_iap.h.


ALD User Manual: D:/svn/src/ald_nand.c File Reference

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  • svn
  • src
Functions
ald_nand.c File Reference

NAND module driver. More...

#include "ald_nand.h"
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Functions

ald_status_t | ald_nand_init (nand_handle_t *hperh, ald_ebi_nand_timing_t *ctiming, ald_ebi_nand_timing_t *atiming)
Perform NAND memory initialization sequence. More...
ald_status_t | ald_nand_deinit (nand_handle_t *hperh)
Perform NAND memory De-Initialization sequence. More...
ald_status_t | ald_nand_reset (nand_handle_t *hperh)
NAND memory reset. More...
void | nand_config_device (nand_handle_t *hperh, nand_device_cfg_t *pdcfg)
configure the device: Enter the physical parameters of the device More...
ald_status_t | ald_nand_read_id (nand_handle_t *hperh, nand_id_t *id)
Read the NAND memory electronic signature. More...
ald_status_t | ald_nand_read_page_8b (nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
Read page(s) from NAND memory block (8-bits addressing) More...
ald_status_t | ald_nand_write_page_8b (nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
Write page(s) to NAND memory block (8-bits addressing) More...
ald_status_t | ald_nand_read_sparearea_8b (nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
Read spare area(s) from NAND memory (8-bits addressing) More...
ald_status_t | ald_nand_write_sparearea_8b (nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
Write spare area(s) to NAND memory (8-bits addressing) More...
ald_status_t | ald_nand_read_page_16b (nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
Read page(s) from NAND memory block (16-bits addressing) More...
ald_status_t | ald_nand_write_page_16b (nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
Write page(s) to NAND memory block (16-bits addressing) More...
ald_status_t | ald_nand_read_sparearea_16b (nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
Read spare area(s) from NAND memory (16-bits addressing) More...
ald_status_t | ald_nand_write_sparearea_16b (nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
Write spare area(s) to NAND memory (16-bits addressing) More...
ald_status_t | ald_nand_erase_block (nand_handle_t *hperh, nand_address_t *addr)
NAND memory Block erase. More...
void | ald_nand_irq_handler (nand_handle_t *hperh)
This function handles NAND device interrupt request. More...
__weak void | ald_nand_irq_cbk (nand_handle_t *hperh)
NAND interrupt feature callback. More...
uint32_t | ald_nand_address_inc (nand_handle_t *hperh, nand_address_t *addr)
Increment the NAND memory address. More...
uint32_t | ald_nand_read_status (nand_handle_t *hperh)
NAND memory read status. More...
ald_nand_state_t | ald_nand_get_state (nand_handle_t *hperh)
return the NAND state More...
ald_status_t | ald_nand_ecc_enable (nand_handle_t *hperh)
Enables dynamically NAND ECC feature. More...
ald_status_t | ald_nand_ecc_disable (nand_handle_t *hperh)
Disables dynamically FSMC_NAND ECC feature. More...
ald_status_t | ald_nand_get_ecc (nand_handle_t *hperh, uint32_t *val, uint32_t timeout)
Disables dynamically NAND ECC feature. More...

Detailed Description

NAND module driver.

Version
V1.0
Date
18 March 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

==============================================================================
                   ##### How to use this driver #####
==============================================================================
  [..]
      This driver is used as follows:
    (#) NAND flash memory configuration sequence using the function ald_nand_init()
        with control and timing parameters for both common and attribute spaces.
    (#) Read NAND flash memory maker and device IDs using the function
        ald_nand_read_id(). The read information is stored in the nand_id_typedef
        structure declared by the function caller.
    (#) Access NAND flash memory by read/write operations using the functions
        ald_nand_read_page_8b()/nand_read_SpareArea_8b(),
        ald_nand_write_page_8b()/ald_nand_write_sparearea_8b(),
        ald_nand_read_page_16b()/ald_nand_read_sparearea_16b(),
        ald_nand_write_page_16b()/ald_nand_write_sparearea_16b()
        to read/write page(s)/spare area(s).
    (#) Perform NAND flash Reset chip operation using the function ald_nand_reset().
    (#) Perform NAND flash erase block operation using the function ald_nand_erase_block().
    (#) Read the NAND flash status operation using the function ald_nand_read_status().
    (#) You can also control the NAND device by calling the control APIs ald_nand_ecc_enable()/
        ald_nand_ecc_disable() to respectively enable/disable the ECC code correction
        feature or the function ald_nand_get_ecc() to get the ECC correction code.

Definition in file ald_nand.c.


ALD User Manual: D:/svn/src/ald_nand.h File Reference

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Data Structures | Macros | Enumerations | Functions
ald_nand.h File Reference

Header file of EBI_NAND module driver. More...

#include "ald_ebi.h"
Include dependency graph for ald_nand.h:
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Data Structures

struct | nand_id_t
NAND Memory electronic signature Structure definition. More...
struct | nand_address_t
NAND Memory address Structure definition. More...
struct | nand_device_cfg_t
NAND Memory info Structure definition. More...
struct | nand_handle_t
NAND handle Structure definition. More...

Macros

#define | NAND_DEVICE1 EBI_BANK2
#define | NAND_DEVICE2 EBI_BANK3
#define | NAND_WRITE_TIMEOUT 1000U
#define | CMD_AREA (1U<<16U) /* A16 = CLE high */
#define | ADDR_AREA (1U<<17U) /* A17 = ALE high */
#define | NAND_CMD_AREA_A ((uint8_t)0x00U)
#define | NAND_CMD_AREA_B ((uint8_t)0x01U)
#define | NAND_CMD_AREA_C ((uint8_t)0x50U)
#define | NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
#define | NAND_CMD_WRITE0 ((uint8_t)0x80U)
#define | NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
#define | NAND_CMD_ERASE0 ((uint8_t)0x60U)
#define | NAND_CMD_ERASE1 ((uint8_t)0xD0U)
#define | NAND_CMD_READID ((uint8_t)0x90U)
#define | NAND_CMD_STATUS ((uint8_t)0x70U)
#define | NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
#define | NAND_CMD_RESET ((uint8_t)0xFFU)
#define | NAND_VALID_ADDRESS 0x00000100U
#define | NAND_INVALID_ADDRESS 0x00000200U
#define | NAND_TIMEOUT_ERROR 0x00000400U
#define | NAND_BUSY 0x00000000U
#define | NAND_ERROR 0x00000001U
#define | NAND_READY 0x00000040U
#define | ARRAY_ADDRESS(x, y)
#define | COLUMN_ADDRESS(x) ((x)->config.page_size)
#define | ADDR_1ST_CYCLE(x) (uint8_t)(x) /* 1st addressing cycle */
#define | ADDR_2ND_CYCLE(x) (uint8_t)((x) >> 8U) /* 2nd addressing cycle */
#define | ADDR_3RD_CYCLE(x) (uint8_t)((x) >> 16U) /* 3rd addressing cycle */
#define | ADDR_4TH_CYCLE(x) (uint8_t)((x) >> 24U) /* 4th addressing cycle */
#define | COLUMN_1ST_CYCLE(x) (uint8_t)(x) /* 1st Column addressing cycle */
#define | COLUMN_2ND_CYCLE(x) (uint8_t)((x) >> 8U) /* 2nd Column addressing cycle */

Enumerations

enum ald_nand_state_t { ALD_NAND_STATE_RESET = 0x00U, ALD_NAND_STATE_READY = 0x01U, ALD_NAND_STATE_BUSY = 0x02U, ALD_NAND_STATE_ERROR = 0x03U }
NAND State structures definition. More...

Functions

ald_status_t | ald_nand_init (nand_handle_t *hperh, ald_ebi_nand_timing_t *ctiming, ald_ebi_nand_timing_t *atiming)
Perform NAND memory initialization sequence. More...
ald_status_t | ald_nand_deinit (nand_handle_t *hperh)
Perform NAND memory De-Initialization sequence. More...
ald_status_t | ald_nand_reset (nand_handle_t *hperh)
NAND memory reset. More...
void | nand_config_device (nand_handle_t *hperh, nand_device_cfg_t *pdcfg)
configure the device: Enter the physical parameters of the device More...
ald_status_t | ald_nand_read_id (nand_handle_t *hperh, nand_id_t *id)
Read the NAND memory electronic signature. More...
ald_status_t | ald_nand_read_page_8b (nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
Read page(s) from NAND memory block (8-bits addressing) More...
ald_status_t | ald_nand_write_page_8b (nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
Write page(s) to NAND memory block (8-bits addressing) More...
ald_status_t | ald_nand_read_sparearea_8b (nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
Read spare area(s) from NAND memory (8-bits addressing) More...
ald_status_t | ald_nand_write_sparearea_8b (nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
Write spare area(s) to NAND memory (8-bits addressing) More...
ald_status_t | ald_nand_read_page_16b (nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
Read page(s) from NAND memory block (16-bits addressing) More...
ald_status_t | ald_nand_write_page_16b (nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
Write page(s) to NAND memory block (16-bits addressing) More...
ald_status_t | ald_nand_read_sparearea_16b (nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
Read spare area(s) from NAND memory (16-bits addressing) More...
ald_status_t | ald_nand_write_sparearea_16b (nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
Write spare area(s) to NAND memory (16-bits addressing) More...
ald_status_t | ald_nand_erase_block (nand_handle_t *hperh, nand_address_t *addr)
NAND memory Block erase. More...
void | ald_nand_irq_handler (nand_handle_t *hperh)
This function handles NAND device interrupt request. More...
__weak void | ald_nand_irq_cbk (nand_handle_t *hperh)
NAND interrupt feature callback. More...
uint32_t | ald_nand_address_inc (nand_handle_t *hperh, nand_address_t *addr)
Increment the NAND memory address. More...
uint32_t | ald_nand_read_status (nand_handle_t *hperh)
NAND memory read status. More...
ald_nand_state_t | ald_nand_get_state (nand_handle_t *hperh)
return the NAND state More...
ald_status_t | ald_nand_ecc_enable (nand_handle_t *hperh)
Enables dynamically NAND ECC feature. More...
ald_status_t | ald_nand_ecc_disable (nand_handle_t *hperh)
Disables dynamically FSMC_NAND ECC feature. More...
ald_status_t | ald_nand_get_ecc (nand_handle_t *hperh, uint32_t *val, uint32_t timeout)
Disables dynamically NAND ECC feature. More...

Detailed Description

Header file of EBI_NAND module driver.

Version
V1.0
Date
07 Dec 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_nand.h.


ALD User Manual: D:/svn/src/ald_nor_lcd.c File Reference

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  • src
Functions | Variables
ald_nor_lcd.c File Reference

EBI_NOR_LCD module driver. More...

#include "ald_nor_lcd.h"
Include dependency graph for ald_nor_lcd.c:

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Functions

ald_status_t | ald_nor_init (nor_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing)
Perform the NOR memory Initialization sequence. More...
ald_status_t | ald_nor_deinit (nor_handle_t *hperh)
Perform NOR memory De-Initialization sequence. More...
ald_status_t | ald_nor_read_id (nor_handle_t *hperh, nor_id_t *id)
Read NOR flash IDs. More...
ald_status_t | ald_nor_return_readmode (nor_handle_t *hperh)
Returns the NOR memory to Read mode. More...
ald_status_t | ald_nor_read (nor_handle_t *hperh, uint32_t *addr, uint16_t *data)
Read data from NOR memory. More...
ald_status_t | ald_nor_program (nor_handle_t *hperh, uint32_t *addr, uint16_t *data)
Program data to NOR memory. More...
ald_status_t | ald_nor_read_buffer (nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size)
Reads a block of data from the EBI NOR memory. More...
ald_status_t | ald_nor_program_buffer (nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size)
Writes a half-word buffer to the EBI NOR memory. More...
ald_status_t | ald_nor_erase_block (nor_handle_t *hperh, uint32_t blkaddr, uint32_t addr)
Erase the specified block of the NOR memory. More...
ald_status_t | ald_nor_erase_chip (nor_handle_t *hperh)
Erase the entire NOR chip. More...
ald_status_t | ald_nor_read_cfi (nor_handle_t *hperh, nor_cfi_t *cfi)
Read NOR flash CFI IDs. More...
ald_status_t | ald_nor_write_enable (nor_handle_t *hperh)
Enables dynamically NOR write operation. More...
ald_status_t | ald_nor_write_disable (nor_handle_t *hperh)
Disables dynamically NOR write operation. More...
ald_nor_state_t | ald_nor_get_state (nor_handle_t *hperh)
return the NOR controller state More...
nor_status_t | ald_nor_get_status (nor_handle_t *hperh, uint32_t addr, uint32_t timeout)
Returns the NOR operation status. More...

Variables

static uint32_t NORMEMDATWIDTH = NOR_MEMORY_8B

Detailed Description

EBI_NOR_LCD module driver.

Version
V1.0
Date
25 Dec 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_nor_lcd.c.


ALD User Manual: D:/svn/src/ald_nor_lcd.h File Reference

  • D:
  • svn
  • src
Data Structures | Macros | Enumerations | Functions
ald_nor_lcd.h File Reference

Header file of EBI_NOR_LCD module driver. More...

#include "ald_ebi.h"
Include dependency graph for ald_nor_lcd.h:
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Data Structures

struct | nor_id_t
EBI NOR ID typedef. More...
struct | nor_cfi_t
EBI NOR CFI typedef. More...
struct | nor_handle_t
NOR handle Structure definition. More...

Macros

#define | MC_ADDRESS ((uint16_t)0x0000U)
#define | DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
#define | DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
#define | DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
#define | CFI1_ADDRESS ((uint16_t)0x10U)
#define | CFI2_ADDRESS ((uint16_t)0x11U)
#define | CFI3_ADDRESS ((uint16_t)0x12U)
#define | CFI4_ADDRESS ((uint16_t)0x13U)
#define | NOR_TMEOUT ((uint16_t)0xFFFFU)
#define | NOR_MEMORY_8B ((uint8_t)0x0U)
#define | NOR_MEMORY_16B ((uint8_t)0x1U)
#define | NOR_MEMORY_ADRESS1 EBI_BANK1_1
#define | NOR_MEMORY_ADRESS2 EBI_BANK1_2
#define | NOR_MEMORY_ADRESS3 EBI_BANK1_3
#define | NOR_MEMORY_ADRESS4 EBI_BANK1_4
#define | NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555U
#define | NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055U
#define | NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AAU
#define | NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555U
#define | NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555U
#define | NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AAU
#define | NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555U
#define | NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0U
#define | NOR_CMD_DATA_FIRST (uint16_t)0x00AAU
#define | NOR_CMD_DATA_SECOND (uint16_t)0x0055U
#define | NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090U
#define | NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0U
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080U
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AAU
#define | NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055U
#define | NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010U
#define | NOR_CMD_DATA_CFI (uint16_t)0x0098U
#define | NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25U
#define | NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29U
#define | NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30U
#define | NOR_MASK_STATUS_DQ5 (uint16_t)0x0020U
#define | NOR_MASK_STATUS_DQ6 (uint16_t)0x0040U
#define | NOR_ADDR_SHIFT(NOR_ADDR, NOR_MEMORY_WIDTH_, ADDRESS)
#define | NOR_WRITE(ADDR, DATA) (*(__IO uint16_t *)((uint32_t)(ADDR)) = (DATA))

Enumerations

enum ald_nor_state_t {
ALD_NOR_STATE_RESET = 0x00U, ALD_NOR_STATE_READY = 0x01U, ALD_NOR_STATE_BUSY = 0x02U, ALD_NOR_STATE_ERROR = 0x03U,
ALD_NOR_STATE_PROTECTED = 0x04U
}
ALD SRAM State structures definition. More...
enum nor_status_t { ALD_NOR_STATUS_SUCCESS = 0U, ALD_NOR_STATUS_ONGOING, ALD_NOR_STATUS_ERROR, ALD_NOR_STATUS_TIMEOUT }
EBI NOR Status typedef. More...

Functions

ald_status_t | ald_nor_init (nor_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing)
Perform the NOR memory Initialization sequence. More...
ald_status_t | ald_nor_deinit (nor_handle_t *hperh)
Perform NOR memory De-Initialization sequence. More...
ald_status_t | ald_nor_read_id (nor_handle_t *hperh, nor_id_t *id)
Read NOR flash IDs. More...
ald_status_t | ald_nor_return_readmode (nor_handle_t *hperh)
Returns the NOR memory to Read mode. More...
ald_status_t | ald_nor_read (nor_handle_t *hperh, uint32_t *addr, uint16_t *data)
Read data from NOR memory. More...
ald_status_t | ald_nor_program (nor_handle_t *hperh, uint32_t *addr, uint16_t *data)
Program data to NOR memory. More...
ald_status_t | ald_nor_read_buffer (nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size)
Reads a block of data from the EBI NOR memory. More...
ald_status_t | ald_nor_program_buffer (nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size)
Writes a half-word buffer to the EBI NOR memory. More...
ald_status_t | ald_nor_erase_block (nor_handle_t *hperh, uint32_t blkaddr, uint32_t addr)
Erase the specified block of the NOR memory. More...
ald_status_t | ald_nor_erase_chip (nor_handle_t *hperh)
Erase the entire NOR chip. More...
ald_status_t | ald_nor_read_cfi (nor_handle_t *hperh, nor_cfi_t *cfi)
Read NOR flash CFI IDs. More...
ald_status_t | ald_nor_write_enable (nor_handle_t *hperh)
Enables dynamically NOR write operation. More...
ald_status_t | ald_nor_write_disable (nor_handle_t *hperh)
Disables dynamically NOR write operation. More...
ald_nor_state_t | ald_nor_get_state (nor_handle_t *hperh)
return the NOR controller state More...
nor_status_t | ald_nor_get_status (nor_handle_t *hperh, uint32_t addr, uint32_t timeout)
Returns the NOR operation status. More...

Detailed Description

Header file of EBI_NOR_LCD module driver.

Version
V1.0
Date
07 Dec 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_nor_lcd.h.


ALD User Manual: D:/svn/src/ald_pis.c File Reference

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Functions
ald_pis.c File Reference

PIS module driver. More...

#include "ald_pis.h"
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Functions

ald_status_t | ald_pis_create (pis_handle_t *hperh)
Create the PIS mode according to the specified parameters in the pis_handle_t and create the associated handle. More...
ald_status_t | ald_pis_destroy (pis_handle_t *hperh)
Destroy the PIS mode according to the specified parameters in the pis_init_t and create the associated handle. More...
ald_status_t | ald_pis_output_start (pis_handle_t *hperh, pis_out_ch_t ch)
Start the PIS output function. More...
ald_status_t | ald_pis_output_stop (pis_handle_t *hperh, pis_out_ch_t ch)
Stop the PIS output function. More...
pis_state_t | ald_pis_get_state (pis_handle_t *hperh)
Returns the PIS state. More...
ald_status_t | ald_pis_modu_config (pis_handle_t *hperh, pis_modulate_config_t *config)
Config the PIS modulate signal function. More...

Detailed Description

PIS module driver.

Version
V1.0
Date
27 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_pis.c.


ALD User Manual: D:/svn/src/ald_pis.h File Reference

  • D:
  • svn
  • src
Data Structures | Macros | Typedefs | Enumerations | Functions
ald_pis.h File Reference

Header file of PIS driver. More...

#include "utils.h"
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Data Structures

struct | pis_init_t
PIS init structure definition. More...
struct | pis_modulate_config_t
PIS modulate config structure definition. More...
struct | pis_handle_s
PIS Handle Structure definition. More...

Macros

#define | IS_PIS(x) (((x) == PIS))
#define | IS_PIS_SRC(x)
#define | IS_PIS_TRIG(x)
#define | IS_PIS_CLOCK(x)
#define | IS_PIS_SIGNAL_MODE(x)
#define | IS_PIS_EDGE(x)
#define | IS_PIS_OUTPUT(x)
#define | IS_PIS_OUPUT_CH(x)
#define | IS_PIS_MODU_TARGET(x)
#define | IS_PIS_MODU_LEVEL(x)
#define | IS_PIS_MODU_SRC(x)
#define | IS_PIS_MODU_CHANNEL(x)

Typedefs

typedef struct pis_handle_s pis_handle_t
PIS Handle Structure definition. More...

Enumerations

enum pis_src_t {
PIS_NON = 0x0U, PIS_GPIO_PIN0 = 0x10U, PIS_GPIO_PIN1 = 0x11U, PIS_GPIO_PIN2 = 0x12U,
PIS_GPIO_PIN3 = 0x13U, PIS_GPIO_PIN4 = 0x14U, PIS_GPIO_PIN5 = 0x15U, PIS_GPIO_PIN6 = 0x16U,
PIS_GPIO_PIN7 = 0x17U, PIS_GPIO_PIN8 = 0x18U, PIS_GPIO_PIN9 = 0x19U, PIS_GPIO_PIN10 = 0x1aU,
PIS_GPIO_PIN11 = 0x1bU, PIS_GPIO_PIN12 = 0x1cU, PIS_GPIO_PIN13 = 0x1dU, PIS_GPIO_PIN14 = 0x1eU,
PIS_GPIO_PIN15 = 0x1fU, PIS_ACMP_OUT0 = 0x30U, PIS_ACMP_OUT1 = 0x31U, PIS_DAC0_CH0 = 0x40U,
PIS_DAC0_CH1 = 0x41U, PIS_ADC0_INSERT = 0x60U, PIS_ADC0_NORMAL = 0x61U, PIS_ADC0_RESERVE = 0x62U,
PIS_LVD = 0x70U, PIS_UART0_RESERVE0 = 0x80U, PIS_UART0_RESERVE1 = 0x81U, PIS_UART0_IRDAOUT = 0x82U,
PIS_UART0_RTSOUT = 0x83U, PIS_UART0_TXOUT = 0x84U, PIS_UART0_SYN_SEND = 0x85U, PIS_UART0_SYN_RECV = 0x86U,
PIS_UART1_RESERVE0 = 0x90U, PIS_UART1_RESERVE1 = 0x91U, PIS_UART1_IRDA = 0x92U, PIS_UART1_RTS = 0x93U,
PIS_UART1_TXOUT = 0x94U, PIS_UART1_SYN_SEND = 0x95U, PIS_UART1_SYN_RECV = 0x96U, PIS_UART2_RESERVE0 = 0xa0U,
PIS_UART2_RESERVE1 = 0xa1U, PIS_UART2_IRDA = 0xa2U, PIS_UART2_RTS = 0xa3U, PIS_UART2_TXOUT = 0xa4U,
PIS_UART2_SYN_SEND = 0xa5U, PIS_UART2_SYN_RECV = 0xa6U, PIS_UART3_RESERVE0 = 0xb1U, PIS_UART3_RESERVE1 = 0xb2U,
PIS_UART3_IRDA = 0xb3U, PIS_UART3_RTS = 0xb4U, PIS_UART3_TXOUT = 0xb5U, PIS_UART3_SYN_SEND = 0xb6U,
PIS_UART3_SYN_RECV = 0xb7U, PIS_UART4_RECV = 0xc0U, PIS_UART4_SEND = 0xc1U, PIS_UART4_TXOUT = 0xc2U,
PIS_UART5_RECV = 0xd0U, PIS_UART5_SEND = 0xd1U, PIS_UART5_TXOUT = 0xd2U, PIS_SPI0_RECV = 0xe0U,
PIS_SPI0_SEND = 0xe1U, PIS_SPI0_NE = 0xe2U, PIS_SPI1_RECV = 0xf0U, PIS_SPI1_SEND = 0xf1U,
PIS_SPI1_NE = 0xf2U, PIS_I2C0_RECV = 0x100U, PIS_I2C0_SEND = 0x101U, PIS_I2C1_RECV = 0x110U,
PIS_I2C1_SEND = 0x111U, PIS_TIMER0_UPDATA = 0x120U, PIS_TIMER0_TRIG = 0x121U, PIS_TIMER0_INPUT_1 = 0x122U,
PIS_TIMER0_OUTPUT_1 = 0x123U, PIS_TIMER0_INPUT_2 = 0x124U, PIS_TIMER0_OUTPUT_2 = 0x125U, PIS_TIMER0_INPUT_3 = 0x126U,
PIS_TIMER0_OUTPUT_3 = 0x127U, PIS_TIMER0_INPUT_4 = 0x128U, PIS_TIMER0_OUTPUT_4 = 0x129U, PIS_TIMER1_UPDATA = 0x130U,
PIS_TIMER1_TRIG = 0x131U, PIS_TIMER1_INPUT_1 = 0x132U, PIS_TIMER1_OUTPUT_1 = 0x133U, PIS_TIMER1_INPUT_2 = 0x134U,
PIS_TIMER1_OUTPUT_2 = 0x135U, PIS_TIMER1_INPUT_3 = 0x136U, PIS_TIMER1_OUTPUT_3 = 0x137U, PIS_TIMER1_INPUT_4 = 0x138U,
PIS_TIMER1_OUTPUT_4 = 0x139U, PIS_TIMER2_UPDATA = 0x140U, PIS_TIMER2_TRIG = 0x141U, PIS_TIMER2_INPUT_1 = 0x142U,
PIS_TIMER2_OUTPUT_1 = 0x143U, PIS_TIMER2_INPUT_2 = 0x144U, PIS_TIMER2_OUTPUT_2 = 0x145U, PIS_TIMER2_INPUT_3 = 0x146U,
PIS_TIMER2_OUTPUT_3 = 0x147U, PIS_TIMER2_INPUT_4 = 0x148U, PIS_TIMER2_OUTPUT_4 = 0x149U, PIS_TIMER3_UPDATA = 0x150U,
PIS_TIMER3_TRIG = 0x151U, PIS_TIMER3_INPUT_1 = 0x152U, PIS_TIMER3_OUTPUT_1 = 0x153U, PIS_TIMER3_INPUT_2 = 0x154U,
PIS_TIMER3_OUTPUT_2 = 0x155U, PIS_TIMER3_INPUT_3 = 0x156U, PIS_TIMER3_OUTPUT_3 = 0x157U, PIS_TIMER3_INPUT_4 = 0x158U,
PIS_TIMER3_OUTPUT_4 = 0x159U, PIS_RTC_CLOCK = 0x160U, PIS_RTC_ALARM = 0x161U, PIS_LPTIMER0_SYN_UPDATA = 0x170U,
PIS_LPTIMER0_ASY_UPDATA = 0x171U, PIS_LPUART0_ASY_RECV = 0x180U, PIS_LPUART0_ASY_SEND = 0x181U, PIS_LPUART0_SYN_RECV = 0x182U,
PIS_LPUART0_SYN_SEND = 0x183U, PIS_DMA = 0x190U, PIS_ADC1_INSERT = 0x1a0U, PIS_ADC1_NORMAL = 0x1a1U,
PIS_ADC1_RESERVE = 0x1a2U
}
Producer entry. More...
enum pis_trig_t {
PIS_CH12_TIMER0_ITR0 = 0x003CU, PIS_CH13_TIMER0_ITR1 = 0x003DU, PIS_CH14_TIMER0_ITR2 = 0x003EU, PIS_CH15_TIMER0_ITR3 = 0x003FU,
PIS_CH12_TIMER1_ITR0 = 0x003CU, PIS_CH13_TIMER1_ITR1 = 0x003DU, PIS_CH14_TIMER1_ITR2 = 0x003EU, PIS_CH15_TIMER1_ITR3 = 0x003FU,
PIS_CH12_TIMER2_ITR0 = 0x003CU, PIS_CH13_TIMER2_ITR1 = 0x003DU, PIS_CH14_TIMER2_ITR2 = 0x003EU, PIS_CH15_TIMER2_ITR3 = 0x003FU,
PIS_CH12_TIMER3_ITR0 = 0x003CU, PIS_CH13_TIMER3_ITR1 = 0x003DU, PIS_CH14_TIMER3_ITR2 = 0x003EU, PIS_CH15_TIMER3_ITR3 = 0x003FU,
PIS_CH6_ADC0_NORMAL = 0x0036U, PIS_CH7_ADC0_INSERT = 0x0037U, PIS_CH0_ADC1_NORMAL = 0x0030U, PIS_CH1_ADC1_INSERT = 0x0031U,
PIS_CH0_LPTIM0_EXT0 = 0x0030U, PIS_CH1_LPTIM0_EXT1 = 0x0031U, PIS_CH2_LPTIM0_EXT2 = 0x0032U, PIS_CH3_LPTIM0_EXT3 = 0x0033U,
PIS_CH4_LPTIM0_EXT4 = 0x0034U, PIS_CH5_LPTIM0_EXT5 = 0x0035U, PIS_CH6_LPTIM0_EXT6 = 0x0036U, PIS_CH7_LPTIM0_EXT7 = 0x0037U,
PIS_CH7_DMA_REQUEST = 0x0037U, PIS_CH15_LPUART0_RXD = 0x081FU, PIS_CH14_UART5_RXD = 0x071EU, PIS_CH13_UART4_RXD = 0x061DU,
PIS_CH12_UART3_RXD = 0x031CU, PIS_CH11_UART2_RXD = 0x021BU, PIS_CH10_UART1_RXD = 0x011AU, PIS_CH9_UART0_RXD = 0x0019U,
PIS_CH8_TIMER3_CH4IN = 0x1B08U, PIS_CH8_TIMER2_CH4IN = 0x1308U, PIS_CH8_SPI1_CLK = 0x0F18U, PIS_CH7_TIMER3_CH3IN = 0x1A07U,
PIS_CH7_TIMER2_CH3IN = 0x1207U, PIS_CH7_SPI1_RX = 0x0E17U, PIS_CH6_TIMER3_CH2IN = 0x1906U, PIS_CH6_TIMER2_CH2IN = 0x1106U,
PIS_CH6_SPI0_CLK = 0x0D16U, PIS_CH5_TIMER3_CH1IN = 0x1805U, PIS_CH5_TIMER2_CH1IN = 0x1005U, PIS_CH5_SPI0_RX = 0x0C15U,
PIS_CH4_TIMER1_CH4IN = 0x0B04U, PIS_CH4_TIMER0_CH4IN = 0x0304U, PIS_CH3_TIMER1_CH3IN = 0x0A03U, PIS_CH3_TIMER0_CH3IN = 0x0203U,
PIS_CH2_TIMER1_CH2IN = 0x0902U, PIS_CH2_TIMER0_CH2IN = 0x0102U, PIS_CH1_TIMER1_CH1IN = 0x0801U, PIS_CH0_TIMER0_CH1IN = 0x0000U,
PIS_CH0_TIMER0_BRKIN = 0x0400U, PIS_CH0_TIMER1_BRKIN = 0x0C00U, PIS_TRIG_RESERVE = 0xFFFFU
}
Consumer entry. More...
enum | pis_clock_t { PIS_CLK_PCLK1 = 0U, PIS_CLK_PCLK2 = 1U, PIS_CLK_SYS = 2U, PIS_CLK_RESERVE = 3U }
Clock select. More...
enum | pis_edge_t { PIS_EDGE_NONE = 0U, PIS_EDGE_UP = 1U, PIS_EDGE_DOWN = 2U, PIS_EDGE_UP_DOWN = 3U }
Level select. More...
enum | pis_output_t { PIS_OUT_LEVEL = 0U, PIS_OUT_PULSE = 1U }
Output style. More...
enum pis_syncsel_t {
PIS_SYN_DIRECT = 0U, PIS_SYN_LEVEL_ASY_APB1 = 1U, PIS_SYN_LEVEL_ASY_APB2 = 2U, PIS_SYN_LEVEL_ASY_AHB = 3U,
PIS_SYN_PULSE_ASY_APB1 = 4U, PIS_SYN_PULSE_ASY_APB2 = 5U, PIS_SYN_PULSE_ASY_AHB = 6U
}
Sync select. More...
enum pis_ch_t {
PIS_CH_0 = 0U, PIS_CH_1 = 1U, PIS_CH_2 = 2U, PIS_CH_3 = 3U,
PIS_CH_4 = 4U, PIS_CH_5 = 5U, PIS_CH_6 = 6U, PIS_CH_7 = 7U,
PIS_CH_8 = 8U, PIS_CH_9 = 9U, PIS_CH_10 = 10U, PIS_CH_11 = 11U,
PIS_CH_12 = 12U, PIS_CH_13 = 13U, PIS_CH_14 = 14U, PIS_CH_15 = 15U
}
Pis channel. More...
enum | pis_out_ch_t { PIS_OUT_CH_0 = 0U, PIS_OUT_CH_1 = 1U, PIS_OUT_CH_2 = 2U, PIS_OUT_CH_3 = 3U }
Pis output channel. More...
enum | pis_con_t { PIS_CON_0 = 0U, PIS_CON_1 = 1U, PIS_CON_NONE = 2U }
Indirect value,no care of it. More...
enum pis_state_t {
PIS_STATE_RESET = 0x00U, PIS_STATE_READY = 0x01U, PIS_STATE_BUSY = 0x02U, PIS_STATE_TIMEOUT = 0x03U,
PIS_STATE_ERROR = 0x04U
}
PIS state structures definition. More...
enum pis_modu_targ_t {
PIS_UART0_TX = 0U, PIS_UART1_TX = 1U, PIS_UART2_TX = 2U, PIS_UART3_TX = 3U,
PIS_LPUART0_TX = 4U
}
PIS modulate target. More...
enum | pis_modu_level_t { PIS_LOW_LEVEL = 0U, PIS_HIGH_LEVEL = 1U }
PIS modulate level. More...
enum pis_modu_src_t {
PIS_SRC_NONE = 0U, PIS_SRC_TIMER0 = 1U, PIS_SRC_TIMER1 = 2U, PIS_SRC_TIMER2 = 3U,
PIS_SRC_TIMER3 = 4U, PIS_SRC_TIMER6 = 5U, PIS_SRC_TIMER7 = 6U, PIS_SRC_LPTIM0 = 7U,
PIS_SRC_BUZ = 8U
}
PIS modulate source. More...
enum | pis_modu_channel_t { PIS_TIMER_CH1 = 0U, PIS_TIMER_CH2 = 1U, PIS_TIMER_CH3 = 2U, PIS_TIMER_CH4 = 3U }
PIS modulate channel. More...
enum | pis_input_sel_t { PIS_NONE_INPUT = 0U, PIS_PORT_INPUT = 1U, PIS_CHAN_INPUT = 2U }
PIS input channel chose. More...

Functions

ald_status_t | ald_pis_create (pis_handle_t *hperh)
Create the PIS mode according to the specified parameters in the pis_handle_t and create the associated handle. More...
ald_status_t | ald_pis_destroy (pis_handle_t *hperh)
Destroy the PIS mode according to the specified parameters in the pis_init_t and create the associated handle. More...
ald_status_t | ald_pis_output_start (pis_handle_t *hperh, pis_out_ch_t ch)
Start the PIS output function. More...
ald_status_t | ald_pis_output_stop (pis_handle_t *hperh, pis_out_ch_t ch)
Stop the PIS output function. More...
pis_state_t | ald_pis_get_state (pis_handle_t *hperh)
Returns the PIS state. More...
ald_status_t | ald_pis_modu_config (pis_handle_t *hperh, pis_modulate_config_t *config)
Config the PIS modulate signal function. More...

Detailed Description

Header file of PIS driver.

Version
V1.0
Date
27 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_pis.h.


ALD User Manual: D:/svn/src/ald_pmu.c File Reference

  • D:
  • svn
  • src
Functions
ald_pmu.c File Reference

PMU module driver. More...

#include "ald_pmu.h"
#include "ald_bkpc.h"
Include dependency graph for ald_pmu.c:

Go to the source code of this file.

Functions

void | ald_lvd_irq_handler (void)
PMU module interrupt handler. More...
void | ald_pmu_stop1_enter (void)
Enter stop1 mode. More...
void | ald_pmu_stop2_enter (void)
Enter stop2 mode. More...
void | ald_pmu_standby_enter (bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
Enter standby mode. More...
void | ald_pmu_ldo_12_config (type_func_t state)
Enable/Disable LDO(1.2V) hold mode. It must be disabled in STOP1. More...
void | ald_pmu_ldo_18_config (pmu_ldo_18_mode_t mode)
Configure LDO(1.8V) mode. More...
flag_status_t | ald_pmu_get_status (pmu_status_t sr)
Get wakup status. More...
void | ald_pmu_clear_status (pmu_status_t sr)
Clear wakup status. More...
void | ald_pmu_perh_power_config (pmu_perh_power_t perh, type_func_t state)
Configure peripheral power. More...
void | ald_pmu_lvd_config (pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state)
Configure lvd using specified parameters. More...

Detailed Description

PMU module driver.

Version
V1.0
Date
04 Dec 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_pmu.c.


ALD User Manual: D:/svn/src/ald_pmu.h File Reference

  • D:
  • svn
  • src
Macros | Enumerations | Functions
ald_pmu.h File Reference

Header file of PMU module driver. More...

#include "utils.h"
#include "ald_syscfg.h"
#include "ald_bkpc.h"
Include dependency graph for ald_pmu.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | PMU_LPSTOP_ENABLE()
#define | PMU_LPSTOP_DISABLE()
#define | PMU_FLASH_MODE_IDLE()
#define | PMU_FLASH_MODE_WAIT()
#define | PMU_MTSTOP_ENABLE()
#define | PMU_MTSTOP_DISABLE()
#define | PMU_VREF_ENABLE()
#define | PMU_VREF_DISABLE()
#define | PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS))
#define | IS_PMU_LP_MODE(x)
#define | IS_PMU_LDO18_MODE(x)
#define | IS_PMU_STATUS(x)
#define | IS_PMU_LVD_VOL_SEL(x)
#define | IS_PMU_LVD_TRIGGER_MODE(x)
#define | IS_PMU_LDO_LPMODE_OUTPUT(x)
#define | IS_PMU_PERH_POWER(x)

Enumerations

enum | pmu_lp_mode_t { PMU_LP_STOP1 = 0x0U, PMU_LP_STOP2 = 0x1U, PMU_LP_STANDBY = 0x2U }
Low power mode. More...
enum | pmu_ldo_18_mode_t { PMU_LDO_18_DRV_HIGH = 0x0U, PMU_LDO_18_DRV_LOW = 0x1U, PMU_LDO_18_HOLD = 0x2U, PMU_LDO_18_OFF = 0x3U }
LDO_18 mode. More...
enum | pmu_status_t { PMU_SR_WUF = (1U << 0), PMU_SR_STANDBYF = (1U << 1), PMU_SR_USBRDY = (1U << 2), PMU_SR_RSTAT = (1U << 3) }
enum pmu_lvd_voltage_sel_t {
PMU_LVD_VOL_SEL_2_2 = 0x0U, PMU_LVD_VOL_SEL_2_4 = 0x1U, PMU_LVD_VOL_SEL_2_6 = 0x2U, PMU_LVD_VOL_SEL_2_8 = 0x3U,
PMU_LVD_VOL_SEL_3_0 = 0x4U, PMU_LVD_VOL_SEL_3_2 = 0x5U, PMU_LVD_VOL_SEL_3_4 = 0x6U, PMU_LVD_VOL_SEL_3_6 = 0x7U,
PMU_LVD_VOL_SEL_3_8 = 0x8U, PMU_LVD_VOL_SEL_4_0 = 0x9U, PMU_LVD_VOL_SEL_4_2 = 0xAU, PMU_LVD_VOL_SEL_4_4 = 0xBU,
PMU_LVD_VOL_SEL_4_6 = 0xCU, PMU_LVD_VOL_SEL_4_8 = 0xDU, PMU_LVD_VOL_SEL_EXT = 0xFU
}
LVD voltage select. More...
enum pmu_lvd_trigger_mode_t {
PMU_LVD_TRIGGER_RISING_EDGE = 0x0U, PMU_LVD_TRIGGER_FALLING_EDGE = 0x1U, PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2U, PMU_LVD_TRIGGER_LOW_LEVEL = 0x3U,
PMU_LVD_TRIGGER_RISING_FALLING = 0x4U
}
LVD trigger mode. More...
enum | pmu_ldo_lpmode_output_t { PMU_LDO_LPMODE_OUTPUT_0_9 = 0x0U, PMU_LDO_LPMODE_OUTPUT_1_0 = 0x1U, PMU_LDO_LPMODE_OUTPUT_1_1 = 0x2U, PMU_LDO_LPMODE_OUTPUT_1_2 = 0x3U }
LDO output voltage selest in low power mode. More...
enum pmu_perh_power_t {
PMU_POWER_SRAM0 = 0x1U, PMU_POWER_SRAM1 = 0x2U, PMU_POWER_SRAM2 = 0x4U, PMU_POWER_SRAM3 = 0x8U,
PMU_POWER_SRAM4 = 0x10U, PMU_POWER_SRAM5 = 0x20U, PMU_POWER_CAN = 0x100U, PMU_POWER_QSPI = 0x400U,
PMU_POWER_USB = 0x800U, PMU_POWER_ROM = 0x1000U
}

Functions

__STATIC_INLINE__ void | ald_pmu_sleep ()
__STATIC_INLINE__ void | ald_pmu_sleep_deep ()
void | ald_pmu_stop1_enter (void)
Enter stop1 mode. More...
void | ald_pmu_stop2_enter (void)
Enter stop2 mode. More...
void | ald_pmu_standby_enter (bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
Enter standby mode. More...
void | ald_pmu_ldo_12_config (type_func_t state)
Enable/Disable LDO(1.2V) hold mode. It must be disabled in STOP1. More...
void | ald_pmu_ldo_18_config (pmu_ldo_18_mode_t mode)
Configure LDO(1.8V) mode. More...
flag_status_t | ald_pmu_get_status (pmu_status_t sr)
Get wakup status. More...
void | ald_pmu_clear_status (pmu_status_t sr)
Clear wakup status. More...
void | ald_pmu_perh_power_config (pmu_perh_power_t perh, type_func_t state)
Configure peripheral power. More...
void | ald_pmu_lvd_config (pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state)
Configure lvd using specified parameters. More...
void | ald_lvd_irq_handler (void)
PMU module interrupt handler. More...

Detailed Description

Header file of PMU module driver.

Version
V1.0
Date
04 Dec 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_pmu.h.


ALD User Manual: D:/svn/src/ald_qspi.c File Reference

  • D:
  • svn
  • src
Functions
ald_qspi.c File Reference

QSPI module driver. More...

#include "ald_qspi.h"
Include dependency graph for ald_qspi.c:

Go to the source code of this file.

Functions

static ald_status_t | qspi_wait_for_idle (qspi_handle_t *hperh, uint32_t tickstart, uint32_t timeout)
Wait for a flag state until timeout. More...
static flag_status_t | qspi_indrd_get_status (qspi_handle_t *hperh, qspi_indrd_flag_t status)
Get indirect read status. More...
void | ald_qspi_init (qspi_handle_t *hperh)
Initializes the QSPI basic parameters. More...
uint32_t | ald_qspi_dac_rd (uint32_t addr)
DAC read. More...
void | ald_qspi_dac_wr (uint32_t addr, uint32_t dat)
DAC write . More...
ald_status_t | ald_qspi_read_config (qspi_handle_t *hperh, const qspi_read_cfg_t *rdcfg)
Configure Read Operations. More...
ald_status_t | ald_qspi_write_config (qspi_handle_t *hperh, const qspi_write_cfg_t *wrcfg)
Configure Write Operations. More...
ald_status_t | ald_qspi_device_delay_config (qspi_handle_t *hperh, qspi_dly_cfg_t *dlycfg)
QSPI Device Delay Configuration. More...
ald_status_t | ald_qspi_read_data_capture_config (qspi_handle_t *hperh, qspi_data_capture_cfg_t *dtcptcfg)
QSPI Read Data Capture Configuration. More...
ald_status_t | ald_qspi_device_size_config (qspi_handle_t *hperh, qspi_device_size_t *devcfg)
QSPI Flash memory Configuration. More...
ald_status_t | qspi_dac_config (qspi_handle_t *hperh, qspi_dac_cfg_t *dcfg)
Initializes the QSPI direct access according to the specified parameters in the associated handle. More...
ald_status_t | ald_qspi_indac_config (qspi_handle_t *hperh, qspi_indac_cfg_t *indcfg)
Initializes the QSPI indirect access according to the specified parameters in the associated handle. More...
ald_status_t | ald_qspi_indac_transmit_by_it (qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size)
QSPI write data by interrupt. More...
ald_status_t | ald_qspi_indac_transmit_by_poll (qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size)
Transmit data to flash by poll. More...
ald_status_t | ald_qspi_indac_read_by_poll (qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size)
Read data from flash by poll. More...
ald_status_t | ald_qspi_indac_read_by_it (qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size)
QSPI read data by interrupt. More...
ald_status_t | ald_qspi_execute_stig_cmd (qspi_handle_t *hperh, const qspi_stig_cmd_t *stigcmd)
Execute a STIG command. More...
ald_status_t | ald_qspi_indac_transmit_by_dma (qspi_handle_t *hperh, uint32_t addr, uint8_t *psrc, uint16_t size)
Sends an amount of data with DMA. More...
ald_status_t | ald_qspi_indac_read_by_dma (qspi_handle_t *hperh, uint32_t addr, uint8_t *pdbuf, uint16_t size)
Receive an amount of data with DMA. More...
flag_status_t | qspi_get_flag_status (qspi_handle_t *hperh, qspi_flag_t flag)
Get the status of QSPI interrupt flag. More...
void | ald_qspi_clear_it_flag (qspi_handle_t *hperh, qspi_flag_t flag)
Clear the QSPI interrupt flag. More...
uint16_t | qspi_read_sram_fill_level (qspi_handle_t *hperh, qspi_sram_t srt)
Read QSPI SRAM fill level. More...
void | ald_qspi_write_proect_config (qspi_handle_t *hperh, qspi_wr_protect_t *wpcfg)
QSPI Write Protect Configuration. More...
void | ald_qspi_write_proect_inverse (qspi_handle_t *hperh, type_func_t state)
QSPI Write Protect Inversion. More...
void | ald_qspi_irq_handler (qspi_handle_t *hperh)
QSPI interrupt handler. More...
void | ald_qspi_interrupt_config (qspi_handle_t *hperh, qspi_it_t it, type_func_t state)
Enable/disable the specified QSPI interrupts. More...
void | ald_qspi_legacy_config (qspi_handle_t *hperh, const qspi_legacy_cfg_t *config)
Configure the QSPI legacy . More...
flag_status_t | qspi_indwr_get_status (qspi_handle_t *hperh, qspi_indwr_status_t status)
Get QSPI indirect write access status. More...
ald_status_t | qspi_indwr_wait_flag (qspi_handle_t *hperh, qspi_indwr_status_t flag, flag_status_t status, uint32_t timeout)
Wait indirect wriet a flag state until time out. More...
ald_status_t | qspi_indrd_wait_flag (qspi_handle_t *hperh, qspi_indrd_flag_t flag, flag_status_t status, uint32_t timeout)
QSPI Indirect read operation wait for specified status. More...
void | qspi_clear_flag_status (qspi_handle_t *hperh, qspi_flag_t flag)
Clear the QSPI interrupt flag. More...

Detailed Description

QSPI module driver.

Version
V1.0
Date
09 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_qspi.c.


ALD User Manual: D:/svn/src/ald_qspi.h File Reference

  • D:
  • svn
  • src
Data Structures | Macros | Enumerations | Functions
ald_qspi.h File Reference

Header file of QSPI module driver. More...

#include "utils.h"
#include "ald_dma.h"
Include dependency graph for ald_qspi.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Data Structures

struct | qspi_device_size_t
Qspi external flash device configuration. More...
struct | qspi_wr_protect_t
Flash write-protected blocks configuration. More...
struct | qspi_stig_cmd_t
QSPI STIG Command Structure. More...
struct | qspi_init_t
QSPI base initialization structure. More...
struct | qspi_legacy_cfg_t
QSPI legacy initialization structure. More...
struct | qspi_read_cfg_t
QSPI Device Read Instruction Configuration structure. More...
struct | qspi_write_cfg_t
QSPI Device Write Instruction Configuration structure. More...
struct | qspi_indac_wr_cfg_t
QSPI Indirect Configuration structure.involatile parameters. More...
struct | qspi_indac_rd_cfg_t
struct | qspi_indac_cfg_t
struct | qspi_dac_cfg_t
QSPI DAC configuration. More...
struct | qspi_handle_t
QSPI Handle Structure definition. More...
struct | qspi_dly_cfg_t
Defines command to be executed using STIG mechanism. More...
struct | qspi_data_capture_cfg_t
QSPI Read Data Capture Configuration. More...
struct | qspi_auto_poll_t
QSPI Auto Poll Configuration Struction. More...

Macros

#define | IS_QSPI_SRAM_PARTITION(x) ((x) < 255)
#define | IS_QSPI_INDIRECT_TRIGGER_RANGE(x) (((x) < 16))
#define | IS_QSPI_INDIRECT_READ_WATERMARK(x) ((x) < 512)
#define | IS_QSPI_INDIRECT_SRAM_FILL_TYPE(x) (((x) == QSPI_SRAM_RD) || ((x) == QSPI_SRAM_WR))
#define | IS_QSPI_INDIRECT_READ_STATUS(x) (((x) == QSPI_INDRD_PROGRESS) || ((x) == QSPI_RD_CPLT))
#define | IS_QSPI_INDIRECT_WRITE_STATUS(x) (((x) == QSPI_INDWR_PROGRESS) || ((x) == QSPI_INDWR_CPLT))
#define | IS_QSPI_DEVICE_DELAY_CCSOT(x) ((x) < 256)
#define | IS_QSPI_DEVICE_DELAY_CSEOT(x) ((x) < 256)
#define | IS_QSPI_DEVICE_DELAY_CSDADS(x) ((x) < 256)
#define | IS_QSPI_DEVICE_DELAY_CSDA(x) ((x) < 256)
#define | IS_QSPI_READ_DATA_CAPTURE_DELAY_READ(x) ((x) < 16)
#define | IS_QSPI_READ_DATA_SAMPLE_EDGE(x)
#define | IS_QSPI_READ_DATA_DELAY_TRANSMIT(x) ((x) < 16)
#define | IS_QSPI_ALL(x) ((x) == QSPI)
#define | IS_QSPI_DCYLES(x) ((x) <= 31)
#define | IS_QSPI_ADDR_SIZE(x) ((x) <= 15)
#define | IS_QSPI_PAGE_SIZE(x) ((x) <= 0xfff)
#define | IS_QSPI_BLOCK_SIZE(x) ((x) <= 0x1f)
#define | IS_QSPI_NSS_SIZE(x) ((x) <= 3)
#define | IS_QSPI_XFER_TYPE(x)
#define | IS_QSPI_DDR_BIT_ENABLE(x)
#define | IS_QSPI_MODE_BIT_ENABLE(x)
#define | IS_QSPI_RD_OPCODE(x) (((x) < 0xFF))
#define | IS_QSPI_WR_OPCODE(x) (((x) < 0xFF))
#define | IS_QSPI_CLOCK_PRESCALER(x)
#define | IS_QSPI_CLOCK_PHASE(x)
#define | IS_QSPI_CLOCK_POLARITY(x)
#define | IS_QSPI_IF(x)
#define | IS_QSPI_IT(x)
#define | QSPI_MEMORY_ADDRESS 0x90000000U
#define | QSPI_SRAM_SIZE 255U
#define | QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5s */
#define | QSPI_SRAM_DEPTH 0xFFU
#define | QSPI_DAC_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_DACEN_MSK)
#define | QSPI_DAC_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_DACEN_MSK)
#define | QSPI_LEGACY_SPI_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_LIMEN_MSK)
#define | QSPI_LEGACY_SPI_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_LIMEN_MSK)
#define | QSPI_WRITE_PROTECT_ENABLE(hperh) SET_BIT((hperh)->perh->WPCR, QSPI_WPCR_WPEN_MSK);
#define | QSPI_WRITE_PROTECT_DISABLE(hperh) CLEAR_BIT((hperh)->perh->WPCR, QSPI_WPCR_WPEN_MSK);
#define | QSPI_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_EN_MSK)
#define | QSPI_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_EN_MSK)
#define | QSPI_AUTO_POLL_ENABLE(hperh) CLEAR_BIT((hperh)->perh->WCR, QSPI_WCR_PDIS_MSK)
#define | QSPI_AUTO_POLL_DISABLE(hperh) SET_BIT((hperh)->perh->WCR, QSPI_WCR_PDIS_MSK)
#define | QSPI_DMA_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_DMAEN_MSK)
#define | QSPI_DMA_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_DMAEN_MSK)
#define | QSPI_CANCEL_INDIRECT_READ(hperh) SET_BIT((hperh)->perh->IRTR, QSPI_IRTR_RDDIS_MSK)

Enumerations

enum | qspi_state_t { QSPI_STATE_BUSY_TX = 0x11U, QSPI_STATE_BUSY_RX = 0x21U }
ALD QSPI state. More...
enum | qspi_xfer_t { QSPI_XFER_SINGLE = 0x00U, QSPI_XFER_DUAL = 0x01U, QSPI_XFER_QUAD = 0x02U }
QSPI Instruction Transfer Type. More...
enum | qspi_sram_t { QSPI_SRAM_RD = 0U, QSPI_SRAM_WR = 1U }
QSPI Indirect Access SRAM fill level. More...
enum | qspi_cpha_t { QSPI_CPHA_1E = 0U, QSPI_CPHA_2E = 1U }
QSPI Clock Phase. More...
enum | qspi_cpol_t { QSPI_CPOL_L = 0U, QSPI_CPOL_H = 1U }
QSPI_Clock_Polarity QSPI Clock Polarity. More...
enum | qspi_nss_decode_t { QSPI_SINGLE_CHIP = 0x0U, QSPI_MULTI_CHIP = 0x1U }
QSPI peripheral select decode. More...
enum qspi_clk_div_t {
QSPI_DIV_2 = 0x0U, QSPI_DIV_4 = 0x1U, QSPI_DIV_6 = 0x2U, QSPI_DIV_8 = 0x3U,
QSPI_DIV_10 = 0x4U, QSPI_DIV_12 = 0x5U, QSPI_DIV_14 = 0x6U, QSPI_DIV_16 = 0x7U,
QSPI_DIV_18 = 0x8U, QSPI_DIV_20 = 0x9U, QSPI_DIV_22 = 0xAU, QSPI_DIV_24 = 0xBU,
QSPI_DIV_26 = 0xCU, QSPI_DIV_28 = 0xDU, QSPI_DIV_30 = 0xEU, QSPI_DIV_32 = 0xFU
}
QSPI_Baud_Rate_Clock_Prescaler QSPI Baud Rate Clock Prescaler. More...
enum | qspi_nss_t { QSPI_CS_NSS0 = 0x0U, QSPI_CS_NSS1 = 0x1U, QSPI_CS_NSS2 = 0x3U, QSPI_CS_NSS3 = 0x7U }
QSPI Peripheral chip select decode. More...
enum | qspi_nss_size_t { QSPI_NSS_512M = 0x0U, QSPI_NSS_1G = 0x1U, QSPI_NSS_2G = 0x2U, QSPI_NSS_4G = 0x3U }
Size of flash connected to CS[x](x = 0 ~ 3)pin. More...
enum | qspi_data_sampled_t { QSPI_FALLING_E = 0x0U, QSPI_RISING_E = 0x1U }
QSPI Sample Edge Selection. More...
enum | qspi_indwr_status_t { QSPI_INDWR_PROGRESS = (1U << 2), QSPI_INDWR_CPLT = (1U << 5) }
QSPI Indirect Write Progress Status. More...
enum | qspi_indrd_flag_t { QSPI_INDRD_PROGRESS = (1U << 2), QSPI_RD_CPLT = (1U << 5) }
QSPI Indirect Read Progress Status. More...
enum qspi_it_t {
QSPI_IT_POLLF = (1U << 13), QSPI_IT_INDRSFF = (1U << 12), QSPI_IT_SRFFF = (1U << 11), QSPI_IT_SRFNEF = (1U << 10),
QSPI_IT_STFFF = (1U << 9), QSPI_IT_STFNFF = (1U << 8), QSPI_IT_ROVF = (1U << 7), QSPI_IT_INDTWF = (1U << 6),
QSPI_IT_AHBAEF = (1U << 5), QSPI_IT_WPAF = (1U << 4), QSPI_IT_INDRRF = (1U << 3), QSPI_IT_INDCF = (1U << 2),
QSPI_IT_UDFF = (1U << 1), QSPI_IT_MODFF = (1U << 0)
}
QSPI_Interrupt_definition QSPI Interrupt Definition. More...
enum qspi_flag_t {
QSPI_IF_POLLF = (1U << 13), QSPI_IF_INDRSFF = (1U << 12), QSPI_IF_SRFFF = (1U << 11), QSPI_IF_SRFNEF = (1U << 10),
QSPI_IF_STFFF = (1U << 9), QSPI_IF_STFNFF = (1U << 8), QSPI_IF_ROVF = (1U << 7), QSPI_IF_INDTWF = (1U << 6),
QSPI_IF_AHBAEF = (1U << 5), QSPI_IF_WPAF = (1U << 4), QSPI_IF_INDRRF = (1U << 3), QSPI_IF_INDCF = (1U << 2),
QSPI_IF_UDFF = (1U << 1), QSPI_IF_MODFF = (1U << 0)
}
QSPI_Flag_definition QSPI Flag Definition. More...

Functions

void | ald_qspi_init (qspi_handle_t *hperh)
Initializes the QSPI basic parameters. More...
uint32_t | ald_qspi_dac_rd (uint32_t addr)
DAC read. More...
void | ald_qspi_dac_wr (uint32_t addr, uint32_t dat)
DAC write . More...
ald_status_t | ald_qspi_read_config (qspi_handle_t *hperh, const qspi_read_cfg_t *rdcfg)
Configure Read Operations. More...
ald_status_t | ald_qspi_write_config (qspi_handle_t *hperh, const qspi_write_cfg_t *wrcfg)
Configure Write Operations. More...
ald_status_t | ald_qspi_device_delay_config (qspi_handle_t *hperh, qspi_dly_cfg_t *dlycfg)
QSPI Device Delay Configuration. More...
ald_status_t | ald_qspi_read_data_capture_config (qspi_handle_t *hperh, qspi_data_capture_cfg_t *dtcptcfg)
QSPI Read Data Capture Configuration. More...
ald_status_t | ald_qspi_device_size_config (qspi_handle_t *hperh, qspi_device_size_t *devcfg)
QSPI Flash memory Configuration. More...
ald_status_t | qspi_dac_config (qspi_handle_t *hperh, qspi_dac_cfg_t *dcfg)
Initializes the QSPI direct access according to the specified parameters in the associated handle. More...
ald_status_t | ald_qspi_indac_config (qspi_handle_t *hperh, qspi_indac_cfg_t *indcfg)
Initializes the QSPI indirect access according to the specified parameters in the associated handle. More...
ald_status_t | ald_qspi_indac_transmit_by_it (qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size)
QSPI write data by interrupt. More...
ald_status_t | ald_qspi_indac_transmit_by_poll (qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size)
Transmit data to flash by poll. More...
ald_status_t | ald_qspi_indac_read_by_poll (qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size)
Read data from flash by poll. More...
ald_status_t | ald_qspi_indac_read_by_it (qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size)
QSPI read data by interrupt. More...
ald_status_t | ald_qspi_execute_stig_cmd (qspi_handle_t *hperh, const qspi_stig_cmd_t *stigcmd)
Execute a STIG command. More...
ald_status_t | ald_qspi_indac_transmit_by_dma (qspi_handle_t *hperh, uint32_t addr, uint8_t *psrc, uint16_t size)
Sends an amount of data with DMA. More...
ald_status_t | ald_qspi_indac_read_by_dma (qspi_handle_t *hperh, uint32_t addr, uint8_t *pdbuf, uint16_t size)
Receive an amount of data with DMA. More...
flag_status_t | qspi_get_flag_status (qspi_handle_t *hperh, qspi_flag_t flag)
Get the status of QSPI interrupt flag. More...
void | ald_qspi_clear_it_flag (qspi_handle_t *hperh, qspi_flag_t flag)
Clear the QSPI interrupt flag. More...
uint16_t | qspi_read_sram_fill_level (qspi_handle_t *hperh, qspi_sram_t srt)
Read QSPI SRAM fill level. More...
void | ald_qspi_write_proect_config (qspi_handle_t *hperh, qspi_wr_protect_t *wpcfg)
QSPI Write Protect Configuration. More...
void | ald_qspi_write_proect_inverse (qspi_handle_t *hperh, type_func_t state)
QSPI Write Protect Inversion. More...
ald_status_t | ald_qspi_auto_poll (qspi_handle_t *hperh, qspi_auto_poll_t *apcfg)
void | ald_qspi_irq_handler (qspi_handle_t *hperh)
QSPI interrupt handler. More...
void | ald_qspi_interrupt_config (qspi_handle_t *hperh, qspi_it_t it, type_func_t state)
Enable/disable the specified QSPI interrupts. More...
void | ald_qspi_legacy_config (qspi_handle_t *hperh, const qspi_legacy_cfg_t *config)
Configure the QSPI legacy . More...
flag_status_t | qspi_indwr_get_status (qspi_handle_t *hperh, qspi_indwr_status_t status)
Get QSPI indirect write access status. More...
ald_status_t | qspi_indwr_wait_flag (qspi_handle_t *hperh, qspi_indwr_status_t flag, flag_status_t status, uint32_t timeout)
Wait indirect wriet a flag state until time out. More...

Detailed Description

Header file of QSPI module driver.

Version
V1.0
Date
09 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_qspi.h.


ALD User Manual: D:/svn/src/ald_rmu.c File Reference

  • D:
  • svn
  • src
Functions
ald_rmu.c File Reference

RMU module driver. More...

#include "ald_rmu.h"
#include "ald_syscfg.h"
Include dependency graph for ald_rmu.c:

Go to the source code of this file.

Functions

void | ald_rmu_bor_config (rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state)
Configure BOR parameters. More...
uint32_t | ald_rmu_get_reset_status (rmu_state_t state)
Get specified reset status. More...
void | ald_rmu_clear_reset_status (rmu_state_t state)
Clear the specified reset status. More...
void | ald_rmu_reset_periperal (rmu_peripheral_t perh)
Reset peripheral device. More...

Detailed Description

RMU module driver.

Version
V1.0
Date
04 Dec 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_rmu.c.


ALD User Manual: D:/svn/src/ald_rmu.h File Reference

  • D:
  • svn
  • src
Macros | Enumerations | Functions
ald_rmu.h File Reference

Header file of RMU module driver. More...

#include "utils.h"
Include dependency graph for ald_rmu.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | IS_RMU_BORFLT(x)
#define | IS_RMU_BORVOL(x)
#define | IS_RMU_STATE(x)
#define | IS_RMU_STATE_CLEAR(x)
#define | IS_RMU_PERH(x)

Enumerations

enum rmu_bor_filter_t {
RMU_BORFLT_1 = 0x1U, RMU_BORFLT_2 = 0x2U, RMU_BORFLT_3 = 0x3U, RMU_BORFLT_4 = 0x4U,
RMU_BORFLT_5 = 0x5U, RMU_BORFLT_6 = 0x6U, RMU_BORFLT_7 = 0x7U
}
RMU BOR fliter. More...
enum rmu_bor_vol_t {
RMU_VOL_NONE = 0x0U, RMU_VOL_2_0 = 0x1U, RMU_VOL_2_2 = 0x2U, RMU_VOL_2_4 = 0x3U,
RMU_VOL_2_6 = 0x4U, RMU_VOL_2_8 = 0x5U, RMU_VOL_3_0 = 0x6U, RMU_VOL_3_2 = 0x7U,
RMU_VOL_3_4 = 0x8U, RMU_VOL_3_6 = 0x9U, RMU_VOL_3_8 = 0xAU, RMU_VOL_4_0 = 0xBU,
RMU_VOL_4_2 = 0xCU, RMU_VOL_4_4 = 0xDU, RMU_VOL_4_6 = 0xEU, RMU_VOL_4_8 = 0xFU
}
RMU BOR voltage. More...
enum rmu_state_t {
RMU_RST_POR = (1U << 0), RMU_RST_WAKEUP = (1U << 1), RMU_RST_BOR = (1U << 2), RMU_RST_NMRST = (1U << 3),
RMU_RST_IWDT = (1U << 4), RMU_RST_WWDT = (1U << 5), RMU_RST_LOCKUP = (1U << 6), RMU_RST_CHIP = (1U << 7),
RMU_RST_MCU = (1U << 8), RMU_RST_CPU = (1U << 9), RMU_RST_CFG = (1U << 10), RMU_RST_CFGERR = (1U << 16),
RMU_RST_ALL = (0xFFFFFU)
}
RMU reset status. More...
enum rmu_peripheral_t {
RMU_PERH_GPIO = (1U << 0), RMU_PERH_CRC = (1U << 1), RMU_PERH_CALC = (1U << 2), RMU_PERH_CRYPT = (1U << 3),
RMU_PERH_TRNG = (1U << 4), RMU_PERH_PIS = (1U << 5), RMU_PERH_USB = (1U << 10), RMU_PERH_ECC = (1U << 11),
RMU_PERH_CHIP = (1U << 0) | (1U << 27), RMU_PERH_CPU = (1U << 1) | (1U << 27), RMU_PERH_EBI = (1U << 8) | (1U << 27), RMU_PERH_TIMER0 = (1U << 0) | (1U << 28),
RMU_PERH_TIMER1 = (1U << 1) | (1U << 28), RMU_PERH_TIMER2 = (1U << 2) | (1U << 28), RMU_PERH_TIMER3 = (1U << 3) | (1U << 28), RMU_PERH_TIMER4 = (1U << 4) | (1U << 28),
RMU_PERH_TIMER5 = (1U << 5) | (1U << 28), RMU_PERH_TIMER6 = (1U << 6) | (1U << 28), RMU_PERH_TIMER7 = (1U << 7) | (1U << 28), RMU_PERH_UART0 = (1U << 8) | (1U << 28),
RMU_PERH_UART1 = (1U << 9) | (1U << 28), RMU_PERH_UART2 = (1U << 10) | (1U << 28), RMU_PERH_UART3 = (1U << 11) | (1U << 28), RMU_PERH_UART4 = (1U << 12) | (1U << 28),
RMU_PERH_UART5 = (1U << 13) | (1U << 28), RMU_PERH_SPI0 = (1U << 16) | (1U << 28), RMU_PERH_SPI1 = (1U << 17) | (1U << 28), RMU_PERH_SPI2 = (1U << 18) | (1U << 28),
RMU_PERH_I2C0 = (1U << 20) | (1U << 28), RMU_PERH_I2C1 = (1U << 21) | (1U << 28), RMU_PERH_CAN0 = (1U << 24) | (1U << 28), RMU_PERH_QSPI = (1U << 25) | (1U << 28),
RMU_PERH_LPTIM0 = (1U << 0) | (1U << 29), RMU_PERH_LPUART0 = (1U << 2) | (1U << 29), RMU_PERH_ADC0 = (1U << 4) | (1U << 29), RMU_PERH_ADC1 = (1U << 5) | (1U << 29),
RMU_PERH_ACMP0 = (1U << 6) | (1U << 29), RMU_PERH_ACMP1 = (1U << 7) | (1U << 29), RMU_PERH_OPAMP = (1U << 8) | (1U << 29), RMU_PERH_DAC0 = (1U << 9) | (1U << 29),
RMU_PERH_ACMP2 = (1U << 11) | (1U << 29), RMU_PERH_WWDT = (1U << 12) | (1U << 29), RMU_PERH_LCD = (1U << 13) | (1U << 29), RMU_PERH_IWDT = (1U << 14) | (1U << 29),
RMU_PERH_RTC = (1U << 15) | (1U << 29), RMU_PERH_TSENSE = (1U << 16) | (1U << 29), RMU_PERH_BKPC = (1U << 17) | (1U << 29), RMU_PERH_BKPRAM = (1U << 18) | (1U << 29)
}
RMU periperal select bit. More...

Functions

void | ald_rmu_bor_config (rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state)
Configure BOR parameters. More...
uint32_t | ald_rmu_get_reset_status (rmu_state_t state)
Get specified reset status. More...
void | ald_rmu_clear_reset_status (rmu_state_t state)
Clear the specified reset status. More...
void | ald_rmu_reset_periperal (rmu_peripheral_t perh)
Reset peripheral device. More...

Detailed Description

Header file of RMU module driver.

Version
V1.0
Date
04 Dec 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_rmu.h.


ALD User Manual: D:/svn/src/ald_rtc.c File Reference

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  • svn
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Functions
ald_rtc.c File Reference

RTC module driver. This file provides firmware functions to manage the following functionalities of the RTC peripheral: More...

#include "ald_rtc.h"
#include "ald_bkpc.h"
#include "ald_tsense.h"
#include "ald_syscfg.h"
Include dependency graph for ald_rtc.c:

Go to the source code of this file.

Functions

static uint32_t | bcd_to_dec (uint32_t bcd)
Converts form 2 digit BCD to Binary. More...
static uint32_t | dec_to_bcd (uint32_t dec)
Converts a 2 digit decimal to BCD format. More...
static int32_t | rtc_consistency_check (rtc_time_t *t_last, rtc_date_t *d_last, rtc_time_t *time, rtc_date_t *date)
Time and Date consistency check. More...
void | ald_rtc_reset (void)
Reset RTC register. More...
void | ald_rtc_init (rtc_init_t *init)
Initialize the RTC module. More...
void | ald_rtc_source_select (rtc_source_sel_t sel)
Configure the RTC source. More...
ald_status_t | ald_rtc_set_time (rtc_time_t *time, rtc_format_t format)
Set specified time. More...
ald_status_t | ald_rtc_set_date (rtc_date_t *date, rtc_format_t format)
Set specified date. More...
void | ald_rtc_get_time (rtc_time_t *time, rtc_format_t format)
Get current time. More...
void | ald_rtc_get_date (rtc_date_t *date, rtc_format_t format)
Get current date. More...
int32_t | ald_rtc_get_date_time (rtc_date_t *date, rtc_time_t *time, rtc_format_t format)
Get time and date consistency. More...
void | ald_rtc_set_alarm (rtc_alarm_t *alarm, rtc_format_t format)
Set alarm. More...
void | ald_rtc_get_alarm (rtc_alarm_t *alarm, rtc_format_t format)
Get alarm parameters. More...
void | ald_rtc_set_time_stamp (rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style)
Set time stamp. More...
void | ald_rtc_cancel_time_stamp (void)
Cancel time stamp. More...
void | ald_rtc_get_time_stamp (rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format)
Get time stamp value. More...
void | ald_rtc_set_tamper (rtc_tamper_t *tamper)
Set tamper parameters. More...
void | ald_rtc_cancel_tamper (rtc_tamper_idx_t idx)
Cancel tamper. More...
void | ald_rtc_set_wakeup (rtc_wakeup_clock_t clock, uint16_t value)
Set wake-up parameters. More...
void | ald_rtc_cancel_wakeup (void)
Cancel wake-up. More...
uint16_t | ald_rtc_get_wakeup_timer_value (void)
Get wake-up re-load register value. More...
ald_status_t | ald_rtc_set_clock_output (rtc_clock_output_t clock)
Set clock output parameters. More...
void | ald_rtc_cancel_clock_output (void)
Cancel clock output. More...
void | ald_rtc_interrupt_config (rtc_it_t it, type_func_t state)
Enable/disable the specified RTC interrupts. More...
void | ald_rtc_alarm_cmd (rtc_alarm_idx_t idx, type_func_t state)
Enable/Disable alarm. More...
ald_status_t | ald_rtc_set_shift (type_func_t add_1s, uint16_t sub_ss)
Set shift parameters. More...
void | ald_rtc_set_cali (rtc_cali_t *config)
Set calibation. More...
void | ald_rtc_cancel_cali (void)
Cancel calibration. More...
ald_status_t | ald_rtc_get_cali_status (void)
Get calibration status. More...
void | ald_rtc_write_temp (uint16_t temp)
Write temperature value. More...
it_status_t | ald_rtc_get_it_status (rtc_it_t it)
Get the status of RTC interrupt source. More...
flag_status_t | ald_rtc_get_flag_status (rtc_flag_t flag)
Get the status of RTC interrupt flag. More...
void | ald_rtc_clear_flag_status (rtc_flag_t flag)
Clear the specified RTC pending flag. More...

Detailed Description

RTC module driver. This file provides firmware functions to manage the following functionalities of the RTC peripheral:

  • Initialization functions
  • Time and date functions
  • Alarm functions
  • Time stamp functions
  • Tamper functions
  • Wake-up functions
  • Clock output functions
  • Peripheral Control functions
    Version
    V1.0
    Date
    25 Apr 2019
    Author
    AE Team
    Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
==============================================================================
                      ##### How to use this driver #####
==============================================================================
  [..]
    (+) Enable the RTC controller interface clock.
    (+) Select the RTC source clock(default LOSC).
    (+) Configure the RTC asynchronous prescaler, synchronous prescaler and hour
        format using the ald_rtc_init() function.

   *** Time and date operation ***
   =================================
   [..]
     (+) To configure the time use the ald_rtc_set_time() function.
     (+) To configure the date use the ald_rtc_set_date() function.
     (+) To read the time use the ald_rtc_get_time() function.
     (+) To read the date use the ald_rtc_get_date() function.

   *** Alarm operation ***
   ===================================
   [..]
     (+) To configure the alarm use ald_rtc_set_alarm() function
     (+) To read the alarm use ald_rtc_get_alarm() function
     (+) To cancel the alarm use ald_rtc_alarm_cmd() function

   *** Time stamp operation ***
   ===================================
   [..]
     (+) To configure the time stamp use ald_rtc_set_time_stamp() function
     (+) To read the time stamp use ald_rtc_get_time_stamp() function
     (+) To cancel the time stamp use ald_rtc_cancel_time_stamp() function

   *** Tamper operation ***
   ===================================
   [..]
     (+) To configure the tamper use ald_rtc_set_tamper() function
     (+) To cancel the tamper use ald_rtc_alarm_cmd() function

   *** Wake-up operation ***
   ===================================
   [..]
     (+) To configure the wake-up parameters use ald_rtc_set_wakeup() function
     (+) To read the re-load register value use ald_rtc_get_wakeup_timer_value() function
     (+) To cancel the wake-up use ald_rtc_cancel_wakeup() function

   *** Output clock operation ***
   ===================================
   [..]
     (+) To configure the clock output type use ald_rtc_set_clock_output() function
     (+) To cancel the clock output use ald_rtc_cancel_clock_output() function

   *** Control functions ***
   ===================================
   [..]
     (+) Configure interrupt enable/disable.
     (+) Enable/disable alarm.
     (+) Configure rtc shift.
     (+) Calibrate time.
     (+) Get interrupt source status.
     (+) Get interrupt flag status.
     (+) Clear interrupt flag.

==================================================================
                ##### RTC and low power modes #####
==================================================================
[..] The MCU can be woken up from a low power mode by an RTC alternate function.
[..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B),
     RTC wake-up, RTC tamper event detection and RTC time stamp event detection.
     These RTC alternate functions can wake up the system from the Stop and
     Standby low power modes.
[..] The system can also wake up from low power modes without depending
     on an external interrupt (Auto-wake-up mode), by using the RTC alarm
     or the RTC wake-up events.
[..] The RTC provides a programmable time base for waking up from the Stop or
     Standby mode at regular intervals. Wake-up from STOP and STANDBY modes
     is possible only when the RTC clock source is LSE or LSI.

   *** RTC driver macros list ***
   =============================================
   [..]
     Below the list of most used macros in RTC driver.

    (+) RTC_UNLOCK() Disable the protect.
    (+) RTC_LOCK() Enable the protect.
    (+) RTC_BY_PASS_ENABLE() Enable the by-pass shadow register.
    (+) RTC_BY_PASS_DISABLE() Disable the by-pass shadow register.
    (+) RTC_SUMMER_TIME_ENABLE() Enable summer time.
    (+) RTC_SUMMER_TIME_DISABLE() Disable summer time.
    (+) RTC_WINTER_TIME_ENABLE() Enable winter time.
    (+) RTC_WINTER_TIME_DISABLE() Disable winter time.
   [..]
    (@) You can refer to the RTC driver header file for used the macros

Definition in file ald_rtc.c.


ALD User Manual: D:/svn/src/ald_rtc.h File Reference

  • D:
  • svn
  • src
Data Structures | Macros | Enumerations | Functions
ald_rtc.h File Reference

Header file of RTC Module driver. More...

#include "utils.h"
Include dependency graph for ald_rtc.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Data Structures

struct | rtc_init_t
Initialization structure. More...
struct | rtc_time_t
Time structure. More...
struct | rtc_date_t
Date structure. More...
struct | rtc_alarm_t
Alarm structure. More...
struct | rtc_tamper_t
Tamper structure. More...
struct | rtc_cali_t
Calibration structure. More...

Macros

#define | RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55U))
#define | RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0U))
#define | RTC_BY_PASS_ENABLE()
#define | RTC_BY_PASS_DISABLE()
#define | RTC_SUMMER_TIME_ENABLE()
#define | RTC_SUMMER_TIME_DISABLE()
#define | RTC_WINTER_TIME_ENABLE()
#define | RTC_WINTER_TIME_DISABLE()
#define | RTC_CALI_UNLOCK() (WRITE_REG(RTC->CALWPR, 0x699655AAU))
#define | RTC_CALI_LOCK() (WRITE_REG(RTC->CALWPR, 0x0U))
#define | ALARM_MASK_ALL 0x40808080
#define | RTC_TIMEOUT_VALUE 100
#define | IS_SHIFT_SUB_SS(x) ((x) < (1U << 15))
#define | IS_RTC_HOUR_FORMAT(x)
#define | IS_RTC_OUTPUT_SEL(x)
#define | IS_RTC_OUTPUT_POLARITY(x)
#define | IS_RTC_SOURCE_SEL(x)
#define | IS_RTC_ALARM(x)
#define | IS_RTC_ALARM_SEL(x)
#define | IS_RTC_ALARM_MASK(x)
#define | IS_RTC_ALARM_SS_MASK(x)
#define | IS_RTC_TS_SIGNAL(x)
#define | IS_RTC_TS_STYLE(x)
#define | IS_RTC_FORMAT(x)
#define | IS_RTC_TAMPER(x)
#define | IS_RTC_TAMPER_TRIGGER(x)
#define | IS_RTC_TAMPER_SAMPLING_FREQ(x)
#define | IS_RTC_TAMPER_DURATION(x)
#define | IS_RTC_WAKEUP_CLOCK(x)
#define | IS_RTC_CLOCK_OUTPUT(x)
#define | IS_RTC_CALI_FREQ(x)
#define | IS_RTC_CALI_TC(x)
#define | IS_RTC_CALC_FREQ(x)
#define | IS_RTC_CALI_CALC(x)
#define | IS_RTC_IT(x)
#define | IS_RTC_IF(x)
#define | IS_RTC_SECOND(x) ((x) < 60)
#define | IS_RTC_MINUTE(x) ((x) < 60)
#define | IS_RTC_HOUR(x) ((x) < 24)
#define | IS_RTC_DAY(x) (((x) > 0) && ((x) < 32))
#define | IS_RTC_MONTH(x) (((x) > 0) && ((x) < 13))
#define | IS_RTC_YEAR(x) ((x) < 100)

Enumerations

enum | rtc_hour_format_t { RTC_HOUR_FORMAT_24 = 0x0U, RTC_HOUR_FORMAT_12 = 0x1U }
Hours format. More...
enum | rtc_output_select_t { RTC_OUTPUT_DISABLE = 0x0U, RTC_OUTPUT_ALARM_A = 0x1U, RTC_OUTPUT_ALARM_B = 0x2U, RTC_OUTPUT_WAKEUP = 0x3U }
Output mode. More...
enum | rtc_output_polarity_t { RTC_OUTPUT_POLARITY_HIGH = 0x0U, RTC_OUTPUT_POLARITY_LOW = 0x1U }
Output polarity. More...
enum | rtc_source_sel_t { RTC_SOURCE_LOSC = 0x0U, RTC_SOURCE_LRC = 0x1U, RTC_SOURCE_HRC_DIV_1M = 0x2U, RTC_SOURCE_HOSC_DIV_1M = 0x3U }
Source select. More...
enum | rtc_format_t { RTC_FORMAT_DEC = 0U, RTC_FORMAT_BCD = 1U }
Data format. More...
enum | rtc_alarm_idx_t { RTC_ALARM_A = 0x0U, RTC_ALARM_B = 0x1U }
Index of alarm. More...
enum rtc_alarm_mask_t {
RTC_ALARM_MASK_NONE = 0x0U, RTC_ALARM_MASK_WEEK_DAY = (1U << 30), RTC_ALARM_MASK_HOUR = (1U << 23), RTC_ALARM_MASK_MINUTE = (1U << 15),
RTC_ALARM_MASK_SECOND = (1U << 7), RTC_ALARM_MASK_ALL = 0x40808080U
}
Alarm mask. More...
enum rtc_sub_second_mask_t {
RTC_ALARM_SS_MASK_NONE = 0xFU, RTC_ALARM_SS_MASK_14_1 = 0x1U, RTC_ALARM_SS_MASK_14_2 = 0x2U, RTC_ALARM_SS_MASK_14_3 = 0x3U,
RTC_ALARM_SS_MASK_14_4 = 0x4U, RTC_ALARM_SS_MASK_14_5 = 0x5U, RTC_ALARM_SS_MASK_14_6 = 0x6U, RTC_ALARM_SS_MASK_14_7 = 0x7U,
RTC_ALARM_SS_MASK_14_8 = 0x8U, RTC_ALARM_SS_MASK_14_9 = 0x9U, RTC_ALARM_SS_MASK_14_10 = 0xAU, RTC_ALARM_SS_MASK_14_11 = 0xBU,
RTC_ALARM_SS_MASK_14_12 = 0xCU, RTC_ALARM_SS_MASK_14_13 = 0xDU, RTC_ALARM_SS_MASK_14 = 0xEU, RTC_ALARM_SS_MASK_ALL = 0x0U
}
Alarm sub-second mask. More...
enum | rtc_week_day_sel_t { RTC_SELECT_DAY = 0x0U, RTC_SELECT_WEEK = 0x1U }
Alarm select week or day. More...
enum | rtc_ts_signal_sel_t { RTC_TS_SIGNAL_SEL_TAMPER0 = 0U, RTC_TS_SIGNAL_SEL_TAMPER1 = 1U }
Time stamp signel select. More...
enum | rtc_ts_trigger_style_t { RTC_TS_RISING_EDGE = 0U, RTC_TS_FALLING_EDGE = 1U }
Time stamp trigger style. More...
enum | rtc_tamper_idx_t { RTC_TAMPER_0 = 0U, RTC_TAMPER_1 = 1U }
Index of tamper. More...
enum | rtc_tamper_trigger_t { RTC_TAMPER_TRIGGER_LOW = 0U, RTC_TAMPER_TRIGGER_HIGH = 1U }
Tamper trigger type. More...
enum rtc_tamper_sampling_freq_t {
RTC_TAMPER_SAMPLING_FREQ_32768 = 0U, RTC_TAMPER_SAMPLING_FREQ_16384 = 1U, RTC_TAMPER_SAMPLING_FREQ_8192 = 2U, RTC_TAMPER_SAMPLING_FREQ_4096 = 3U,
RTC_TAMPER_SAMPLING_FREQ_2048 = 4U, RTC_TAMPER_SAMPLING_FREQ_1024 = 5U, RTC_TAMPER_SAMPLING_FREQ_512 = 6U, RTC_TAMPER_SAMPLING_FREQ_256 = 7U
}
Tamper sampling frequency. More...
enum | rtc_tamper_duration_t { RTC_TAMPER_DURATION_1 = 0U, RTC_TAMPER_DURATION_2 = 1U, RTC_TAMPER_DURATION_4 = 2U, RTC_TAMPER_DURATION_8 = 3U }
Tamper filter time. More...
enum rtc_wakeup_clock_t {
RTC_WAKEUP_CLOCK_DIV_16 = 0U, RTC_WAKEUP_CLOCK_DIV_8 = 1U, RTC_WAKEUP_CLOCK_DIV_4 = 2U, RTC_WAKEUP_CLOCK_DIV_2 = 3U,
RTC_WAKEUP_CLOCK_1HZ = 4U, RTC_WAKEUP_CLOCK_1HZ_PULS = 6U
}
Wake-up clock. More...
enum rtc_clock_output_t {
RTC_CLOCK_OUTPUT_32768 = 0U, RTC_CLOCK_OUTPUT_1024 = 1U, RTC_CLOCK_OUTPUT_32 = 2U, RTC_CLOCK_OUTPUT_1 = 3U,
RTC_CLOCK_OUTPUT_CAL_1 = 4U, RTC_CLOCK_OUTPUT_EXA_1 = 5U
}
RTC clock output type. More...
enum rtc_cali_freq_t {
RTC_CALI_FREQ_10_SEC = 0U, RTC_CALI_FREQ_20_SEC = 1U, RTC_CALI_FREQ_1_MIN = 2U, RTC_CALI_FREQ_2_MIN = 3U,
RTC_CALI_FREQ_5_MIN = 4U, RTC_CALI_FREQ_10_MIN = 5U, RTC_CALI_FREQ_20_MIN = 6U, RTC_CALI_FREQ_1_SEC = 7U
}
enum | rtc_cali_tc_t { RTC_CALI_TC_NONE = 0U, RTC_CALI_TC_AUTO_BY_HW = 1U, RTC_CALI_TC_AUTO_BY_SF = 2U, RTC_CALI_TC_AUTO_BY_HW_SF = 3U }
Temperature compensate type. More...
enum rtc_cali_calc_freq_t {
RTC_CALI_CALC_FREQ_10_SEC = 0U, RTC_CALI_CALC_FREQ_20_SEC = 1U, RTC_CALI_CALC_FREQ_1_MIN = 2U, RTC_CALI_CALC_FREQ_2_MIN = 3U,
RTC_CALI_CALC_FREQ_5_MIN = 4U, RTC_CALI_CALC_FREQ_10_MIN = 5U, RTC_CALI_CALC_FREQ_20_MIN = 6U, RTC_CALI_CALC_FREQ_1_HOUR = 7U
}
enum | rtc_cali_calc_t { RTC_CALI_CALC_4 = 0U, RTC_CALI_CALC_2 = 1U }
Calibration algorithm. More...
enum rtc_it_t {
RTC_IT_SEC = (1U << 0), RTC_IT_MIN = (1U << 1), RTC_IT_HR = (1U << 2), RTC_IT_DAY = (1U << 3),
RTC_IT_MON = (1U << 4), RTC_IT_YR = (1U << 5), RTC_IT_ALMA = (1U << 8), RTC_IT_ALMB = (1U << 9),
RTC_IT_TS = (1U << 10), RTC_IT_TSOV = (1U << 11), RTC_IT_TP0 = (1U << 12), RTC_IT_TP1 = (1U << 13),
RTC_IT_RSC = (1U << 16), RTC_IT_SFC = (1U << 17), RTC_IT_WU = (1U << 18), RTC_IT_TCC = (1U << 24),
RTC_IT_TCE = (1U << 25)
}
Interrupt type. More...
enum rtc_flag_t {
RTC_IF_SEC = (1U << 0), RTC_IF_MIN = (1U << 1), RTC_IF_HR = (1U << 2), RTC_IF_DAY = (1U << 3),
RTC_IF_MON = (1U << 4), RTC_IF_YR = (1U << 5), RTC_IF_ALMA = (1U << 8), RTC_IF_ALMB = (1U << 9),
RTC_IF_TS = (1U << 10), RTC_IF_TSOV = (1U << 11), RTC_IF_TP0 = (1U << 12), RTC_IF_TP1 = (1U << 13),
RTC_IF_RSC = (1U << 16), RTC_IF_SFC = (1U << 17), RTC_IF_WU = (1U << 18), RTC_IF_TCC = (1U << 24),
RTC_IF_TCE = (1U << 25)
}
Interrupt flag. More...

Functions

void | ald_rtc_reset (void)
Reset RTC register. More...
void | ald_rtc_init (rtc_init_t *init)
Initialize the RTC module. More...
void | ald_rtc_source_select (rtc_source_sel_t sel)
Configure the RTC source. More...
ald_status_t | ald_rtc_set_time (rtc_time_t *time, rtc_format_t format)
Set specified time. More...
ald_status_t | ald_rtc_set_date (rtc_date_t *date, rtc_format_t format)
Set specified date. More...
void | ald_rtc_get_time (rtc_time_t *time, rtc_format_t format)
Get current time. More...
void | ald_rtc_get_date (rtc_date_t *date, rtc_format_t format)
Get current date. More...
int32_t | ald_rtc_get_date_time (rtc_date_t *date, rtc_time_t *time, rtc_format_t format)
Get time and date consistency. More...
void | ald_rtc_set_alarm (rtc_alarm_t *alarm, rtc_format_t format)
Set alarm. More...
void | ald_rtc_get_alarm (rtc_alarm_t *alarm, rtc_format_t format)
Get alarm parameters. More...
void | ald_rtc_set_time_stamp (rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style)
Set time stamp. More...
void | ald_rtc_cancel_time_stamp (void)
Cancel time stamp. More...
void | ald_rtc_get_time_stamp (rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format)
Get time stamp value. More...
void | ald_rtc_set_tamper (rtc_tamper_t *tamper)
Set tamper parameters. More...
void | ald_rtc_cancel_tamper (rtc_tamper_idx_t idx)
Cancel tamper. More...
void | ald_rtc_set_wakeup (rtc_wakeup_clock_t clock, uint16_t value)
Set wake-up parameters. More...
void | ald_rtc_cancel_wakeup (void)
Cancel wake-up. More...
uint16_t | ald_rtc_get_wakeup_timer_value (void)
Get wake-up re-load register value. More...
ald_status_t | ald_rtc_set_clock_output (rtc_clock_output_t clock)
Set clock output parameters. More...
void | ald_rtc_cancel_clock_output (void)
Cancel clock output. More...
void | ald_rtc_interrupt_config (rtc_it_t it, type_func_t state)
Enable/disable the specified RTC interrupts. More...
void | ald_rtc_alarm_cmd (rtc_alarm_idx_t idx, type_func_t state)
Enable/Disable alarm. More...
ald_status_t | ald_rtc_set_shift (type_func_t add_1s, uint16_t sub_ss)
Set shift parameters. More...
void | ald_rtc_set_cali (rtc_cali_t *config)
Set calibation. More...
void | ald_rtc_cancel_cali (void)
Cancel calibration. More...
ald_status_t | ald_rtc_get_cali_status (void)
Get calibration status. More...
void | ald_rtc_write_temp (uint16_t temp)
Write temperature value. More...
it_status_t | ald_rtc_get_it_status (rtc_it_t it)
Get the status of RTC interrupt source. More...
flag_status_t | ald_rtc_get_flag_status (rtc_flag_t flag)
Get the status of RTC interrupt flag. More...
void | ald_rtc_clear_flag_status (rtc_flag_t flag)
Clear the specified RTC pending flag. More...

Detailed Description

Header file of RTC Module driver.

Version
V1.0
Date
16 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_rtc.h.


ALD User Manual: D:/svn/src/ald_rtchw.c File Reference

  • D:
  • svn
  • src
Functions
ald_rtchw.c File Reference

RTCHW module driver. This file provides firmware functions to manage the following functionalities of the RTC peripheral: More...

#include "ald_rtchw.h"
Include dependency graph for ald_rtchw.c:

Go to the source code of this file.

Functions

static void | delay_losc_clk (uint16_t u)
delay losc clock More...
static uint8_t | rtc_hw_auto_check (rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode)
Check parameter for calibation. More...
void | ald_rtc_hw_auto_cali (rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode)
Hardware automatic calibate. More...

Detailed Description

RTCHW module driver. This file provides firmware functions to manage the following functionalities of the RTC peripheral:

  • Calibration functions
    Version
    V1.0
    Date
    25 Apr 2019
    Author
    AE Team
    Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_rtchw.c.


ALD User Manual: D:/svn/src/ald_rtchw.h File Reference

  • D:
  • svn
  • src
Data Structures | Macros | Enumerations | Functions
ald_rtchw.h File Reference

Header file of RTCHW Module driver. More...

#include "utils.h"
#include "ald_rtc.h"
Include dependency graph for ald_rtchw.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Data Structures

struct | RTCINFO_TypeDef
the parameters table of rtc calibration More...
struct | rtc_hw_cali_offset_t
Hardware calibration structure. More...

Macros

#define | TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0U))
#define | TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669U))
#define | RTCINFO ((RTCINFO_TypeDef *)0x81000U)

Enumerations

enum rtc_hw_cali_mode_t { RTC_CALI_MODE_NORMAL = 0U, RTC_CALI_MODE_SLEEP = 1U }
Hardware calibration algorithm. More...

Functions

void ald_rtc_hw_auto_cali (rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode)
Hardware automatic calibate. More...

Detailed Description

Header file of RTCHW Module driver.

Version
V1.0
Date
16 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_rtchw.h.


ALD User Manual: D:/svn/src/ald_spi.c File Reference

  • D:
  • svn
  • src
Functions
ald_spi.c File Reference

SPI module driver. This file provides firmware functions to manage the following functionalities of SPI peripheral: More...

#include "ald_spi.h"
Include dependency graph for ald_spi.c:

Go to the source code of this file.

Functions

static void | __spi_send_by_it (spi_handle_t *hperh)
handle program when an tx empty interrupt flag arrived in non block mode More...
static void | __spi_recv_by_it (spi_handle_t *hperh)
handle program when an rx no empty interrupt flag arrived in non block mode More...
static void | __spi_send_recv_by_it (spi_handle_t *hperh, spi_sr_status_t status)
handle program when an rx no empty interrupt flag arrived in non block mode(2 lines) More...
static ald_status_t | spi_wait_flag_irq (spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout)
This function handles SPI communication timeout in interrupt function. More...
static void | spi_dma_send_cplt (void *arg)
DMA SPI transmit process complete callback. More...
static void | spi_dma_recv_cplt (void *arg)
DMA SPI receive process complete callback. More...
static void | spi_dma_send_recv_cplt (void *arg)
DMA SPI transmit and receive process complete callback. More...
void | ald_spi_reset (spi_handle_t *hperh)
Reset the SPI peripheral. More...
ald_status_t | ald_spi_init (spi_handle_t *hperh)
Initializes the SPI mode according to the specified parameters in the SPI_init_t and create the associated handle. More...
ald_status_t | spi_fifo_threshold_config (spi_handle_t *hperh, uint8_t threshold)
Config the fifo threshold. More...
int32_t | ald_spi_send_byte_fast (spi_handle_t *hperh, uint8_t data)
Transmit one byte fast in blocking mode. More...
int32_t | ald_spi_send_byte_fast_1line (spi_handle_t *hperh, uint8_t data)
Transmit one byte fast in blocking mode(1line). More...
uint8_t | ald_spi_recv_byte_fast (spi_handle_t *hperh, int *status)
Receive one byte fast in blocking mode. More...
ald_status_t | ald_spi_send_bytes_fast (spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Transmit some bytes fast in blocking mode. More...
ald_status_t | ald_spi_master_recv_bytes_fast (spi_handle_t *hperh, uint8_t *buf, uint32_t size)
Receive some bytes fast in blocking mode. More...
ald_status_t | ald_spi_slave_recv_bytes_fast (spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Receive some bytes fast in blocking mode. More...
ald_status_t | ald_spi_send_dbytes_fast (spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Transmit some double-bytes fast in blocking mode. More...
ald_status_t | ald_spi_master_recv_dbytes_fast (spi_handle_t *hperh, uint8_t *buf, uint32_t size)
Receive some double-bytes fast in blocking mode. More...
ald_status_t | ald_spi_slave_recv_dbytes_fast (spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Receive some double-bytes fast in blocking mode. More...
ald_status_t | ald_spi_send (spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Transmit an amount of data in blocking mode. More...
ald_status_t | ald_spi_recv (spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Receive an amount of data in blocking mode. More...
ald_status_t | ald_spi_send_recv (spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout)
Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode). More...
ald_status_t | ald_spi_send_by_it (spi_handle_t *hperh, uint8_t *buf, uint16_t size)
Wraps up transmission in non blocking mode. More...
ald_status_t | ald_spi_recv_by_it (spi_handle_t *hperh, uint8_t *buf, uint16_t size)
Receives an amount of data in non blocking mode. More...
ald_status_t | ald_spi_send_recv_by_it (spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size)
Transmit and Receives an amount of data in non blocking mode. More...
ald_status_t | ald_spi_send_by_dma (spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
Transmit an amount of data used dma channel. More...
ald_status_t | ald_spi_recv_by_dma (spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
Receive an amount of data used dma channel. More...
ald_status_t | ald_spi_send_recv_by_dma (spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel)
Transmit and Receive an amount of data used dma channel. More...
ald_status_t | ald_spi_dma_pause (spi_handle_t *hperh)
Pauses the DMA Transfer. More...
ald_status_t | ald_spi_dma_resume (spi_handle_t *hperh)
Resumes the DMA Transfer. More...
ald_status_t | ald_spi_dma_stop (spi_handle_t *hperh)
Stops the DMA Transfer. More...
void | ald_spi_irq_handler (spi_handle_t *hperh)
This function handles SPI interrupt request. More...
void | ald_spi_interrupt_config (spi_handle_t *hperh, spi_it_t it, type_func_t state)
Enables or disables the specified SPI interrupts. More...
void | ald_spi_speed_config (spi_handle_t *hperh, spi_baud_t speed)
Configure the specified SPI speed. More...
void | ald_spi_dma_req_config (spi_handle_t *hperh, spi_dma_req_t req, type_func_t state)
Enables or disables the dma request. More...
flag_status_t | spi_get_status (spi_handle_t *hperh, spi_status_t status)
Check whether the specified SPI state flag is set or not. More...
it_status_t | ald_spi_get_it_status (spi_handle_t *hperh, spi_it_t it)
Checks whether the specified SPI interrupt has occurred or not. More...
flag_status_t | ald_spi_get_flag_status (spi_handle_t *hperh, spi_flag_t flag)
Check whether the specified SPI flag is set or not. More...
void | ald_spi_clear_flag_status (spi_handle_t *hperh, spi_flag_t flag)
Clear the specified SPI pending flags. More...
static ald_status_t | spi_wait_bsy_flag (spi_handle_t *hperh, flag_status_t status, uint32_t timeout)
spi_state_t | ald_spi_get_state (spi_handle_t *hperh)
Returns the SPI state. More...
uint32_t | ald_spi_get_error (spi_handle_t *hperh)
Return the SPI error code. More...

Detailed Description

SPI module driver. This file provides firmware functions to manage the following functionalities of SPI peripheral:

Header file of SPI module driver.

  • Initialization functions
  • IO operation functions
  • Peripheral Control functions
  • Peripheral State functions
Version
V1.0
Date
13 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

==============================================================================
                      ##### How to use this driver #####
==============================================================================
  [..]
    The SPI driver can be used as follows:

    (#) Declare a spi_handle_t structure, for example:
        spi_handle_t hperh;

    (#) Initialize the SPI low level resources:
        (##) Enable the SPIx interface clock
        (##) SPI pins configuration
            (+++) Enable the clock for the SPI GPIOs
            (+++) Configure these SPI pins as push-pull
        (##) NVIC configuration if you need to use interrupt process
             by implementing the ald_mcu_irq_config() API.
             Invoked ald_spi_irq_handler() function in SPI-IRQ function
        (##) DMA Configuration if you need to use DMA process
            (+++) Define ALD_DMA in ald_conf.h
            (+++) Enable the DMAx clock

    (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
        management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.

    (#) Initialize the SPI module by invoking the ald_spi_init() API.

   [..]
     Circular mode restriction:
    (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
        (##) Master 2Lines RxOnly
        (##) Master 1Line Rx
    (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
        the ald_spi_dma_pause()/ ald_spi_dma_stop().

*
Version
V1.0
Date
13 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_spi.c.


ALD User Manual: D:/svn/src/ald_spi.h File Reference

  • D:
  • svn
  • src
Data Structures | Macros | Typedefs | Enumerations | Functions
ald_spi.h File Reference
#include "utils.h"
#include "ald_dma.h"
Include dependency graph for ald_spi.h:
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Data Structures

struct | spi_init_t
SPI init structure definition. More...
struct | spi_handle_s
SPI handle structure definition. More...

Macros

#define | SPI_RESET_HANDLE_STATE(x) ((x)->state = SPI_STATE_RESET)
#define | SPI_ENABLE(x) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS))
#define | SPI_DISABLE(x) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS))
#define | SPI_CRC_RESET(x)
#define | SPI_CRCNEXT_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
#define | SPI_CRCNEXT_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
#define | SPI_RXONLY_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))
#define | SPI_RXONLY_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))
#define | SPI_1LINE_TX(x) (SET_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK))
#define | SPI_1LINE_RX(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK))
#define | SPI_SSI_HIGH(x) (SET_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK))
#define | SPI_SSI_LOW(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK))
#define | SPI_SSOE_ENABLE(x) (SET_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK))
#define | SPI_SSOE_DISABLE(x) (CLEAR_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK))
#define | IS_SPI(x)
#define | IS_SPI_CPHA(x)
#define | IS_SPI_CPOL(x)
#define | IS_SPI_MODE(x)
#define | IS_SPI_FIRBIT(x)
#define | IS_SPI_BAUD(x)
#define | IS_SPI_DATASIZE(x)
#define | IS_SPI_BIDOE(x)
#define | IS_SPI_BIDMODE(x)
#define | IS_SPI_DIRECTION(x)
#define | IS_SPI_DMA_REQ(x)
#define | IS_SPI_STATUS(x)
#define | IS_SPI_IT(x)
#define | IS_SPI_IF(x)
#define | IS_SPI_FRAME(x)

Typedefs

typedef struct spi_handle_s spi_handle_t
SPI handle structure definition. More...

Enumerations

enum | spi_cpha_t { SPI_CPHA_FIRST = 0U, SPI_CPHA_SECOND = 1U }
clock phase More...
enum | spi_cpol_t { SPI_CPOL_LOW = 0U, SPI_CPOL_HIGH = 1U }
clock polarity More...
enum | spi_mode_t { SPI_MODE_SLAVER = 0U, SPI_MODE_MASTER = 1U }
master selection More...
enum spi_baud_t {
SPI_BAUD_2 = 0U, SPI_BAUD_4 = 1U, SPI_BAUD_8 = 2U, SPI_BAUD_16 = 3U,
SPI_BAUD_32 = 4U, SPI_BAUD_64 = 5U, SPI_BAUD_128 = 6U, SPI_BAUD_256 = 7U
}
baud rate control More...
enum | spi_firstbit_t { SPI_FIRSTBIT_MSB = 0U, SPI_FIRSTBIT_LSB = 1U }
frame format More...
enum | spi_datasize_t { SPI_DATA_SIZE_8 = 0U, SPI_DATA_SIZE_16 = 1U }
data frame format More...
enum spi_error_t {
SPI_ERROR_NONE = 0U, SPI_ERROR_MODF = 1U, SPI_ERROR_CRC = 2U, SPI_ERROR_FRE = 4U,
SPI_ERROR_RXOV = 8U, SPI_ERROR_TXOV = 0x10U, SPI_ERROR_FLAG = 0x20U
}
SPI error status. More...
enum spi_it_t {
SPI_IT_TXE = (1U << 0), SPI_IT_TXOV = (1U << 2), SPI_IT_TXUD = (1U << 3), SPI_IT_TXTH = (1U << 4),
SPI_IT_RXF = (1U << 9), SPI_IT_RXOV = (1U << 10), SPI_IT_RXUD = (1U << 11), SPI_IT_RXTH = (1U << 12),
SPI_IT_CRCERR = (1U << 16), SPI_IT_MODF = (1U << 17), SPI_IT_FRE = (1U << 18)
}
interrupt control More...
enum spi_flag_t {
SPI_IF_TXE = (1U << 0), SPI_IF_TXOV = (1U << 2), SPI_IF_TXUD = (1U << 3), SPI_IF_TXTH = (1U << 4),
SPI_IF_RXF = (1U << 9), SPI_IF_RXOV = (1U << 10), SPI_IF_RXUD = (1U << 11), SPI_IF_RXTH = (1U << 12),
SPI_IF_CRCERR = (1U << 16), SPI_IF_MODF = (1U << 17), SPI_IF_FRE = (1U << 18)
}
interrupt flag More...
enum spi_state_t {
SPI_STATE_RESET = 0x00U, SPI_STATE_READY = 0x01U, SPI_STATE_BUSY = 0x02U, SPI_STATE_BUSY_TX = 0x11U,
SPI_STATE_BUSY_RX = 0x21U, SPI_STATE_BUSY_TX_RX = 0x31U, SPI_STATE_TIMEOUT = 0x03U, SPI_STATE_ERROR = 0x04U
}
SPI state structures definition. More...
enum | spi_direction_t { SPI_DIRECTION_2LINES = 0U, SPI_DIRECTION_2LINES_RXONLY = 1U, SPI_DIRECTION_1LINE = 2U, SPI_DIRECTION_1LINE_RX = 3U }
SPI direction definition. More...
enum | spi_dma_req_t { SPI_DMA_REQ_TX = 0U, SPI_DMA_REQ_RX = 1U }
SPI dma request definition. More...
enum | spi_frame_t { SPI_FRAME_MOTOROLA = 0U, SPI_FRAME_TI = 1U }
SPI crc length definition. More...
enum spi_status_t {
SPI_STATUS_TXE = (1U << 0), SPI_STATUS_TXF = (1U << 1), SPI_STATUS_TXOV = (1U << 2), SPI_STATUS_TXUD = (1U << 3),
SPI_STATUS_TXTH = (1U << 4), SPI_STATUS_RXE = (1U << 8), SPI_STATUS_RXF = (1U << 9), SPI_STATUS_RXOV = (1U << 10),
SPI_STATUS_RXUD = (1U << 11), SPI_STATUS_RXTH = (1U << 12), SPI_STATUS_BUSY = (1U << 15)
}
SPI status definition. More...
enum | spi_sr_status_t { SPI_SR_TXE = 0U, SPI_SR_RXNE = 1U, SPI_SR_TXE_RXNE = 2U }
SPI TXE/RXNE status definition. More...

Functions

ald_status_t | ald_spi_init (spi_handle_t *hperh)
Initializes the SPI mode according to the specified parameters in the SPI_init_t and create the associated handle. More...
void | ald_spi_reset (spi_handle_t *hperh)
Reset the SPI peripheral. More...
int32_t | ald_spi_send_byte_fast (spi_handle_t *hperh, uint8_t data)
Transmit one byte fast in blocking mode. More...
int32_t | ald_spi_send_byte_fast_1line (spi_handle_t *hperh, uint8_t data)
Transmit one byte fast in blocking mode(1line). More...
uint8_t | ald_spi_recv_byte_fast (spi_handle_t *hperh, int *status)
Receive one byte fast in blocking mode. More...
ald_status_t | ald_spi_send_bytes_fast (spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Transmit some bytes fast in blocking mode. More...
ald_status_t | ald_spi_master_recv_bytes_fast (spi_handle_t *hperh, uint8_t *buf, uint32_t size)
Receive some bytes fast in blocking mode. More...
ald_status_t | ald_spi_slave_recv_bytes_fast (spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Receive some bytes fast in blocking mode. More...
ald_status_t | ald_spi_send_dbytes_fast (spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Transmit some double-bytes fast in blocking mode. More...
ald_status_t | ald_spi_master_recv_dbytes_fast (spi_handle_t *hperh, uint8_t *buf, uint32_t size)
Receive some double-bytes fast in blocking mode. More...
ald_status_t | ald_spi_slave_recv_dbytes_fast (spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Receive some double-bytes fast in blocking mode. More...
ald_status_t | ald_spi_send (spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Transmit an amount of data in blocking mode. More...
ald_status_t | ald_spi_recv (spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Receive an amount of data in blocking mode. More...
ald_status_t | ald_spi_send_recv (spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout)
Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode). More...
ald_status_t | ald_spi_send_by_it (spi_handle_t *hperh, uint8_t *buf, uint16_t size)
Wraps up transmission in non blocking mode. More...
ald_status_t | ald_spi_recv_by_it (spi_handle_t *hperh, uint8_t *buf, uint16_t size)
Receives an amount of data in non blocking mode. More...
ald_status_t | ald_spi_send_recv_by_it (spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size)
Transmit and Receives an amount of data in non blocking mode. More...
ald_status_t | ald_spi_send_by_dma (spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
Transmit an amount of data used dma channel. More...
ald_status_t | ald_spi_recv_by_dma (spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
Receive an amount of data used dma channel. More...
ald_status_t | ald_spi_send_recv_by_dma (spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel)
Transmit and Receive an amount of data used dma channel. More...
ald_status_t | ald_spi_dma_pause (spi_handle_t *hperh)
Pauses the DMA Transfer. More...
ald_status_t | ald_spi_dma_resume (spi_handle_t *hperh)
Resumes the DMA Transfer. More...
ald_status_t | ald_spi_dma_stop (spi_handle_t *hperh)
Stops the DMA Transfer. More...
void | ald_spi_irq_handler (spi_handle_t *hperh)
This function handles SPI interrupt request. More...
void | ald_spi_interrupt_config (spi_handle_t *hperh, spi_it_t it, type_func_t state)
Enables or disables the specified SPI interrupts. More...
void | ald_spi_speed_config (spi_handle_t *hperh, spi_baud_t speed)
Configure the specified SPI speed. More...
void | ald_spi_dma_req_config (spi_handle_t *hperh, spi_dma_req_t req, type_func_t state)
Enables or disables the dma request. More...
it_status_t | ald_spi_get_it_status (spi_handle_t *hperh, spi_it_t it)
Checks whether the specified SPI interrupt has occurred or not. More...
flag_status_t | spi_get_status (spi_handle_t *hperh, spi_status_t status)
Check whether the specified SPI state flag is set or not. More...
flag_status_t | ald_spi_get_flag_status (spi_handle_t *hperh, spi_flag_t flag)
Check whether the specified SPI flag is set or not. More...
void | ald_spi_clear_flag_status (spi_handle_t *hperh, spi_flag_t flag)
Clear the specified SPI pending flags. More...
spi_state_t | ald_spi_get_state (spi_handle_t *hperh)
Returns the SPI state. More...
uint32_t | ald_spi_get_error (spi_handle_t *hperh)
Return the SPI error code. More...


ALD User Manual: D:/svn/src/ald_sram.c File Reference

  • D:
  • svn
  • src
Functions
ald_sram.c File Reference

SRAM module driver. More...

#include "ald_sram.h"
Include dependency graph for ald_sram.c:

Go to the source code of this file.

Functions

ald_status_t | ald_sram_init (sram_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing)
Performs the SRAM device initialization sequence. More...
ald_status_t | ald_sram_deinit (sram_handle_t *hperh)
Performs the SRAM device De-initialization sequence. More...
ald_status_t | ald_sram_read_8b (sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size)
Reads 8-bit buffer from SRAM memory. More...
ald_status_t | ald_sram_write_8b (sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size)
Writes 8-bit buffer to SRAM memory. More...
ald_status_t | ald_sram_read_16b (sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size)
Reads 16-bit buffer from SRAM memory. More...
ald_status_t | ald_sram_write_16b (sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size)
Writes 16-bit buffer to SRAM memory. More...
ald_status_t | ald_sram_read_32b (sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size)
Reads 32-bit buffer from SRAM memory. More...
ald_status_t | ald_sram_write_32b (sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size)
Writes 32-bit buffer to SRAM memory. More...
ald_status_t | ald_sram_read_by_dma (sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch)
Reads a halfwords data from the SRAM memory using DMA transfer. More...
ald_status_t | ald_sram_write_by_dma (sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch)
Write a halfwords data to the SRAM memory using DMA transfer. More...
ald_status_t | ald_sram_write_enable (sram_handle_t *hperh)
Enables dynamically SRAM write operation. More...
ald_status_t | ald_sram_write_disable (sram_handle_t *hperh)
Disables dynamically SRAM write operation. More...
ald_sram_state_t | ald_sram_get_state (sram_handle_t *hperh)
Returns the SRAM controller state. More...

Detailed Description

SRAM module driver.

Version
V1.0
Date
25 Dec 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_sram.c.


ALD User Manual: D:/svn/src/ald_sram.h File Reference

  • D:
  • svn
  • src
Data Structures | Enumerations | Functions
ald_sram.h File Reference

Header file of EBI_SRAM driver. More...

#include "ald_ebi.h"
#include "ald_dma.h"
Include dependency graph for ald_sram.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Data Structures

struct sram_handle_t
SRAM handle Structure definition. More...

Enumerations

enum ald_sram_state_t {
ALD_SRAM_STATE_RESET = 0x00U, ALD_SRAM_STATE_READY = 0x01U, ALD_SRAM_STATE_BUSY = 0x02U, ALD_SRAM_STATE_ERROR = 0x03U,
ALD_SRAM_STATE_PROTECTED = 0x04U
}
ALD SRAM State structures definition. More...

Functions

ald_status_t | ald_sram_init (sram_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing)
Performs the SRAM device initialization sequence. More...
ald_status_t | ald_sram_deinit (sram_handle_t *hperh)
Performs the SRAM device De-initialization sequence. More...
ald_status_t | ald_sram_read_8b (sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size)
Reads 8-bit buffer from SRAM memory. More...
ald_status_t | ald_sram_write_8b (sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size)
Writes 8-bit buffer to SRAM memory. More...
ald_status_t | ald_sram_read_16b (sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size)
Reads 16-bit buffer from SRAM memory. More...
ald_status_t | ald_sram_write_16b (sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size)
Writes 16-bit buffer to SRAM memory. More...
ald_status_t | ald_sram_read_32b (sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size)
Reads 32-bit buffer from SRAM memory. More...
ald_status_t | ald_sram_write_32b (sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size)
Writes 32-bit buffer to SRAM memory. More...
ald_status_t | ald_sram_read_by_dma (sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch)
Reads a halfwords data from the SRAM memory using DMA transfer. More...
ald_status_t | ald_sram_write_by_dma (sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch)
Write a halfwords data to the SRAM memory using DMA transfer. More...
ald_status_t | ald_sram_write_enable (sram_handle_t *hperh)
Enables dynamically SRAM write operation. More...
ald_status_t | ald_sram_write_disable (sram_handle_t *hperh)
Disables dynamically SRAM write operation. More...
ald_sram_state_t | ald_sram_get_state (sram_handle_t *hperh)
Returns the SRAM controller state. More...

Detailed Description

Header file of EBI_SRAM driver.

Version
V1.0
Date
07 Dec 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_sram.h.


ALD User Manual: D:/svn/src/ald_syscfg.h File Reference

  • D:
  • svn
  • src
Macros | Functions
ald_syscfg.h File Reference

SYSCFG module driver. More...

#include "utils.h"
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Macros

#define | SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0U)
#define | SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996U)
#define | GET_SYSCFG_LOCK() READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK)
#define | SYSCFG_BOOTFLASH_MAPPING_ENABLE() SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK)
#define | SYSCFG_BOOTFLASH_MAPPING_DISABLE() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK)

Functions

__STATIC_INLINE__ void ald_vtor_config (uint32_t offset, type_func_t status)
Set the offset of the interrup vector map. More...

Detailed Description

SYSCFG module driver.

Version
V1.0
Date
04 Jun 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_syscfg.h.


ALD User Manual: D:/svn/src/ald_timer.c File Reference

  • D:
  • svn
  • src
Functions
ald_timer.c File Reference

TIMER module driver. This is the common part of the TIMER initialization. More...

#include <string.h>
#include "ald_timer.h"
#include "ald_cmu.h"
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Go to the source code of this file.

Functions

static void | timer_base_set_config (TIMER_TypeDef *TIMERx, timer_base_init_t *init)
Time Base configuration. More...
static void | timer_oc1_set_config (TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
Time Ouput Compare 1 configuration. More...
static void | timer_oc2_set_config (TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
Time Ouput Compare 2 configuration. More...
static void | timer_oc3_set_config (TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
Time Ouput Compare 3 configuration. More...
static void | timer_oc4_set_config (TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
Time Ouput Compare 4 configuration. More...
static void | timer_ccx_channel_cmd (TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x. More...
static void | timer_ccxn_channel_cmd (TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel xN. More...
static void | timer_ti1_set_config (TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, timer_ic_select_t sel, uint32_t filter)
Configure the TI1 as Input. More...
static void | timer_ti1_set_config_stage (TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter)
Configure the Polarity and Filter for TI1. More...
static void | timer_ti2_set_config (TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, timer_ic_select_t sel, uint32_t filter)
Configure the TI2 as Input. More...
static void | timer_ti2_set_config_stage (TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter)
Configure the Polarity and Filter for TI2. More...
static void | timer_ti3_set_config (TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, timer_ic_select_t sel, uint32_t filter)
Configure the TI3 as Input. More...
static void | timer_ti4_set_config (TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, timer_ic_select_t sel, uint32_t filter)
Configure the TI4 as Input. More...
static void | timer_etr_set_config (TIMER_TypeDef *TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter)
Configures the TIMERx External Trigger (ETR). More...
static void | timer_slave_set_config (timer_handle_t *hperh, timer_slave_config_t *config)
Time Slave configuration. More...
static void | timer_dma_oc_cplt (void *arg)
TIMER DMA out compare complete callback. More...
static void | timer_dma_capture_cplt (void *arg)
TIMER DMA Capture complete callback. More...
static void | timer_dma_period_elapse_cplt (void *arg)
TIMER DMA Period Elapse complete callback. More...
static void | timer_dma_error (void *arg)
TIMER DMA error callback. More...
static void | timer_dma_msel (TIMER_TypeDef *hperh, dma_config_t *config)
Timer DMA msel signal configuration. More...
ald_status_t | ald_timer_base_init (timer_handle_t *hperh)
Initializes the TIMER Time base Unit according to the specified parameters in the timer_handle_t and create the associated handle. More...
void | ald_timer_base_reset (timer_handle_t *hperh)
Reset the TIMER base peripheral. More...
void | ald_timer_base_start (timer_handle_t *hperh)
Starts the TIMER Base generation. More...
void | ald_timer_base_stop (timer_handle_t *hperh)
Stops the TIMER Base generation. More...
void | ald_timer_base_start_by_it (timer_handle_t *hperh)
Starts the TIMER Base generation in interrupt mode. More...
void | ald_timer_base_stop_by_it (timer_handle_t *hperh)
Stops the TIMER Base generation in interrupt mode. More...
ald_status_t | ald_timer_base_start_by_dma (timer_handle_t *hperh, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER Base generation in DMA mode. More...
void | ald_timer_base_stop_by_dma (timer_handle_t *hperh)
Stops the TIMER Base generation in DMA mode. More...
ald_status_t | ald_timer_oc_init (timer_handle_t *hperh)
Initializes the TIMER Output Compare according to the specified parameters in the timer_handle_t and create the associated handle. More...
void | ald_timer_oc_start (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Output Compare signal generation. More...
void | ald_timer_oc_stop (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Output Compare signal generation. More...
void | ald_timer_oc_start_by_it (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Output Compare signal generation in interrupt mode. More...
void | ald_timer_oc_stop_by_it (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Output Compare signal generation in interrupt mode. More...
ald_status_t | ald_timer_oc_start_by_dma (timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER Output Compare signal generation in DMA mode. More...
void | ald_timer_oc_stop_by_dma (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Output Compare signal generation in DMA mode. More...
ald_status_t | ald_timer_pwm_init (timer_handle_t *hperh)
Initializes the TIMER PWM Time Base according to the specified parameters in the timer_handle_t and create the associated handle. More...
void | ald_timer_pwm_start (timer_handle_t *hperh, timer_channel_t ch)
Starts the PWM signal generation. More...
void | ald_timer_pwm_stop (timer_handle_t *hperh, timer_channel_t ch)
Stops the PWM signal generation. More...
void | ald_timer_pwm_start_by_it (timer_handle_t *hperh, timer_channel_t ch)
Starts the PWM signal generation in interrupt mode. More...
void | ald_timer_pwm_stop_by_it (timer_handle_t *hperh, timer_channel_t ch)
Stops the PWM signal generation in interrupt mode. More...
ald_status_t | ald_timer_pwm_start_by_dma (timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER PWM signal generation in DMA mode. More...
void | ald_timer_pwm_stop_by_dma (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER PWM signal generation in DMA mode. More...
void | ald_timer_pwm_set_freq (timer_handle_t *hperh, uint16_t freq)
Set the PWM freq. More...
void | ald_timer_pwm_set_duty (timer_handle_t *hperh, timer_channel_t ch, uint16_t duty)
Set the PWM duty. More...
void | ald_timer_pwm_set_input (timer_handle_t *hperh, timer_channel_t ch)
Set capture the PWM. More...
ald_status_t | ald_timer_ic_init (timer_handle_t *hperh)
Initializes the TIMER Input Capture Time base according to the specified parameters in the timer_handle_t and create the associated handle. More...
void | ald_timer_ic_start (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Input Capture measurement. More...
void | ald_timer_ic_stop (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Input Capture measurement. More...
void | ald_timer_ic_start_by_it (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Input Capture measurement in interrupt mode. More...
void | ald_timer_ic_stop_by_it (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Input Capture measurement in interrupt mode. More...
ald_status_t | ald_timer_ic_start_by_dma (timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER Input Capture measurement in DMA mode. More...
void | ald_timer_ic_stop_by_dma (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Input Capture measurement in DMA mode. More...
ald_status_t | ald_timer_one_pulse_init (timer_handle_t *hperh, timer_op_mode_t mode)
Initializes the TIMER One Pulse Time Base according to the specified parameters in the timer_handle_t and create the associated handle. More...
void | ald_timer_one_pulse_start (timer_handle_t *hperh, timer_op_output_channel_t ch)
Starts the TIMER One Pulse signal generation. More...
void | ald_timer_one_pulse_stop (timer_handle_t *hperh, timer_op_output_channel_t ch)
Stops the TIMER One Pulse signal generation. More...
void | ald_timer_one_pulse_start_by_it (timer_handle_t *hperh, timer_op_output_channel_t ch)
Starts the TIMER One Pulse signal generation in interrupt mode. More...
void | ald_timer_one_pulse_stop_by_it (timer_handle_t *hperh, timer_op_output_channel_t ch)
Stops the TIMER One Pulse signal generation in interrupt mode. More...
ald_status_t | ald_timer_encoder_init (timer_handle_t *hperh, timer_encoder_init_t *config)
Initializes the TIMER Encoder Interface and create the associated handle. More...
void | ald_timer_encoder_start (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Encoder Interface. More...
void | ald_timer_encoder_stop (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Encoder Interface. More...
void | ald_timer_encoder_start_by_it (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Encoder Interface in interrupt mode. More...
void | ald_timer_encoder_stop_by_it (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Encoder Interface in interrupt mode. More...
ald_status_t | ald_timer_encoder_start_by_dma (timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf1, uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2)
Starts the TIMER Encoder Interface in DMA mode. More...
void | ald_timer_encoder_stop_by_dma (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Encoder Interface in DMA mode. More...
ald_status_t | ald_timer_hall_sensor_init (timer_handle_t *hperh, timer_hall_sensor_init_t *config)
Initializes the TIMER Encoder Interface and create the associated handle. More...
void | ald_timer_hall_sensor_start (timer_handle_t *hperh)
Starts the TIMER hall sensor interface. More...
void | ald_timer_hall_sensor_stop (timer_handle_t *hperh)
Stops the TIMER hall sensor interface. More...
void | ald_timer_hall_sensor_start_by_it (timer_handle_t *hperh)
Starts the TIMER hall sensor interface in interrupt mode. More...
void | ald_timer_hall_sensor_stop_by_it (timer_handle_t *hperh)
Stops the TIMER hall sensor interface in interrupt mode. More...
ald_status_t | ald_timer_hall_sensor_start_by_dma (timer_handle_t *hperh, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER hall sensor interface in DMA mode. More...
void | ald_timer_hall_sensor_stop_by_dma (timer_handle_t *hperh)
Stops the TIMER hall sensor interface in DMA mode. More...
void | ald_timer_ocn_start (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER output compare signal generation on the complementary output. More...
void | ald_timer_ocn_stop (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER output compare signal generation on the complementary output. More...
void | ald_timer_ocn_start_by_it (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER output compare signal generation on the complementary output. in interrupt mode. More...
void | ald_timer_ocn_stop_by_it (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER output compare signal generation on the complementary output. in interrupt mode. More...
ald_status_t | ald_timer_ocn_start_by_dma (timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER output compare signal generation on the complementary output. in DMA mode. More...
void | ald_timer_ocn_stop_by_dma (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER output compare signal generation on the complementary output. in DMA mode. More...
void | ald_timer_pwmn_start (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER PWM signal generation on the complementary output. More...
void | ald_timer_pwmn_stop (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER PWM signal generation on the complementary output. More...
void | ald_timer_pwmn_start_by_it (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER PWM signal generation on the complementary output. in interrupt mode. More...
void | ald_timer_pwmn_stop_by_it (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER PWM signal generation on the complementary output. in interrupt mode. More...
ald_status_t | ald_timer_pwmn_start_by_dma (timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER PWM signal generation on the complementary output. in DMA mode. More...
void | ald_timer_pwmn_stop_by_dma (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER PWM signal generation on the complementary output. in DMA mode. More...
void | ald_timer_one_pulse_n_start (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER one pulse signal generation on the complementary output. More...
void | ald_timer_one_pulse_n_stop (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER one pulse signal generation on the complementary output. More...
void | ald_timer_one_pulse_n_start_by_it (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER one pulse signal generation on the complementary output. in interrupt mode. More...
void | ald_timer_one_pulse_n_stop_by_it (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER one pulse signal generation on the complementary output. in interrupt mode. More...
ald_status_t | ald_timer_oc_config_channel (timer_handle_t *hperh, timer_oc_init_t *config, timer_channel_t ch)
Initializes the TIMER Output Compare Channels according to the specified parameters in the timer_oc_init_t. More...
ald_status_t | ald_timer_ic_config_channel (timer_handle_t *hperh, timer_ic_init_t *config, timer_channel_t ch)
Initializes the TIMER Input Capture Channels according to the specified parameters in the timer_ic_init_t. More...
ald_status_t | ald_timer_one_pulse_config_channel (timer_handle_t *hperh, timer_one_pulse_init_t *config, timer_channel_t ch_out, timer_channel_t ch_in)
Initializes the TIMER One Pulse Channels according to the specified parameters in the timer_one_pulse_init_t. More...
ald_status_t | ald_timer_config_oc_ref_clear (timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch)
Configures the OCRef clear feature. More...
ald_status_t | ald_timer_config_clock_source (timer_handle_t *hperh, timer_clock_config_t *config)
Configures the clock source to be used. More...
ald_status_t | ald_timer_config_ti1_input (timer_handle_t *hperh, uint32_t ti1_select)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input. More...
ald_status_t | ald_timer_slave_config_sync (timer_handle_t *hperh, timer_slave_config_t *config)
Configures the TIMER in Slave mode. More...
ald_status_t | ald_timer_slave_config_sync_by_it (timer_handle_t *hperh, timer_slave_config_t *config)
Configures the TIMER in Slave mode in interrupt mode. More...
ald_status_t | ald_timer_generate_event (timer_handle_t *hperh, timer_event_source_t event)
Generate a software event. More...
uint32_t | ald_timer_read_capture_value (timer_handle_t *hperh, timer_channel_t ch)
Read the captured value from Capture Compare unit. More...
void | ald_timer_set_output_mode (timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch)
Sets TIMER output mode. More...
void | ald_timer_com_change_config (timer_handle_t *hperh, timer_com_channel_config_t *config)
Configure the channel in commutation event. More...
void | ald_timer_com_event_config (timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi)
Configure the TIMER commutation event sequence. More...
void | ald_timer_com_event_config_it (timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi)
Configure the TIMER commutation event sequence with interrupt. More...
void | ald_timer_break_dead_time_config (timer_handle_t *hperh, timer_break_dead_time_t *config)
Configure the break, dead timere, lock level state. More...
void | ald_timer_master_sync_config (timer_handle_t *hperh, timer_master_config_t *config)
Configure the master mode. More...
void | ald_timer_irq_handler (timer_handle_t *hperh)
This function handles TIMER interrupts requests. More...
void | ald_timer_dma_req_config (timer_handle_t *hperh, timer_dma_req_t req, type_func_t state)
Configure DMA request source. More...
void | ald_timer_interrupt_config (timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts. More...
it_status_t | ald_timer_get_it_status (timer_handle_t *hperh, timer_it_t it)
Get the status of TIMER interrupt source. More...
flag_status_t | ald_timer_get_flag_status (timer_handle_t *hperh, timer_flag_t flag)
Get the status of TIMER interrupt flag. More...
void | ald_timer_clear_flag_status (timer_handle_t *hperh, timer_flag_t flag)
Clear the TIMER interrupt flag. More...
timer_state_t | ald_timer_get_state (timer_handle_t *hperh)
Return the TIMER Base state. More...

Detailed Description

TIMER module driver. This is the common part of the TIMER initialization.

Version
V1.0
Date
06 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_timer.c.


ALD User Manual: D:/svn/src/ald_timer.h File Reference

  • D:
  • svn
  • src
Data Structures | Macros | Typedefs | Enumerations | Functions
ald_timer.h File Reference

TIMER module driver. This is the common part of the TIMER initialization. More...

#include "utils.h"
#include "ald_dma.h"
Include dependency graph for ald_timer.h:
This graph shows which files directly or indirectly include this file:

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Data Structures

struct | timer_base_init_t
TIMER time base configuration structure definition. More...
struct | timer_oc_init_t
TIMER output compare configuration structure definition. More...
struct | timer_handle_s
TIMER time base handle structure definition. More...
struct | timer_encoder_init_t
TIMER encoder configuration structure definition. More...
struct | timer_ic_init_t
TIMER input capture configuration structure definition. More...
struct | timer_one_pulse_init_t
TIMER one pulse mode configuration structure definition. More...
struct | timer_clear_input_config_t
TIMER clear input configuration handle structure definition. More...
struct | timer_clock_config_t
TIMER clock config structure definition. More...
struct | timer_slave_config_t
TIMER slave configuration structure definition. More...
struct | timer_hall_sensor_init_t
TIMER hall sensor configuretion structure definition. More...
struct | timer_break_dead_time_t
TIMER break and dead time configuretion structure definition. More...
struct | timer_channel_config_t
TIMER commutation event channel configuretion structure definition. More...
struct | timer_com_channel_config_t
TIMER commutation event configuretion structure definition. More...
struct | timer_master_config_t
TIMER master configuretion structure definition. More...

Macros

#define | CCER_CCxE_MASK ((1U << 0) | (1U << 4) | (1U << 8) | (1U << 12))
#define | CCER_CCxNE_MASK ((1U << 2) | (1U << 6) | (1U << 10))
#define | TIMER_RESET_HANDLE_STATE(hperh) ((hperh)->state = TIMER_STATE_RESET)
Reset TIMER handle state. More...
#define | TIMER_ENABLE(hperh) (SET_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK))
Enable the TIMER peripheral. More...
#define | TIMER_MOE_ENABLE(hperh) (SET_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK))
Enable the TIMER main output. More...
#define | TIMER_DISABLE(hperh)
Disable the TIMER peripheral. More...
#define | TIMER_MOE_DISABLE(hperh)
Disable the TIMER main output. More...
#define | TIMER_SET_AUTORELOAD(handle, AUTORELOAD)
Sets the TIMER autoreload register value on runtime without calling another time any Init function. More...
#define | TIMER_GET_AUTORELOAD(handle) ((handle)->perh->AR)
Gets the TIMER autoreload register value on runtime. More...
#define | TIMER_GET_CNT(handle) ((handle)->perh->COUNT)
Gets the TIMER count register value on runtime. More...
#define | TIMER_GET_DIR(handle) (READ_BITS((handle)->perh->CON1, TIMER_CON1_DIRSEL_MSK, TIMER_CON1_DIRSEL_POS))
Gets the TIMER count direction value on runtime. More...
#define | TIMER_CCx_DMA_REQ_CCx(handle) (CLEAR_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK))
CCx DMA request sent when CCx event occurs. More...
#define | TIMER_CCx_DMA_REQ_UPDATE(handle) (SET_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK))
CCx DMA request sent when update event occurs. More...
#define | TIMER_CCx_ENABLE(handle, ch)
Enable channel. More...
#define | TIMER_CCx_DISABLE(handle, ch)
Disable channel. More...
#define | TIMER_CCxN_ENABLE(handle, ch) ((handle)->perh->CCEP |= (1 << (((ch) << 2) + 2)))
Enable complementary channel. More...
#define | TIMER_CCxN_DISABLE(handle, ch) ((handle)->perh->CCEP &= ~(1 << (((ch) << 2) + 2)))
Disable complementary channel. More...
#define | IS_TIMER_COUNTER_MODE(x)
#define | IS_TIMER_CLOCK_DIVISION(x)
#define | IS_TIMER_PWM_MODE(x)
#define | IS_TIMER_OC_MODE(x)
#define | IS_TIMER_OC_POLARITY(x)
#define | IS_TIMER_OCN_POLARITY(x)
#define | IS_TIMER_OCIDLE_STATE(x)
#define | IS_TIMER_OCNIDLE_STATE(x)
#define | IS_TIMER_CHANNELS(x)
#define | IS_TIMER_OP_MODE(x)
#define | IS_TIMER_OP_OUTPUT_CH(x)
#define | IS_TIMER_ENCODER_MODE(x)
#define | IS_TIMER_IC_POLARITY(x)
#define | IS_TIMER_IC_SELECT(x)
#define | IS_TIMER_IC_PSC(x)
#define | IS_TIMER_IC_FILTER(x) ((x) <= 0xF)
#define | IS_TIMER_DEAD_TIMERE(x) ((x) <= 0xFF)
#define | IS_TIMER_CLEAR_INPUT_SOURCE(x)
#define | IS_TIMER_CLEAR_INPUT_POLARITY(x)
#define | IS_TIMER_ETR_PSC(x)
#define | IS_TIMER_CHNREF_CLEAR(X)
#define | IS_TIMER_CLOCK_SOURCE(x)
#define | IS_TIMER_CLOCK_POLARITY(x)
#define | IS_TIMER_SLAVE_MODE(x)
#define | IS_TIMER_EVENT_SOURCE(x)
#define | IS_TIMER_TS(x)
#define | IS_TIMER_CLOCK_LEVEL(x)
#define | IS_TIMER_BREAK_POLARITY(x)
#define | IS_TIMER_MASTER_MODE_SEL(x)
#define | IS_TIMER_IT(x)
#define | IS_TIMER_DMA_REQ(x)
#define | IS_TIMER_FLAG(x)

Typedefs

typedef struct timer_handle_s timer_handle_t
TIMER time base handle structure definition. More...

Enumerations

enum timer_cnt_mode_t {
TIMER_CNT_MODE_UP = 0U, TIMER_CNT_MODE_DOWN = 1U, TIMER_CNT_MODE_CENTER1 = 2U, TIMER_CNT_MODE_CENTER2 = 3U,
TIMER_CNT_MODE_CENTER3 = 4U
}
TIMER counter mode. More...
enum | timer_clock_division_t { TIMER_CLOCK_DIV1 = 0U, TIMER_CLOCK_DIV2 = 1U, TIMER_CLOCK_DIV4 = 2U }
TIMER clock division. More...
enum timer_oc_mode_t {
TIMER_OC_MODE_TIMERING = 0U, TIMER_OC_MODE_ACTIVE = 1U, TIMER_OC_MODE_INACTIVE = 2U, TIMER_OC_MODE_TOGGLE = 3U,
TIMER_OC_MODE_FORCE_INACTIVE = 4U, TIMER_OC_MODE_FORCE_ACTIVE = 5U, TIMER_OC_MODE_PWM1 = 6U, TIMER_OC_MODE_PWM2 = 7U
}
TIMER output compare and PWM modes. More...
enum | timer_oc_polarity_t { TIMER_OC_POLARITY_HIGH = 0U, TIMER_OC_POLARITY_LOW = 1U }
TIMER output compare polarity. More...
enum | timer_ocn_polarity_t { TIMER_OCN_POLARITY_HIGH = 0U, TIMER_OCN_POLARITY_LOW = 1U }
TIMER complementary output compare polarity. More...
enum | timer_oc_idle_t { TIMER_OC_IDLE_RESET = 0U, TIMER_OC_IDLE_SET = 1U }
TIMER output compare idle state. More...
enum | timer_ocn_idle_t { TIMER_OCN_IDLE_RESET = 0U, TIMER_OCN_IDLE_SET = 1U }
TIMER complementary output compare idle state. More...
enum timer_channel_t {
TIMER_CHANNEL_1 = 0U, TIMER_CHANNEL_2 = 1U, TIMER_CHANNEL_3 = 2U, TIMER_CHANNEL_4 = 3U,
TIMER_CHANNEL_ALL = 0xFU
}
TIMER channel. More...
enum | timer_op_mode_t { TIMER_OP_MODE_REPEAT = 0U, TIMER_OP_MODE_SINGLE = 1U }
TIMER one pulse mode. More...
enum | timer_op_output_channel_t { TIMER_OP_OUTPUT_CHANNEL_1 = 0U, TIMER_OP_OUTPUT_CHANNEL_2 = 1U }
TIMER one pulse output channel. More...
enum timer_state_t {
TIMER_STATE_RESET = 0x00U, TIMER_STATE_READY = 0x01U, TIMER_STATE_BUSY = 0x02U, TIMER_STATE_TIMEREOUT = 0x03U,
TIMER_STATE_ERROR = 0x04U
}
State structures definition. More...
enum timer_active_channel_t {
TIMER_ACTIVE_CHANNEL_1 = 0x01U, TIMER_ACTIVE_CHANNEL_2 = 0x02U, TIMER_ACTIVE_CHANNEL_3 = 0x04U, TIMER_ACTIVE_CHANNEL_4 = 0x08U,
TIMER_ACTIVE_CHANNEL_CLEARED = 0x00U
}
Active channel structures definition. More...
enum | timer_encoder_mode_t { TIMER_ENC_MODE_TI1 = 1U, TIMER_ENC_MODE_TI2 = 2U, TIMER_ENC_MODE_TI12 = 3U }
TIMER encoder mode. More...
enum | timer_ic_polarity_t { TIMER_IC_POLARITY_RISE = 0U, TIMER_IC_POLARITY_FALL = 1U }
TIMER input capture polarity. More...
enum | timer_ic_select_t { TIMER_IC_SEL_DIRECT = 1U, TIMER_IC_SEL_INDIRECT = 2U, TIMER_IC_SEL_TRC = 3U }
TIMER input capture selection. More...
enum | timer_ic_prescaler_t { TIMER_IC_PSC_DIV1 = 0U, TIMER_IC_PSC_DIV2 = 1U, TIMER_IC_PSC_DIV4 = 2U, TIMER_IC_PSC_DIV8 = 3U }
TIMER input capture prescaler. More...
enum | timer_clear_input_source_t { TIMER_INPUT_NONE = 0U, TIMER_INPUT_ETR = 1U }
TIMER clear input source. More...
enum | timer_clear_input_polarity_t { TIMER_POLARITY_NO_INV = 0U, TIMER_POLARITY_INV = 1U }
TIMER clear input polarity. More...
enum | timer_etr_psc_t { TIMER_ETR_PSC_DIV1 = 0U, TIMER_ETR_PSC_DIV2 = 1U, TIMER_ETR_PSC_DIV4 = 2U, TIMER_ETR_PSC_DIV8 = 3U }
TIMER clear input polarity. More...
enum | timer_chnref_clr_sel_t { TIMER_CHNREF_CLR_CMP_IN = 0U, TIMER_CHNREF_CLR_ETF = 1U }
TIMER CHnREF Clear Select. More...
enum timer_clock_source_t {
TIMER_SRC_ETRMODE2 = 0U, TIMER_SRC_INTER = 1U, TIMER_SRC_ITR0 = 2U, TIMER_SRC_ITR1 = 3U,
TIMER_SRC_ITR2 = 4U, TIMER_SRC_ITR3 = 5U, TIMER_SRC_TI1ED = 6U, TIMER_SRC_TI1 = 7U,
TIMER_SRC_TI2 = 8U, TIMER_SRC_ETRMODE1 = 9U
}
TIMER clock source. More...
enum timer_clock_polarity_t {
TIMER_CLK_POLARITY_INV = 1U, TIMER_CLK_POLARITY_NO_INV = 0U, TIMER_CLK_POLARITY_RISE = 0U, TIMER_CLK_POLARITY_FALL = 1U,
TIMER_CLK_POLARITY_BOTH = 3U
}
TIMER clock polarity. More...
enum timer_slave_mode_t {
TIMER_MODE_DISABLE = 0U, TIMER_MODE_ENC1 = 1U, TIMER_MODE_ENC2 = 2U, TIMER_MODE_ENC3 = 3U,
TIMER_MODE_RESET = 4U, TIMER_MODE_GATED = 5U, TIMER_MODE_TRIG = 6U, TIMER_MODE_EXTERNAL1 = 7U
}
TIMER slave mode. More...
enum timer_ts_t {
TIMER_TS_ITR0 = 0U, TIMER_TS_ITR1 = 1U, TIMER_TS_ITR2 = 2U, TIMER_TS_ITR3 = 3U,
TIMER_TS_TI1F_ED = 4U, TIMER_TS_TI1FP1 = 5U, TIMER_TS_TI2FP2 = 6U, TIMER_TS_ETRF = 7U
}
TIMER ts definition. More...
enum | timer_lock_level_t { TIMER_LOCK_LEVEL_OFF = 0U, TIMER_LOCK_LEVEL_1 = 1U, TIMER_LOCK_LEVEL_2 = 2U, TIMER_LOCK_LEVEL_3 = 3U }
TIMER lock level. More...
enum | timer_break_polarity_t { TIMER_BREAK_POLARITY_LOW = 0U, TIMER_BREAK_POLARITY_HIGH = 1U }
TIMER break polarity. More...
enum timer_master_mode_sel_t {
TIMER_TRGO_RESET = 0U, TIMER_TRGO_ENABLE = 1U, TIMER_TRGO_UPDATE = 2U, TIMER_TRGO_OC1 = 3U,
TIMER_TRGO_OC1REF = 4U, TIMER_TRGO_OC2REF = 5U, TIMER_TRGO_OC3REF = 6U, TIMER_TRGO_OC4REF = 7U
}
TIMER master mode selection. More...
enum timer_event_source_t {
TIMER_SRC_UPDATE = (1U << 0), TIMER_SRC_CC1 = (1U << 1), TIMER_SRC_CC2 = (1U << 2), TIMER_SRC_CC3 = (1U << 3),
TIMER_SRC_CC4 = (1U << 4), TIMER_SRC_COM = (1U << 5), TIMER_SRC_TRIG = (1U << 6), TIMER_SRC_BREAK = (1U << 7)
}
Specifies the event source. More...
enum timer_it_t {
TIMER_IT_UPDATE = (1U << 0), TIMER_IT_CC1 = (1U << 1), TIMER_IT_CC2 = (1U << 2), TIMER_IT_CC3 = (1U << 3),
TIMER_IT_CC4 = (1U << 4), TIMER_IT_COM = (1U << 5), TIMER_IT_TRIGGER = (1U << 6), TIMER_IT_BREAK = (1U << 7)
}
TIMER interrupt definition. More...
enum timer_dma_req_t {
TIMER_DMA_UPDATE = (1U << 0), TIMER_DMA_CC1 = (1U << 1), TIMER_DMA_CC2 = (1U << 2), TIMER_DMA_CC3 = (1U << 3),
TIMER_DMA_CC4 = (1U << 4), TIMER_DMA_COM = (1U << 5), TIMER_DMA_TRIGGER = (1U << 6)
}
TIMER DMA request. More...
enum timer_flag_t {
TIMER_FLAG_UPDATE = (1U << 0), TIMER_FLAG_CC1 = (1U << 1), TIMER_FLAG_CC2 = (1U << 2), TIMER_FLAG_CC3 = (1U << 3),
TIMER_FLAG_CC4 = (1U << 4), TIMER_FLAG_COM = (1U << 5), TIMER_FLAG_TRIGGER = (1U << 6), TIMER_FLAG_BREAK = (1U << 7),
TIMER_FLAG_CC1OF = (1U << 9), TIMER_FLAG_CC2OF = (1U << 10), TIMER_FLAG_CC3OF = (1U << 11), TIMER_FLAG_CC4OF = (1U << 12)
}
TIMER flag definition. More...

Functions

ald_status_t | ald_timer_base_init (timer_handle_t *hperh)
Initializes the TIMER Time base Unit according to the specified parameters in the timer_handle_t and create the associated handle. More...
void | ald_timer_base_reset (timer_handle_t *hperh)
Reset the TIMER base peripheral. More...
void | ald_timer_base_start (timer_handle_t *hperh)
Starts the TIMER Base generation. More...
void | ald_timer_base_stop (timer_handle_t *hperh)
Stops the TIMER Base generation. More...
void | ald_timer_base_start_by_it (timer_handle_t *hperh)
Starts the TIMER Base generation in interrupt mode. More...
void | ald_timer_base_stop_by_it (timer_handle_t *hperh)
Stops the TIMER Base generation in interrupt mode. More...
ald_status_t | ald_timer_base_start_by_dma (timer_handle_t *hperh, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER Base generation in DMA mode. More...
void | ald_timer_base_stop_by_dma (timer_handle_t *hperh)
Stops the TIMER Base generation in DMA mode. More...
ald_status_t | ald_timer_oc_init (timer_handle_t *hperh)
Initializes the TIMER Output Compare according to the specified parameters in the timer_handle_t and create the associated handle. More...
void | ald_timer_oc_start (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Output Compare signal generation. More...
void | ald_timer_oc_stop (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Output Compare signal generation. More...
void | ald_timer_oc_start_by_it (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Output Compare signal generation in interrupt mode. More...
void | ald_timer_oc_stop_by_it (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Output Compare signal generation in interrupt mode. More...
ald_status_t | ald_timer_oc_start_by_dma (timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER Output Compare signal generation in DMA mode. More...
void | ald_timer_oc_stop_by_dma (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Output Compare signal generation in DMA mode. More...
ald_status_t | ald_timer_pwm_init (timer_handle_t *hperh)
Initializes the TIMER PWM Time Base according to the specified parameters in the timer_handle_t and create the associated handle. More...
void | ald_timer_pwm_start (timer_handle_t *hperh, timer_channel_t ch)
Starts the PWM signal generation. More...
void | ald_timer_pwm_stop (timer_handle_t *hperh, timer_channel_t ch)
Stops the PWM signal generation. More...
void | ald_timer_pwm_start_by_it (timer_handle_t *hperh, timer_channel_t ch)
Starts the PWM signal generation in interrupt mode. More...
void | ald_timer_pwm_stop_by_it (timer_handle_t *hperh, timer_channel_t ch)
Stops the PWM signal generation in interrupt mode. More...
void | ald_timer_pwm_set_freq (timer_handle_t *hperh, uint16_t freq)
Set the PWM freq. More...
void | ald_timer_pwm_set_duty (timer_handle_t *hperh, timer_channel_t ch, uint16_t duty)
Set the PWM duty. More...
void | ald_timer_pwm_set_input (timer_handle_t *hperh, timer_channel_t ch)
Set capture the PWM. More...
ald_status_t | ald_timer_pwm_start_by_dma (timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER PWM signal generation in DMA mode. More...
void | ald_timer_pwm_stop_by_dma (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER PWM signal generation in DMA mode. More...
ald_status_t | ald_timer_ic_init (timer_handle_t *hperh)
Initializes the TIMER Input Capture Time base according to the specified parameters in the timer_handle_t and create the associated handle. More...
void | ald_timer_ic_start (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Input Capture measurement. More...
void | ald_timer_ic_stop (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Input Capture measurement. More...
void | ald_timer_ic_start_by_it (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Input Capture measurement in interrupt mode. More...
void | ald_timer_ic_stop_by_it (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Input Capture measurement in interrupt mode. More...
ald_status_t | ald_timer_ic_start_by_dma (timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER Input Capture measurement in DMA mode. More...
void | ald_timer_ic_stop_by_dma (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Input Capture measurement in DMA mode. More...
ald_status_t | ald_timer_one_pulse_init (timer_handle_t *hperh, timer_op_mode_t mode)
Initializes the TIMER One Pulse Time Base according to the specified parameters in the timer_handle_t and create the associated handle. More...
void | ald_timer_one_pulse_start (timer_handle_t *hperh, timer_op_output_channel_t ch)
Starts the TIMER One Pulse signal generation. More...
void | ald_timer_one_pulse_stop (timer_handle_t *hperh, timer_op_output_channel_t ch)
Stops the TIMER One Pulse signal generation. More...
void | ald_timer_one_pulse_start_by_it (timer_handle_t *hperh, timer_op_output_channel_t ch)
Starts the TIMER One Pulse signal generation in interrupt mode. More...
void | ald_timer_one_pulse_stop_by_it (timer_handle_t *hperh, timer_op_output_channel_t ch)
Stops the TIMER One Pulse signal generation in interrupt mode. More...
ald_status_t | ald_timer_encoder_init (timer_handle_t *hperh, timer_encoder_init_t *config)
Initializes the TIMER Encoder Interface and create the associated handle. More...
void | ald_timer_encoder_start (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Encoder Interface. More...
void | ald_timer_encoder_stop (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Encoder Interface. More...
void | ald_timer_encoder_start_by_it (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Encoder Interface in interrupt mode. More...
void | ald_timer_encoder_stop_by_it (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Encoder Interface in interrupt mode. More...
ald_status_t | ald_timer_encoder_start_by_dma (timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf1, uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2)
Starts the TIMER Encoder Interface in DMA mode. More...
void | ald_timer_encoder_stop_by_dma (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Encoder Interface in DMA mode. More...
ald_status_t | ald_timer_hall_sensor_init (timer_handle_t *hperh, timer_hall_sensor_init_t *config)
Initializes the TIMER Encoder Interface and create the associated handle. More...
void | ald_timer_hall_sensor_start (timer_handle_t *hperh)
Starts the TIMER hall sensor interface. More...
void | ald_timer_hall_sensor_stop (timer_handle_t *hperh)
Stops the TIMER hall sensor interface. More...
void | ald_timer_hall_sensor_start_by_it (timer_handle_t *hperh)
Starts the TIMER hall sensor interface in interrupt mode. More...
void | ald_timer_hall_sensor_stop_by_it (timer_handle_t *hperh)
Stops the TIMER hall sensor interface in interrupt mode. More...
ald_status_t | ald_timer_hall_sensor_start_by_dma (timer_handle_t *hperh, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER hall sensor interface in DMA mode. More...
void | ald_timer_hall_sensor_stop_by_dma (timer_handle_t *hperh)
Stops the TIMER hall sensor interface in DMA mode. More...
void | ald_timer_ocn_start (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER output compare signal generation on the complementary output. More...
void | ald_timer_ocn_stop (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER output compare signal generation on the complementary output. More...
void | ald_timer_ocn_start_by_it (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER output compare signal generation on the complementary output. in interrupt mode. More...
void | ald_timer_ocn_stop_by_it (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER output compare signal generation on the complementary output. in interrupt mode. More...
ald_status_t | ald_timer_ocn_start_by_dma (timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER output compare signal generation on the complementary output. in DMA mode. More...
void | ald_timer_ocn_stop_by_dma (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER output compare signal generation on the complementary output. in DMA mode. More...
void | ald_timer_pwmn_start (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER PWM signal generation on the complementary output. More...
void | ald_timer_pwmn_stop (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER PWM signal generation on the complementary output. More...
void | ald_timer_pwmn_start_by_it (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER PWM signal generation on the complementary output. in interrupt mode. More...
void | ald_timer_pwmn_stop_by_it (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER PWM signal generation on the complementary output. in interrupt mode. More...
ald_status_t | ald_timer_pwmn_start_by_dma (timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER PWM signal generation on the complementary output. in DMA mode. More...
void | ald_timer_pwmn_stop_by_dma (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER PWM signal generation on the complementary output. in DMA mode. More...
void | ald_timer_one_pulse_n_start (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER one pulse signal generation on the complementary output. More...
void | ald_timer_one_pulse_n_stop (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER one pulse signal generation on the complementary output. More...
void | ald_timer_one_pulse_n_start_by_it (timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER one pulse signal generation on the complementary output. in interrupt mode. More...
void | ald_timer_one_pulse_n_stop_by_it (timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER one pulse signal generation on the complementary output. in interrupt mode. More...
ald_status_t | ald_timer_oc_config_channel (timer_handle_t *hperh, timer_oc_init_t *config, timer_channel_t ch)
Initializes the TIMER Output Compare Channels according to the specified parameters in the timer_oc_init_t. More...
ald_status_t | ald_timer_ic_config_channel (timer_handle_t *hperh, timer_ic_init_t *config, timer_channel_t ch)
Initializes the TIMER Input Capture Channels according to the specified parameters in the timer_ic_init_t. More...
ald_status_t | ald_timer_one_pulse_config_channel (timer_handle_t *hperh, timer_one_pulse_init_t *config, timer_channel_t ch_out, timer_channel_t ch_in)
Initializes the TIMER One Pulse Channels according to the specified parameters in the timer_one_pulse_init_t. More...
ald_status_t | ald_timer_config_oc_ref_clear (timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch)
Configures the OCRef clear feature. More...
ald_status_t | ald_timer_config_clock_source (timer_handle_t *hperh, timer_clock_config_t *config)
Configures the clock source to be used. More...
ald_status_t | ald_timer_config_ti1_input (timer_handle_t *hperh, uint32_t ti1_select)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1_input, CH2_input & CH3_input. More...
ald_status_t | ald_timer_slave_config_sync (timer_handle_t *hperh, timer_slave_config_t *config)
Configures the TIMER in Slave mode. More...
ald_status_t | ald_timer_slave_config_sync_by_it (timer_handle_t *hperh, timer_slave_config_t *config)
Configures the TIMER in Slave mode in interrupt mode. More...
ald_status_t | ald_timer_generate_event (timer_handle_t *hperh, timer_event_source_t event)
Generate a software event. More...
uint32_t | ald_timer_read_capture_value (timer_handle_t *hperh, timer_channel_t ch)
Read the captured value from Capture Compare unit. More...
void | ald_timer_set_output_mode (timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch)
Sets TIMER output mode. More...
void | ald_timer_com_change_config (timer_handle_t *hperh, timer_com_channel_config_t *config)
Configure the channel in commutation event. More...
void | ald_timer_com_event_config (timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi)
Configure the TIMER commutation event sequence. More...
void | ald_timer_com_event_config_it (timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi)
Configure the TIMER commutation event sequence with interrupt. More...
void | ald_timer_break_dead_time_config (timer_handle_t *hperh, timer_break_dead_time_t *config)
Configure the break, dead timere, lock level state. More...
void | ald_timer_master_sync_config (timer_handle_t *hperh, timer_master_config_t *config)
Configure the master mode. More...
void | ald_timer_irq_handler (timer_handle_t *hperh)
This function handles TIMER interrupts requests. More...
void | ald_timer_dma_req_config (timer_handle_t *hperh, timer_dma_req_t req, type_func_t state)
Configure DMA request source. More...
void | ald_timer_interrupt_config (timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts. More...
it_status_t | ald_timer_get_it_status (timer_handle_t *hperh, timer_it_t it)
Get the status of TIMER interrupt source. More...
flag_status_t | ald_timer_get_flag_status (timer_handle_t *hperh, timer_flag_t flag)
Get the status of TIMER interrupt flag. More...
void | ald_timer_clear_flag_status (timer_handle_t *hperh, timer_flag_t flag)
Clear the TIMER interrupt flag. More...
timer_state_t | ald_timer_get_state (timer_handle_t *hperh)
Return the TIMER Base state. More...

Detailed Description

TIMER module driver. This is the common part of the TIMER initialization.

Version
V1.0
Date
06 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_timer.h.


ALD User Manual: D:/svn/src/ald_trng.c File Reference

  • D:
  • svn
  • src
Functions
ald_trng.c File Reference

TRNG module driver. More...

#include "ald_trng.h"
Include dependency graph for ald_trng.c:

Go to the source code of this file.

Functions

void | trng_reset (trng_handle_t *hperh)
Reset the TRNG peripheral. More...
ald_status_t | ald_trng_init (trng_handle_t *hperh)
Initializes the TRNG according to the specified parameters in the trng_init_t. More...
uint32_t | ald_trng_get_result (trng_handle_t *hperh)
Get the result. More...
void | ald_trng_interrupt_config (trng_handle_t *hperh, trng_it_t it, type_func_t state)
Enable/disable the specified interrupts. More...
flag_status_t | ald_trng_get_status (trng_handle_t *hperh, trng_status_t status)
Get the status of SR register. More...
it_status_t | ald_trng_get_it_status (trng_handle_t *hperh, trng_it_t it)
Get the status of interrupt source. More...
flag_status_t | ald_trng_get_flag_status (trng_handle_t *hperh, trng_flag_t flag)
Get the status of interrupt flag. More...
void | ald_trng_clear_flag_status (trng_handle_t *hperh, trng_flag_t flag)
Clear the interrupt flag. More...
void | ald_trng_irq_handler (trng_handle_t *hperh)
This function handles TRNG interrupt request. More...

Detailed Description

TRNG module driver.

Version
V1.0
Date
26 Jun 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_trng.c.


ALD User Manual: D:/svn/src/ald_trng.h File Reference

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  • svn
  • src
Data Structures | Macros | Typedefs | Enumerations | Functions
ald_trng.h File Reference

Header file of TRNG module driver. More...

#include "utils.h"
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Data Structures

struct | trng_init_t
TRNG init structure definition. More...
struct | trng_handle_s
TRNG Handle Structure definition. More...

Macros

#define | TRNG_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))
#define | TRNG_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))
#define | TRNG_ADJM_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))
#define | TRNG_ADJM_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))
#define | IS_TRNG_DATA_WIDTH(x)
#define | IS_TRNG_SEED_TYPE(x)
#define | IS_TRNG_STATUS(x)
#define | IS_TRNG_IT(x)
#define | IS_TRNG_FLAG(x)
#define | IS_TRNG_ADJC(x) ((x) < 4)
#define | IS_TRNG_T_START(x) ((x) < 8)

Typedefs

typedef struct trng_handle_s trng_handle_t
TRNG Handle Structure definition. More...

Enumerations

enum | trng_data_width_t { TRNG_DSEL_1B = 0x0U, TRNG_DSEL_8B = 0x1U, TRNG_DSEL_16B = 0x2U, TRNG_DSEL_32B = 0x3U }
Data width. More...
enum | trng_seed_type_t { TRNG_SEED_TYPE_0 = 0x0U, TRNG_SEED_TYPE_1 = 0x1U, TRNG_SEED_TYPE_LAST = 0x2U, TRNG_SEED_TYPE_SEED = 0x3U }
seed type More...
enum | trng_state_t { TRNG_STATE_RESET = 0x0U, TRNG_STATE_READY = 0x1U, TRNG_STATE_BUSY = 0x2U, TRNG_STATE_ERROR = 0x4U }
TRNG state structures definition. More...
enum | trng_status_t { TRNG_STATUS_START = (1U << 0), TRNG_STATUS_DAVLD = (1U << 1), TRNG_STATUS_SERR = (1U << 2) }
State type. More...
enum | trng_it_t { TRNG_IT_START = (1U << 0), TRNG_IT_DAVLD = (1U << 1), TRNG_IT_SERR = (1U << 2) }
Interrupt type. More...
enum | trng_flag_t { TRNG_IF_START = (1U << 0), TRNG_IF_DAVLD = (1U << 1), TRNG_IF_SERR = (1U << 2) }
Interrupt flag type. More...

Functions

ald_status_t | ald_trng_init (trng_handle_t *hperh)
Initializes the TRNG according to the specified parameters in the trng_init_t. More...
uint32_t | ald_trng_get_result (trng_handle_t *hperh)
Get the result. More...
void | ald_trng_interrupt_config (trng_handle_t *hperh, trng_it_t it, type_func_t state)
Enable/disable the specified interrupts. More...
flag_status_t | ald_trng_get_status (trng_handle_t *hperh, trng_status_t status)
Get the status of SR register. More...
it_status_t | ald_trng_get_it_status (trng_handle_t *hperh, trng_it_t it)
Get the status of interrupt source. More...
flag_status_t | ald_trng_get_flag_status (trng_handle_t *hperh, trng_flag_t flag)
Get the status of interrupt flag. More...
void | ald_trng_clear_flag_status (trng_handle_t *hperh, trng_flag_t flag)
Clear the interrupt flag. More...
void | ald_trng_irq_handler (trng_handle_t *hperh)
This function handles TRNG interrupt request. More...

Detailed Description

Header file of TRNG module driver.

Version
V1.0
Date
26 Jun 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_trng.h.


ALD User Manual: D:/svn/src/ald_tsense.c File Reference

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  • svn
  • src
Functions | Variables
ald_tsense.c File Reference

TSENSE module driver. More...

#include "ald_tsense.h"
#include "ald_bkpc.h"
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Go to the source code of this file.

Functions

void | ald_tsense_init (void)
Initializes the TSENSE according to the specified. More...
void | ald_tsense_source_select (tsense_source_sel_t sel)
Configure the TSENSE source. More...
ald_status_t | ald_tsense_get_value (uint16_t *tsense)
Get the current temperature. More...
void | ald_tsense_get_value_by_it (tsense_cbk cbk)
Get the current temperature by interrupt. More...
void | ald_tsense_irq_handler (void)
This function handles TSENSE interrupt request. More...

Variables

tsense_cbk __tsense_cbk

Detailed Description

TSENSE module driver.

Version
V1.0
Date
26 Jun 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_tsense.c.


ALD User Manual: D:/svn/src/ald_tsense.h File Reference

  • D:
  • svn
  • src
Macros | Typedefs | Enumerations | Functions
ald_tsense.h File Reference

Header file of TSENSE module driver. More...

#include "utils.h"
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Macros

#define | TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0U))
#define | TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669U))
#define | TSENSE_ENABLE()
#define | TSENSE_DISABLE()
#define | TSENSE_REQ_ENABLE()
#define | TSENSE_REQ_DISABLE()
#define | TSENSE_CTN_ENABLE()
#define | TSENSE_CTN_DISABLE()
#define | TSENSE_RESET()
#define | TSENSE_LTGR_WR(data)
#define | TSENSE_HTGR_WR(data)
#define | TSENSE_TBDR_WR(data)
#define | TSENSE_TCALBDR_WR(data)
#define | IS_TSENSE_SOURCE_SEL(x)

Typedefs

typedef void(* tsense_cbk) (uint16_t value, ald_status_t status)
Define callback function type. More...

Enumerations

enum tsense_update_cycle_t {
TSENSE_UPDATE_CYCLE_3 = 0x3U, TSENSE_UPDATE_CYCLE_4 = 0x4U, TSENSE_UPDATE_CYCLE_5 = 0x5U, TSENSE_UPDATE_CYCLE_6 = 0x6U,
TSENSE_UPDATE_CYCLE_7 = 0x7U
}
Temperature update time. More...
enum tsense_output_mode_t {
TSENSE_OUTPUT_MODE_200 = 0x0U, TSENSE_OUTPUT_MODE_400 = 0x1U, TSENSE_OUTPUT_MODE_800 = 0x2U, TSENSE_OUTPUT_MODE_1600 = 0x3U,
TSENSE_OUTPUT_MODE_3200 = 0x4U
}
Temperature output mode. More...
enum tsense_source_sel_t { TSENSE_SOURCE_LOSC = 0x0U, TSENSE_SOURCE_LRC = 0x1U }
Source select. More...

Functions

void | ald_tsense_init (void)
Initializes the TSENSE according to the specified. More...
void | ald_tsense_source_select (tsense_source_sel_t sel)
Configure the TSENSE source. More...
ald_status_t | ald_tsense_get_value (uint16_t *tsense)
Get the current temperature. More...
void | ald_tsense_get_value_by_it (tsense_cbk cbk)
Get the current temperature by interrupt. More...
void | ald_tsense_irq_handler (void)
This function handles TSENSE interrupt request. More...

Detailed Description

Header file of TSENSE module driver.

Version
V1.0
Date
26 Jun 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_tsense.h.


ALD User Manual: D:/svn/src/ald_uart.c File Reference

  • D:
  • svn
  • src
Functions
ald_uart.c File Reference

UART module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: More...

#include "ald_uart.h"
#include "ald_cmu.h"
Include dependency graph for ald_uart.c:

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Functions

static void | uart_dma_send_cplt (void *arg)
DMA uart transmit process complete callback. More...
static void | uart_dma_recv_cplt (void *arg)
DMA uart receive process complete callback. More...
static void | uart_dma_error (void *arg)
DMA uart communication error callback. More...
static ald_status_t | uart_wait_flag (uart_handle_t *hperh, uart_status_t flag, flag_status_t status, uint32_t timeout)
This function handles uart Communication Timeout. More...
static ald_status_t | __uart_send_by_it (uart_handle_t *hperh)
Sends an amount of data in non blocking mode. More...
static ald_status_t | __uart_end_send_by_it (uart_handle_t *hperh)
Wraps up transmission in non blocking mode. More...
static ald_status_t | __uart_recv_by_it (uart_handle_t *hperh)
Receives an amount of data in non blocking mode. More...
void | ald_uart_reset (uart_handle_t *hperh)
Reset UART peripheral. More...
void | ald_uart_init (uart_handle_t *hperh)
Initializes the UARTx according to the specified parameters in the uart_handle_t. More...
void | ald_uart_rs485_config (uart_handle_t *hperh, uart_rs485_config_t *config)
Configure the RS485 mode according to the specified parameters in the uart_rs485_config_t. More...
void | ald_uart_scard_config (uart_handle_t *hperh, uart_scard_config_t *config)
Configure the smart card mode according to the specified parameters in the uart_scard_config_t. More...
ald_status_t | ald_uart_send (uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Sends an amount of data in blocking mode. More...
ald_status_t | ald_uart_recv (uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Receives an amount of data in blocking mode. More...
ald_status_t | ald_uart_send_n_lock (uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Sends an amount of data in blocking mode. Don't care about device lock. This is for RTOS. More...
ald_status_t | ald_uart_recv_n_lock (uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Receives an amount of data in blocking mode. Don't care about device lock. This is for RTOS. More...
ald_status_t | ald_uart_send_by_it (uart_handle_t *hperh, uint8_t *buf, uint16_t size)
Sends an amount of data in non blocking mode. More...
ald_status_t | ald_uart_recv_by_it (uart_handle_t *hperh, uint8_t *buf, uint16_t size)
Receives an amount of data in non blocking mode. More...
ald_status_t | ald_uart_recv_frame_by_it (uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t t_out)
Receives an frame of data in non blocking mode. More...
ald_status_t | ald_uart_send_by_dma (uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
Sends an amount of data in non blocking mode. More...
ald_status_t | ald_uart_recv_by_dma (uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
Receives an amount of data in non blocking mode. More...
ald_status_t | ald_uart_dma_pause (uart_handle_t *hperh)
Pauses the DMA Transfer. More...
ald_status_t | ald_uart_dma_resume (uart_handle_t *hperh)
Resumes the DMA Transfer. More...
ald_status_t | ald_uart_dma_stop (uart_handle_t *hperh)
Stops the DMA Transfer. More...
void | ald_uart_irq_handler (uart_handle_t *hperh)
This function handles UART interrupt request. More...
void | ald_uart_irq_handler_fast (uart_handle_t *hperh)
This function handles UART interrupt request. More...
void | ald_uart_interrupt_config (uart_handle_t *hperh, uart_it_t it, type_func_t state)
Enable/disable the specified UART interrupts. More...
void | ald_uart_dma_req_config (uart_handle_t *hperh, uart_dma_req_t req, type_func_t state)
Configure UART DMA request. More...
void | ald_uart_tx_fifo_config (uart_handle_t *hperh, uart_txfifo_t config)
Configure transmit fifo parameters. More...
void | ald_uart_rx_fifo_config (uart_handle_t *hperh, uart_rxfifo_t config)
Configure receive fifo parameters. More...
void | uart_lin_break_detect_irq (uart_handle_t *hperh, type_func_t status)
Enable/Disable break signal detect interrup. More...
void | ald_uart_lin_send_break (uart_handle_t *hperh)
request to send a frame of break. More...
void | ald_uart_lin_detect_break_len_config (uart_handle_t *hperh, uart_lin_break_len_t len)
Configure the length of break frame to be detect. More...
void | ald_uart_auto_baud_config (uart_handle_t *hperh, uart_auto_baud_mode_t mode)
Configure the mode of auto-baud-rate detect. More...
ald_status_t | ald_uart_rs485_send_addr (uart_handle_t *hperh, uint16_t addr, uint32_t timeout)
Send address in RS485 mode. More...
it_status_t | ald_uart_get_it_status (uart_handle_t *hperh, uart_it_t it)
Get the status of UART interrupt source. More...
flag_status_t | ald_uart_get_status (uart_handle_t *hperh, uart_status_t status)
Get the status of UART_SR register. More...
flag_status_t | ald_uart_get_flag_status (uart_handle_t *hperh, uart_flag_t flag)
Get the status of UART interrupt flag. More...
flag_status_t | ald_uart_get_mask_flag_status (uart_handle_t *hperh, uart_flag_t flag)
Get the status of interrupt flag and interupt source. More...
void | ald_uart_clear_flag_status (uart_handle_t *hperh, uart_flag_t flag)
Clear the UART interrupt flag. More...
uart_state_t | ald_uart_get_state (uart_handle_t *hperh)
Returns the UART state. More...
uint32_t | ald_uart_get_error (uart_handle_t *hperh)
Return the UART error code. More...

Detailed Description

UART module driver. This file provides firmware functions to manage the following functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:

  • Initialization and Configuration functions
  • IO operation functions
  • Peripheral Control functions
  • Peripheral State and Errors functions
Version
V1.0
Date
21 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

==============================================================================
                      ##### How to use this driver #####
==============================================================================
[..]
  The UART driver can be used as follows:

  (#) Declare a uart_handle_t handle structure.

  (#) Initialize the UART low level resources:
      (##) Enable the UARTx interface clock.
      (##) UART pins configuration:
          (+++) Enable the clock for the UART GPIOs.
          (+++) Configure the UART pins (TX as alternate function pull-up, RX as alternate function Input).
      (##) NVIC configuration if you need to use interrupt process (ald_uart_send_by_it()
           and ald_uart_recv_by_it() APIs):
          (+++) Configure the uart interrupt priority.
          (+++) Enable the NVIC UART IRQ handle.
      (##) DMA Configuration if you need to use DMA process (ald_uart_send_by_dma()
           and ald_uart_recv_by_dma() APIs):
          (+++) Select the DMA Tx/Rx channel.
          (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.

  (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
      flow control and Mode(Receiver/Transmitter) in the hperh Init structure.

  (#) Initialize the UART registers by calling the ald_uart_init() API.

   [..]
      Three operation modes are available within this driver:

   *** Polling mode IO operation ***
   =================================
   [..]
     (+) Send an amount of data in blocking mode using ald_uart_send()
     (+) Receive an amount of data in blocking mode using ald_uart_recv()

   *** Interrupt mode IO operation ***
   ===================================
   [..]
     (+) Send an amount of data in non blocking mode using ald_uart_send_by_it()
     (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can
         add his own code by customization of function pointer hperh->tx_cplt_cbk()
     (+) Receive an amount of data in non blocking mode using ald_uart_recv_by_it()
     (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can
         add his own code by customization of function pointer hperh->rx_cplt_cbk()
     (+) In case of transfer Error, hperh->error_cbk() function is executed and user can
         add his own code by customization of function pointer hperh->error_cbk()

   *** DMA mode IO operation ***
   ==============================
   [..]
     (+) Send an amount of data in non blocking mode (DMA) using ald_uart_send_by_dma()
     (+) At transmission end of transfer hperh->tx_cplt_cbk() is executed and user can
         add his own code by customization of function pointer hperh->tx_cplt_cbk()
     (+) Receive an amount of data in non blocking mode (DMA) using ald_uart_recv_by_dma()
     (+) At reception end of transfer hperh->rx_cplt_cbk() is executed and user can
         add his own code by customization of function pointer hperh->rx_cplt_cbk()
     (+) In case of transfer Error, hperh->error_cbk() function is executed and user can
         add his own code by customization of function pointer hperh->error_cbk()
     (+) Pause the DMA Transfer using ald_uart_dma_pause()
     (+) Resume the DMA Transfer using ald_uart_dma_resume()
     (+) Stop the DMA Transfer using ald_uart_dma_stop()

Definition in file ald_uart.c.


ALD User Manual: D:/svn/src/ald_uart.h File Reference

  • D:
  • svn
  • src
Data Structures | Macros | Typedefs | Enumerations | Functions
ald_uart.h File Reference

Header file of UART module library. More...

#include "utils.h"
#include "ald_dma.h"
Include dependency graph for ald_uart.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Data Structures

struct | uart_init_t
UART init structure definition. More...
struct | uart_handle_s
UART handle structure definition. More...
struct | uart_rs485_config_t
UART RS485 configure structure definition. More...
struct | uart_scard_config_t
UART Smart card configure structure definition. More...

Macros

#define | UART_RX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_RXEN_MSK))
#define | UART_RX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RXEN_MSK))
#define | UART_TX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK))
#define | UART_TX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK))
#define | UART_RX_TIMEOUT_ENABLE(hperh) (SET_BIT((hperh)->perh->RTOR, UART_RTOR_RTOEN_MSK))
#define | UART_RX_TIMEOUT_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->RTOR, UART_RTOR_RTOEN_MSK))
#define | UART_MSB_FIRST_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK))
#define | UART_MSB_FIRST_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK))
#define | UART_DATA_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_DATAINV_MSK))
#define | UART_DATA_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_DATAINV_MSK))
#define | UART_RX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_RXINV_MSK))
#define | UART_RX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RXINV_MSK))
#define | UART_TX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_TXINV_MSK))
#define | UART_TX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_TXINV_MSK))
#define | UART_TX_RX_SWAP_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_SWAP_MSK))
#define | UART_TX_RX_SWAP_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_SWAP_MSK))
#define | UART_HDSEL_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_HDEN_MSK))
#define | UART_HDSEL_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_HDEN_MSK))
#define | UART_FIFO_TX_RESET(hperh) (SET_BIT((hperh)->perh->FCON, UART_FCON_TFRST_MSK))
#define | UART_FIFO_RX_RESET(hperh) (SET_BIT((hperh)->perh->FCON, UART_FCON_RFRST_MSK))
#define | UART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_LPBKEN_MSK))
#define | UART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_LPBKEN_MSK))
#define | UART_AUTOBR_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK))
#define | UART_AUTOBR_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK))
#define | UART_AUTOBR_REPT(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_ABRREPT_MSK))
#define | UART_GET_BRR_VALUE(hperh) (READ_REG((hperh)->perh->BRR))
#define | UART_SET_TIMEOUT_VALUE(x, y) (MODIFY_REG((x)->perh->RTOR, UART_RTOR_RTO_MSK, (y) << UART_RTOR_RTO_POSS))
#define | UART_ENABLE_SCARD_CLK(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCLKEN_MSK))
#define | UART_DISABLE_SCARD_CLK(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCLKEN_MSK))
#define | UART_ENABLE_SCARD_NACK(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCNACK_MSK))
#define | UART_DISABLE_SCARD_NACK(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCNACK_MSK))
#define | UART_SCARD_ENABLE(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCEN_MSK))
#define | UART_SCARD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCEN_MSK))
#define | IS_UART_SCARD(x)
#define | IS_UART_ALL(x)
#define | IS_UART_WORD_LENGTH(x)
#define | IS_UART_STOPBITS(x)
#define | IS_UART_PARITY(x)
#define | IS_UART_MODE(x)
#define | IS_UART_HARDWARE_FLOW_CONTROL(x)
#define | IS_UART_LIN_BREAK_LEN(x)
#define | IS_UART_TXFIFO_TYPE(x)
#define | IS_UART_RXFIFO_TYPE(x)
#define | IS_UART_AUTO_BAUD_MODE(x)
#define | IS_UART_DMA_REQ(x)
#define | IS_UART_STATUS(x)
#define | IS_UART_IT(x)
#define | IS_UART_IF(x)
#define | IS_UART_SCARD_CLK(x)
#define | IS_UART_BAUDRATE(x) (((x) > 0) && ((x) < 0x44AA21))
#define | IS_UART_DATA(x) ((x) <= 0x1FF)
#define | UART_STATE_TX_MASK (1U << 4)
#define | UART_STATE_RX_MASK (1U << 5)

Typedefs

typedef struct uart_handle_s uart_handle_t
UART handle structure definition. More...

Enumerations

enum | uart_word_length_t { UART_WORD_LENGTH_8B = 0x0U, UART_WORD_LENGTH_7B = 0x1U, UART_WORD_LENGTH_6B = 0x2U, UART_WORD_LENGTH_5B = 0x3U }
UART word length. More...
enum | uart_stop_bits_t { UART_STOP_BITS_1 = 0x0U, UART_STOP_BITS_2 = 0x1U, UART_STOP_BITS_0_5 = 0x0U, UART_STOP_BITS_1_5 = 0x1U }
UART stop bits. More...
enum | uart_parity_t { UART_PARITY_NONE = 0x0U, UART_PARITY_ODD = 0x1U, UART_PARITY_EVEN = 0x3U }
UART parity. More...
enum uart_mode_t {
UART_MODE_UART = 0x0U, UART_MODE_LIN = 0x1U, UART_MODE_IrDA = 0x2U, UART_MODE_RS485 = 0x3U,
UART_MODE_HDSEL = 0x4U, UART_MODE_SCARD = 0x5U
}
UART mode. More...
enum | uart_hw_flow_ctl_t { UART_HW_FLOW_CTL_DISABLE = 0x0U, UART_HW_FLOW_CTL_ENABLE = 0x1U }
UART hardware flow control. More...
enum uart_state_t {
UART_STATE_RESET = 0x00U, UART_STATE_READY = 0x01U, UART_STATE_BUSY = 0x02U, UART_STATE_BUSY_TX = 0x11U,
UART_STATE_BUSY_RX = 0x21U, UART_STATE_BUSY_TX_RX = 0x31U, UART_STATE_TIMEOUT = 0x03U, UART_STATE_ERROR = 0x04U
}
ALD UART state. More...
enum uart_error_t {
UART_ERROR_NONE = ((uint32_t)0x00U), UART_ERROR_PE = ((uint32_t)0x01U), UART_ERROR_NE = ((uint32_t)0x02U), UART_ERROR_FE = ((uint32_t)0x04U),
UART_ERROR_ORE = ((uint32_t)0x08U), UART_ERROR_DMA = ((uint32_t)0x10U)
}
UART error codes. More...
enum | scard_clk_div_t { SCARD_CLOCK_DIV1 = 0x0U, SCARD_CLOCK_DIV2 = 0x1U, SCARD_CLOCK_DIV4 = 0x2U, SCARD_CLOCK_DIV6 = 0x3U }
Smart_card clock division. More...
enum scard_retry_t {
SCARD_RETRY_CNT0 = 0x0U, SCARD_RETRY_CNT1 = 0x1U, SCARD_RETRY_CNT2 = 0x2U, SCARD_RETRY_CNT3 = 0x3U,
SCARD_RETRY_CNT4 = 0x4U, SCARD_RETRY_CNT5 = 0x5U, SCARD_RETRY_CNT6 = 0x6U, SCARD_RETRY_CNT7 = 0x7U
}
Smart_card Rx/Tx handle retry time. More...
enum | uart_lin_break_len_t { LIN_BREAK_LEN_10B = 0x0U, LIN_BREAK_LEN_11B = 0x1U }
LIN detection break length. More...
enum | uart_txfifo_t { UART_TXFIFO_EMPTY = 0x0U, UART_TXFIFO_2BYTE = 0x1U, UART_TXFIFO_4BYTE = 0x2U, UART_TXFIFO_8BYTE = 0x3U }
UART TXFIFO size. More...
enum | uart_rxfifo_t { UART_RXFIFO_1BYTE = 0x0U, UART_RXFIFO_4BYTE = 0x1U, UART_RXFIFO_8BYTE = 0x2U, UART_RXFIFO_14BYTE = 0x3U }
UART RXFIFO size. More...
enum | uart_auto_baud_mode_t { UART_ABRMOD_1_TO_0 = 0x0U, UART_ABRMOD_1 = 0x1U, UART_ABRMOD_0_TO_1 = 0x2U }
UART auto-baud mode. More...
enum | uart_dma_req_t { UART_DMA_REQ_TX = 0x0U, UART_DMA_REQ_RX = 0x1U }
UART DMA Requests. More...
enum uart_status_t {
UART_STATUS_PERR = (1U << 0), UART_STATUS_FERR = (1U << 1), UART_STATUS_BKERR = (1U << 2), UART_STATUS_CTSSTA = (1U << 3),
UART_STATUS_RSBUSY = (1U << 8), UART_STATUS_RFTH = (1U << 9), UART_STATUS_RFEMPTY = (1U << 10), UART_STATUS_RFFULL = (1U << 11),
UART_STATUS_RFOERR = (1U << 12), UART_STATUS_RFUERR = (1U << 13), UART_STATUS_TSBUSY = (1U << 14), UART_STATUS_TFTH = (1U << 15),
UART_STATUS_TFEMPTY = (1U << 16), UART_STATUS_TFFULL = (1U << 17), UART_STATUS_TFOERR = (1U << 18)
}
UART status types. More...
enum uart_it_t {
UART_IT_RXBERR = (1U << 0), UART_IT_ABEND = (1U << 1), UART_IT_ABTO = (1U << 2), UART_IT_DCTS = (1U << 3),
UART_IT_RXTO = (1U << 4), UART_IT_ADDRM = (1U << 5), UART_IT_LINBK = (1U << 6), UART_IT_EOB = (1U << 7),
UART_IT_NOISE = (1U << 8), UART_IT_RFTH = (1U << 9), UART_IT_RFFULL = (1U << 11), UART_IT_RFOERR = (1U << 12),
UART_IT_RFUERR = (1U << 13), UART_IT_TSEMPTY = (1U << 14), UART_IT_TFTH = (1U << 15), UART_IT_TFEMPTY = (1U << 16),
UART_IT_TFOVER = (1U << 18)
}
UART interrupt types. More...
enum uart_flag_t {
UART_IF_RXBERR = (1U << 0), UART_IF_ABEND = (1U << 1), UART_IF_ABTO = (1U << 2), UART_IF_DCTS = (1U << 3),
UART_IF_RXTO = (1U << 4), UART_IF_ADDRM = (1U << 5), UART_IF_LINBK = (1U << 6), UART_IF_EOB = (1U << 7),
UART_IF_NOISE = (1U << 8), UART_IF_RFTH = (1U << 9), UART_IF_RFFULL = (1U << 11), UART_IF_RFOERR = (1U << 12),
UART_IF_RFUERR = (1U << 13), UART_IF_TBC = (1U << 14), UART_IF_TFTH = (1U << 15), UART_IF_TFEMPTY = (1U << 16),
UART_IF_TFOVER = (1U << 18)
}
UART flags types. More...

Functions

void | ald_uart_init (uart_handle_t *hperh)
Initializes the UARTx according to the specified parameters in the uart_handle_t. More...
void | ald_uart_reset (uart_handle_t *hperh)
Reset UART peripheral. More...
void | ald_uart_rs485_config (uart_handle_t *hperh, uart_rs485_config_t *config)
Configure the RS485 mode according to the specified parameters in the uart_rs485_config_t. More...
void | ald_uart_scard_config (uart_handle_t *hperh, uart_scard_config_t *config)
Configure the smart card mode according to the specified parameters in the uart_scard_config_t. More...
ald_status_t | ald_uart_send (uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Sends an amount of data in blocking mode. More...
ald_status_t | ald_uart_recv (uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Receives an amount of data in blocking mode. More...
ald_status_t | ald_uart_send_n_lock (uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Sends an amount of data in blocking mode. Don't care about device lock. This is for RTOS. More...
ald_status_t | ald_uart_recv_n_lock (uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Receives an amount of data in blocking mode. Don't care about device lock. This is for RTOS. More...
ald_status_t | ald_uart_send_by_it (uart_handle_t *hperh, uint8_t *buf, uint16_t size)
Sends an amount of data in non blocking mode. More...
ald_status_t | ald_uart_recv_by_it (uart_handle_t *hperh, uint8_t *buf, uint16_t size)
Receives an amount of data in non blocking mode. More...
ald_status_t | ald_uart_recv_frame_by_it (uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t t_out)
Receives an frame of data in non blocking mode. More...
ald_status_t | ald_uart_send_by_dma (uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
Sends an amount of data in non blocking mode. More...
ald_status_t | ald_uart_recv_by_dma (uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
Receives an amount of data in non blocking mode. More...
ald_status_t | ald_uart_dma_pause (uart_handle_t *hperh)
Pauses the DMA Transfer. More...
ald_status_t | ald_uart_dma_resume (uart_handle_t *hperh)
Resumes the DMA Transfer. More...
ald_status_t | ald_uart_dma_stop (uart_handle_t *hperh)
Stops the DMA Transfer. More...
void | ald_uart_irq_handler (uart_handle_t *hperh)
This function handles UART interrupt request. More...
void | ald_uart_irq_handler_fast (uart_handle_t *hperh)
This function handles UART interrupt request. More...
void | ald_uart_interrupt_config (uart_handle_t *hperh, uart_it_t it, type_func_t state)
Enable/disable the specified UART interrupts. More...
void | ald_uart_dma_req_config (uart_handle_t *hperh, uart_dma_req_t req, type_func_t state)
Configure UART DMA request. More...
void | ald_uart_tx_fifo_config (uart_handle_t *hperh, uart_txfifo_t config)
Configure transmit fifo parameters. More...
void | ald_uart_rx_fifo_config (uart_handle_t *hperh, uart_rxfifo_t config)
Configure receive fifo parameters. More...
void | uart_lin_break_detect_irq (uart_handle_t *hperh, type_func_t status)
Enable/Disable break signal detect interrup. More...
void | ald_uart_lin_send_break (uart_handle_t *hperh)
request to send a frame of break. More...
void | ald_uart_lin_detect_break_len_config (uart_handle_t *hperh, uart_lin_break_len_t len)
Configure the length of break frame to be detect. More...
void | ald_uart_auto_baud_config (uart_handle_t *hperh, uart_auto_baud_mode_t mode)
Configure the mode of auto-baud-rate detect. More...
ald_status_t | ald_uart_rs485_send_addr (uart_handle_t *hperh, uint16_t addr, uint32_t timeout)
Send address in RS485 mode. More...
it_status_t | ald_uart_get_it_status (uart_handle_t *hperh, uart_it_t it)
Get the status of UART interrupt source. More...
flag_status_t | ald_uart_get_status (uart_handle_t *hperh, uart_status_t status)
Get the status of UART_SR register. More...
flag_status_t | ald_uart_get_flag_status (uart_handle_t *hperh, uart_flag_t flag)
Get the status of UART interrupt flag. More...
flag_status_t | ald_uart_get_mask_flag_status (uart_handle_t *hperh, uart_flag_t flag)
Get the status of interrupt flag and interupt source. More...
void | ald_uart_clear_flag_status (uart_handle_t *hperh, uart_flag_t flag)
Clear the UART interrupt flag. More...
uart_state_t | ald_uart_get_state (uart_handle_t *hperh)
Returns the UART state. More...
uint32_t | ald_uart_get_error (uart_handle_t *hperh)
Return the UART error code. More...

Detailed Description

Header file of UART module library.

Version
V1.0
Date
21 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_uart.h.


ALD User Manual: D:/svn/src/ald_usb.c File Reference

  • D:
  • svn
  • src
Functions
ald_usb.c File Reference

USB module driver. More...

#include "ald_usb.h"
#include "ald_syscfg.h"
Include dependency graph for ald_usb.c:

Go to the source code of this file.

Functions

uint32_t | ald_usb_frame_number_get (void)
Gets the number of current frame. More...
void | ald_usb_otg_session_request (bool start)
Request the session. More...
uint32_t | ald_usb_mode_get (void)
Gets the mode. More...
void | ald_usb_high_speed_enable (bool enable)
Enable/Disable the high mode. More...
uint32_t | ald_usb_device_speed_get (void)
Gets the speed of the device. More...
uint32_t | ald_usb_num_ep_get (void)
Gets the number of the endpoint. More...
void | ald_usb_control_reset (void)
Reset USB Control. More...
void | ald_usb_clock_output (void)
Output USB clock via PA15, 60MHz/256=234.375KHz. More...
int | ald_usb_eye_diagram_start (uint8_t *buf, uint16_t len)
Starts eye diagram for high-speed host. More...
uint8_t | ald_usb_dev_get_addr (void)
Gets the address. More...
void | ald_usb_dev_set_addr (uint8_t addr)
Sets the address. More...
void | ald_usb_dev_connect (void)
Enable connection. More...
void | ald_usb_dev_disconnect (void)
Disable connection. More...
void | ald_usb_dev_ep_config (uint32_t ep_idx, uint32_t p_max, uint32_t flags)
Configure the endpoint in device mode. More...
void | ald_usb_dev_ep_get_config (uint32_t ep_idx, uint32_t *p_max, uint32_t *flags)
Gets the parameters of the endpoint. More...
void | ald_usb_dev_ep_data_ack (uint32_t ep_idx, bool last)
Acknowledge the data from the host. More...
void | ald_usb_dev_ep_stall (uint32_t ep_idx, uint32_t flags)
Stall the endpoint. More...
void | ald_usb_dev_ep_stall_clear (uint32_t ep_idx, uint32_t flags)
Cancel the stall status. More...
void | ald_usb_dev_ep_status_clear (uint32_t ep_idx, uint32_t flags)
Clear the status of the endpoint. More...
uint32_t | ald_usb_host_addr_get (uint32_t ep_idx, uint32_t flags)
Gets the device's address. More...
void | ald_usb_host_addr_set (uint32_t ep_idx, uint32_t addr, uint32_t flags)
Sets the device's address. More...
void | ald_usb_host_ep_config (uint32_t ep_idx, uint32_t p_max, uint32_t nak_val, uint32_t t_ep, uint32_t flags)
Configure the endpoint in host mode. More...
void | ald_usb_host_ep_data_ack (uint32_t ep_idx)
Acknowledge the data in host mode. More...
void | ald_usb_host_ep_data_toggle (uint32_t ep_idx, bool toggle, uint32_t flags)
Toggle the data in host mode. More...
void | ald_usb_host_ep_status_clear (uint32_t ep_idx, uint32_t flags)
Clear the status of endpoint in host mode. More...
uint32_t | ald_usb_host_hub_addr_get (uint32_t ep_idx, uint32_t flags)
Gets the HUB's address. More...
void | ald_usb_host_hub_addr_set (uint32_t ep_idx, uint32_t addr, uint32_t flags)
Sets the HUB's address. More...
void | ald_usb_host_pwr_disable (void)
Disable power. More...
void | ald_usb_host_pwr_enable (void)
Enable power. More...
void | ald_usb_host_pwr_config (uint32_t flags)
Configure power in host mode. More...
void | ald_usb_host_pwr_fault_disable (void)
Disable the fault parameters of the power. More...
void | ald_usb_host_pwr_fault_enable (void)
Enable the fault parameters of the power. More...
void | ald_usb_host_request_in (uint32_t ep_idx)
Request data IN(from device to host) More...
void | ald_usb_host_request_in_clear (uint32_t ep_idx)
Clear the status of request IN. More...
void | ald_usb_host_request_status (void)
Request data IN at endpoint 0. More...
void | ald_usb_host_reset (bool start)
Reset the USB's bus. More...
void | ald_usb_host_resume (bool start)
Resume the devices. More...
void | ald_usb_host_suspend (void)
Suspend the devices. More...
uint32_t | ald_usb_host_speed_get (void)
Gets the device's speed. More...
void | ald_usb_host_ep_speed_set (uint32_t ep_idx, uint32_t flags)
Sets the endpoint speed. More...
void | ald_usb_host_ep_ping (uint32_t ep_idx, bool enable)
Ping the endpoint. More...
uint32_t | ald_usb_ep_data_avail (uint32_t ep_idx)
Gets the size of the available data. More...
int32_t | ald_usb_ep_data_get (uint32_t ep_idx, uint8_t *data, uint32_t *size)
Gets the data from FIFO. More...
int32_t | ald_usb_ep_data_put (uint32_t ep_idx, uint8_t *data, uint32_t size)
Puts data to the FIFO. More...
int32_t | ald_usb_ep_data_send (uint32_t ep_idx, uint32_t tx_type)
Send data. More...
void | ald_usb_ep_data_toggle_clear (uint32_t ep_idx, uint32_t flags)
Clear the status of the toggle. More...
void | ald_usb_ep_req_packet_count (uint32_t ep_idx, uint32_t count)
Sets the size of request data IN. More...
uint32_t | ald_usb_ep_status (uint32_t ep_idx)
Gets the status of the endpoint. More...
void | ald_usb_ep_dma_config (uint32_t ep_idx, uint32_t flag, type_func_t en)
Configure the endpoint in DMA mode. More...
uint32_t | ald_usb_fifo_addr_get (uint32_t ep_idx)
Gets the address of the FIFO. More...
void | ald_usb_fifo_config_get (uint32_t ep_idx, uint32_t *addr, uint32_t *size, uint32_t flags)
Gets the parameters of the FIFO. More...
void | ald_usb_fifo_config_set (uint32_t ep_idx, uint32_t addr, uint32_t size, uint32_t flags)
Sets the parameters of the FIFO. More...
void | ald_usb_fifo_flush (uint32_t ep_idx, uint32_t flags)
Flush the FIFO. More...
void | ald_usb_int_disable (uint32_t flags)
Disable interrupt. More...
void | ald_usb_int_enable (uint32_t flags)
Enable interrupt. More...
uint32_t | ald_usb_int_status_get (void)
Gets the status of the interrupt. More...
void | ald_usb_int_disable_ep (uint32_t flags)
Disable interrupt of the endpoint. More...
void | ald_usb_int_enable_ep (uint32_t flags)
Enable interrupt of the endpoint. More...
uint32_t | ald_usb_int_status_ep_get (void)
Gets the ststus of the endpoint interrupt. More...
void | ald_usb_int_register (void)
Register USB's interrupt. More...
void | ald_usb_int_unregister (void)
Unregister USB's interrupt. More...
uint32_t | ald_usb_int_num_get (void)
Get USB's interrupt number. More...
void | ald_usb_dma_channel_config (uint8_t ch, uint32_t addr, uint32_t count, uint32_t ctrl)
Configure DMA's channel. More...
void | ald_usb_dma_mult_recv_start (uint32_t ep_idx)
Start multiple receive. More...
void | ald_usb_dma_channel_start (uint8_t ch)
Start DMA's machine. More...
void | ald_usb_dma_channel_stop (uint8_t ch)
Stop DMA's machine. More...
uint32_t | ald_usb_dma_get_interrupt_flag (void)
Gets flags of the interrupt. More...
uint32_t | ald_usb_dma_get_channel_error (uint8_t ch)
Gets the status of the error. More...
void | ald_usb_dma_clear_channel_error (uint8_t ch)
Clear the status of the error. More...
void | ald_usb_host_lpm_send (uint32_t addr, uint32_t ep_idx)
Transmit a LPM transaction in host mode. More...
void | ald_usb_host_lpm_config (uint32_t resume_time, uint32_t config)
Configure the LPM parameters in host mode. More...
uint32_t | ald_usb_lpm_remote_wake_is_enable (void)
Gets status of remote wakeup. More...
void | ald_usb_host_lpm_resume (void)
Initiate a RESUME from the L1 state in host mode. More...
void | ald_usb_dev_lpm_remote_wake (void)
Enable remote wakeup in device mode. More...
void | ald_usb_dev_lpm_config (uint32_t config)
Enable remote wakeup in device mode. More...
void | ald_usb_dev_lpm_enable (void)
Enable LPM in device mode. More...
void | ald_usb_dev_lpm_disable (void)
Disable LPM in device mode. More...
uint32_t | ald_usb_lpm_link_status_get (void)
Gets the link status. More...
uint32_t | ald_usb_lpm_ep_get (void)
Gets the index of the endpoint. More...
uint32_t | ald_usb_lpm_int_status_get (void)
Gets the status of the interrupt. More...
void | ald_usb_lpm_int_disable (uint32_t ints)
Disable the LPM interrupt. More...
void | ald_usb_lpm_int_enable (uint32_t ints)
Enable the LPM interrupt. More...

Detailed Description

USB module driver.

Version
V1.0
Date
25 Dec 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_usb.c.


ALD User Manual: D:/svn/src/ald_usb.h File Reference

  • D:
  • svn
  • src
Macros | Functions
ald_usb.h File Reference

Header file of USB module driver. More...

#include <stdbool.h>
#include "utils.h"
#include "ald_rmu.h"
Include dependency graph for ald_usb.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | USB_POWER_ISOUP 0x00000080U
#define | USB_POWER_SOFTCONN 0x00000040U
#define | USB_POWER_HS_EN 0x00000020U
#define | USB_POWER_HS_M 0x00000010U
#define | USB_POWER_RESET 0x00000008U
#define | USB_POWER_RESUME 0x00000004U
#define | USB_POWER_SUSPEND 0x00000002U
#define | USB_POWER_PWRDNPHY 0x00000001U
#define | USB_DEVCTL_DEV 0x00000080U
#define | USB_DEVCTL_FSDEV 0x00000040U
#define | USB_DEVCTL_LSDEV 0x00000020U
#define | USB_DEVCTL_VBUS_M 0x00000018U
#define | USB_DEVCTL_VBUS_NONE 0x00000000U
#define | USB_DEVCTL_VBUS_SEND 0x00000008U
#define | USB_DEVCTL_VBUS_AVALID 0x00000010U
#define | USB_DEVCTL_VBUS_VALID 0x00000018U
#define | USB_DEVCTL_HOST 0x00000004U
#define | USB_DEVCTL_HOSTREQ 0x00000002U
#define | USB_DEVCTL_SESSION 0x00000001U
#define | USB_RXCSRH1_AUTOCL 0x00000080U
#define | USB_RXCSRH1_AUTORQ 0x00000040U
#define | USB_RXCSRH1_ISO 0x00000040U
#define | USB_RXCSRH1_DMAEN 0x00000020U
#define | USB_RXCSRH1_DISNYET 0x00000010U
#define | USB_RXCSRH1_PIDERR 0x00000010U
#define | USB_RXCSRH1_DMAMOD 0x00000008U
#define | USB_RXCSRH1_DTWE 0x00000004U
#define | USB_RXCSRH1_DT 0x00000002U
#define | USB_RXCSRH1_INCOMPRX 0x00000001U
#define | USB_CSRH0_DISPING 0x00000008U
#define | USB_CSRH0_DTWE 0x00000004U
#define | USB_CSRH0_DT 0x00000002U
#define | USB_CSRH0_FLUSH 0x00000001U
#define | USB_TXCSRH1_AUTOSET 0x00000080U
#define | USB_TXCSRH1_ISO 0x00000040U
#define | USB_TXCSRH1_MODE 0x00000020U
#define | USB_TXCSRH1_DMAEN 0x00000010U
#define | USB_TXCSRH1_FDT 0x00000008U
#define | USB_TXCSRH1_DMAMOD 0x00000004U
#define | USB_TXCSRH1_DTWE 0x00000002U
#define | USB_TXCSRH1_DT 0x00000001U
#define | USB_TXCSRL1_NAKTO 0x00000080U
#define | USB_TXCSRL1_CLRDT 0x00000040U
#define | USB_TXCSRL1_STALLED 0x00000020U
#define | USB_TXCSRL1_STALL 0x00000010U
#define | USB_TXCSRL1_SETUP 0x00000010U
#define | USB_TXCSRL1_FLUSH 0x00000008U
#define | USB_TXCSRL1_ERROR 0x00000004U
#define | USB_TXCSRL1_UNDRN 0x00000004U
#define | USB_TXCSRL1_FIFONE 0x00000002U
#define | USB_TXCSRL1_TXRDY 0x00000001U
#define | USB_RXCSRL1_CLRDT 0x00000080U
#define | USB_RXCSRL1_STALLED 0x00000040U
#define | USB_RXCSRL1_STALL 0x00000020U
#define | USB_RXCSRL1_REQPKT 0x00000020U
#define | USB_RXCSRL1_FLUSH 0x00000010U
#define | USB_RXCSRL1_DATAERR 0x00000008U
#define | USB_RXCSRL1_NAKTO 0x00000008U
#define | USB_RXCSRL1_OVER 0x00000004U
#define | USB_RXCSRL1_ERROR 0x00000004U
#define | USB_RXCSRL1_FULL 0x00000002U
#define | USB_RXCSRL1_RXRDY 0x00000001U
#define | USB_CSRL0_NAKTO 0x00000080U
#define | USB_CSRL0_SETENDC 0x00000080U
#define | USB_CSRL0_STATUS 0x00000040U
#define | USB_CSRL0_RXRDYC 0x00000040U
#define | USB_CSRL0_REQPKT 0x00000020U
#define | USB_CSRL0_STALL 0x00000020U
#define | USB_CSRL0_SETEND 0x00000010U
#define | USB_CSRL0_ERROR 0x00000010U
#define | USB_CSRL0_DATAEND 0x00000008U
#define | USB_CSRL0_SETUP 0x00000008U
#define | USB_CSRL0_STALLED 0x00000004U
#define | USB_CSRL0_TXRDY 0x00000002U
#define | USB_CSRL0_RXRDY 0x00000001U
#define | USB_TYPE0_SPEED_M 0x000000C0U
#define | USB_TYPE0_SPEED_HIGH 0x00000040U
#define | USB_TYPE0_SPEED_FULL 0x00000080U
#define | USB_TYPE0_SPEED_LOW 0x000000C0U
#define | USB_TXTYPE1_SPEED_M 0x000000C0U
#define | USB_TXTYPE1_SPEED_DFLT 0x00000000U
#define | USB_TXTYPE1_SPEED_HIGH 0x00000040U
#define | USB_TXTYPE1_SPEED_FULL 0x00000080U
#define | USB_TXTYPE1_SPEED_LOW 0x000000C0U
#define | USB_TXTYPE1_PROTO_M 0x00000030U
#define | USB_TXTYPE1_PROTO_CTRL 0x00000000U
#define | USB_TXTYPE1_PROTO_ISOC 0x00000010U
#define | USB_TXTYPE1_PROTO_BULK 0x00000020U
#define | USB_TXTYPE1_PROTO_INT 0x00000030U
#define | USB_TXTYPE1_TEP_M 0x0000000FU
#define | USB_TXTYPE1_TEP_S 0U
#define | USB_LPMATTR_ENDPT_M 0x0000F000U
#define | USB_LPMATTR_RMTWAK 0x00000100U
#define | USB_LPMATTR_HIRD_M 0x000000F0U
#define | USB_LPMATTR_LS_M 0x0000000FU
#define | USB_LPMATTR_LS_L1 0x00000001U
#define | USB_LPMATTR_ENDPT_S 12U
#define | USB_LPMATTR_HIRD_S 4U
#define | USB_LPMCNTRL_LPMRES 0x00000002U
#define | USB_LPMCNTRL_LPMXMT 0x00000001U
#define | USB_LPMCNTRL_ENABLE 0x00000006U
#define | USB_LPMCNTRL_DISABLE 0x00000000U
#define | USB_INTCTRL_ALL 0x000003FFU
#define | USB_INTCTRL_STATUS 0x000000FFU
#define | USB_INTCTRL_VBUS_ERR 0x00000080U
#define | USB_INTCTRL_SESSION 0x00000040U
#define | USB_INTCTRL_SESSION_END 0x00000040U
#define | USB_INTCTRL_DISCONNECT 0x00000020U
#define | USB_INTCTRL_CONNECT 0x00000010U
#define | USB_INTCTRL_SOF 0x00000008U
#define | USB_INTCTRL_BABBLE 0x00000004U
#define | USB_INTCTRL_RESET 0x00000004U
#define | USB_INTCTRL_RESUME 0x00000002U
#define | USB_INTCTRL_SUSPEND 0x00000001U
#define | USB_INTCTRL_MODE_DETECT 0x00000200U
#define | USB_INTCTRL_POWER_FAULT 0x00000100U
#define | USB_INTEP_ALL 0xFFFFFFFFU
#define | USB_INTEP_HOST_IN 0xFFFE0000U
#define | USB_INTEP_HOST_IN_15 0x80000000U
#define | USB_INTEP_HOST_IN_14 0x40000000U
#define | USB_INTEP_HOST_IN_13 0x20000000U
#define | USB_INTEP_HOST_IN_12 0x10000000U
#define | USB_INTEP_HOST_IN_11 0x08000000U
#define | USB_INTEP_HOST_IN_10 0x04000000U
#define | USB_INTEP_HOST_IN_9 0x02000000U
#define | USB_INTEP_HOST_IN_8 0x01000000U
#define | USB_INTEP_HOST_IN_7 0x00800000U
#define | USB_INTEP_HOST_IN_6 0x00400000U
#define | USB_INTEP_HOST_IN_5 0x00200000U
#define | USB_INTEP_HOST_IN_4 0x00100000U
#define | USB_INTEP_HOST_IN_3 0x00080000U
#define | USB_INTEP_HOST_IN_2 0x00040000U
#define | USB_INTEP_HOST_IN_1 0x00020000U
#define | USB_INTEP_DEV_OUT 0xFFFE0000U
#define | USB_INTEP_DEV_OUT_15 0x80000000U
#define | USB_INTEP_DEV_OUT_14 0x40000000U
#define | USB_INTEP_DEV_OUT_13 0x20000000U
#define | USB_INTEP_DEV_OUT_12 0x10000000U
#define | USB_INTEP_DEV_OUT_11 0x08000000U
#define | USB_INTEP_DEV_OUT_10 0x04000000U
#define | USB_INTEP_DEV_OUT_9 0x02000000U
#define | USB_INTEP_DEV_OUT_8 0x01000000U
#define | USB_INTEP_DEV_OUT_7 0x00800000U
#define | USB_INTEP_DEV_OUT_6 0x00400000U
#define | USB_INTEP_DEV_OUT_5 0x00200000U
#define | USB_INTEP_DEV_OUT_4 0x00100000U
#define | USB_INTEP_DEV_OUT_3 0x00080000U
#define | USB_INTEP_DEV_OUT_2 0x00040000U
#define | USB_INTEP_DEV_OUT_1 0x00020000U
#define | USB_INTEP_HOST_OUT 0x0000FFFEU
#define | USB_INTEP_HOST_OUT_15 0x00008000U
#define | USB_INTEP_HOST_OUT_14 0x00004000U
#define | USB_INTEP_HOST_OUT_13 0x00002000U
#define | USB_INTEP_HOST_OUT_12 0x00001000U
#define | USB_INTEP_HOST_OUT_11 0x00000800U
#define | USB_INTEP_HOST_OUT_10 0x00000400U
#define | USB_INTEP_HOST_OUT_9 0x00000200U
#define | USB_INTEP_HOST_OUT_8 0x00000100U
#define | USB_INTEP_HOST_OUT_7 0x00000080U
#define | USB_INTEP_HOST_OUT_6 0x00000040U
#define | USB_INTEP_HOST_OUT_5 0x00000020U
#define | USB_INTEP_HOST_OUT_4 0x00000010U
#define | USB_INTEP_HOST_OUT_3 0x00000008U
#define | USB_INTEP_HOST_OUT_2 0x00000004U
#define | USB_INTEP_HOST_OUT_1 0x00000002U
#define | USB_INTEP_DEV_IN 0x0000FFFEU
#define | USB_INTEP_DEV_IN_15 0x00008000U
#define | USB_INTEP_DEV_IN_14 0x00004000U
#define | USB_INTEP_DEV_IN_13 0x00002000U
#define | USB_INTEP_DEV_IN_12 0x00001000U
#define | USB_INTEP_DEV_IN_11 0x00000800U
#define | USB_INTEP_DEV_IN_10 0x00000400U
#define | USB_INTEP_DEV_IN_9 0x00000200U
#define | USB_INTEP_DEV_IN_8 0x00000100U
#define | USB_INTEP_DEV_IN_7 0x00000080U
#define | USB_INTEP_DEV_IN_6 0x00000040U
#define | USB_INTEP_DEV_IN_5 0x00000020U
#define | USB_INTEP_DEV_IN_4 0x00000010U
#define | USB_INTEP_DEV_IN_3 0x00000008U
#define | USB_INTEP_DEV_IN_2 0x00000004U
#define | USB_INTEP_DEV_IN_1 0x00000002U
#define | USB_INTEP_0 0x00000001U
#define | USB_UNDEF_SPEED 0x80000000U
#define | USB_HIGH_SPEED 0x00000002U
#define | USB_FULL_SPEED 0x00000001U
#define | USB_LOW_SPEED 0x00000000U
#define | USB_HOST_IN_STATUS 0x114F0000U
#define | USB_HOST_IN_PID_ERROR 0x10000000U
#define | USB_HOST_IN_NOT_COMP 0x01000000U
#define | USB_HOST_IN_STALL 0x00400000U
#define | USB_HOST_IN_DATA_ERROR 0x00080000U
#define | USB_HOST_IN_NAK_TO 0x00080000U
#define | USB_HOST_IN_ERROR 0x00040000U
#define | USB_HOST_IN_FIFO_FULL 0x00020000U
#define | USB_HOST_IN_PKTRDY 0x00010000U
#define | USB_HOST_OUT_STATUS 0x000000A7U
#define | USB_HOST_OUT_NAK_TO 0x00000080U
#define | USB_HOST_OUT_NOT_COMP 0x00000080U
#define | USB_HOST_OUT_STALL 0x00000020U
#define | USB_HOST_OUT_ERROR 0x00000004U
#define | USB_HOST_OUT_FIFO_NE 0x00000002U
#define | USB_HOST_OUT_PKTPEND 0x00000001U
#define | USB_HOST_EP0_NAK_TO 0x00000080U
#define | USB_HOST_EP0_STATUS 0x00000040U
#define | USB_HOST_EP0_ERROR 0x00000010U
#define | USB_HOST_EP0_RX_STALL 0x00000004U
#define | USB_HOST_EP0_RXPKTRDY 0x00000001U
#define | USB_DEV_RX_PID_ERROR 0x01000000U
#define | USB_DEV_RX_SENT_STALL 0x00400000U
#define | USB_DEV_RX_DATA_ERROR 0x00080000U
#define | USB_DEV_RX_OVERRUN 0x00040000U
#define | USB_DEV_RX_FIFO_FULL 0x00020000U
#define | USB_DEV_RX_PKT_RDY 0x00010000U
#define | USB_DEV_TX_NOT_COMP 0x00000080U
#define | USB_DEV_TX_SENT_STALL 0x00000020U
#define | USB_DEV_TX_UNDERRUN 0x00000004U
#define | USB_DEV_TX_FIFO_NE 0x00000002U
#define | USB_DEV_TX_TXPKTRDY 0x00000001U
#define | USB_DEV_EP0_SETUP_END 0x00000010U
#define | USB_DEV_EP0_SENT_STALL 0x00000004U
#define | USB_DEV_EP0_IN_PKTPEND 0x00000002U
#define | USB_DEV_EP0_OUT_PKTRDY 0x00000001U
#define | USB_EP_AUTO_SET 0x00000001U
#define | USB_EP_AUTO_REQUEST 0x00000002U
#define | USB_EP_AUTO_CLEAR 0x00000004U
#define | USB_EP_DMA_MODE_0 0x00000008U
#define | USB_EP_DMA_MODE_1 0x00000010U
#define | USB_EP_DIS_NYET 0x00000020U
#define | USB_EP_MODE_ISOC 0x00000000U
#define | USB_EP_MODE_BULK 0x00000100U
#define | USB_EP_MODE_INT 0x00000200U
#define | USB_EP_MODE_CTRL 0x00000300U
#define | USB_EP_MODE_MASK 0x00000300U
#define | USB_EP_SPEED_LOW 0x00000000U
#define | USB_EP_SPEED_FULL 0x00001000U
#define | USB_EP_SPEED_HIGH 0x00004000U
#define | USB_EP_HOST_IN 0x00000000U
#define | USB_EP_HOST_OUT 0x00002000U
#define | USB_EP_DEV_IN 0x00002000U
#define | USB_EP_DEV_OUT 0x00000000U
#define | USB_HOST_PWRFLT_LOW 0x00000010U
#define | USB_HOST_PWRFLT_HIGH 0x00000030U
#define | USB_HOST_PWRFLT_EP_NONE 0x00000000U
#define | USB_HOST_PWRFLT_EP_TRI 0x00000140U
#define | USB_HOST_PWRFLT_EP_LOW 0x00000240U
#define | USB_HOST_PWRFLT_EP_HIGH 0x00000340U
#define | USB_HOST_PWREN_MAN_LOW 0x00000000U
#define | USB_HOST_PWREN_MAN_HIGH 0x00000001U
#define | USB_HOST_PWREN_AUTOLOW 0x00000002U
#define | USB_HOST_PWREN_AUTOHIGH 0x00000003U
#define | USB_HOST_PWREN_FILTER 0x00010000U
#define | USB_HOST_LPM_RMTWAKE 0x00000100U
#define | USB_HOST_LPM_L1 0x00000001U
#define | USB_DEV_LPM_NAK 0x00000010U
#define | USB_DEV_LPM_NONE 0x00000000U
#define | USB_DEV_LPM_EN 0x0000000cU
#define | USB_DEV_LPM_EXTONLY 0x00000004U
#define | USB_DEV_LPM_LS_RMTWAKE 0x00000100U
#define | USB_DEV_LPM_LS_L1 0x00000001U
#define | USB_INTLPM_ERROR 0x00000020U
#define | USB_INTLPM_RESUME 0x00000010U
#define | USB_INTLPM_INCOMPLETE 0x00000008U
#define | USB_INTLPM_ACK 0x00000004U
#define | USB_INTLPM_NYET 0x00000002U
#define | USB_INTLPM_STALL 0x00000001U
#define | MAX_NAK_LIMIT 31U
#define | DISABLE_NAK_LIMIT 0U
#define | MAX_PACKET_SIZE_EP0 64U
#define | USB_EP_0 0U
#define | USB_EP_1 1U
#define | USB_EP_2 2U
#define | USB_EP_3 3U
#define | USB_EP_4 4U
#define | USB_EP_5 5U
#define | NUM_USB_EP 6U
#define | IndexToUSBEP(x) ((x))
#define | USBEPToIndex(x) ((x))
#define | USB_FIFO_SZ_8 0x00000000U
#define | USB_FIFO_SZ_16 0x00000001U
#define | USB_FIFO_SZ_32 0x00000002U
#define | USB_FIFO_SZ_64 0x00000003U
#define | USB_FIFO_SZ_128 0x00000004U
#define | USB_FIFO_SZ_256 0x00000005U
#define | USB_FIFO_SZ_512 0x00000006U
#define | USB_FIFO_SZ_1024 0x00000007U
#define | USB_FIFO_SZ_2048 0x00000008U
#define | USBFIFOSizeToBytes(x) (8 << (x))
#define | USB_TRANS_OUT 0x00000102U
#define | USB_TRANS_IN 0x00000102U
#define | USB_TRANS_IN_LAST 0x0000010aU
#define | USB_TRANS_SETUP 0x0000110aU
#define | USB_TRANS_STATUS 0x00000142U
#define | USB_DUAL_MODE_HOST 0x00000001U
#define | USB_DUAL_MODE_DEVICE 0x00000081U
#define | USB_DUAL_MODE_NONE 0x00000080U
#define | USB_OTG_MODE_ASIDE_HOST 0x0000001dU
#define | USB_OTG_MODE_ASIDE_NPWR 0x00000001U
#define | USB_OTG_MODE_ASIDE_SESS 0x00000009U
#define | USB_OTG_MODE_ASIDE_AVAL 0x00000011U
#define | USB_OTG_MODE_ASIDE_DEV 0x00000019U
#define | USB_OTG_MODE_BSIDE_HOST 0x0000009dU
#define | USB_OTG_MODE_BSIDE_DEV 0x00000099U
#define | USB_OTG_MODE_BSIDE_NPWR 0x00000081U
#define | USB_OTG_MODE_NONE 0x00000080U
#define | USB_DMA_INT_CH8 0x00000080U
#define | USB_DMA_INT_CH7 0x00000040U
#define | USB_DMA_INT_CH6 0x00000020U
#define | USB_DMA_INT_CH5 0x00000010U
#define | USB_DMA_INT_CH4 0x00000008U
#define | USB_DMA_INT_CH3 0x00000004U
#define | USB_DMA_INT_CH2 0x00000002U
#define | USB_DMA_INT_CH1 0x00000001U
#define | USB_DMA_EP_CFG_TX 0x00000001U
#define | USB_DMA_EP_CFG_RX_DEV 0x00000002U
#define | USB_DMA_EP_CFG_RX_HOST 0x00000004U
#define | USB_DMA_EP_TX_MSK 0x94U
#define | USB_DMA_EP_RX_DEV_MSK 0xA8U
#define | USB_DMA_EP_RX_HOST_MSK 0xE8U
#define | USB_DMA_STATUS_ERROR 0x00000100U
#define | USB_MODE_HOST_VBUS 0x00000004U
#define | USB_MODE_HOST 0x00000002U
#define | USB_MODE_DEV_VBUS 0x00000005U
#define | USB_MODE_DEV 0x00000003U
#define | USB_MODE_OTG 0x00000000U
#define | USB_RX_EPSTATUS_SHIFT 16U
#define | USB_INTEP_RX_SHIFT 16U
#define | USB_DMA_CFG_START 0x00000001U
#define | USB_DMA_CFG_START_NO 0x00000000U
#define | USB_DMA_CFG_DIR_WR 0x00000000U
#define | USB_DMA_CFG_DIR_RD 0x00000002U
#define | USB_DMA_CFG_MODE_0 0x00000000U
#define | USB_DMA_CFG_MODE_1 0x00000004U
#define | USB_DMA_CFG_IE_DIS 0x00000000U
#define | USB_DMA_CFG_IE_EN 0x00000008U
#define | USB_DMA_CFG_EP_1 0x00000010U
#define | USB_DMA_CFG_EP_2 0x00000020U
#define | USB_DMA_CFG_EP_3 0x00000030U
#define | USB_DMA_CFG_EP_4 0x00000040U
#define | USB_DMA_CFG_EP_5 0x00000050U
#define | USB_DMA_CFG_BURST_NONE 0x00000000U
#define | USB_DMA_CFG_BURST_4 0x00000200U
#define | USB_DMA_CFG_BURST_8 0x00000400U
#define | USB_DMA_CFG_BURST_16 0x00000600U
#define | USB_DMA_CFG_MODE_MSK 0x00000004U
#define | USB_DMA_CFG_EP_POS 0x00000004U
#define | USB_DMA_CFG_EP_MSK 0x000000F0U
#define | USB_DMA_CH_ERR_MSK 0x100U

Functions

uint32_t | ald_usb_frame_number_get (void)
Gets the number of current frame. More...
void | ald_usb_otg_session_request (bool start)
Request the session. More...
uint32_t | ald_usb_mode_get (void)
Gets the mode. More...
void | ald_usb_high_speed_enable (bool enable)
Enable/Disable the high mode. More...
uint32_t | ald_usb_device_speed_get (void)
Gets the speed of the device. More...
uint32_t | ald_usb_num_ep_get (void)
Gets the number of the endpoint. More...
void | ald_usb_control_reset (void)
Reset USB Control. More...
void | ald_usb_clock_output (void)
Output USB clock via PA15, 60MHz/256=234.375KHz. More...
int | ald_usb_eye_diagram_start (uint8_t *buf, uint16_t len)
Starts eye diagram for high-speed host. More...
uint8_t | ald_usb_dev_get_addr (void)
Gets the address. More...
void | ald_usb_dev_set_addr (uint8_t addr)
Sets the address. More...
void | ald_usb_dev_connect (void)
Enable connection. More...
void | ald_usb_dev_disconnect (void)
Disable connection. More...
void | ald_usb_dev_ep_config (uint32_t ep_idx, uint32_t p_max, uint32_t flags)
Configure the endpoint in device mode. More...
void | ald_usb_dev_ep_get_config (uint32_t ep_idx, uint32_t *p_max, uint32_t *flags)
Gets the parameters of the endpoint. More...
void | ald_usb_dev_ep_data_ack (uint32_t ep_idx, bool last)
Acknowledge the data from the host. More...
void | ald_usb_dev_ep_stall (uint32_t ep_idx, uint32_t flags)
Stall the endpoint. More...
void | ald_usb_dev_ep_stall_clear (uint32_t ep_idx, uint32_t flags)
Cancel the stall status. More...
void | ald_usb_dev_ep_status_clear (uint32_t ep_idx, uint32_t flags)
Clear the status of the endpoint. More...
uint32_t | ald_usb_host_addr_get (uint32_t ep_idx, uint32_t flags)
Gets the device's address. More...
void | ald_usb_host_addr_set (uint32_t ep_idx, uint32_t addr, uint32_t flags)
Sets the device's address. More...
void | ald_usb_host_ep_config (uint32_t ep_idx, uint32_t p_max, uint32_t nak_val, uint32_t t_ep, uint32_t flags)
Configure the endpoint in host mode. More...
void | ald_usb_host_ep_data_ack (uint32_t ep_idx)
Acknowledge the data in host mode. More...
void | ald_usb_host_ep_data_toggle (uint32_t ep_idx, bool toggle, uint32_t flags)
Toggle the data in host mode. More...
void | ald_usb_host_ep_status_clear (uint32_t ep_idx, uint32_t flags)
Clear the status of endpoint in host mode. More...
uint32_t | ald_usb_host_hub_addr_get (uint32_t ep_idx, uint32_t flags)
Gets the HUB's address. More...
void | ald_usb_host_hub_addr_set (uint32_t ep_idx, uint32_t addr, uint32_t flags)
Sets the HUB's address. More...
void | ald_usb_host_pwr_disable (void)
Disable power. More...
void | ald_usb_host_pwr_enable (void)
Enable power. More...
void | ald_usb_host_pwr_config (uint32_t flags)
Configure power in host mode. More...
void | ald_usb_host_pwr_fault_disable (void)
Disable the fault parameters of the power. More...
void | ald_usb_host_pwr_fault_enable (void)
Enable the fault parameters of the power. More...
void | ald_usb_host_request_in (uint32_t ep_idx)
Request data IN(from device to host) More...
void | ald_usb_host_request_in_clear (uint32_t ep_idx)
Clear the status of request IN. More...
void | ald_usb_host_request_status (void)
Request data IN at endpoint 0. More...
void | ald_usb_host_reset (bool start)
Reset the USB's bus. More...
void | ald_usb_host_resume (bool start)
Resume the devices. More...
void | ald_usb_host_suspend (void)
Suspend the devices. More...
uint32_t | ald_usb_host_speed_get (void)
Gets the device's speed. More...
void | ald_usb_host_ep_speed_set (uint32_t ep_idx, uint32_t flags)
Sets the endpoint speed. More...
void | ald_usb_host_ep_ping (uint32_t ep_idx, bool enable)
Ping the endpoint. More...
uint32_t | ald_usb_ep_data_avail (uint32_t ep_idx)
Gets the size of the available data. More...
int32_t | ald_usb_ep_data_get (uint32_t ep_idx, uint8_t *data, uint32_t *size)
Gets the data from FIFO. More...
int32_t | ald_usb_ep_data_put (uint32_t ep_idx, uint8_t *data, uint32_t size)
Puts data to the FIFO. More...
int32_t | ald_usb_ep_data_send (uint32_t ep_idx, uint32_t tx_type)
Send data. More...
void | ald_usb_ep_data_toggle_clear (uint32_t ep_idx, uint32_t flags)
Clear the status of the toggle. More...
void | ald_usb_ep_req_packet_count (uint32_t ep_idx, uint32_t count)
Sets the size of request data IN. More...
uint32_t | ald_usb_ep_status (uint32_t ep_idx)
Gets the status of the endpoint. More...
void | ald_usb_ep_dma_config (uint32_t ep_idx, uint32_t flag, type_func_t en)
Configure the endpoint in DMA mode. More...
uint32_t | ald_usb_fifo_addr_get (uint32_t ep_idx)
Gets the address of the FIFO. More...
void | ald_usb_fifo_config_get (uint32_t ep_idx, uint32_t *addr, uint32_t *size, uint32_t flags)
Gets the parameters of the FIFO. More...
void | ald_usb_fifo_config_set (uint32_t ep_idx, uint32_t addr, uint32_t size, uint32_t flags)
Sets the parameters of the FIFO. More...
void | ald_usb_fifo_flush (uint32_t ep_idx, uint32_t flags)
Flush the FIFO. More...
void | ald_usb_int_disable (uint32_t flags)
Disable interrupt. More...
void | ald_usb_int_enable (uint32_t flags)
Enable interrupt. More...
uint32_t | ald_usb_int_status_get (void)
Gets the status of the interrupt. More...
void | ald_usb_int_disable_ep (uint32_t flags)
Disable interrupt of the endpoint. More...
void | ald_usb_int_enable_ep (uint32_t flags)
Enable interrupt of the endpoint. More...
uint32_t | ald_usb_int_status_ep_get (void)
Gets the ststus of the endpoint interrupt. More...
void | ald_usb_int_register (void)
Register USB's interrupt. More...
void | ald_usb_int_unregister (void)
Unregister USB's interrupt. More...
uint32_t | ald_usb_int_num_get (void)
Get USB's interrupt number. More...
void | ald_usb_dma_channel_config (uint8_t ch, uint32_t addr, uint32_t count, uint32_t ctrl)
Configure DMA's channel. More...
void | ald_usb_dma_mult_recv_start (uint32_t ep_idx)
Start multiple receive. More...
void | ald_usb_dma_channel_start (uint8_t ch)
Start DMA's machine. More...
void | ald_usb_dma_channel_stop (uint8_t ch)
Stop DMA's machine. More...
uint32_t | ald_usb_dma_get_interrupt_flag (void)
Gets flags of the interrupt. More...
uint32_t | ald_usb_dma_get_channel_error (uint8_t ch)
Gets the status of the error. More...
void | ald_usb_dma_clear_channel_error (uint8_t ch)
Clear the status of the error. More...
void | ald_usb_host_lpm_send (uint32_t addr, uint32_t ep_idx)
Transmit a LPM transaction in host mode. More...
void | ald_usb_host_lpm_config (uint32_t resume_time, uint32_t config)
Configure the LPM parameters in host mode. More...
uint32_t | ald_usb_lpm_remote_wake_is_enable (void)
Gets status of remote wakeup. More...
void | ald_usb_host_lpm_resume (void)
Initiate a RESUME from the L1 state in host mode. More...
void | ald_usb_dev_lpm_remote_wake (void)
Enable remote wakeup in device mode. More...
void | ald_usb_dev_lpm_config (uint32_t config)
Enable remote wakeup in device mode. More...
void | ald_usb_dev_lpm_enable (void)
Enable LPM in device mode. More...
void | ald_usb_dev_lpm_disable (void)
Disable LPM in device mode. More...
uint32_t | ald_usb_lpm_link_status_get (void)
Gets the link status. More...
uint32_t | ald_usb_lpm_ep_get (void)
Gets the index of the endpoint. More...
uint32_t | ald_usb_lpm_int_status_get (void)
Gets the status of the interrupt. More...
void | ald_usb_lpm_int_disable (uint32_t ints)
Disable the LPM interrupt. More...
void | ald_usb_lpm_int_enable (uint32_t ints)
Enable the LPM interrupt. More...

Detailed Description

Header file of USB module driver.

Version
V1.0
Date
25 Dec 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_usb.h.


ALD User Manual: D:/svn/src/ald_wdt.c File Reference

  • D:
  • svn
  • src
Functions
ald_wdt.c File Reference

WDT module driver. More...

#include "ald_conf.h"
#include "ald_wdt.h"
Include dependency graph for ald_wdt.c:

Go to the source code of this file.

Functions

void | ald_wwdt_init (uint32_t load, wwdt_win_t win, type_func_t interrupt)
Initializes the WWDT according to the specified parameters. More...
void | ald_wwdt_start (void)
Start the WWDT. More...
uint32_t | ald_wwdt_get_value (void)
Get the free-running downcounter value. More...
it_status_t | ald_wwdt_get_flag_status (void)
Get interrupt state. More...
void | ald_wwdt_clear_flag_status (void)
Clear interrupt state. More...
void | ald_wwdt_feed_dog (void)
Refreshes the WWDT. More...
void | ald_iwdt_init (uint32_t load, type_func_t interrupt)
Initializes the IWDG according to the specified parameters. More...
void | ald_iwdt_start (void)
Start the IWDT. More...
uint32_t | ald_iwdt_get_value (void)
Get the free-running downcounter value. More...
it_status_t | ald_iwdt_get_flag_status (void)
Get interrupt state. More...
void | ald_iwdt_clear_flag_status (void)
Clear interrupt state. More...
void | ald_iwdt_feed_dog (void)
Refreshes the WWDT. More...

Detailed Description

WDT module driver.

Version
V1.0
Date
18 Dec 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_wdt.c.


ALD User Manual: D:/svn/src/ald_wdt.h File Reference

  • D:
  • svn
  • src
Macros | Enumerations | Functions
ald_wdt.h File Reference

Header file of WDT module driver. More...

#include "utils.h"
Include dependency graph for ald_wdt.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551U);}
#define | WWDT_LOCK() {WRITE_REG(WWDT->LOCK, 0xFFFFFFFFU);}
#define | IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551U);}
#define | IWDT_LOCK() {WRITE_REG(IWDT->LOCK, 0xFFFFFFFFU);}
#define | IS_WWDT_WIN_TYPE(x)
#define | IS_FUNC_STATE(x)

Enumerations

enum wwdt_win_t { WWDT_WIN_25 = 0x0U, WWDT_WIN_50 = 0x1U, WWDT_WIN_75 = 0x2U, WWDT_WIN_00 = 0x3U }
Wwdt no dog window. More...

Functions

void | ald_wwdt_init (uint32_t load, wwdt_win_t win, type_func_t interrupt)
Initializes the WWDT according to the specified parameters. More...
void | ald_wwdt_start (void)
Start the WWDT. More...
uint32_t | ald_wwdt_get_value (void)
Get the free-running downcounter value. More...
it_status_t | ald_wwdt_get_flag_status (void)
Get interrupt state. More...
void | ald_wwdt_clear_flag_status (void)
Clear interrupt state. More...
void | ald_wwdt_feed_dog (void)
Refreshes the WWDT. More...
void | ald_iwdt_init (uint32_t load, type_func_t interrupt)
Initializes the IWDG according to the specified parameters. More...
void | ald_iwdt_start (void)
Start the IWDT. More...
uint32_t | ald_iwdt_get_value (void)
Get the free-running downcounter value. More...
it_status_t | ald_iwdt_get_flag_status (void)
Get interrupt state. More...
void | ald_iwdt_clear_flag_status (void)
Clear interrupt state. More...
void | ald_iwdt_feed_dog (void)
Refreshes the WWDT. More...

Detailed Description

Header file of WDT module driver.

Version
V1.0
Date
18 Dec 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file ald_wdt.h.


ALD User Manual: D:/svn/src/type.h File Reference

  • D:
  • svn
  • src
Macros | Typedefs | Enumerations | Functions
type.h File Reference

define type More...

#include <stdint.h>
Include dependency graph for type.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | __INLINE__ inline
#define | __STATIC_INLINE__ static inline
#define | __isr__
#define | IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE))
#define | IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK))
#define | BIT(x) ((1U << (x)))
#define | BITS(s, e) ((0xffffffffU << (s)) & (0xffffffffU >> (31 - (e))))
#define | SET_BIT(reg, bit) ((reg) |= (bit))
#define | CLEAR_BIT(reg, bit) ((reg) &= ~(bit))
#define | READ_BIT(reg, bit) ((reg) & (bit))
#define | READ_BITS(reg, msk, s) (((reg) & (msk)) >> (s))
#define | CLEAR_REG(reg) ((reg) = (0x0))
#define | WRITE_REG(reg, val) ((reg) = (val))
#define | READ_REG(reg) ((reg))
#define | MODIFY_REG(reg, clearmask, setmask) WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask)))
#define | UNUSED(x) ((void)(x))
#define | assert_param(x)
#define | PER_MEM_BASE ((uint32_t) 0x40000000UL) /* PER base address */
#define | RAM_MEM_BASE ((uint32_t) 0x20000000UL) /* RAM base address */
#define | BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /* Peripheral Address Space bit-band area */
#define | BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /* SRAM Address Space bit-band area */

Typedefs

typedef enum flag_status_t it_status_t

Enumerations

enum | flag_status_t { RESET = 0x0U, SET = 0x1U }
enum | bit_status_t { BIT_RESET = 0x0U, BIT_SET = 0x1U }
enum | type_func_t { DISABLE = 0x0U, ENABLE = 0x1U }
enum | type_bool_t { FALSE = 0x0U, TRUE = 0x1U }
enum | lock_state_t { UNLOCK = 0x0U, LOCK = 0x1U }

Functions

__STATIC_INLINE__ void | BITBAND_PER (volatile uint32_t *addr, uint32_t bit, uint32_t val)
__STATIC_INLINE__ void | BITBAND_SRAM (uint32_t *addr, uint32_t bit, uint32_t val)

Detailed Description

define type

Version
V1.0
Date
17 Apr 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file type.h.

Macro Definition Documentation

◆ __INLINE__

#define __INLINE__ inline

Definition at line 31 of file type.h.

◆ __isr__

#define __isr__

Definition at line 35 of file type.h.

◆ __STATIC_INLINE__

#define __STATIC_INLINE__ static inline

Definition at line 32 of file type.h.

◆ assert_param

#define assert_param ( x )

Definition at line 88 of file type.h.

◆ BIT

#define BIT ( x ) ((1U << (x)))

Definition at line 65 of file type.h.

◆ BITBAND_PER_BASE

#define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /* Peripheral Address Space bit-band area */

Definition at line 94 of file type.h.

◆ BITBAND_RAM_BASE

#define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /* SRAM Address Space bit-band area */

Definition at line 95 of file type.h.

◆ BITS

#define BITS | ( | s,
 |  | e
 | ) | ((0xffffffffU << (s)) & (0xffffffffU >> (31 - (e))))

Definition at line 66 of file type.h.

◆ CLEAR_BIT

#define CLEAR_BIT | ( | reg,
 |  | bit
 | ) | ((reg) &= ~(bit))

Definition at line 68 of file type.h.

◆ CLEAR_REG

#define CLEAR_REG ( reg ) ((reg) = (0x0))

Definition at line 71 of file type.h.

◆ IS_FUNC_STATE

#define IS_FUNC_STATE ( x ) (((x) == DISABLE) || ((x) == ENABLE))

Definition at line 51 of file type.h.

◆ IS_LOCK_STATE

#define IS_LOCK_STATE ( x ) (((x) == UNLOCK) || ((x) == LOCK))

Definition at line 62 of file type.h.

◆ MODIFY_REG

#define MODIFY_REG | ( | reg,
 |  | clearmask,
 |  | setmask
 | ) | WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask)))

Definition at line 74 of file type.h.

◆ PER_MEM_BASE

#define PER_MEM_BASE ((uint32_t) 0x40000000UL) /* PER base address */

Definition at line 92 of file type.h.

◆ RAM_MEM_BASE

#define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /* RAM base address */

Definition at line 93 of file type.h.

◆ READ_BIT

#define READ_BIT | ( | reg,
 |  | bit
 | ) | ((reg) & (bit))

Definition at line 69 of file type.h.

◆ READ_BITS

#define READ_BITS | ( | reg,
 |  | msk,
 |  | s
 | ) | (((reg) & (msk)) >> (s))

Definition at line 70 of file type.h.

◆ READ_REG

#define READ_REG ( reg ) ((reg))

Definition at line 73 of file type.h.

◆ SET_BIT

#define SET_BIT | ( | reg,
 |  | bit
 | ) | ((reg) |= (bit))

Definition at line 67 of file type.h.

◆ UNUSED

#define UNUSED ( x ) ((void)(x))

Definition at line 76 of file type.h.

◆ WRITE_REG

#define WRITE_REG | ( | reg,
 |  | val
 | ) | ((reg) = (val))

Definition at line 72 of file type.h.

Typedef Documentation

◆ it_status_t

typedef enum flag_status_t it_status_t

Enumeration Type Documentation

◆ bit_status_t

enum bit_status_t
Enumerator
BIT_RESET
BIT_SET

Definition at line 42 of file type.h.

42 {
43 BIT_RESET = 0x0U,
44 BIT_SET = 0x1U,
45 } bit_status_t;
BIT_RESET
Definition: type.h:43
bit_status_t
bit_status_t
Definition: type.h:42
BIT_SET
Definition: type.h:44

◆ flag_status_t

enum flag_status_t
Enumerator
RESET
SET

Definition at line 37 of file type.h.

37 {
38 RESET = 0x0U,
39 SET = 0x1U,
40 } flag_status_t, it_status_t;
SET
Definition: type.h:39
RESET
Definition: type.h:38
it_status_t
enum flag_status_t it_status_t
flag_status_t
flag_status_t
Definition: type.h:37

◆ lock_state_t

enum lock_state_t
Enumerator
UNLOCK
LOCK

Definition at line 58 of file type.h.

58 {
59 UNLOCK = 0x0U,
60 LOCK = 0x1U,
61 } lock_state_t;
LOCK
Definition: type.h:60
UNLOCK
Definition: type.h:59
lock_state_t
lock_state_t
Definition: type.h:58

◆ type_bool_t

enum type_bool_t
Enumerator
FALSE
TRUE

Definition at line 53 of file type.h.

53 {
54 FALSE = 0x0U,
55 TRUE = 0x1U,
56 } type_bool_t;
FALSE
Definition: type.h:54
type_bool_t
type_bool_t
Definition: type.h:53
TRUE
Definition: type.h:55

◆ type_func_t

enum type_func_t
Enumerator
DISABLE
ENABLE

Definition at line 47 of file type.h.

47 {
48 DISABLE = 0x0U,
49 ENABLE = 0x1U,
50 } type_func_t;
ENABLE
Definition: type.h:49
type_func_t
type_func_t
Definition: type.h:47
DISABLE
Definition: type.h:48

Function Documentation

◆ BITBAND_PER()

__STATIC_INLINE__ void BITBAND_PER | ( | volatile uint32_t * | addr,
 |  | uint32_t | bit,
 |  | uint32_t | val
 | ) |  |

Definition at line 97 of file type.h.

98 {
99 uint32_t tmp = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) << 5) + (bit << 2);
100 *((volatile uint32_t *)tmp) = (uint32_t)val;
101 }
PER_MEM_BASE
#define PER_MEM_BASE
Definition: type.h:92
BITBAND_PER_BASE
#define BITBAND_PER_BASE
Definition: type.h:94

◆ BITBAND_SRAM()

__STATIC_INLINE__ void BITBAND_SRAM | ( | uint32_t * | addr,
 |  | uint32_t | bit,
 |  | uint32_t | val
 | ) |  |

Definition at line 103 of file type.h.

104 {
105 uint32_t tmp = BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) << 5) + (bit << 2);
106 *((volatile uint32_t *)tmp) = (uint32_t)val;
107 }
BITBAND_RAM_BASE
#define BITBAND_RAM_BASE
Definition: type.h:95
RAM_MEM_BASE
#define RAM_MEM_BASE
Definition: type.h:93


ALD User Manual: D:/svn/src/utils.c File Reference

  • D:
  • svn
  • src
Macros | Functions | Variables
utils.c File Reference

This file contains the Utilities functions/types for the driver. More...

#include <string.h>
#include "utils.h"
#include "ald_dma.h"
#include "ald_cmu.h"
Include dependency graph for utils.c:

Go to the source code of this file.

Macros

#define | __ALD_VERSION_MAIN (0x01)
ALD version number. More...
#define | __ALD_VERSION_SUB1 (0x00)
#define | __ALD_VERSION_SUB2 (0x00)
#define | __ALD_VERSION_RC (0x00)
#define | __ALD_VERSION

Functions

void | ald_cmu_init (void)
This function Configures time base source, NVIC and DMA. More...
__weak void | ald_tick_init (uint32_t prio)
This function configures the source of the time base. The time source is configured to have 1ms time base with a dedicated Tick interrupt priority. More...
void | ald_systick_interval_select (systick_interval_t value)
Selects the interval of systick interrupt. More...
__weak void | ald_systick_irq_cbk (void)
This function invoked by Systick ISR. More...
__weak void | ald_inc_tick (void)
This function is called to increment a global variable "lib_tick" used as application time base. More...
__weak uint32_t | ald_get_tick (void)
Provides a tick value in millisecond. More...
__weak void | ald_delay_ms (__IO uint32_t delay)
This function provides accurate delay (in milliseconds) based on variable incremented. More...
__weak void | ald_suspend_tick (void)
Suspend Tick increment. More...
__weak void | ald_resume_tick (void)
Resume Tick increment. More...
uint32_t | ald_get_ald_version (void)
This method returns the ALD revision. More...
void | ald_flash_wait_config (uint8_t cycle)
Configure the flash wait period. More...
ald_status_t | ald_wait_flag (uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout)
Waiting the specified bit in the register change to SET/RESET. More...
void | ald_mcu_irq_config (IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, type_func_t status)
Configure interrupt. More...
void | ald_mcu_timestamp_init (void)
Initialize core timestamp. More...
uint32_t | ald_mcu_get_timestamp (void)
Get core timestamp. More...
uint32_t | ald_mcu_get_cpu_id (void)
Get the CPU ID. More...
void | ald_mcu_get_uid (uint8_t *buf)
Get the UID. More...
uint32_t | ald_mcu_get_chipid (void)
Get the CHIPID. More...

Variables

static __IO uint32_t | lib_tick
lib_tick: Increase by one millisecond More...
uint32_t | __systick_interval = SYSTICK_INTERVAL_1MS
SysTick interval. More...

Detailed Description

This file contains the Utilities functions/types for the driver.

Version
V1.0
Date
07 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file utils.c.


ALD User Manual: D:/svn/src/utils.h File Reference

  • D:
  • svn
  • src
Macros | Enumerations | Functions | Variables
utils.h File Reference

This file contains the Utilities functions/types for the driver. More...

#include <stdlib.h>
#include "ald_conf.h"
#include "type.h"
Include dependency graph for utils.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Macros

#define | ALD_MAX_DELAY 0xFFFFFFFFU
#define | IS_BIT_SET(reg, bit) (((reg) & (bit)) != RESET)
#define | IS_BIT_CLR(reg, bit) (((reg) & (bit)) == RESET)
#define | RESET_HANDLE_STATE(x) ((x)->state = 0)
#define | __LOCK(x)
#define | __UNLOCK(x)
#define | ALD_PANIC()
#define | MCU_UID0_ADDR 0x000803E0U
#define | MCU_UID1_ADDR 0x000803E8U
#define | MCU_UID2_ADDR 0x000803F0U
#define | MCU_CHIPID_ADDR 0x000803F8U
#define | DWT_CR *(uint32_t *)0xE0001000U
#define | DWT_CYCCNT *(volatile uint32_t *)0xE0001004U
#define | DEM_CR *(uint32_t *)0xE000EDFCU
#define | DEM_CR_TRCENA (1U << 24)
#define | DWT_CR_CYCCNTEA (1U << 0)
#define | IS_PREEMPT_PRIO(x) ((x) < 16)
#define | IS_SUB_PRIO(x) ((x) < 16)
#define | IS_SYSTICK_INTERVAL(x)

Enumerations

enum | ald_status_t { OK = 0x0U, ERROR = 0x1U, BUSY = 0x2U, TIMEOUT = 0x3U }
ALD Status structures definition. More...
enum nvic_priority_group_t {
NVIC_PRIORITY_GROUP_0 = 0x7U, NVIC_PRIORITY_GROUP_1 = 0x6U, NVIC_PRIORITY_GROUP_2 = 0x5U, NVIC_PRIORITY_GROUP_3 = 0x4U,
NVIC_PRIORITY_GROUP_4 = 0x3U
}
NVIC Preemption Priority Group. More...
enum | systick_interval_t { SYSTICK_INTERVAL_1MS = 1000U, SYSTICK_INTERVAL_10MS = 100U, SYSTICK_INTERVAL_100MS = 10U, SYSTICK_INTERVAL_1000MS = 1U }
SysTick interval definition. More...

Functions

void | ald_cmu_init (void)
This function Configures time base source, NVIC and DMA. More...
__weak void | ald_tick_init (uint32_t prio)
This function configures the source of the time base. The time source is configured to have 1ms time base with a dedicated Tick interrupt priority. More...
void | ald_systick_interval_select (systick_interval_t value)
Selects the interval of systick interrupt. More...
__weak void | ald_inc_tick (void)
This function is called to increment a global variable "lib_tick" used as application time base. More...
__weak void | ald_systick_irq_cbk (void)
This function invoked by Systick ISR. More...
__weak void | ald_delay_ms (__IO uint32_t delay)
This function provides accurate delay (in milliseconds) based on variable incremented. More...
__weak uint32_t | ald_get_tick (void)
Provides a tick value in millisecond. More...
__weak void | ald_suspend_tick (void)
Suspend Tick increment. More...
__weak void | ald_resume_tick (void)
Resume Tick increment. More...
uint32_t | ald_get_ald_version (void)
This method returns the ALD revision. More...
void | ald_flash_wait_config (uint8_t cycle)
Configure the flash wait period. More...
ald_status_t | ald_wait_flag (uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout)
Waiting the specified bit in the register change to SET/RESET. More...
void | ald_mcu_irq_config (IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, type_func_t status)
Configure interrupt. More...
void | ald_mcu_timestamp_init (void)
Initialize core timestamp. More...
uint32_t | ald_mcu_get_timestamp (void)
Get core timestamp. More...
uint32_t | ald_mcu_get_cpu_id (void)
Get the CPU ID. More...
void | ald_mcu_get_uid (uint8_t *buf)
Get the UID. More...
uint32_t | ald_mcu_get_chipid (void)
Get the CHIPID. More...

Variables

uint32_t __systick_interval
SysTick interval. More...

Detailed Description

This file contains the Utilities functions/types for the driver.

Version
V1.0
Date
07 Nov 2019
Author
AE Team
Note

Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.

Definition in file utils.h.


ALD User Manual: Globals

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- _ -

  • __ALD_VERSION : utils.c
  • __ALD_VERSION_MAIN : utils.c
  • __ALD_VERSION_RC : utils.c
  • __ALD_VERSION_SUB1 : utils.c
  • __ALD_VERSION_SUB2 : utils.c
  • __attribute__() : ald_dma.c
  • __can_recv_by_it() : ald_can.c
  • __can_rx_check() : ald_can.c
  • __can_send_by_it() : ald_can.c
  • __i2s_recv_by_it() : ald_i2s.c
  • __i2s_send_by_it() : ald_i2s.c
  • __i2s_tx_recv_by_it() : ald_i2s.c
  • __INLINE__ : type.h
  • __isr__ : type.h
  • __LOCK : utils.h
  • __RAMFUNC : ald_flash.c
  • __spi_recv_by_it() : ald_spi.c
  • __spi_send_by_it() : ald_spi.c
  • __spi_send_recv_by_it() : ald_spi.c
  • __STATIC_INLINE__ : type.h
  • __system_clock : ald_cmu.c
  • __systick_interval : utils.h , utils.c
  • __tsense_cbk : ald_tsense.c
  • __uart_end_send_by_it() : ald_uart.c
  • __uart_recv_by_it() : ald_uart.c
  • __uart_send_by_it() : ald_uart.c
  • __UNLOCK : utils.h


ALD User Manual: Globals

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- a -

  • ACMP_128_PCLK : ald_acmp.h
  • ACMP_16_PCLK : ald_acmp.h
  • ACMP_256_PCLK : ald_acmp.h
  • ACMP_32_PCLK : ald_acmp.h
  • ACMP_4_PCLK : ald_acmp.h
  • ACMP_512_PCLK : ald_acmp.h
  • ACMP_64_PCLK : ald_acmp.h
  • ACMP_8_PCLK : ald_acmp.h
  • ACMP_DISABLE : ald_acmp.h
  • ACMP_EDGE_ALL : ald_acmp.h
  • ACMP_EDGE_FALL : ald_acmp.h
  • ACMP_EDGE_NONE : ald_acmp.h
  • ACMP_EDGE_RISE : ald_acmp.h
  • acmp_edge_t : ald_acmp.h
  • ACMP_ENABLE : ald_acmp.h
  • ACMP_FLAG_EDGE : ald_acmp.h
  • acmp_flag_t : ald_acmp.h
  • ACMP_FLAG_WARMUP : ald_acmp.h
  • acmp_handle_t : ald_acmp.h
  • ACMP_HIGH_POWER : ald_acmp.h
  • ACMP_HYST_0 : ald_acmp.h
  • ACMP_HYST_15 : ald_acmp.h
  • ACMP_HYST_22 : ald_acmp.h
  • ACMP_HYST_29 : ald_acmp.h
  • ACMP_HYST_36 : ald_acmp.h
  • ACMP_HYST_43 : ald_acmp.h
  • ACMP_HYST_50 : ald_acmp.h
  • ACMP_HYST_57 : ald_acmp.h
  • acmp_hystsel_t : ald_acmp.h
  • ACMP_INACTVAL_HIGH : ald_acmp.h
  • ACMP_INACTVAL_LOW : ald_acmp.h
  • acmp_inactval_t : ald_acmp.h
  • ACMP_IT_EDGE : ald_acmp.h
  • acmp_it_t : ald_acmp.h
  • ACMP_IT_WARMUP : ald_acmp.h
  • ACMP_LOW_POWER : ald_acmp.h
  • ACMP_MIDDLE_POWER : ald_acmp.h
  • acmp_mode_t : ald_acmp.h
  • ACMP_NEG_1V25 : ald_acmp.h
  • ACMP_NEG_2V5 : ald_acmp.h
  • ACMP_NEG_CH0 : ald_acmp.h
  • ACMP_NEG_CH1 : ald_acmp.h
  • ACMP_NEG_CH2 : ald_acmp.h
  • ACMP_NEG_CH3 : ald_acmp.h
  • ACMP_NEG_CH4 : ald_acmp.h
  • ACMP_NEG_CH5 : ald_acmp.h
  • ACMP_NEG_CH6 : ald_acmp.h
  • ACMP_NEG_CH7 : ald_acmp.h
  • acmp_neg_input_t : ald_acmp.h
  • ACMP_NEG_VDD : ald_acmp.h
  • ACMP_OUT_DISABLE : ald_acmp.h
  • ACMP_OUT_ENABLE : ald_acmp.h
  • acmp_out_func_t : ald_acmp.h
  • ACMP_POS_CH0 : ald_acmp.h
  • ACMP_POS_CH1 : ald_acmp.h
  • ACMP_POS_CH2 : ald_acmp.h
  • ACMP_POS_CH3 : ald_acmp.h
  • ACMP_POS_CH4 : ald_acmp.h
  • ACMP_POS_CH5 : ald_acmp.h
  • ACMP_POS_CH6 : ald_acmp.h
  • ACMP_POS_CH7 : ald_acmp.h
  • acmp_pos_input_t : ald_acmp.h
  • ACMP_STATUS_ACT : ald_acmp.h
  • ACMP_STATUS_OUT : ald_acmp.h
  • acmp_status_t : ald_acmp.h
  • ACMP_ULTRA_LOW_POWER : ald_acmp.h
  • acmp_warm_time_t : ald_acmp.h
  • adc_align_t : ald_adc.h
  • ADC_ALL_DISABLE : ald_adc.h
  • adc_ana_wdg_t : ald_adc.h
  • ADC_ANAWTD_ALL_IST : ald_adc.h
  • ADC_ANAWTD_ALL_NM : ald_adc.h
  • ADC_ANAWTD_ALL_NMIST : ald_adc.h
  • ADC_ANAWTD_NONE : ald_adc.h
  • ADC_ANAWTD_SING_IST : ald_adc.h
  • ADC_ANAWTD_SING_NM : ald_adc.h
  • ADC_ANAWTD_SING_NMIST : ald_adc.h
  • ADC_AWD_EVENT : ald_adc.h
  • ADC_CALIBRATE_DISABLE : ald_adc.h
  • ADC_CALIBRATE_ENABLE : ald_adc.h
  • ADC_CHANNEL_0 : ald_adc.h
  • ADC_CHANNEL_1 : ald_adc.h
  • ADC_CHANNEL_10 : ald_adc.h
  • ADC_CHANNEL_11 : ald_adc.h
  • ADC_CHANNEL_12 : ald_adc.h
  • ADC_CHANNEL_13 : ald_adc.h
  • ADC_CHANNEL_14 : ald_adc.h
  • ADC_CHANNEL_15 : ald_adc.h
  • ADC_CHANNEL_16 : ald_adc.h
  • ADC_CHANNEL_17 : ald_adc.h
  • ADC_CHANNEL_18 : ald_adc.h
  • ADC_CHANNEL_2 : ald_adc.h
  • ADC_CHANNEL_3 : ald_adc.h
  • ADC_CHANNEL_4 : ald_adc.h
  • ADC_CHANNEL_5 : ald_adc.h
  • ADC_CHANNEL_6 : ald_adc.h
  • ADC_CHANNEL_7 : ald_adc.h
  • ADC_CHANNEL_8 : ald_adc.h
  • ADC_CHANNEL_9 : ald_adc.h
  • adc_channel_t : ald_adc.h
  • ADC_CKDIV_1 : ald_adc.h
  • ADC_CKDIV_128 : ald_adc.h
  • ADC_CKDIV_16 : ald_adc.h
  • ADC_CKDIV_2 : ald_adc.h
  • ADC_CKDIV_32 : ald_adc.h
  • ADC_CKDIV_4 : ald_adc.h
  • ADC_CKDIV_64 : ald_adc.h
  • ADC_CKDIV_8 : ald_adc.h
  • adc_clk_div_t : ald_adc.h
  • ADC_CONV_BIT_10 : ald_adc.h
  • ADC_CONV_BIT_12 : ald_adc.h
  • ADC_CONV_BIT_6 : ald_adc.h
  • ADC_CONV_BIT_8 : ald_adc.h
  • adc_conv_bit_t : ald_adc.h
  • ADC_DATAALIGN_LEFT : ald_adc.h
  • ADC_DATAALIGN_RIGHT : ald_adc.h
  • ADC_DISABLE : ald_adc.h
  • adc_disc_mode_t : ald_adc.h
  • ADC_DISC_NR_1 : ald_adc.h
  • ADC_DISC_NR_2 : ald_adc.h
  • ADC_DISC_NR_3 : ald_adc.h
  • ADC_DISC_NR_4 : ald_adc.h
  • ADC_DISC_NR_5 : ald_adc.h
  • ADC_DISC_NR_6 : ald_adc.h
  • ADC_DISC_NR_7 : ald_adc.h
  • ADC_DISC_NR_8 : ald_adc.h
  • adc_disc_nr_t : ald_adc.h
  • adc_dma_error() : ald_adc.c
  • adc_dma_normal_conv_cplt() : ald_adc.c
  • adc_dma_timer_trigger_cplt() : ald_adc.c
  • ADC_ENABLE : ald_adc.h
  • ADC_ERROR_DMA : ald_adc.h
  • ADC_ERROR_INTERNAL : ald_adc.h
  • ADC_ERROR_NONE : ald_adc.h
  • ADC_ERROR_OVR : ald_adc.h
  • adc_error_t : ald_adc.h
  • ADC_ETS_DISABLE : ald_adc.h
  • ADC_ETS_FALL : ald_adc.h
  • ADC_ETS_RISE : ald_adc.h
  • ADC_ETS_RISE_FALL : ald_adc.h
  • adc_ets_t : ald_adc.h
  • adc_event_type_t : ald_adc.h
  • ADC_FLAG_AWD : ald_adc.h
  • ADC_FLAG_ICH : ald_adc.h
  • ADC_FLAG_ICHS : ald_adc.h
  • ADC_FLAG_NCH : ald_adc.h
  • ADC_FLAG_NCHS : ald_adc.h
  • ADC_FLAG_OVR : ald_adc.h
  • adc_flag_t : ald_adc.h
  • adc_handle_t : ald_adc.h
  • ADC_ICH_DISC_EN : ald_adc.h
  • ADC_ICH_IDX_1 : ald_adc.h
  • ADC_ICH_IDX_2 : ald_adc.h
  • ADC_ICH_IDX_3 : ald_adc.h
  • ADC_ICH_IDX_4 : ald_adc.h
  • adc_ich_idx_t : ald_adc.h
  • ADC_ICH_NR_1 : ald_adc.h
  • ADC_ICH_NR_2 : ald_adc.h
  • ADC_ICH_NR_3 : ald_adc.h
  • ADC_ICH_NR_4 : ald_adc.h
  • adc_ich_nr_t : ald_adc.h
  • ADC_IETS_DISABLE : ald_adc.h
  • ADC_IETS_ENABLE : ald_adc.h
  • ADC_IH_TRIG_BY_SOFT : ald_adc.h
  • ADC_IT_AWD : ald_adc.h
  • ADC_IT_ICH : ald_adc.h
  • ADC_IT_NCH : ald_adc.h
  • ADC_IT_OVR : ald_adc.h
  • adc_it_t : ald_adc.h
  • ADC_NCH_DISC_EN : ald_adc.h
  • ADC_NCH_IDX_1 : ald_adc.h
  • ADC_NCH_IDX_10 : ald_adc.h
  • ADC_NCH_IDX_11 : ald_adc.h
  • ADC_NCH_IDX_12 : ald_adc.h
  • ADC_NCH_IDX_13 : ald_adc.h
  • ADC_NCH_IDX_14 : ald_adc.h
  • ADC_NCH_IDX_15 : ald_adc.h
  • ADC_NCH_IDX_16 : ald_adc.h
  • ADC_NCH_IDX_2 : ald_adc.h
  • ADC_NCH_IDX_3 : ald_adc.h
  • ADC_NCH_IDX_4 : ald_adc.h
  • ADC_NCH_IDX_5 : ald_adc.h
  • ADC_NCH_IDX_6 : ald_adc.h
  • ADC_NCH_IDX_7 : ald_adc.h
  • ADC_NCH_IDX_8 : ald_adc.h
  • ADC_NCH_IDX_9 : ald_adc.h
  • adc_nch_idx_t : ald_adc.h
  • ADC_NCH_NR_1 : ald_adc.h
  • ADC_NCH_NR_10 : ald_adc.h
  • ADC_NCH_NR_11 : ald_adc.h
  • ADC_NCH_NR_12 : ald_adc.h
  • ADC_NCH_NR_13 : ald_adc.h
  • ADC_NCH_NR_14 : ald_adc.h
  • ADC_NCH_NR_15 : ald_adc.h
  • ADC_NCH_NR_16 : ald_adc.h
  • ADC_NCH_NR_2 : ald_adc.h
  • ADC_NCH_NR_3 : ald_adc.h
  • ADC_NCH_NR_4 : ald_adc.h
  • ADC_NCH_NR_5 : ald_adc.h
  • ADC_NCH_NR_6 : ald_adc.h
  • ADC_NCH_NR_7 : ald_adc.h
  • ADC_NCH_NR_8 : ald_adc.h
  • ADC_NCH_NR_9 : ald_adc.h
  • adc_nch_nr_t : ald_adc.h
  • ADC_NCHESEL_MODE_ALL : ald_adc.h
  • ADC_NCHESEL_MODE_ONE : ald_adc.h
  • adc_nchesel_t : ald_adc.h
  • adc_neg_ref_t : ald_adc.h
  • ADC_NEG_REF_VREFN : ald_adc.h
  • ADC_NEG_REF_VSS : ald_adc.h
  • ADC_NETS_DISABLE : ald_adc.h
  • ADC_NETS_ENABLE : ald_adc.h
  • ADC_NH_TRIG_BY_SOFT : ald_adc.h
  • ADC_POS_REF_2V : ald_adc.h
  • adc_pos_ref_t : ald_adc.h
  • ADC_POS_REF_VDD : ald_adc.h
  • ADC_POS_REF_VREEFP : ald_adc.h
  • ADC_POS_REF_VREEFP_BUF : ald_adc.h
  • ADC_RESET_HANDLE_STATE : ald_adc.h
  • adc_samp_t : ald_adc.h
  • ADC_SAMPLETIME_1 : ald_adc.h
  • ADC_SAMPLETIME_15 : ald_adc.h
  • ADC_SAMPLETIME_2 : ald_adc.h
  • ADC_SAMPLETIME_4 : ald_adc.h
  • ADC_SPEED_HIGH_DISABLE : ald_adc.h
  • ADC_SPEED_HIGH_ENABLE : ald_adc.h
  • ADC_STATE_BUSY : ald_adc.h
  • ADC_STATE_BUSY_I : ald_adc.h
  • ADC_STATE_BUSY_N : ald_adc.h
  • ADC_STATE_BUSY_WDG : ald_adc.h
  • ADC_STATE_ERROR : ald_adc.h
  • ADC_STATE_READY : ald_adc.h
  • ADC_STATE_RESET : ald_adc.h
  • adc_state_t : ald_adc.h
  • ADC_STATE_TIMEOUT : ald_adc.h
  • ADC_VREF_OUT_DISABLE : ald_adc.h
  • ADC_VREF_OUT_ENABLE : ald_adc.h
  • ADDR_1ST_CYCLE : ald_nand.h
  • ADDR_2ND_CYCLE : ald_nand.h
  • ADDR_3RD_CYCLE : ald_nand.h
  • ADDR_4TH_CYCLE : ald_nand.h
  • ADDR_AREA : ald_nand.h
  • ALARM_MASK_ALL : ald_rtc.h
  • ALD_ACMP : ald_conf.h
  • ald_acmp_clear_flag_status() : ald_acmp.c
  • ald_acmp_get_flag_status() : ald_acmp.c
  • ald_acmp_get_it_status() : ald_acmp.c
  • ald_acmp_get_mask_flag_status() : ald_acmp.c
  • ald_acmp_get_status() : ald_acmp.c
  • ald_acmp_init() : ald_acmp.c
  • ald_acmp_interrupt_config() : ald_acmp.c
  • ald_acmp_irq_handler() : ald_acmp.c
  • ald_acmp_out_config() : ald_acmp.c
  • ald_acmp_out_result() : ald_acmp.c
  • ALD_ADC : ald_conf.h
  • ald_adc_analog_wdg_config() : ald_adc.c
  • ald_adc_clear_flag_status() : ald_adc.c
  • ald_adc_get_error() : ald_adc.c
  • ald_adc_get_flag_status() : ald_adc.c
  • ald_adc_get_it_status() : ald_adc.c
  • ald_adc_get_state() : ald_adc.c
  • ald_adc_init() : ald_adc.c
  • ald_adc_insert_channel_config() : ald_adc.c
  • ald_adc_insert_get_value() : ald_adc.c
  • ald_adc_insert_poll_for_conversion() : ald_adc.c
  • ald_adc_insert_start() : ald_adc.c
  • ald_adc_insert_start_by_it() : ald_adc.c
  • ald_adc_insert_stop() : ald_adc.c
  • ald_adc_insert_stop_by_it() : ald_adc.c
  • ald_adc_interrupt_config() : ald_adc.c
  • ald_adc_irq_handler() : ald_adc.c
  • ald_adc_normal_channel_config() : ald_adc.c
  • ald_adc_normal_get_value() : ald_adc.c
  • ald_adc_normal_poll_for_conversion() : ald_adc.c
  • ald_adc_normal_start() : ald_adc.c
  • ald_adc_normal_start_by_it() : ald_adc.c
  • ald_adc_normal_stop() : ald_adc.c
  • ald_adc_normal_stop_by_it() : ald_adc.c
  • ald_adc_poll_for_event() : ald_adc.c
  • ald_adc_reset() : ald_adc.c
  • ald_adc_start_by_dma() : ald_adc.c
  • ald_adc_stop_by_dma() : ald_adc.c
  • ald_adc_timer_trigger_adc_by_dma() : ald_adc.c
  • ALD_BKPC : ald_conf.h
  • ald_bkpc_read_ram() : ald_bkpc.c
  • ald_bkpc_rtc_clock_config() : ald_bkpc.c
  • ald_bkpc_standby_wakeup_config() : ald_bkpc.c
  • ald_bkpc_tsense_clock_config() : ald_bkpc.c
  • ald_bkpc_write_ram() : ald_bkpc.c
  • ALD_CALC : ald_conf.h
  • ald_calc_div() : ald_calc.c
  • ald_calc_div_sign() : ald_calc.c
  • ald_calc_get_dz_status() : ald_calc.c
  • ald_calc_sqrt() : ald_calc.c
  • ALD_CAN : ald_conf.h
  • ald_can_cancel_send() : ald_can.c
  • ald_can_clear_flag_status() : ald_can.h
  • ald_can_filter_config() : ald_can.c
  • ald_can_get_error() : ald_can.c
  • ald_can_get_flag_status() : ald_can.c
  • ald_can_get_it_status() : ald_can.c
  • ald_can_get_state() : ald_can.c
  • ald_can_get_tx_status() : ald_can.c
  • ald_can_init() : ald_can.c
  • ald_can_interrupt_config() : ald_can.c
  • ald_can_irq_handler() : ald_can.c
  • ald_can_recv() : ald_can.c
  • ald_can_recv_by_it() : ald_can.c
  • ald_can_reset() : ald_can.c
  • ald_can_send() : ald_can.c
  • ald_can_send_by_it() : ald_can.c
  • ald_can_sleep() : ald_can.c
  • ald_can_wake_up() : ald_can.c
  • ALD_CMU : ald_conf.h
  • ald_cmu_buzz_config() : ald_cmu.c
  • ald_cmu_clock_config() : ald_cmu.c
  • ald_cmu_clock_config_default() : ald_cmu.c
  • ald_cmu_current_clock_source_get() : ald_cmu.c
  • ald_cmu_div_config() : ald_cmu.c
  • ald_cmu_get_clock() : ald_cmu.c
  • ald_cmu_get_clock_state() : ald_cmu.c
  • ald_cmu_get_hclk1_clock() : ald_cmu.c
  • ald_cmu_get_hclk2_clock() : ald_cmu.c
  • ald_cmu_get_pclk1_clock() : ald_cmu.c
  • ald_cmu_get_pclk2_clock() : ald_cmu.c
  • ald_cmu_get_sys_clock() : ald_cmu.c
  • ald_cmu_hosc_safe_config() : ald_cmu.c
  • ald_cmu_init() : utils.c
  • ald_cmu_irq_cbk() : ald_cmu.c
  • ald_cmu_irq_handler() : ald_cmu.c , ald_cmu.h
  • ald_cmu_lcd_clock_select() : ald_cmu.c
  • ald_cmu_losc_safe_config() : ald_cmu.c
  • ald_cmu_lptim0_clock_select() : ald_cmu.c
  • ald_cmu_lpuart0_clock_select() : ald_cmu.c
  • ald_cmu_output_high_clock_config() : ald_cmu.c
  • ald_cmu_output_low_clock_config() : ald_cmu.c
  • ald_cmu_perh_clock_config() : ald_cmu.c
  • ald_cmu_pll1_config() : ald_cmu.c
  • ald_cmu_pll_safe_config() : ald_cmu.c
  • ald_cmu_qspi_clock_select() : ald_cmu.c
  • ald_cmu_stop1_clock_sel() : ald_cmu.c
  • ald_cmu_usb_clock_config() : ald_cmu.c
  • ALD_CRC : ald_conf.h
  • ald_crc_calculate() : ald_crc.c
  • ald_crc_calculate_by_dma() : ald_crc.c
  • ald_crc_calculate_halfword() : ald_crc.c
  • ald_crc_calculate_halfword_by_dma() : ald_crc.c
  • ald_crc_calculate_word() : ald_crc.c
  • ald_crc_calculate_word_by_dma() : ald_crc.c
  • ald_crc_dma_pause() : ald_crc.c
  • ald_crc_dma_resume() : ald_crc.c
  • ald_crc_dma_stop() : ald_crc.c
  • ald_crc_get_state() : ald_crc.c
  • ald_crc_init() : ald_crc.c
  • ald_crc_reset() : ald_crc.c , ald_crc.h
  • ALD_CRYPT : ald_conf.h
  • ald_crypt_clear_flag_status() : ald_crypt.c
  • ald_crypt_decrypt() : ald_crypt.c
  • ald_crypt_decrypt_by_dma() : ald_crypt.c
  • ald_crypt_decrypt_by_it() : ald_crypt.c
  • ald_crypt_dma_pause() : ald_crypt.c
  • ald_crypt_dma_resume() : ald_crypt.c
  • ald_crypt_dma_stop() : ald_crypt.c
  • ald_crypt_encrypt() : ald_crypt.c
  • ald_crypt_encrypt_by_dma() : ald_crypt.c
  • ald_crypt_encrypt_by_it() : ald_crypt.c
  • ald_crypt_gcm_verify() : ald_crypt.c
  • ald_crypt_get_flag_status() : ald_crypt.c
  • ald_crypt_get_it_status() : ald_crypt.c
  • ald_crypt_get_state() : ald_crypt.c
  • ald_crypt_init() : ald_crypt.c
  • ald_crypt_interrupt_config() : ald_crypt.c
  • ald_crypt_irq_handler() : ald_crypt.c
  • ald_crypt_read_ivr() : ald_crypt.c
  • ald_crypt_read_key() : ald_crypt.c
  • ald_crypt_write_ivr() : ald_crypt.c
  • ald_crypt_write_key() : ald_crypt.c
  • ALD_DAC : ald_conf.h
  • ald_dac_channel_config() : ald_dac.c
  • ald_dac_clear_flag_status() : ald_dac.c
  • ald_dac_get_flag_status() : ald_dac.c
  • ald_dac_get_it_status() : ald_dac.c
  • ald_dac_get_mask_flag_status() : ald_dac.c
  • ald_dac_get_status() : ald_dac.c
  • ald_dac_init() : ald_dac.c
  • ald_dac_interrupt_config() : ald_dac.c
  • ald_dac_irq_handler() : ald_dac.c
  • ald_dac_output_set() : ald_dac.c
  • ald_dac_reset() : ald_dac.c
  • ald_dbgc_get_core_id() : ald_dbgc.h
  • ald_dbgc_get_device_id() : ald_dbgc.h
  • ald_dbgc_get_rev_id() : ald_dbgc.h
  • ald_dbgc_mode_config() : ald_dbgc.h
  • ald_dbgc_perh_config() : ald_dbgc.h
  • ald_delay_ms() : utils.c
  • ALD_DMA : ald_conf.h
  • ald_dma_channel_config() : ald_dma.c
  • ald_dma_clear_flag_status() : ald_dma.c
  • ald_dma_config_auto() : ald_dma.c
  • ald_dma_config_auto_easy() : ald_dma.c
  • ald_dma_config_basic() : ald_dma.c
  • ald_dma_config_basic_easy() : ald_dma.c
  • ald_dma_config_ping_pong() : ald_dma.c
  • ald_dma_config_sg_alt_desc() : ald_dma.c
  • ald_dma_config_sg_mem() : ald_dma.c
  • ald_dma_config_sg_per() : ald_dma.c
  • ald_dma_config_struct() : ald_dma.c
  • ald_dma_descriptor_cplt_get() : ald_dma.c
  • ald_dma_get_flag_status() : ald_dma.c
  • ald_dma_get_it_status() : ald_dma.c
  • ald_dma_init() : ald_dma.c
  • ald_dma_interrupt_config() : ald_dma.c
  • ald_dma_irq_handler() : ald_dma.c , ald_dma.h
  • ald_dma_reset() : ald_dma.c
  • ald_dma_restart_auto() : ald_dma.c
  • ald_dma_restart_basic() : ald_dma.c
  • ALD_EBI : ald_conf.h
  • ald_ebi_lcd_init() : ald_ebi.c
  • ald_ebi_lcd_reset() : ald_ebi.c
  • ald_ebi_nand_attr_timing_init() : ald_ebi.c
  • ald_ebi_nand_clear_flag() : ald_ebi.c
  • ald_ebi_nand_comm_timing_init() : ald_ebi.c
  • ald_ebi_nand_deinit() : ald_ebi.c
  • ald_ebi_nand_disable() : ald_ebi.c
  • ald_ebi_nand_disable_it() : ald_ebi.c
  • ald_ebi_nand_ecc_disable() : ald_ebi.c
  • ald_ebi_nand_ecc_enable() : ald_ebi.c
  • ald_ebi_nand_enable() : ald_ebi.c
  • ald_ebi_nand_enable_it() : ald_ebi.c
  • ald_ebi_nand_get_ecc() : ald_ebi.c
  • ald_ebi_nand_get_flag() : ald_ebi.c
  • ald_ebi_nand_init() : ald_ebi.c
  • ald_ebi_nor_sram_deinit() : ald_ebi.c
  • ald_ebi_nor_sram_disable() : ald_ebi.c
  • ald_ebi_nor_sram_enable() : ald_ebi.c
  • ald_ebi_nor_sram_ext_timing_init() : ald_ebi.c
  • ald_ebi_nor_sram_init() : ald_ebi.c
  • ald_ebi_nor_sram_timing_init() : ald_ebi.c
  • ald_ebi_nor_sram_write_disable() : ald_ebi.c
  • ald_ebi_nor_sram_write_enable() : ald_ebi.c
  • ALD_ECC : ald_conf.h
  • ALD_FLASH : ald_conf.h
  • ald_flash_erase() : ald_flash.h
  • ald_flash_read() : ald_flash.h
  • ald_flash_wait_config() : utils.c
  • ald_flash_write() : ald_flash.h
  • ald_get_ald_version() : utils.c
  • ald_get_tick() : utils.c
  • ALD_GPIO : ald_conf.h
  • ald_gpio_exti_clear_flag_status() : ald_gpio.c
  • ald_gpio_exti_get_flag_status() : ald_gpio.c
  • ald_gpio_exti_init() : ald_gpio.c
  • ald_gpio_exti_interrupt_config() : ald_gpio.c
  • ald_gpio_func_default() : ald_gpio.c
  • ald_gpio_init() : ald_gpio.c
  • ald_gpio_init_default() : ald_gpio.c
  • ald_gpio_lock_pin() : ald_gpio.c
  • ald_gpio_read_pin() : ald_gpio.c
  • ald_gpio_read_port() : ald_gpio.c
  • ald_gpio_toggle_dir() : ald_gpio.c
  • ald_gpio_toggle_pin() : ald_gpio.c
  • ald_gpio_write_pin() : ald_gpio.c
  • ald_gpio_write_port() : ald_gpio.c
  • ALD_I2C : ald_conf.h
  • ald_i2c_clear_flag_status() : ald_i2c.c , ald_i2c.h
  • ald_i2c_er_irq_handler() : ald_i2c.c
  • ald_i2c_ev_irq_handler() : ald_i2c.c
  • ald_i2c_get_error() : ald_i2c.c
  • ald_i2c_get_flag_status() : ald_i2c.c , ald_i2c.h
  • ald_i2c_get_it_status() : ald_i2c.c , ald_i2c.h
  • ald_i2c_get_mask_flag_status() : ald_i2c.c , ald_i2c.h
  • ald_i2c_get_state() : ald_i2c.c
  • ald_i2c_init() : ald_i2c.c
  • ald_i2c_interrupt_config() : ald_i2c.c
  • ald_i2c_master_recv() : ald_i2c.c
  • ald_i2c_master_recv_by_dma() : ald_i2c.c
  • ald_i2c_master_recv_by_it() : ald_i2c.c
  • ald_i2c_master_send() : ald_i2c.c
  • ald_i2c_master_send_by_dma() : ald_i2c.c
  • ald_i2c_master_send_by_it() : ald_i2c.c
  • ald_i2c_mem_read() : ald_i2c.c
  • ald_i2c_mem_read_by_dma() : ald_i2c.c
  • ald_i2c_mem_read_by_it() : ald_i2c.c
  • ald_i2c_mem_write() : ald_i2c.c
  • ald_i2c_mem_write_by_dma() : ald_i2c.c
  • ald_i2c_mem_write_by_it() : ald_i2c.c
  • ald_i2c_reset() : ald_i2c.c
  • ald_i2c_slave_recv() : ald_i2c.c
  • ald_i2c_slave_recv_by_dma() : ald_i2c.c
  • ald_i2c_slave_recv_by_it() : ald_i2c.c
  • ald_i2c_slave_send() : ald_i2c.c
  • ald_i2c_slave_send_by_dma() : ald_i2c.c
  • ald_i2c_slave_send_by_it() : ald_i2c.c
  • ALD_I2S : ald_conf.h
  • ald_i2s_clear_flag_status() : ald_i2s.c
  • ald_i2s_dma_pause() : ald_i2s.c
  • ald_i2s_dma_req_config() : ald_i2s.c
  • ald_i2s_dma_resume() : ald_i2s.c
  • ald_i2s_dma_stop() : ald_i2s.c
  • ald_i2s_get_error() : ald_i2s.c
  • ald_i2s_get_flag_status() : ald_i2s.c
  • ald_i2s_get_it_status() : ald_i2s.c
  • ald_i2s_get_mask_flag_status() : ald_i2s.c
  • ald_i2s_get_state() : ald_i2s.c
  • ald_i2s_get_status() : ald_i2s.c
  • ald_i2s_init() : ald_i2s.c
  • ald_i2s_interrupt_config() : ald_i2s.c
  • ald_i2s_irq_handler() : ald_i2s.c
  • ald_i2s_master_recv() : ald_i2s.c
  • ald_i2s_master_recv_by_dma() : ald_i2s.c
  • ald_i2s_master_recv_by_it() : ald_i2s.c
  • ald_i2s_master_send() : ald_i2s.c
  • ald_i2s_master_send_by_dma() : ald_i2s.c
  • ald_i2s_master_send_by_it() : ald_i2s.c
  • ald_i2s_reset() : ald_i2s.c
  • ALD_IAP : ald_conf.h
  • ald_iap_erase_page() : ald_iap.c
  • ald_iap_program_dword() : ald_iap.c
  • ald_iap_program_word() : ald_iap.c
  • ald_iap_program_words() : ald_iap.c
  • ald_inc_tick() : utils.c
  • ald_iwdt_clear_flag_status() : ald_wdt.c
  • ald_iwdt_feed_dog() : ald_wdt.c
  • ald_iwdt_get_flag_status() : ald_wdt.c
  • ald_iwdt_get_value() : ald_wdt.c
  • ald_iwdt_init() : ald_wdt.c
  • ald_iwdt_start() : ald_wdt.c
  • ALD_LCD : ald_conf.h
  • ALD_LPTIM : ald_conf.h
  • ALD_LPUART : ald_conf.h
  • ald_lvd_irq_handler() : ald_pmu.c , ald_pmu.h
  • ALD_MAX_DELAY : utils.h
  • ald_mcu_get_chipid() : utils.c
  • ald_mcu_get_cpu_id() : utils.c
  • ald_mcu_get_timestamp() : utils.c
  • ald_mcu_get_uid() : utils.c
  • ald_mcu_irq_config() : utils.c
  • ald_mcu_timestamp_init() : utils.c
  • ALD_NAND : ald_conf.h
  • ald_nand_address_inc() : ald_nand.c
  • ald_nand_deinit() : ald_nand.c
  • ald_nand_ecc_disable() : ald_nand.c
  • ald_nand_ecc_enable() : ald_nand.c
  • ald_nand_erase_block() : ald_nand.c
  • ald_nand_get_ecc() : ald_nand.c
  • ald_nand_get_state() : ald_nand.c
  • ald_nand_init() : ald_nand.c
  • ald_nand_irq_cbk() : ald_nand.c
  • ald_nand_irq_handler() : ald_nand.c
  • ald_nand_read_id() : ald_nand.c
  • ald_nand_read_page_16b() : ald_nand.c
  • ald_nand_read_page_8b() : ald_nand.c
  • ald_nand_read_sparearea_16b() : ald_nand.c
  • ald_nand_read_sparearea_8b() : ald_nand.c
  • ald_nand_read_status() : ald_nand.c
  • ald_nand_reset() : ald_nand.c
  • ALD_NAND_STATE_BUSY : ald_nand.h
  • ALD_NAND_STATE_ERROR : ald_nand.h
  • ALD_NAND_STATE_READY : ald_nand.h
  • ALD_NAND_STATE_RESET : ald_nand.h
  • ald_nand_state_t : ald_nand.h
  • ald_nand_write_page_16b() : ald_nand.c
  • ald_nand_write_page_8b() : ald_nand.c
  • ald_nand_write_sparearea_16b() : ald_nand.c
  • ald_nand_write_sparearea_8b() : ald_nand.c
  • ALD_NOR : ald_conf.h
  • ald_nor_deinit() : ald_nor_lcd.h , ald_nor_lcd.c
  • ald_nor_erase_block() : ald_nor_lcd.c
  • ald_nor_erase_chip() : ald_nor_lcd.c
  • ald_nor_get_state() : ald_nor_lcd.c
  • ald_nor_get_status() : ald_nor_lcd.c
  • ald_nor_init() : ald_nor_lcd.c , ald_nor_lcd.h
  • ald_nor_program() : ald_nor_lcd.c
  • ald_nor_program_buffer() : ald_nor_lcd.c
  • ald_nor_read() : ald_nor_lcd.c
  • ald_nor_read_buffer() : ald_nor_lcd.c
  • ald_nor_read_cfi() : ald_nor_lcd.c
  • ald_nor_read_id() : ald_nor_lcd.c
  • ald_nor_return_readmode() : ald_nor_lcd.c
  • ALD_NOR_STATE_BUSY : ald_nor_lcd.h
  • ALD_NOR_STATE_ERROR : ald_nor_lcd.h
  • ALD_NOR_STATE_PROTECTED : ald_nor_lcd.h
  • ALD_NOR_STATE_READY : ald_nor_lcd.h
  • ALD_NOR_STATE_RESET : ald_nor_lcd.h
  • ald_nor_state_t : ald_nor_lcd.h
  • ALD_NOR_STATUS_ERROR : ald_nor_lcd.h
  • ALD_NOR_STATUS_ONGOING : ald_nor_lcd.h
  • ALD_NOR_STATUS_SUCCESS : ald_nor_lcd.h
  • ALD_NOR_STATUS_TIMEOUT : ald_nor_lcd.h
  • ald_nor_write_disable() : ald_nor_lcd.c
  • ald_nor_write_enable() : ald_nor_lcd.c
  • ALD_OPAMP : ald_conf.h
  • ALD_PANIC : utils.h
  • ALD_PIS : ald_conf.h
  • ald_pis_create() : ald_pis.c
  • ald_pis_destroy() : ald_pis.c
  • ald_pis_get_state() : ald_pis.c
  • ald_pis_modu_config() : ald_pis.c
  • ald_pis_output_start() : ald_pis.c
  • ald_pis_output_stop() : ald_pis.c
  • ALD_PMU : ald_conf.h
  • ald_pmu_clear_status() : ald_pmu.c
  • ald_pmu_get_status() : ald_pmu.c
  • ald_pmu_ldo_12_config() : ald_pmu.c
  • ald_pmu_ldo_18_config() : ald_pmu.c
  • ald_pmu_lvd_config() : ald_pmu.c
  • ald_pmu_perh_power_config() : ald_pmu.c
  • ald_pmu_sleep() : ald_pmu.h
  • ald_pmu_sleep_deep() : ald_pmu.h
  • ald_pmu_standby_enter() : ald_pmu.c
  • ald_pmu_stop1_enter() : ald_pmu.c
  • ald_pmu_stop2_enter() : ald_pmu.c
  • ALD_QSPI : ald_conf.h
  • ald_qspi_auto_poll() : ald_qspi.h
  • ald_qspi_clear_it_flag() : ald_qspi.c
  • ald_qspi_dac_rd() : ald_qspi.c
  • ald_qspi_dac_wr() : ald_qspi.c
  • ald_qspi_device_delay_config() : ald_qspi.c
  • ald_qspi_device_size_config() : ald_qspi.c
  • ald_qspi_execute_stig_cmd() : ald_qspi.c
  • ald_qspi_indac_config() : ald_qspi.c
  • ald_qspi_indac_read_by_dma() : ald_qspi.c
  • ald_qspi_indac_read_by_it() : ald_qspi.c
  • ald_qspi_indac_read_by_poll() : ald_qspi.c
  • ald_qspi_indac_transmit_by_dma() : ald_qspi.c
  • ald_qspi_indac_transmit_by_it() : ald_qspi.c
  • ald_qspi_indac_transmit_by_poll() : ald_qspi.c
  • ald_qspi_init() : ald_qspi.c
  • ald_qspi_interrupt_config() : ald_qspi.c
  • ald_qspi_irq_handler() : ald_qspi.c
  • ald_qspi_legacy_config() : ald_qspi.c
  • ald_qspi_read_config() : ald_qspi.c
  • ald_qspi_read_data_capture_config() : ald_qspi.c
  • ald_qspi_write_config() : ald_qspi.c
  • ald_qspi_write_proect_config() : ald_qspi.c
  • ald_qspi_write_proect_inverse() : ald_qspi.c
  • ald_resume_tick() : utils.c
  • ALD_RMU : ald_conf.h
  • ald_rmu_bor_config() : ald_rmu.c
  • ald_rmu_clear_reset_status() : ald_rmu.c
  • ald_rmu_get_reset_status() : ald_rmu.c
  • ald_rmu_reset_periperal() : ald_rmu.c
  • ALD_RTC : ald_conf.h
  • ald_rtc_alarm_cmd() : ald_rtc.c
  • ald_rtc_cancel_cali() : ald_rtc.c
  • ald_rtc_cancel_clock_output() : ald_rtc.c
  • ald_rtc_cancel_tamper() : ald_rtc.c
  • ald_rtc_cancel_time_stamp() : ald_rtc.c
  • ald_rtc_cancel_wakeup() : ald_rtc.c
  • ald_rtc_clear_flag_status() : ald_rtc.c
  • ald_rtc_get_alarm() : ald_rtc.c
  • ald_rtc_get_cali_status() : ald_rtc.c
  • ald_rtc_get_date() : ald_rtc.c
  • ald_rtc_get_date_time() : ald_rtc.c
  • ald_rtc_get_flag_status() : ald_rtc.c
  • ald_rtc_get_it_status() : ald_rtc.c
  • ald_rtc_get_time() : ald_rtc.c
  • ald_rtc_get_time_stamp() : ald_rtc.c
  • ald_rtc_get_wakeup_timer_value() : ald_rtc.c
  • ald_rtc_hw_auto_cali() : ald_rtchw.c
  • ald_rtc_init() : ald_rtc.c
  • ald_rtc_interrupt_config() : ald_rtc.c
  • ald_rtc_reset() : ald_rtc.c
  • ald_rtc_set_alarm() : ald_rtc.c
  • ald_rtc_set_cali() : ald_rtc.c
  • ald_rtc_set_clock_output() : ald_rtc.c
  • ald_rtc_set_date() : ald_rtc.c
  • ald_rtc_set_shift() : ald_rtc.c
  • ald_rtc_set_tamper() : ald_rtc.c
  • ald_rtc_set_time() : ald_rtc.c
  • ald_rtc_set_time_stamp() : ald_rtc.c
  • ald_rtc_set_wakeup() : ald_rtc.c
  • ald_rtc_source_select() : ald_rtc.c
  • ald_rtc_write_temp() : ald_rtc.c
  • ALD_SPI : ald_conf.h
  • ald_spi_clear_flag_status() : ald_spi.c
  • ald_spi_dma_pause() : ald_spi.c
  • ald_spi_dma_req_config() : ald_spi.c
  • ald_spi_dma_resume() : ald_spi.c
  • ald_spi_dma_stop() : ald_spi.c
  • ald_spi_get_error() : ald_spi.c
  • ald_spi_get_flag_status() : ald_spi.c
  • ald_spi_get_it_status() : ald_spi.c
  • ald_spi_get_state() : ald_spi.c
  • ald_spi_init() : ald_spi.c
  • ald_spi_interrupt_config() : ald_spi.c
  • ald_spi_irq_handler() : ald_spi.c
  • ald_spi_master_recv_bytes_fast() : ald_spi.c
  • ald_spi_master_recv_dbytes_fast() : ald_spi.c
  • ald_spi_recv() : ald_spi.c
  • ald_spi_recv_by_dma() : ald_spi.c
  • ald_spi_recv_by_it() : ald_spi.c
  • ald_spi_recv_byte_fast() : ald_spi.c
  • ald_spi_reset() : ald_spi.c
  • ald_spi_send() : ald_spi.c
  • ald_spi_send_by_dma() : ald_spi.c
  • ald_spi_send_by_it() : ald_spi.c
  • ald_spi_send_byte_fast() : ald_spi.c
  • ald_spi_send_byte_fast_1line() : ald_spi.c
  • ald_spi_send_bytes_fast() : ald_spi.c
  • ald_spi_send_dbytes_fast() : ald_spi.c
  • ald_spi_send_recv() : ald_spi.c
  • ald_spi_send_recv_by_dma() : ald_spi.c
  • ald_spi_send_recv_by_it() : ald_spi.c
  • ald_spi_slave_recv_bytes_fast() : ald_spi.c
  • ald_spi_slave_recv_dbytes_fast() : ald_spi.c
  • ald_spi_speed_config() : ald_spi.c
  • ALD_SRAM : ald_conf.h
  • ald_sram_deinit() : ald_sram.c
  • ald_sram_get_state() : ald_sram.c
  • ald_sram_init() : ald_sram.c
  • ald_sram_read_16b() : ald_sram.c
  • ald_sram_read_32b() : ald_sram.c
  • ald_sram_read_8b() : ald_sram.c
  • ald_sram_read_by_dma() : ald_sram.c
  • ALD_SRAM_STATE_BUSY : ald_sram.h
  • ALD_SRAM_STATE_ERROR : ald_sram.h
  • ALD_SRAM_STATE_PROTECTED : ald_sram.h
  • ALD_SRAM_STATE_READY : ald_sram.h
  • ALD_SRAM_STATE_RESET : ald_sram.h
  • ald_sram_state_t : ald_sram.h
  • ald_sram_write_16b() : ald_sram.c
  • ald_sram_write_32b() : ald_sram.c
  • ald_sram_write_8b() : ald_sram.c
  • ald_sram_write_by_dma() : ald_sram.c
  • ald_sram_write_disable() : ald_sram.c
  • ald_sram_write_enable() : ald_sram.c
  • ald_status_t : utils.h
  • ald_suspend_tick() : utils.c
  • ald_systick_interval_select() : utils.c
  • ald_systick_irq_cbk() : utils.c
  • ald_tick_init() : utils.c
  • ALD_TIMER : ald_conf.h
  • ald_timer_base_init() : ald_timer.c
  • ald_timer_base_reset() : ald_timer.c
  • ald_timer_base_start() : ald_timer.c
  • ald_timer_base_start_by_dma() : ald_timer.c
  • ald_timer_base_start_by_it() : ald_timer.c
  • ald_timer_base_stop() : ald_timer.c
  • ald_timer_base_stop_by_dma() : ald_timer.c
  • ald_timer_base_stop_by_it() : ald_timer.c
  • ald_timer_break_dead_time_config() : ald_timer.c
  • ald_timer_clear_flag_status() : ald_timer.c
  • ald_timer_com_change_config() : ald_timer.c
  • ald_timer_com_event_config() : ald_timer.c
  • ald_timer_com_event_config_it() : ald_timer.c
  • ald_timer_config_clock_source() : ald_timer.c
  • ald_timer_config_oc_ref_clear() : ald_timer.c
  • ald_timer_config_ti1_input() : ald_timer.c
  • ald_timer_dma_req_config() : ald_timer.c
  • ald_timer_encoder_init() : ald_timer.c
  • ald_timer_encoder_start() : ald_timer.c
  • ald_timer_encoder_start_by_dma() : ald_timer.c
  • ald_timer_encoder_start_by_it() : ald_timer.c
  • ald_timer_encoder_stop() : ald_timer.c
  • ald_timer_encoder_stop_by_dma() : ald_timer.c
  • ald_timer_encoder_stop_by_it() : ald_timer.c
  • ald_timer_generate_event() : ald_timer.c
  • ald_timer_get_flag_status() : ald_timer.c
  • ald_timer_get_it_status() : ald_timer.c
  • ald_timer_get_state() : ald_timer.c
  • ald_timer_hall_sensor_init() : ald_timer.c
  • ald_timer_hall_sensor_start() : ald_timer.c
  • ald_timer_hall_sensor_start_by_dma() : ald_timer.c
  • ald_timer_hall_sensor_start_by_it() : ald_timer.c
  • ald_timer_hall_sensor_stop() : ald_timer.c
  • ald_timer_hall_sensor_stop_by_dma() : ald_timer.c
  • ald_timer_hall_sensor_stop_by_it() : ald_timer.c
  • ald_timer_ic_config_channel() : ald_timer.c
  • ald_timer_ic_init() : ald_timer.c
  • ald_timer_ic_start() : ald_timer.c
  • ald_timer_ic_start_by_dma() : ald_timer.c
  • ald_timer_ic_start_by_it() : ald_timer.c
  • ald_timer_ic_stop() : ald_timer.c
  • ald_timer_ic_stop_by_dma() : ald_timer.c
  • ald_timer_ic_stop_by_it() : ald_timer.c
  • ald_timer_interrupt_config() : ald_timer.c
  • ald_timer_irq_handler() : ald_timer.c
  • ald_timer_master_sync_config() : ald_timer.c
  • ald_timer_oc_config_channel() : ald_timer.c
  • ald_timer_oc_init() : ald_timer.c
  • ald_timer_oc_start() : ald_timer.c
  • ald_timer_oc_start_by_dma() : ald_timer.c
  • ald_timer_oc_start_by_it() : ald_timer.c
  • ald_timer_oc_stop() : ald_timer.c
  • ald_timer_oc_stop_by_dma() : ald_timer.c
  • ald_timer_oc_stop_by_it() : ald_timer.c
  • ald_timer_ocn_start() : ald_timer.c
  • ald_timer_ocn_start_by_dma() : ald_timer.c
  • ald_timer_ocn_start_by_it() : ald_timer.c
  • ald_timer_ocn_stop() : ald_timer.c
  • ald_timer_ocn_stop_by_dma() : ald_timer.c
  • ald_timer_ocn_stop_by_it() : ald_timer.c
  • ald_timer_one_pulse_config_channel() : ald_timer.c
  • ald_timer_one_pulse_init() : ald_timer.c
  • ald_timer_one_pulse_n_start() : ald_timer.c
  • ald_timer_one_pulse_n_start_by_it() : ald_timer.c
  • ald_timer_one_pulse_n_stop() : ald_timer.c
  • ald_timer_one_pulse_n_stop_by_it() : ald_timer.c
  • ald_timer_one_pulse_start() : ald_timer.c
  • ald_timer_one_pulse_start_by_it() : ald_timer.c
  • ald_timer_one_pulse_stop() : ald_timer.c
  • ald_timer_one_pulse_stop_by_it() : ald_timer.c
  • ald_timer_pwm_init() : ald_timer.c
  • ald_timer_pwm_set_duty() : ald_timer.c
  • ald_timer_pwm_set_freq() : ald_timer.c
  • ald_timer_pwm_set_input() : ald_timer.c
  • ald_timer_pwm_start() : ald_timer.c
  • ald_timer_pwm_start_by_dma() : ald_timer.c
  • ald_timer_pwm_start_by_it() : ald_timer.c
  • ald_timer_pwm_stop() : ald_timer.c
  • ald_timer_pwm_stop_by_dma() : ald_timer.c
  • ald_timer_pwm_stop_by_it() : ald_timer.c
  • ald_timer_pwmn_start() : ald_timer.c
  • ald_timer_pwmn_start_by_dma() : ald_timer.c
  • ald_timer_pwmn_start_by_it() : ald_timer.c
  • ald_timer_pwmn_stop() : ald_timer.c
  • ald_timer_pwmn_stop_by_dma() : ald_timer.c
  • ald_timer_pwmn_stop_by_it() : ald_timer.c
  • ald_timer_read_capture_value() : ald_timer.c
  • ald_timer_set_output_mode() : ald_timer.c
  • ald_timer_slave_config_sync() : ald_timer.c
  • ald_timer_slave_config_sync_by_it() : ald_timer.c
  • ALD_TRNG : ald_conf.h
  • ald_trng_clear_flag_status() : ald_trng.c
  • ald_trng_get_flag_status() : ald_trng.c
  • ald_trng_get_it_status() : ald_trng.c
  • ald_trng_get_result() : ald_trng.c
  • ald_trng_get_status() : ald_trng.c
  • ald_trng_init() : ald_trng.c
  • ald_trng_interrupt_config() : ald_trng.c
  • ald_trng_irq_handler() : ald_trng.c
  • ALD_TSENSE : ald_conf.h
  • ald_tsense_get_value() : ald_tsense.c
  • ald_tsense_get_value_by_it() : ald_tsense.c
  • ald_tsense_init() : ald_tsense.c
  • ald_tsense_irq_handler() : ald_tsense.c
  • ald_tsense_source_select() : ald_tsense.c
  • ALD_UART : ald_conf.h
  • ald_uart_auto_baud_config() : ald_uart.c
  • ald_uart_clear_flag_status() : ald_uart.c
  • ald_uart_dma_pause() : ald_uart.c
  • ald_uart_dma_req_config() : ald_uart.c
  • ald_uart_dma_resume() : ald_uart.c
  • ald_uart_dma_stop() : ald_uart.c
  • ald_uart_get_error() : ald_uart.c
  • ald_uart_get_flag_status() : ald_uart.c
  • ald_uart_get_it_status() : ald_uart.c
  • ald_uart_get_mask_flag_status() : ald_uart.c
  • ald_uart_get_state() : ald_uart.c
  • ald_uart_get_status() : ald_uart.c
  • ald_uart_init() : ald_uart.c
  • ald_uart_interrupt_config() : ald_uart.c
  • ald_uart_irq_handler() : ald_uart.c
  • ald_uart_irq_handler_fast() : ald_uart.c
  • ald_uart_lin_detect_break_len_config() : ald_uart.c
  • ald_uart_lin_send_break() : ald_uart.c
  • ald_uart_recv() : ald_uart.c
  • ald_uart_recv_by_dma() : ald_uart.c
  • ald_uart_recv_by_it() : ald_uart.c
  • ald_uart_recv_frame_by_it() : ald_uart.c
  • ald_uart_recv_n_lock() : ald_uart.c
  • ald_uart_reset() : ald_uart.c
  • ald_uart_rs485_config() : ald_uart.c
  • ald_uart_rs485_send_addr() : ald_uart.c
  • ald_uart_rx_fifo_config() : ald_uart.c
  • ald_uart_scard_config() : ald_uart.c
  • ald_uart_send() : ald_uart.c
  • ald_uart_send_by_dma() : ald_uart.c
  • ald_uart_send_by_it() : ald_uart.c
  • ald_uart_send_n_lock() : ald_uart.c
  • ald_uart_tx_fifo_config() : ald_uart.c
  • ALD_USB : ald_conf.h
  • ald_usb_clock_output() : ald_usb.c
  • ald_usb_control_reset() : ald_usb.c
  • ald_usb_dev_connect() : ald_usb.c
  • ald_usb_dev_disconnect() : ald_usb.c
  • ald_usb_dev_ep_config() : ald_usb.c
  • ald_usb_dev_ep_data_ack() : ald_usb.c
  • ald_usb_dev_ep_get_config() : ald_usb.c
  • ald_usb_dev_ep_stall() : ald_usb.c
  • ald_usb_dev_ep_stall_clear() : ald_usb.c
  • ald_usb_dev_ep_status_clear() : ald_usb.c
  • ald_usb_dev_get_addr() : ald_usb.c
  • ald_usb_dev_lpm_config() : ald_usb.c
  • ald_usb_dev_lpm_disable() : ald_usb.c
  • ald_usb_dev_lpm_enable() : ald_usb.c
  • ald_usb_dev_lpm_remote_wake() : ald_usb.c
  • ald_usb_dev_set_addr() : ald_usb.c
  • ald_usb_device_speed_get() : ald_usb.c
  • ald_usb_dma_channel_config() : ald_usb.c
  • ald_usb_dma_channel_start() : ald_usb.c
  • ald_usb_dma_channel_stop() : ald_usb.c
  • ald_usb_dma_clear_channel_error() : ald_usb.c
  • ald_usb_dma_get_channel_error() : ald_usb.c
  • ald_usb_dma_get_interrupt_flag() : ald_usb.c
  • ald_usb_dma_mult_recv_start() : ald_usb.c
  • ald_usb_ep_data_avail() : ald_usb.c
  • ald_usb_ep_data_get() : ald_usb.c
  • ald_usb_ep_data_put() : ald_usb.c
  • ald_usb_ep_data_send() : ald_usb.c
  • ald_usb_ep_data_toggle_clear() : ald_usb.c
  • ald_usb_ep_dma_config() : ald_usb.c
  • ald_usb_ep_req_packet_count() : ald_usb.c
  • ald_usb_ep_status() : ald_usb.c
  • ald_usb_eye_diagram_start() : ald_usb.c
  • ald_usb_fifo_addr_get() : ald_usb.c
  • ald_usb_fifo_config_get() : ald_usb.c
  • ald_usb_fifo_config_set() : ald_usb.c
  • ald_usb_fifo_flush() : ald_usb.c
  • ald_usb_frame_number_get() : ald_usb.c
  • ald_usb_high_speed_enable() : ald_usb.c
  • ald_usb_host_addr_get() : ald_usb.c
  • ald_usb_host_addr_set() : ald_usb.c
  • ald_usb_host_ep_config() : ald_usb.c
  • ald_usb_host_ep_data_ack() : ald_usb.c
  • ald_usb_host_ep_data_toggle() : ald_usb.c
  • ald_usb_host_ep_ping() : ald_usb.c
  • ald_usb_host_ep_speed_set() : ald_usb.c
  • ald_usb_host_ep_status_clear() : ald_usb.c
  • ald_usb_host_hub_addr_get() : ald_usb.c
  • ald_usb_host_hub_addr_set() : ald_usb.c
  • ald_usb_host_lpm_config() : ald_usb.c
  • ald_usb_host_lpm_resume() : ald_usb.c
  • ald_usb_host_lpm_send() : ald_usb.c
  • ald_usb_host_pwr_config() : ald_usb.c
  • ald_usb_host_pwr_disable() : ald_usb.c
  • ald_usb_host_pwr_enable() : ald_usb.c
  • ald_usb_host_pwr_fault_disable() : ald_usb.c
  • ald_usb_host_pwr_fault_enable() : ald_usb.c
  • ald_usb_host_request_in() : ald_usb.c
  • ald_usb_host_request_in_clear() : ald_usb.c
  • ald_usb_host_request_status() : ald_usb.c
  • ald_usb_host_reset() : ald_usb.c
  • ald_usb_host_resume() : ald_usb.c
  • ald_usb_host_speed_get() : ald_usb.c
  • ald_usb_host_suspend() : ald_usb.c
  • ald_usb_int_disable() : ald_usb.c
  • ald_usb_int_disable_ep() : ald_usb.c
  • ald_usb_int_enable() : ald_usb.c
  • ald_usb_int_enable_ep() : ald_usb.c
  • ald_usb_int_num_get() : ald_usb.c
  • ald_usb_int_register() : ald_usb.c
  • ald_usb_int_status_ep_get() : ald_usb.c
  • ald_usb_int_status_get() : ald_usb.c
  • ald_usb_int_unregister() : ald_usb.c
  • ald_usb_lpm_ep_get() : ald_usb.c
  • ald_usb_lpm_int_disable() : ald_usb.c
  • ald_usb_lpm_int_enable() : ald_usb.c
  • ald_usb_lpm_int_status_get() : ald_usb.c
  • ald_usb_lpm_link_status_get() : ald_usb.c
  • ald_usb_lpm_remote_wake_is_enable() : ald_usb.c
  • ald_usb_mode_get() : ald_usb.c
  • ald_usb_num_ep_get() : ald_usb.c
  • ald_usb_otg_session_request() : ald_usb.c
  • ald_vtor_config() : ald_syscfg.h
  • ald_wait_flag() : utils.c
  • ALD_WDT : ald_conf.h
  • ald_wwdt_clear_flag_status() : ald_wdt.c
  • ald_wwdt_feed_dog() : ald_wdt.c
  • ald_wwdt_get_flag_status() : ald_wdt.c
  • ald_wwdt_get_value() : ald_wdt.c
  • ald_wwdt_init() : ald_wdt.c
  • ald_wwdt_start() : ald_wdt.c
  • ARRAY_ADDRESS : ald_nand.h
  • assert_param : type.h


ALD User Manual: Globals

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- b -

  • bcd_to_dec() : ald_rtc.c
  • BCTRLR_CLEAR_MASK : ald_ebi.h
  • BIT : type.h
  • BIT_RESET : type.h
  • BIT_SET : type.h
  • bit_status_t : type.h
  • BITBAND_PER() : type.h
  • BITBAND_PER_BASE : type.h
  • BITBAND_RAM_BASE : type.h
  • BITBAND_SRAM() : type.h
  • BITS : type.h
  • BKPC_LOCK : ald_bkpc.h
  • BKPC_LOSC_DISABLE : ald_bkpc.h
  • BKPC_LOSC_ENABLE : ald_bkpc.h
  • BKPC_LOSM_DISABLE : ald_bkpc.h
  • BKPC_LOSM_ENABLE : ald_bkpc.h
  • BKPC_LRC_DISABLE : ald_bkpc.h
  • BKPC_LRC_ENABLE : ald_bkpc.h
  • BKPC_MRST_WAKEUP_DISABLE : ald_bkpc.h
  • BKPC_MRST_WAKEUP_ENABLE : ald_bkpc.h
  • BKPC_PREH_CLK_HOSC_1M : ald_bkpc.h
  • BKPC_PREH_CLK_HRC_1M : ald_bkpc.h
  • BKPC_PREH_CLK_LOSM : ald_bkpc.h
  • BKPC_PREH_CLK_LRC : ald_bkpc.h
  • bkpc_preh_clk_t : ald_bkpc.h
  • BKPC_UNLOCK : ald_bkpc.h
  • bkpc_wakeup_level_t : ald_bkpc.h
  • bkpc_wakeup_port_t : ald_bkpc.h
  • BTR_CLEAR_MASK : ald_ebi.h
  • BUSY : utils.h
  • BWTR_CLEAR_MASK : ald_ebi.h


ALD User Manual: Globals

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- c -

  • can_clear_flag() : ald_can.c
  • CAN_DBG_FREEZE : ald_can.h
  • CAN_ERROR_ACK : ald_can.h
  • CAN_ERROR_BD : ald_can.h
  • CAN_ERROR_BOF : ald_can.h
  • CAN_ERROR_BR : ald_can.h
  • CAN_ERROR_CRC : ald_can.h
  • CAN_ERROR_EPV : ald_can.h
  • CAN_ERROR_EWG : ald_can.h
  • CAN_ERROR_FOR : ald_can.h
  • CAN_ERROR_NONE : ald_can.h
  • CAN_ERROR_STF : ald_can.h
  • can_error_t : ald_can.h
  • CAN_ERROR_UNK : ald_can.h
  • CAN_FILTER_FIFO0 : ald_can.h
  • CAN_FILTER_FIFO1 : ald_can.h
  • can_filter_fifo_t : ald_can.h
  • CAN_FILTER_MODE_LIST : ald_can.h
  • CAN_FILTER_MODE_MASK : ald_can.h
  • can_filter_mode_t : ald_can.h
  • CAN_FILTER_SCALE_16 : ald_can.h
  • CAN_FILTER_SCALE_32 : ald_can.h
  • can_filter_scale_t : ald_can.h
  • CAN_FLAG_BOF : ald_can.h
  • CAN_FLAG_ERR : ald_can.h
  • CAN_FLAG_FF0 : ald_can.h
  • CAN_FLAG_FF1 : ald_can.h
  • CAN_FLAG_FOV0 : ald_can.h
  • CAN_FLAG_FOV1 : ald_can.h
  • CAN_FLAG_M0REQC : ald_can.h
  • CAN_FLAG_M0TXC : ald_can.h
  • CAN_FLAG_M1REQC : ald_can.h
  • CAN_FLAG_M1TXC : ald_can.h
  • CAN_FLAG_M2REQC : ald_can.h
  • CAN_FLAG_M2TXC : ald_can.h
  • CAN_FLAG_PERR : ald_can.h
  • CAN_FLAG_SLP : ald_can.h
  • CAN_FLAG_SLPS : ald_can.h
  • can_flag_t : ald_can.h
  • CAN_FLAG_TXM0 : ald_can.h
  • CAN_FLAG_TXM1 : ald_can.h
  • CAN_FLAG_TXM2 : ald_can.h
  • CAN_FLAG_WARN : ald_can.h
  • CAN_FLAG_WK : ald_can.h
  • can_handle_t : ald_can.h
  • CAN_ID_EXT : ald_can.h
  • CAN_ID_STD : ald_can.h
  • can_id_type_t : ald_can.h
  • CAN_IT_BOF : ald_can.h
  • CAN_IT_ERR : ald_can.h
  • CAN_IT_FF0 : ald_can.h
  • CAN_IT_FF1 : ald_can.h
  • CAN_IT_FOV0 : ald_can.h
  • CAN_IT_FOV1 : ald_can.h
  • CAN_IT_FP0 : ald_can.h
  • CAN_IT_FP1 : ald_can.h
  • CAN_IT_PERR : ald_can.h
  • CAN_IT_PRERR : ald_can.h
  • CAN_IT_SLP : ald_can.h
  • can_it_t : ald_can.h
  • CAN_IT_TXM : ald_can.h
  • CAN_IT_WARN : ald_can.h
  • CAN_IT_WK : ald_can.h
  • CAN_MODE_LOOPBACK : ald_can.h
  • CAN_MODE_NORMAL : ald_can.h
  • CAN_MODE_SILENT : ald_can.h
  • CAN_MODE_SILENT_LOOPBACK : ald_can.h
  • can_operate_mode_t : ald_can.h
  • can_remote_req_t : ald_can.h
  • CAN_RESET_HANDLE_STATE : ald_can.h
  • CAN_RTR_DATA : ald_can.h
  • CAN_RTR_REMOTE : ald_can.h
  • CAN_RX_FIFO0 : ald_can.h
  • CAN_RX_FIFO1 : ald_can.h
  • can_rx_fifo_release() : ald_can.c
  • can_rx_fifo_t : ald_can.h
  • CAN_RX_MSG_PENDING : ald_can.h
  • CAN_SEG1_1 : ald_can.h
  • CAN_SEG1_10 : ald_can.h
  • CAN_SEG1_11 : ald_can.h
  • CAN_SEG1_12 : ald_can.h
  • CAN_SEG1_13 : ald_can.h
  • CAN_SEG1_14 : ald_can.h
  • CAN_SEG1_15 : ald_can.h
  • CAN_SEG1_16 : ald_can.h
  • CAN_SEG1_2 : ald_can.h
  • CAN_SEG1_3 : ald_can.h
  • CAN_SEG1_4 : ald_can.h
  • CAN_SEG1_5 : ald_can.h
  • CAN_SEG1_6 : ald_can.h
  • CAN_SEG1_7 : ald_can.h
  • CAN_SEG1_8 : ald_can.h
  • CAN_SEG1_9 : ald_can.h
  • can_seg1_t : ald_can.h
  • CAN_SEG2_1 : ald_can.h
  • CAN_SEG2_2 : ald_can.h
  • CAN_SEG2_3 : ald_can.h
  • CAN_SEG2_4 : ald_can.h
  • CAN_SEG2_5 : ald_can.h
  • CAN_SEG2_6 : ald_can.h
  • CAN_SEG2_7 : ald_can.h
  • CAN_SEG2_8 : ald_can.h
  • can_seg2_t : ald_can.h
  • CAN_SJW_1 : ald_can.h
  • CAN_SJW_2 : ald_can.h
  • CAN_SJW_3 : ald_can.h
  • CAN_SJW_4 : ald_can.h
  • can_sjw_t : ald_can.h
  • CAN_STATE_BUSY : ald_can.h
  • CAN_STATE_BUSY_RX0 : ald_can.h
  • CAN_STATE_BUSY_RX0_RX1 : ald_can.h
  • CAN_STATE_BUSY_RX1 : ald_can.h
  • CAN_STATE_BUSY_TX : ald_can.h
  • CAN_STATE_BUSY_TX_RX0 : ald_can.h
  • CAN_STATE_BUSY_TX_RX0_RX1 : ald_can.h
  • CAN_STATE_BUSY_TX_RX1 : ald_can.h
  • CAN_STATE_ERROR : ald_can.h
  • CAN_STATE_READY : ald_can.h
  • CAN_STATE_RESET : ald_can.h
  • CAN_STATE_RX0_MASK : ald_can.h
  • CAN_STATE_RX1_MASK : ald_can.h
  • can_state_t : ald_can.h
  • CAN_STATE_TIMEOUT : ald_can.h
  • CAN_STATE_TX_MASK : ald_can.h
  • CAN_TIMEOUT_VALUE : ald_can.h
  • CAN_TX_MAILBOX_0 : ald_can.h
  • CAN_TX_MAILBOX_1 : ald_can.h
  • CAN_TX_MAILBOX_2 : ald_can.h
  • CAN_TX_MAILBOX_NONE : ald_can.h
  • can_tx_mailbox_t : ald_can.h
  • CAN_TX_STAMP_DISABLE : ald_can.h
  • CAN_TX_STAMP_ENABLE : ald_can.h
  • CCER_CCxE_MASK : ald_timer.h
  • CCER_CCxNE_MASK : ald_timer.h
  • CFI1_ADDRESS : ald_nor_lcd.h
  • CFI2_ADDRESS : ald_nor_lcd.h
  • CFI3_ADDRESS : ald_nor_lcd.h
  • CFI4_ADDRESS : ald_nor_lcd.h
  • CLEAR_BIT : type.h
  • CLEAR_REG : type.h
  • CMD_AREA : ald_nand.h
  • cmu_bus_t : ald_cmu.h
  • CMU_BUZZ_DIV_128 : ald_cmu.h
  • CMU_BUZZ_DIV_16 : ald_cmu.h
  • CMU_BUZZ_DIV_2 : ald_cmu.h
  • CMU_BUZZ_DIV_256 : ald_cmu.h
  • CMU_BUZZ_DIV_32 : ald_cmu.h
  • CMU_BUZZ_DIV_4 : ald_cmu.h
  • CMU_BUZZ_DIV_64 : ald_cmu.h
  • CMU_BUZZ_DIV_8 : ald_cmu.h
  • cmu_buzz_div_t : ald_cmu.h
  • CMU_CLOCK_HOSC : ald_cmu.h
  • CMU_CLOCK_HRC : ald_cmu.h
  • CMU_CLOCK_LOSC : ald_cmu.h
  • CMU_CLOCK_LRC : ald_cmu.h
  • CMU_CLOCK_PLL1 : ald_cmu.h
  • cmu_clock_safe_type_t : ald_cmu.h
  • CMU_CLOCK_STATE_HOSCACT : ald_cmu.h
  • CMU_CLOCK_STATE_HOSCRDY : ald_cmu.h
  • CMU_CLOCK_STATE_HRCACT : ald_cmu.h
  • CMU_CLOCK_STATE_HRCRDY : ald_cmu.h
  • CMU_CLOCK_STATE_LOSCACT : ald_cmu.h
  • CMU_CLOCK_STATE_LOSCRDY : ald_cmu.h
  • CMU_CLOCK_STATE_LRCACT : ald_cmu.h
  • CMU_CLOCK_STATE_LRCRDY : ald_cmu.h
  • CMU_CLOCK_STATE_PLL1ACT : ald_cmu.h
  • CMU_CLOCK_STATE_PLL1RDY : ald_cmu.h
  • CMU_CLOCK_STATE_PLL2ACT : ald_cmu.h
  • CMU_CLOCK_STATE_PLL2RDY : ald_cmu.h
  • cmu_clock_state_t : ald_cmu.h
  • CMU_CLOCK_STATE_ULRCACT : ald_cmu.h
  • cmu_clock_t : ald_cmu.h
  • cmu_clock_update() : ald_cmu.c
  • CMU_DIV_1 : ald_cmu.h
  • CMU_DIV_1024 : ald_cmu.h
  • CMU_DIV_128 : ald_cmu.h
  • CMU_DIV_16 : ald_cmu.h
  • CMU_DIV_2 : ald_cmu.h
  • CMU_DIV_2048 : ald_cmu.h
  • CMU_DIV_256 : ald_cmu.h
  • CMU_DIV_32 : ald_cmu.h
  • CMU_DIV_4 : ald_cmu.h
  • CMU_DIV_4096 : ald_cmu.h
  • CMU_DIV_512 : ald_cmu.h
  • CMU_DIV_64 : ald_cmu.h
  • CMU_DIV_8 : ald_cmu.h
  • cmu_div_t : ald_cmu.h
  • CMU_HCLK_1 : ald_cmu.h
  • CMU_HCLK_2 : ald_cmu.h
  • CMU_HOSC_16M : ald_cmu.h
  • CMU_HOSC_24M : ald_cmu.h
  • CMU_HOSC_2M : ald_cmu.h
  • CMU_HOSC_4M : ald_cmu.h
  • CMU_HOSC_8M : ald_cmu.h
  • CMU_HOSC_DIV_1MHZ_DISABLE : ald_cmu.h
  • CMU_HOSC_DIV_1MHZ_ENABLE : ald_cmu.h
  • cmu_hosc_range_t : ald_cmu.h
  • CMU_HOSC_START : ald_cmu.h
  • CMU_HOSC_STOP : ald_cmu.h
  • CMU_HRC_DIV_1MHZ_DISABLE : ald_cmu.h
  • CMU_HRC_DIV_1MHZ_ENABLE : ald_cmu.h
  • CMU_HRC_SEL_BY_CFGW : ald_cmu.h
  • CMU_HRC_SEL_BY_SW : ald_cmu.h
  • cmu_lcd_clock_sel_t : ald_cmu.h
  • CMU_LCD_SEL_HOSC_1M : ald_cmu.h
  • CMU_LCD_SEL_HRC_1M : ald_cmu.h
  • CMU_LCD_SEL_LOSC : ald_cmu.h
  • CMU_LCD_SEL_LOSM : ald_cmu.h
  • CMU_LCD_SEL_LRC : ald_cmu.h
  • CMU_LCD_SEL_ULRC : ald_cmu.h
  • CMU_LOSC_DISABLE : ald_cmu.h
  • CMU_LOSC_ENABLE : ald_cmu.h
  • CMU_LOSC_START : ald_cmu.h
  • CMU_LOSC_STOP : ald_cmu.h
  • CMU_LP_HOSC_DISABLE : ald_cmu.h
  • CMU_LP_HOSC_ENABLE : ald_cmu.h
  • CMU_LP_HRC_DISABLE : ald_cmu.h
  • CMU_LP_HRC_ENABLE : ald_cmu.h
  • CMU_LP_LOSC_DISABLE : ald_cmu.h
  • CMU_LP_LOSC_ENABLE : ald_cmu.h
  • CMU_LP_LRC_DISABLE : ald_cmu.h
  • CMU_LP_LRC_ENABLE : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_HOSC : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_HOSC_1M : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_HOSM : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_HRC : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_HRC_1M : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_LOSC : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_LOSM : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_LRC : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_PCLK2 : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_PLL1 : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_PLL2 : ald_cmu.h
  • cmu_lp_perh_clock_sel_t : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_ULRC : ald_cmu.h
  • CMU_LRC_DISABLE : ald_cmu.h
  • CMU_LRC_ENABLE : ald_cmu.h
  • CMU_OUTPUT_DIV_1 : ald_cmu.h
  • CMU_OUTPUT_DIV_128 : ald_cmu.h
  • CMU_OUTPUT_DIV_16 : ald_cmu.h
  • CMU_OUTPUT_DIV_2 : ald_cmu.h
  • CMU_OUTPUT_DIV_32 : ald_cmu.h
  • CMU_OUTPUT_DIV_4 : ald_cmu.h
  • CMU_OUTPUT_DIV_64 : ald_cmu.h
  • CMU_OUTPUT_DIV_8 : ald_cmu.h
  • cmu_output_high_div_t : ald_cmu.h
  • CMU_OUTPUT_HIGH_SEL_HOSC : ald_cmu.h
  • CMU_OUTPUT_HIGH_SEL_HOSM : ald_cmu.h
  • CMU_OUTPUT_HIGH_SEL_HRC : ald_cmu.h
  • CMU_OUTPUT_HIGH_SEL_LOSC : ald_cmu.h
  • CMU_OUTPUT_HIGH_SEL_LRC : ald_cmu.h
  • CMU_OUTPUT_HIGH_SEL_PLL1 : ald_cmu.h
  • CMU_OUTPUT_HIGH_SEL_PLL2 : ald_cmu.h
  • CMU_OUTPUT_HIGH_SEL_SYSCLK : ald_cmu.h
  • cmu_output_high_sel_t : ald_cmu.h
  • CMU_OUTPUT_LOW_SEL_BUZZ : ald_cmu.h
  • CMU_OUTPUT_LOW_SEL_LOSC : ald_cmu.h
  • CMU_OUTPUT_LOW_SEL_LOSM : ald_cmu.h
  • CMU_OUTPUT_LOW_SEL_LRC : ald_cmu.h
  • cmu_output_low_sel_t : ald_cmu.h
  • CMU_OUTPUT_LOW_SEL_ULRC : ald_cmu.h
  • CMU_PCLK_1 : ald_cmu.h
  • CMU_PCLK_2 : ald_cmu.h
  • CMU_PERH_ACMP0 : ald_cmu.h
  • CMU_PERH_ACMP1 : ald_cmu.h
  • CMU_PERH_ACMP2 : ald_cmu.h
  • CMU_PERH_ADC0 : ald_cmu.h
  • CMU_PERH_ADC1 : ald_cmu.h
  • CMU_PERH_ALL : ald_cmu.h
  • CMU_PERH_BKPC : ald_cmu.h
  • CMU_PERH_CALC : ald_cmu.h
  • CMU_PERH_CAN : ald_cmu.h
  • CMU_PERH_CRC : ald_cmu.h
  • CMU_PERH_CRYPT : ald_cmu.h
  • CMU_PERH_DAC0 : ald_cmu.h
  • CMU_PERH_DBGC : ald_cmu.h
  • CMU_PERH_DMA : ald_cmu.h
  • CMU_PERH_EBI : ald_cmu.h
  • CMU_PERH_ECC : ald_cmu.h
  • CMU_PERH_GPIO : ald_cmu.h
  • CMU_PERH_I2C0 : ald_cmu.h
  • CMU_PERH_I2C1 : ald_cmu.h
  • CMU_PERH_IWDT : ald_cmu.h
  • CMU_PERH_LCD : ald_cmu.h
  • CMU_PERH_LPTIM0 : ald_cmu.h
  • CMU_PERH_LPUART0 : ald_cmu.h
  • CMU_PERH_OPAMP : ald_cmu.h
  • CMU_PERH_PIS : ald_cmu.h
  • CMU_PERH_QSPI_H : ald_cmu.h
  • CMU_PERH_QSPI_P : ald_cmu.h
  • CMU_PERH_RTC : ald_cmu.h
  • CMU_PERH_SPI0 : ald_cmu.h
  • CMU_PERH_SPI1 : ald_cmu.h
  • CMU_PERH_SPI2 : ald_cmu.h
  • cmu_perh_t : ald_cmu.h
  • CMU_PERH_TIMER0 : ald_cmu.h
  • CMU_PERH_TIMER1 : ald_cmu.h
  • CMU_PERH_TIMER2 : ald_cmu.h
  • CMU_PERH_TIMER3 : ald_cmu.h
  • CMU_PERH_TIMER4 : ald_cmu.h
  • CMU_PERH_TIMER5 : ald_cmu.h
  • CMU_PERH_TIMER6 : ald_cmu.h
  • CMU_PERH_TIMER7 : ald_cmu.h
  • CMU_PERH_TRNG : ald_cmu.h
  • CMU_PERH_TSENSE : ald_cmu.h
  • CMU_PERH_UART0 : ald_cmu.h
  • CMU_PERH_UART1 : ald_cmu.h
  • CMU_PERH_UART2 : ald_cmu.h
  • CMU_PERH_UART3 : ald_cmu.h
  • CMU_PERH_UART4 : ald_cmu.h
  • CMU_PERH_UART5 : ald_cmu.h
  • CMU_PERH_USB : ald_cmu.h
  • CMU_PERH_WWDT : ald_cmu.h
  • CMU_PLL1_INPUT_HOSC : ald_cmu.h
  • CMU_PLL1_INPUT_HOSC_2 : ald_cmu.h
  • CMU_PLL1_INPUT_HOSC_3 : ald_cmu.h
  • CMU_PLL1_INPUT_HOSC_4 : ald_cmu.h
  • CMU_PLL1_INPUT_HOSC_5 : ald_cmu.h
  • CMU_PLL1_INPUT_HOSC_6 : ald_cmu.h
  • CMU_PLL1_INPUT_HRC_6 : ald_cmu.h
  • CMU_PLL1_INPUT_PLL2 : ald_cmu.h
  • cmu_pll1_input_t : ald_cmu.h
  • CMU_PLL1_OUTPUT_36M : ald_cmu.h
  • CMU_PLL1_OUTPUT_48M : ald_cmu.h
  • cmu_pll1_output_t : ald_cmu.h
  • CMU_PLL1_UNLOCK : ald_cmu.h
  • CMU_QSPI_CLOCK_SEL_HCLK2 : ald_cmu.h
  • CMU_QSPI_CLOCK_SEL_HOSC : ald_cmu.h
  • CMU_QSPI_CLOCK_SEL_HOSM : ald_cmu.h
  • CMU_QSPI_CLOCK_SEL_HRC : ald_cmu.h
  • CMU_QSPI_CLOCK_SEL_PCLK1 : ald_cmu.h
  • CMU_QSPI_CLOCK_SEL_PLL1 : ald_cmu.h
  • cmu_qspi_clock_sel_t : ald_cmu.h
  • CMU_SAFE_CLK_HOSC : ald_cmu.h
  • CMU_SAFE_CLK_LOSC : ald_cmu.h
  • CMU_SAFE_CLK_PLL : ald_cmu.h
  • cmu_security_t : ald_cmu.h
  • CMU_STOP1_CLOCK_HOSC : ald_cmu.h
  • CMU_STOP1_CLOCK_HOSC_1M : ald_cmu.h
  • CMU_STOP1_CLOCK_HOSCM : ald_cmu.h
  • CMU_STOP1_CLOCK_HRC_1M : ald_cmu.h
  • CMU_STOP1_CLOCK_HRC_24M : ald_cmu.h
  • CMU_STOP1_CLOCK_HRC_2M : ald_cmu.h
  • CMU_STOP1_CLOCK_LRC : ald_cmu.h
  • cmu_stop1_clock_t : ald_cmu.h
  • CMU_SYS : ald_cmu.h
  • CMU_ULRC_DISABLE : ald_cmu.h
  • CMU_ULRC_ENABLE : ald_cmu.h
  • CMU_USB_CLOCK_SEL_HOSC : ald_cmu.h
  • CMU_USB_CLOCK_SEL_HOSM : ald_cmu.h
  • CMU_USB_CLOCK_SEL_HRC : ald_cmu.h
  • CMU_USB_CLOCK_SEL_PCLK1 : ald_cmu.h
  • CMU_USB_CLOCK_SEL_PLL1 : ald_cmu.h
  • cmu_usb_clock_sel_t : ald_cmu.h
  • CMU_USB_DIV_1 : ald_cmu.h
  • CMU_USB_DIV_1024 : ald_cmu.h
  • CMU_USB_DIV_128 : ald_cmu.h
  • CMU_USB_DIV_16 : ald_cmu.h
  • CMU_USB_DIV_2 : ald_cmu.h
  • CMU_USB_DIV_2048 : ald_cmu.h
  • CMU_USB_DIV_256 : ald_cmu.h
  • CMU_USB_DIV_32 : ald_cmu.h
  • CMU_USB_DIV_4 : ald_cmu.h
  • CMU_USB_DIV_4096 : ald_cmu.h
  • CMU_USB_DIV_512 : ald_cmu.h
  • CMU_USB_DIV_64 : ald_cmu.h
  • CMU_USB_DIV_8 : ald_cmu.h
  • cmu_usb_div_t : ald_cmu.h
  • COLUMN_1ST_CYCLE : ald_nand.h
  • COLUMN_2ND_CYCLE : ald_nand.h
  • COLUMN_ADDRESS : ald_nand.h
  • CRC_CLEAR_ERROR_FLAG : ald_crc.h
  • CRC_DATASIZE_16 : ald_crc.h
  • CRC_DATASIZE_32 : ald_crc.h
  • CRC_DATASIZE_8 : ald_crc.h
  • crc_datasize_t : ald_crc.h
  • CRC_DISABLE : ald_crc.h
  • crc_dma_calculate_cplt() : ald_crc.c
  • CRC_DMA_DISABLE : ald_crc.h
  • CRC_DMA_ENABLE : ald_crc.h
  • crc_dma_error() : ald_crc.c
  • CRC_ENABLE : ald_crc.h
  • crc_handle_t : ald_crc.h
  • CRC_LEN_AUTO : ald_crc.h
  • CRC_MODE_16 : ald_crc.h
  • CRC_MODE_32 : ald_crc.h
  • CRC_MODE_8 : ald_crc.h
  • CRC_MODE_CCITT : ald_crc.h
  • crc_mode_t : ald_crc.h
  • CRC_RESET : ald_crc.h
  • CRC_STATE_BUSY : ald_crc.h
  • CRC_STATE_ERROR : ald_crc.h
  • CRC_STATE_READY : ald_crc.h
  • CRC_STATE_RESET : ald_crc.h
  • crc_state_t : ald_crc.h
  • CRC_WERR_ERR : ald_crc.h
  • CRC_WERR_NO : ald_crc.h
  • crc_werr_t : ald_crc.h
  • CRYPT_AES_BITS_128 : ald_crypt.h
  • CRYPT_AES_BITS_192 : ald_crypt.h
  • CRYPT_AES_BITS_256 : ald_crypt.h
  • crypt_aesks_t : ald_crypt.h
  • CRYPT_BITS_128 : ald_crypt.h
  • CRYPT_BITS_192 : ald_crypt.h
  • CRYPT_BITS_256 : ald_crypt.h
  • CRYPT_CRYSEL_AES : ald_crypt.h
  • CRYPT_CRYSEL_DES : ald_crypt.h
  • crypt_crysel_t : ald_crypt.h
  • CRYPT_DATA_CHANGE_1 : ald_crypt.h
  • CRYPT_DATA_CHANGE_16 : ald_crypt.h
  • CRYPT_DATA_CHANGE_8 : ald_crypt.h
  • CRYPT_DATA_CHANGE_NO : ald_crypt.h
  • crypt_data_t : ald_crypt.h
  • crypt_datatype_t : ald_crypt.h
  • CRYPT_DECRYPT : ald_crypt.h
  • CRYPT_DES_KEYS_1 : ald_crypt.h
  • CRYPT_DES_KEYS_2 : ald_crypt.h
  • CRYPT_DES_KEYS_3 : ald_crypt.h
  • crypt_desks_t : ald_crypt.h
  • crypt_dma_crypt_cplt() : ald_crypt.c
  • CRYPT_DMA_DISABLE : ald_crypt.h
  • CRYPT_DMA_ENABLE : ald_crypt.h
  • crypt_dma_error() : ald_crypt.c
  • CRYPT_ENCRYPT : ald_crypt.h
  • crypt_encs_t : ald_crypt.h
  • CRYPT_FIFOEN_DISABLE : ald_crypt.h
  • CRYPT_FIFOEN_ENABLE : ald_crypt.h
  • CRYPT_FLAG_AESIF : ald_crypt.h
  • CRYPT_FLAG_DESIF : ald_crypt.h
  • CRYPT_FLAG_DONE : ald_crypt.h
  • crypt_flag_t : ald_crypt.h
  • CRYPT_GO : ald_crypt.h
  • crypt_handle_t : ald_crypt.h
  • CRYPT_IE_DISABLE : ald_crypt.h
  • CRYPT_IE_ENABLE : ald_crypt.h
  • CRYPT_IT_IT : ald_crypt.h
  • crypt_it_t : ald_crypt.h
  • CRYPT_IVEN_DISABLE : ald_crypt.h
  • CRYPT_IVEN_ENABLE : ald_crypt.h
  • crypt_ivr_len_t : ald_crypt.h
  • crypt_key_len_t : ald_crypt.h
  • CRYPT_KEYS_1 : ald_crypt.h
  • CRYPT_KEYS_2 : ald_crypt.h
  • CRYPT_KEYS_3 : ald_crypt.h
  • crypt_ks_t : ald_crypt.h
  • CRYPT_MODE_CBC : ald_crypt.h
  • CRYPT_MODE_CTR : ald_crypt.h
  • CRYPT_MODE_ECB : ald_crypt.h
  • crypt_mode_t : ald_crypt.h
  • CRYPT_READ_FIFO : ald_crypt.h
  • crypt_reset() : ald_crypt.c
  • CRYPT_SETDIR : ald_crypt.h
  • CRYPT_STATE_BUSY : ald_crypt.h
  • CRYPT_STATE_ERROR : ald_crypt.h
  • CRYPT_STATE_READY : ald_crypt.h
  • CRYPT_STATE_RESET : ald_crypt.h
  • crypt_state_t : ald_crypt.h
  • CRYPT_WRITE_FIFO : ald_crypt.h


ALD User Manual: Globals

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- d -

  • DAC_CH0_BSY : ald_dac.h
  • DAC_CH0_DISABLE : ald_dac.h
  • DAC_CH0_ENABLE : ald_dac.h
  • DAC_CH1_BSY : ald_dac.h
  • DAC_CH1_DISABLE : ald_dac.h
  • DAC_CH1_ENABLE : ald_dac.h
  • DAC_CHANNEL_0 : ald_dac.h
  • DAC_CHANNEL_1 : ald_dac.h
  • DAC_CHANNEL_COMB : ald_dac.h
  • dac_channel_t : ald_dac.h
  • DAC_CONV_MODE_CONTINUOUS : ald_dac.h
  • DAC_CONV_MODE_SAMPLEHOLD : ald_dac.h
  • DAC_CONV_MODE_SAMPLEOFF : ald_dac.h
  • dac_conv_mode_t : ald_dac.h
  • DAC_EVENT_CH0_CPLT : ald_dac.h
  • DAC_EVENT_CH0_UF : ald_dac.h
  • DAC_EVENT_CH1_CPLT : ald_dac.h
  • DAC_EVENT_CH1_UF : ald_dac.h
  • DAC_FLAG_CH0 : ald_dac.h
  • DAC_FLAG_CH0_UF : ald_dac.h
  • DAC_FLAG_CH1 : ald_dac.h
  • DAC_FLAG_CH1_UF : ald_dac.h
  • dac_flag_t : ald_dac.h
  • dac_handle_t : ald_dac.h
  • DAC_IT_CH0 : ald_dac.h
  • DAC_IT_CH0_UF : ald_dac.h
  • DAC_IT_CH1 : ald_dac.h
  • DAC_IT_CH1_UF : ald_dac.h
  • dac_it_t : ald_dac.h
  • dac_neg_ref_t : ald_dac.h
  • DAC_NEG_REF_VREFN : ald_dac.h
  • DAC_NEG_REF_VSS : ald_dac.h
  • dac_out_mode_t : ald_dac.h
  • DAC_OUTPUT_ADC : ald_dac.h
  • DAC_OUTPUT_DISABLE : ald_dac.h
  • DAC_OUTPUT_PIN : ald_dac.h
  • DAC_OUTPUT_PIN_ADC : ald_dac.h
  • DAC_PIS_CH_0 : ald_dac.h
  • DAC_PIS_CH_1 : ald_dac.h
  • DAC_PIS_CH_10 : ald_dac.h
  • DAC_PIS_CH_11 : ald_dac.h
  • DAC_PIS_CH_2 : ald_dac.h
  • DAC_PIS_CH_3 : ald_dac.h
  • DAC_PIS_CH_4 : ald_dac.h
  • DAC_PIS_CH_5 : ald_dac.h
  • DAC_PIS_CH_6 : ald_dac.h
  • DAC_PIS_CH_7 : ald_dac.h
  • DAC_PIS_CH_8 : ald_dac.h
  • DAC_PIS_CH_9 : ald_dac.h
  • dac_pissel_t : ald_dac.h
  • DAC_POS_REF_2V : ald_dac.h
  • dac_pos_ref_t : ald_dac.h
  • DAC_POS_REF_VDD : ald_dac.h
  • DAC_POS_REF_VREEFP : ald_dac.h
  • DAC_POS_REF_VREEFP_BUF : ald_dac.h
  • DAC_PRES_DIV_1 : ald_dac.h
  • DAC_PRES_DIV_128 : ald_dac.h
  • DAC_PRES_DIV_16 : ald_dac.h
  • DAC_PRES_DIV_2 : ald_dac.h
  • DAC_PRES_DIV_32 : ald_dac.h
  • DAC_PRES_DIV_4 : ald_dac.h
  • DAC_PRES_DIV_64 : ald_dac.h
  • DAC_PRES_DIV_8 : ald_dac.h
  • dac_prescale_div_t : ald_dac.h
  • DAC_REFRESH_16 : ald_dac.h
  • DAC_REFRESH_32 : ald_dac.h
  • DAC_REFRESH_64 : ald_dac.h
  • DAC_REFRESH_8 : ald_dac.h
  • dac_refresh_t : ald_dac.h
  • dac_status_t : ald_dac.h
  • DAC_TRIGGER_BY_DATA : ald_dac.h
  • DAC_TRIGGER_BY_PIS : ald_dac.h
  • dac_trigger_t : ald_dac.h
  • DATA_16_BIT : ald_crypt.h
  • DATA_1_BIT : ald_crypt.h
  • DATA_32_BIT : ald_crypt.h
  • DATA_8_BIT : ald_crypt.h
  • dbgc_mode_t : ald_dbgc.h
  • dbgc_perh_t : ald_dbgc.h
  • DEBC_MODE_SLEEP : ald_dbgc.h
  • DEBC_MODE_STANDBY : ald_dbgc.h
  • DEBC_MODE_STOP1 : ald_dbgc.h
  • DEBC_MODE_STOP2 : ald_dbgc.h
  • DEBC_PERH_CAN : ald_dbgc.h
  • DEBC_PERH_I2C0 : ald_dbgc.h
  • DEBC_PERH_I2C1 : ald_dbgc.h
  • DEBC_PERH_IWDT : ald_dbgc.h
  • DEBC_PERH_LPTIM0 : ald_dbgc.h
  • DEBC_PERH_RTC : ald_dbgc.h
  • DEBC_PERH_TIMER0 : ald_dbgc.h
  • DEBC_PERH_TIMER1 : ald_dbgc.h
  • DEBC_PERH_TIMER2 : ald_dbgc.h
  • DEBC_PERH_TIMER3 : ald_dbgc.h
  • DEBC_PERH_TIMER4 : ald_dbgc.h
  • DEBC_PERH_TIMER5 : ald_dbgc.h
  • DEBC_PERH_TIMER6 : ald_dbgc.h
  • DEBC_PERH_TIMER7 : ald_dbgc.h
  • DEBC_PERH_WWDT : ald_dbgc.h
  • dec_to_bcd() : ald_rtc.c
  • delay_losc_clk() : ald_rtchw.c
  • DEM_CR : utils.h
  • DEM_CR_TRCENA : utils.h
  • DEVICE_CODE1_ADDR : ald_nor_lcd.h
  • DEVICE_CODE2_ADDR : ald_nor_lcd.h
  • DEVICE_CODE3_ADDR : ald_nor_lcd.h
  • DISABLE : type.h
  • DISABLE_NAK_LIMIT : ald_usb.h
  • dma0_cbk : ald_dma.c
  • dma_arbiter_config_t : ald_dma.h
  • DMA_CH_COUNT : ald_dma.h
  • dma_config_base() : ald_dma.c
  • DMA_CYCLE_CTRL_AUTO : ald_dma.h
  • DMA_CYCLE_CTRL_BASIC : ald_dma.h
  • DMA_CYCLE_CTRL_MEM_SG_ALTERNATE : ald_dma.h
  • DMA_CYCLE_CTRL_MEM_SG_PRIMARY : ald_dma.h
  • DMA_CYCLE_CTRL_NONE : ald_dma.h
  • DMA_CYCLE_CTRL_PER_SG_ALTERNATE : ald_dma.h
  • DMA_CYCLE_CTRL_PER_SG_PRIMARY : ald_dma.h
  • DMA_CYCLE_CTRL_PINGPONG : ald_dma.h
  • dma_cycle_ctrl_t : ald_dma.h
  • DMA_DATA_INC_BYTE : ald_dma.h
  • DMA_DATA_INC_HALFWORD : ald_dma.h
  • DMA_DATA_INC_NONE : ald_dma.h
  • dma_data_inc_t : ald_dma.h
  • DMA_DATA_INC_WORD : ald_dma.h
  • DMA_DATA_SIZE_BYTE : ald_dma.h
  • DMA_DATA_SIZE_HALFWORD : ald_dma.h
  • dma_data_size_t : ald_dma.h
  • DMA_DATA_SIZE_WORD : ald_dma.h
  • DMA_DESCP_CPLT_ALL : ald_dma.h
  • DMA_DESCP_CPLT_ALT : ald_dma.h
  • DMA_DESCP_CPLT_PRI : ald_dma.h
  • dma_descrp_cplt_t : ald_dma.h
  • DMA_ERR : ald_dma.h
  • DMA_MSEL_ADC0 : ald_dma.h
  • DMA_MSEL_ADC1 : ald_dma.h
  • DMA_MSEL_CRC : ald_dma.h
  • DMA_MSEL_CRYPT : ald_dma.h
  • DMA_MSEL_DAC0 : ald_dma.h
  • DMA_MSEL_GPIO : ald_dma.h
  • DMA_MSEL_I2C0 : ald_dma.h
  • DMA_MSEL_I2C1 : ald_dma.h
  • DMA_MSEL_LPUART0 : ald_dma.h
  • DMA_MSEL_NONE : ald_dma.h
  • DMA_MSEL_PIS : ald_dma.h
  • DMA_MSEL_QSPI : ald_dma.h
  • DMA_MSEL_SPI0 : ald_dma.h
  • DMA_MSEL_SPI1 : ald_dma.h
  • DMA_MSEL_SPI2 : ald_dma.h
  • dma_msel_t : ald_dma.h
  • DMA_MSEL_TIMER0 : ald_dma.h
  • DMA_MSEL_TIMER1 : ald_dma.h
  • DMA_MSEL_TIMER2 : ald_dma.h
  • DMA_MSEL_TIMER3 : ald_dma.h
  • DMA_MSEL_TIMER4 : ald_dma.h
  • DMA_MSEL_TIMER5 : ald_dma.h
  • DMA_MSEL_TIMER6 : ald_dma.h
  • DMA_MSEL_TIMER7 : ald_dma.h
  • DMA_MSEL_TRNG : ald_dma.h
  • DMA_MSEL_UART0 : ald_dma.h
  • DMA_MSEL_UART1 : ald_dma.h
  • DMA_MSEL_UART2 : ald_dma.h
  • DMA_MSEL_UART3 : ald_dma.h
  • DMA_MSEL_UART4 : ald_dma.h
  • DMA_MSEL_UART5 : ald_dma.h
  • DMA_MSEL_USB : ald_dma.h
  • DMA_MSIGSEL_ADC : ald_dma.h
  • DMA_MSIGSEL_CRYPT_READ : ald_dma.h
  • DMA_MSIGSEL_CRYPT_WRITE : ald_dma.h
  • DMA_MSIGSEL_DAC0_CH0 : ald_dma.h
  • DMA_MSIGSEL_DAC0_CH1 : ald_dma.h
  • DMA_MSIGSEL_EP_RX1 : ald_dma.h
  • DMA_MSIGSEL_EP_RX2 : ald_dma.h
  • DMA_MSIGSEL_EP_RX3 : ald_dma.h
  • DMA_MSIGSEL_EP_RX4 : ald_dma.h
  • DMA_MSIGSEL_EP_RX5 : ald_dma.h
  • DMA_MSIGSEL_EP_TX1 : ald_dma.h
  • DMA_MSIGSEL_EP_TX2 : ald_dma.h
  • DMA_MSIGSEL_EP_TX3 : ald_dma.h
  • DMA_MSIGSEL_EP_TX4 : ald_dma.h
  • DMA_MSIGSEL_EP_TX5 : ald_dma.h
  • DMA_MSIGSEL_EXTI_0 : ald_dma.h
  • DMA_MSIGSEL_EXTI_1 : ald_dma.h
  • DMA_MSIGSEL_EXTI_10 : ald_dma.h
  • DMA_MSIGSEL_EXTI_11 : ald_dma.h
  • DMA_MSIGSEL_EXTI_12 : ald_dma.h
  • DMA_MSIGSEL_EXTI_13 : ald_dma.h
  • DMA_MSIGSEL_EXTI_14 : ald_dma.h
  • DMA_MSIGSEL_EXTI_15 : ald_dma.h
  • DMA_MSIGSEL_EXTI_2 : ald_dma.h
  • DMA_MSIGSEL_EXTI_3 : ald_dma.h
  • DMA_MSIGSEL_EXTI_4 : ald_dma.h
  • DMA_MSIGSEL_EXTI_5 : ald_dma.h
  • DMA_MSIGSEL_EXTI_6 : ald_dma.h
  • DMA_MSIGSEL_EXTI_7 : ald_dma.h
  • DMA_MSIGSEL_EXTI_8 : ald_dma.h
  • DMA_MSIGSEL_EXTI_9 : ald_dma.h
  • DMA_MSIGSEL_I2C_RNR : ald_dma.h
  • DMA_MSIGSEL_I2C_TXEMPTY : ald_dma.h
  • DMA_MSIGSEL_LPUART_RNR : ald_dma.h
  • DMA_MSIGSEL_LPUART_TXEMPTY : ald_dma.h
  • DMA_MSIGSEL_NONE : ald_dma.h
  • DMA_MSIGSEL_PIS_CH0 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH1 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH10 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH11 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH12 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH13 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH14 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH15 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH2 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH3 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH4 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH5 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH6 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH7 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH8 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH9 : ald_dma.h
  • DMA_MSIGSEL_QSPI_READ : ald_dma.h
  • DMA_MSIGSEL_QSPI_WRITE : ald_dma.h
  • DMA_MSIGSEL_SPI_RNR : ald_dma.h
  • DMA_MSIGSEL_SPI_TXEMPTY : ald_dma.h
  • dma_msigsel_t : ald_dma.h
  • DMA_MSIGSEL_TIMER_CH1 : ald_dma.h
  • DMA_MSIGSEL_TIMER_CH2 : ald_dma.h
  • DMA_MSIGSEL_TIMER_CH3 : ald_dma.h
  • DMA_MSIGSEL_TIMER_CH4 : ald_dma.h
  • DMA_MSIGSEL_TIMER_COMP : ald_dma.h
  • DMA_MSIGSEL_TIMER_TRI : ald_dma.h
  • DMA_MSIGSEL_TIMER_UPDATE : ald_dma.h
  • DMA_MSIGSEL_UART45_RNR : ald_dma.h
  • DMA_MSIGSEL_UART45_TXEMPTY : ald_dma.h
  • DMA_MSIGSEL_UART_RNR : ald_dma.h
  • DMA_MSIGSEL_UART_TXEMPTY : ald_dma.h
  • DMA_R_POWER_1 : ald_dma.h
  • DMA_R_POWER_1024 : ald_dma.h
  • DMA_R_POWER_128 : ald_dma.h
  • DMA_R_POWER_16 : ald_dma.h
  • DMA_R_POWER_2 : ald_dma.h
  • DMA_R_POWER_256 : ald_dma.h
  • DMA_R_POWER_32 : ald_dma.h
  • DMA_R_POWER_4 : ald_dma.h
  • DMA_R_POWER_512 : ald_dma.h
  • DMA_R_POWER_64 : ald_dma.h
  • DMA_R_POWER_8 : ald_dma.h
  • DWT_CR : utils.h
  • DWT_CR_CYCCNTEA : utils.h
  • DWT_CYCCNT : utils.h


ALD User Manual: Globals

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- e -

  • EBI_ACCESS_MODE_A : ald_ebi.h
  • EBI_ACCESS_MODE_B : ald_ebi.h
  • EBI_ACCESS_MODE_C : ald_ebi.h
  • EBI_ACCESS_MODE_D : ald_ebi.h
  • ebi_access_mode_t : ald_ebi.h
  • EBI_ASYNCHRONOUS_WAIT_DISABLE : ald_ebi.h
  • EBI_ASYNCHRONOUS_WAIT_ENABLE : ald_ebi.h
  • ebi_asynchronous_wait_t : ald_ebi.h
  • EBI_BURST_ACCESS_MODE_DISABLE : ald_ebi.h
  • EBI_BURST_ACCESS_MODE_ENABLE : ald_ebi.h
  • ebi_burst_access_mode_t : ald_ebi.h
  • EBI_DATA_ADDRESS_MUX_DISABLE : ald_ebi.h
  • EBI_DATA_ADDRESS_MUX_ENABLE : ald_ebi.h
  • ebi_data_address_mux_t : ald_ebi.h
  • EBI_EXTENDED_MODE_DISABLE : ald_ebi.h
  • EBI_EXTENDED_MODE_ENABLE : ald_ebi.h
  • ebi_extended_mode_t : ald_ebi.h
  • EBI_FLAG_FALLING_EDGE : ald_ebi.h
  • EBI_FLAG_FEMPT : ald_ebi.h
  • EBI_FLAG_LEVEL : ald_ebi.h
  • EBI_FLAG_RISING_EDGE : ald_ebi.h
  • ebi_flag_t : ald_ebi.h
  • EBI_IT_FALLING_EDGE : ald_ebi.h
  • EBI_IT_LEVEL : ald_ebi.h
  • EBI_IT_RISING_EDGE : ald_ebi.h
  • ebi_it_t : ald_ebi.h
  • EBI_LCD_DCLKPOL_FALLING : ald_ebi.h
  • EBI_LCD_DCLKPOL_RISING : ald_ebi.h
  • ebi_lcd_dclkpol_t : ald_ebi.h
  • EBI_LCD_DENPOL_HIGH : ald_ebi.h
  • EBI_LCD_DENPOL_LOW : ald_ebi.h
  • ebi_lcd_denpol_t : ald_ebi.h
  • EBI_LCD_DEVICE : ald_ebi.h
  • EBI_LCD_HSYNCPOL_HIGH : ald_ebi.h
  • EBI_LCD_HSYNCPOL_LOW : ald_ebi.h
  • ebi_lcd_hsyncpol_t : ald_ebi.h
  • EBI_LCD_LCDEN_DISABLE : ald_ebi.h
  • EBI_LCD_LCDEN_ENABLE : ald_ebi.h
  • ebi_lcd_lcden_t : ald_ebi.h
  • EBI_LCD_LCDINT_DISABLE : ald_ebi.h
  • EBI_LCD_LCDINT_ENABLE : ald_ebi.h
  • ebi_lcd_lcdint_t : ald_ebi.h
  • EBI_LCD_TypeDef : ald_ebi.h
  • EBI_LCD_VSYNCPOL_HIGH : ald_ebi.h
  • EBI_LCD_VSYNCPOL_LOW : ald_ebi.h
  • ebi_lcd_vsyncpol_t : ald_ebi.h
  • ebi_md_ecc_page_size_t : ald_ebi.h
  • EBI_MEMORY_TYPE_NOR : ald_ebi.h
  • EBI_MEMORY_TYPE_PSRAM : ald_ebi.h
  • EBI_MEMORY_TYPE_SRAM : ald_ebi.h
  • ebi_memory_type_t : ald_ebi.h
  • EBI_NAND_BANK2 : ald_ebi.h
  • EBI_NAND_BANK3 : ald_ebi.h
  • EBI_NAND_DEVICE : ald_ebi.h
  • EBI_NAND_ECC_DISABLE : ald_ebi.h
  • EBI_NAND_ECC_ENABLE : ald_ebi.h
  • EBI_NAND_ECC_PAGE_SIZE_1024BYTE : ald_ebi.h
  • EBI_NAND_ECC_PAGE_SIZE_2048BYTE : ald_ebi.h
  • EBI_NAND_ECC_PAGE_SIZE_256BYTE : ald_ebi.h
  • EBI_NAND_ECC_PAGE_SIZE_4096BYTE : ald_ebi.h
  • EBI_NAND_ECC_PAGE_SIZE_512BYTE : ald_ebi.h
  • EBI_NAND_ECC_PAGE_SIZE_8192BYTE : ald_ebi.h
  • ebi_nand_ecc_t : ald_ebi.h
  • EBI_NAND_MEM_BUS_WIDTH_16 : ald_ebi.h
  • EBI_NAND_MEM_BUS_WIDTH_8 : ald_ebi.h
  • ebi_nand_mem_bus_width_t : ald_ebi.h
  • EBI_NAND_TypeDef : ald_ebi.h
  • EBI_NAND_WAIT_FEATURE_DISABLE : ald_ebi.h
  • EBI_NAND_WAIT_FEATURE_ENABLE : ald_ebi.h
  • ebi_nand_wait_feature_t : ald_ebi.h
  • EBI_NOR_SRAM_DEVICE : ald_ebi.h
  • EBI_NOR_SRAM_EXTENDED_DEVICE : ald_ebi.h
  • EBI_NOR_SRAM_EXTENDED_TypeDef : ald_ebi.h
  • EBI_NOR_SRAM_TypeDef : ald_ebi.h
  • EBI_NORSRAM_BANK1 : ald_ebi.h
  • EBI_NORSRAM_BANK2 : ald_ebi.h
  • EBI_NORSRAM_BANK3 : ald_ebi.h
  • EBI_NORSRAM_BANK4 : ald_ebi.h
  • ebi_norsram_bank_t : ald_ebi.h
  • EBI_NORSRAM_FLASH_ACCESS_DISABLE : ald_ebi.h
  • EBI_NORSRAM_FLASH_ACCESS_ENABLE : ald_ebi.h
  • ebi_norsram_flash_access_t : ald_ebi.h
  • EBI_NORSRAM_MEM_BUS_WIDTH_16 : ald_ebi.h
  • EBI_NORSRAM_MEM_BUS_WIDTH_32 : ald_ebi.h
  • EBI_NORSRAM_MEM_BUS_WIDTH_8 : ald_ebi.h
  • ebi_norsram_mem_bus_width_t : ald_ebi.h
  • EBI_PCTRLR_MEMORY_TYPE_NAND : ald_ebi.h
  • EBI_PCTRLR_MEMORY_TYPE_None : ald_ebi.h
  • ebi_pctrlr_memory_type_t : ald_ebi.h
  • EBI_WAIT_SIGNAL_DISABLE : ald_ebi.h
  • EBI_WAIT_SIGNAL_ENABLE : ald_ebi.h
  • EBI_WAIT_SIGNAL_POLARITY_HIGH : ald_ebi.h
  • EBI_WAIT_SIGNAL_POLARITY_LOW : ald_ebi.h
  • ebi_wait_signal_polarity_t : ald_ebi.h
  • ebi_wait_signal_t : ald_ebi.h
  • EBI_WAIT_TIMING_BEFORE_WS : ald_ebi.h
  • EBI_WAIT_TIMING_DURING_WS : ald_ebi.h
  • ebi_wait_timing_t : ald_ebi.h
  • EBI_WRAP_MODE_DISABLE : ald_ebi.h
  • EBI_WRAP_MODE_ENABLE : ald_ebi.h
  • ebi_wrap_mode_t : ald_ebi.h
  • EBI_WRITE_BURST_DISABLE : ald_ebi.h
  • EBI_WRITE_BURST_ENABLE : ald_ebi.h
  • ebi_write_burst_t : ald_ebi.h
  • EBI_WRITE_OPERATION_DISABLE : ald_ebi.h
  • EBI_WRITE_OPERATION_ENABLE : ald_ebi.h
  • ebi_write_operation_t : ald_ebi.h
  • ENABLE : type.h
  • ERROR : utils.h
  • EXTI_FILTER_CLOCK_10K : ald_gpio.h
  • EXTI_FILTER_CLOCK_32K : ald_gpio.h
  • exti_filter_clock_t : ald_gpio.h
  • EXTI_TRIGGER_BOTH_EDGE : ald_gpio.h
  • EXTI_TRIGGER_RISING_EDGE : ald_gpio.h
  • exti_trigger_style_t : ald_gpio.h
  • EXTI_TRIGGER_TRAILING_EDGE : ald_gpio.h


ALD User Manual: Globals

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- f -

  • FALSE : type.h
  • flag_status_t : type.h
  • FLASH_BASE_ADDR : ald_flash.h
  • FLASH_CMD_AE : ald_flash.h
  • FLASH_CMD_DATAPE : ald_flash.h
  • FLASH_CMD_DATAWP : ald_flash.h
  • FLASH_CMD_DATAWP_FAST : ald_flash.h
  • FLASH_CMD_NP_AE : ald_flash.h
  • FLASH_CMD_PE : ald_flash.h
  • flash_cmd_type : ald_flash.h
  • FLASH_CMD_WP : ald_flash.h
  • FLASH_CMD_WP_FAST : ald_flash.h
  • FLASH_FIFO : ald_flash.h
  • FLASH_IAP_DISABLE : ald_flash.h
  • FLASH_IAP_ENABLE : ald_flash.h
  • flash_lock() : ald_flash.c
  • FLASH_PAGE_ADDR : ald_flash.h
  • flash_page_erase() : ald_flash.c
  • FLASH_PAGE_MASK : ald_flash.h
  • FLASH_PAGE_SIZE : ald_flash.h
  • FLASH_PAGEEND_ADDR : ald_flash.h
  • FLASH_REG_UNLOCK : ald_flash.h
  • FLASH_REQ : ald_flash.h
  • FLASH_REQ_FIN : ald_flash.h
  • FLASH_TOTAL_SIZE : ald_flash.h
  • flash_unlock() : ald_flash.c
  • FLASH_WORD_ADDR : ald_flash.h
  • FLASH_WORD_MASK : ald_flash.h
  • flash_word_program() : ald_flash.c
  • FLASH_WORD_SIZE : ald_flash.h
  • FLASH_WORDEND_ADDR : ald_flash.h


ALD User Manual: Globals

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- g -

  • gcm_mul() : ald_crypt.c
  • GET_SYSCFG_LOCK : ald_syscfg.h
  • GPIO_FILTER_DISABLE : ald_gpio.h
  • GPIO_FILTER_ENABLE : ald_gpio.h
  • gpio_filter_t : ald_gpio.h
  • GPIO_FLOATING : ald_gpio.h
  • GPIO_FUNC_0 : ald_gpio.h
  • GPIO_FUNC_1 : ald_gpio.h
  • GPIO_FUNC_2 : ald_gpio.h
  • GPIO_FUNC_3 : ald_gpio.h
  • GPIO_FUNC_4 : ald_gpio.h
  • GPIO_FUNC_5 : ald_gpio.h
  • GPIO_FUNC_6 : ald_gpio.h
  • GPIO_FUNC_7 : ald_gpio.h
  • gpio_func_t : ald_gpio.h
  • GPIO_MODE_CLOSE : ald_gpio.h
  • GPIO_MODE_INPUT : ald_gpio.h
  • GPIO_MODE_OUTPUT : ald_gpio.h
  • gpio_mode_t : ald_gpio.h
  • gpio_odos_t : ald_gpio.h
  • GPIO_OPEN_DRAIN : ald_gpio.h
  • GPIO_OPEN_SOURCE : ald_gpio.h
  • GPIO_OUT_DRIVE_0_1 : ald_gpio.h
  • GPIO_OUT_DRIVE_1 : ald_gpio.h
  • GPIO_OUT_DRIVE_20 : ald_gpio.h
  • GPIO_OUT_DRIVE_6 : ald_gpio.h
  • gpio_out_drive_t : ald_gpio.h
  • GPIO_PIN_0 : ald_gpio.h
  • GPIO_PIN_1 : ald_gpio.h
  • GPIO_PIN_10 : ald_gpio.h
  • GPIO_PIN_11 : ald_gpio.h
  • GPIO_PIN_12 : ald_gpio.h
  • GPIO_PIN_13 : ald_gpio.h
  • GPIO_PIN_14 : ald_gpio.h
  • GPIO_PIN_15 : ald_gpio.h
  • GPIO_PIN_2 : ald_gpio.h
  • GPIO_PIN_3 : ald_gpio.h
  • GPIO_PIN_4 : ald_gpio.h
  • GPIO_PIN_5 : ald_gpio.h
  • GPIO_PIN_6 : ald_gpio.h
  • GPIO_PIN_7 : ald_gpio.h
  • GPIO_PIN_8 : ald_gpio.h
  • GPIO_PIN_9 : ald_gpio.h
  • GPIO_PIN_ALL : ald_gpio.h
  • GPIO_PUSH_DOWN : ald_gpio.h
  • GPIO_PUSH_PULL : ald_gpio.h
  • gpio_push_t : ald_gpio.h
  • GPIO_PUSH_UP : ald_gpio.h
  • GPIO_PUSH_UP_DOWN : ald_gpio.h
  • GPIO_TYPE_CMOS : ald_gpio.h
  • gpio_type_t : ald_gpio.h
  • GPIO_TYPE_TTL : ald_gpio.h


ALD User Manual: Globals

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- i -

  • i2c_addr1_t : ald_i2c.h
  • i2c_addr2_t : ald_i2c.h
  • I2C_ADDR_10BIT : ald_i2c.h
  • I2C_ADDR_7BIT : ald_i2c.h
  • i2c_addr_size_t : ald_i2c.h
  • i2c_addr_t : ald_i2c.h
  • I2C_CLEAR_IT : ald_i2c.h
  • i2c_clock_t : ald_i2c.h
  • I2C_CON1_ALERTEN : ald_i2c.h
  • I2C_CON1_GCEN : ald_i2c.h
  • I2C_CON1_NOSTRETCH : ald_i2c.h
  • I2C_CON1_PE : ald_i2c.h
  • I2C_CON1_PECEN : ald_i2c.h
  • I2C_CON1_RXDMA : ald_i2c.h
  • I2C_CON1_SBC : ald_i2c.h
  • I2C_CON1_SMBDEN : ald_i2c.h
  • I2C_CON1_SMBHEN : ald_i2c.h
  • i2c_con1_t : ald_i2c.h
  • I2C_CON1_TXDMA : ald_i2c.h
  • I2C_CON2_ADD10 : ald_i2c.h
  • I2C_CON2_AUTOEND : ald_i2c.h
  • I2C_CON2_HEAD10R : ald_i2c.h
  • I2C_CON2_HOLDACK : ald_i2c.h
  • I2C_CON2_NACK : ald_i2c.h
  • I2C_CON2_PECBYTE : ald_i2c.h
  • I2C_CON2_RD_WRN : ald_i2c.h
  • I2C_CON2_RELOAD : ald_i2c.h
  • I2C_CON2_START : ald_i2c.h
  • I2C_CON2_STOP : ald_i2c.h
  • i2c_con2_t : ald_i2c.h
  • I2C_DISABLE : ald_i2c.h
  • I2C_DISABLE_IT : ald_i2c.h
  • i2c_dma_error() : ald_i2c.c
  • i2c_dma_master_recv_cplt() : ald_i2c.c
  • i2c_dma_master_send_cplt() : ald_i2c.c
  • i2c_dma_mem_recv_cplt() : ald_i2c.c
  • i2c_dma_mem_send_cplt() : ald_i2c.c
  • i2c_dma_slave_recv_cplt() : ald_i2c.c
  • i2c_dma_slave_send_cplt() : ald_i2c.c
  • i2c_dual_addr_t : ald_i2c.h
  • I2C_DUALADDR_DISABLE : ald_i2c.h
  • I2C_DUALADDR_ENABLE : ald_i2c.h
  • I2C_ENABLE : ald_i2c.h
  • I2C_ENABLE_IT : ald_i2c.h
  • I2C_ERROR_AF : ald_i2c.h
  • I2C_ERROR_ARLO : ald_i2c.h
  • I2C_ERROR_BERR : ald_i2c.h
  • I2C_ERROR_DMA : ald_i2c.h
  • I2C_ERROR_NONE : ald_i2c.h
  • I2C_ERROR_RF : ald_i2c.h
  • I2C_ERROR_ROV : ald_i2c.h
  • I2C_ERROR_RUD : ald_i2c.h
  • i2c_error_t : ald_i2c.h
  • I2C_ERROR_TE : ald_i2c.h
  • I2C_ERROR_TIMEOUT : ald_i2c.h
  • I2C_ERROR_TOV : ald_i2c.h
  • I2C_ERROR_TUD : ald_i2c.h
  • I2C_EXTREME_FAST_MODE_MAX_CLK : ald_i2c.h
  • I2C_FAST_MODE_MAX_CLK : ald_i2c.h
  • I2C_FLAG_MASK : ald_i2c.h
  • I2C_FREQ_RANGE : ald_i2c.h
  • i2c_general_addr_t : ald_i2c.h
  • I2C_GENERALCALL_DISABLE : ald_i2c.h
  • I2C_GENERALCALL_ENABLE : ald_i2c.h
  • I2C_GET_FLAG : ald_i2c.h
  • I2C_GET_IT_FLAG : ald_i2c.h
  • I2C_GET_IT_SOURCE : ald_i2c.h
  • i2c_handle_t : ald_i2c.h
  • i2c_interrupt_t : ald_i2c.h
  • I2C_IT_ADDR : ald_i2c.h
  • I2C_IT_ALERT : ald_i2c.h
  • I2C_IT_ARLO : ald_i2c.h
  • I2C_IT_BERR : ald_i2c.h
  • I2C_IT_NACK : ald_i2c.h
  • I2C_IT_PECE : ald_i2c.h
  • I2C_IT_RXF : ald_i2c.h
  • I2C_IT_RXOV : ald_i2c.h
  • I2C_IT_RXTH : ald_i2c.h
  • I2C_IT_RXUD : ald_i2c.h
  • I2C_IT_STOP : ald_i2c.h
  • I2C_IT_TC : ald_i2c.h
  • I2C_IT_TCR : ald_i2c.h
  • I2C_IT_TOUT : ald_i2c.h
  • I2C_IT_TXE : ald_i2c.h
  • I2C_IT_TXOV : ald_i2c.h
  • I2C_IT_TXTH : ald_i2c.h
  • I2C_IT_TXUD : ald_i2c.h
  • I2C_MASTER_GET_DIR : ald_i2c.h
  • i2c_master_recv_rxne() : ald_i2c.c
  • i2c_master_recv_tc() : ald_i2c.c
  • i2c_master_req_read() : ald_i2c.c
  • i2c_master_req_write() : ald_i2c.c
  • i2c_master_send_tc() : ald_i2c.c
  • i2c_master_send_txe() : ald_i2c.c
  • I2C_MAX_DELAY : ald_i2c.c
  • I2C_MEM_ADD_LSB : ald_i2c.h
  • I2C_MEM_ADD_MSB : ald_i2c.h
  • I2C_MEMADD_SIZE_16BIT : ald_i2c.h
  • I2C_MEMADD_SIZE_8BIT : ald_i2c.h
  • I2C_MODE_MASTER : ald_i2c.h
  • I2C_MODE_MEM : ald_i2c.h
  • I2C_MODE_NONE : ald_i2c.h
  • I2C_MODE_SLAVE : ald_i2c.h
  • i2c_mode_t : ald_i2c.h
  • I2C_MODULE_MASTER : ald_i2c.h
  • I2C_MODULE_SLAVE : ald_i2c.h
  • i2c_module_t : ald_i2c.h
  • I2C_NOSTRETCH_DISABLE : ald_i2c.h
  • I2C_NOSTRETCH_ENABLE : ald_i2c.h
  • i2c_nostretch_t : ald_i2c.h
  • I2C_OA1EN : ald_i2c.h
  • I2C_OA1MODE : ald_i2c.h
  • I2C_OA2EN : ald_i2c.h
  • I2C_OAR2_ADD2 : ald_i2c.h
  • I2C_OAR2_ENDUAL : ald_i2c.h
  • i2c_oar2_t : ald_i2c.h
  • i2c_req_mem_read() : ald_i2c.c
  • i2c_req_mem_write() : ald_i2c.c
  • I2C_RESET_HANDLE_STATE : ald_i2c.h
  • I2C_SLAVE_GET_DIR : ald_i2c.h
  • i2c_slave_recv_rxne() : ald_i2c.c
  • i2c_slave_send_txe() : ald_i2c.c
  • i2c_slave_stopf() : ald_i2c.c
  • i2c_speed_init() : ald_i2c.c
  • I2C_STANDARD_MODE_MAX_CLK : ald_i2c.h
  • I2C_STAT_BUSY : ald_i2c.h
  • I2C_STAT_DIR : ald_i2c.h
  • I2C_STAT_RXE : ald_i2c.h
  • I2C_STAT_RXF : ald_i2c.h
  • I2C_STAT_RXOV : ald_i2c.h
  • I2C_STAT_RXTH : ald_i2c.h
  • I2C_STAT_RXUD : ald_i2c.h
  • i2c_stat_t : ald_i2c.h
  • I2C_STAT_TC : ald_i2c.h
  • I2C_STAT_TCR : ald_i2c.h
  • I2C_STAT_THTH : ald_i2c.h
  • I2C_STAT_TXE : ald_i2c.h
  • I2C_STAT_TXF : ald_i2c.h
  • I2C_STAT_TXOV : ald_i2c.h
  • I2C_STAT_TXUD : ald_i2c.h
  • I2C_STATE_BUSY : ald_i2c.h
  • I2C_STATE_BUSY_RX : ald_i2c.h
  • I2C_STATE_BUSY_TX : ald_i2c.h
  • I2C_STATE_ERROR : ald_i2c.h
  • I2C_STATE_READY : ald_i2c.h
  • I2C_STATE_RESET : ald_i2c.h
  • i2c_state_t : ald_i2c.h
  • I2C_STATE_TIMEOUT : ald_i2c.h
  • I2C_TIMEOUT_ADDR_SLAVE : ald_i2c.c
  • I2C_TIMEOUT_BUSY_FLAG : ald_i2c.c
  • I2C_TIMEOUT_FLAG : ald_i2c.c
  • I2C_TIMEOUTR_TIDLE : ald_i2c.h
  • I2C_TIMEOUTR_TIMEOUTEN : ald_i2c.h
  • i2c_timoutr_t : ald_i2c.h
  • i2c_trise_t : ald_i2c.h
  • I2C_TRISE_TRISE : ald_i2c.h
  • i2c_wait_flag_change_to_timeout() : ald_i2c.c
  • i2c_wait_master_addr_to_timeout() : ald_i2c.c
  • i2c_wait_rxne_to_timeout() : ald_i2c.c
  • i2c_wait_txe_to_timeout() : ald_i2c.c
  • i2s_cfg_t : ald_i2s.h
  • i2s_ch_side_t : ald_i2s.h
  • i2s_chlen_t : ald_i2s.h
  • i2s_cpol_t : ald_i2s.h
  • i2s_datalen_t : ald_i2s.h
  • I2S_DISABLE : ald_i2s.h
  • i2s_dma_error() : ald_i2s.c
  • i2s_dma_recv_cplt() : ald_i2s.c
  • I2S_DMA_REQ_RX : ald_i2s.h
  • i2s_dma_req_t : ald_i2s.h
  • I2S_DMA_REQ_TX : ald_i2s.h
  • i2s_dma_send_cplt() : ald_i2s.c
  • I2S_ENABLE : ald_i2s.h
  • I2S_ERROR_DMA : ald_i2s.h
  • I2S_ERROR_FLAG : ald_i2s.h
  • I2S_ERROR_FRE : ald_i2s.h
  • I2S_ERROR_MODF : ald_i2s.h
  • I2S_ERROR_NONE : ald_i2s.h
  • I2S_ERROR_RXOV : ald_i2s.h
  • i2s_error_t : ald_i2s.h
  • I2S_ERROR_TXOV : ald_i2s.h
  • i2s_flag_t : ald_i2s.h
  • I2S_FRAME_LONG : ald_i2s.h
  • I2S_FRAME_SHORT : ald_i2s.h
  • i2s_handle_t : ald_i2s.h
  • I2S_IF_FRE : ald_i2s.h
  • I2S_IF_RXF : ald_i2s.h
  • I2S_IF_RXOV : ald_i2s.h
  • I2S_IF_RXTH : ald_i2s.h
  • I2S_IF_RXUD : ald_i2s.h
  • I2S_IF_TXE : ald_i2s.h
  • I2S_IF_TXOV : ald_i2s.h
  • I2S_IF_TXUD : ald_i2s.h
  • I2S_INACTIVE_HIGH : ald_i2s.h
  • I2S_INACTIVE_LOW : ald_i2s.h
  • I2S_IT_CRCERR : ald_i2s.h
  • I2S_IT_FRE : ald_i2s.h
  • I2S_IT_MODF : ald_i2s.h
  • I2S_IT_RXF : ald_i2s.h
  • I2S_IT_RXOV : ald_i2s.h
  • I2S_IT_RXTH : ald_i2s.h
  • I2S_IT_RXUD : ald_i2s.h
  • i2s_it_t : ald_i2s.h
  • I2S_IT_TXE : ald_i2s.h
  • I2S_IT_TXOV : ald_i2s.h
  • I2S_IT_TXUD : ald_i2s.h
  • I2S_LEN_16 : ald_i2s.h
  • I2S_LEN_24 : ald_i2s.h
  • I2S_LEN_32 : ald_i2s.h
  • I2S_MASTER_RECEIVE : ald_i2s.h
  • I2S_MASTER_TRANSMIT : ald_i2s.h
  • i2s_pcms_t : ald_i2s.h
  • I2S_RESET_HANDLE_STATE : ald_i2s.h
  • I2S_SIDE_LEFT : ald_i2s.h
  • I2S_SIDE_RIGHT : ald_i2s.h
  • I2S_SR_RXNE : ald_i2s.h
  • i2s_sr_status_t : ald_i2s.h
  • I2S_SR_TXE : ald_i2s.h
  • I2S_SR_TXE_RXNE : ald_i2s.h
  • i2s_standard_t : ald_i2s.h
  • I2S_STATE_BUSY : ald_i2s.h
  • I2S_STATE_BUSY_RX : ald_i2s.h
  • I2S_STATE_BUSY_TX : ald_i2s.h
  • I2S_STATE_BUSY_TX_RX : ald_i2s.h
  • I2S_STATE_ERROR : ald_i2s.h
  • I2S_STATE_READY : ald_i2s.h
  • I2S_STATE_RESET : ald_i2s.h
  • i2s_state_t : ald_i2s.h
  • I2S_STATE_TIMEOUT : ald_i2s.h
  • I2S_STATUS_BUSY : ald_i2s.h
  • I2S_STATUS_CHSIDE : ald_i2s.h
  • I2S_STATUS_RXE : ald_i2s.h
  • I2S_STATUS_RXF : ald_i2s.h
  • I2S_STATUS_RXOV : ald_i2s.h
  • I2S_STATUS_RXUD : ald_i2s.h
  • i2s_status_t : ald_i2s.h
  • I2S_STATUS_TXE : ald_i2s.h
  • I2S_STATUS_TXF : ald_i2s.h
  • I2S_STATUS_TXOV : ald_i2s.h
  • I2S_STATUS_TXUD : ald_i2s.h
  • I2S_STD_LSB : ald_i2s.h
  • I2S_STD_MSB : ald_i2s.h
  • I2S_STD_PCM : ald_i2s.h
  • I2S_STD_PHI : ald_i2s.h
  • i2s_wait_status() : ald_i2s.c
  • I2S_WIDE_16 : ald_i2s.h
  • I2S_WIDE_32 : ald_i2s.h
  • IAP_DWP : ald_iap.h
  • IAP_DWP_ADDR : ald_iap.h
  • IAP_PE : ald_iap.h
  • IAP_PE_ADDR : ald_iap.h
  • IAP_WP : ald_iap.h
  • IAP_WP_ADDR : ald_iap.h
  • IAP_WSP : ald_iap.h
  • IAP_WSP_ADDR : ald_iap.h
  • IndexToUSBEP : ald_usb.h
  • INFO_PAGE_ADDR : ald_flash.h
  • INFO_PAGE_MASK : ald_flash.h
  • INFO_PAGE_SIZE : ald_flash.h
  • IS_4BYTES_ALIGN : ald_flash.h
  • IS_ACMP_EDGE_TYPE : ald_acmp.h
  • IS_ACMP_FLAG_TYPE : ald_acmp.h
  • IS_ACMP_HYSTSEL_TYPE : ald_acmp.h
  • IS_ACMP_INACTVAL_TYPE : ald_acmp.h
  • IS_ACMP_IT_TYPE : ald_acmp.h
  • IS_ACMP_MODE_TYPE : ald_acmp.h
  • IS_ACMP_NEG_INPUT_TYPE : ald_acmp.h
  • IS_ACMP_POS_INPUT_TYPE : ald_acmp.h
  • IS_ACMP_STATUS_TYPE : ald_acmp.h
  • IS_ACMP_TYPE : ald_acmp.h
  • IS_ACMP_WARM_UP_TIME_TYPE : ald_acmp.h
  • IS_ADC_ANALOG_WTD_MODE_TYPE : ald_adc.h
  • IS_ADC_CHANNELS_TYPE : ald_adc.h
  • IS_ADC_CLK_DIV_TYPE : ald_adc.h
  • IS_ADC_CONV_BIT_TYPE : ald_adc.h
  • IS_ADC_DATA_ALIGN_TYPE : ald_adc.h
  • IS_ADC_DISC_NR_TYPE : ald_adc.h
  • IS_ADC_EVENT_TYPE : ald_adc.h
  • IS_ADC_FLAGS_TYPE : ald_adc.h
  • IS_ADC_ICH_IDX_TYPE : ald_adc.h
  • IS_ADC_ICH_NR_TYPE : ald_adc.h
  • IS_ADC_IST_OFFSET_TYPE : ald_adc.h
  • IS_ADC_IT_TYPE : ald_adc.h
  • IS_ADC_NCH_IDX_TYPE : ald_adc.h
  • IS_ADC_NCH_NR_TYPE : ald_adc.h
  • IS_ADC_NCHESEL_MODE_TYPE : ald_adc.h
  • IS_ADC_NEG_REF_VOLTAGE_TYPE : ald_adc.h
  • IS_ADC_SAMPLING_TIMES_TYPE : ald_adc.h
  • IS_ADC_TYPE : ald_adc.h
  • IS_BIT_CLR : utils.h
  • IS_BIT_SET : utils.h
  • IS_BKPC_PREH_CLOCK : ald_bkpc.h
  • IS_BKPC_RAM_IDX : ald_bkpc.h
  • IS_BKPC_WAKEUP_LEVEL : ald_bkpc.h
  • IS_BKPC_WAKEUP_PORT : ald_bkpc.h
  • IS_CAN_ALL : ald_can.h
  • IS_CAN_BS1 : ald_can.h
  • IS_CAN_BS2 : ald_can.h
  • IS_CAN_CLEAR_FLAG : ald_can.h
  • IS_CAN_DATA_LEN : ald_can.h
  • IS_CAN_EXTID : ald_can.h
  • IS_CAN_FIFO : ald_can.h
  • IS_CAN_FILTER_FIFO : ald_can.h
  • IS_CAN_FILTER_MODE : ald_can.h
  • IS_CAN_FILTER_NUMBER : ald_can.h
  • IS_CAN_FILTER_SCALE : ald_can.h
  • IS_CAN_GET_FLAG : ald_can.h
  • IS_CAN_IDTYPE : ald_can.h
  • IS_CAN_IT : ald_can.h
  • IS_CAN_MODE : ald_can.h
  • IS_CAN_PRESCALER : ald_can.h
  • IS_CAN_RTR : ald_can.h
  • IS_CAN_SJW : ald_can.h
  • IS_CAN_STDID : ald_can.h
  • IS_CAN_TX_MAILBOX : ald_can.h
  • IS_CMU_BUS : ald_cmu.h
  • IS_CMU_BUZZ_DIV : ald_cmu.h
  • IS_CMU_CLOCK : ald_cmu.h
  • IS_CMU_CLOCK_STATE : ald_cmu.h
  • IS_CMU_DIV : ald_cmu.h
  • IS_CMU_HOSC_RANGE : ald_cmu.h
  • IS_CMU_LCD_CLOCK_SEL : ald_cmu.h
  • IS_CMU_LP_PERH_CLOCK_SEL : ald_cmu.h
  • IS_CMU_OUTPUT_HIGH_DIV : ald_cmu.h
  • IS_CMU_OUTPUT_HIGH_SEL : ald_cmu.h
  • IS_CMU_OUTPUT_LOW_SEL : ald_cmu.h
  • IS_CMU_PERH : ald_cmu.h
  • IS_CMU_PLL1_INPUT : ald_cmu.h
  • IS_CMU_QSPI_CLOCK_SEL : ald_cmu.h
  • IS_CMU_SAFE_CLOCK_TYPE : ald_cmu.h
  • IS_CMU_STOP1_CLOCK : ald_cmu.h
  • IS_CMU_USB_CLOCK_SEL : ald_cmu.h
  • IS_CMU_USB_DIV : ald_cmu.h
  • IS_CRC : ald_crc.h
  • IS_CRC_MODE : ald_crc.h
  • IS_CRYPT : ald_crypt.h
  • IS_CRYPT_FLAG : ald_crypt.h
  • IS_CRYPT_IT : ald_crypt.h
  • IS_CRYPT_IV_LEN : ald_crypt.h
  • IS_CRYPT_KEY_LEN : ald_crypt.h
  • IS_CRYPT_KS : ald_crypt.h
  • IS_CRYPT_MODE : ald_crypt.h
  • IS_CYCLECTRL_TYPE : ald_dma.h
  • IS_DAC_CHANNEL_TYPE : ald_dac.h
  • IS_DAC_CONVERT_TYPE : ald_dac.h
  • IS_DAC_FLAG_TYPE : ald_dac.h
  • IS_DAC_INTERRUPT_TYPE : ald_dac.h
  • IS_DAC_NEG_REFRESH_TYPE : ald_dac.h
  • IS_DAC_OUTPUT_TYPE : ald_dac.h
  • IS_DAC_PISSEL_CH_TYPE : ald_dac.h
  • IS_DAC_POS_REFRESH_TYPE : ald_dac.h
  • IS_DAC_PRESCALE_TYPE : ald_dac.h
  • IS_DAC_REFRESH_TYPE : ald_dac.h
  • IS_DAC_STATUS_TYPE : ald_dac.h
  • IS_DAC_TRIGGER_TYPE : ald_dac.h
  • IS_DAC_TYPE : ald_dac.h
  • IS_DMA : ald_dma.h
  • IS_DMA_ARBITERCONFIG_TYPE : ald_dma.h
  • IS_DMA_CHANNEL : ald_dma.h
  • IS_DMA_DATA_SIZE : ald_dma.h
  • IS_DMA_DATAINC_TYPE : ald_dma.h
  • IS_DMA_DATASIZE_TYPE : ald_dma.h
  • IS_DMA_IT_TYPE : ald_dma.h
  • IS_DMA_MSEL_TYPE : ald_dma.h
  • IS_DMA_MSIGSEL_TYPE : ald_dma.h
  • IS_EBI_ACCESS_MODE : ald_ebi.h
  • IS_EBI_ADDRESS_HOLD_TIME : ald_ebi.h
  • IS_EBI_ADDRESS_SETUP_TIME : ald_ebi.h
  • IS_EBI_ASYNWAIT : ald_ebi.h
  • IS_EBI_BANK_NUMBER : ald_ebi.h
  • IS_EBI_BURSTMODE : ald_ebi.h
  • IS_EBI_CLK_DIV : ald_ebi.h
  • IS_EBI_DATA_CLOCK : ald_ebi.h
  • IS_EBI_DATA_ENABLE : ald_ebi.h
  • IS_EBI_DATA_LATENCY : ald_ebi.h
  • IS_EBI_DATASETUP_TIME : ald_ebi.h
  • IS_EBI_ECC_STATE : ald_ebi.h
  • IS_EBI_ECCPAGE_SIZE : ald_ebi.h
  • IS_EBI_EXTENDED_MODE : ald_ebi.h
  • IS_EBI_FRAME_LINE_NUMBER : ald_ebi.h
  • IS_EBI_FRAME_PIXEL_NUMBER : ald_ebi.h
  • IS_EBI_HIZ_TIME : ald_ebi.h
  • IS_EBI_HOLD_TIME : ald_ebi.h
  • IS_EBI_HORIZONTAL_SYNCH : ald_ebi.h
  • IS_EBI_HYSNC_PULSE_WIDTH : ald_ebi.h
  • IS_EBI_LCD_DATASETUP_TIME : ald_ebi.h
  • IS_EBI_LCD_DEVICE : ald_ebi.h
  • IS_EBI_LCD_ENABLE : ald_ebi.h
  • IS_EBI_LCD_RESET : ald_ebi.h
  • IS_EBI_MEMORY : ald_ebi.h
  • IS_EBI_MUX : ald_ebi.h
  • IS_EBI_NAND_BANK : ald_ebi.h
  • IS_EBI_NAND_DEVICE : ald_ebi.h
  • IS_EBI_NAND_MEMORY_WIDTH : ald_ebi.h
  • IS_EBI_NORSRAM_BANK : ald_ebi.h
  • IS_EBI_NORSRAM_DEVICE : ald_ebi.h
  • IS_EBI_NORSRAM_EXTENDED_DEVICE : ald_ebi.h
  • IS_EBI_NORSRAM_MEMORY_WIDTH : ald_ebi.h
  • IS_EBI_SETUP_TIME : ald_ebi.h
  • IS_EBI_TAR_TIME : ald_ebi.h
  • IS_EBI_TCLR_TIME : ald_ebi.h
  • IS_EBI_TURNAROUND_TIME : ald_ebi.h
  • IS_EBI_VERTICAL_SYNCH : ald_ebi.h
  • IS_EBI_VSYNC_PULSE_WIDTH : ald_ebi.h
  • IS_EBI_WAIT_FEATURE : ald_ebi.h
  • IS_EBI_WAIT_POLARITY : ald_ebi.h
  • IS_EBI_WAIT_SIGNAL_ACTIVE : ald_ebi.h
  • IS_EBI_WAIT_TIME : ald_ebi.h
  • IS_EBI_WAITE_SIGNAL : ald_ebi.h
  • IS_EBI_WRAP_MODE : ald_ebi.h
  • IS_EBI_WRITE_BURST : ald_ebi.h
  • IS_EBI_WRITE_OPERATION : ald_ebi.h
  • IS_EXTI_FLTCKS_TYPE : ald_gpio.h
  • IS_FLASH_ADDRESS : ald_flash.h
  • IS_FUNC_STATE : type.h , ald_wdt.h
  • IS_GPIO_FLT : ald_gpio.h
  • IS_GPIO_FUNC : ald_gpio.h
  • IS_GPIO_MODE : ald_gpio.h
  • IS_GPIO_ODOS : ald_gpio.h
  • IS_GPIO_ODRV : ald_gpio.h
  • IS_GPIO_PIN : ald_gpio.h
  • IS_GPIO_PORT : ald_gpio.h
  • IS_GPIO_PUPD : ald_gpio.h
  • IS_GPIO_TYPE : ald_gpio.h
  • IS_HTR_TYPE : ald_adc.h
  • IS_I2C_ADDRESSING_MODE : ald_i2c.h
  • IS_I2C_CLOCK_SPEED : ald_i2c.h
  • IS_I2C_DUAL_ADDRESS : ald_i2c.h
  • IS_I2C_GENERAL_CALL : ald_i2c.h
  • IS_I2C_IT : ald_i2c.h
  • IS_I2C_MEMADD_size : ald_i2c.h
  • IS_I2C_MODULE : ald_i2c.h
  • IS_I2C_NO_STRETCH : ald_i2c.h
  • IS_I2C_TYPE : ald_i2c.h
  • IS_I2S : ald_i2s.h
  • IS_I2S_CH_LEN : ald_i2s.h
  • IS_I2S_CPOL : ald_i2s.h
  • IS_I2S_DATE_LEN : ald_i2s.h
  • IS_I2S_DMA_REQ : ald_i2s.h
  • IS_I2S_FLAG : ald_i2s.h
  • IS_I2S_IF : ald_i2s.h
  • IS_I2S_IT : ald_i2s.h
  • IS_I2S_PCMS : ald_i2s.h
  • IS_I2S_STANDARD : ald_i2s.h
  • IS_I2S_STATUS : ald_i2s.h
  • IS_LOCK_STATE : type.h
  • IS_LTR_TYPE : ald_adc.h
  • IS_PIS : ald_pis.h
  • IS_PIS_CLOCK : ald_pis.h
  • IS_PIS_EDGE : ald_pis.h
  • IS_PIS_MODU_CHANNEL : ald_pis.h
  • IS_PIS_MODU_LEVEL : ald_pis.h
  • IS_PIS_MODU_SRC : ald_pis.h
  • IS_PIS_MODU_TARGET : ald_pis.h
  • IS_PIS_OUPUT_CH : ald_pis.h
  • IS_PIS_OUTPUT : ald_pis.h
  • IS_PIS_SIGNAL_MODE : ald_pis.h
  • IS_PIS_SRC : ald_pis.h
  • IS_PIS_TRIG : ald_pis.h
  • IS_PMU_LDO18_MODE : ald_pmu.h
  • IS_PMU_LDO_LPMODE_OUTPUT : ald_pmu.h
  • IS_PMU_LP_MODE : ald_pmu.h
  • IS_PMU_LVD_TRIGGER_MODE : ald_pmu.h
  • IS_PMU_LVD_VOL_SEL : ald_pmu.h
  • IS_PMU_PERH_POWER : ald_pmu.h
  • IS_PMU_STATUS : ald_pmu.h
  • IS_POS_REF_VOLTAGE_TYPE : ald_adc.h
  • IS_PREEMPT_PRIO : utils.h
  • IS_QSPI_ADDR_SIZE : ald_qspi.h
  • IS_QSPI_ALL : ald_qspi.h
  • IS_QSPI_BLOCK_SIZE : ald_qspi.h
  • IS_QSPI_CLOCK_PHASE : ald_qspi.h
  • IS_QSPI_CLOCK_POLARITY : ald_qspi.h
  • IS_QSPI_CLOCK_PRESCALER : ald_qspi.h
  • IS_QSPI_DCYLES : ald_qspi.h
  • IS_QSPI_DDR_BIT_ENABLE : ald_qspi.h
  • IS_QSPI_DEVICE_DELAY_CCSOT : ald_qspi.h
  • IS_QSPI_DEVICE_DELAY_CSDA : ald_qspi.h
  • IS_QSPI_DEVICE_DELAY_CSDADS : ald_qspi.h
  • IS_QSPI_DEVICE_DELAY_CSEOT : ald_qspi.h
  • IS_QSPI_IF : ald_qspi.h
  • IS_QSPI_INDIRECT_READ_STATUS : ald_qspi.h
  • IS_QSPI_INDIRECT_READ_WATERMARK : ald_qspi.h
  • IS_QSPI_INDIRECT_SRAM_FILL_TYPE : ald_qspi.h
  • IS_QSPI_INDIRECT_TRIGGER_RANGE : ald_qspi.h
  • IS_QSPI_INDIRECT_WRITE_STATUS : ald_qspi.h
  • IS_QSPI_IT : ald_qspi.h
  • IS_QSPI_MODE_BIT_ENABLE : ald_qspi.h
  • IS_QSPI_NSS_SIZE : ald_qspi.h
  • IS_QSPI_PAGE_SIZE : ald_qspi.h
  • IS_QSPI_RD_OPCODE : ald_qspi.h
  • IS_QSPI_READ_DATA_CAPTURE_DELAY_READ : ald_qspi.h
  • IS_QSPI_READ_DATA_DELAY_TRANSMIT : ald_qspi.h
  • IS_QSPI_READ_DATA_SAMPLE_EDGE : ald_qspi.h
  • IS_QSPI_SRAM_PARTITION : ald_qspi.h
  • IS_QSPI_WR_OPCODE : ald_qspi.h
  • IS_QSPI_XFER_TYPE : ald_qspi.h
  • IS_RMU_BORFLT : ald_rmu.h
  • IS_RMU_BORVOL : ald_rmu.h
  • IS_RMU_PERH : ald_rmu.h
  • IS_RMU_STATE : ald_rmu.h
  • IS_RMU_STATE_CLEAR : ald_rmu.h
  • IS_RTC_ALARM : ald_rtc.h
  • IS_RTC_ALARM_MASK : ald_rtc.h
  • IS_RTC_ALARM_SEL : ald_rtc.h
  • IS_RTC_ALARM_SS_MASK : ald_rtc.h
  • IS_RTC_CALC_FREQ : ald_rtc.h
  • IS_RTC_CALI_CALC : ald_rtc.h
  • IS_RTC_CALI_FREQ : ald_rtc.h
  • IS_RTC_CALI_TC : ald_rtc.h
  • IS_RTC_CLOCK_OUTPUT : ald_rtc.h
  • IS_RTC_DAY : ald_rtc.h
  • IS_RTC_FORMAT : ald_rtc.h
  • IS_RTC_HOUR : ald_rtc.h
  • IS_RTC_HOUR_FORMAT : ald_rtc.h
  • IS_RTC_IF : ald_rtc.h
  • IS_RTC_IT : ald_rtc.h
  • IS_RTC_MINUTE : ald_rtc.h
  • IS_RTC_MONTH : ald_rtc.h
  • IS_RTC_OUTPUT_POLARITY : ald_rtc.h
  • IS_RTC_OUTPUT_SEL : ald_rtc.h
  • IS_RTC_SECOND : ald_rtc.h
  • IS_RTC_SOURCE_SEL : ald_rtc.h
  • IS_RTC_TAMPER : ald_rtc.h
  • IS_RTC_TAMPER_DURATION : ald_rtc.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : ald_rtc.h
  • IS_RTC_TAMPER_TRIGGER : ald_rtc.h
  • IS_RTC_TS_SIGNAL : ald_rtc.h
  • IS_RTC_TS_STYLE : ald_rtc.h
  • IS_RTC_WAKEUP_CLOCK : ald_rtc.h
  • IS_RTC_YEAR : ald_rtc.h
  • IS_SHIFT_SUB_SS : ald_rtc.h
  • IS_SPI : ald_spi.h
  • IS_SPI_BAUD : ald_spi.h
  • IS_SPI_BIDMODE : ald_spi.h
  • IS_SPI_BIDOE : ald_spi.h
  • IS_SPI_CPHA : ald_spi.h
  • IS_SPI_CPOL : ald_spi.h
  • IS_SPI_DATASIZE : ald_spi.h
  • IS_SPI_DIRECTION : ald_spi.h
  • IS_SPI_DMA_REQ : ald_spi.h
  • IS_SPI_FIRBIT : ald_spi.h
  • IS_SPI_FRAME : ald_spi.h
  • IS_SPI_IF : ald_spi.h
  • IS_SPI_IT : ald_spi.h
  • IS_SPI_MODE : ald_spi.h
  • IS_SPI_STATUS : ald_spi.h
  • IS_SUB_PRIO : utils.h
  • IS_SYSTICK_INTERVAL : utils.h
  • IS_TIMER_BREAK_POLARITY : ald_timer.h
  • IS_TIMER_CHANNELS : ald_timer.h
  • IS_TIMER_CHNREF_CLEAR : ald_timer.h
  • IS_TIMER_CLEAR_INPUT_POLARITY : ald_timer.h
  • IS_TIMER_CLEAR_INPUT_SOURCE : ald_timer.h
  • IS_TIMER_CLOCK_DIVISION : ald_timer.h
  • IS_TIMER_CLOCK_LEVEL : ald_timer.h
  • IS_TIMER_CLOCK_POLARITY : ald_timer.h
  • IS_TIMER_CLOCK_SOURCE : ald_timer.h
  • IS_TIMER_COUNTER_MODE : ald_timer.h
  • IS_TIMER_DEAD_TIMERE : ald_timer.h
  • IS_TIMER_DMA_REQ : ald_timer.h
  • IS_TIMER_ENCODER_MODE : ald_timer.h
  • IS_TIMER_ETR_PSC : ald_timer.h
  • IS_TIMER_EVENT_SOURCE : ald_timer.h
  • IS_TIMER_FLAG : ald_timer.h
  • IS_TIMER_IC_FILTER : ald_timer.h
  • IS_TIMER_IC_POLARITY : ald_timer.h
  • IS_TIMER_IC_PSC : ald_timer.h
  • IS_TIMER_IC_SELECT : ald_timer.h
  • IS_TIMER_IT : ald_timer.h
  • IS_TIMER_MASTER_MODE_SEL : ald_timer.h
  • IS_TIMER_OC_MODE : ald_timer.h
  • IS_TIMER_OC_POLARITY : ald_timer.h
  • IS_TIMER_OCIDLE_STATE : ald_timer.h
  • IS_TIMER_OCN_POLARITY : ald_timer.h
  • IS_TIMER_OCNIDLE_STATE : ald_timer.h
  • IS_TIMER_OP_MODE : ald_timer.h
  • IS_TIMER_OP_OUTPUT_CH : ald_timer.h
  • IS_TIMER_PWM_MODE : ald_timer.h
  • IS_TIMER_SLAVE_MODE : ald_timer.h
  • IS_TIMER_TS : ald_timer.h
  • IS_TRIGGER_STYLE : ald_gpio.h
  • IS_TRNG_ADJC : ald_trng.h
  • IS_TRNG_DATA_WIDTH : ald_trng.h
  • IS_TRNG_FLAG : ald_trng.h
  • IS_TRNG_IT : ald_trng.h
  • IS_TRNG_SEED_TYPE : ald_trng.h
  • IS_TRNG_STATUS : ald_trng.h
  • IS_TRNG_T_START : ald_trng.h
  • IS_TSENSE_SOURCE_SEL : ald_tsense.h
  • IS_UART_ALL : ald_uart.h
  • IS_UART_AUTO_BAUD_MODE : ald_uart.h
  • IS_UART_BAUDRATE : ald_uart.h
  • IS_UART_DATA : ald_uart.h
  • IS_UART_DMA_REQ : ald_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : ald_uart.h
  • IS_UART_IF : ald_uart.h
  • IS_UART_IT : ald_uart.h
  • IS_UART_LIN_BREAK_LEN : ald_uart.h
  • IS_UART_MODE : ald_uart.h
  • IS_UART_PARITY : ald_uart.h
  • IS_UART_RXFIFO_TYPE : ald_uart.h
  • IS_UART_SCARD : ald_uart.h
  • IS_UART_SCARD_CLK : ald_uart.h
  • IS_UART_STATUS : ald_uart.h
  • IS_UART_STOPBITS : ald_uart.h
  • IS_UART_TXFIFO_TYPE : ald_uart.h
  • IS_UART_WORD_LENGTH : ald_uart.h
  • IS_WWDT_WIN_TYPE : ald_wdt.h
  • it_status_t : type.h
  • IV_2_LEN : ald_crypt.h
  • IV_4_LEN : ald_crypt.h
  • IWDT_LOCK : ald_wdt.h
  • IWDT_UNLOCK : ald_wdt.h


ALD User Manual: Globals

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- k -

  • KEY_2_LEN : ald_crypt.h
  • KEY_4_LEN : ald_crypt.h
  • KEY_6_LEN : ald_crypt.h
  • KEY_8_LEN : ald_crypt.h


ALD User Manual: Globals

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- l -

  • LCDCTRL_CLEAR_MASK : ald_ebi.h
  • lib_tick : utils.c
  • LIN_BREAK_LEN_10B : ald_uart.h
  • LIN_BREAK_LEN_11B : ald_uart.h
  • LOCK : type.h
  • lock_state_t : type.h


ALD User Manual: Globals

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- m -

  • MAX_NAK_LIMIT : ald_usb.h
  • MAX_PACKET_SIZE_EP0 : ald_usb.h
  • MC_ADDRESS : ald_nor_lcd.h
  • MCU_CHIPID_ADDR : utils.h
  • MCU_UID0_ADDR : utils.h
  • MCU_UID1_ADDR : utils.h
  • MCU_UID2_ADDR : utils.h
  • MODIFY_REG : type.h


ALD User Manual: Globals

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- n -

  • NAND_BUSY : ald_nand.h
  • NAND_CMD_AREA_A : ald_nand.h
  • NAND_CMD_AREA_B : ald_nand.h
  • NAND_CMD_AREA_C : ald_nand.h
  • NAND_CMD_AREA_TRUE1 : ald_nand.h
  • NAND_CMD_ERASE0 : ald_nand.h
  • NAND_CMD_ERASE1 : ald_nand.h
  • NAND_CMD_LOCK_STATUS : ald_nand.h
  • NAND_CMD_READID : ald_nand.h
  • NAND_CMD_RESET : ald_nand.h
  • NAND_CMD_STATUS : ald_nand.h
  • NAND_CMD_WRITE0 : ald_nand.h
  • NAND_CMD_WRITE_TRUE1 : ald_nand.h
  • nand_config_device() : ald_nand.c
  • NAND_DEVICE1 : ald_nand.h
  • NAND_DEVICE2 : ald_nand.h
  • NAND_ERROR : ald_nand.h
  • NAND_INVALID_ADDRESS : ald_nand.h
  • NAND_READY : ald_nand.h
  • NAND_TIMEOUT_ERROR : ald_nand.h
  • NAND_VALID_ADDRESS : ald_nand.h
  • NAND_WRITE_TIMEOUT : ald_nand.h
  • NOR_ADDR_SHIFT : ald_nor_lcd.h
  • NOR_CMD_ADDRESS_FIFTH : ald_nor_lcd.h
  • NOR_CMD_ADDRESS_FIRST : ald_nor_lcd.h
  • NOR_CMD_ADDRESS_FIRST_CFI : ald_nor_lcd.h
  • NOR_CMD_ADDRESS_FOURTH : ald_nor_lcd.h
  • NOR_CMD_ADDRESS_SECOND : ald_nor_lcd.h
  • NOR_CMD_ADDRESS_SIXTH : ald_nor_lcd.h
  • NOR_CMD_ADDRESS_THIRD : ald_nor_lcd.h
  • NOR_CMD_DATA_AUTO_SELECT : ald_nor_lcd.h
  • NOR_CMD_DATA_BLOCK_ERASE : ald_nor_lcd.h
  • NOR_CMD_DATA_BUFFER_AND_PROG : ald_nor_lcd.h
  • NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM : ald_nor_lcd.h
  • NOR_CMD_DATA_CFI : ald_nor_lcd.h
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH : ald_nor_lcd.h
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH : ald_nor_lcd.h
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD : ald_nor_lcd.h
  • NOR_CMD_DATA_CHIP_ERASE : ald_nor_lcd.h
  • NOR_CMD_DATA_FIRST : ald_nor_lcd.h
  • NOR_CMD_DATA_PROGRAM : ald_nor_lcd.h
  • NOR_CMD_DATA_READ_RESET : ald_nor_lcd.h
  • NOR_CMD_DATA_SECOND : ald_nor_lcd.h
  • NOR_MASK_STATUS_DQ5 : ald_nor_lcd.h
  • NOR_MASK_STATUS_DQ6 : ald_nor_lcd.h
  • NOR_MEMORY_16B : ald_nor_lcd.h
  • NOR_MEMORY_8B : ald_nor_lcd.h
  • NOR_MEMORY_ADRESS1 : ald_nor_lcd.h
  • NOR_MEMORY_ADRESS2 : ald_nor_lcd.h
  • NOR_MEMORY_ADRESS3 : ald_nor_lcd.h
  • NOR_MEMORY_ADRESS4 : ald_nor_lcd.h
  • nor_status_t : ald_nor_lcd.h
  • NOR_TMEOUT : ald_nor_lcd.h
  • NOR_WRITE : ald_nor_lcd.h
  • NORMEMDATWIDTH : ald_nor_lcd.c
  • NUM_USB_EP : ald_usb.h
  • NVIC_PRIORITY_GROUP_0 : utils.h
  • NVIC_PRIORITY_GROUP_1 : utils.h
  • NVIC_PRIORITY_GROUP_2 : utils.h
  • NVIC_PRIORITY_GROUP_3 : utils.h
  • NVIC_PRIORITY_GROUP_4 : utils.h
  • nvic_priority_group_t : utils.h


ALD User Manual: Globals

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- o -

  • OK : utils.h
  • OP_CMD : ald_flash.c
  • op_cmd_type : ald_flash.h
  • OP_FLASH : ald_flash.h
  • OP_INFO : ald_flash.h


ALD User Manual: Globals

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- p -

  • page_have_writen() : ald_flash_ext.c
  • PATTR_CLEAR_MASK : ald_ebi.h
  • PCTRLR_CLEAR_MASK : ald_ebi.h
  • PER_MEM_BASE : type.h
  • PIN_MASK : ald_gpio.h
  • PIS_ACMP_OUT0 : ald_pis.h
  • PIS_ACMP_OUT1 : ald_pis.h
  • PIS_ADC0_INSERT : ald_pis.h
  • PIS_ADC0_NORMAL : ald_pis.h
  • PIS_ADC0_RESERVE : ald_pis.h
  • PIS_ADC1_INSERT : ald_pis.h
  • PIS_ADC1_NORMAL : ald_pis.h
  • PIS_ADC1_RESERVE : ald_pis.h
  • PIS_CH0_ADC1_NORMAL : ald_pis.h
  • PIS_CH0_LPTIM0_EXT0 : ald_pis.h
  • PIS_CH0_TIMER0_BRKIN : ald_pis.h
  • PIS_CH0_TIMER0_CH1IN : ald_pis.h
  • PIS_CH0_TIMER1_BRKIN : ald_pis.h
  • PIS_CH10_UART1_RXD : ald_pis.h
  • PIS_CH11_UART2_RXD : ald_pis.h
  • PIS_CH12_TIMER0_ITR0 : ald_pis.h
  • PIS_CH12_TIMER1_ITR0 : ald_pis.h
  • PIS_CH12_TIMER2_ITR0 : ald_pis.h
  • PIS_CH12_TIMER3_ITR0 : ald_pis.h
  • PIS_CH12_UART3_RXD : ald_pis.h
  • PIS_CH13_TIMER0_ITR1 : ald_pis.h
  • PIS_CH13_TIMER1_ITR1 : ald_pis.h
  • PIS_CH13_TIMER2_ITR1 : ald_pis.h
  • PIS_CH13_TIMER3_ITR1 : ald_pis.h
  • PIS_CH13_UART4_RXD : ald_pis.h
  • PIS_CH14_TIMER0_ITR2 : ald_pis.h
  • PIS_CH14_TIMER1_ITR2 : ald_pis.h
  • PIS_CH14_TIMER2_ITR2 : ald_pis.h
  • PIS_CH14_TIMER3_ITR2 : ald_pis.h
  • PIS_CH14_UART5_RXD : ald_pis.h
  • PIS_CH15_LPUART0_RXD : ald_pis.h
  • PIS_CH15_TIMER0_ITR3 : ald_pis.h
  • PIS_CH15_TIMER1_ITR3 : ald_pis.h
  • PIS_CH15_TIMER2_ITR3 : ald_pis.h
  • PIS_CH15_TIMER3_ITR3 : ald_pis.h
  • PIS_CH1_ADC1_INSERT : ald_pis.h
  • PIS_CH1_LPTIM0_EXT1 : ald_pis.h
  • PIS_CH1_TIMER1_CH1IN : ald_pis.h
  • PIS_CH2_LPTIM0_EXT2 : ald_pis.h
  • PIS_CH2_TIMER0_CH2IN : ald_pis.h
  • PIS_CH2_TIMER1_CH2IN : ald_pis.h
  • PIS_CH3_LPTIM0_EXT3 : ald_pis.h
  • PIS_CH3_TIMER0_CH3IN : ald_pis.h
  • PIS_CH3_TIMER1_CH3IN : ald_pis.h
  • PIS_CH4_LPTIM0_EXT4 : ald_pis.h
  • PIS_CH4_TIMER0_CH4IN : ald_pis.h
  • PIS_CH4_TIMER1_CH4IN : ald_pis.h
  • PIS_CH5_LPTIM0_EXT5 : ald_pis.h
  • PIS_CH5_SPI0_RX : ald_pis.h
  • PIS_CH5_TIMER2_CH1IN : ald_pis.h
  • PIS_CH5_TIMER3_CH1IN : ald_pis.h
  • PIS_CH6_ADC0_NORMAL : ald_pis.h
  • PIS_CH6_LPTIM0_EXT6 : ald_pis.h
  • PIS_CH6_SPI0_CLK : ald_pis.h
  • PIS_CH6_TIMER2_CH2IN : ald_pis.h
  • PIS_CH6_TIMER3_CH2IN : ald_pis.h
  • PIS_CH7_ADC0_INSERT : ald_pis.h
  • PIS_CH7_DMA_REQUEST : ald_pis.h
  • PIS_CH7_LPTIM0_EXT7 : ald_pis.h
  • PIS_CH7_SPI1_RX : ald_pis.h
  • PIS_CH7_TIMER2_CH3IN : ald_pis.h
  • PIS_CH7_TIMER3_CH3IN : ald_pis.h
  • PIS_CH8_SPI1_CLK : ald_pis.h
  • PIS_CH8_TIMER2_CH4IN : ald_pis.h
  • PIS_CH8_TIMER3_CH4IN : ald_pis.h
  • PIS_CH9_UART0_RXD : ald_pis.h
  • PIS_CH_0 : ald_pis.h
  • PIS_CH_1 : ald_pis.h
  • PIS_CH_10 : ald_pis.h
  • PIS_CH_11 : ald_pis.h
  • PIS_CH_12 : ald_pis.h
  • PIS_CH_13 : ald_pis.h
  • PIS_CH_14 : ald_pis.h
  • PIS_CH_15 : ald_pis.h
  • PIS_CH_2 : ald_pis.h
  • PIS_CH_3 : ald_pis.h
  • PIS_CH_4 : ald_pis.h
  • PIS_CH_5 : ald_pis.h
  • PIS_CH_6 : ald_pis.h
  • PIS_CH_7 : ald_pis.h
  • PIS_CH_8 : ald_pis.h
  • PIS_CH_9 : ald_pis.h
  • pis_ch_t : ald_pis.h
  • PIS_CHAN_INPUT : ald_pis.h
  • PIS_CLK_PCLK1 : ald_pis.h
  • PIS_CLK_PCLK2 : ald_pis.h
  • PIS_CLK_RESERVE : ald_pis.h
  • PIS_CLK_SYS : ald_pis.h
  • pis_clock_t : ald_pis.h
  • PIS_CON_0 : ald_pis.h
  • PIS_CON_1 : ald_pis.h
  • PIS_CON_NONE : ald_pis.h
  • pis_con_t : ald_pis.h
  • PIS_DAC0_CH0 : ald_pis.h
  • PIS_DAC0_CH1 : ald_pis.h
  • PIS_DMA : ald_pis.h
  • PIS_EDGE_DOWN : ald_pis.h
  • PIS_EDGE_NONE : ald_pis.h
  • pis_edge_t : ald_pis.h
  • PIS_EDGE_UP : ald_pis.h
  • PIS_EDGE_UP_DOWN : ald_pis.h
  • PIS_GPIO_PIN0 : ald_pis.h
  • PIS_GPIO_PIN1 : ald_pis.h
  • PIS_GPIO_PIN10 : ald_pis.h
  • PIS_GPIO_PIN11 : ald_pis.h
  • PIS_GPIO_PIN12 : ald_pis.h
  • PIS_GPIO_PIN13 : ald_pis.h
  • PIS_GPIO_PIN14 : ald_pis.h
  • PIS_GPIO_PIN15 : ald_pis.h
  • PIS_GPIO_PIN2 : ald_pis.h
  • PIS_GPIO_PIN3 : ald_pis.h
  • PIS_GPIO_PIN4 : ald_pis.h
  • PIS_GPIO_PIN5 : ald_pis.h
  • PIS_GPIO_PIN6 : ald_pis.h
  • PIS_GPIO_PIN7 : ald_pis.h
  • PIS_GPIO_PIN8 : ald_pis.h
  • PIS_GPIO_PIN9 : ald_pis.h
  • pis_handle_t : ald_pis.h
  • PIS_HIGH_LEVEL : ald_pis.h
  • PIS_I2C0_RECV : ald_pis.h
  • PIS_I2C0_SEND : ald_pis.h
  • PIS_I2C1_RECV : ald_pis.h
  • PIS_I2C1_SEND : ald_pis.h
  • pis_input_sel_t : ald_pis.h
  • PIS_LOW_LEVEL : ald_pis.h
  • PIS_LPTIMER0_ASY_UPDATA : ald_pis.h
  • PIS_LPTIMER0_SYN_UPDATA : ald_pis.h
  • PIS_LPUART0_ASY_RECV : ald_pis.h
  • PIS_LPUART0_ASY_SEND : ald_pis.h
  • PIS_LPUART0_SYN_RECV : ald_pis.h
  • PIS_LPUART0_SYN_SEND : ald_pis.h
  • PIS_LPUART0_TX : ald_pis.h
  • PIS_LVD : ald_pis.h
  • pis_modu_channel_t : ald_pis.h
  • pis_modu_level_t : ald_pis.h
  • pis_modu_src_t : ald_pis.h
  • pis_modu_targ_t : ald_pis.h
  • PIS_NON : ald_pis.h
  • PIS_NONE_INPUT : ald_pis.h
  • PIS_OUT_CH_0 : ald_pis.h
  • PIS_OUT_CH_1 : ald_pis.h
  • PIS_OUT_CH_2 : ald_pis.h
  • PIS_OUT_CH_3 : ald_pis.h
  • pis_out_ch_t : ald_pis.h
  • PIS_OUT_LEVEL : ald_pis.h
  • PIS_OUT_PULSE : ald_pis.h
  • pis_output_t : ald_pis.h
  • PIS_PORT_INPUT : ald_pis.h
  • PIS_RTC_ALARM : ald_pis.h
  • PIS_RTC_CLOCK : ald_pis.h
  • PIS_SPI0_NE : ald_pis.h
  • PIS_SPI0_RECV : ald_pis.h
  • PIS_SPI0_SEND : ald_pis.h
  • PIS_SPI1_NE : ald_pis.h
  • PIS_SPI1_RECV : ald_pis.h
  • PIS_SPI1_SEND : ald_pis.h
  • PIS_SRC_BUZ : ald_pis.h
  • PIS_SRC_LPTIM0 : ald_pis.h
  • PIS_SRC_NONE : ald_pis.h
  • pis_src_t : ald_pis.h
  • PIS_SRC_TIMER0 : ald_pis.h
  • PIS_SRC_TIMER1 : ald_pis.h
  • PIS_SRC_TIMER2 : ald_pis.h
  • PIS_SRC_TIMER3 : ald_pis.h
  • PIS_SRC_TIMER6 : ald_pis.h
  • PIS_SRC_TIMER7 : ald_pis.h
  • PIS_STATE_BUSY : ald_pis.h
  • PIS_STATE_ERROR : ald_pis.h
  • PIS_STATE_READY : ald_pis.h
  • PIS_STATE_RESET : ald_pis.h
  • pis_state_t : ald_pis.h
  • PIS_STATE_TIMEOUT : ald_pis.h
  • PIS_SYN_DIRECT : ald_pis.h
  • PIS_SYN_LEVEL_ASY_AHB : ald_pis.h
  • PIS_SYN_LEVEL_ASY_APB1 : ald_pis.h
  • PIS_SYN_LEVEL_ASY_APB2 : ald_pis.h
  • PIS_SYN_PULSE_ASY_AHB : ald_pis.h
  • PIS_SYN_PULSE_ASY_APB1 : ald_pis.h
  • PIS_SYN_PULSE_ASY_APB2 : ald_pis.h
  • pis_syncsel_t : ald_pis.h
  • PIS_TIMER0_INPUT_1 : ald_pis.h
  • PIS_TIMER0_INPUT_2 : ald_pis.h
  • PIS_TIMER0_INPUT_3 : ald_pis.h
  • PIS_TIMER0_INPUT_4 : ald_pis.h
  • PIS_TIMER0_OUTPUT_1 : ald_pis.h
  • PIS_TIMER0_OUTPUT_2 : ald_pis.h
  • PIS_TIMER0_OUTPUT_3 : ald_pis.h
  • PIS_TIMER0_OUTPUT_4 : ald_pis.h
  • PIS_TIMER0_TRIG : ald_pis.h
  • PIS_TIMER0_UPDATA : ald_pis.h
  • PIS_TIMER1_INPUT_1 : ald_pis.h
  • PIS_TIMER1_INPUT_2 : ald_pis.h
  • PIS_TIMER1_INPUT_3 : ald_pis.h
  • PIS_TIMER1_INPUT_4 : ald_pis.h
  • PIS_TIMER1_OUTPUT_1 : ald_pis.h
  • PIS_TIMER1_OUTPUT_2 : ald_pis.h
  • PIS_TIMER1_OUTPUT_3 : ald_pis.h
  • PIS_TIMER1_OUTPUT_4 : ald_pis.h
  • PIS_TIMER1_TRIG : ald_pis.h
  • PIS_TIMER1_UPDATA : ald_pis.h
  • PIS_TIMER2_INPUT_1 : ald_pis.h
  • PIS_TIMER2_INPUT_2 : ald_pis.h
  • PIS_TIMER2_INPUT_3 : ald_pis.h
  • PIS_TIMER2_INPUT_4 : ald_pis.h
  • PIS_TIMER2_OUTPUT_1 : ald_pis.h
  • PIS_TIMER2_OUTPUT_2 : ald_pis.h
  • PIS_TIMER2_OUTPUT_3 : ald_pis.h
  • PIS_TIMER2_OUTPUT_4 : ald_pis.h
  • PIS_TIMER2_TRIG : ald_pis.h
  • PIS_TIMER2_UPDATA : ald_pis.h
  • PIS_TIMER3_INPUT_1 : ald_pis.h
  • PIS_TIMER3_INPUT_2 : ald_pis.h
  • PIS_TIMER3_INPUT_3 : ald_pis.h
  • PIS_TIMER3_INPUT_4 : ald_pis.h
  • PIS_TIMER3_OUTPUT_1 : ald_pis.h
  • PIS_TIMER3_OUTPUT_2 : ald_pis.h
  • PIS_TIMER3_OUTPUT_3 : ald_pis.h
  • PIS_TIMER3_OUTPUT_4 : ald_pis.h
  • PIS_TIMER3_TRIG : ald_pis.h
  • PIS_TIMER3_UPDATA : ald_pis.h
  • PIS_TIMER_CH1 : ald_pis.h
  • PIS_TIMER_CH2 : ald_pis.h
  • PIS_TIMER_CH3 : ald_pis.h
  • PIS_TIMER_CH4 : ald_pis.h
  • PIS_TRIG_RESERVE : ald_pis.h
  • pis_trig_t : ald_pis.h
  • PIS_UART0_IRDAOUT : ald_pis.h
  • PIS_UART0_RESERVE0 : ald_pis.h
  • PIS_UART0_RESERVE1 : ald_pis.h
  • PIS_UART0_RTSOUT : ald_pis.h
  • PIS_UART0_SYN_RECV : ald_pis.h
  • PIS_UART0_SYN_SEND : ald_pis.h
  • PIS_UART0_TX : ald_pis.h
  • PIS_UART0_TXOUT : ald_pis.h
  • PIS_UART1_IRDA : ald_pis.h
  • PIS_UART1_RESERVE0 : ald_pis.h
  • PIS_UART1_RESERVE1 : ald_pis.h
  • PIS_UART1_RTS : ald_pis.h
  • PIS_UART1_SYN_RECV : ald_pis.h
  • PIS_UART1_SYN_SEND : ald_pis.h
  • PIS_UART1_TX : ald_pis.h
  • PIS_UART1_TXOUT : ald_pis.h
  • PIS_UART2_IRDA : ald_pis.h
  • PIS_UART2_RESERVE0 : ald_pis.h
  • PIS_UART2_RESERVE1 : ald_pis.h
  • PIS_UART2_RTS : ald_pis.h
  • PIS_UART2_SYN_RECV : ald_pis.h
  • PIS_UART2_SYN_SEND : ald_pis.h
  • PIS_UART2_TX : ald_pis.h
  • PIS_UART2_TXOUT : ald_pis.h
  • PIS_UART3_IRDA : ald_pis.h
  • PIS_UART3_RESERVE0 : ald_pis.h
  • PIS_UART3_RESERVE1 : ald_pis.h
  • PIS_UART3_RTS : ald_pis.h
  • PIS_UART3_SYN_RECV : ald_pis.h
  • PIS_UART3_SYN_SEND : ald_pis.h
  • PIS_UART3_TX : ald_pis.h
  • PIS_UART3_TXOUT : ald_pis.h
  • PIS_UART4_RECV : ald_pis.h
  • PIS_UART4_SEND : ald_pis.h
  • PIS_UART4_TXOUT : ald_pis.h
  • PIS_UART5_RECV : ald_pis.h
  • PIS_UART5_SEND : ald_pis.h
  • PIS_UART5_TXOUT : ald_pis.h
  • PMEMR_CLEAR_MASK : ald_ebi.h
  • PMU_FLASH_MODE_IDLE : ald_pmu.h
  • PMU_FLASH_MODE_WAIT : ald_pmu.h
  • PMU_GET_LVD_STATUS : ald_pmu.h
  • PMU_LDO_18_DRV_HIGH : ald_pmu.h
  • PMU_LDO_18_DRV_LOW : ald_pmu.h
  • PMU_LDO_18_HOLD : ald_pmu.h
  • pmu_ldo_18_mode_t : ald_pmu.h
  • PMU_LDO_18_OFF : ald_pmu.h
  • PMU_LDO_LPMODE_OUTPUT_0_9 : ald_pmu.h
  • PMU_LDO_LPMODE_OUTPUT_1_0 : ald_pmu.h
  • PMU_LDO_LPMODE_OUTPUT_1_1 : ald_pmu.h
  • PMU_LDO_LPMODE_OUTPUT_1_2 : ald_pmu.h
  • pmu_ldo_lpmode_output_t : ald_pmu.h
  • pmu_lp_mode_t : ald_pmu.h
  • PMU_LP_STANDBY : ald_pmu.h
  • PMU_LP_STOP1 : ald_pmu.h
  • PMU_LP_STOP2 : ald_pmu.h
  • PMU_LPSTOP_DISABLE : ald_pmu.h
  • PMU_LPSTOP_ENABLE : ald_pmu.h
  • PMU_LVD_TRIGGER_FALLING_EDGE : ald_pmu.h
  • PMU_LVD_TRIGGER_HIGH_LEVEL : ald_pmu.h
  • PMU_LVD_TRIGGER_LOW_LEVEL : ald_pmu.h
  • pmu_lvd_trigger_mode_t : ald_pmu.h
  • PMU_LVD_TRIGGER_RISING_EDGE : ald_pmu.h
  • PMU_LVD_TRIGGER_RISING_FALLING : ald_pmu.h
  • PMU_LVD_VOL_SEL_2_2 : ald_pmu.h
  • PMU_LVD_VOL_SEL_2_4 : ald_pmu.h
  • PMU_LVD_VOL_SEL_2_6 : ald_pmu.h
  • PMU_LVD_VOL_SEL_2_8 : ald_pmu.h
  • PMU_LVD_VOL_SEL_3_0 : ald_pmu.h
  • PMU_LVD_VOL_SEL_3_2 : ald_pmu.h
  • PMU_LVD_VOL_SEL_3_4 : ald_pmu.h
  • PMU_LVD_VOL_SEL_3_6 : ald_pmu.h
  • PMU_LVD_VOL_SEL_3_8 : ald_pmu.h
  • PMU_LVD_VOL_SEL_4_0 : ald_pmu.h
  • PMU_LVD_VOL_SEL_4_2 : ald_pmu.h
  • PMU_LVD_VOL_SEL_4_4 : ald_pmu.h
  • PMU_LVD_VOL_SEL_4_6 : ald_pmu.h
  • PMU_LVD_VOL_SEL_4_8 : ald_pmu.h
  • PMU_LVD_VOL_SEL_EXT : ald_pmu.h
  • pmu_lvd_voltage_sel_t : ald_pmu.h
  • PMU_MTSTOP_DISABLE : ald_pmu.h
  • PMU_MTSTOP_ENABLE : ald_pmu.h
  • pmu_perh_power_t : ald_pmu.h
  • PMU_POWER_CAN : ald_pmu.h
  • PMU_POWER_QSPI : ald_pmu.h
  • PMU_POWER_ROM : ald_pmu.h
  • PMU_POWER_SRAM0 : ald_pmu.h
  • PMU_POWER_SRAM1 : ald_pmu.h
  • PMU_POWER_SRAM2 : ald_pmu.h
  • PMU_POWER_SRAM3 : ald_pmu.h
  • PMU_POWER_SRAM4 : ald_pmu.h
  • PMU_POWER_SRAM5 : ald_pmu.h
  • PMU_POWER_USB : ald_pmu.h
  • PMU_SR_RSTAT : ald_pmu.h
  • PMU_SR_STANDBYF : ald_pmu.h
  • PMU_SR_USBRDY : ald_pmu.h
  • PMU_SR_WUF : ald_pmu.h
  • PMU_STANDBY_LEVEL_HIGH : ald_bkpc.h
  • PMU_STANDBY_LEVEL_LOW : ald_bkpc.h
  • PMU_STANDBY_PORT_SEL_NONE : ald_bkpc.h
  • PMU_STANDBY_PORT_SEL_PA0 : ald_bkpc.h
  • PMU_STANDBY_PORT_SEL_PA1 : ald_bkpc.h
  • PMU_STANDBY_PORT_SEL_PA2 : ald_bkpc.h
  • PMU_STANDBY_PORT_SEL_PA3 : ald_bkpc.h
  • PMU_STANDBY_PORT_SEL_PA4 : ald_bkpc.h
  • PMU_STANDBY_PORT_SEL_PA5 : ald_bkpc.h
  • PMU_STANDBY_PORT_SEL_PA6 : ald_bkpc.h
  • PMU_STANDBY_PORT_SEL_PA7 : ald_bkpc.h
  • pmu_status_t : ald_pmu.h
  • PMU_VREF_DISABLE : ald_pmu.h
  • PMU_VREF_ENABLE : ald_pmu.h


ALD User Manual: Globals

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- q -

  • QSPI_AUTO_POLL_DISABLE : ald_qspi.h
  • QSPI_AUTO_POLL_ENABLE : ald_qspi.h
  • QSPI_CANCEL_INDIRECT_READ : ald_qspi.h
  • qspi_clear_flag_status() : ald_qspi.c
  • qspi_clk_div_t : ald_qspi.h
  • QSPI_CPHA_1E : ald_qspi.h
  • QSPI_CPHA_2E : ald_qspi.h
  • qspi_cpha_t : ald_qspi.h
  • QSPI_CPOL_H : ald_qspi.h
  • QSPI_CPOL_L : ald_qspi.h
  • qspi_cpol_t : ald_qspi.h
  • QSPI_CS_NSS0 : ald_qspi.h
  • QSPI_CS_NSS1 : ald_qspi.h
  • QSPI_CS_NSS2 : ald_qspi.h
  • QSPI_CS_NSS3 : ald_qspi.h
  • qspi_dac_config() : ald_qspi.c
  • QSPI_DAC_DISABLE : ald_qspi.h
  • QSPI_DAC_ENABLE : ald_qspi.h
  • qspi_data_sampled_t : ald_qspi.h
  • QSPI_DISABLE : ald_qspi.h
  • QSPI_DIV_10 : ald_qspi.h
  • QSPI_DIV_12 : ald_qspi.h
  • QSPI_DIV_14 : ald_qspi.h
  • QSPI_DIV_16 : ald_qspi.h
  • QSPI_DIV_18 : ald_qspi.h
  • QSPI_DIV_2 : ald_qspi.h
  • QSPI_DIV_20 : ald_qspi.h
  • QSPI_DIV_22 : ald_qspi.h
  • QSPI_DIV_24 : ald_qspi.h
  • QSPI_DIV_26 : ald_qspi.h
  • QSPI_DIV_28 : ald_qspi.h
  • QSPI_DIV_30 : ald_qspi.h
  • QSPI_DIV_32 : ald_qspi.h
  • QSPI_DIV_4 : ald_qspi.h
  • QSPI_DIV_6 : ald_qspi.h
  • QSPI_DIV_8 : ald_qspi.h
  • QSPI_DMA_DISABLE : ald_qspi.h
  • QSPI_DMA_ENABLE : ald_qspi.h
  • QSPI_ENABLE : ald_qspi.h
  • QSPI_FALLING_E : ald_qspi.h
  • qspi_flag_t : ald_qspi.h
  • qspi_get_flag_status() : ald_qspi.c
  • QSPI_IF_AHBAEF : ald_qspi.h
  • QSPI_IF_INDCF : ald_qspi.h
  • QSPI_IF_INDRRF : ald_qspi.h
  • QSPI_IF_INDRSFF : ald_qspi.h
  • QSPI_IF_INDTWF : ald_qspi.h
  • QSPI_IF_MODFF : ald_qspi.h
  • QSPI_IF_POLLF : ald_qspi.h
  • QSPI_IF_ROVF : ald_qspi.h
  • QSPI_IF_SRFFF : ald_qspi.h
  • QSPI_IF_SRFNEF : ald_qspi.h
  • QSPI_IF_STFFF : ald_qspi.h
  • QSPI_IF_STFNFF : ald_qspi.h
  • QSPI_IF_UDFF : ald_qspi.h
  • QSPI_IF_WPAF : ald_qspi.h
  • qspi_indrd_flag_t : ald_qspi.h
  • qspi_indrd_get_status() : ald_qspi.c
  • QSPI_INDRD_PROGRESS : ald_qspi.h
  • qspi_indrd_wait_flag() : ald_qspi.c
  • QSPI_INDWR_CPLT : ald_qspi.h
  • qspi_indwr_get_status() : ald_qspi.c
  • QSPI_INDWR_PROGRESS : ald_qspi.h
  • qspi_indwr_status_t : ald_qspi.h
  • qspi_indwr_wait_flag() : ald_qspi.c
  • QSPI_IT_AHBAEF : ald_qspi.h
  • QSPI_IT_INDCF : ald_qspi.h
  • QSPI_IT_INDRRF : ald_qspi.h
  • QSPI_IT_INDRSFF : ald_qspi.h
  • QSPI_IT_INDTWF : ald_qspi.h
  • QSPI_IT_MODFF : ald_qspi.h
  • QSPI_IT_POLLF : ald_qspi.h
  • QSPI_IT_ROVF : ald_qspi.h
  • QSPI_IT_SRFFF : ald_qspi.h
  • QSPI_IT_SRFNEF : ald_qspi.h
  • QSPI_IT_STFFF : ald_qspi.h
  • QSPI_IT_STFNFF : ald_qspi.h
  • qspi_it_t : ald_qspi.h
  • QSPI_IT_UDFF : ald_qspi.h
  • QSPI_IT_WPAF : ald_qspi.h
  • QSPI_LEGACY_SPI_DISABLE : ald_qspi.h
  • QSPI_LEGACY_SPI_ENABLE : ald_qspi.h
  • QSPI_MEMORY_ADDRESS : ald_qspi.h
  • QSPI_MULTI_CHIP : ald_qspi.h
  • QSPI_NSS_1G : ald_qspi.h
  • QSPI_NSS_2G : ald_qspi.h
  • QSPI_NSS_4G : ald_qspi.h
  • QSPI_NSS_512M : ald_qspi.h
  • qspi_nss_decode_t : ald_qspi.h
  • qspi_nss_size_t : ald_qspi.h
  • qspi_nss_t : ald_qspi.h
  • QSPI_RD_CPLT : ald_qspi.h
  • qspi_read_sram_fill_level() : ald_qspi.c
  • QSPI_RISING_E : ald_qspi.h
  • QSPI_SINGLE_CHIP : ald_qspi.h
  • QSPI_SRAM_DEPTH : ald_qspi.h
  • QSPI_SRAM_RD : ald_qspi.h
  • QSPI_SRAM_SIZE : ald_qspi.h
  • qspi_sram_t : ald_qspi.h
  • QSPI_SRAM_WR : ald_qspi.h
  • QSPI_STATE_BUSY_RX : ald_qspi.h
  • QSPI_STATE_BUSY_TX : ald_qspi.h
  • qspi_state_t : ald_qspi.h
  • QSPI_TIMEOUT_DEFAULT_VALUE : ald_qspi.h
  • qspi_wait_for_idle() : ald_qspi.c
  • QSPI_WRITE_PROTECT_DISABLE : ald_qspi.h
  • QSPI_WRITE_PROTECT_ENABLE : ald_qspi.h
  • QSPI_XFER_DUAL : ald_qspi.h
  • QSPI_XFER_QUAD : ald_qspi.h
  • QSPI_XFER_SINGLE : ald_qspi.h
  • qspi_xfer_t : ald_qspi.h


ALD User Manual: Globals

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- r -

  • RAM_MEM_BASE : type.h
  • READ_BIT : type.h
  • READ_BITS : type.h
  • READ_REG : type.h
  • RESET : type.h
  • RESET_HANDLE_STATE : utils.h
  • rmu_bor_filter_t : ald_rmu.h
  • rmu_bor_vol_t : ald_rmu.h
  • RMU_BORFLT_1 : ald_rmu.h
  • RMU_BORFLT_2 : ald_rmu.h
  • RMU_BORFLT_3 : ald_rmu.h
  • RMU_BORFLT_4 : ald_rmu.h
  • RMU_BORFLT_5 : ald_rmu.h
  • RMU_BORFLT_6 : ald_rmu.h
  • RMU_BORFLT_7 : ald_rmu.h
  • RMU_PERH_ACMP0 : ald_rmu.h
  • RMU_PERH_ACMP1 : ald_rmu.h
  • RMU_PERH_ACMP2 : ald_rmu.h
  • RMU_PERH_ADC0 : ald_rmu.h
  • RMU_PERH_ADC1 : ald_rmu.h
  • RMU_PERH_BKPC : ald_rmu.h
  • RMU_PERH_BKPRAM : ald_rmu.h
  • RMU_PERH_CALC : ald_rmu.h
  • RMU_PERH_CAN0 : ald_rmu.h
  • RMU_PERH_CHIP : ald_rmu.h
  • RMU_PERH_CPU : ald_rmu.h
  • RMU_PERH_CRC : ald_rmu.h
  • RMU_PERH_CRYPT : ald_rmu.h
  • RMU_PERH_DAC0 : ald_rmu.h
  • RMU_PERH_EBI : ald_rmu.h
  • RMU_PERH_ECC : ald_rmu.h
  • RMU_PERH_GPIO : ald_rmu.h
  • RMU_PERH_I2C0 : ald_rmu.h
  • RMU_PERH_I2C1 : ald_rmu.h
  • RMU_PERH_IWDT : ald_rmu.h
  • RMU_PERH_LCD : ald_rmu.h
  • RMU_PERH_LPTIM0 : ald_rmu.h
  • RMU_PERH_LPUART0 : ald_rmu.h
  • RMU_PERH_OPAMP : ald_rmu.h
  • RMU_PERH_PIS : ald_rmu.h
  • RMU_PERH_QSPI : ald_rmu.h
  • RMU_PERH_RTC : ald_rmu.h
  • RMU_PERH_SPI0 : ald_rmu.h
  • RMU_PERH_SPI1 : ald_rmu.h
  • RMU_PERH_SPI2 : ald_rmu.h
  • RMU_PERH_TIMER0 : ald_rmu.h
  • RMU_PERH_TIMER1 : ald_rmu.h
  • RMU_PERH_TIMER2 : ald_rmu.h
  • RMU_PERH_TIMER3 : ald_rmu.h
  • RMU_PERH_TIMER4 : ald_rmu.h
  • RMU_PERH_TIMER5 : ald_rmu.h
  • RMU_PERH_TIMER6 : ald_rmu.h
  • RMU_PERH_TIMER7 : ald_rmu.h
  • RMU_PERH_TRNG : ald_rmu.h
  • RMU_PERH_TSENSE : ald_rmu.h
  • RMU_PERH_UART0 : ald_rmu.h
  • RMU_PERH_UART1 : ald_rmu.h
  • RMU_PERH_UART2 : ald_rmu.h
  • RMU_PERH_UART3 : ald_rmu.h
  • RMU_PERH_UART4 : ald_rmu.h
  • RMU_PERH_UART5 : ald_rmu.h
  • RMU_PERH_USB : ald_rmu.h
  • RMU_PERH_WWDT : ald_rmu.h
  • rmu_peripheral_t : ald_rmu.h
  • RMU_RST_ALL : ald_rmu.h
  • RMU_RST_BOR : ald_rmu.h
  • RMU_RST_CFG : ald_rmu.h
  • RMU_RST_CFGERR : ald_rmu.h
  • RMU_RST_CHIP : ald_rmu.h
  • RMU_RST_CPU : ald_rmu.h
  • RMU_RST_IWDT : ald_rmu.h
  • RMU_RST_LOCKUP : ald_rmu.h
  • RMU_RST_MCU : ald_rmu.h
  • RMU_RST_NMRST : ald_rmu.h
  • RMU_RST_POR : ald_rmu.h
  • RMU_RST_WAKEUP : ald_rmu.h
  • RMU_RST_WWDT : ald_rmu.h
  • rmu_state_t : ald_rmu.h
  • RMU_VOL_2_0 : ald_rmu.h
  • RMU_VOL_2_2 : ald_rmu.h
  • RMU_VOL_2_4 : ald_rmu.h
  • RMU_VOL_2_6 : ald_rmu.h
  • RMU_VOL_2_8 : ald_rmu.h
  • RMU_VOL_3_0 : ald_rmu.h
  • RMU_VOL_3_2 : ald_rmu.h
  • RMU_VOL_3_4 : ald_rmu.h
  • RMU_VOL_3_6 : ald_rmu.h
  • RMU_VOL_3_8 : ald_rmu.h
  • RMU_VOL_4_0 : ald_rmu.h
  • RMU_VOL_4_2 : ald_rmu.h
  • RMU_VOL_4_4 : ald_rmu.h
  • RMU_VOL_4_6 : ald_rmu.h
  • RMU_VOL_4_8 : ald_rmu.h
  • RMU_VOL_NONE : ald_rmu.h
  • RTC_ALARM_A : ald_rtc.h
  • RTC_ALARM_B : ald_rtc.h
  • rtc_alarm_idx_t : ald_rtc.h
  • RTC_ALARM_MASK_ALL : ald_rtc.h
  • RTC_ALARM_MASK_HOUR : ald_rtc.h
  • RTC_ALARM_MASK_MINUTE : ald_rtc.h
  • RTC_ALARM_MASK_NONE : ald_rtc.h
  • RTC_ALARM_MASK_SECOND : ald_rtc.h
  • rtc_alarm_mask_t : ald_rtc.h
  • RTC_ALARM_MASK_WEEK_DAY : ald_rtc.h
  • RTC_ALARM_SS_MASK_14 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_1 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_10 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_11 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_12 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_13 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_2 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_3 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_4 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_5 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_6 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_7 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_8 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_9 : ald_rtc.h
  • RTC_ALARM_SS_MASK_ALL : ald_rtc.h
  • RTC_ALARM_SS_MASK_NONE : ald_rtc.h
  • RTC_BY_PASS_DISABLE : ald_rtc.h
  • RTC_BY_PASS_ENABLE : ald_rtc.h
  • RTC_CALI_CALC_2 : ald_rtc.h
  • RTC_CALI_CALC_4 : ald_rtc.h
  • RTC_CALI_CALC_FREQ_10_MIN : ald_rtc.h
  • RTC_CALI_CALC_FREQ_10_SEC : ald_rtc.h
  • RTC_CALI_CALC_FREQ_1_HOUR : ald_rtc.h
  • RTC_CALI_CALC_FREQ_1_MIN : ald_rtc.h
  • RTC_CALI_CALC_FREQ_20_MIN : ald_rtc.h
  • RTC_CALI_CALC_FREQ_20_SEC : ald_rtc.h
  • RTC_CALI_CALC_FREQ_2_MIN : ald_rtc.h
  • RTC_CALI_CALC_FREQ_5_MIN : ald_rtc.h
  • rtc_cali_calc_freq_t : ald_rtc.h
  • rtc_cali_calc_t : ald_rtc.h
  • RTC_CALI_FREQ_10_MIN : ald_rtc.h
  • RTC_CALI_FREQ_10_SEC : ald_rtc.h
  • RTC_CALI_FREQ_1_MIN : ald_rtc.h
  • RTC_CALI_FREQ_1_SEC : ald_rtc.h
  • RTC_CALI_FREQ_20_MIN : ald_rtc.h
  • RTC_CALI_FREQ_20_SEC : ald_rtc.h
  • RTC_CALI_FREQ_2_MIN : ald_rtc.h
  • RTC_CALI_FREQ_5_MIN : ald_rtc.h
  • rtc_cali_freq_t : ald_rtc.h
  • RTC_CALI_LOCK : ald_rtc.h
  • RTC_CALI_MODE_NORMAL : ald_rtchw.h
  • RTC_CALI_MODE_SLEEP : ald_rtchw.h
  • RTC_CALI_TC_AUTO_BY_HW : ald_rtc.h
  • RTC_CALI_TC_AUTO_BY_HW_SF : ald_rtc.h
  • RTC_CALI_TC_AUTO_BY_SF : ald_rtc.h
  • RTC_CALI_TC_NONE : ald_rtc.h
  • rtc_cali_tc_t : ald_rtc.h
  • RTC_CALI_UNLOCK : ald_rtc.h
  • RTC_CLOCK_OUTPUT_1 : ald_rtc.h
  • RTC_CLOCK_OUTPUT_1024 : ald_rtc.h
  • RTC_CLOCK_OUTPUT_32 : ald_rtc.h
  • RTC_CLOCK_OUTPUT_32768 : ald_rtc.h
  • RTC_CLOCK_OUTPUT_CAL_1 : ald_rtc.h
  • RTC_CLOCK_OUTPUT_EXA_1 : ald_rtc.h
  • rtc_clock_output_t : ald_rtc.h
  • rtc_consistency_check() : ald_rtc.c
  • rtc_flag_t : ald_rtc.h
  • RTC_FORMAT_BCD : ald_rtc.h
  • RTC_FORMAT_DEC : ald_rtc.h
  • rtc_format_t : ald_rtc.h
  • RTC_HOUR_FORMAT_12 : ald_rtc.h
  • RTC_HOUR_FORMAT_24 : ald_rtc.h
  • rtc_hour_format_t : ald_rtc.h
  • rtc_hw_auto_check() : ald_rtchw.c
  • rtc_hw_cali_mode_t : ald_rtchw.h
  • RTC_IF_ALMA : ald_rtc.h
  • RTC_IF_ALMB : ald_rtc.h
  • RTC_IF_DAY : ald_rtc.h
  • RTC_IF_HR : ald_rtc.h
  • RTC_IF_MIN : ald_rtc.h
  • RTC_IF_MON : ald_rtc.h
  • RTC_IF_RSC : ald_rtc.h
  • RTC_IF_SEC : ald_rtc.h
  • RTC_IF_SFC : ald_rtc.h
  • RTC_IF_TCC : ald_rtc.h
  • RTC_IF_TCE : ald_rtc.h
  • RTC_IF_TP0 : ald_rtc.h
  • RTC_IF_TP1 : ald_rtc.h
  • RTC_IF_TS : ald_rtc.h
  • RTC_IF_TSOV : ald_rtc.h
  • RTC_IF_WU : ald_rtc.h
  • RTC_IF_YR : ald_rtc.h
  • RTC_IT_ALMA : ald_rtc.h
  • RTC_IT_ALMB : ald_rtc.h
  • RTC_IT_DAY : ald_rtc.h
  • RTC_IT_HR : ald_rtc.h
  • RTC_IT_MIN : ald_rtc.h
  • RTC_IT_MON : ald_rtc.h
  • RTC_IT_RSC : ald_rtc.h
  • RTC_IT_SEC : ald_rtc.h
  • RTC_IT_SFC : ald_rtc.h
  • rtc_it_t : ald_rtc.h
  • RTC_IT_TCC : ald_rtc.h
  • RTC_IT_TCE : ald_rtc.h
  • RTC_IT_TP0 : ald_rtc.h
  • RTC_IT_TP1 : ald_rtc.h
  • RTC_IT_TS : ald_rtc.h
  • RTC_IT_TSOV : ald_rtc.h
  • RTC_IT_WU : ald_rtc.h
  • RTC_IT_YR : ald_rtc.h
  • RTC_LOCK : ald_rtc.h
  • RTC_OUTPUT_ALARM_A : ald_rtc.h
  • RTC_OUTPUT_ALARM_B : ald_rtc.h
  • RTC_OUTPUT_DISABLE : ald_rtc.h
  • RTC_OUTPUT_POLARITY_HIGH : ald_rtc.h
  • RTC_OUTPUT_POLARITY_LOW : ald_rtc.h
  • rtc_output_polarity_t : ald_rtc.h
  • rtc_output_select_t : ald_rtc.h
  • RTC_OUTPUT_WAKEUP : ald_rtc.h
  • RTC_SELECT_DAY : ald_rtc.h
  • RTC_SELECT_WEEK : ald_rtc.h
  • RTC_SOURCE_HOSC_DIV_1M : ald_rtc.h
  • RTC_SOURCE_HRC_DIV_1M : ald_rtc.h
  • RTC_SOURCE_LOSC : ald_rtc.h
  • RTC_SOURCE_LRC : ald_rtc.h
  • rtc_source_sel_t : ald_rtc.h
  • rtc_sub_second_mask_t : ald_rtc.h
  • RTC_SUMMER_TIME_DISABLE : ald_rtc.h
  • RTC_SUMMER_TIME_ENABLE : ald_rtc.h
  • RTC_TAMPER_0 : ald_rtc.h
  • RTC_TAMPER_1 : ald_rtc.h
  • RTC_TAMPER_DURATION_1 : ald_rtc.h
  • RTC_TAMPER_DURATION_2 : ald_rtc.h
  • RTC_TAMPER_DURATION_4 : ald_rtc.h
  • RTC_TAMPER_DURATION_8 : ald_rtc.h
  • rtc_tamper_duration_t : ald_rtc.h
  • rtc_tamper_idx_t : ald_rtc.h
  • RTC_TAMPER_SAMPLING_FREQ_1024 : ald_rtc.h
  • RTC_TAMPER_SAMPLING_FREQ_16384 : ald_rtc.h
  • RTC_TAMPER_SAMPLING_FREQ_2048 : ald_rtc.h
  • RTC_TAMPER_SAMPLING_FREQ_256 : ald_rtc.h
  • RTC_TAMPER_SAMPLING_FREQ_32768 : ald_rtc.h
  • RTC_TAMPER_SAMPLING_FREQ_4096 : ald_rtc.h
  • RTC_TAMPER_SAMPLING_FREQ_512 : ald_rtc.h
  • RTC_TAMPER_SAMPLING_FREQ_8192 : ald_rtc.h
  • rtc_tamper_sampling_freq_t : ald_rtc.h
  • RTC_TAMPER_TRIGGER_HIGH : ald_rtc.h
  • RTC_TAMPER_TRIGGER_LOW : ald_rtc.h
  • rtc_tamper_trigger_t : ald_rtc.h
  • RTC_TIMEOUT_VALUE : ald_rtc.h
  • RTC_TS_FALLING_EDGE : ald_rtc.h
  • RTC_TS_RISING_EDGE : ald_rtc.h
  • rtc_ts_signal_sel_t : ald_rtc.h
  • RTC_TS_SIGNAL_SEL_TAMPER0 : ald_rtc.h
  • RTC_TS_SIGNAL_SEL_TAMPER1 : ald_rtc.h
  • rtc_ts_trigger_style_t : ald_rtc.h
  • RTC_UNLOCK : ald_rtc.h
  • RTC_WAKEUP_CLOCK_1HZ : ald_rtc.h
  • RTC_WAKEUP_CLOCK_1HZ_PULS : ald_rtc.h
  • RTC_WAKEUP_CLOCK_DIV_16 : ald_rtc.h
  • RTC_WAKEUP_CLOCK_DIV_2 : ald_rtc.h
  • RTC_WAKEUP_CLOCK_DIV_4 : ald_rtc.h
  • RTC_WAKEUP_CLOCK_DIV_8 : ald_rtc.h
  • rtc_wakeup_clock_t : ald_rtc.h
  • rtc_week_day_sel_t : ald_rtc.h
  • RTC_WINTER_TIME_DISABLE : ald_rtc.h
  • RTC_WINTER_TIME_ENABLE : ald_rtc.h
  • RTCINFO : ald_rtchw.h


ALD User Manual: Globals

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- s -

  • scard_clk_div_t : ald_uart.h
  • SCARD_CLOCK_DIV1 : ald_uart.h
  • SCARD_CLOCK_DIV2 : ald_uart.h
  • SCARD_CLOCK_DIV4 : ald_uart.h
  • SCARD_CLOCK_DIV6 : ald_uart.h
  • SCARD_RETRY_CNT0 : ald_uart.h
  • SCARD_RETRY_CNT1 : ald_uart.h
  • SCARD_RETRY_CNT2 : ald_uart.h
  • SCARD_RETRY_CNT3 : ald_uart.h
  • SCARD_RETRY_CNT4 : ald_uart.h
  • SCARD_RETRY_CNT5 : ald_uart.h
  • SCARD_RETRY_CNT6 : ald_uart.h
  • SCARD_RETRY_CNT7 : ald_uart.h
  • scard_retry_t : ald_uart.h
  • SET : type.h
  • SET_BIT : type.h
  • SPI_1LINE_RX : ald_spi.h
  • SPI_1LINE_TX : ald_spi.h
  • SPI_BAUD_128 : ald_spi.h
  • SPI_BAUD_16 : ald_spi.h
  • SPI_BAUD_2 : ald_spi.h
  • SPI_BAUD_256 : ald_spi.h
  • SPI_BAUD_32 : ald_spi.h
  • SPI_BAUD_4 : ald_spi.h
  • SPI_BAUD_64 : ald_spi.h
  • SPI_BAUD_8 : ald_spi.h
  • spi_baud_t : ald_spi.h
  • SPI_CPHA_FIRST : ald_spi.h
  • SPI_CPHA_SECOND : ald_spi.h
  • spi_cpha_t : ald_spi.h
  • SPI_CPOL_HIGH : ald_spi.h
  • SPI_CPOL_LOW : ald_spi.h
  • spi_cpol_t : ald_spi.h
  • SPI_CRC_RESET : ald_spi.h
  • SPI_CRCNEXT_DISABLE : ald_spi.h
  • SPI_CRCNEXT_ENABLE : ald_spi.h
  • SPI_DATA_SIZE_16 : ald_spi.h
  • SPI_DATA_SIZE_8 : ald_spi.h
  • spi_datasize_t : ald_spi.h
  • SPI_DIRECTION_1LINE : ald_spi.h
  • SPI_DIRECTION_1LINE_RX : ald_spi.h
  • SPI_DIRECTION_2LINES : ald_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : ald_spi.h
  • spi_direction_t : ald_spi.h
  • SPI_DISABLE : ald_spi.h
  • spi_dma_recv_cplt() : ald_spi.c
  • SPI_DMA_REQ_RX : ald_spi.h
  • spi_dma_req_t : ald_spi.h
  • SPI_DMA_REQ_TX : ald_spi.h
  • spi_dma_send_cplt() : ald_spi.c
  • spi_dma_send_recv_cplt() : ald_spi.c
  • SPI_ENABLE : ald_spi.h
  • SPI_ERROR_CRC : ald_spi.h
  • SPI_ERROR_FLAG : ald_spi.h
  • SPI_ERROR_FRE : ald_spi.h
  • SPI_ERROR_MODF : ald_spi.h
  • SPI_ERROR_NONE : ald_spi.h
  • SPI_ERROR_RXOV : ald_spi.h
  • spi_error_t : ald_spi.h
  • SPI_ERROR_TXOV : ald_spi.h
  • spi_fifo_threshold_config() : ald_spi.c
  • SPI_FIRSTBIT_LSB : ald_spi.h
  • SPI_FIRSTBIT_MSB : ald_spi.h
  • spi_firstbit_t : ald_spi.h
  • spi_flag_t : ald_spi.h
  • SPI_FRAME_MOTOROLA : ald_spi.h
  • spi_frame_t : ald_spi.h
  • SPI_FRAME_TI : ald_spi.h
  • spi_get_status() : ald_spi.c
  • spi_handle_t : ald_spi.h
  • SPI_IF_CRCERR : ald_spi.h
  • SPI_IF_FRE : ald_spi.h
  • SPI_IF_MODF : ald_spi.h
  • SPI_IF_RXF : ald_spi.h
  • SPI_IF_RXOV : ald_spi.h
  • SPI_IF_RXTH : ald_spi.h
  • SPI_IF_RXUD : ald_spi.h
  • SPI_IF_TXE : ald_spi.h
  • SPI_IF_TXOV : ald_spi.h
  • SPI_IF_TXTH : ald_spi.h
  • SPI_IF_TXUD : ald_spi.h
  • SPI_IT_CRCERR : ald_spi.h
  • SPI_IT_FRE : ald_spi.h
  • SPI_IT_MODF : ald_spi.h
  • SPI_IT_RXF : ald_spi.h
  • SPI_IT_RXOV : ald_spi.h
  • SPI_IT_RXTH : ald_spi.h
  • SPI_IT_RXUD : ald_spi.h
  • spi_it_t : ald_spi.h
  • SPI_IT_TXE : ald_spi.h
  • SPI_IT_TXOV : ald_spi.h
  • SPI_IT_TXTH : ald_spi.h
  • SPI_IT_TXUD : ald_spi.h
  • SPI_MODE_MASTER : ald_spi.h
  • SPI_MODE_SLAVER : ald_spi.h
  • spi_mode_t : ald_spi.h
  • SPI_RESET_HANDLE_STATE : ald_spi.h
  • SPI_RXONLY_DISABLE : ald_spi.h
  • SPI_RXONLY_ENABLE : ald_spi.h
  • SPI_SR_RXNE : ald_spi.h
  • spi_sr_status_t : ald_spi.h
  • SPI_SR_TXE : ald_spi.h
  • SPI_SR_TXE_RXNE : ald_spi.h
  • SPI_SSI_HIGH : ald_spi.h
  • SPI_SSI_LOW : ald_spi.h
  • SPI_SSOE_DISABLE : ald_spi.h
  • SPI_SSOE_ENABLE : ald_spi.h
  • SPI_STATE_BUSY : ald_spi.h
  • SPI_STATE_BUSY_RX : ald_spi.h
  • SPI_STATE_BUSY_TX : ald_spi.h
  • SPI_STATE_BUSY_TX_RX : ald_spi.h
  • SPI_STATE_ERROR : ald_spi.h
  • SPI_STATE_READY : ald_spi.h
  • SPI_STATE_RESET : ald_spi.h
  • spi_state_t : ald_spi.h
  • SPI_STATE_TIMEOUT : ald_spi.h
  • SPI_STATUS_BUSY : ald_spi.h
  • SPI_STATUS_RXE : ald_spi.h
  • SPI_STATUS_RXF : ald_spi.h
  • SPI_STATUS_RXOV : ald_spi.h
  • SPI_STATUS_RXTH : ald_spi.h
  • SPI_STATUS_RXUD : ald_spi.h
  • spi_status_t : ald_spi.h
  • SPI_STATUS_TXE : ald_spi.h
  • SPI_STATUS_TXF : ald_spi.h
  • SPI_STATUS_TXOV : ald_spi.h
  • SPI_STATUS_TXTH : ald_spi.h
  • SPI_STATUS_TXUD : ald_spi.h
  • spi_wait_bsy_flag() : ald_spi.c
  • spi_wait_flag_irq() : ald_spi.c
  • SYSCFG_BOOTFLASH_MAPPING_DISABLE : ald_syscfg.h
  • SYSCFG_BOOTFLASH_MAPPING_ENABLE : ald_syscfg.h
  • SYSCFG_LOCK : ald_syscfg.h
  • SYSCFG_UNLOCK : ald_syscfg.h
  • SYSTICK_INTERVAL_1000MS : utils.h
  • SYSTICK_INTERVAL_100MS : utils.h
  • SYSTICK_INTERVAL_10MS : utils.h
  • SYSTICK_INTERVAL_1MS : utils.h
  • systick_interval_t : utils.h


ALD User Manual: Globals

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- t -

  • TICK_INT_PRIORITY : ald_conf.h
  • TIMEOUT : utils.h
  • TIMER_ACTIVE_CHANNEL_1 : ald_timer.h
  • TIMER_ACTIVE_CHANNEL_2 : ald_timer.h
  • TIMER_ACTIVE_CHANNEL_3 : ald_timer.h
  • TIMER_ACTIVE_CHANNEL_4 : ald_timer.h
  • TIMER_ACTIVE_CHANNEL_CLEARED : ald_timer.h
  • timer_active_channel_t : ald_timer.h
  • timer_base_set_config() : ald_timer.c
  • TIMER_BREAK_POLARITY_HIGH : ald_timer.h
  • TIMER_BREAK_POLARITY_LOW : ald_timer.h
  • timer_break_polarity_t : ald_timer.h
  • timer_ccx_channel_cmd() : ald_timer.c
  • TIMER_CCx_DISABLE : ald_timer.h
  • TIMER_CCx_DMA_REQ_CCx : ald_timer.h
  • TIMER_CCx_DMA_REQ_UPDATE : ald_timer.h
  • TIMER_CCx_ENABLE : ald_timer.h
  • timer_ccxn_channel_cmd() : ald_timer.c
  • TIMER_CCxN_DISABLE : ald_timer.h
  • TIMER_CCxN_ENABLE : ald_timer.h
  • TIMER_CHANNEL_1 : ald_timer.h
  • TIMER_CHANNEL_2 : ald_timer.h
  • TIMER_CHANNEL_3 : ald_timer.h
  • TIMER_CHANNEL_4 : ald_timer.h
  • TIMER_CHANNEL_ALL : ald_timer.h
  • timer_channel_t : ald_timer.h
  • TIMER_CHNREF_CLR_CMP_IN : ald_timer.h
  • TIMER_CHNREF_CLR_ETF : ald_timer.h
  • timer_chnref_clr_sel_t : ald_timer.h
  • timer_clear_input_polarity_t : ald_timer.h
  • timer_clear_input_source_t : ald_timer.h
  • TIMER_CLK_POLARITY_BOTH : ald_timer.h
  • TIMER_CLK_POLARITY_FALL : ald_timer.h
  • TIMER_CLK_POLARITY_INV : ald_timer.h
  • TIMER_CLK_POLARITY_NO_INV : ald_timer.h
  • TIMER_CLK_POLARITY_RISE : ald_timer.h
  • TIMER_CLOCK_DIV1 : ald_timer.h
  • TIMER_CLOCK_DIV2 : ald_timer.h
  • TIMER_CLOCK_DIV4 : ald_timer.h
  • timer_clock_division_t : ald_timer.h
  • timer_clock_polarity_t : ald_timer.h
  • timer_clock_source_t : ald_timer.h
  • TIMER_CNT_MODE_CENTER1 : ald_timer.h
  • TIMER_CNT_MODE_CENTER2 : ald_timer.h
  • TIMER_CNT_MODE_CENTER3 : ald_timer.h
  • TIMER_CNT_MODE_DOWN : ald_timer.h
  • timer_cnt_mode_t : ald_timer.h
  • TIMER_CNT_MODE_UP : ald_timer.h
  • TIMER_DISABLE : ald_timer.h
  • timer_dma_capture_cplt() : ald_timer.c
  • TIMER_DMA_CC1 : ald_timer.h
  • TIMER_DMA_CC2 : ald_timer.h
  • TIMER_DMA_CC3 : ald_timer.h
  • TIMER_DMA_CC4 : ald_timer.h
  • TIMER_DMA_COM : ald_timer.h
  • timer_dma_error() : ald_timer.c
  • timer_dma_msel() : ald_timer.c
  • timer_dma_oc_cplt() : ald_timer.c
  • timer_dma_period_elapse_cplt() : ald_timer.c
  • timer_dma_req_t : ald_timer.h
  • TIMER_DMA_TRIGGER : ald_timer.h
  • TIMER_DMA_UPDATE : ald_timer.h
  • TIMER_ENABLE : ald_timer.h
  • TIMER_ENC_MODE_TI1 : ald_timer.h
  • TIMER_ENC_MODE_TI12 : ald_timer.h
  • TIMER_ENC_MODE_TI2 : ald_timer.h
  • timer_encoder_mode_t : ald_timer.h
  • TIMER_ETR_PSC_DIV1 : ald_timer.h
  • TIMER_ETR_PSC_DIV2 : ald_timer.h
  • TIMER_ETR_PSC_DIV4 : ald_timer.h
  • TIMER_ETR_PSC_DIV8 : ald_timer.h
  • timer_etr_psc_t : ald_timer.h
  • timer_etr_set_config() : ald_timer.c
  • timer_event_source_t : ald_timer.h
  • TIMER_FLAG_BREAK : ald_timer.h
  • TIMER_FLAG_CC1 : ald_timer.h
  • TIMER_FLAG_CC1OF : ald_timer.h
  • TIMER_FLAG_CC2 : ald_timer.h
  • TIMER_FLAG_CC2OF : ald_timer.h
  • TIMER_FLAG_CC3 : ald_timer.h
  • TIMER_FLAG_CC3OF : ald_timer.h
  • TIMER_FLAG_CC4 : ald_timer.h
  • TIMER_FLAG_CC4OF : ald_timer.h
  • TIMER_FLAG_COM : ald_timer.h
  • timer_flag_t : ald_timer.h
  • TIMER_FLAG_TRIGGER : ald_timer.h
  • TIMER_FLAG_UPDATE : ald_timer.h
  • TIMER_GET_AUTORELOAD : ald_timer.h
  • TIMER_GET_CNT : ald_timer.h
  • TIMER_GET_DIR : ald_timer.h
  • timer_handle_t : ald_timer.h
  • TIMER_IC_POLARITY_FALL : ald_timer.h
  • TIMER_IC_POLARITY_RISE : ald_timer.h
  • timer_ic_polarity_t : ald_timer.h
  • timer_ic_prescaler_t : ald_timer.h
  • TIMER_IC_PSC_DIV1 : ald_timer.h
  • TIMER_IC_PSC_DIV2 : ald_timer.h
  • TIMER_IC_PSC_DIV4 : ald_timer.h
  • TIMER_IC_PSC_DIV8 : ald_timer.h
  • TIMER_IC_SEL_DIRECT : ald_timer.h
  • TIMER_IC_SEL_INDIRECT : ald_timer.h
  • TIMER_IC_SEL_TRC : ald_timer.h
  • timer_ic_select_t : ald_timer.h
  • TIMER_INPUT_ETR : ald_timer.h
  • TIMER_INPUT_NONE : ald_timer.h
  • TIMER_IT_BREAK : ald_timer.h
  • TIMER_IT_CC1 : ald_timer.h
  • TIMER_IT_CC2 : ald_timer.h
  • TIMER_IT_CC3 : ald_timer.h
  • TIMER_IT_CC4 : ald_timer.h
  • TIMER_IT_COM : ald_timer.h
  • timer_it_t : ald_timer.h
  • TIMER_IT_TRIGGER : ald_timer.h
  • TIMER_IT_UPDATE : ald_timer.h
  • TIMER_LOCK_LEVEL_1 : ald_timer.h
  • TIMER_LOCK_LEVEL_2 : ald_timer.h
  • TIMER_LOCK_LEVEL_3 : ald_timer.h
  • TIMER_LOCK_LEVEL_OFF : ald_timer.h
  • timer_lock_level_t : ald_timer.h
  • timer_master_mode_sel_t : ald_timer.h
  • TIMER_MODE_DISABLE : ald_timer.h
  • TIMER_MODE_ENC1 : ald_timer.h
  • TIMER_MODE_ENC2 : ald_timer.h
  • TIMER_MODE_ENC3 : ald_timer.h
  • TIMER_MODE_EXTERNAL1 : ald_timer.h
  • TIMER_MODE_GATED : ald_timer.h
  • TIMER_MODE_RESET : ald_timer.h
  • TIMER_MODE_TRIG : ald_timer.h
  • TIMER_MOE_DISABLE : ald_timer.h
  • TIMER_MOE_ENABLE : ald_timer.h
  • timer_oc1_set_config() : ald_timer.c
  • timer_oc2_set_config() : ald_timer.c
  • timer_oc3_set_config() : ald_timer.c
  • timer_oc4_set_config() : ald_timer.c
  • TIMER_OC_IDLE_RESET : ald_timer.h
  • TIMER_OC_IDLE_SET : ald_timer.h
  • timer_oc_idle_t : ald_timer.h
  • TIMER_OC_MODE_ACTIVE : ald_timer.h
  • TIMER_OC_MODE_FORCE_ACTIVE : ald_timer.h
  • TIMER_OC_MODE_FORCE_INACTIVE : ald_timer.h
  • TIMER_OC_MODE_INACTIVE : ald_timer.h
  • TIMER_OC_MODE_PWM1 : ald_timer.h
  • TIMER_OC_MODE_PWM2 : ald_timer.h
  • timer_oc_mode_t : ald_timer.h
  • TIMER_OC_MODE_TIMERING : ald_timer.h
  • TIMER_OC_MODE_TOGGLE : ald_timer.h
  • TIMER_OC_POLARITY_HIGH : ald_timer.h
  • TIMER_OC_POLARITY_LOW : ald_timer.h
  • timer_oc_polarity_t : ald_timer.h
  • TIMER_OCN_IDLE_RESET : ald_timer.h
  • TIMER_OCN_IDLE_SET : ald_timer.h
  • timer_ocn_idle_t : ald_timer.h
  • TIMER_OCN_POLARITY_HIGH : ald_timer.h
  • TIMER_OCN_POLARITY_LOW : ald_timer.h
  • timer_ocn_polarity_t : ald_timer.h
  • TIMER_OP_MODE_REPEAT : ald_timer.h
  • TIMER_OP_MODE_SINGLE : ald_timer.h
  • timer_op_mode_t : ald_timer.h
  • TIMER_OP_OUTPUT_CHANNEL_1 : ald_timer.h
  • TIMER_OP_OUTPUT_CHANNEL_2 : ald_timer.h
  • timer_op_output_channel_t : ald_timer.h
  • TIMER_POLARITY_INV : ald_timer.h
  • TIMER_POLARITY_NO_INV : ald_timer.h
  • TIMER_RESET_HANDLE_STATE : ald_timer.h
  • TIMER_SET_AUTORELOAD : ald_timer.h
  • timer_slave_mode_t : ald_timer.h
  • timer_slave_set_config() : ald_timer.c
  • TIMER_SRC_BREAK : ald_timer.h
  • TIMER_SRC_CC1 : ald_timer.h
  • TIMER_SRC_CC2 : ald_timer.h
  • TIMER_SRC_CC3 : ald_timer.h
  • TIMER_SRC_CC4 : ald_timer.h
  • TIMER_SRC_COM : ald_timer.h
  • TIMER_SRC_ETRMODE1 : ald_timer.h
  • TIMER_SRC_ETRMODE2 : ald_timer.h
  • TIMER_SRC_INTER : ald_timer.h
  • TIMER_SRC_ITR0 : ald_timer.h
  • TIMER_SRC_ITR1 : ald_timer.h
  • TIMER_SRC_ITR2 : ald_timer.h
  • TIMER_SRC_ITR3 : ald_timer.h
  • TIMER_SRC_TI1 : ald_timer.h
  • TIMER_SRC_TI1ED : ald_timer.h
  • TIMER_SRC_TI2 : ald_timer.h
  • TIMER_SRC_TRIG : ald_timer.h
  • TIMER_SRC_UPDATE : ald_timer.h
  • TIMER_STATE_BUSY : ald_timer.h
  • TIMER_STATE_ERROR : ald_timer.h
  • TIMER_STATE_READY : ald_timer.h
  • TIMER_STATE_RESET : ald_timer.h
  • timer_state_t : ald_timer.h
  • TIMER_STATE_TIMEREOUT : ald_timer.h
  • timer_ti1_set_config() : ald_timer.c
  • timer_ti1_set_config_stage() : ald_timer.c
  • timer_ti2_set_config() : ald_timer.c
  • timer_ti2_set_config_stage() : ald_timer.c
  • timer_ti3_set_config() : ald_timer.c
  • timer_ti4_set_config() : ald_timer.c
  • TIMER_TRGO_ENABLE : ald_timer.h
  • TIMER_TRGO_OC1 : ald_timer.h
  • TIMER_TRGO_OC1REF : ald_timer.h
  • TIMER_TRGO_OC2REF : ald_timer.h
  • TIMER_TRGO_OC3REF : ald_timer.h
  • TIMER_TRGO_OC4REF : ald_timer.h
  • TIMER_TRGO_RESET : ald_timer.h
  • TIMER_TRGO_UPDATE : ald_timer.h
  • TIMER_TS_ETRF : ald_timer.h
  • TIMER_TS_ITR0 : ald_timer.h
  • TIMER_TS_ITR1 : ald_timer.h
  • TIMER_TS_ITR2 : ald_timer.h
  • TIMER_TS_ITR3 : ald_timer.h
  • timer_ts_t : ald_timer.h
  • TIMER_TS_TI1F_ED : ald_timer.h
  • TIMER_TS_TI1FP1 : ald_timer.h
  • TIMER_TS_TI2FP2 : ald_timer.h
  • TRNG_ADJM_DISABLE : ald_trng.h
  • TRNG_ADJM_ENABLE : ald_trng.h
  • trng_data_width_t : ald_trng.h
  • TRNG_DISABLE : ald_trng.h
  • TRNG_DSEL_16B : ald_trng.h
  • TRNG_DSEL_1B : ald_trng.h
  • TRNG_DSEL_32B : ald_trng.h
  • TRNG_DSEL_8B : ald_trng.h
  • TRNG_ENABLE : ald_trng.h
  • trng_flag_t : ald_trng.h
  • trng_handle_t : ald_trng.h
  • TRNG_IF_DAVLD : ald_trng.h
  • TRNG_IF_SERR : ald_trng.h
  • TRNG_IF_START : ald_trng.h
  • TRNG_IT_DAVLD : ald_trng.h
  • TRNG_IT_SERR : ald_trng.h
  • TRNG_IT_START : ald_trng.h
  • trng_it_t : ald_trng.h
  • trng_reset() : ald_trng.c
  • TRNG_SEED_TYPE_0 : ald_trng.h
  • TRNG_SEED_TYPE_1 : ald_trng.h
  • TRNG_SEED_TYPE_LAST : ald_trng.h
  • TRNG_SEED_TYPE_SEED : ald_trng.h
  • trng_seed_type_t : ald_trng.h
  • TRNG_STATE_BUSY : ald_trng.h
  • TRNG_STATE_ERROR : ald_trng.h
  • TRNG_STATE_READY : ald_trng.h
  • TRNG_STATE_RESET : ald_trng.h
  • trng_state_t : ald_trng.h
  • TRNG_STATUS_DAVLD : ald_trng.h
  • TRNG_STATUS_SERR : ald_trng.h
  • TRNG_STATUS_START : ald_trng.h
  • trng_status_t : ald_trng.h
  • TRUE : type.h
  • tsense_cbk : ald_tsense.h
  • TSENSE_CTN_DISABLE : ald_tsense.h
  • TSENSE_CTN_ENABLE : ald_tsense.h
  • TSENSE_DISABLE : ald_tsense.h
  • TSENSE_ENABLE : ald_tsense.h
  • TSENSE_HTGR_WR : ald_tsense.h
  • TSENSE_LOCK : ald_tsense.h , ald_rtchw.h
  • TSENSE_LTGR_WR : ald_tsense.h
  • TSENSE_OUTPUT_MODE_1600 : ald_tsense.h
  • TSENSE_OUTPUT_MODE_200 : ald_tsense.h
  • TSENSE_OUTPUT_MODE_3200 : ald_tsense.h
  • TSENSE_OUTPUT_MODE_400 : ald_tsense.h
  • TSENSE_OUTPUT_MODE_800 : ald_tsense.h
  • tsense_output_mode_t : ald_tsense.h
  • TSENSE_REQ_DISABLE : ald_tsense.h
  • TSENSE_REQ_ENABLE : ald_tsense.h
  • TSENSE_RESET : ald_tsense.h
  • TSENSE_SOURCE_LOSC : ald_tsense.h
  • TSENSE_SOURCE_LRC : ald_tsense.h
  • tsense_source_sel_t : ald_tsense.h
  • TSENSE_TBDR_WR : ald_tsense.h
  • TSENSE_TCALBDR_WR : ald_tsense.h
  • TSENSE_UNLOCK : ald_tsense.h , ald_rtchw.h
  • TSENSE_UPDATE_CYCLE_3 : ald_tsense.h
  • TSENSE_UPDATE_CYCLE_4 : ald_tsense.h
  • TSENSE_UPDATE_CYCLE_5 : ald_tsense.h
  • TSENSE_UPDATE_CYCLE_6 : ald_tsense.h
  • TSENSE_UPDATE_CYCLE_7 : ald_tsense.h
  • tsense_update_cycle_t : ald_tsense.h
  • type_bool_t : type.h
  • type_func_t : type.h


ALD User Manual: Globals

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- u -

  • UART_ABRMOD_0_TO_1 : ald_uart.h
  • UART_ABRMOD_1 : ald_uart.h
  • UART_ABRMOD_1_TO_0 : ald_uart.h
  • uart_auto_baud_mode_t : ald_uart.h
  • UART_AUTOBR_DISABLE : ald_uart.h
  • UART_AUTOBR_ENABLE : ald_uart.h
  • UART_AUTOBR_REPT : ald_uart.h
  • UART_DATA_INV_DISABLE : ald_uart.h
  • UART_DATA_INV_ENABLE : ald_uart.h
  • UART_DISABLE_SCARD_CLK : ald_uart.h
  • UART_DISABLE_SCARD_NACK : ald_uart.h
  • uart_dma_error() : ald_uart.c
  • uart_dma_recv_cplt() : ald_uart.c
  • UART_DMA_REQ_RX : ald_uart.h
  • uart_dma_req_t : ald_uart.h
  • UART_DMA_REQ_TX : ald_uart.h
  • uart_dma_send_cplt() : ald_uart.c
  • UART_ENABLE_SCARD_CLK : ald_uart.h
  • UART_ENABLE_SCARD_NACK : ald_uart.h
  • UART_ERROR_DMA : ald_uart.h
  • UART_ERROR_FE : ald_uart.h
  • UART_ERROR_NE : ald_uart.h
  • UART_ERROR_NONE : ald_uart.h
  • UART_ERROR_ORE : ald_uart.h
  • UART_ERROR_PE : ald_uart.h
  • uart_error_t : ald_uart.h
  • UART_FIFO_RX_RESET : ald_uart.h
  • UART_FIFO_TX_RESET : ald_uart.h
  • uart_flag_t : ald_uart.h
  • UART_GET_BRR_VALUE : ald_uart.h
  • uart_handle_t : ald_uart.h
  • UART_HDSEL_DISABLE : ald_uart.h
  • UART_HDSEL_ENABLE : ald_uart.h
  • UART_HW_FLOW_CTL_DISABLE : ald_uart.h
  • UART_HW_FLOW_CTL_ENABLE : ald_uart.h
  • uart_hw_flow_ctl_t : ald_uart.h
  • UART_IF_ABEND : ald_uart.h
  • UART_IF_ABTO : ald_uart.h
  • UART_IF_ADDRM : ald_uart.h
  • UART_IF_DCTS : ald_uart.h
  • UART_IF_EOB : ald_uart.h
  • UART_IF_LINBK : ald_uart.h
  • UART_IF_NOISE : ald_uart.h
  • UART_IF_RFFULL : ald_uart.h
  • UART_IF_RFOERR : ald_uart.h
  • UART_IF_RFTH : ald_uart.h
  • UART_IF_RFUERR : ald_uart.h
  • UART_IF_RXBERR : ald_uart.h
  • UART_IF_RXTO : ald_uart.h
  • UART_IF_TBC : ald_uart.h
  • UART_IF_TFEMPTY : ald_uart.h
  • UART_IF_TFOVER : ald_uart.h
  • UART_IF_TFTH : ald_uart.h
  • UART_IT_ABEND : ald_uart.h
  • UART_IT_ABTO : ald_uart.h
  • UART_IT_ADDRM : ald_uart.h
  • UART_IT_DCTS : ald_uart.h
  • UART_IT_EOB : ald_uart.h
  • UART_IT_LINBK : ald_uart.h
  • UART_IT_NOISE : ald_uart.h
  • UART_IT_RFFULL : ald_uart.h
  • UART_IT_RFOERR : ald_uart.h
  • UART_IT_RFTH : ald_uart.h
  • UART_IT_RFUERR : ald_uart.h
  • UART_IT_RXBERR : ald_uart.h
  • UART_IT_RXTO : ald_uart.h
  • uart_it_t : ald_uart.h
  • UART_IT_TFEMPTY : ald_uart.h
  • UART_IT_TFOVER : ald_uart.h
  • UART_IT_TFTH : ald_uart.h
  • UART_IT_TSEMPTY : ald_uart.h
  • uart_lin_break_detect_irq() : ald_uart.c
  • uart_lin_break_len_t : ald_uart.h
  • UART_LPBMOD_DISABLE : ald_uart.h
  • UART_LPBMOD_ENABLE : ald_uart.h
  • UART_MODE_HDSEL : ald_uart.h
  • UART_MODE_IrDA : ald_uart.h
  • UART_MODE_LIN : ald_uart.h
  • UART_MODE_RS485 : ald_uart.h
  • UART_MODE_SCARD : ald_uart.h
  • uart_mode_t : ald_uart.h
  • UART_MODE_UART : ald_uart.h
  • UART_MSB_FIRST_DISABLE : ald_uart.h
  • UART_MSB_FIRST_ENABLE : ald_uart.h
  • UART_PARITY_EVEN : ald_uart.h
  • UART_PARITY_NONE : ald_uart.h
  • UART_PARITY_ODD : ald_uart.h
  • uart_parity_t : ald_uart.h
  • UART_RX_DISABLE : ald_uart.h
  • UART_RX_ENABLE : ald_uart.h
  • UART_RX_INV_DISABLE : ald_uart.h
  • UART_RX_INV_ENABLE : ald_uart.h
  • UART_RX_TIMEOUT_DISABLE : ald_uart.h
  • UART_RX_TIMEOUT_ENABLE : ald_uart.h
  • UART_RXFIFO_14BYTE : ald_uart.h
  • UART_RXFIFO_1BYTE : ald_uart.h
  • UART_RXFIFO_4BYTE : ald_uart.h
  • UART_RXFIFO_8BYTE : ald_uart.h
  • uart_rxfifo_t : ald_uart.h
  • UART_SCARD_DISABLE : ald_uart.h
  • UART_SCARD_ENABLE : ald_uart.h
  • UART_SET_TIMEOUT_VALUE : ald_uart.h
  • UART_STATE_BUSY : ald_uart.h
  • UART_STATE_BUSY_RX : ald_uart.h
  • UART_STATE_BUSY_TX : ald_uart.h
  • UART_STATE_BUSY_TX_RX : ald_uart.h
  • UART_STATE_ERROR : ald_uart.h
  • UART_STATE_READY : ald_uart.h
  • UART_STATE_RESET : ald_uart.h
  • UART_STATE_RX_MASK : ald_uart.h
  • uart_state_t : ald_uart.h
  • UART_STATE_TIMEOUT : ald_uart.h
  • UART_STATE_TX_MASK : ald_uart.h
  • UART_STATUS_BKERR : ald_uart.h
  • UART_STATUS_CTSSTA : ald_uart.h
  • UART_STATUS_FERR : ald_uart.h
  • UART_STATUS_PERR : ald_uart.h
  • UART_STATUS_RFEMPTY : ald_uart.h
  • UART_STATUS_RFFULL : ald_uart.h
  • UART_STATUS_RFOERR : ald_uart.h
  • UART_STATUS_RFTH : ald_uart.h
  • UART_STATUS_RFUERR : ald_uart.h
  • UART_STATUS_RSBUSY : ald_uart.h
  • uart_status_t : ald_uart.h
  • UART_STATUS_TFEMPTY : ald_uart.h
  • UART_STATUS_TFFULL : ald_uart.h
  • UART_STATUS_TFOERR : ald_uart.h
  • UART_STATUS_TFTH : ald_uart.h
  • UART_STATUS_TSBUSY : ald_uart.h
  • UART_STOP_BITS_0_5 : ald_uart.h
  • UART_STOP_BITS_1 : ald_uart.h
  • UART_STOP_BITS_1_5 : ald_uart.h
  • UART_STOP_BITS_2 : ald_uart.h
  • uart_stop_bits_t : ald_uart.h
  • UART_TX_DISABLE : ald_uart.h
  • UART_TX_ENABLE : ald_uart.h
  • UART_TX_INV_DISABLE : ald_uart.h
  • UART_TX_INV_ENABLE : ald_uart.h
  • UART_TX_RX_SWAP_DISABLE : ald_uart.h
  • UART_TX_RX_SWAP_ENABLE : ald_uart.h
  • UART_TXFIFO_2BYTE : ald_uart.h
  • UART_TXFIFO_4BYTE : ald_uart.h
  • UART_TXFIFO_8BYTE : ald_uart.h
  • UART_TXFIFO_EMPTY : ald_uart.h
  • uart_txfifo_t : ald_uart.h
  • uart_wait_flag() : ald_uart.c
  • UART_WORD_LENGTH_5B : ald_uart.h
  • UART_WORD_LENGTH_6B : ald_uart.h
  • UART_WORD_LENGTH_7B : ald_uart.h
  • UART_WORD_LENGTH_8B : ald_uart.h
  • uart_word_length_t : ald_uart.h
  • UNLOCK : type.h
  • UNLOCK_KEY : ald_gpio.h
  • UNUSED : type.h
  • USB_CSRH0_DISPING : ald_usb.h
  • USB_CSRH0_DT : ald_usb.h
  • USB_CSRH0_DTWE : ald_usb.h
  • USB_CSRH0_FLUSH : ald_usb.h
  • USB_CSRL0_DATAEND : ald_usb.h
  • USB_CSRL0_ERROR : ald_usb.h
  • USB_CSRL0_NAKTO : ald_usb.h
  • USB_CSRL0_REQPKT : ald_usb.h
  • USB_CSRL0_RXRDY : ald_usb.h
  • USB_CSRL0_RXRDYC : ald_usb.h
  • USB_CSRL0_SETEND : ald_usb.h
  • USB_CSRL0_SETENDC : ald_usb.h
  • USB_CSRL0_SETUP : ald_usb.h
  • USB_CSRL0_STALL : ald_usb.h
  • USB_CSRL0_STALLED : ald_usb.h
  • USB_CSRL0_STATUS : ald_usb.h
  • USB_CSRL0_TXRDY : ald_usb.h
  • USB_DEV_EP0_IN_PKTPEND : ald_usb.h
  • USB_DEV_EP0_OUT_PKTRDY : ald_usb.h
  • USB_DEV_EP0_SENT_STALL : ald_usb.h
  • USB_DEV_EP0_SETUP_END : ald_usb.h
  • USB_DEV_LPM_EN : ald_usb.h
  • USB_DEV_LPM_EXTONLY : ald_usb.h
  • USB_DEV_LPM_LS_L1 : ald_usb.h
  • USB_DEV_LPM_LS_RMTWAKE : ald_usb.h
  • USB_DEV_LPM_NAK : ald_usb.h
  • USB_DEV_LPM_NONE : ald_usb.h
  • USB_DEV_RX_DATA_ERROR : ald_usb.h
  • USB_DEV_RX_FIFO_FULL : ald_usb.h
  • USB_DEV_RX_OVERRUN : ald_usb.h
  • USB_DEV_RX_PID_ERROR : ald_usb.h
  • USB_DEV_RX_PKT_RDY : ald_usb.h
  • USB_DEV_RX_SENT_STALL : ald_usb.h
  • USB_DEV_TX_FIFO_NE : ald_usb.h
  • USB_DEV_TX_NOT_COMP : ald_usb.h
  • USB_DEV_TX_SENT_STALL : ald_usb.h
  • USB_DEV_TX_TXPKTRDY : ald_usb.h
  • USB_DEV_TX_UNDERRUN : ald_usb.h
  • USB_DEVCTL_DEV : ald_usb.h
  • USB_DEVCTL_FSDEV : ald_usb.h
  • USB_DEVCTL_HOST : ald_usb.h
  • USB_DEVCTL_HOSTREQ : ald_usb.h
  • USB_DEVCTL_LSDEV : ald_usb.h
  • USB_DEVCTL_SESSION : ald_usb.h
  • USB_DEVCTL_VBUS_AVALID : ald_usb.h
  • USB_DEVCTL_VBUS_M : ald_usb.h
  • USB_DEVCTL_VBUS_NONE : ald_usb.h
  • USB_DEVCTL_VBUS_SEND : ald_usb.h
  • USB_DEVCTL_VBUS_VALID : ald_usb.h
  • USB_DMA_CFG_BURST_16 : ald_usb.h
  • USB_DMA_CFG_BURST_4 : ald_usb.h
  • USB_DMA_CFG_BURST_8 : ald_usb.h
  • USB_DMA_CFG_BURST_NONE : ald_usb.h
  • USB_DMA_CFG_DIR_RD : ald_usb.h
  • USB_DMA_CFG_DIR_WR : ald_usb.h
  • USB_DMA_CFG_EP_1 : ald_usb.h
  • USB_DMA_CFG_EP_2 : ald_usb.h
  • USB_DMA_CFG_EP_3 : ald_usb.h
  • USB_DMA_CFG_EP_4 : ald_usb.h
  • USB_DMA_CFG_EP_5 : ald_usb.h
  • USB_DMA_CFG_EP_MSK : ald_usb.h
  • USB_DMA_CFG_EP_POS : ald_usb.h
  • USB_DMA_CFG_IE_DIS : ald_usb.h
  • USB_DMA_CFG_IE_EN : ald_usb.h
  • USB_DMA_CFG_MODE_0 : ald_usb.h
  • USB_DMA_CFG_MODE_1 : ald_usb.h
  • USB_DMA_CFG_MODE_MSK : ald_usb.h
  • USB_DMA_CFG_START : ald_usb.h
  • USB_DMA_CFG_START_NO : ald_usb.h
  • USB_DMA_CH_ERR_MSK : ald_usb.h
  • USB_DMA_EP_CFG_RX_DEV : ald_usb.h
  • USB_DMA_EP_CFG_RX_HOST : ald_usb.h
  • USB_DMA_EP_CFG_TX : ald_usb.h
  • USB_DMA_EP_RX_DEV_MSK : ald_usb.h
  • USB_DMA_EP_RX_HOST_MSK : ald_usb.h
  • USB_DMA_EP_TX_MSK : ald_usb.h
  • USB_DMA_INT_CH1 : ald_usb.h
  • USB_DMA_INT_CH2 : ald_usb.h
  • USB_DMA_INT_CH3 : ald_usb.h
  • USB_DMA_INT_CH4 : ald_usb.h
  • USB_DMA_INT_CH5 : ald_usb.h
  • USB_DMA_INT_CH6 : ald_usb.h
  • USB_DMA_INT_CH7 : ald_usb.h
  • USB_DMA_INT_CH8 : ald_usb.h
  • USB_DMA_STATUS_ERROR : ald_usb.h
  • USB_DUAL_MODE_DEVICE : ald_usb.h
  • USB_DUAL_MODE_HOST : ald_usb.h
  • USB_DUAL_MODE_NONE : ald_usb.h
  • USB_EP_0 : ald_usb.h
  • USB_EP_1 : ald_usb.h
  • USB_EP_2 : ald_usb.h
  • USB_EP_3 : ald_usb.h
  • USB_EP_4 : ald_usb.h
  • USB_EP_5 : ald_usb.h
  • USB_EP_AUTO_CLEAR : ald_usb.h
  • USB_EP_AUTO_REQUEST : ald_usb.h
  • USB_EP_AUTO_SET : ald_usb.h
  • USB_EP_DEV_IN : ald_usb.h
  • USB_EP_DEV_OUT : ald_usb.h
  • USB_EP_DIS_NYET : ald_usb.h
  • USB_EP_DMA_MODE_0 : ald_usb.h
  • USB_EP_DMA_MODE_1 : ald_usb.h
  • USB_EP_HOST_IN : ald_usb.h
  • USB_EP_HOST_OUT : ald_usb.h
  • USB_EP_MODE_BULK : ald_usb.h
  • USB_EP_MODE_CTRL : ald_usb.h
  • USB_EP_MODE_INT : ald_usb.h
  • USB_EP_MODE_ISOC : ald_usb.h
  • USB_EP_MODE_MASK : ald_usb.h
  • USB_EP_SPEED_FULL : ald_usb.h
  • USB_EP_SPEED_HIGH : ald_usb.h
  • USB_EP_SPEED_LOW : ald_usb.h
  • USB_FIFO_SZ_1024 : ald_usb.h
  • USB_FIFO_SZ_128 : ald_usb.h
  • USB_FIFO_SZ_16 : ald_usb.h
  • USB_FIFO_SZ_2048 : ald_usb.h
  • USB_FIFO_SZ_256 : ald_usb.h
  • USB_FIFO_SZ_32 : ald_usb.h
  • USB_FIFO_SZ_512 : ald_usb.h
  • USB_FIFO_SZ_64 : ald_usb.h
  • USB_FIFO_SZ_8 : ald_usb.h
  • USB_FULL_SPEED : ald_usb.h
  • USB_HIGH_SPEED : ald_usb.h
  • USB_HOST_EP0_ERROR : ald_usb.h
  • USB_HOST_EP0_NAK_TO : ald_usb.h
  • USB_HOST_EP0_RX_STALL : ald_usb.h
  • USB_HOST_EP0_RXPKTRDY : ald_usb.h
  • USB_HOST_EP0_STATUS : ald_usb.h
  • USB_HOST_IN_DATA_ERROR : ald_usb.h
  • USB_HOST_IN_ERROR : ald_usb.h
  • USB_HOST_IN_FIFO_FULL : ald_usb.h
  • USB_HOST_IN_NAK_TO : ald_usb.h
  • USB_HOST_IN_NOT_COMP : ald_usb.h
  • USB_HOST_IN_PID_ERROR : ald_usb.h
  • USB_HOST_IN_PKTRDY : ald_usb.h
  • USB_HOST_IN_STALL : ald_usb.h
  • USB_HOST_IN_STATUS : ald_usb.h
  • USB_HOST_LPM_L1 : ald_usb.h
  • USB_HOST_LPM_RMTWAKE : ald_usb.h
  • USB_HOST_OUT_ERROR : ald_usb.h
  • USB_HOST_OUT_FIFO_NE : ald_usb.h
  • USB_HOST_OUT_NAK_TO : ald_usb.h
  • USB_HOST_OUT_NOT_COMP : ald_usb.h
  • USB_HOST_OUT_PKTPEND : ald_usb.h
  • USB_HOST_OUT_STALL : ald_usb.h
  • USB_HOST_OUT_STATUS : ald_usb.h
  • USB_HOST_PWREN_AUTOHIGH : ald_usb.h
  • USB_HOST_PWREN_AUTOLOW : ald_usb.h
  • USB_HOST_PWREN_FILTER : ald_usb.h
  • USB_HOST_PWREN_MAN_HIGH : ald_usb.h
  • USB_HOST_PWREN_MAN_LOW : ald_usb.h
  • USB_HOST_PWRFLT_EP_HIGH : ald_usb.h
  • USB_HOST_PWRFLT_EP_LOW : ald_usb.h
  • USB_HOST_PWRFLT_EP_NONE : ald_usb.h
  • USB_HOST_PWRFLT_EP_TRI : ald_usb.h
  • USB_HOST_PWRFLT_HIGH : ald_usb.h
  • USB_HOST_PWRFLT_LOW : ald_usb.h
  • USB_INTCTRL_ALL : ald_usb.h
  • USB_INTCTRL_BABBLE : ald_usb.h
  • USB_INTCTRL_CONNECT : ald_usb.h
  • USB_INTCTRL_DISCONNECT : ald_usb.h
  • USB_INTCTRL_MODE_DETECT : ald_usb.h
  • USB_INTCTRL_POWER_FAULT : ald_usb.h
  • USB_INTCTRL_RESET : ald_usb.h
  • USB_INTCTRL_RESUME : ald_usb.h
  • USB_INTCTRL_SESSION : ald_usb.h
  • USB_INTCTRL_SESSION_END : ald_usb.h
  • USB_INTCTRL_SOF : ald_usb.h
  • USB_INTCTRL_STATUS : ald_usb.h
  • USB_INTCTRL_SUSPEND : ald_usb.h
  • USB_INTCTRL_VBUS_ERR : ald_usb.h
  • USB_INTEP_0 : ald_usb.h
  • USB_INTEP_ALL : ald_usb.h
  • USB_INTEP_DEV_IN : ald_usb.h
  • USB_INTEP_DEV_IN_1 : ald_usb.h
  • USB_INTEP_DEV_IN_10 : ald_usb.h
  • USB_INTEP_DEV_IN_11 : ald_usb.h
  • USB_INTEP_DEV_IN_12 : ald_usb.h
  • USB_INTEP_DEV_IN_13 : ald_usb.h
  • USB_INTEP_DEV_IN_14 : ald_usb.h
  • USB_INTEP_DEV_IN_15 : ald_usb.h
  • USB_INTEP_DEV_IN_2 : ald_usb.h
  • USB_INTEP_DEV_IN_3 : ald_usb.h
  • USB_INTEP_DEV_IN_4 : ald_usb.h
  • USB_INTEP_DEV_IN_5 : ald_usb.h
  • USB_INTEP_DEV_IN_6 : ald_usb.h
  • USB_INTEP_DEV_IN_7 : ald_usb.h
  • USB_INTEP_DEV_IN_8 : ald_usb.h
  • USB_INTEP_DEV_IN_9 : ald_usb.h
  • USB_INTEP_DEV_OUT : ald_usb.h
  • USB_INTEP_DEV_OUT_1 : ald_usb.h
  • USB_INTEP_DEV_OUT_10 : ald_usb.h
  • USB_INTEP_DEV_OUT_11 : ald_usb.h
  • USB_INTEP_DEV_OUT_12 : ald_usb.h
  • USB_INTEP_DEV_OUT_13 : ald_usb.h
  • USB_INTEP_DEV_OUT_14 : ald_usb.h
  • USB_INTEP_DEV_OUT_15 : ald_usb.h
  • USB_INTEP_DEV_OUT_2 : ald_usb.h
  • USB_INTEP_DEV_OUT_3 : ald_usb.h
  • USB_INTEP_DEV_OUT_4 : ald_usb.h
  • USB_INTEP_DEV_OUT_5 : ald_usb.h
  • USB_INTEP_DEV_OUT_6 : ald_usb.h
  • USB_INTEP_DEV_OUT_7 : ald_usb.h
  • USB_INTEP_DEV_OUT_8 : ald_usb.h
  • USB_INTEP_DEV_OUT_9 : ald_usb.h
  • USB_INTEP_HOST_IN : ald_usb.h
  • USB_INTEP_HOST_IN_1 : ald_usb.h
  • USB_INTEP_HOST_IN_10 : ald_usb.h
  • USB_INTEP_HOST_IN_11 : ald_usb.h
  • USB_INTEP_HOST_IN_12 : ald_usb.h
  • USB_INTEP_HOST_IN_13 : ald_usb.h
  • USB_INTEP_HOST_IN_14 : ald_usb.h
  • USB_INTEP_HOST_IN_15 : ald_usb.h
  • USB_INTEP_HOST_IN_2 : ald_usb.h
  • USB_INTEP_HOST_IN_3 : ald_usb.h
  • USB_INTEP_HOST_IN_4 : ald_usb.h
  • USB_INTEP_HOST_IN_5 : ald_usb.h
  • USB_INTEP_HOST_IN_6 : ald_usb.h
  • USB_INTEP_HOST_IN_7 : ald_usb.h
  • USB_INTEP_HOST_IN_8 : ald_usb.h
  • USB_INTEP_HOST_IN_9 : ald_usb.h
  • USB_INTEP_HOST_OUT : ald_usb.h
  • USB_INTEP_HOST_OUT_1 : ald_usb.h
  • USB_INTEP_HOST_OUT_10 : ald_usb.h
  • USB_INTEP_HOST_OUT_11 : ald_usb.h
  • USB_INTEP_HOST_OUT_12 : ald_usb.h
  • USB_INTEP_HOST_OUT_13 : ald_usb.h
  • USB_INTEP_HOST_OUT_14 : ald_usb.h
  • USB_INTEP_HOST_OUT_15 : ald_usb.h
  • USB_INTEP_HOST_OUT_2 : ald_usb.h
  • USB_INTEP_HOST_OUT_3 : ald_usb.h
  • USB_INTEP_HOST_OUT_4 : ald_usb.h
  • USB_INTEP_HOST_OUT_5 : ald_usb.h
  • USB_INTEP_HOST_OUT_6 : ald_usb.h
  • USB_INTEP_HOST_OUT_7 : ald_usb.h
  • USB_INTEP_HOST_OUT_8 : ald_usb.h
  • USB_INTEP_HOST_OUT_9 : ald_usb.h
  • USB_INTEP_RX_SHIFT : ald_usb.h
  • USB_INTLPM_ACK : ald_usb.h
  • USB_INTLPM_ERROR : ald_usb.h
  • USB_INTLPM_INCOMPLETE : ald_usb.h
  • USB_INTLPM_NYET : ald_usb.h
  • USB_INTLPM_RESUME : ald_usb.h
  • USB_INTLPM_STALL : ald_usb.h
  • USB_LOW_SPEED : ald_usb.h
  • USB_LPMATTR_ENDPT_M : ald_usb.h
  • USB_LPMATTR_ENDPT_S : ald_usb.h
  • USB_LPMATTR_HIRD_M : ald_usb.h
  • USB_LPMATTR_HIRD_S : ald_usb.h
  • USB_LPMATTR_LS_L1 : ald_usb.h
  • USB_LPMATTR_LS_M : ald_usb.h
  • USB_LPMATTR_RMTWAK : ald_usb.h
  • USB_LPMCNTRL_DISABLE : ald_usb.h
  • USB_LPMCNTRL_ENABLE : ald_usb.h
  • USB_LPMCNTRL_LPMRES : ald_usb.h
  • USB_LPMCNTRL_LPMXMT : ald_usb.h
  • USB_MODE_DEV : ald_usb.h
  • USB_MODE_DEV_VBUS : ald_usb.h
  • USB_MODE_HOST : ald_usb.h
  • USB_MODE_HOST_VBUS : ald_usb.h
  • USB_MODE_OTG : ald_usb.h
  • USB_OTG_MODE_ASIDE_AVAL : ald_usb.h
  • USB_OTG_MODE_ASIDE_DEV : ald_usb.h
  • USB_OTG_MODE_ASIDE_HOST : ald_usb.h
  • USB_OTG_MODE_ASIDE_NPWR : ald_usb.h
  • USB_OTG_MODE_ASIDE_SESS : ald_usb.h
  • USB_OTG_MODE_BSIDE_DEV : ald_usb.h
  • USB_OTG_MODE_BSIDE_HOST : ald_usb.h
  • USB_OTG_MODE_BSIDE_NPWR : ald_usb.h
  • USB_OTG_MODE_NONE : ald_usb.h
  • USB_POWER_HS_EN : ald_usb.h
  • USB_POWER_HS_M : ald_usb.h
  • USB_POWER_ISOUP : ald_usb.h
  • USB_POWER_PWRDNPHY : ald_usb.h
  • USB_POWER_RESET : ald_usb.h
  • USB_POWER_RESUME : ald_usb.h
  • USB_POWER_SOFTCONN : ald_usb.h
  • USB_POWER_SUSPEND : ald_usb.h
  • USB_RX_EPSTATUS_SHIFT : ald_usb.h
  • USB_RXCSRH1_AUTOCL : ald_usb.h
  • USB_RXCSRH1_AUTORQ : ald_usb.h
  • USB_RXCSRH1_DISNYET : ald_usb.h
  • USB_RXCSRH1_DMAEN : ald_usb.h
  • USB_RXCSRH1_DMAMOD : ald_usb.h
  • USB_RXCSRH1_DT : ald_usb.h
  • USB_RXCSRH1_DTWE : ald_usb.h
  • USB_RXCSRH1_INCOMPRX : ald_usb.h
  • USB_RXCSRH1_ISO : ald_usb.h
  • USB_RXCSRH1_PIDERR : ald_usb.h
  • USB_RXCSRL1_CLRDT : ald_usb.h
  • USB_RXCSRL1_DATAERR : ald_usb.h
  • USB_RXCSRL1_ERROR : ald_usb.h
  • USB_RXCSRL1_FLUSH : ald_usb.h
  • USB_RXCSRL1_FULL : ald_usb.h
  • USB_RXCSRL1_NAKTO : ald_usb.h
  • USB_RXCSRL1_OVER : ald_usb.h
  • USB_RXCSRL1_REQPKT : ald_usb.h
  • USB_RXCSRL1_RXRDY : ald_usb.h
  • USB_RXCSRL1_STALL : ald_usb.h
  • USB_RXCSRL1_STALLED : ald_usb.h
  • USB_TRANS_IN : ald_usb.h
  • USB_TRANS_IN_LAST : ald_usb.h
  • USB_TRANS_OUT : ald_usb.h
  • USB_TRANS_SETUP : ald_usb.h
  • USB_TRANS_STATUS : ald_usb.h
  • USB_TXCSRH1_AUTOSET : ald_usb.h
  • USB_TXCSRH1_DMAEN : ald_usb.h
  • USB_TXCSRH1_DMAMOD : ald_usb.h
  • USB_TXCSRH1_DT : ald_usb.h
  • USB_TXCSRH1_DTWE : ald_usb.h
  • USB_TXCSRH1_FDT : ald_usb.h
  • USB_TXCSRH1_ISO : ald_usb.h
  • USB_TXCSRH1_MODE : ald_usb.h
  • USB_TXCSRL1_CLRDT : ald_usb.h
  • USB_TXCSRL1_ERROR : ald_usb.h
  • USB_TXCSRL1_FIFONE : ald_usb.h
  • USB_TXCSRL1_FLUSH : ald_usb.h
  • USB_TXCSRL1_NAKTO : ald_usb.h
  • USB_TXCSRL1_SETUP : ald_usb.h
  • USB_TXCSRL1_STALL : ald_usb.h
  • USB_TXCSRL1_STALLED : ald_usb.h
  • USB_TXCSRL1_TXRDY : ald_usb.h
  • USB_TXCSRL1_UNDRN : ald_usb.h
  • USB_TXTYPE1_PROTO_BULK : ald_usb.h
  • USB_TXTYPE1_PROTO_CTRL : ald_usb.h
  • USB_TXTYPE1_PROTO_INT : ald_usb.h
  • USB_TXTYPE1_PROTO_ISOC : ald_usb.h
  • USB_TXTYPE1_PROTO_M : ald_usb.h
  • USB_TXTYPE1_SPEED_DFLT : ald_usb.h
  • USB_TXTYPE1_SPEED_FULL : ald_usb.h
  • USB_TXTYPE1_SPEED_HIGH : ald_usb.h
  • USB_TXTYPE1_SPEED_LOW : ald_usb.h
  • USB_TXTYPE1_SPEED_M : ald_usb.h
  • USB_TXTYPE1_TEP_M : ald_usb.h
  • USB_TXTYPE1_TEP_S : ald_usb.h
  • USB_TYPE0_SPEED_FULL : ald_usb.h
  • USB_TYPE0_SPEED_HIGH : ald_usb.h
  • USB_TYPE0_SPEED_LOW : ald_usb.h
  • USB_TYPE0_SPEED_M : ald_usb.h
  • USB_UNDEF_SPEED : ald_usb.h
  • USBEPToIndex : ald_usb.h
  • USBFIFOSizeToBytes : ald_usb.h


ALD User Manual: Globals

Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:

- w -

  • write_buf : ald_flash_ext.c
  • WRITE_REG : type.h
  • WWDT_LOCK : ald_wdt.h
  • WWDT_UNLOCK : ald_wdt.h
  • WWDT_WIN_00 : ald_wdt.h
  • WWDT_WIN_25 : ald_wdt.h
  • WWDT_WIN_50 : ald_wdt.h
  • WWDT_WIN_75 : ald_wdt.h
  • wwdt_win_t : ald_wdt.h


ALD User Manual: Globals

- _ -

  • __attribute__() : ald_dma.c
  • __can_recv_by_it() : ald_can.c
  • __can_rx_check() : ald_can.c
  • __can_send_by_it() : ald_can.c
  • __i2s_recv_by_it() : ald_i2s.c
  • __i2s_send_by_it() : ald_i2s.c
  • __i2s_tx_recv_by_it() : ald_i2s.c
  • __spi_recv_by_it() : ald_spi.c
  • __spi_send_by_it() : ald_spi.c
  • __spi_send_recv_by_it() : ald_spi.c
  • __uart_end_send_by_it() : ald_uart.c
  • __uart_recv_by_it() : ald_uart.c
  • __uart_send_by_it() : ald_uart.c


ALD User Manual: Globals

- a -

  • adc_dma_error() : ald_adc.c
  • adc_dma_normal_conv_cplt() : ald_adc.c
  • adc_dma_timer_trigger_cplt() : ald_adc.c
  • ald_acmp_clear_flag_status() : ald_acmp.c
  • ald_acmp_get_flag_status() : ald_acmp.c
  • ald_acmp_get_it_status() : ald_acmp.c
  • ald_acmp_get_mask_flag_status() : ald_acmp.c
  • ald_acmp_get_status() : ald_acmp.c
  • ald_acmp_init() : ald_acmp.c
  • ald_acmp_interrupt_config() : ald_acmp.c
  • ald_acmp_irq_handler() : ald_acmp.c
  • ald_acmp_out_config() : ald_acmp.c
  • ald_acmp_out_result() : ald_acmp.c
  • ald_adc_analog_wdg_config() : ald_adc.c
  • ald_adc_clear_flag_status() : ald_adc.c
  • ald_adc_get_error() : ald_adc.c
  • ald_adc_get_flag_status() : ald_adc.c
  • ald_adc_get_it_status() : ald_adc.c
  • ald_adc_get_state() : ald_adc.c
  • ald_adc_init() : ald_adc.c
  • ald_adc_insert_channel_config() : ald_adc.c
  • ald_adc_insert_get_value() : ald_adc.c
  • ald_adc_insert_poll_for_conversion() : ald_adc.c
  • ald_adc_insert_start() : ald_adc.c
  • ald_adc_insert_start_by_it() : ald_adc.c
  • ald_adc_insert_stop() : ald_adc.c
  • ald_adc_insert_stop_by_it() : ald_adc.c
  • ald_adc_interrupt_config() : ald_adc.c
  • ald_adc_irq_handler() : ald_adc.c
  • ald_adc_normal_channel_config() : ald_adc.c
  • ald_adc_normal_get_value() : ald_adc.c
  • ald_adc_normal_poll_for_conversion() : ald_adc.c
  • ald_adc_normal_start() : ald_adc.c
  • ald_adc_normal_start_by_it() : ald_adc.c
  • ald_adc_normal_stop() : ald_adc.c
  • ald_adc_normal_stop_by_it() : ald_adc.c
  • ald_adc_poll_for_event() : ald_adc.c
  • ald_adc_reset() : ald_adc.c
  • ald_adc_start_by_dma() : ald_adc.c
  • ald_adc_stop_by_dma() : ald_adc.c
  • ald_adc_timer_trigger_adc_by_dma() : ald_adc.c
  • ald_bkpc_read_ram() : ald_bkpc.c
  • ald_bkpc_rtc_clock_config() : ald_bkpc.c
  • ald_bkpc_standby_wakeup_config() : ald_bkpc.c
  • ald_bkpc_tsense_clock_config() : ald_bkpc.c
  • ald_bkpc_write_ram() : ald_bkpc.c
  • ald_calc_div() : ald_calc.c
  • ald_calc_div_sign() : ald_calc.c
  • ald_calc_get_dz_status() : ald_calc.c
  • ald_calc_sqrt() : ald_calc.c
  • ald_can_cancel_send() : ald_can.c
  • ald_can_clear_flag_status() : ald_can.h
  • ald_can_filter_config() : ald_can.c
  • ald_can_get_error() : ald_can.c
  • ald_can_get_flag_status() : ald_can.c
  • ald_can_get_it_status() : ald_can.c
  • ald_can_get_state() : ald_can.c
  • ald_can_get_tx_status() : ald_can.c
  • ald_can_init() : ald_can.c
  • ald_can_interrupt_config() : ald_can.c
  • ald_can_irq_handler() : ald_can.c
  • ald_can_recv() : ald_can.c
  • ald_can_recv_by_it() : ald_can.c
  • ald_can_reset() : ald_can.c
  • ald_can_send() : ald_can.c
  • ald_can_send_by_it() : ald_can.c
  • ald_can_sleep() : ald_can.c
  • ald_can_wake_up() : ald_can.c
  • ald_cmu_buzz_config() : ald_cmu.c
  • ald_cmu_clock_config() : ald_cmu.c
  • ald_cmu_clock_config_default() : ald_cmu.c
  • ald_cmu_current_clock_source_get() : ald_cmu.c
  • ald_cmu_div_config() : ald_cmu.c
  • ald_cmu_get_clock() : ald_cmu.c
  • ald_cmu_get_clock_state() : ald_cmu.c
  • ald_cmu_get_hclk1_clock() : ald_cmu.c
  • ald_cmu_get_hclk2_clock() : ald_cmu.c
  • ald_cmu_get_pclk1_clock() : ald_cmu.c
  • ald_cmu_get_pclk2_clock() : ald_cmu.c
  • ald_cmu_get_sys_clock() : ald_cmu.c
  • ald_cmu_hosc_safe_config() : ald_cmu.c
  • ald_cmu_init() : utils.c
  • ald_cmu_irq_cbk() : ald_cmu.c
  • ald_cmu_irq_handler() : ald_cmu.c , ald_cmu.h
  • ald_cmu_lcd_clock_select() : ald_cmu.c
  • ald_cmu_losc_safe_config() : ald_cmu.c
  • ald_cmu_lptim0_clock_select() : ald_cmu.c
  • ald_cmu_lpuart0_clock_select() : ald_cmu.c
  • ald_cmu_output_high_clock_config() : ald_cmu.c
  • ald_cmu_output_low_clock_config() : ald_cmu.c
  • ald_cmu_perh_clock_config() : ald_cmu.c
  • ald_cmu_pll1_config() : ald_cmu.c
  • ald_cmu_pll_safe_config() : ald_cmu.c
  • ald_cmu_qspi_clock_select() : ald_cmu.c
  • ald_cmu_stop1_clock_sel() : ald_cmu.c
  • ald_cmu_usb_clock_config() : ald_cmu.c
  • ald_crc_calculate() : ald_crc.c
  • ald_crc_calculate_by_dma() : ald_crc.c
  • ald_crc_calculate_halfword() : ald_crc.c
  • ald_crc_calculate_halfword_by_dma() : ald_crc.c
  • ald_crc_calculate_word() : ald_crc.c
  • ald_crc_calculate_word_by_dma() : ald_crc.c
  • ald_crc_dma_pause() : ald_crc.c
  • ald_crc_dma_resume() : ald_crc.c
  • ald_crc_dma_stop() : ald_crc.c
  • ald_crc_get_state() : ald_crc.c
  • ald_crc_init() : ald_crc.c
  • ald_crc_reset() : ald_crc.c , ald_crc.h
  • ald_crypt_clear_flag_status() : ald_crypt.c
  • ald_crypt_decrypt() : ald_crypt.c
  • ald_crypt_decrypt_by_dma() : ald_crypt.c
  • ald_crypt_decrypt_by_it() : ald_crypt.c
  • ald_crypt_dma_pause() : ald_crypt.c
  • ald_crypt_dma_resume() : ald_crypt.c
  • ald_crypt_dma_stop() : ald_crypt.c
  • ald_crypt_encrypt() : ald_crypt.c
  • ald_crypt_encrypt_by_dma() : ald_crypt.c
  • ald_crypt_encrypt_by_it() : ald_crypt.c
  • ald_crypt_gcm_verify() : ald_crypt.c
  • ald_crypt_get_flag_status() : ald_crypt.c
  • ald_crypt_get_it_status() : ald_crypt.c
  • ald_crypt_get_state() : ald_crypt.c
  • ald_crypt_init() : ald_crypt.c
  • ald_crypt_interrupt_config() : ald_crypt.c
  • ald_crypt_irq_handler() : ald_crypt.c
  • ald_crypt_read_ivr() : ald_crypt.c
  • ald_crypt_read_key() : ald_crypt.c
  • ald_crypt_write_ivr() : ald_crypt.c
  • ald_crypt_write_key() : ald_crypt.c
  • ald_dac_channel_config() : ald_dac.c
  • ald_dac_clear_flag_status() : ald_dac.c
  • ald_dac_get_flag_status() : ald_dac.c
  • ald_dac_get_it_status() : ald_dac.c
  • ald_dac_get_mask_flag_status() : ald_dac.c
  • ald_dac_get_status() : ald_dac.c
  • ald_dac_init() : ald_dac.c
  • ald_dac_interrupt_config() : ald_dac.c
  • ald_dac_irq_handler() : ald_dac.c
  • ald_dac_output_set() : ald_dac.c
  • ald_dac_reset() : ald_dac.c
  • ald_dbgc_get_core_id() : ald_dbgc.h
  • ald_dbgc_get_device_id() : ald_dbgc.h
  • ald_dbgc_get_rev_id() : ald_dbgc.h
  • ald_dbgc_mode_config() : ald_dbgc.h
  • ald_dbgc_perh_config() : ald_dbgc.h
  • ald_delay_ms() : utils.c
  • ald_dma_channel_config() : ald_dma.c
  • ald_dma_clear_flag_status() : ald_dma.c
  • ald_dma_config_auto() : ald_dma.c
  • ald_dma_config_auto_easy() : ald_dma.c
  • ald_dma_config_basic() : ald_dma.c
  • ald_dma_config_basic_easy() : ald_dma.c
  • ald_dma_config_ping_pong() : ald_dma.c
  • ald_dma_config_sg_alt_desc() : ald_dma.c
  • ald_dma_config_sg_mem() : ald_dma.c
  • ald_dma_config_sg_per() : ald_dma.c
  • ald_dma_config_struct() : ald_dma.c
  • ald_dma_descriptor_cplt_get() : ald_dma.c
  • ald_dma_get_flag_status() : ald_dma.c
  • ald_dma_get_it_status() : ald_dma.c
  • ald_dma_init() : ald_dma.c
  • ald_dma_interrupt_config() : ald_dma.c
  • ald_dma_irq_handler() : ald_dma.c , ald_dma.h
  • ald_dma_reset() : ald_dma.c
  • ald_dma_restart_auto() : ald_dma.c
  • ald_dma_restart_basic() : ald_dma.c
  • ald_ebi_lcd_init() : ald_ebi.c
  • ald_ebi_lcd_reset() : ald_ebi.c
  • ald_ebi_nand_attr_timing_init() : ald_ebi.c
  • ald_ebi_nand_clear_flag() : ald_ebi.c
  • ald_ebi_nand_comm_timing_init() : ald_ebi.c
  • ald_ebi_nand_deinit() : ald_ebi.c
  • ald_ebi_nand_disable() : ald_ebi.c
  • ald_ebi_nand_disable_it() : ald_ebi.c
  • ald_ebi_nand_ecc_disable() : ald_ebi.c
  • ald_ebi_nand_ecc_enable() : ald_ebi.c
  • ald_ebi_nand_enable() : ald_ebi.c
  • ald_ebi_nand_enable_it() : ald_ebi.c
  • ald_ebi_nand_get_ecc() : ald_ebi.c
  • ald_ebi_nand_get_flag() : ald_ebi.c
  • ald_ebi_nand_init() : ald_ebi.c
  • ald_ebi_nor_sram_deinit() : ald_ebi.c
  • ald_ebi_nor_sram_disable() : ald_ebi.c
  • ald_ebi_nor_sram_enable() : ald_ebi.c
  • ald_ebi_nor_sram_ext_timing_init() : ald_ebi.c
  • ald_ebi_nor_sram_init() : ald_ebi.c
  • ald_ebi_nor_sram_timing_init() : ald_ebi.c
  • ald_ebi_nor_sram_write_disable() : ald_ebi.c
  • ald_ebi_nor_sram_write_enable() : ald_ebi.c
  • ald_flash_erase() : ald_flash.h
  • ald_flash_read() : ald_flash.h
  • ald_flash_wait_config() : utils.c
  • ald_flash_write() : ald_flash.h
  • ald_get_ald_version() : utils.c
  • ald_get_tick() : utils.c
  • ald_gpio_exti_clear_flag_status() : ald_gpio.c
  • ald_gpio_exti_get_flag_status() : ald_gpio.c
  • ald_gpio_exti_init() : ald_gpio.c
  • ald_gpio_exti_interrupt_config() : ald_gpio.c
  • ald_gpio_func_default() : ald_gpio.c
  • ald_gpio_init() : ald_gpio.c
  • ald_gpio_init_default() : ald_gpio.c
  • ald_gpio_lock_pin() : ald_gpio.c
  • ald_gpio_read_pin() : ald_gpio.c
  • ald_gpio_read_port() : ald_gpio.c
  • ald_gpio_toggle_dir() : ald_gpio.c
  • ald_gpio_toggle_pin() : ald_gpio.c
  • ald_gpio_write_pin() : ald_gpio.c
  • ald_gpio_write_port() : ald_gpio.c
  • ald_i2c_clear_flag_status() : ald_i2c.c , ald_i2c.h
  • ald_i2c_er_irq_handler() : ald_i2c.c
  • ald_i2c_ev_irq_handler() : ald_i2c.c
  • ald_i2c_get_error() : ald_i2c.c
  • ald_i2c_get_flag_status() : ald_i2c.c , ald_i2c.h
  • ald_i2c_get_it_status() : ald_i2c.c , ald_i2c.h
  • ald_i2c_get_mask_flag_status() : ald_i2c.c , ald_i2c.h
  • ald_i2c_get_state() : ald_i2c.c
  • ald_i2c_init() : ald_i2c.c
  • ald_i2c_interrupt_config() : ald_i2c.c
  • ald_i2c_master_recv() : ald_i2c.c
  • ald_i2c_master_recv_by_dma() : ald_i2c.c
  • ald_i2c_master_recv_by_it() : ald_i2c.c
  • ald_i2c_master_send() : ald_i2c.c
  • ald_i2c_master_send_by_dma() : ald_i2c.c
  • ald_i2c_master_send_by_it() : ald_i2c.c
  • ald_i2c_mem_read() : ald_i2c.c
  • ald_i2c_mem_read_by_dma() : ald_i2c.c
  • ald_i2c_mem_read_by_it() : ald_i2c.c
  • ald_i2c_mem_write() : ald_i2c.c
  • ald_i2c_mem_write_by_dma() : ald_i2c.c
  • ald_i2c_mem_write_by_it() : ald_i2c.c
  • ald_i2c_reset() : ald_i2c.c
  • ald_i2c_slave_recv() : ald_i2c.c
  • ald_i2c_slave_recv_by_dma() : ald_i2c.c
  • ald_i2c_slave_recv_by_it() : ald_i2c.c
  • ald_i2c_slave_send() : ald_i2c.c
  • ald_i2c_slave_send_by_dma() : ald_i2c.c
  • ald_i2c_slave_send_by_it() : ald_i2c.c
  • ald_i2s_clear_flag_status() : ald_i2s.c
  • ald_i2s_dma_pause() : ald_i2s.c
  • ald_i2s_dma_req_config() : ald_i2s.c
  • ald_i2s_dma_resume() : ald_i2s.c
  • ald_i2s_dma_stop() : ald_i2s.c
  • ald_i2s_get_error() : ald_i2s.c
  • ald_i2s_get_flag_status() : ald_i2s.c
  • ald_i2s_get_it_status() : ald_i2s.c
  • ald_i2s_get_mask_flag_status() : ald_i2s.c
  • ald_i2s_get_state() : ald_i2s.c
  • ald_i2s_get_status() : ald_i2s.c
  • ald_i2s_init() : ald_i2s.c
  • ald_i2s_interrupt_config() : ald_i2s.c
  • ald_i2s_irq_handler() : ald_i2s.c
  • ald_i2s_master_recv() : ald_i2s.c
  • ald_i2s_master_recv_by_dma() : ald_i2s.c
  • ald_i2s_master_recv_by_it() : ald_i2s.c
  • ald_i2s_master_send() : ald_i2s.c
  • ald_i2s_master_send_by_dma() : ald_i2s.c
  • ald_i2s_master_send_by_it() : ald_i2s.c
  • ald_i2s_reset() : ald_i2s.c
  • ald_iap_erase_page() : ald_iap.c
  • ald_iap_program_dword() : ald_iap.c
  • ald_iap_program_word() : ald_iap.c
  • ald_iap_program_words() : ald_iap.c
  • ald_inc_tick() : utils.c
  • ald_iwdt_clear_flag_status() : ald_wdt.c
  • ald_iwdt_feed_dog() : ald_wdt.c
  • ald_iwdt_get_flag_status() : ald_wdt.c
  • ald_iwdt_get_value() : ald_wdt.c
  • ald_iwdt_init() : ald_wdt.c
  • ald_iwdt_start() : ald_wdt.c
  • ald_lvd_irq_handler() : ald_pmu.c , ald_pmu.h
  • ald_mcu_get_chipid() : utils.c
  • ald_mcu_get_cpu_id() : utils.c
  • ald_mcu_get_timestamp() : utils.c
  • ald_mcu_get_uid() : utils.c
  • ald_mcu_irq_config() : utils.c
  • ald_mcu_timestamp_init() : utils.c
  • ald_nand_address_inc() : ald_nand.c
  • ald_nand_deinit() : ald_nand.c
  • ald_nand_ecc_disable() : ald_nand.c
  • ald_nand_ecc_enable() : ald_nand.c
  • ald_nand_erase_block() : ald_nand.c
  • ald_nand_get_ecc() : ald_nand.c
  • ald_nand_get_state() : ald_nand.c
  • ald_nand_init() : ald_nand.c
  • ald_nand_irq_cbk() : ald_nand.c
  • ald_nand_irq_handler() : ald_nand.c
  • ald_nand_read_id() : ald_nand.c
  • ald_nand_read_page_16b() : ald_nand.c
  • ald_nand_read_page_8b() : ald_nand.c
  • ald_nand_read_sparearea_16b() : ald_nand.c
  • ald_nand_read_sparearea_8b() : ald_nand.c
  • ald_nand_read_status() : ald_nand.c
  • ald_nand_reset() : ald_nand.c
  • ald_nand_write_page_16b() : ald_nand.c
  • ald_nand_write_page_8b() : ald_nand.c
  • ald_nand_write_sparearea_16b() : ald_nand.c
  • ald_nand_write_sparearea_8b() : ald_nand.c
  • ald_nor_deinit() : ald_nor_lcd.c , ald_nor_lcd.h
  • ald_nor_erase_block() : ald_nor_lcd.c
  • ald_nor_erase_chip() : ald_nor_lcd.c
  • ald_nor_get_state() : ald_nor_lcd.c
  • ald_nor_get_status() : ald_nor_lcd.c
  • ald_nor_init() : ald_nor_lcd.c , ald_nor_lcd.h
  • ald_nor_program() : ald_nor_lcd.c
  • ald_nor_program_buffer() : ald_nor_lcd.c
  • ald_nor_read() : ald_nor_lcd.c
  • ald_nor_read_buffer() : ald_nor_lcd.c
  • ald_nor_read_cfi() : ald_nor_lcd.c
  • ald_nor_read_id() : ald_nor_lcd.c
  • ald_nor_return_readmode() : ald_nor_lcd.c
  • ald_nor_write_disable() : ald_nor_lcd.c
  • ald_nor_write_enable() : ald_nor_lcd.c
  • ald_pis_create() : ald_pis.c
  • ald_pis_destroy() : ald_pis.c
  • ald_pis_get_state() : ald_pis.c
  • ald_pis_modu_config() : ald_pis.c
  • ald_pis_output_start() : ald_pis.c
  • ald_pis_output_stop() : ald_pis.c
  • ald_pmu_clear_status() : ald_pmu.c
  • ald_pmu_get_status() : ald_pmu.c
  • ald_pmu_ldo_12_config() : ald_pmu.c
  • ald_pmu_ldo_18_config() : ald_pmu.c
  • ald_pmu_lvd_config() : ald_pmu.c
  • ald_pmu_perh_power_config() : ald_pmu.c
  • ald_pmu_sleep() : ald_pmu.h
  • ald_pmu_sleep_deep() : ald_pmu.h
  • ald_pmu_standby_enter() : ald_pmu.c
  • ald_pmu_stop1_enter() : ald_pmu.c
  • ald_pmu_stop2_enter() : ald_pmu.c
  • ald_qspi_auto_poll() : ald_qspi.h
  • ald_qspi_clear_it_flag() : ald_qspi.c
  • ald_qspi_dac_rd() : ald_qspi.c
  • ald_qspi_dac_wr() : ald_qspi.c
  • ald_qspi_device_delay_config() : ald_qspi.c
  • ald_qspi_device_size_config() : ald_qspi.c
  • ald_qspi_execute_stig_cmd() : ald_qspi.c
  • ald_qspi_indac_config() : ald_qspi.c
  • ald_qspi_indac_read_by_dma() : ald_qspi.c
  • ald_qspi_indac_read_by_it() : ald_qspi.c
  • ald_qspi_indac_read_by_poll() : ald_qspi.c
  • ald_qspi_indac_transmit_by_dma() : ald_qspi.c
  • ald_qspi_indac_transmit_by_it() : ald_qspi.c
  • ald_qspi_indac_transmit_by_poll() : ald_qspi.c
  • ald_qspi_init() : ald_qspi.c
  • ald_qspi_interrupt_config() : ald_qspi.c
  • ald_qspi_irq_handler() : ald_qspi.c
  • ald_qspi_legacy_config() : ald_qspi.c
  • ald_qspi_read_config() : ald_qspi.c
  • ald_qspi_read_data_capture_config() : ald_qspi.c
  • ald_qspi_write_config() : ald_qspi.c
  • ald_qspi_write_proect_config() : ald_qspi.c
  • ald_qspi_write_proect_inverse() : ald_qspi.c
  • ald_resume_tick() : utils.c
  • ald_rmu_bor_config() : ald_rmu.c
  • ald_rmu_clear_reset_status() : ald_rmu.c
  • ald_rmu_get_reset_status() : ald_rmu.c
  • ald_rmu_reset_periperal() : ald_rmu.c
  • ald_rtc_alarm_cmd() : ald_rtc.c
  • ald_rtc_cancel_cali() : ald_rtc.c
  • ald_rtc_cancel_clock_output() : ald_rtc.c
  • ald_rtc_cancel_tamper() : ald_rtc.c
  • ald_rtc_cancel_time_stamp() : ald_rtc.c
  • ald_rtc_cancel_wakeup() : ald_rtc.c
  • ald_rtc_clear_flag_status() : ald_rtc.c
  • ald_rtc_get_alarm() : ald_rtc.c
  • ald_rtc_get_cali_status() : ald_rtc.c
  • ald_rtc_get_date() : ald_rtc.c
  • ald_rtc_get_date_time() : ald_rtc.c
  • ald_rtc_get_flag_status() : ald_rtc.c
  • ald_rtc_get_it_status() : ald_rtc.c
  • ald_rtc_get_time() : ald_rtc.c
  • ald_rtc_get_time_stamp() : ald_rtc.c
  • ald_rtc_get_wakeup_timer_value() : ald_rtc.c
  • ald_rtc_hw_auto_cali() : ald_rtchw.c
  • ald_rtc_init() : ald_rtc.c
  • ald_rtc_interrupt_config() : ald_rtc.c
  • ald_rtc_reset() : ald_rtc.c
  • ald_rtc_set_alarm() : ald_rtc.c
  • ald_rtc_set_cali() : ald_rtc.c
  • ald_rtc_set_clock_output() : ald_rtc.c
  • ald_rtc_set_date() : ald_rtc.c
  • ald_rtc_set_shift() : ald_rtc.c
  • ald_rtc_set_tamper() : ald_rtc.c
  • ald_rtc_set_time() : ald_rtc.c
  • ald_rtc_set_time_stamp() : ald_rtc.c
  • ald_rtc_set_wakeup() : ald_rtc.c
  • ald_rtc_source_select() : ald_rtc.c
  • ald_rtc_write_temp() : ald_rtc.c
  • ald_spi_clear_flag_status() : ald_spi.c
  • ald_spi_dma_pause() : ald_spi.c
  • ald_spi_dma_req_config() : ald_spi.c
  • ald_spi_dma_resume() : ald_spi.c
  • ald_spi_dma_stop() : ald_spi.c
  • ald_spi_get_error() : ald_spi.c
  • ald_spi_get_flag_status() : ald_spi.c
  • ald_spi_get_it_status() : ald_spi.c
  • ald_spi_get_state() : ald_spi.c
  • ald_spi_init() : ald_spi.c
  • ald_spi_interrupt_config() : ald_spi.c
  • ald_spi_irq_handler() : ald_spi.c
  • ald_spi_master_recv_bytes_fast() : ald_spi.c
  • ald_spi_master_recv_dbytes_fast() : ald_spi.c
  • ald_spi_recv() : ald_spi.c
  • ald_spi_recv_by_dma() : ald_spi.c
  • ald_spi_recv_by_it() : ald_spi.c
  • ald_spi_recv_byte_fast() : ald_spi.c
  • ald_spi_reset() : ald_spi.c
  • ald_spi_send() : ald_spi.c
  • ald_spi_send_by_dma() : ald_spi.c
  • ald_spi_send_by_it() : ald_spi.c
  • ald_spi_send_byte_fast() : ald_spi.c
  • ald_spi_send_byte_fast_1line() : ald_spi.c
  • ald_spi_send_bytes_fast() : ald_spi.c
  • ald_spi_send_dbytes_fast() : ald_spi.c
  • ald_spi_send_recv() : ald_spi.c
  • ald_spi_send_recv_by_dma() : ald_spi.c
  • ald_spi_send_recv_by_it() : ald_spi.c
  • ald_spi_slave_recv_bytes_fast() : ald_spi.c
  • ald_spi_slave_recv_dbytes_fast() : ald_spi.c
  • ald_spi_speed_config() : ald_spi.c
  • ald_sram_deinit() : ald_sram.c
  • ald_sram_get_state() : ald_sram.c
  • ald_sram_init() : ald_sram.c
  • ald_sram_read_16b() : ald_sram.c
  • ald_sram_read_32b() : ald_sram.c
  • ald_sram_read_8b() : ald_sram.c
  • ald_sram_read_by_dma() : ald_sram.c
  • ald_sram_write_16b() : ald_sram.c
  • ald_sram_write_32b() : ald_sram.c
  • ald_sram_write_8b() : ald_sram.c
  • ald_sram_write_by_dma() : ald_sram.c
  • ald_sram_write_disable() : ald_sram.c
  • ald_sram_write_enable() : ald_sram.c
  • ald_suspend_tick() : utils.c
  • ald_systick_interval_select() : utils.c
  • ald_systick_irq_cbk() : utils.c
  • ald_tick_init() : utils.c
  • ald_timer_base_init() : ald_timer.c
  • ald_timer_base_reset() : ald_timer.c
  • ald_timer_base_start() : ald_timer.c
  • ald_timer_base_start_by_dma() : ald_timer.c
  • ald_timer_base_start_by_it() : ald_timer.c
  • ald_timer_base_stop() : ald_timer.c
  • ald_timer_base_stop_by_dma() : ald_timer.c
  • ald_timer_base_stop_by_it() : ald_timer.c
  • ald_timer_break_dead_time_config() : ald_timer.c
  • ald_timer_clear_flag_status() : ald_timer.c
  • ald_timer_com_change_config() : ald_timer.c
  • ald_timer_com_event_config() : ald_timer.c
  • ald_timer_com_event_config_it() : ald_timer.c
  • ald_timer_config_clock_source() : ald_timer.c
  • ald_timer_config_oc_ref_clear() : ald_timer.c
  • ald_timer_config_ti1_input() : ald_timer.c
  • ald_timer_dma_req_config() : ald_timer.c
  • ald_timer_encoder_init() : ald_timer.c
  • ald_timer_encoder_start() : ald_timer.c
  • ald_timer_encoder_start_by_dma() : ald_timer.c
  • ald_timer_encoder_start_by_it() : ald_timer.c
  • ald_timer_encoder_stop() : ald_timer.c
  • ald_timer_encoder_stop_by_dma() : ald_timer.c
  • ald_timer_encoder_stop_by_it() : ald_timer.c
  • ald_timer_generate_event() : ald_timer.c
  • ald_timer_get_flag_status() : ald_timer.c
  • ald_timer_get_it_status() : ald_timer.c
  • ald_timer_get_state() : ald_timer.c
  • ald_timer_hall_sensor_init() : ald_timer.c
  • ald_timer_hall_sensor_start() : ald_timer.c
  • ald_timer_hall_sensor_start_by_dma() : ald_timer.c
  • ald_timer_hall_sensor_start_by_it() : ald_timer.c
  • ald_timer_hall_sensor_stop() : ald_timer.c
  • ald_timer_hall_sensor_stop_by_dma() : ald_timer.c
  • ald_timer_hall_sensor_stop_by_it() : ald_timer.c
  • ald_timer_ic_config_channel() : ald_timer.c
  • ald_timer_ic_init() : ald_timer.c
  • ald_timer_ic_start() : ald_timer.c
  • ald_timer_ic_start_by_dma() : ald_timer.c
  • ald_timer_ic_start_by_it() : ald_timer.c
  • ald_timer_ic_stop() : ald_timer.c
  • ald_timer_ic_stop_by_dma() : ald_timer.c
  • ald_timer_ic_stop_by_it() : ald_timer.c
  • ald_timer_interrupt_config() : ald_timer.c
  • ald_timer_irq_handler() : ald_timer.c
  • ald_timer_master_sync_config() : ald_timer.c
  • ald_timer_oc_config_channel() : ald_timer.c
  • ald_timer_oc_init() : ald_timer.c
  • ald_timer_oc_start() : ald_timer.c
  • ald_timer_oc_start_by_dma() : ald_timer.c
  • ald_timer_oc_start_by_it() : ald_timer.c
  • ald_timer_oc_stop() : ald_timer.c
  • ald_timer_oc_stop_by_dma() : ald_timer.c
  • ald_timer_oc_stop_by_it() : ald_timer.c
  • ald_timer_ocn_start() : ald_timer.c
  • ald_timer_ocn_start_by_dma() : ald_timer.c
  • ald_timer_ocn_start_by_it() : ald_timer.c
  • ald_timer_ocn_stop() : ald_timer.c
  • ald_timer_ocn_stop_by_dma() : ald_timer.c
  • ald_timer_ocn_stop_by_it() : ald_timer.c
  • ald_timer_one_pulse_config_channel() : ald_timer.c
  • ald_timer_one_pulse_init() : ald_timer.c
  • ald_timer_one_pulse_n_start() : ald_timer.c
  • ald_timer_one_pulse_n_start_by_it() : ald_timer.c
  • ald_timer_one_pulse_n_stop() : ald_timer.c
  • ald_timer_one_pulse_n_stop_by_it() : ald_timer.c
  • ald_timer_one_pulse_start() : ald_timer.c
  • ald_timer_one_pulse_start_by_it() : ald_timer.c
  • ald_timer_one_pulse_stop() : ald_timer.c
  • ald_timer_one_pulse_stop_by_it() : ald_timer.c
  • ald_timer_pwm_init() : ald_timer.c
  • ald_timer_pwm_set_duty() : ald_timer.c
  • ald_timer_pwm_set_freq() : ald_timer.c
  • ald_timer_pwm_set_input() : ald_timer.c
  • ald_timer_pwm_start() : ald_timer.c
  • ald_timer_pwm_start_by_dma() : ald_timer.c
  • ald_timer_pwm_start_by_it() : ald_timer.c
  • ald_timer_pwm_stop() : ald_timer.c
  • ald_timer_pwm_stop_by_dma() : ald_timer.c
  • ald_timer_pwm_stop_by_it() : ald_timer.c
  • ald_timer_pwmn_start() : ald_timer.c
  • ald_timer_pwmn_start_by_dma() : ald_timer.c
  • ald_timer_pwmn_start_by_it() : ald_timer.c
  • ald_timer_pwmn_stop() : ald_timer.c
  • ald_timer_pwmn_stop_by_dma() : ald_timer.c
  • ald_timer_pwmn_stop_by_it() : ald_timer.c
  • ald_timer_read_capture_value() : ald_timer.c
  • ald_timer_set_output_mode() : ald_timer.c
  • ald_timer_slave_config_sync() : ald_timer.c
  • ald_timer_slave_config_sync_by_it() : ald_timer.c
  • ald_trng_clear_flag_status() : ald_trng.c
  • ald_trng_get_flag_status() : ald_trng.c
  • ald_trng_get_it_status() : ald_trng.c
  • ald_trng_get_result() : ald_trng.c
  • ald_trng_get_status() : ald_trng.c
  • ald_trng_init() : ald_trng.c
  • ald_trng_interrupt_config() : ald_trng.c
  • ald_trng_irq_handler() : ald_trng.c
  • ald_tsense_get_value() : ald_tsense.c
  • ald_tsense_get_value_by_it() : ald_tsense.c
  • ald_tsense_init() : ald_tsense.c
  • ald_tsense_irq_handler() : ald_tsense.c
  • ald_tsense_source_select() : ald_tsense.c
  • ald_uart_auto_baud_config() : ald_uart.c
  • ald_uart_clear_flag_status() : ald_uart.c
  • ald_uart_dma_pause() : ald_uart.c
  • ald_uart_dma_req_config() : ald_uart.c
  • ald_uart_dma_resume() : ald_uart.c
  • ald_uart_dma_stop() : ald_uart.c
  • ald_uart_get_error() : ald_uart.c
  • ald_uart_get_flag_status() : ald_uart.c
  • ald_uart_get_it_status() : ald_uart.c
  • ald_uart_get_mask_flag_status() : ald_uart.c
  • ald_uart_get_state() : ald_uart.c
  • ald_uart_get_status() : ald_uart.c
  • ald_uart_init() : ald_uart.c
  • ald_uart_interrupt_config() : ald_uart.c
  • ald_uart_irq_handler() : ald_uart.c
  • ald_uart_irq_handler_fast() : ald_uart.c
  • ald_uart_lin_detect_break_len_config() : ald_uart.c
  • ald_uart_lin_send_break() : ald_uart.c
  • ald_uart_recv() : ald_uart.c
  • ald_uart_recv_by_dma() : ald_uart.c
  • ald_uart_recv_by_it() : ald_uart.c
  • ald_uart_recv_frame_by_it() : ald_uart.c
  • ald_uart_recv_n_lock() : ald_uart.c
  • ald_uart_reset() : ald_uart.c
  • ald_uart_rs485_config() : ald_uart.c
  • ald_uart_rs485_send_addr() : ald_uart.c
  • ald_uart_rx_fifo_config() : ald_uart.c
  • ald_uart_scard_config() : ald_uart.c
  • ald_uart_send() : ald_uart.c
  • ald_uart_send_by_dma() : ald_uart.c
  • ald_uart_send_by_it() : ald_uart.c
  • ald_uart_send_n_lock() : ald_uart.c
  • ald_uart_tx_fifo_config() : ald_uart.c
  • ald_usb_clock_output() : ald_usb.c
  • ald_usb_control_reset() : ald_usb.c
  • ald_usb_dev_connect() : ald_usb.c
  • ald_usb_dev_disconnect() : ald_usb.c
  • ald_usb_dev_ep_config() : ald_usb.c
  • ald_usb_dev_ep_data_ack() : ald_usb.c
  • ald_usb_dev_ep_get_config() : ald_usb.c
  • ald_usb_dev_ep_stall() : ald_usb.c
  • ald_usb_dev_ep_stall_clear() : ald_usb.c
  • ald_usb_dev_ep_status_clear() : ald_usb.c
  • ald_usb_dev_get_addr() : ald_usb.c
  • ald_usb_dev_lpm_config() : ald_usb.c
  • ald_usb_dev_lpm_disable() : ald_usb.c
  • ald_usb_dev_lpm_enable() : ald_usb.c
  • ald_usb_dev_lpm_remote_wake() : ald_usb.c
  • ald_usb_dev_set_addr() : ald_usb.c
  • ald_usb_device_speed_get() : ald_usb.c
  • ald_usb_dma_channel_config() : ald_usb.c
  • ald_usb_dma_channel_start() : ald_usb.c
  • ald_usb_dma_channel_stop() : ald_usb.c
  • ald_usb_dma_clear_channel_error() : ald_usb.c
  • ald_usb_dma_get_channel_error() : ald_usb.c
  • ald_usb_dma_get_interrupt_flag() : ald_usb.c
  • ald_usb_dma_mult_recv_start() : ald_usb.c
  • ald_usb_ep_data_avail() : ald_usb.c
  • ald_usb_ep_data_get() : ald_usb.c
  • ald_usb_ep_data_put() : ald_usb.c
  • ald_usb_ep_data_send() : ald_usb.c
  • ald_usb_ep_data_toggle_clear() : ald_usb.c
  • ald_usb_ep_dma_config() : ald_usb.c
  • ald_usb_ep_req_packet_count() : ald_usb.c
  • ald_usb_ep_status() : ald_usb.c
  • ald_usb_eye_diagram_start() : ald_usb.c
  • ald_usb_fifo_addr_get() : ald_usb.c
  • ald_usb_fifo_config_get() : ald_usb.c
  • ald_usb_fifo_config_set() : ald_usb.c
  • ald_usb_fifo_flush() : ald_usb.c
  • ald_usb_frame_number_get() : ald_usb.c
  • ald_usb_high_speed_enable() : ald_usb.c
  • ald_usb_host_addr_get() : ald_usb.c
  • ald_usb_host_addr_set() : ald_usb.c
  • ald_usb_host_ep_config() : ald_usb.c
  • ald_usb_host_ep_data_ack() : ald_usb.c
  • ald_usb_host_ep_data_toggle() : ald_usb.c
  • ald_usb_host_ep_ping() : ald_usb.c
  • ald_usb_host_ep_speed_set() : ald_usb.c
  • ald_usb_host_ep_status_clear() : ald_usb.c
  • ald_usb_host_hub_addr_get() : ald_usb.c
  • ald_usb_host_hub_addr_set() : ald_usb.c
  • ald_usb_host_lpm_config() : ald_usb.c
  • ald_usb_host_lpm_resume() : ald_usb.c
  • ald_usb_host_lpm_send() : ald_usb.c
  • ald_usb_host_pwr_config() : ald_usb.c
  • ald_usb_host_pwr_disable() : ald_usb.c
  • ald_usb_host_pwr_enable() : ald_usb.c
  • ald_usb_host_pwr_fault_disable() : ald_usb.c
  • ald_usb_host_pwr_fault_enable() : ald_usb.c
  • ald_usb_host_request_in() : ald_usb.c
  • ald_usb_host_request_in_clear() : ald_usb.c
  • ald_usb_host_request_status() : ald_usb.c
  • ald_usb_host_reset() : ald_usb.c
  • ald_usb_host_resume() : ald_usb.c
  • ald_usb_host_speed_get() : ald_usb.c
  • ald_usb_host_suspend() : ald_usb.c
  • ald_usb_int_disable() : ald_usb.c
  • ald_usb_int_disable_ep() : ald_usb.c
  • ald_usb_int_enable() : ald_usb.c
  • ald_usb_int_enable_ep() : ald_usb.c
  • ald_usb_int_num_get() : ald_usb.c
  • ald_usb_int_register() : ald_usb.c
  • ald_usb_int_status_ep_get() : ald_usb.c
  • ald_usb_int_status_get() : ald_usb.c
  • ald_usb_int_unregister() : ald_usb.c
  • ald_usb_lpm_ep_get() : ald_usb.c
  • ald_usb_lpm_int_disable() : ald_usb.c
  • ald_usb_lpm_int_enable() : ald_usb.c
  • ald_usb_lpm_int_status_get() : ald_usb.c
  • ald_usb_lpm_link_status_get() : ald_usb.c
  • ald_usb_lpm_remote_wake_is_enable() : ald_usb.c
  • ald_usb_mode_get() : ald_usb.c
  • ald_usb_num_ep_get() : ald_usb.c
  • ald_usb_otg_session_request() : ald_usb.c
  • ald_vtor_config() : ald_syscfg.h
  • ald_wait_flag() : utils.c
  • ald_wwdt_clear_flag_status() : ald_wdt.c
  • ald_wwdt_feed_dog() : ald_wdt.c
  • ald_wwdt_get_flag_status() : ald_wdt.c
  • ald_wwdt_get_value() : ald_wdt.c
  • ald_wwdt_init() : ald_wdt.c
  • ald_wwdt_start() : ald_wdt.c


ALD User Manual: Globals

- b -

  • bcd_to_dec() : ald_rtc.c
  • BITBAND_PER() : type.h
  • BITBAND_SRAM() : type.h


ALD User Manual: Globals

- c -

  • can_clear_flag() : ald_can.c
  • can_rx_fifo_release() : ald_can.c
  • cmu_clock_update() : ald_cmu.c
  • crc_dma_calculate_cplt() : ald_crc.c
  • crc_dma_error() : ald_crc.c
  • crypt_dma_crypt_cplt() : ald_crypt.c
  • crypt_dma_error() : ald_crypt.c
  • crypt_reset() : ald_crypt.c


ALD User Manual: Globals

- d -

  • dec_to_bcd() : ald_rtc.c
  • delay_losc_clk() : ald_rtchw.c
  • dma_config_base() : ald_dma.c


ALD User Manual: Globals

- f -

  • flash_lock() : ald_flash.c
  • flash_page_erase() : ald_flash.c
  • flash_unlock() : ald_flash.c
  • flash_word_program() : ald_flash.c


ALD User Manual: Globals

- g -

  • gcm_mul() : ald_crypt.c


ALD User Manual: Globals

- i -

  • i2c_dma_error() : ald_i2c.c
  • i2c_dma_master_recv_cplt() : ald_i2c.c
  • i2c_dma_master_send_cplt() : ald_i2c.c
  • i2c_dma_mem_recv_cplt() : ald_i2c.c
  • i2c_dma_mem_send_cplt() : ald_i2c.c
  • i2c_dma_slave_recv_cplt() : ald_i2c.c
  • i2c_dma_slave_send_cplt() : ald_i2c.c
  • i2c_master_recv_rxne() : ald_i2c.c
  • i2c_master_recv_tc() : ald_i2c.c
  • i2c_master_req_read() : ald_i2c.c
  • i2c_master_req_write() : ald_i2c.c
  • i2c_master_send_tc() : ald_i2c.c
  • i2c_master_send_txe() : ald_i2c.c
  • i2c_req_mem_read() : ald_i2c.c
  • i2c_req_mem_write() : ald_i2c.c
  • i2c_slave_recv_rxne() : ald_i2c.c
  • i2c_slave_send_txe() : ald_i2c.c
  • i2c_slave_stopf() : ald_i2c.c
  • i2c_speed_init() : ald_i2c.c
  • i2c_wait_flag_change_to_timeout() : ald_i2c.c
  • i2c_wait_master_addr_to_timeout() : ald_i2c.c
  • i2c_wait_rxne_to_timeout() : ald_i2c.c
  • i2c_wait_txe_to_timeout() : ald_i2c.c
  • i2s_dma_error() : ald_i2s.c
  • i2s_dma_recv_cplt() : ald_i2s.c
  • i2s_dma_send_cplt() : ald_i2s.c
  • i2s_wait_status() : ald_i2s.c


ALD User Manual: Globals

- n -

  • nand_config_device() : ald_nand.c


ALD User Manual: Globals

- p -

  • page_have_writen() : ald_flash_ext.c


ALD User Manual: Globals

- q -

  • qspi_clear_flag_status() : ald_qspi.c
  • qspi_dac_config() : ald_qspi.c
  • qspi_get_flag_status() : ald_qspi.c
  • qspi_indrd_get_status() : ald_qspi.c
  • qspi_indrd_wait_flag() : ald_qspi.c
  • qspi_indwr_get_status() : ald_qspi.c
  • qspi_indwr_wait_flag() : ald_qspi.c
  • qspi_read_sram_fill_level() : ald_qspi.c
  • qspi_wait_for_idle() : ald_qspi.c


ALD User Manual: Globals

- r -

  • rtc_consistency_check() : ald_rtc.c
  • rtc_hw_auto_check() : ald_rtchw.c


ALD User Manual: Globals

- s -

  • spi_dma_recv_cplt() : ald_spi.c
  • spi_dma_send_cplt() : ald_spi.c
  • spi_dma_send_recv_cplt() : ald_spi.c
  • spi_fifo_threshold_config() : ald_spi.c
  • spi_get_status() : ald_spi.c
  • spi_wait_bsy_flag() : ald_spi.c
  • spi_wait_flag_irq() : ald_spi.c


ALD User Manual: Globals

- t -

  • timer_base_set_config() : ald_timer.c
  • timer_ccx_channel_cmd() : ald_timer.c
  • timer_ccxn_channel_cmd() : ald_timer.c
  • timer_dma_capture_cplt() : ald_timer.c
  • timer_dma_error() : ald_timer.c
  • timer_dma_msel() : ald_timer.c
  • timer_dma_oc_cplt() : ald_timer.c
  • timer_dma_period_elapse_cplt() : ald_timer.c
  • timer_etr_set_config() : ald_timer.c
  • timer_oc1_set_config() : ald_timer.c
  • timer_oc2_set_config() : ald_timer.c
  • timer_oc3_set_config() : ald_timer.c
  • timer_oc4_set_config() : ald_timer.c
  • timer_slave_set_config() : ald_timer.c
  • timer_ti1_set_config() : ald_timer.c
  • timer_ti1_set_config_stage() : ald_timer.c
  • timer_ti2_set_config() : ald_timer.c
  • timer_ti2_set_config_stage() : ald_timer.c
  • timer_ti3_set_config() : ald_timer.c
  • timer_ti4_set_config() : ald_timer.c
  • trng_reset() : ald_trng.c


ALD User Manual: Globals

- u -

  • uart_dma_error() : ald_uart.c
  • uart_dma_recv_cplt() : ald_uart.c
  • uart_dma_send_cplt() : ald_uart.c
  • uart_lin_break_detect_irq() : ald_uart.c
  • uart_wait_flag() : ald_uart.c


ALD User Manual: Globals

  • __system_clock : ald_cmu.c
  • __systick_interval : utils.c , utils.h
  • __tsense_cbk : ald_tsense.c
  • dma0_cbk : ald_dma.c
  • lib_tick : utils.c
  • NORMEMDATWIDTH : ald_nor_lcd.c
  • OP_CMD : ald_flash.c
  • write_buf : ald_flash_ext.c


ALD User Manual: Globals

  • acmp_handle_t : ald_acmp.h
  • adc_handle_t : ald_adc.h
  • can_handle_t : ald_can.h
  • crc_handle_t : ald_crc.h
  • crypt_handle_t : ald_crypt.h
  • dac_handle_t : ald_dac.h
  • i2c_handle_t : ald_i2c.h
  • i2s_handle_t : ald_i2s.h
  • IAP_DWP : ald_iap.h
  • IAP_PE : ald_iap.h
  • IAP_WP : ald_iap.h
  • IAP_WSP : ald_iap.h
  • it_status_t : type.h
  • pis_handle_t : ald_pis.h
  • spi_handle_t : ald_spi.h
  • timer_handle_t : ald_timer.h
  • trng_handle_t : ald_trng.h
  • tsense_cbk : ald_tsense.h
  • uart_handle_t : ald_uart.h


ALD User Manual: Globals

- a -

  • acmp_edge_t : ald_acmp.h
  • acmp_flag_t : ald_acmp.h
  • acmp_hystsel_t : ald_acmp.h
  • acmp_inactval_t : ald_acmp.h
  • acmp_it_t : ald_acmp.h
  • acmp_mode_t : ald_acmp.h
  • acmp_neg_input_t : ald_acmp.h
  • acmp_out_func_t : ald_acmp.h
  • acmp_pos_input_t : ald_acmp.h
  • acmp_status_t : ald_acmp.h
  • acmp_warm_time_t : ald_acmp.h
  • adc_align_t : ald_adc.h
  • adc_ana_wdg_t : ald_adc.h
  • adc_channel_t : ald_adc.h
  • adc_clk_div_t : ald_adc.h
  • adc_conv_bit_t : ald_adc.h
  • adc_disc_mode_t : ald_adc.h
  • adc_disc_nr_t : ald_adc.h
  • adc_error_t : ald_adc.h
  • adc_ets_t : ald_adc.h
  • adc_event_type_t : ald_adc.h
  • adc_flag_t : ald_adc.h
  • adc_ich_idx_t : ald_adc.h
  • adc_ich_nr_t : ald_adc.h
  • adc_it_t : ald_adc.h
  • adc_nch_idx_t : ald_adc.h
  • adc_nch_nr_t : ald_adc.h
  • adc_nchesel_t : ald_adc.h
  • adc_neg_ref_t : ald_adc.h
  • adc_pos_ref_t : ald_adc.h
  • adc_samp_t : ald_adc.h
  • adc_state_t : ald_adc.h
  • ald_nand_state_t : ald_nand.h
  • ald_nor_state_t : ald_nor_lcd.h
  • ald_sram_state_t : ald_sram.h
  • ald_status_t : utils.h


ALD User Manual: Globals

- b -

  • bit_status_t : type.h
  • bkpc_preh_clk_t : ald_bkpc.h
  • bkpc_wakeup_level_t : ald_bkpc.h
  • bkpc_wakeup_port_t : ald_bkpc.h


ALD User Manual: Globals

- c -

  • can_error_t : ald_can.h
  • can_filter_fifo_t : ald_can.h
  • can_filter_mode_t : ald_can.h
  • can_filter_scale_t : ald_can.h
  • can_flag_t : ald_can.h
  • can_id_type_t : ald_can.h
  • can_it_t : ald_can.h
  • can_operate_mode_t : ald_can.h
  • can_remote_req_t : ald_can.h
  • can_rx_fifo_t : ald_can.h
  • can_seg1_t : ald_can.h
  • can_seg2_t : ald_can.h
  • can_sjw_t : ald_can.h
  • can_state_t : ald_can.h
  • can_tx_mailbox_t : ald_can.h
  • cmu_bus_t : ald_cmu.h
  • cmu_buzz_div_t : ald_cmu.h
  • cmu_clock_safe_type_t : ald_cmu.h
  • cmu_clock_state_t : ald_cmu.h
  • cmu_clock_t : ald_cmu.h
  • cmu_div_t : ald_cmu.h
  • cmu_hosc_range_t : ald_cmu.h
  • cmu_lcd_clock_sel_t : ald_cmu.h
  • cmu_lp_perh_clock_sel_t : ald_cmu.h
  • cmu_output_high_div_t : ald_cmu.h
  • cmu_output_high_sel_t : ald_cmu.h
  • cmu_output_low_sel_t : ald_cmu.h
  • cmu_perh_t : ald_cmu.h
  • cmu_pll1_input_t : ald_cmu.h
  • cmu_pll1_output_t : ald_cmu.h
  • cmu_qspi_clock_sel_t : ald_cmu.h
  • cmu_security_t : ald_cmu.h
  • cmu_stop1_clock_t : ald_cmu.h
  • cmu_usb_clock_sel_t : ald_cmu.h
  • cmu_usb_div_t : ald_cmu.h
  • crc_datasize_t : ald_crc.h
  • crc_mode_t : ald_crc.h
  • crc_state_t : ald_crc.h
  • crc_werr_t : ald_crc.h
  • crypt_aesks_t : ald_crypt.h
  • crypt_crysel_t : ald_crypt.h
  • crypt_data_t : ald_crypt.h
  • crypt_datatype_t : ald_crypt.h
  • crypt_desks_t : ald_crypt.h
  • crypt_encs_t : ald_crypt.h
  • crypt_flag_t : ald_crypt.h
  • crypt_it_t : ald_crypt.h
  • crypt_ivr_len_t : ald_crypt.h
  • crypt_key_len_t : ald_crypt.h
  • crypt_ks_t : ald_crypt.h
  • crypt_mode_t : ald_crypt.h
  • crypt_state_t : ald_crypt.h


ALD User Manual: Globals

- d -

  • dac_channel_t : ald_dac.h
  • dac_conv_mode_t : ald_dac.h
  • dac_flag_t : ald_dac.h
  • dac_it_t : ald_dac.h
  • dac_neg_ref_t : ald_dac.h
  • dac_out_mode_t : ald_dac.h
  • dac_pissel_t : ald_dac.h
  • dac_pos_ref_t : ald_dac.h
  • dac_prescale_div_t : ald_dac.h
  • dac_refresh_t : ald_dac.h
  • dac_status_t : ald_dac.h
  • dac_trigger_t : ald_dac.h
  • dbgc_mode_t : ald_dbgc.h
  • dbgc_perh_t : ald_dbgc.h
  • dma_arbiter_config_t : ald_dma.h
  • dma_cycle_ctrl_t : ald_dma.h
  • dma_data_inc_t : ald_dma.h
  • dma_data_size_t : ald_dma.h
  • dma_descrp_cplt_t : ald_dma.h
  • dma_msel_t : ald_dma.h
  • dma_msigsel_t : ald_dma.h


ALD User Manual: Globals

- e -

  • ebi_access_mode_t : ald_ebi.h
  • ebi_asynchronous_wait_t : ald_ebi.h
  • ebi_burst_access_mode_t : ald_ebi.h
  • ebi_data_address_mux_t : ald_ebi.h
  • ebi_extended_mode_t : ald_ebi.h
  • ebi_flag_t : ald_ebi.h
  • ebi_it_t : ald_ebi.h
  • ebi_lcd_dclkpol_t : ald_ebi.h
  • ebi_lcd_denpol_t : ald_ebi.h
  • ebi_lcd_hsyncpol_t : ald_ebi.h
  • ebi_lcd_lcden_t : ald_ebi.h
  • ebi_lcd_lcdint_t : ald_ebi.h
  • ebi_lcd_vsyncpol_t : ald_ebi.h
  • ebi_md_ecc_page_size_t : ald_ebi.h
  • ebi_memory_type_t : ald_ebi.h
  • ebi_nand_ecc_t : ald_ebi.h
  • ebi_nand_mem_bus_width_t : ald_ebi.h
  • ebi_nand_wait_feature_t : ald_ebi.h
  • ebi_norsram_bank_t : ald_ebi.h
  • ebi_norsram_flash_access_t : ald_ebi.h
  • ebi_norsram_mem_bus_width_t : ald_ebi.h
  • ebi_pctrlr_memory_type_t : ald_ebi.h
  • ebi_wait_signal_polarity_t : ald_ebi.h
  • ebi_wait_signal_t : ald_ebi.h
  • ebi_wait_timing_t : ald_ebi.h
  • ebi_wrap_mode_t : ald_ebi.h
  • ebi_write_burst_t : ald_ebi.h
  • ebi_write_operation_t : ald_ebi.h
  • exti_filter_clock_t : ald_gpio.h
  • exti_trigger_style_t : ald_gpio.h


ALD User Manual: Globals

- f -

  • flag_status_t : type.h
  • flash_cmd_type : ald_flash.h


ALD User Manual: Globals

- g -

  • gpio_filter_t : ald_gpio.h
  • gpio_func_t : ald_gpio.h
  • gpio_mode_t : ald_gpio.h
  • gpio_odos_t : ald_gpio.h
  • gpio_out_drive_t : ald_gpio.h
  • gpio_push_t : ald_gpio.h
  • gpio_type_t : ald_gpio.h


ALD User Manual: Globals

- i -

  • i2c_addr1_t : ald_i2c.h
  • i2c_addr2_t : ald_i2c.h
  • i2c_addr_size_t : ald_i2c.h
  • i2c_addr_t : ald_i2c.h
  • i2c_clock_t : ald_i2c.h
  • i2c_con1_t : ald_i2c.h
  • i2c_con2_t : ald_i2c.h
  • i2c_dual_addr_t : ald_i2c.h
  • i2c_error_t : ald_i2c.h
  • i2c_general_addr_t : ald_i2c.h
  • i2c_interrupt_t : ald_i2c.h
  • i2c_mode_t : ald_i2c.h
  • i2c_module_t : ald_i2c.h
  • i2c_nostretch_t : ald_i2c.h
  • i2c_oar2_t : ald_i2c.h
  • i2c_stat_t : ald_i2c.h
  • i2c_state_t : ald_i2c.h
  • i2c_timoutr_t : ald_i2c.h
  • i2c_trise_t : ald_i2c.h
  • i2s_cfg_t : ald_i2s.h
  • i2s_ch_side_t : ald_i2s.h
  • i2s_chlen_t : ald_i2s.h
  • i2s_cpol_t : ald_i2s.h
  • i2s_datalen_t : ald_i2s.h
  • i2s_dma_req_t : ald_i2s.h
  • i2s_error_t : ald_i2s.h
  • i2s_flag_t : ald_i2s.h
  • i2s_it_t : ald_i2s.h
  • i2s_pcms_t : ald_i2s.h
  • i2s_sr_status_t : ald_i2s.h
  • i2s_standard_t : ald_i2s.h
  • i2s_state_t : ald_i2s.h
  • i2s_status_t : ald_i2s.h


ALD User Manual: Globals

- l -

  • lock_state_t : type.h


ALD User Manual: Globals

- n -

  • nor_status_t : ald_nor_lcd.h
  • nvic_priority_group_t : utils.h


ALD User Manual: Globals

- o -

  • op_cmd_type : ald_flash.h


ALD User Manual: Globals

- p -

  • pis_ch_t : ald_pis.h
  • pis_clock_t : ald_pis.h
  • pis_con_t : ald_pis.h
  • pis_edge_t : ald_pis.h
  • pis_input_sel_t : ald_pis.h
  • pis_modu_channel_t : ald_pis.h
  • pis_modu_level_t : ald_pis.h
  • pis_modu_src_t : ald_pis.h
  • pis_modu_targ_t : ald_pis.h
  • pis_out_ch_t : ald_pis.h
  • pis_output_t : ald_pis.h
  • pis_src_t : ald_pis.h
  • pis_state_t : ald_pis.h
  • pis_syncsel_t : ald_pis.h
  • pis_trig_t : ald_pis.h
  • pmu_ldo_18_mode_t : ald_pmu.h
  • pmu_ldo_lpmode_output_t : ald_pmu.h
  • pmu_lp_mode_t : ald_pmu.h
  • pmu_lvd_trigger_mode_t : ald_pmu.h
  • pmu_lvd_voltage_sel_t : ald_pmu.h
  • pmu_perh_power_t : ald_pmu.h
  • pmu_status_t : ald_pmu.h


ALD User Manual: Globals

- q -

  • qspi_clk_div_t : ald_qspi.h
  • qspi_cpha_t : ald_qspi.h
  • qspi_cpol_t : ald_qspi.h
  • qspi_data_sampled_t : ald_qspi.h
  • qspi_flag_t : ald_qspi.h
  • qspi_indrd_flag_t : ald_qspi.h
  • qspi_indwr_status_t : ald_qspi.h
  • qspi_it_t : ald_qspi.h
  • qspi_nss_decode_t : ald_qspi.h
  • qspi_nss_size_t : ald_qspi.h
  • qspi_nss_t : ald_qspi.h
  • qspi_sram_t : ald_qspi.h
  • qspi_state_t : ald_qspi.h
  • qspi_xfer_t : ald_qspi.h


ALD User Manual: Globals

- r -

  • rmu_bor_filter_t : ald_rmu.h
  • rmu_bor_vol_t : ald_rmu.h
  • rmu_peripheral_t : ald_rmu.h
  • rmu_state_t : ald_rmu.h
  • rtc_alarm_idx_t : ald_rtc.h
  • rtc_alarm_mask_t : ald_rtc.h
  • rtc_cali_calc_freq_t : ald_rtc.h
  • rtc_cali_calc_t : ald_rtc.h
  • rtc_cali_freq_t : ald_rtc.h
  • rtc_cali_tc_t : ald_rtc.h
  • rtc_clock_output_t : ald_rtc.h
  • rtc_flag_t : ald_rtc.h
  • rtc_format_t : ald_rtc.h
  • rtc_hour_format_t : ald_rtc.h
  • rtc_hw_cali_mode_t : ald_rtchw.h
  • rtc_it_t : ald_rtc.h
  • rtc_output_polarity_t : ald_rtc.h
  • rtc_output_select_t : ald_rtc.h
  • rtc_source_sel_t : ald_rtc.h
  • rtc_sub_second_mask_t : ald_rtc.h
  • rtc_tamper_duration_t : ald_rtc.h
  • rtc_tamper_idx_t : ald_rtc.h
  • rtc_tamper_sampling_freq_t : ald_rtc.h
  • rtc_tamper_trigger_t : ald_rtc.h
  • rtc_ts_signal_sel_t : ald_rtc.h
  • rtc_ts_trigger_style_t : ald_rtc.h
  • rtc_wakeup_clock_t : ald_rtc.h
  • rtc_week_day_sel_t : ald_rtc.h


ALD User Manual: Globals

- s -

  • scard_clk_div_t : ald_uart.h
  • scard_retry_t : ald_uart.h
  • spi_baud_t : ald_spi.h
  • spi_cpha_t : ald_spi.h
  • spi_cpol_t : ald_spi.h
  • spi_datasize_t : ald_spi.h
  • spi_direction_t : ald_spi.h
  • spi_dma_req_t : ald_spi.h
  • spi_error_t : ald_spi.h
  • spi_firstbit_t : ald_spi.h
  • spi_flag_t : ald_spi.h
  • spi_frame_t : ald_spi.h
  • spi_it_t : ald_spi.h
  • spi_mode_t : ald_spi.h
  • spi_sr_status_t : ald_spi.h
  • spi_state_t : ald_spi.h
  • spi_status_t : ald_spi.h
  • systick_interval_t : utils.h


ALD User Manual: Globals

- t -

  • timer_active_channel_t : ald_timer.h
  • timer_break_polarity_t : ald_timer.h
  • timer_channel_t : ald_timer.h
  • timer_chnref_clr_sel_t : ald_timer.h
  • timer_clear_input_polarity_t : ald_timer.h
  • timer_clear_input_source_t : ald_timer.h
  • timer_clock_division_t : ald_timer.h
  • timer_clock_polarity_t : ald_timer.h
  • timer_clock_source_t : ald_timer.h
  • timer_cnt_mode_t : ald_timer.h
  • timer_dma_req_t : ald_timer.h
  • timer_encoder_mode_t : ald_timer.h
  • timer_etr_psc_t : ald_timer.h
  • timer_event_source_t : ald_timer.h
  • timer_flag_t : ald_timer.h
  • timer_ic_polarity_t : ald_timer.h
  • timer_ic_prescaler_t : ald_timer.h
  • timer_ic_select_t : ald_timer.h
  • timer_it_t : ald_timer.h
  • timer_lock_level_t : ald_timer.h
  • timer_master_mode_sel_t : ald_timer.h
  • timer_oc_idle_t : ald_timer.h
  • timer_oc_mode_t : ald_timer.h
  • timer_oc_polarity_t : ald_timer.h
  • timer_ocn_idle_t : ald_timer.h
  • timer_ocn_polarity_t : ald_timer.h
  • timer_op_mode_t : ald_timer.h
  • timer_op_output_channel_t : ald_timer.h
  • timer_slave_mode_t : ald_timer.h
  • timer_state_t : ald_timer.h
  • timer_ts_t : ald_timer.h
  • trng_data_width_t : ald_trng.h
  • trng_flag_t : ald_trng.h
  • trng_it_t : ald_trng.h
  • trng_seed_type_t : ald_trng.h
  • trng_state_t : ald_trng.h
  • trng_status_t : ald_trng.h
  • tsense_output_mode_t : ald_tsense.h
  • tsense_source_sel_t : ald_tsense.h
  • tsense_update_cycle_t : ald_tsense.h
  • type_bool_t : type.h
  • type_func_t : type.h


ALD User Manual: Globals

- u -

  • uart_auto_baud_mode_t : ald_uart.h
  • uart_dma_req_t : ald_uart.h
  • uart_error_t : ald_uart.h
  • uart_flag_t : ald_uart.h
  • uart_hw_flow_ctl_t : ald_uart.h
  • uart_it_t : ald_uart.h
  • uart_lin_break_len_t : ald_uart.h
  • uart_mode_t : ald_uart.h
  • uart_parity_t : ald_uart.h
  • uart_rxfifo_t : ald_uart.h
  • uart_state_t : ald_uart.h
  • uart_status_t : ald_uart.h
  • uart_stop_bits_t : ald_uart.h
  • uart_txfifo_t : ald_uart.h
  • uart_word_length_t : ald_uart.h


ALD User Manual: Globals

- w -

  • wwdt_win_t : ald_wdt.h


ALD User Manual: Globals

- a -

  • ACMP_128_PCLK : ald_acmp.h
  • ACMP_16_PCLK : ald_acmp.h
  • ACMP_256_PCLK : ald_acmp.h
  • ACMP_32_PCLK : ald_acmp.h
  • ACMP_4_PCLK : ald_acmp.h
  • ACMP_512_PCLK : ald_acmp.h
  • ACMP_64_PCLK : ald_acmp.h
  • ACMP_8_PCLK : ald_acmp.h
  • ACMP_EDGE_ALL : ald_acmp.h
  • ACMP_EDGE_FALL : ald_acmp.h
  • ACMP_EDGE_NONE : ald_acmp.h
  • ACMP_EDGE_RISE : ald_acmp.h
  • ACMP_FLAG_EDGE : ald_acmp.h
  • ACMP_FLAG_WARMUP : ald_acmp.h
  • ACMP_HIGH_POWER : ald_acmp.h
  • ACMP_HYST_0 : ald_acmp.h
  • ACMP_HYST_15 : ald_acmp.h
  • ACMP_HYST_22 : ald_acmp.h
  • ACMP_HYST_29 : ald_acmp.h
  • ACMP_HYST_36 : ald_acmp.h
  • ACMP_HYST_43 : ald_acmp.h
  • ACMP_HYST_50 : ald_acmp.h
  • ACMP_HYST_57 : ald_acmp.h
  • ACMP_INACTVAL_HIGH : ald_acmp.h
  • ACMP_INACTVAL_LOW : ald_acmp.h
  • ACMP_IT_EDGE : ald_acmp.h
  • ACMP_IT_WARMUP : ald_acmp.h
  • ACMP_LOW_POWER : ald_acmp.h
  • ACMP_MIDDLE_POWER : ald_acmp.h
  • ACMP_NEG_1V25 : ald_acmp.h
  • ACMP_NEG_2V5 : ald_acmp.h
  • ACMP_NEG_CH0 : ald_acmp.h
  • ACMP_NEG_CH1 : ald_acmp.h
  • ACMP_NEG_CH2 : ald_acmp.h
  • ACMP_NEG_CH3 : ald_acmp.h
  • ACMP_NEG_CH4 : ald_acmp.h
  • ACMP_NEG_CH5 : ald_acmp.h
  • ACMP_NEG_CH6 : ald_acmp.h
  • ACMP_NEG_CH7 : ald_acmp.h
  • ACMP_NEG_VDD : ald_acmp.h
  • ACMP_OUT_DISABLE : ald_acmp.h
  • ACMP_OUT_ENABLE : ald_acmp.h
  • ACMP_POS_CH0 : ald_acmp.h
  • ACMP_POS_CH1 : ald_acmp.h
  • ACMP_POS_CH2 : ald_acmp.h
  • ACMP_POS_CH3 : ald_acmp.h
  • ACMP_POS_CH4 : ald_acmp.h
  • ACMP_POS_CH5 : ald_acmp.h
  • ACMP_POS_CH6 : ald_acmp.h
  • ACMP_POS_CH7 : ald_acmp.h
  • ACMP_STATUS_ACT : ald_acmp.h
  • ACMP_STATUS_OUT : ald_acmp.h
  • ACMP_ULTRA_LOW_POWER : ald_acmp.h
  • ADC_ALL_DISABLE : ald_adc.h
  • ADC_ANAWTD_ALL_IST : ald_adc.h
  • ADC_ANAWTD_ALL_NM : ald_adc.h
  • ADC_ANAWTD_ALL_NMIST : ald_adc.h
  • ADC_ANAWTD_NONE : ald_adc.h
  • ADC_ANAWTD_SING_IST : ald_adc.h
  • ADC_ANAWTD_SING_NM : ald_adc.h
  • ADC_ANAWTD_SING_NMIST : ald_adc.h
  • ADC_AWD_EVENT : ald_adc.h
  • ADC_CHANNEL_0 : ald_adc.h
  • ADC_CHANNEL_1 : ald_adc.h
  • ADC_CHANNEL_10 : ald_adc.h
  • ADC_CHANNEL_11 : ald_adc.h
  • ADC_CHANNEL_12 : ald_adc.h
  • ADC_CHANNEL_13 : ald_adc.h
  • ADC_CHANNEL_14 : ald_adc.h
  • ADC_CHANNEL_15 : ald_adc.h
  • ADC_CHANNEL_16 : ald_adc.h
  • ADC_CHANNEL_17 : ald_adc.h
  • ADC_CHANNEL_18 : ald_adc.h
  • ADC_CHANNEL_2 : ald_adc.h
  • ADC_CHANNEL_3 : ald_adc.h
  • ADC_CHANNEL_4 : ald_adc.h
  • ADC_CHANNEL_5 : ald_adc.h
  • ADC_CHANNEL_6 : ald_adc.h
  • ADC_CHANNEL_7 : ald_adc.h
  • ADC_CHANNEL_8 : ald_adc.h
  • ADC_CHANNEL_9 : ald_adc.h
  • ADC_CKDIV_1 : ald_adc.h
  • ADC_CKDIV_128 : ald_adc.h
  • ADC_CKDIV_16 : ald_adc.h
  • ADC_CKDIV_2 : ald_adc.h
  • ADC_CKDIV_32 : ald_adc.h
  • ADC_CKDIV_4 : ald_adc.h
  • ADC_CKDIV_64 : ald_adc.h
  • ADC_CKDIV_8 : ald_adc.h
  • ADC_CONV_BIT_10 : ald_adc.h
  • ADC_CONV_BIT_12 : ald_adc.h
  • ADC_CONV_BIT_6 : ald_adc.h
  • ADC_CONV_BIT_8 : ald_adc.h
  • ADC_DATAALIGN_LEFT : ald_adc.h
  • ADC_DATAALIGN_RIGHT : ald_adc.h
  • ADC_DISC_NR_1 : ald_adc.h
  • ADC_DISC_NR_2 : ald_adc.h
  • ADC_DISC_NR_3 : ald_adc.h
  • ADC_DISC_NR_4 : ald_adc.h
  • ADC_DISC_NR_5 : ald_adc.h
  • ADC_DISC_NR_6 : ald_adc.h
  • ADC_DISC_NR_7 : ald_adc.h
  • ADC_DISC_NR_8 : ald_adc.h
  • ADC_ERROR_DMA : ald_adc.h
  • ADC_ERROR_INTERNAL : ald_adc.h
  • ADC_ERROR_NONE : ald_adc.h
  • ADC_ERROR_OVR : ald_adc.h
  • ADC_ETS_DISABLE : ald_adc.h
  • ADC_ETS_FALL : ald_adc.h
  • ADC_ETS_RISE : ald_adc.h
  • ADC_ETS_RISE_FALL : ald_adc.h
  • ADC_FLAG_AWD : ald_adc.h
  • ADC_FLAG_ICH : ald_adc.h
  • ADC_FLAG_ICHS : ald_adc.h
  • ADC_FLAG_NCH : ald_adc.h
  • ADC_FLAG_NCHS : ald_adc.h
  • ADC_FLAG_OVR : ald_adc.h
  • ADC_ICH_DISC_EN : ald_adc.h
  • ADC_ICH_IDX_1 : ald_adc.h
  • ADC_ICH_IDX_2 : ald_adc.h
  • ADC_ICH_IDX_3 : ald_adc.h
  • ADC_ICH_IDX_4 : ald_adc.h
  • ADC_ICH_NR_1 : ald_adc.h
  • ADC_ICH_NR_2 : ald_adc.h
  • ADC_ICH_NR_3 : ald_adc.h
  • ADC_ICH_NR_4 : ald_adc.h
  • ADC_IT_AWD : ald_adc.h
  • ADC_IT_ICH : ald_adc.h
  • ADC_IT_NCH : ald_adc.h
  • ADC_IT_OVR : ald_adc.h
  • ADC_NCH_DISC_EN : ald_adc.h
  • ADC_NCH_IDX_1 : ald_adc.h
  • ADC_NCH_IDX_10 : ald_adc.h
  • ADC_NCH_IDX_11 : ald_adc.h
  • ADC_NCH_IDX_12 : ald_adc.h
  • ADC_NCH_IDX_13 : ald_adc.h
  • ADC_NCH_IDX_14 : ald_adc.h
  • ADC_NCH_IDX_15 : ald_adc.h
  • ADC_NCH_IDX_16 : ald_adc.h
  • ADC_NCH_IDX_2 : ald_adc.h
  • ADC_NCH_IDX_3 : ald_adc.h
  • ADC_NCH_IDX_4 : ald_adc.h
  • ADC_NCH_IDX_5 : ald_adc.h
  • ADC_NCH_IDX_6 : ald_adc.h
  • ADC_NCH_IDX_7 : ald_adc.h
  • ADC_NCH_IDX_8 : ald_adc.h
  • ADC_NCH_IDX_9 : ald_adc.h
  • ADC_NCH_NR_1 : ald_adc.h
  • ADC_NCH_NR_10 : ald_adc.h
  • ADC_NCH_NR_11 : ald_adc.h
  • ADC_NCH_NR_12 : ald_adc.h
  • ADC_NCH_NR_13 : ald_adc.h
  • ADC_NCH_NR_14 : ald_adc.h
  • ADC_NCH_NR_15 : ald_adc.h
  • ADC_NCH_NR_16 : ald_adc.h
  • ADC_NCH_NR_2 : ald_adc.h
  • ADC_NCH_NR_3 : ald_adc.h
  • ADC_NCH_NR_4 : ald_adc.h
  • ADC_NCH_NR_5 : ald_adc.h
  • ADC_NCH_NR_6 : ald_adc.h
  • ADC_NCH_NR_7 : ald_adc.h
  • ADC_NCH_NR_8 : ald_adc.h
  • ADC_NCH_NR_9 : ald_adc.h
  • ADC_NCHESEL_MODE_ALL : ald_adc.h
  • ADC_NCHESEL_MODE_ONE : ald_adc.h
  • ADC_NEG_REF_VREFN : ald_adc.h
  • ADC_NEG_REF_VSS : ald_adc.h
  • ADC_POS_REF_2V : ald_adc.h
  • ADC_POS_REF_VDD : ald_adc.h
  • ADC_POS_REF_VREEFP : ald_adc.h
  • ADC_POS_REF_VREEFP_BUF : ald_adc.h
  • ADC_SAMPLETIME_1 : ald_adc.h
  • ADC_SAMPLETIME_15 : ald_adc.h
  • ADC_SAMPLETIME_2 : ald_adc.h
  • ADC_SAMPLETIME_4 : ald_adc.h
  • ADC_STATE_BUSY : ald_adc.h
  • ADC_STATE_BUSY_I : ald_adc.h
  • ADC_STATE_BUSY_N : ald_adc.h
  • ADC_STATE_BUSY_WDG : ald_adc.h
  • ADC_STATE_ERROR : ald_adc.h
  • ADC_STATE_READY : ald_adc.h
  • ADC_STATE_RESET : ald_adc.h
  • ADC_STATE_TIMEOUT : ald_adc.h
  • ALD_NAND_STATE_BUSY : ald_nand.h
  • ALD_NAND_STATE_ERROR : ald_nand.h
  • ALD_NAND_STATE_READY : ald_nand.h
  • ALD_NAND_STATE_RESET : ald_nand.h
  • ALD_NOR_STATE_BUSY : ald_nor_lcd.h
  • ALD_NOR_STATE_ERROR : ald_nor_lcd.h
  • ALD_NOR_STATE_PROTECTED : ald_nor_lcd.h
  • ALD_NOR_STATE_READY : ald_nor_lcd.h
  • ALD_NOR_STATE_RESET : ald_nor_lcd.h
  • ALD_NOR_STATUS_ERROR : ald_nor_lcd.h
  • ALD_NOR_STATUS_ONGOING : ald_nor_lcd.h
  • ALD_NOR_STATUS_SUCCESS : ald_nor_lcd.h
  • ALD_NOR_STATUS_TIMEOUT : ald_nor_lcd.h
  • ALD_SRAM_STATE_BUSY : ald_sram.h
  • ALD_SRAM_STATE_ERROR : ald_sram.h
  • ALD_SRAM_STATE_PROTECTED : ald_sram.h
  • ALD_SRAM_STATE_READY : ald_sram.h
  • ALD_SRAM_STATE_RESET : ald_sram.h


ALD User Manual: Globals

- b -

  • BIT_RESET : type.h
  • BIT_SET : type.h
  • BKPC_PREH_CLK_HOSC_1M : ald_bkpc.h
  • BKPC_PREH_CLK_HRC_1M : ald_bkpc.h
  • BKPC_PREH_CLK_LOSM : ald_bkpc.h
  • BKPC_PREH_CLK_LRC : ald_bkpc.h
  • BUSY : utils.h


ALD User Manual: Globals

- c -

  • CAN_ERROR_ACK : ald_can.h
  • CAN_ERROR_BD : ald_can.h
  • CAN_ERROR_BOF : ald_can.h
  • CAN_ERROR_BR : ald_can.h
  • CAN_ERROR_CRC : ald_can.h
  • CAN_ERROR_EPV : ald_can.h
  • CAN_ERROR_EWG : ald_can.h
  • CAN_ERROR_FOR : ald_can.h
  • CAN_ERROR_NONE : ald_can.h
  • CAN_ERROR_STF : ald_can.h
  • CAN_ERROR_UNK : ald_can.h
  • CAN_FILTER_FIFO0 : ald_can.h
  • CAN_FILTER_FIFO1 : ald_can.h
  • CAN_FILTER_MODE_LIST : ald_can.h
  • CAN_FILTER_MODE_MASK : ald_can.h
  • CAN_FILTER_SCALE_16 : ald_can.h
  • CAN_FILTER_SCALE_32 : ald_can.h
  • CAN_FLAG_BOF : ald_can.h
  • CAN_FLAG_ERR : ald_can.h
  • CAN_FLAG_FF0 : ald_can.h
  • CAN_FLAG_FF1 : ald_can.h
  • CAN_FLAG_FOV0 : ald_can.h
  • CAN_FLAG_FOV1 : ald_can.h
  • CAN_FLAG_M0REQC : ald_can.h
  • CAN_FLAG_M0TXC : ald_can.h
  • CAN_FLAG_M1REQC : ald_can.h
  • CAN_FLAG_M1TXC : ald_can.h
  • CAN_FLAG_M2REQC : ald_can.h
  • CAN_FLAG_M2TXC : ald_can.h
  • CAN_FLAG_PERR : ald_can.h
  • CAN_FLAG_SLP : ald_can.h
  • CAN_FLAG_SLPS : ald_can.h
  • CAN_FLAG_TXM0 : ald_can.h
  • CAN_FLAG_TXM1 : ald_can.h
  • CAN_FLAG_TXM2 : ald_can.h
  • CAN_FLAG_WARN : ald_can.h
  • CAN_FLAG_WK : ald_can.h
  • CAN_ID_EXT : ald_can.h
  • CAN_ID_STD : ald_can.h
  • CAN_IT_BOF : ald_can.h
  • CAN_IT_ERR : ald_can.h
  • CAN_IT_FF0 : ald_can.h
  • CAN_IT_FF1 : ald_can.h
  • CAN_IT_FOV0 : ald_can.h
  • CAN_IT_FOV1 : ald_can.h
  • CAN_IT_FP0 : ald_can.h
  • CAN_IT_FP1 : ald_can.h
  • CAN_IT_PERR : ald_can.h
  • CAN_IT_PRERR : ald_can.h
  • CAN_IT_SLP : ald_can.h
  • CAN_IT_TXM : ald_can.h
  • CAN_IT_WARN : ald_can.h
  • CAN_IT_WK : ald_can.h
  • CAN_MODE_LOOPBACK : ald_can.h
  • CAN_MODE_NORMAL : ald_can.h
  • CAN_MODE_SILENT : ald_can.h
  • CAN_MODE_SILENT_LOOPBACK : ald_can.h
  • CAN_RTR_DATA : ald_can.h
  • CAN_RTR_REMOTE : ald_can.h
  • CAN_RX_FIFO0 : ald_can.h
  • CAN_RX_FIFO1 : ald_can.h
  • CAN_SEG1_1 : ald_can.h
  • CAN_SEG1_10 : ald_can.h
  • CAN_SEG1_11 : ald_can.h
  • CAN_SEG1_12 : ald_can.h
  • CAN_SEG1_13 : ald_can.h
  • CAN_SEG1_14 : ald_can.h
  • CAN_SEG1_15 : ald_can.h
  • CAN_SEG1_16 : ald_can.h
  • CAN_SEG1_2 : ald_can.h
  • CAN_SEG1_3 : ald_can.h
  • CAN_SEG1_4 : ald_can.h
  • CAN_SEG1_5 : ald_can.h
  • CAN_SEG1_6 : ald_can.h
  • CAN_SEG1_7 : ald_can.h
  • CAN_SEG1_8 : ald_can.h
  • CAN_SEG1_9 : ald_can.h
  • CAN_SEG2_1 : ald_can.h
  • CAN_SEG2_2 : ald_can.h
  • CAN_SEG2_3 : ald_can.h
  • CAN_SEG2_4 : ald_can.h
  • CAN_SEG2_5 : ald_can.h
  • CAN_SEG2_6 : ald_can.h
  • CAN_SEG2_7 : ald_can.h
  • CAN_SEG2_8 : ald_can.h
  • CAN_SJW_1 : ald_can.h
  • CAN_SJW_2 : ald_can.h
  • CAN_SJW_3 : ald_can.h
  • CAN_SJW_4 : ald_can.h
  • CAN_STATE_BUSY : ald_can.h
  • CAN_STATE_BUSY_RX0 : ald_can.h
  • CAN_STATE_BUSY_RX0_RX1 : ald_can.h
  • CAN_STATE_BUSY_RX1 : ald_can.h
  • CAN_STATE_BUSY_TX : ald_can.h
  • CAN_STATE_BUSY_TX_RX0 : ald_can.h
  • CAN_STATE_BUSY_TX_RX0_RX1 : ald_can.h
  • CAN_STATE_BUSY_TX_RX1 : ald_can.h
  • CAN_STATE_ERROR : ald_can.h
  • CAN_STATE_READY : ald_can.h
  • CAN_STATE_RESET : ald_can.h
  • CAN_STATE_TIMEOUT : ald_can.h
  • CAN_TX_MAILBOX_0 : ald_can.h
  • CAN_TX_MAILBOX_1 : ald_can.h
  • CAN_TX_MAILBOX_2 : ald_can.h
  • CAN_TX_MAILBOX_NONE : ald_can.h
  • CMU_BUZZ_DIV_128 : ald_cmu.h
  • CMU_BUZZ_DIV_16 : ald_cmu.h
  • CMU_BUZZ_DIV_2 : ald_cmu.h
  • CMU_BUZZ_DIV_256 : ald_cmu.h
  • CMU_BUZZ_DIV_32 : ald_cmu.h
  • CMU_BUZZ_DIV_4 : ald_cmu.h
  • CMU_BUZZ_DIV_64 : ald_cmu.h
  • CMU_BUZZ_DIV_8 : ald_cmu.h
  • CMU_CLOCK_HOSC : ald_cmu.h
  • CMU_CLOCK_HRC : ald_cmu.h
  • CMU_CLOCK_LOSC : ald_cmu.h
  • CMU_CLOCK_LRC : ald_cmu.h
  • CMU_CLOCK_PLL1 : ald_cmu.h
  • CMU_CLOCK_STATE_HOSCACT : ald_cmu.h
  • CMU_CLOCK_STATE_HOSCRDY : ald_cmu.h
  • CMU_CLOCK_STATE_HRCACT : ald_cmu.h
  • CMU_CLOCK_STATE_HRCRDY : ald_cmu.h
  • CMU_CLOCK_STATE_LOSCACT : ald_cmu.h
  • CMU_CLOCK_STATE_LOSCRDY : ald_cmu.h
  • CMU_CLOCK_STATE_LRCACT : ald_cmu.h
  • CMU_CLOCK_STATE_LRCRDY : ald_cmu.h
  • CMU_CLOCK_STATE_PLL1ACT : ald_cmu.h
  • CMU_CLOCK_STATE_PLL1RDY : ald_cmu.h
  • CMU_CLOCK_STATE_PLL2ACT : ald_cmu.h
  • CMU_CLOCK_STATE_PLL2RDY : ald_cmu.h
  • CMU_CLOCK_STATE_ULRCACT : ald_cmu.h
  • CMU_DIV_1 : ald_cmu.h
  • CMU_DIV_1024 : ald_cmu.h
  • CMU_DIV_128 : ald_cmu.h
  • CMU_DIV_16 : ald_cmu.h
  • CMU_DIV_2 : ald_cmu.h
  • CMU_DIV_2048 : ald_cmu.h
  • CMU_DIV_256 : ald_cmu.h
  • CMU_DIV_32 : ald_cmu.h
  • CMU_DIV_4 : ald_cmu.h
  • CMU_DIV_4096 : ald_cmu.h
  • CMU_DIV_512 : ald_cmu.h
  • CMU_DIV_64 : ald_cmu.h
  • CMU_DIV_8 : ald_cmu.h
  • CMU_HCLK_1 : ald_cmu.h
  • CMU_HCLK_2 : ald_cmu.h
  • CMU_HOSC_16M : ald_cmu.h
  • CMU_HOSC_24M : ald_cmu.h
  • CMU_HOSC_2M : ald_cmu.h
  • CMU_HOSC_4M : ald_cmu.h
  • CMU_HOSC_8M : ald_cmu.h
  • CMU_HOSC_START : ald_cmu.h
  • CMU_HOSC_STOP : ald_cmu.h
  • CMU_LCD_SEL_HOSC_1M : ald_cmu.h
  • CMU_LCD_SEL_HRC_1M : ald_cmu.h
  • CMU_LCD_SEL_LOSC : ald_cmu.h
  • CMU_LCD_SEL_LOSM : ald_cmu.h
  • CMU_LCD_SEL_LRC : ald_cmu.h
  • CMU_LCD_SEL_ULRC : ald_cmu.h
  • CMU_LOSC_START : ald_cmu.h
  • CMU_LOSC_STOP : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_HOSC : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_HOSC_1M : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_HOSM : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_HRC : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_HRC_1M : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_LOSC : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_LOSM : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_LRC : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_PCLK2 : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_PLL1 : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_PLL2 : ald_cmu.h
  • CMU_LP_PERH_CLOCK_SEL_ULRC : ald_cmu.h
  • CMU_OUTPUT_DIV_1 : ald_cmu.h
  • CMU_OUTPUT_DIV_128 : ald_cmu.h
  • CMU_OUTPUT_DIV_16 : ald_cmu.h
  • CMU_OUTPUT_DIV_2 : ald_cmu.h
  • CMU_OUTPUT_DIV_32 : ald_cmu.h
  • CMU_OUTPUT_DIV_4 : ald_cmu.h
  • CMU_OUTPUT_DIV_64 : ald_cmu.h
  • CMU_OUTPUT_DIV_8 : ald_cmu.h
  • CMU_OUTPUT_HIGH_SEL_HOSC : ald_cmu.h
  • CMU_OUTPUT_HIGH_SEL_HOSM : ald_cmu.h
  • CMU_OUTPUT_HIGH_SEL_HRC : ald_cmu.h
  • CMU_OUTPUT_HIGH_SEL_LOSC : ald_cmu.h
  • CMU_OUTPUT_HIGH_SEL_LRC : ald_cmu.h
  • CMU_OUTPUT_HIGH_SEL_PLL1 : ald_cmu.h
  • CMU_OUTPUT_HIGH_SEL_PLL2 : ald_cmu.h
  • CMU_OUTPUT_HIGH_SEL_SYSCLK : ald_cmu.h
  • CMU_OUTPUT_LOW_SEL_BUZZ : ald_cmu.h
  • CMU_OUTPUT_LOW_SEL_LOSC : ald_cmu.h
  • CMU_OUTPUT_LOW_SEL_LOSM : ald_cmu.h
  • CMU_OUTPUT_LOW_SEL_LRC : ald_cmu.h
  • CMU_OUTPUT_LOW_SEL_ULRC : ald_cmu.h
  • CMU_PCLK_1 : ald_cmu.h
  • CMU_PCLK_2 : ald_cmu.h
  • CMU_PERH_ACMP0 : ald_cmu.h
  • CMU_PERH_ACMP1 : ald_cmu.h
  • CMU_PERH_ACMP2 : ald_cmu.h
  • CMU_PERH_ADC0 : ald_cmu.h
  • CMU_PERH_ADC1 : ald_cmu.h
  • CMU_PERH_ALL : ald_cmu.h
  • CMU_PERH_BKPC : ald_cmu.h
  • CMU_PERH_CALC : ald_cmu.h
  • CMU_PERH_CAN : ald_cmu.h
  • CMU_PERH_CRC : ald_cmu.h
  • CMU_PERH_CRYPT : ald_cmu.h
  • CMU_PERH_DAC0 : ald_cmu.h
  • CMU_PERH_DBGC : ald_cmu.h
  • CMU_PERH_DMA : ald_cmu.h
  • CMU_PERH_EBI : ald_cmu.h
  • CMU_PERH_ECC : ald_cmu.h
  • CMU_PERH_GPIO : ald_cmu.h
  • CMU_PERH_I2C0 : ald_cmu.h
  • CMU_PERH_I2C1 : ald_cmu.h
  • CMU_PERH_IWDT : ald_cmu.h
  • CMU_PERH_LCD : ald_cmu.h
  • CMU_PERH_LPTIM0 : ald_cmu.h
  • CMU_PERH_LPUART0 : ald_cmu.h
  • CMU_PERH_OPAMP : ald_cmu.h
  • CMU_PERH_PIS : ald_cmu.h
  • CMU_PERH_QSPI_H : ald_cmu.h
  • CMU_PERH_QSPI_P : ald_cmu.h
  • CMU_PERH_RTC : ald_cmu.h
  • CMU_PERH_SPI0 : ald_cmu.h
  • CMU_PERH_SPI1 : ald_cmu.h
  • CMU_PERH_SPI2 : ald_cmu.h
  • CMU_PERH_TIMER0 : ald_cmu.h
  • CMU_PERH_TIMER1 : ald_cmu.h
  • CMU_PERH_TIMER2 : ald_cmu.h
  • CMU_PERH_TIMER3 : ald_cmu.h
  • CMU_PERH_TIMER4 : ald_cmu.h
  • CMU_PERH_TIMER5 : ald_cmu.h
  • CMU_PERH_TIMER6 : ald_cmu.h
  • CMU_PERH_TIMER7 : ald_cmu.h
  • CMU_PERH_TRNG : ald_cmu.h
  • CMU_PERH_TSENSE : ald_cmu.h
  • CMU_PERH_UART0 : ald_cmu.h
  • CMU_PERH_UART1 : ald_cmu.h
  • CMU_PERH_UART2 : ald_cmu.h
  • CMU_PERH_UART3 : ald_cmu.h
  • CMU_PERH_UART4 : ald_cmu.h
  • CMU_PERH_UART5 : ald_cmu.h
  • CMU_PERH_USB : ald_cmu.h
  • CMU_PERH_WWDT : ald_cmu.h
  • CMU_PLL1_INPUT_HOSC : ald_cmu.h
  • CMU_PLL1_INPUT_HOSC_2 : ald_cmu.h
  • CMU_PLL1_INPUT_HOSC_3 : ald_cmu.h
  • CMU_PLL1_INPUT_HOSC_4 : ald_cmu.h
  • CMU_PLL1_INPUT_HOSC_5 : ald_cmu.h
  • CMU_PLL1_INPUT_HOSC_6 : ald_cmu.h
  • CMU_PLL1_INPUT_HRC_6 : ald_cmu.h
  • CMU_PLL1_INPUT_PLL2 : ald_cmu.h
  • CMU_PLL1_OUTPUT_36M : ald_cmu.h
  • CMU_PLL1_OUTPUT_48M : ald_cmu.h
  • CMU_PLL1_UNLOCK : ald_cmu.h
  • CMU_QSPI_CLOCK_SEL_HCLK2 : ald_cmu.h
  • CMU_QSPI_CLOCK_SEL_HOSC : ald_cmu.h
  • CMU_QSPI_CLOCK_SEL_HOSM : ald_cmu.h
  • CMU_QSPI_CLOCK_SEL_HRC : ald_cmu.h
  • CMU_QSPI_CLOCK_SEL_PCLK1 : ald_cmu.h
  • CMU_QSPI_CLOCK_SEL_PLL1 : ald_cmu.h
  • CMU_SAFE_CLK_HOSC : ald_cmu.h
  • CMU_SAFE_CLK_LOSC : ald_cmu.h
  • CMU_SAFE_CLK_PLL : ald_cmu.h
  • CMU_STOP1_CLOCK_HOSC : ald_cmu.h
  • CMU_STOP1_CLOCK_HOSC_1M : ald_cmu.h
  • CMU_STOP1_CLOCK_HOSCM : ald_cmu.h
  • CMU_STOP1_CLOCK_HRC_1M : ald_cmu.h
  • CMU_STOP1_CLOCK_HRC_24M : ald_cmu.h
  • CMU_STOP1_CLOCK_HRC_2M : ald_cmu.h
  • CMU_STOP1_CLOCK_LRC : ald_cmu.h
  • CMU_SYS : ald_cmu.h
  • CMU_USB_CLOCK_SEL_HOSC : ald_cmu.h
  • CMU_USB_CLOCK_SEL_HOSM : ald_cmu.h
  • CMU_USB_CLOCK_SEL_HRC : ald_cmu.h
  • CMU_USB_CLOCK_SEL_PCLK1 : ald_cmu.h
  • CMU_USB_CLOCK_SEL_PLL1 : ald_cmu.h
  • CMU_USB_DIV_1 : ald_cmu.h
  • CMU_USB_DIV_1024 : ald_cmu.h
  • CMU_USB_DIV_128 : ald_cmu.h
  • CMU_USB_DIV_16 : ald_cmu.h
  • CMU_USB_DIV_2 : ald_cmu.h
  • CMU_USB_DIV_2048 : ald_cmu.h
  • CMU_USB_DIV_256 : ald_cmu.h
  • CMU_USB_DIV_32 : ald_cmu.h
  • CMU_USB_DIV_4 : ald_cmu.h
  • CMU_USB_DIV_4096 : ald_cmu.h
  • CMU_USB_DIV_512 : ald_cmu.h
  • CMU_USB_DIV_64 : ald_cmu.h
  • CMU_USB_DIV_8 : ald_cmu.h
  • CRC_DATASIZE_16 : ald_crc.h
  • CRC_DATASIZE_32 : ald_crc.h
  • CRC_DATASIZE_8 : ald_crc.h
  • CRC_LEN_AUTO : ald_crc.h
  • CRC_MODE_16 : ald_crc.h
  • CRC_MODE_32 : ald_crc.h
  • CRC_MODE_8 : ald_crc.h
  • CRC_MODE_CCITT : ald_crc.h
  • CRC_STATE_BUSY : ald_crc.h
  • CRC_STATE_ERROR : ald_crc.h
  • CRC_STATE_READY : ald_crc.h
  • CRC_STATE_RESET : ald_crc.h
  • CRC_WERR_ERR : ald_crc.h
  • CRC_WERR_NO : ald_crc.h
  • CRYPT_AES_BITS_128 : ald_crypt.h
  • CRYPT_AES_BITS_192 : ald_crypt.h
  • CRYPT_AES_BITS_256 : ald_crypt.h
  • CRYPT_BITS_128 : ald_crypt.h
  • CRYPT_BITS_192 : ald_crypt.h
  • CRYPT_BITS_256 : ald_crypt.h
  • CRYPT_CRYSEL_AES : ald_crypt.h
  • CRYPT_CRYSEL_DES : ald_crypt.h
  • CRYPT_DATA_CHANGE_1 : ald_crypt.h
  • CRYPT_DATA_CHANGE_16 : ald_crypt.h
  • CRYPT_DATA_CHANGE_8 : ald_crypt.h
  • CRYPT_DATA_CHANGE_NO : ald_crypt.h
  • CRYPT_DECRYPT : ald_crypt.h
  • CRYPT_DES_KEYS_1 : ald_crypt.h
  • CRYPT_DES_KEYS_2 : ald_crypt.h
  • CRYPT_DES_KEYS_3 : ald_crypt.h
  • CRYPT_ENCRYPT : ald_crypt.h
  • CRYPT_FLAG_AESIF : ald_crypt.h
  • CRYPT_FLAG_DESIF : ald_crypt.h
  • CRYPT_FLAG_DONE : ald_crypt.h
  • CRYPT_IT_IT : ald_crypt.h
  • CRYPT_KEYS_1 : ald_crypt.h
  • CRYPT_KEYS_2 : ald_crypt.h
  • CRYPT_KEYS_3 : ald_crypt.h
  • CRYPT_MODE_CBC : ald_crypt.h
  • CRYPT_MODE_CTR : ald_crypt.h
  • CRYPT_MODE_ECB : ald_crypt.h
  • CRYPT_STATE_BUSY : ald_crypt.h
  • CRYPT_STATE_ERROR : ald_crypt.h
  • CRYPT_STATE_READY : ald_crypt.h
  • CRYPT_STATE_RESET : ald_crypt.h


ALD User Manual: Globals

- d -

  • DAC_CH0_BSY : ald_dac.h
  • DAC_CH1_BSY : ald_dac.h
  • DAC_CHANNEL_0 : ald_dac.h
  • DAC_CHANNEL_1 : ald_dac.h
  • DAC_CHANNEL_COMB : ald_dac.h
  • DAC_CONV_MODE_CONTINUOUS : ald_dac.h
  • DAC_CONV_MODE_SAMPLEHOLD : ald_dac.h
  • DAC_CONV_MODE_SAMPLEOFF : ald_dac.h
  • DAC_FLAG_CH0 : ald_dac.h
  • DAC_FLAG_CH0_UF : ald_dac.h
  • DAC_FLAG_CH1 : ald_dac.h
  • DAC_FLAG_CH1_UF : ald_dac.h
  • DAC_IT_CH0 : ald_dac.h
  • DAC_IT_CH0_UF : ald_dac.h
  • DAC_IT_CH1 : ald_dac.h
  • DAC_IT_CH1_UF : ald_dac.h
  • DAC_NEG_REF_VREFN : ald_dac.h
  • DAC_NEG_REF_VSS : ald_dac.h
  • DAC_OUTPUT_ADC : ald_dac.h
  • DAC_OUTPUT_DISABLE : ald_dac.h
  • DAC_OUTPUT_PIN : ald_dac.h
  • DAC_OUTPUT_PIN_ADC : ald_dac.h
  • DAC_PIS_CH_0 : ald_dac.h
  • DAC_PIS_CH_1 : ald_dac.h
  • DAC_PIS_CH_10 : ald_dac.h
  • DAC_PIS_CH_11 : ald_dac.h
  • DAC_PIS_CH_2 : ald_dac.h
  • DAC_PIS_CH_3 : ald_dac.h
  • DAC_PIS_CH_4 : ald_dac.h
  • DAC_PIS_CH_5 : ald_dac.h
  • DAC_PIS_CH_6 : ald_dac.h
  • DAC_PIS_CH_7 : ald_dac.h
  • DAC_PIS_CH_8 : ald_dac.h
  • DAC_PIS_CH_9 : ald_dac.h
  • DAC_POS_REF_2V : ald_dac.h
  • DAC_POS_REF_VDD : ald_dac.h
  • DAC_POS_REF_VREEFP : ald_dac.h
  • DAC_POS_REF_VREEFP_BUF : ald_dac.h
  • DAC_PRES_DIV_1 : ald_dac.h
  • DAC_PRES_DIV_128 : ald_dac.h
  • DAC_PRES_DIV_16 : ald_dac.h
  • DAC_PRES_DIV_2 : ald_dac.h
  • DAC_PRES_DIV_32 : ald_dac.h
  • DAC_PRES_DIV_4 : ald_dac.h
  • DAC_PRES_DIV_64 : ald_dac.h
  • DAC_PRES_DIV_8 : ald_dac.h
  • DAC_REFRESH_16 : ald_dac.h
  • DAC_REFRESH_32 : ald_dac.h
  • DAC_REFRESH_64 : ald_dac.h
  • DAC_REFRESH_8 : ald_dac.h
  • DAC_TRIGGER_BY_DATA : ald_dac.h
  • DAC_TRIGGER_BY_PIS : ald_dac.h
  • DATA_16_BIT : ald_crypt.h
  • DATA_1_BIT : ald_crypt.h
  • DATA_32_BIT : ald_crypt.h
  • DATA_8_BIT : ald_crypt.h
  • DEBC_MODE_SLEEP : ald_dbgc.h
  • DEBC_MODE_STANDBY : ald_dbgc.h
  • DEBC_MODE_STOP1 : ald_dbgc.h
  • DEBC_MODE_STOP2 : ald_dbgc.h
  • DEBC_PERH_CAN : ald_dbgc.h
  • DEBC_PERH_I2C0 : ald_dbgc.h
  • DEBC_PERH_I2C1 : ald_dbgc.h
  • DEBC_PERH_IWDT : ald_dbgc.h
  • DEBC_PERH_LPTIM0 : ald_dbgc.h
  • DEBC_PERH_RTC : ald_dbgc.h
  • DEBC_PERH_TIMER0 : ald_dbgc.h
  • DEBC_PERH_TIMER1 : ald_dbgc.h
  • DEBC_PERH_TIMER2 : ald_dbgc.h
  • DEBC_PERH_TIMER3 : ald_dbgc.h
  • DEBC_PERH_TIMER4 : ald_dbgc.h
  • DEBC_PERH_TIMER5 : ald_dbgc.h
  • DEBC_PERH_TIMER6 : ald_dbgc.h
  • DEBC_PERH_TIMER7 : ald_dbgc.h
  • DEBC_PERH_WWDT : ald_dbgc.h
  • DISABLE : type.h
  • DMA_CYCLE_CTRL_AUTO : ald_dma.h
  • DMA_CYCLE_CTRL_BASIC : ald_dma.h
  • DMA_CYCLE_CTRL_MEM_SG_ALTERNATE : ald_dma.h
  • DMA_CYCLE_CTRL_MEM_SG_PRIMARY : ald_dma.h
  • DMA_CYCLE_CTRL_NONE : ald_dma.h
  • DMA_CYCLE_CTRL_PER_SG_ALTERNATE : ald_dma.h
  • DMA_CYCLE_CTRL_PER_SG_PRIMARY : ald_dma.h
  • DMA_CYCLE_CTRL_PINGPONG : ald_dma.h
  • DMA_DATA_INC_BYTE : ald_dma.h
  • DMA_DATA_INC_HALFWORD : ald_dma.h
  • DMA_DATA_INC_NONE : ald_dma.h
  • DMA_DATA_INC_WORD : ald_dma.h
  • DMA_DATA_SIZE_BYTE : ald_dma.h
  • DMA_DATA_SIZE_HALFWORD : ald_dma.h
  • DMA_DATA_SIZE_WORD : ald_dma.h
  • DMA_DESCP_CPLT_ALL : ald_dma.h
  • DMA_DESCP_CPLT_ALT : ald_dma.h
  • DMA_DESCP_CPLT_PRI : ald_dma.h
  • DMA_MSEL_ADC0 : ald_dma.h
  • DMA_MSEL_ADC1 : ald_dma.h
  • DMA_MSEL_CRC : ald_dma.h
  • DMA_MSEL_CRYPT : ald_dma.h
  • DMA_MSEL_DAC0 : ald_dma.h
  • DMA_MSEL_GPIO : ald_dma.h
  • DMA_MSEL_I2C0 : ald_dma.h
  • DMA_MSEL_I2C1 : ald_dma.h
  • DMA_MSEL_LPUART0 : ald_dma.h
  • DMA_MSEL_NONE : ald_dma.h
  • DMA_MSEL_PIS : ald_dma.h
  • DMA_MSEL_QSPI : ald_dma.h
  • DMA_MSEL_SPI0 : ald_dma.h
  • DMA_MSEL_SPI1 : ald_dma.h
  • DMA_MSEL_SPI2 : ald_dma.h
  • DMA_MSEL_TIMER0 : ald_dma.h
  • DMA_MSEL_TIMER1 : ald_dma.h
  • DMA_MSEL_TIMER2 : ald_dma.h
  • DMA_MSEL_TIMER3 : ald_dma.h
  • DMA_MSEL_TIMER4 : ald_dma.h
  • DMA_MSEL_TIMER5 : ald_dma.h
  • DMA_MSEL_TIMER6 : ald_dma.h
  • DMA_MSEL_TIMER7 : ald_dma.h
  • DMA_MSEL_TRNG : ald_dma.h
  • DMA_MSEL_UART0 : ald_dma.h
  • DMA_MSEL_UART1 : ald_dma.h
  • DMA_MSEL_UART2 : ald_dma.h
  • DMA_MSEL_UART3 : ald_dma.h
  • DMA_MSEL_UART4 : ald_dma.h
  • DMA_MSEL_UART5 : ald_dma.h
  • DMA_MSEL_USB : ald_dma.h
  • DMA_MSIGSEL_ADC : ald_dma.h
  • DMA_MSIGSEL_CRYPT_READ : ald_dma.h
  • DMA_MSIGSEL_CRYPT_WRITE : ald_dma.h
  • DMA_MSIGSEL_DAC0_CH0 : ald_dma.h
  • DMA_MSIGSEL_DAC0_CH1 : ald_dma.h
  • DMA_MSIGSEL_EP_RX1 : ald_dma.h
  • DMA_MSIGSEL_EP_RX2 : ald_dma.h
  • DMA_MSIGSEL_EP_RX3 : ald_dma.h
  • DMA_MSIGSEL_EP_RX4 : ald_dma.h
  • DMA_MSIGSEL_EP_RX5 : ald_dma.h
  • DMA_MSIGSEL_EP_TX1 : ald_dma.h
  • DMA_MSIGSEL_EP_TX2 : ald_dma.h
  • DMA_MSIGSEL_EP_TX3 : ald_dma.h
  • DMA_MSIGSEL_EP_TX4 : ald_dma.h
  • DMA_MSIGSEL_EP_TX5 : ald_dma.h
  • DMA_MSIGSEL_EXTI_0 : ald_dma.h
  • DMA_MSIGSEL_EXTI_1 : ald_dma.h
  • DMA_MSIGSEL_EXTI_10 : ald_dma.h
  • DMA_MSIGSEL_EXTI_11 : ald_dma.h
  • DMA_MSIGSEL_EXTI_12 : ald_dma.h
  • DMA_MSIGSEL_EXTI_13 : ald_dma.h
  • DMA_MSIGSEL_EXTI_14 : ald_dma.h
  • DMA_MSIGSEL_EXTI_15 : ald_dma.h
  • DMA_MSIGSEL_EXTI_2 : ald_dma.h
  • DMA_MSIGSEL_EXTI_3 : ald_dma.h
  • DMA_MSIGSEL_EXTI_4 : ald_dma.h
  • DMA_MSIGSEL_EXTI_5 : ald_dma.h
  • DMA_MSIGSEL_EXTI_6 : ald_dma.h
  • DMA_MSIGSEL_EXTI_7 : ald_dma.h
  • DMA_MSIGSEL_EXTI_8 : ald_dma.h
  • DMA_MSIGSEL_EXTI_9 : ald_dma.h
  • DMA_MSIGSEL_I2C_RNR : ald_dma.h
  • DMA_MSIGSEL_I2C_TXEMPTY : ald_dma.h
  • DMA_MSIGSEL_LPUART_RNR : ald_dma.h
  • DMA_MSIGSEL_LPUART_TXEMPTY : ald_dma.h
  • DMA_MSIGSEL_NONE : ald_dma.h
  • DMA_MSIGSEL_PIS_CH0 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH1 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH10 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH11 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH12 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH13 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH14 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH15 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH2 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH3 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH4 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH5 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH6 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH7 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH8 : ald_dma.h
  • DMA_MSIGSEL_PIS_CH9 : ald_dma.h
  • DMA_MSIGSEL_QSPI_READ : ald_dma.h
  • DMA_MSIGSEL_QSPI_WRITE : ald_dma.h
  • DMA_MSIGSEL_SPI_RNR : ald_dma.h
  • DMA_MSIGSEL_SPI_TXEMPTY : ald_dma.h
  • DMA_MSIGSEL_TIMER_CH1 : ald_dma.h
  • DMA_MSIGSEL_TIMER_CH2 : ald_dma.h
  • DMA_MSIGSEL_TIMER_CH3 : ald_dma.h
  • DMA_MSIGSEL_TIMER_CH4 : ald_dma.h
  • DMA_MSIGSEL_TIMER_COMP : ald_dma.h
  • DMA_MSIGSEL_TIMER_TRI : ald_dma.h
  • DMA_MSIGSEL_TIMER_UPDATE : ald_dma.h
  • DMA_MSIGSEL_UART45_RNR : ald_dma.h
  • DMA_MSIGSEL_UART45_TXEMPTY : ald_dma.h
  • DMA_MSIGSEL_UART_RNR : ald_dma.h
  • DMA_MSIGSEL_UART_TXEMPTY : ald_dma.h
  • DMA_R_POWER_1 : ald_dma.h
  • DMA_R_POWER_1024 : ald_dma.h
  • DMA_R_POWER_128 : ald_dma.h
  • DMA_R_POWER_16 : ald_dma.h
  • DMA_R_POWER_2 : ald_dma.h
  • DMA_R_POWER_256 : ald_dma.h
  • DMA_R_POWER_32 : ald_dma.h
  • DMA_R_POWER_4 : ald_dma.h
  • DMA_R_POWER_512 : ald_dma.h
  • DMA_R_POWER_64 : ald_dma.h
  • DMA_R_POWER_8 : ald_dma.h


ALD User Manual: Globals

- e -

  • EBI_ACCESS_MODE_A : ald_ebi.h
  • EBI_ACCESS_MODE_B : ald_ebi.h
  • EBI_ACCESS_MODE_C : ald_ebi.h
  • EBI_ACCESS_MODE_D : ald_ebi.h
  • EBI_ASYNCHRONOUS_WAIT_DISABLE : ald_ebi.h
  • EBI_ASYNCHRONOUS_WAIT_ENABLE : ald_ebi.h
  • EBI_BURST_ACCESS_MODE_DISABLE : ald_ebi.h
  • EBI_BURST_ACCESS_MODE_ENABLE : ald_ebi.h
  • EBI_DATA_ADDRESS_MUX_DISABLE : ald_ebi.h
  • EBI_DATA_ADDRESS_MUX_ENABLE : ald_ebi.h
  • EBI_EXTENDED_MODE_DISABLE : ald_ebi.h
  • EBI_EXTENDED_MODE_ENABLE : ald_ebi.h
  • EBI_FLAG_FALLING_EDGE : ald_ebi.h
  • EBI_FLAG_FEMPT : ald_ebi.h
  • EBI_FLAG_LEVEL : ald_ebi.h
  • EBI_FLAG_RISING_EDGE : ald_ebi.h
  • EBI_IT_FALLING_EDGE : ald_ebi.h
  • EBI_IT_LEVEL : ald_ebi.h
  • EBI_IT_RISING_EDGE : ald_ebi.h
  • EBI_LCD_DCLKPOL_FALLING : ald_ebi.h
  • EBI_LCD_DCLKPOL_RISING : ald_ebi.h
  • EBI_LCD_DENPOL_HIGH : ald_ebi.h
  • EBI_LCD_DENPOL_LOW : ald_ebi.h
  • EBI_LCD_HSYNCPOL_HIGH : ald_ebi.h
  • EBI_LCD_HSYNCPOL_LOW : ald_ebi.h
  • EBI_LCD_LCDEN_DISABLE : ald_ebi.h
  • EBI_LCD_LCDEN_ENABLE : ald_ebi.h
  • EBI_LCD_LCDINT_DISABLE : ald_ebi.h
  • EBI_LCD_LCDINT_ENABLE : ald_ebi.h
  • EBI_LCD_VSYNCPOL_HIGH : ald_ebi.h
  • EBI_LCD_VSYNCPOL_LOW : ald_ebi.h
  • EBI_MEMORY_TYPE_NOR : ald_ebi.h
  • EBI_MEMORY_TYPE_PSRAM : ald_ebi.h
  • EBI_MEMORY_TYPE_SRAM : ald_ebi.h
  • EBI_NAND_ECC_DISABLE : ald_ebi.h
  • EBI_NAND_ECC_ENABLE : ald_ebi.h
  • EBI_NAND_ECC_PAGE_SIZE_1024BYTE : ald_ebi.h
  • EBI_NAND_ECC_PAGE_SIZE_2048BYTE : ald_ebi.h
  • EBI_NAND_ECC_PAGE_SIZE_256BYTE : ald_ebi.h
  • EBI_NAND_ECC_PAGE_SIZE_4096BYTE : ald_ebi.h
  • EBI_NAND_ECC_PAGE_SIZE_512BYTE : ald_ebi.h
  • EBI_NAND_ECC_PAGE_SIZE_8192BYTE : ald_ebi.h
  • EBI_NAND_MEM_BUS_WIDTH_16 : ald_ebi.h
  • EBI_NAND_MEM_BUS_WIDTH_8 : ald_ebi.h
  • EBI_NAND_WAIT_FEATURE_DISABLE : ald_ebi.h
  • EBI_NAND_WAIT_FEATURE_ENABLE : ald_ebi.h
  • EBI_NORSRAM_BANK1 : ald_ebi.h
  • EBI_NORSRAM_BANK2 : ald_ebi.h
  • EBI_NORSRAM_BANK3 : ald_ebi.h
  • EBI_NORSRAM_BANK4 : ald_ebi.h
  • EBI_NORSRAM_FLASH_ACCESS_DISABLE : ald_ebi.h
  • EBI_NORSRAM_FLASH_ACCESS_ENABLE : ald_ebi.h
  • EBI_NORSRAM_MEM_BUS_WIDTH_16 : ald_ebi.h
  • EBI_NORSRAM_MEM_BUS_WIDTH_32 : ald_ebi.h
  • EBI_NORSRAM_MEM_BUS_WIDTH_8 : ald_ebi.h
  • EBI_PCTRLR_MEMORY_TYPE_NAND : ald_ebi.h
  • EBI_PCTRLR_MEMORY_TYPE_None : ald_ebi.h
  • EBI_WAIT_SIGNAL_DISABLE : ald_ebi.h
  • EBI_WAIT_SIGNAL_ENABLE : ald_ebi.h
  • EBI_WAIT_SIGNAL_POLARITY_HIGH : ald_ebi.h
  • EBI_WAIT_SIGNAL_POLARITY_LOW : ald_ebi.h
  • EBI_WAIT_TIMING_BEFORE_WS : ald_ebi.h
  • EBI_WAIT_TIMING_DURING_WS : ald_ebi.h
  • EBI_WRAP_MODE_DISABLE : ald_ebi.h
  • EBI_WRAP_MODE_ENABLE : ald_ebi.h
  • EBI_WRITE_BURST_DISABLE : ald_ebi.h
  • EBI_WRITE_BURST_ENABLE : ald_ebi.h
  • EBI_WRITE_OPERATION_DISABLE : ald_ebi.h
  • EBI_WRITE_OPERATION_ENABLE : ald_ebi.h
  • ENABLE : type.h
  • ERROR : utils.h
  • EXTI_FILTER_CLOCK_10K : ald_gpio.h
  • EXTI_FILTER_CLOCK_32K : ald_gpio.h
  • EXTI_TRIGGER_BOTH_EDGE : ald_gpio.h
  • EXTI_TRIGGER_RISING_EDGE : ald_gpio.h
  • EXTI_TRIGGER_TRAILING_EDGE : ald_gpio.h


ALD User Manual: Globals

- f -

  • FALSE : type.h
  • FLASH_CMD_AE : ald_flash.h
  • FLASH_CMD_DATAPE : ald_flash.h
  • FLASH_CMD_DATAWP : ald_flash.h
  • FLASH_CMD_DATAWP_FAST : ald_flash.h
  • FLASH_CMD_NP_AE : ald_flash.h
  • FLASH_CMD_PE : ald_flash.h
  • FLASH_CMD_WP : ald_flash.h
  • FLASH_CMD_WP_FAST : ald_flash.h


ALD User Manual: Globals

- g -

  • GPIO_FILTER_DISABLE : ald_gpio.h
  • GPIO_FILTER_ENABLE : ald_gpio.h
  • GPIO_FLOATING : ald_gpio.h
  • GPIO_FUNC_0 : ald_gpio.h
  • GPIO_FUNC_1 : ald_gpio.h
  • GPIO_FUNC_2 : ald_gpio.h
  • GPIO_FUNC_3 : ald_gpio.h
  • GPIO_FUNC_4 : ald_gpio.h
  • GPIO_FUNC_5 : ald_gpio.h
  • GPIO_FUNC_6 : ald_gpio.h
  • GPIO_FUNC_7 : ald_gpio.h
  • GPIO_MODE_CLOSE : ald_gpio.h
  • GPIO_MODE_INPUT : ald_gpio.h
  • GPIO_MODE_OUTPUT : ald_gpio.h
  • GPIO_OPEN_DRAIN : ald_gpio.h
  • GPIO_OPEN_SOURCE : ald_gpio.h
  • GPIO_OUT_DRIVE_0_1 : ald_gpio.h
  • GPIO_OUT_DRIVE_1 : ald_gpio.h
  • GPIO_OUT_DRIVE_20 : ald_gpio.h
  • GPIO_OUT_DRIVE_6 : ald_gpio.h
  • GPIO_PUSH_DOWN : ald_gpio.h
  • GPIO_PUSH_PULL : ald_gpio.h
  • GPIO_PUSH_UP : ald_gpio.h
  • GPIO_PUSH_UP_DOWN : ald_gpio.h
  • GPIO_TYPE_CMOS : ald_gpio.h
  • GPIO_TYPE_TTL : ald_gpio.h


ALD User Manual: Globals

- i -

  • I2C_ADDR_10BIT : ald_i2c.h
  • I2C_ADDR_7BIT : ald_i2c.h
  • I2C_CON1_ALERTEN : ald_i2c.h
  • I2C_CON1_GCEN : ald_i2c.h
  • I2C_CON1_NOSTRETCH : ald_i2c.h
  • I2C_CON1_PE : ald_i2c.h
  • I2C_CON1_PECEN : ald_i2c.h
  • I2C_CON1_RXDMA : ald_i2c.h
  • I2C_CON1_SBC : ald_i2c.h
  • I2C_CON1_SMBDEN : ald_i2c.h
  • I2C_CON1_SMBHEN : ald_i2c.h
  • I2C_CON1_TXDMA : ald_i2c.h
  • I2C_CON2_ADD10 : ald_i2c.h
  • I2C_CON2_AUTOEND : ald_i2c.h
  • I2C_CON2_HEAD10R : ald_i2c.h
  • I2C_CON2_HOLDACK : ald_i2c.h
  • I2C_CON2_NACK : ald_i2c.h
  • I2C_CON2_PECBYTE : ald_i2c.h
  • I2C_CON2_RD_WRN : ald_i2c.h
  • I2C_CON2_RELOAD : ald_i2c.h
  • I2C_CON2_START : ald_i2c.h
  • I2C_CON2_STOP : ald_i2c.h
  • I2C_DUALADDR_DISABLE : ald_i2c.h
  • I2C_DUALADDR_ENABLE : ald_i2c.h
  • I2C_ERROR_AF : ald_i2c.h
  • I2C_ERROR_ARLO : ald_i2c.h
  • I2C_ERROR_BERR : ald_i2c.h
  • I2C_ERROR_DMA : ald_i2c.h
  • I2C_ERROR_NONE : ald_i2c.h
  • I2C_ERROR_RF : ald_i2c.h
  • I2C_ERROR_ROV : ald_i2c.h
  • I2C_ERROR_RUD : ald_i2c.h
  • I2C_ERROR_TE : ald_i2c.h
  • I2C_ERROR_TIMEOUT : ald_i2c.h
  • I2C_ERROR_TOV : ald_i2c.h
  • I2C_ERROR_TUD : ald_i2c.h
  • I2C_EXTREME_FAST_MODE_MAX_CLK : ald_i2c.h
  • I2C_FAST_MODE_MAX_CLK : ald_i2c.h
  • I2C_GENERALCALL_DISABLE : ald_i2c.h
  • I2C_GENERALCALL_ENABLE : ald_i2c.h
  • I2C_IT_ADDR : ald_i2c.h
  • I2C_IT_ALERT : ald_i2c.h
  • I2C_IT_ARLO : ald_i2c.h
  • I2C_IT_BERR : ald_i2c.h
  • I2C_IT_NACK : ald_i2c.h
  • I2C_IT_PECE : ald_i2c.h
  • I2C_IT_RXF : ald_i2c.h
  • I2C_IT_RXOV : ald_i2c.h
  • I2C_IT_RXTH : ald_i2c.h
  • I2C_IT_RXUD : ald_i2c.h
  • I2C_IT_STOP : ald_i2c.h
  • I2C_IT_TC : ald_i2c.h
  • I2C_IT_TCR : ald_i2c.h
  • I2C_IT_TOUT : ald_i2c.h
  • I2C_IT_TXE : ald_i2c.h
  • I2C_IT_TXOV : ald_i2c.h
  • I2C_IT_TXTH : ald_i2c.h
  • I2C_IT_TXUD : ald_i2c.h
  • I2C_MEMADD_SIZE_16BIT : ald_i2c.h
  • I2C_MEMADD_SIZE_8BIT : ald_i2c.h
  • I2C_MODE_MASTER : ald_i2c.h
  • I2C_MODE_MEM : ald_i2c.h
  • I2C_MODE_NONE : ald_i2c.h
  • I2C_MODE_SLAVE : ald_i2c.h
  • I2C_MODULE_MASTER : ald_i2c.h
  • I2C_MODULE_SLAVE : ald_i2c.h
  • I2C_NOSTRETCH_DISABLE : ald_i2c.h
  • I2C_NOSTRETCH_ENABLE : ald_i2c.h
  • I2C_OA1EN : ald_i2c.h
  • I2C_OA1MODE : ald_i2c.h
  • I2C_OA2EN : ald_i2c.h
  • I2C_OAR2_ADD2 : ald_i2c.h
  • I2C_OAR2_ENDUAL : ald_i2c.h
  • I2C_STANDARD_MODE_MAX_CLK : ald_i2c.h
  • I2C_STAT_BUSY : ald_i2c.h
  • I2C_STAT_DIR : ald_i2c.h
  • I2C_STAT_RXE : ald_i2c.h
  • I2C_STAT_RXF : ald_i2c.h
  • I2C_STAT_RXOV : ald_i2c.h
  • I2C_STAT_RXTH : ald_i2c.h
  • I2C_STAT_RXUD : ald_i2c.h
  • I2C_STAT_TC : ald_i2c.h
  • I2C_STAT_TCR : ald_i2c.h
  • I2C_STAT_THTH : ald_i2c.h
  • I2C_STAT_TXE : ald_i2c.h
  • I2C_STAT_TXF : ald_i2c.h
  • I2C_STAT_TXOV : ald_i2c.h
  • I2C_STAT_TXUD : ald_i2c.h
  • I2C_STATE_BUSY : ald_i2c.h
  • I2C_STATE_BUSY_RX : ald_i2c.h
  • I2C_STATE_BUSY_TX : ald_i2c.h
  • I2C_STATE_ERROR : ald_i2c.h
  • I2C_STATE_READY : ald_i2c.h
  • I2C_STATE_RESET : ald_i2c.h
  • I2C_STATE_TIMEOUT : ald_i2c.h
  • I2C_TIMEOUTR_TIDLE : ald_i2c.h
  • I2C_TIMEOUTR_TIMEOUTEN : ald_i2c.h
  • I2C_TRISE_TRISE : ald_i2c.h
  • I2S_DMA_REQ_RX : ald_i2s.h
  • I2S_DMA_REQ_TX : ald_i2s.h
  • I2S_ERROR_DMA : ald_i2s.h
  • I2S_ERROR_FLAG : ald_i2s.h
  • I2S_ERROR_FRE : ald_i2s.h
  • I2S_ERROR_MODF : ald_i2s.h
  • I2S_ERROR_NONE : ald_i2s.h
  • I2S_ERROR_RXOV : ald_i2s.h
  • I2S_ERROR_TXOV : ald_i2s.h
  • I2S_FRAME_LONG : ald_i2s.h
  • I2S_FRAME_SHORT : ald_i2s.h
  • I2S_IF_FRE : ald_i2s.h
  • I2S_IF_RXF : ald_i2s.h
  • I2S_IF_RXOV : ald_i2s.h
  • I2S_IF_RXTH : ald_i2s.h
  • I2S_IF_RXUD : ald_i2s.h
  • I2S_IF_TXE : ald_i2s.h
  • I2S_IF_TXOV : ald_i2s.h
  • I2S_IF_TXUD : ald_i2s.h
  • I2S_INACTIVE_HIGH : ald_i2s.h
  • I2S_INACTIVE_LOW : ald_i2s.h
  • I2S_IT_CRCERR : ald_i2s.h
  • I2S_IT_FRE : ald_i2s.h
  • I2S_IT_MODF : ald_i2s.h
  • I2S_IT_RXF : ald_i2s.h
  • I2S_IT_RXOV : ald_i2s.h
  • I2S_IT_RXTH : ald_i2s.h
  • I2S_IT_RXUD : ald_i2s.h
  • I2S_IT_TXE : ald_i2s.h
  • I2S_IT_TXOV : ald_i2s.h
  • I2S_IT_TXUD : ald_i2s.h
  • I2S_LEN_16 : ald_i2s.h
  • I2S_LEN_24 : ald_i2s.h
  • I2S_LEN_32 : ald_i2s.h
  • I2S_MASTER_RECEIVE : ald_i2s.h
  • I2S_MASTER_TRANSMIT : ald_i2s.h
  • I2S_SIDE_LEFT : ald_i2s.h
  • I2S_SIDE_RIGHT : ald_i2s.h
  • I2S_SR_RXNE : ald_i2s.h
  • I2S_SR_TXE : ald_i2s.h
  • I2S_SR_TXE_RXNE : ald_i2s.h
  • I2S_STATE_BUSY : ald_i2s.h
  • I2S_STATE_BUSY_RX : ald_i2s.h
  • I2S_STATE_BUSY_TX : ald_i2s.h
  • I2S_STATE_BUSY_TX_RX : ald_i2s.h
  • I2S_STATE_ERROR : ald_i2s.h
  • I2S_STATE_READY : ald_i2s.h
  • I2S_STATE_RESET : ald_i2s.h
  • I2S_STATE_TIMEOUT : ald_i2s.h
  • I2S_STATUS_BUSY : ald_i2s.h
  • I2S_STATUS_CHSIDE : ald_i2s.h
  • I2S_STATUS_RXE : ald_i2s.h
  • I2S_STATUS_RXF : ald_i2s.h
  • I2S_STATUS_RXOV : ald_i2s.h
  • I2S_STATUS_RXUD : ald_i2s.h
  • I2S_STATUS_TXE : ald_i2s.h
  • I2S_STATUS_TXF : ald_i2s.h
  • I2S_STATUS_TXOV : ald_i2s.h
  • I2S_STATUS_TXUD : ald_i2s.h
  • I2S_STD_LSB : ald_i2s.h
  • I2S_STD_MSB : ald_i2s.h
  • I2S_STD_PCM : ald_i2s.h
  • I2S_STD_PHI : ald_i2s.h
  • I2S_WIDE_16 : ald_i2s.h
  • I2S_WIDE_32 : ald_i2s.h
  • IV_2_LEN : ald_crypt.h
  • IV_4_LEN : ald_crypt.h


ALD User Manual: Globals

- k -

  • KEY_2_LEN : ald_crypt.h
  • KEY_4_LEN : ald_crypt.h
  • KEY_6_LEN : ald_crypt.h
  • KEY_8_LEN : ald_crypt.h


ALD User Manual: Globals

- l -

  • LIN_BREAK_LEN_10B : ald_uart.h
  • LIN_BREAK_LEN_11B : ald_uart.h
  • LOCK : type.h


ALD User Manual: Globals

- n -

  • NVIC_PRIORITY_GROUP_0 : utils.h
  • NVIC_PRIORITY_GROUP_1 : utils.h
  • NVIC_PRIORITY_GROUP_2 : utils.h
  • NVIC_PRIORITY_GROUP_3 : utils.h
  • NVIC_PRIORITY_GROUP_4 : utils.h


ALD User Manual: Globals

- o -

  • OK : utils.h
  • OP_FLASH : ald_flash.h
  • OP_INFO : ald_flash.h


ALD User Manual: Globals

- p -

  • PIS_ACMP_OUT0 : ald_pis.h
  • PIS_ACMP_OUT1 : ald_pis.h
  • PIS_ADC0_INSERT : ald_pis.h
  • PIS_ADC0_NORMAL : ald_pis.h
  • PIS_ADC0_RESERVE : ald_pis.h
  • PIS_ADC1_INSERT : ald_pis.h
  • PIS_ADC1_NORMAL : ald_pis.h
  • PIS_ADC1_RESERVE : ald_pis.h
  • PIS_CH0_ADC1_NORMAL : ald_pis.h
  • PIS_CH0_LPTIM0_EXT0 : ald_pis.h
  • PIS_CH0_TIMER0_BRKIN : ald_pis.h
  • PIS_CH0_TIMER0_CH1IN : ald_pis.h
  • PIS_CH0_TIMER1_BRKIN : ald_pis.h
  • PIS_CH10_UART1_RXD : ald_pis.h
  • PIS_CH11_UART2_RXD : ald_pis.h
  • PIS_CH12_TIMER0_ITR0 : ald_pis.h
  • PIS_CH12_TIMER1_ITR0 : ald_pis.h
  • PIS_CH12_TIMER2_ITR0 : ald_pis.h
  • PIS_CH12_TIMER3_ITR0 : ald_pis.h
  • PIS_CH12_UART3_RXD : ald_pis.h
  • PIS_CH13_TIMER0_ITR1 : ald_pis.h
  • PIS_CH13_TIMER1_ITR1 : ald_pis.h
  • PIS_CH13_TIMER2_ITR1 : ald_pis.h
  • PIS_CH13_TIMER3_ITR1 : ald_pis.h
  • PIS_CH13_UART4_RXD : ald_pis.h
  • PIS_CH14_TIMER0_ITR2 : ald_pis.h
  • PIS_CH14_TIMER1_ITR2 : ald_pis.h
  • PIS_CH14_TIMER2_ITR2 : ald_pis.h
  • PIS_CH14_TIMER3_ITR2 : ald_pis.h
  • PIS_CH14_UART5_RXD : ald_pis.h
  • PIS_CH15_LPUART0_RXD : ald_pis.h
  • PIS_CH15_TIMER0_ITR3 : ald_pis.h
  • PIS_CH15_TIMER1_ITR3 : ald_pis.h
  • PIS_CH15_TIMER2_ITR3 : ald_pis.h
  • PIS_CH15_TIMER3_ITR3 : ald_pis.h
  • PIS_CH1_ADC1_INSERT : ald_pis.h
  • PIS_CH1_LPTIM0_EXT1 : ald_pis.h
  • PIS_CH1_TIMER1_CH1IN : ald_pis.h
  • PIS_CH2_LPTIM0_EXT2 : ald_pis.h
  • PIS_CH2_TIMER0_CH2IN : ald_pis.h
  • PIS_CH2_TIMER1_CH2IN : ald_pis.h
  • PIS_CH3_LPTIM0_EXT3 : ald_pis.h
  • PIS_CH3_TIMER0_CH3IN : ald_pis.h
  • PIS_CH3_TIMER1_CH3IN : ald_pis.h
  • PIS_CH4_LPTIM0_EXT4 : ald_pis.h
  • PIS_CH4_TIMER0_CH4IN : ald_pis.h
  • PIS_CH4_TIMER1_CH4IN : ald_pis.h
  • PIS_CH5_LPTIM0_EXT5 : ald_pis.h
  • PIS_CH5_SPI0_RX : ald_pis.h
  • PIS_CH5_TIMER2_CH1IN : ald_pis.h
  • PIS_CH5_TIMER3_CH1IN : ald_pis.h
  • PIS_CH6_ADC0_NORMAL : ald_pis.h
  • PIS_CH6_LPTIM0_EXT6 : ald_pis.h
  • PIS_CH6_SPI0_CLK : ald_pis.h
  • PIS_CH6_TIMER2_CH2IN : ald_pis.h
  • PIS_CH6_TIMER3_CH2IN : ald_pis.h
  • PIS_CH7_ADC0_INSERT : ald_pis.h
  • PIS_CH7_DMA_REQUEST : ald_pis.h
  • PIS_CH7_LPTIM0_EXT7 : ald_pis.h
  • PIS_CH7_SPI1_RX : ald_pis.h
  • PIS_CH7_TIMER2_CH3IN : ald_pis.h
  • PIS_CH7_TIMER3_CH3IN : ald_pis.h
  • PIS_CH8_SPI1_CLK : ald_pis.h
  • PIS_CH8_TIMER2_CH4IN : ald_pis.h
  • PIS_CH8_TIMER3_CH4IN : ald_pis.h
  • PIS_CH9_UART0_RXD : ald_pis.h
  • PIS_CH_0 : ald_pis.h
  • PIS_CH_1 : ald_pis.h
  • PIS_CH_10 : ald_pis.h
  • PIS_CH_11 : ald_pis.h
  • PIS_CH_12 : ald_pis.h
  • PIS_CH_13 : ald_pis.h
  • PIS_CH_14 : ald_pis.h
  • PIS_CH_15 : ald_pis.h
  • PIS_CH_2 : ald_pis.h
  • PIS_CH_3 : ald_pis.h
  • PIS_CH_4 : ald_pis.h
  • PIS_CH_5 : ald_pis.h
  • PIS_CH_6 : ald_pis.h
  • PIS_CH_7 : ald_pis.h
  • PIS_CH_8 : ald_pis.h
  • PIS_CH_9 : ald_pis.h
  • PIS_CHAN_INPUT : ald_pis.h
  • PIS_CLK_PCLK1 : ald_pis.h
  • PIS_CLK_PCLK2 : ald_pis.h
  • PIS_CLK_RESERVE : ald_pis.h
  • PIS_CLK_SYS : ald_pis.h
  • PIS_CON_0 : ald_pis.h
  • PIS_CON_1 : ald_pis.h
  • PIS_CON_NONE : ald_pis.h
  • PIS_DAC0_CH0 : ald_pis.h
  • PIS_DAC0_CH1 : ald_pis.h
  • PIS_DMA : ald_pis.h
  • PIS_EDGE_DOWN : ald_pis.h
  • PIS_EDGE_NONE : ald_pis.h
  • PIS_EDGE_UP : ald_pis.h
  • PIS_EDGE_UP_DOWN : ald_pis.h
  • PIS_GPIO_PIN0 : ald_pis.h
  • PIS_GPIO_PIN1 : ald_pis.h
  • PIS_GPIO_PIN10 : ald_pis.h
  • PIS_GPIO_PIN11 : ald_pis.h
  • PIS_GPIO_PIN12 : ald_pis.h
  • PIS_GPIO_PIN13 : ald_pis.h
  • PIS_GPIO_PIN14 : ald_pis.h
  • PIS_GPIO_PIN15 : ald_pis.h
  • PIS_GPIO_PIN2 : ald_pis.h
  • PIS_GPIO_PIN3 : ald_pis.h
  • PIS_GPIO_PIN4 : ald_pis.h
  • PIS_GPIO_PIN5 : ald_pis.h
  • PIS_GPIO_PIN6 : ald_pis.h
  • PIS_GPIO_PIN7 : ald_pis.h
  • PIS_GPIO_PIN8 : ald_pis.h
  • PIS_GPIO_PIN9 : ald_pis.h
  • PIS_HIGH_LEVEL : ald_pis.h
  • PIS_I2C0_RECV : ald_pis.h
  • PIS_I2C0_SEND : ald_pis.h
  • PIS_I2C1_RECV : ald_pis.h
  • PIS_I2C1_SEND : ald_pis.h
  • PIS_LOW_LEVEL : ald_pis.h
  • PIS_LPTIMER0_ASY_UPDATA : ald_pis.h
  • PIS_LPTIMER0_SYN_UPDATA : ald_pis.h
  • PIS_LPUART0_ASY_RECV : ald_pis.h
  • PIS_LPUART0_ASY_SEND : ald_pis.h
  • PIS_LPUART0_SYN_RECV : ald_pis.h
  • PIS_LPUART0_SYN_SEND : ald_pis.h
  • PIS_LPUART0_TX : ald_pis.h
  • PIS_LVD : ald_pis.h
  • PIS_NON : ald_pis.h
  • PIS_NONE_INPUT : ald_pis.h
  • PIS_OUT_CH_0 : ald_pis.h
  • PIS_OUT_CH_1 : ald_pis.h
  • PIS_OUT_CH_2 : ald_pis.h
  • PIS_OUT_CH_3 : ald_pis.h
  • PIS_OUT_LEVEL : ald_pis.h
  • PIS_OUT_PULSE : ald_pis.h
  • PIS_PORT_INPUT : ald_pis.h
  • PIS_RTC_ALARM : ald_pis.h
  • PIS_RTC_CLOCK : ald_pis.h
  • PIS_SPI0_NE : ald_pis.h
  • PIS_SPI0_RECV : ald_pis.h
  • PIS_SPI0_SEND : ald_pis.h
  • PIS_SPI1_NE : ald_pis.h
  • PIS_SPI1_RECV : ald_pis.h
  • PIS_SPI1_SEND : ald_pis.h
  • PIS_SRC_BUZ : ald_pis.h
  • PIS_SRC_LPTIM0 : ald_pis.h
  • PIS_SRC_NONE : ald_pis.h
  • PIS_SRC_TIMER0 : ald_pis.h
  • PIS_SRC_TIMER1 : ald_pis.h
  • PIS_SRC_TIMER2 : ald_pis.h
  • PIS_SRC_TIMER3 : ald_pis.h
  • PIS_SRC_TIMER6 : ald_pis.h
  • PIS_SRC_TIMER7 : ald_pis.h
  • PIS_STATE_BUSY : ald_pis.h
  • PIS_STATE_ERROR : ald_pis.h
  • PIS_STATE_READY : ald_pis.h
  • PIS_STATE_RESET : ald_pis.h
  • PIS_STATE_TIMEOUT : ald_pis.h
  • PIS_SYN_DIRECT : ald_pis.h
  • PIS_SYN_LEVEL_ASY_AHB : ald_pis.h
  • PIS_SYN_LEVEL_ASY_APB1 : ald_pis.h
  • PIS_SYN_LEVEL_ASY_APB2 : ald_pis.h
  • PIS_SYN_PULSE_ASY_AHB : ald_pis.h
  • PIS_SYN_PULSE_ASY_APB1 : ald_pis.h
  • PIS_SYN_PULSE_ASY_APB2 : ald_pis.h
  • PIS_TIMER0_INPUT_1 : ald_pis.h
  • PIS_TIMER0_INPUT_2 : ald_pis.h
  • PIS_TIMER0_INPUT_3 : ald_pis.h
  • PIS_TIMER0_INPUT_4 : ald_pis.h
  • PIS_TIMER0_OUTPUT_1 : ald_pis.h
  • PIS_TIMER0_OUTPUT_2 : ald_pis.h
  • PIS_TIMER0_OUTPUT_3 : ald_pis.h
  • PIS_TIMER0_OUTPUT_4 : ald_pis.h
  • PIS_TIMER0_TRIG : ald_pis.h
  • PIS_TIMER0_UPDATA : ald_pis.h
  • PIS_TIMER1_INPUT_1 : ald_pis.h
  • PIS_TIMER1_INPUT_2 : ald_pis.h
  • PIS_TIMER1_INPUT_3 : ald_pis.h
  • PIS_TIMER1_INPUT_4 : ald_pis.h
  • PIS_TIMER1_OUTPUT_1 : ald_pis.h
  • PIS_TIMER1_OUTPUT_2 : ald_pis.h
  • PIS_TIMER1_OUTPUT_3 : ald_pis.h
  • PIS_TIMER1_OUTPUT_4 : ald_pis.h
  • PIS_TIMER1_TRIG : ald_pis.h
  • PIS_TIMER1_UPDATA : ald_pis.h
  • PIS_TIMER2_INPUT_1 : ald_pis.h
  • PIS_TIMER2_INPUT_2 : ald_pis.h
  • PIS_TIMER2_INPUT_3 : ald_pis.h
  • PIS_TIMER2_INPUT_4 : ald_pis.h
  • PIS_TIMER2_OUTPUT_1 : ald_pis.h
  • PIS_TIMER2_OUTPUT_2 : ald_pis.h
  • PIS_TIMER2_OUTPUT_3 : ald_pis.h
  • PIS_TIMER2_OUTPUT_4 : ald_pis.h
  • PIS_TIMER2_TRIG : ald_pis.h
  • PIS_TIMER2_UPDATA : ald_pis.h
  • PIS_TIMER3_INPUT_1 : ald_pis.h
  • PIS_TIMER3_INPUT_2 : ald_pis.h
  • PIS_TIMER3_INPUT_3 : ald_pis.h
  • PIS_TIMER3_INPUT_4 : ald_pis.h
  • PIS_TIMER3_OUTPUT_1 : ald_pis.h
  • PIS_TIMER3_OUTPUT_2 : ald_pis.h
  • PIS_TIMER3_OUTPUT_3 : ald_pis.h
  • PIS_TIMER3_OUTPUT_4 : ald_pis.h
  • PIS_TIMER3_TRIG : ald_pis.h
  • PIS_TIMER3_UPDATA : ald_pis.h
  • PIS_TIMER_CH1 : ald_pis.h
  • PIS_TIMER_CH2 : ald_pis.h
  • PIS_TIMER_CH3 : ald_pis.h
  • PIS_TIMER_CH4 : ald_pis.h
  • PIS_TRIG_RESERVE : ald_pis.h
  • PIS_UART0_IRDAOUT : ald_pis.h
  • PIS_UART0_RESERVE0 : ald_pis.h
  • PIS_UART0_RESERVE1 : ald_pis.h
  • PIS_UART0_RTSOUT : ald_pis.h
  • PIS_UART0_SYN_RECV : ald_pis.h
  • PIS_UART0_SYN_SEND : ald_pis.h
  • PIS_UART0_TX : ald_pis.h
  • PIS_UART0_TXOUT : ald_pis.h
  • PIS_UART1_IRDA : ald_pis.h
  • PIS_UART1_RESERVE0 : ald_pis.h
  • PIS_UART1_RESERVE1 : ald_pis.h
  • PIS_UART1_RTS : ald_pis.h
  • PIS_UART1_SYN_RECV : ald_pis.h
  • PIS_UART1_SYN_SEND : ald_pis.h
  • PIS_UART1_TX : ald_pis.h
  • PIS_UART1_TXOUT : ald_pis.h
  • PIS_UART2_IRDA : ald_pis.h
  • PIS_UART2_RESERVE0 : ald_pis.h
  • PIS_UART2_RESERVE1 : ald_pis.h
  • PIS_UART2_RTS : ald_pis.h
  • PIS_UART2_SYN_RECV : ald_pis.h
  • PIS_UART2_SYN_SEND : ald_pis.h
  • PIS_UART2_TX : ald_pis.h
  • PIS_UART2_TXOUT : ald_pis.h
  • PIS_UART3_IRDA : ald_pis.h
  • PIS_UART3_RESERVE0 : ald_pis.h
  • PIS_UART3_RESERVE1 : ald_pis.h
  • PIS_UART3_RTS : ald_pis.h
  • PIS_UART3_SYN_RECV : ald_pis.h
  • PIS_UART3_SYN_SEND : ald_pis.h
  • PIS_UART3_TX : ald_pis.h
  • PIS_UART3_TXOUT : ald_pis.h
  • PIS_UART4_RECV : ald_pis.h
  • PIS_UART4_SEND : ald_pis.h
  • PIS_UART4_TXOUT : ald_pis.h
  • PIS_UART5_RECV : ald_pis.h
  • PIS_UART5_SEND : ald_pis.h
  • PIS_UART5_TXOUT : ald_pis.h
  • PMU_LDO_18_DRV_HIGH : ald_pmu.h
  • PMU_LDO_18_DRV_LOW : ald_pmu.h
  • PMU_LDO_18_HOLD : ald_pmu.h
  • PMU_LDO_18_OFF : ald_pmu.h
  • PMU_LDO_LPMODE_OUTPUT_0_9 : ald_pmu.h
  • PMU_LDO_LPMODE_OUTPUT_1_0 : ald_pmu.h
  • PMU_LDO_LPMODE_OUTPUT_1_1 : ald_pmu.h
  • PMU_LDO_LPMODE_OUTPUT_1_2 : ald_pmu.h
  • PMU_LP_STANDBY : ald_pmu.h
  • PMU_LP_STOP1 : ald_pmu.h
  • PMU_LP_STOP2 : ald_pmu.h
  • PMU_LVD_TRIGGER_FALLING_EDGE : ald_pmu.h
  • PMU_LVD_TRIGGER_HIGH_LEVEL : ald_pmu.h
  • PMU_LVD_TRIGGER_LOW_LEVEL : ald_pmu.h
  • PMU_LVD_TRIGGER_RISING_EDGE : ald_pmu.h
  • PMU_LVD_TRIGGER_RISING_FALLING : ald_pmu.h
  • PMU_LVD_VOL_SEL_2_2 : ald_pmu.h
  • PMU_LVD_VOL_SEL_2_4 : ald_pmu.h
  • PMU_LVD_VOL_SEL_2_6 : ald_pmu.h
  • PMU_LVD_VOL_SEL_2_8 : ald_pmu.h
  • PMU_LVD_VOL_SEL_3_0 : ald_pmu.h
  • PMU_LVD_VOL_SEL_3_2 : ald_pmu.h
  • PMU_LVD_VOL_SEL_3_4 : ald_pmu.h
  • PMU_LVD_VOL_SEL_3_6 : ald_pmu.h
  • PMU_LVD_VOL_SEL_3_8 : ald_pmu.h
  • PMU_LVD_VOL_SEL_4_0 : ald_pmu.h
  • PMU_LVD_VOL_SEL_4_2 : ald_pmu.h
  • PMU_LVD_VOL_SEL_4_4 : ald_pmu.h
  • PMU_LVD_VOL_SEL_4_6 : ald_pmu.h
  • PMU_LVD_VOL_SEL_4_8 : ald_pmu.h
  • PMU_LVD_VOL_SEL_EXT : ald_pmu.h
  • PMU_POWER_CAN : ald_pmu.h
  • PMU_POWER_QSPI : ald_pmu.h
  • PMU_POWER_ROM : ald_pmu.h
  • PMU_POWER_SRAM0 : ald_pmu.h
  • PMU_POWER_SRAM1 : ald_pmu.h
  • PMU_POWER_SRAM2 : ald_pmu.h
  • PMU_POWER_SRAM3 : ald_pmu.h
  • PMU_POWER_SRAM4 : ald_pmu.h
  • PMU_POWER_SRAM5 : ald_pmu.h
  • PMU_POWER_USB : ald_pmu.h
  • PMU_SR_RSTAT : ald_pmu.h
  • PMU_SR_STANDBYF : ald_pmu.h
  • PMU_SR_USBRDY : ald_pmu.h
  • PMU_SR_WUF : ald_pmu.h
  • PMU_STANDBY_LEVEL_HIGH : ald_bkpc.h
  • PMU_STANDBY_LEVEL_LOW : ald_bkpc.h
  • PMU_STANDBY_PORT_SEL_NONE : ald_bkpc.h
  • PMU_STANDBY_PORT_SEL_PA0 : ald_bkpc.h
  • PMU_STANDBY_PORT_SEL_PA1 : ald_bkpc.h
  • PMU_STANDBY_PORT_SEL_PA2 : ald_bkpc.h
  • PMU_STANDBY_PORT_SEL_PA3 : ald_bkpc.h
  • PMU_STANDBY_PORT_SEL_PA4 : ald_bkpc.h
  • PMU_STANDBY_PORT_SEL_PA5 : ald_bkpc.h
  • PMU_STANDBY_PORT_SEL_PA6 : ald_bkpc.h
  • PMU_STANDBY_PORT_SEL_PA7 : ald_bkpc.h


ALD User Manual: Globals

- q -

  • QSPI_CPHA_1E : ald_qspi.h
  • QSPI_CPHA_2E : ald_qspi.h
  • QSPI_CPOL_H : ald_qspi.h
  • QSPI_CPOL_L : ald_qspi.h
  • QSPI_CS_NSS0 : ald_qspi.h
  • QSPI_CS_NSS1 : ald_qspi.h
  • QSPI_CS_NSS2 : ald_qspi.h
  • QSPI_CS_NSS3 : ald_qspi.h
  • QSPI_DIV_10 : ald_qspi.h
  • QSPI_DIV_12 : ald_qspi.h
  • QSPI_DIV_14 : ald_qspi.h
  • QSPI_DIV_16 : ald_qspi.h
  • QSPI_DIV_18 : ald_qspi.h
  • QSPI_DIV_2 : ald_qspi.h
  • QSPI_DIV_20 : ald_qspi.h
  • QSPI_DIV_22 : ald_qspi.h
  • QSPI_DIV_24 : ald_qspi.h
  • QSPI_DIV_26 : ald_qspi.h
  • QSPI_DIV_28 : ald_qspi.h
  • QSPI_DIV_30 : ald_qspi.h
  • QSPI_DIV_32 : ald_qspi.h
  • QSPI_DIV_4 : ald_qspi.h
  • QSPI_DIV_6 : ald_qspi.h
  • QSPI_DIV_8 : ald_qspi.h
  • QSPI_FALLING_E : ald_qspi.h
  • QSPI_IF_AHBAEF : ald_qspi.h
  • QSPI_IF_INDCF : ald_qspi.h
  • QSPI_IF_INDRRF : ald_qspi.h
  • QSPI_IF_INDRSFF : ald_qspi.h
  • QSPI_IF_INDTWF : ald_qspi.h
  • QSPI_IF_MODFF : ald_qspi.h
  • QSPI_IF_POLLF : ald_qspi.h
  • QSPI_IF_ROVF : ald_qspi.h
  • QSPI_IF_SRFFF : ald_qspi.h
  • QSPI_IF_SRFNEF : ald_qspi.h
  • QSPI_IF_STFFF : ald_qspi.h
  • QSPI_IF_STFNFF : ald_qspi.h
  • QSPI_IF_UDFF : ald_qspi.h
  • QSPI_IF_WPAF : ald_qspi.h
  • QSPI_INDRD_PROGRESS : ald_qspi.h
  • QSPI_INDWR_CPLT : ald_qspi.h
  • QSPI_INDWR_PROGRESS : ald_qspi.h
  • QSPI_IT_AHBAEF : ald_qspi.h
  • QSPI_IT_INDCF : ald_qspi.h
  • QSPI_IT_INDRRF : ald_qspi.h
  • QSPI_IT_INDRSFF : ald_qspi.h
  • QSPI_IT_INDTWF : ald_qspi.h
  • QSPI_IT_MODFF : ald_qspi.h
  • QSPI_IT_POLLF : ald_qspi.h
  • QSPI_IT_ROVF : ald_qspi.h
  • QSPI_IT_SRFFF : ald_qspi.h
  • QSPI_IT_SRFNEF : ald_qspi.h
  • QSPI_IT_STFFF : ald_qspi.h
  • QSPI_IT_STFNFF : ald_qspi.h
  • QSPI_IT_UDFF : ald_qspi.h
  • QSPI_IT_WPAF : ald_qspi.h
  • QSPI_MULTI_CHIP : ald_qspi.h
  • QSPI_NSS_1G : ald_qspi.h
  • QSPI_NSS_2G : ald_qspi.h
  • QSPI_NSS_4G : ald_qspi.h
  • QSPI_NSS_512M : ald_qspi.h
  • QSPI_RD_CPLT : ald_qspi.h
  • QSPI_RISING_E : ald_qspi.h
  • QSPI_SINGLE_CHIP : ald_qspi.h
  • QSPI_SRAM_RD : ald_qspi.h
  • QSPI_SRAM_WR : ald_qspi.h
  • QSPI_STATE_BUSY_RX : ald_qspi.h
  • QSPI_STATE_BUSY_TX : ald_qspi.h
  • QSPI_XFER_DUAL : ald_qspi.h
  • QSPI_XFER_QUAD : ald_qspi.h
  • QSPI_XFER_SINGLE : ald_qspi.h


ALD User Manual: Globals

- r -

  • RESET : type.h
  • RMU_BORFLT_1 : ald_rmu.h
  • RMU_BORFLT_2 : ald_rmu.h
  • RMU_BORFLT_3 : ald_rmu.h
  • RMU_BORFLT_4 : ald_rmu.h
  • RMU_BORFLT_5 : ald_rmu.h
  • RMU_BORFLT_6 : ald_rmu.h
  • RMU_BORFLT_7 : ald_rmu.h
  • RMU_PERH_ACMP0 : ald_rmu.h
  • RMU_PERH_ACMP1 : ald_rmu.h
  • RMU_PERH_ACMP2 : ald_rmu.h
  • RMU_PERH_ADC0 : ald_rmu.h
  • RMU_PERH_ADC1 : ald_rmu.h
  • RMU_PERH_BKPC : ald_rmu.h
  • RMU_PERH_BKPRAM : ald_rmu.h
  • RMU_PERH_CALC : ald_rmu.h
  • RMU_PERH_CAN0 : ald_rmu.h
  • RMU_PERH_CHIP : ald_rmu.h
  • RMU_PERH_CPU : ald_rmu.h
  • RMU_PERH_CRC : ald_rmu.h
  • RMU_PERH_CRYPT : ald_rmu.h
  • RMU_PERH_DAC0 : ald_rmu.h
  • RMU_PERH_EBI : ald_rmu.h
  • RMU_PERH_ECC : ald_rmu.h
  • RMU_PERH_GPIO : ald_rmu.h
  • RMU_PERH_I2C0 : ald_rmu.h
  • RMU_PERH_I2C1 : ald_rmu.h
  • RMU_PERH_IWDT : ald_rmu.h
  • RMU_PERH_LCD : ald_rmu.h
  • RMU_PERH_LPTIM0 : ald_rmu.h
  • RMU_PERH_LPUART0 : ald_rmu.h
  • RMU_PERH_OPAMP : ald_rmu.h
  • RMU_PERH_PIS : ald_rmu.h
  • RMU_PERH_QSPI : ald_rmu.h
  • RMU_PERH_RTC : ald_rmu.h
  • RMU_PERH_SPI0 : ald_rmu.h
  • RMU_PERH_SPI1 : ald_rmu.h
  • RMU_PERH_SPI2 : ald_rmu.h
  • RMU_PERH_TIMER0 : ald_rmu.h
  • RMU_PERH_TIMER1 : ald_rmu.h
  • RMU_PERH_TIMER2 : ald_rmu.h
  • RMU_PERH_TIMER3 : ald_rmu.h
  • RMU_PERH_TIMER4 : ald_rmu.h
  • RMU_PERH_TIMER5 : ald_rmu.h
  • RMU_PERH_TIMER6 : ald_rmu.h
  • RMU_PERH_TIMER7 : ald_rmu.h
  • RMU_PERH_TRNG : ald_rmu.h
  • RMU_PERH_TSENSE : ald_rmu.h
  • RMU_PERH_UART0 : ald_rmu.h
  • RMU_PERH_UART1 : ald_rmu.h
  • RMU_PERH_UART2 : ald_rmu.h
  • RMU_PERH_UART3 : ald_rmu.h
  • RMU_PERH_UART4 : ald_rmu.h
  • RMU_PERH_UART5 : ald_rmu.h
  • RMU_PERH_USB : ald_rmu.h
  • RMU_PERH_WWDT : ald_rmu.h
  • RMU_RST_ALL : ald_rmu.h
  • RMU_RST_BOR : ald_rmu.h
  • RMU_RST_CFG : ald_rmu.h
  • RMU_RST_CFGERR : ald_rmu.h
  • RMU_RST_CHIP : ald_rmu.h
  • RMU_RST_CPU : ald_rmu.h
  • RMU_RST_IWDT : ald_rmu.h
  • RMU_RST_LOCKUP : ald_rmu.h
  • RMU_RST_MCU : ald_rmu.h
  • RMU_RST_NMRST : ald_rmu.h
  • RMU_RST_POR : ald_rmu.h
  • RMU_RST_WAKEUP : ald_rmu.h
  • RMU_RST_WWDT : ald_rmu.h
  • RMU_VOL_2_0 : ald_rmu.h
  • RMU_VOL_2_2 : ald_rmu.h
  • RMU_VOL_2_4 : ald_rmu.h
  • RMU_VOL_2_6 : ald_rmu.h
  • RMU_VOL_2_8 : ald_rmu.h
  • RMU_VOL_3_0 : ald_rmu.h
  • RMU_VOL_3_2 : ald_rmu.h
  • RMU_VOL_3_4 : ald_rmu.h
  • RMU_VOL_3_6 : ald_rmu.h
  • RMU_VOL_3_8 : ald_rmu.h
  • RMU_VOL_4_0 : ald_rmu.h
  • RMU_VOL_4_2 : ald_rmu.h
  • RMU_VOL_4_4 : ald_rmu.h
  • RMU_VOL_4_6 : ald_rmu.h
  • RMU_VOL_4_8 : ald_rmu.h
  • RMU_VOL_NONE : ald_rmu.h
  • RTC_ALARM_A : ald_rtc.h
  • RTC_ALARM_B : ald_rtc.h
  • RTC_ALARM_MASK_ALL : ald_rtc.h
  • RTC_ALARM_MASK_HOUR : ald_rtc.h
  • RTC_ALARM_MASK_MINUTE : ald_rtc.h
  • RTC_ALARM_MASK_NONE : ald_rtc.h
  • RTC_ALARM_MASK_SECOND : ald_rtc.h
  • RTC_ALARM_MASK_WEEK_DAY : ald_rtc.h
  • RTC_ALARM_SS_MASK_14 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_1 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_10 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_11 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_12 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_13 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_2 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_3 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_4 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_5 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_6 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_7 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_8 : ald_rtc.h
  • RTC_ALARM_SS_MASK_14_9 : ald_rtc.h
  • RTC_ALARM_SS_MASK_ALL : ald_rtc.h
  • RTC_ALARM_SS_MASK_NONE : ald_rtc.h
  • RTC_CALI_CALC_2 : ald_rtc.h
  • RTC_CALI_CALC_4 : ald_rtc.h
  • RTC_CALI_CALC_FREQ_10_MIN : ald_rtc.h
  • RTC_CALI_CALC_FREQ_10_SEC : ald_rtc.h
  • RTC_CALI_CALC_FREQ_1_HOUR : ald_rtc.h
  • RTC_CALI_CALC_FREQ_1_MIN : ald_rtc.h
  • RTC_CALI_CALC_FREQ_20_MIN : ald_rtc.h
  • RTC_CALI_CALC_FREQ_20_SEC : ald_rtc.h
  • RTC_CALI_CALC_FREQ_2_MIN : ald_rtc.h
  • RTC_CALI_CALC_FREQ_5_MIN : ald_rtc.h
  • RTC_CALI_FREQ_10_MIN : ald_rtc.h
  • RTC_CALI_FREQ_10_SEC : ald_rtc.h
  • RTC_CALI_FREQ_1_MIN : ald_rtc.h
  • RTC_CALI_FREQ_1_SEC : ald_rtc.h
  • RTC_CALI_FREQ_20_MIN : ald_rtc.h
  • RTC_CALI_FREQ_20_SEC : ald_rtc.h
  • RTC_CALI_FREQ_2_MIN : ald_rtc.h
  • RTC_CALI_FREQ_5_MIN : ald_rtc.h
  • RTC_CALI_MODE_NORMAL : ald_rtchw.h
  • RTC_CALI_MODE_SLEEP : ald_rtchw.h
  • RTC_CALI_TC_AUTO_BY_HW : ald_rtc.h
  • RTC_CALI_TC_AUTO_BY_HW_SF : ald_rtc.h
  • RTC_CALI_TC_AUTO_BY_SF : ald_rtc.h
  • RTC_CALI_TC_NONE : ald_rtc.h
  • RTC_CLOCK_OUTPUT_1 : ald_rtc.h
  • RTC_CLOCK_OUTPUT_1024 : ald_rtc.h
  • RTC_CLOCK_OUTPUT_32 : ald_rtc.h
  • RTC_CLOCK_OUTPUT_32768 : ald_rtc.h
  • RTC_CLOCK_OUTPUT_CAL_1 : ald_rtc.h
  • RTC_CLOCK_OUTPUT_EXA_1 : ald_rtc.h
  • RTC_FORMAT_BCD : ald_rtc.h
  • RTC_FORMAT_DEC : ald_rtc.h
  • RTC_HOUR_FORMAT_12 : ald_rtc.h
  • RTC_HOUR_FORMAT_24 : ald_rtc.h
  • RTC_IF_ALMA : ald_rtc.h
  • RTC_IF_ALMB : ald_rtc.h
  • RTC_IF_DAY : ald_rtc.h
  • RTC_IF_HR : ald_rtc.h
  • RTC_IF_MIN : ald_rtc.h
  • RTC_IF_MON : ald_rtc.h
  • RTC_IF_RSC : ald_rtc.h
  • RTC_IF_SEC : ald_rtc.h
  • RTC_IF_SFC : ald_rtc.h
  • RTC_IF_TCC : ald_rtc.h
  • RTC_IF_TCE : ald_rtc.h
  • RTC_IF_TP0 : ald_rtc.h
  • RTC_IF_TP1 : ald_rtc.h
  • RTC_IF_TS : ald_rtc.h
  • RTC_IF_TSOV : ald_rtc.h
  • RTC_IF_WU : ald_rtc.h
  • RTC_IF_YR : ald_rtc.h
  • RTC_IT_ALMA : ald_rtc.h
  • RTC_IT_ALMB : ald_rtc.h
  • RTC_IT_DAY : ald_rtc.h
  • RTC_IT_HR : ald_rtc.h
  • RTC_IT_MIN : ald_rtc.h
  • RTC_IT_MON : ald_rtc.h
  • RTC_IT_RSC : ald_rtc.h
  • RTC_IT_SEC : ald_rtc.h
  • RTC_IT_SFC : ald_rtc.h
  • RTC_IT_TCC : ald_rtc.h
  • RTC_IT_TCE : ald_rtc.h
  • RTC_IT_TP0 : ald_rtc.h
  • RTC_IT_TP1 : ald_rtc.h
  • RTC_IT_TS : ald_rtc.h
  • RTC_IT_TSOV : ald_rtc.h
  • RTC_IT_WU : ald_rtc.h
  • RTC_IT_YR : ald_rtc.h
  • RTC_OUTPUT_ALARM_A : ald_rtc.h
  • RTC_OUTPUT_ALARM_B : ald_rtc.h
  • RTC_OUTPUT_DISABLE : ald_rtc.h
  • RTC_OUTPUT_POLARITY_HIGH : ald_rtc.h
  • RTC_OUTPUT_POLARITY_LOW : ald_rtc.h
  • RTC_OUTPUT_WAKEUP : ald_rtc.h
  • RTC_SELECT_DAY : ald_rtc.h
  • RTC_SELECT_WEEK : ald_rtc.h
  • RTC_SOURCE_HOSC_DIV_1M : ald_rtc.h
  • RTC_SOURCE_HRC_DIV_1M : ald_rtc.h
  • RTC_SOURCE_LOSC : ald_rtc.h
  • RTC_SOURCE_LRC : ald_rtc.h
  • RTC_TAMPER_0 : ald_rtc.h
  • RTC_TAMPER_1 : ald_rtc.h
  • RTC_TAMPER_DURATION_1 : ald_rtc.h
  • RTC_TAMPER_DURATION_2 : ald_rtc.h
  • RTC_TAMPER_DURATION_4 : ald_rtc.h
  • RTC_TAMPER_DURATION_8 : ald_rtc.h
  • RTC_TAMPER_SAMPLING_FREQ_1024 : ald_rtc.h
  • RTC_TAMPER_SAMPLING_FREQ_16384 : ald_rtc.h
  • RTC_TAMPER_SAMPLING_FREQ_2048 : ald_rtc.h
  • RTC_TAMPER_SAMPLING_FREQ_256 : ald_rtc.h
  • RTC_TAMPER_SAMPLING_FREQ_32768 : ald_rtc.h
  • RTC_TAMPER_SAMPLING_FREQ_4096 : ald_rtc.h
  • RTC_TAMPER_SAMPLING_FREQ_512 : ald_rtc.h
  • RTC_TAMPER_SAMPLING_FREQ_8192 : ald_rtc.h
  • RTC_TAMPER_TRIGGER_HIGH : ald_rtc.h
  • RTC_TAMPER_TRIGGER_LOW : ald_rtc.h
  • RTC_TS_FALLING_EDGE : ald_rtc.h
  • RTC_TS_RISING_EDGE : ald_rtc.h
  • RTC_TS_SIGNAL_SEL_TAMPER0 : ald_rtc.h
  • RTC_TS_SIGNAL_SEL_TAMPER1 : ald_rtc.h
  • RTC_WAKEUP_CLOCK_1HZ : ald_rtc.h
  • RTC_WAKEUP_CLOCK_1HZ_PULS : ald_rtc.h
  • RTC_WAKEUP_CLOCK_DIV_16 : ald_rtc.h
  • RTC_WAKEUP_CLOCK_DIV_2 : ald_rtc.h
  • RTC_WAKEUP_CLOCK_DIV_4 : ald_rtc.h
  • RTC_WAKEUP_CLOCK_DIV_8 : ald_rtc.h


ALD User Manual: Globals

- s -

  • SCARD_CLOCK_DIV1 : ald_uart.h
  • SCARD_CLOCK_DIV2 : ald_uart.h
  • SCARD_CLOCK_DIV4 : ald_uart.h
  • SCARD_CLOCK_DIV6 : ald_uart.h
  • SCARD_RETRY_CNT0 : ald_uart.h
  • SCARD_RETRY_CNT1 : ald_uart.h
  • SCARD_RETRY_CNT2 : ald_uart.h
  • SCARD_RETRY_CNT3 : ald_uart.h
  • SCARD_RETRY_CNT4 : ald_uart.h
  • SCARD_RETRY_CNT5 : ald_uart.h
  • SCARD_RETRY_CNT6 : ald_uart.h
  • SCARD_RETRY_CNT7 : ald_uart.h
  • SET : type.h
  • SPI_BAUD_128 : ald_spi.h
  • SPI_BAUD_16 : ald_spi.h
  • SPI_BAUD_2 : ald_spi.h
  • SPI_BAUD_256 : ald_spi.h
  • SPI_BAUD_32 : ald_spi.h
  • SPI_BAUD_4 : ald_spi.h
  • SPI_BAUD_64 : ald_spi.h
  • SPI_BAUD_8 : ald_spi.h
  • SPI_CPHA_FIRST : ald_spi.h
  • SPI_CPHA_SECOND : ald_spi.h
  • SPI_CPOL_HIGH : ald_spi.h
  • SPI_CPOL_LOW : ald_spi.h
  • SPI_DATA_SIZE_16 : ald_spi.h
  • SPI_DATA_SIZE_8 : ald_spi.h
  • SPI_DIRECTION_1LINE : ald_spi.h
  • SPI_DIRECTION_1LINE_RX : ald_spi.h
  • SPI_DIRECTION_2LINES : ald_spi.h
  • SPI_DIRECTION_2LINES_RXONLY : ald_spi.h
  • SPI_DMA_REQ_RX : ald_spi.h
  • SPI_DMA_REQ_TX : ald_spi.h
  • SPI_ERROR_CRC : ald_spi.h
  • SPI_ERROR_FLAG : ald_spi.h
  • SPI_ERROR_FRE : ald_spi.h
  • SPI_ERROR_MODF : ald_spi.h
  • SPI_ERROR_NONE : ald_spi.h
  • SPI_ERROR_RXOV : ald_spi.h
  • SPI_ERROR_TXOV : ald_spi.h
  • SPI_FIRSTBIT_LSB : ald_spi.h
  • SPI_FIRSTBIT_MSB : ald_spi.h
  • SPI_FRAME_MOTOROLA : ald_spi.h
  • SPI_FRAME_TI : ald_spi.h
  • SPI_IF_CRCERR : ald_spi.h
  • SPI_IF_FRE : ald_spi.h
  • SPI_IF_MODF : ald_spi.h
  • SPI_IF_RXF : ald_spi.h
  • SPI_IF_RXOV : ald_spi.h
  • SPI_IF_RXTH : ald_spi.h
  • SPI_IF_RXUD : ald_spi.h
  • SPI_IF_TXE : ald_spi.h
  • SPI_IF_TXOV : ald_spi.h
  • SPI_IF_TXTH : ald_spi.h
  • SPI_IF_TXUD : ald_spi.h
  • SPI_IT_CRCERR : ald_spi.h
  • SPI_IT_FRE : ald_spi.h
  • SPI_IT_MODF : ald_spi.h
  • SPI_IT_RXF : ald_spi.h
  • SPI_IT_RXOV : ald_spi.h
  • SPI_IT_RXTH : ald_spi.h
  • SPI_IT_RXUD : ald_spi.h
  • SPI_IT_TXE : ald_spi.h
  • SPI_IT_TXOV : ald_spi.h
  • SPI_IT_TXTH : ald_spi.h
  • SPI_IT_TXUD : ald_spi.h
  • SPI_MODE_MASTER : ald_spi.h
  • SPI_MODE_SLAVER : ald_spi.h
  • SPI_SR_RXNE : ald_spi.h
  • SPI_SR_TXE : ald_spi.h
  • SPI_SR_TXE_RXNE : ald_spi.h
  • SPI_STATE_BUSY : ald_spi.h
  • SPI_STATE_BUSY_RX : ald_spi.h
  • SPI_STATE_BUSY_TX : ald_spi.h
  • SPI_STATE_BUSY_TX_RX : ald_spi.h
  • SPI_STATE_ERROR : ald_spi.h
  • SPI_STATE_READY : ald_spi.h
  • SPI_STATE_RESET : ald_spi.h
  • SPI_STATE_TIMEOUT : ald_spi.h
  • SPI_STATUS_BUSY : ald_spi.h
  • SPI_STATUS_RXE : ald_spi.h
  • SPI_STATUS_RXF : ald_spi.h
  • SPI_STATUS_RXOV : ald_spi.h
  • SPI_STATUS_RXTH : ald_spi.h
  • SPI_STATUS_RXUD : ald_spi.h
  • SPI_STATUS_TXE : ald_spi.h
  • SPI_STATUS_TXF : ald_spi.h
  • SPI_STATUS_TXOV : ald_spi.h
  • SPI_STATUS_TXTH : ald_spi.h
  • SPI_STATUS_TXUD : ald_spi.h
  • SYSTICK_INTERVAL_1000MS : utils.h
  • SYSTICK_INTERVAL_100MS : utils.h
  • SYSTICK_INTERVAL_10MS : utils.h
  • SYSTICK_INTERVAL_1MS : utils.h


ALD User Manual: Globals

- t -

  • TIMEOUT : utils.h
  • TIMER_ACTIVE_CHANNEL_1 : ald_timer.h
  • TIMER_ACTIVE_CHANNEL_2 : ald_timer.h
  • TIMER_ACTIVE_CHANNEL_3 : ald_timer.h
  • TIMER_ACTIVE_CHANNEL_4 : ald_timer.h
  • TIMER_ACTIVE_CHANNEL_CLEARED : ald_timer.h
  • TIMER_BREAK_POLARITY_HIGH : ald_timer.h
  • TIMER_BREAK_POLARITY_LOW : ald_timer.h
  • TIMER_CHANNEL_1 : ald_timer.h
  • TIMER_CHANNEL_2 : ald_timer.h
  • TIMER_CHANNEL_3 : ald_timer.h
  • TIMER_CHANNEL_4 : ald_timer.h
  • TIMER_CHANNEL_ALL : ald_timer.h
  • TIMER_CHNREF_CLR_CMP_IN : ald_timer.h
  • TIMER_CHNREF_CLR_ETF : ald_timer.h
  • TIMER_CLK_POLARITY_BOTH : ald_timer.h
  • TIMER_CLK_POLARITY_FALL : ald_timer.h
  • TIMER_CLK_POLARITY_INV : ald_timer.h
  • TIMER_CLK_POLARITY_NO_INV : ald_timer.h
  • TIMER_CLK_POLARITY_RISE : ald_timer.h
  • TIMER_CLOCK_DIV1 : ald_timer.h
  • TIMER_CLOCK_DIV2 : ald_timer.h
  • TIMER_CLOCK_DIV4 : ald_timer.h
  • TIMER_CNT_MODE_CENTER1 : ald_timer.h
  • TIMER_CNT_MODE_CENTER2 : ald_timer.h
  • TIMER_CNT_MODE_CENTER3 : ald_timer.h
  • TIMER_CNT_MODE_DOWN : ald_timer.h
  • TIMER_CNT_MODE_UP : ald_timer.h
  • TIMER_DMA_CC1 : ald_timer.h
  • TIMER_DMA_CC2 : ald_timer.h
  • TIMER_DMA_CC3 : ald_timer.h
  • TIMER_DMA_CC4 : ald_timer.h
  • TIMER_DMA_COM : ald_timer.h
  • TIMER_DMA_TRIGGER : ald_timer.h
  • TIMER_DMA_UPDATE : ald_timer.h
  • TIMER_ENC_MODE_TI1 : ald_timer.h
  • TIMER_ENC_MODE_TI12 : ald_timer.h
  • TIMER_ENC_MODE_TI2 : ald_timer.h
  • TIMER_ETR_PSC_DIV1 : ald_timer.h
  • TIMER_ETR_PSC_DIV2 : ald_timer.h
  • TIMER_ETR_PSC_DIV4 : ald_timer.h
  • TIMER_ETR_PSC_DIV8 : ald_timer.h
  • TIMER_FLAG_BREAK : ald_timer.h
  • TIMER_FLAG_CC1 : ald_timer.h
  • TIMER_FLAG_CC1OF : ald_timer.h
  • TIMER_FLAG_CC2 : ald_timer.h
  • TIMER_FLAG_CC2OF : ald_timer.h
  • TIMER_FLAG_CC3 : ald_timer.h
  • TIMER_FLAG_CC3OF : ald_timer.h
  • TIMER_FLAG_CC4 : ald_timer.h
  • TIMER_FLAG_CC4OF : ald_timer.h
  • TIMER_FLAG_COM : ald_timer.h
  • TIMER_FLAG_TRIGGER : ald_timer.h
  • TIMER_FLAG_UPDATE : ald_timer.h
  • TIMER_IC_POLARITY_FALL : ald_timer.h
  • TIMER_IC_POLARITY_RISE : ald_timer.h
  • TIMER_IC_PSC_DIV1 : ald_timer.h
  • TIMER_IC_PSC_DIV2 : ald_timer.h
  • TIMER_IC_PSC_DIV4 : ald_timer.h
  • TIMER_IC_PSC_DIV8 : ald_timer.h
  • TIMER_IC_SEL_DIRECT : ald_timer.h
  • TIMER_IC_SEL_INDIRECT : ald_timer.h
  • TIMER_IC_SEL_TRC : ald_timer.h
  • TIMER_INPUT_ETR : ald_timer.h
  • TIMER_INPUT_NONE : ald_timer.h
  • TIMER_IT_BREAK : ald_timer.h
  • TIMER_IT_CC1 : ald_timer.h
  • TIMER_IT_CC2 : ald_timer.h
  • TIMER_IT_CC3 : ald_timer.h
  • TIMER_IT_CC4 : ald_timer.h
  • TIMER_IT_COM : ald_timer.h
  • TIMER_IT_TRIGGER : ald_timer.h
  • TIMER_IT_UPDATE : ald_timer.h
  • TIMER_LOCK_LEVEL_1 : ald_timer.h
  • TIMER_LOCK_LEVEL_2 : ald_timer.h
  • TIMER_LOCK_LEVEL_3 : ald_timer.h
  • TIMER_LOCK_LEVEL_OFF : ald_timer.h
  • TIMER_MODE_DISABLE : ald_timer.h
  • TIMER_MODE_ENC1 : ald_timer.h
  • TIMER_MODE_ENC2 : ald_timer.h
  • TIMER_MODE_ENC3 : ald_timer.h
  • TIMER_MODE_EXTERNAL1 : ald_timer.h
  • TIMER_MODE_GATED : ald_timer.h
  • TIMER_MODE_RESET : ald_timer.h
  • TIMER_MODE_TRIG : ald_timer.h
  • TIMER_OC_IDLE_RESET : ald_timer.h
  • TIMER_OC_IDLE_SET : ald_timer.h
  • TIMER_OC_MODE_ACTIVE : ald_timer.h
  • TIMER_OC_MODE_FORCE_ACTIVE : ald_timer.h
  • TIMER_OC_MODE_FORCE_INACTIVE : ald_timer.h
  • TIMER_OC_MODE_INACTIVE : ald_timer.h
  • TIMER_OC_MODE_PWM1 : ald_timer.h
  • TIMER_OC_MODE_PWM2 : ald_timer.h
  • TIMER_OC_MODE_TIMERING : ald_timer.h
  • TIMER_OC_MODE_TOGGLE : ald_timer.h
  • TIMER_OC_POLARITY_HIGH : ald_timer.h
  • TIMER_OC_POLARITY_LOW : ald_timer.h
  • TIMER_OCN_IDLE_RESET : ald_timer.h
  • TIMER_OCN_IDLE_SET : ald_timer.h
  • TIMER_OCN_POLARITY_HIGH : ald_timer.h
  • TIMER_OCN_POLARITY_LOW : ald_timer.h
  • TIMER_OP_MODE_REPEAT : ald_timer.h
  • TIMER_OP_MODE_SINGLE : ald_timer.h
  • TIMER_OP_OUTPUT_CHANNEL_1 : ald_timer.h
  • TIMER_OP_OUTPUT_CHANNEL_2 : ald_timer.h
  • TIMER_POLARITY_INV : ald_timer.h
  • TIMER_POLARITY_NO_INV : ald_timer.h
  • TIMER_SRC_BREAK : ald_timer.h
  • TIMER_SRC_CC1 : ald_timer.h
  • TIMER_SRC_CC2 : ald_timer.h
  • TIMER_SRC_CC3 : ald_timer.h
  • TIMER_SRC_CC4 : ald_timer.h
  • TIMER_SRC_COM : ald_timer.h
  • TIMER_SRC_ETRMODE1 : ald_timer.h
  • TIMER_SRC_ETRMODE2 : ald_timer.h
  • TIMER_SRC_INTER : ald_timer.h
  • TIMER_SRC_ITR0 : ald_timer.h
  • TIMER_SRC_ITR1 : ald_timer.h
  • TIMER_SRC_ITR2 : ald_timer.h
  • TIMER_SRC_ITR3 : ald_timer.h
  • TIMER_SRC_TI1 : ald_timer.h
  • TIMER_SRC_TI1ED : ald_timer.h
  • TIMER_SRC_TI2 : ald_timer.h
  • TIMER_SRC_TRIG : ald_timer.h
  • TIMER_SRC_UPDATE : ald_timer.h
  • TIMER_STATE_BUSY : ald_timer.h
  • TIMER_STATE_ERROR : ald_timer.h
  • TIMER_STATE_READY : ald_timer.h
  • TIMER_STATE_RESET : ald_timer.h
  • TIMER_STATE_TIMEREOUT : ald_timer.h
  • TIMER_TRGO_ENABLE : ald_timer.h
  • TIMER_TRGO_OC1 : ald_timer.h
  • TIMER_TRGO_OC1REF : ald_timer.h
  • TIMER_TRGO_OC2REF : ald_timer.h
  • TIMER_TRGO_OC3REF : ald_timer.h
  • TIMER_TRGO_OC4REF : ald_timer.h
  • TIMER_TRGO_RESET : ald_timer.h
  • TIMER_TRGO_UPDATE : ald_timer.h
  • TIMER_TS_ETRF : ald_timer.h
  • TIMER_TS_ITR0 : ald_timer.h
  • TIMER_TS_ITR1 : ald_timer.h
  • TIMER_TS_ITR2 : ald_timer.h
  • TIMER_TS_ITR3 : ald_timer.h
  • TIMER_TS_TI1F_ED : ald_timer.h
  • TIMER_TS_TI1FP1 : ald_timer.h
  • TIMER_TS_TI2FP2 : ald_timer.h
  • TRNG_DSEL_16B : ald_trng.h
  • TRNG_DSEL_1B : ald_trng.h
  • TRNG_DSEL_32B : ald_trng.h
  • TRNG_DSEL_8B : ald_trng.h
  • TRNG_IF_DAVLD : ald_trng.h
  • TRNG_IF_SERR : ald_trng.h
  • TRNG_IF_START : ald_trng.h
  • TRNG_IT_DAVLD : ald_trng.h
  • TRNG_IT_SERR : ald_trng.h
  • TRNG_IT_START : ald_trng.h
  • TRNG_SEED_TYPE_0 : ald_trng.h
  • TRNG_SEED_TYPE_1 : ald_trng.h
  • TRNG_SEED_TYPE_LAST : ald_trng.h
  • TRNG_SEED_TYPE_SEED : ald_trng.h
  • TRNG_STATE_BUSY : ald_trng.h
  • TRNG_STATE_ERROR : ald_trng.h
  • TRNG_STATE_READY : ald_trng.h
  • TRNG_STATE_RESET : ald_trng.h
  • TRNG_STATUS_DAVLD : ald_trng.h
  • TRNG_STATUS_SERR : ald_trng.h
  • TRNG_STATUS_START : ald_trng.h
  • TRUE : type.h
  • TSENSE_OUTPUT_MODE_1600 : ald_tsense.h
  • TSENSE_OUTPUT_MODE_200 : ald_tsense.h
  • TSENSE_OUTPUT_MODE_3200 : ald_tsense.h
  • TSENSE_OUTPUT_MODE_400 : ald_tsense.h
  • TSENSE_OUTPUT_MODE_800 : ald_tsense.h
  • TSENSE_SOURCE_LOSC : ald_tsense.h
  • TSENSE_SOURCE_LRC : ald_tsense.h
  • TSENSE_UPDATE_CYCLE_3 : ald_tsense.h
  • TSENSE_UPDATE_CYCLE_4 : ald_tsense.h
  • TSENSE_UPDATE_CYCLE_5 : ald_tsense.h
  • TSENSE_UPDATE_CYCLE_6 : ald_tsense.h
  • TSENSE_UPDATE_CYCLE_7 : ald_tsense.h


ALD User Manual: Globals

- u -

  • UART_ABRMOD_0_TO_1 : ald_uart.h
  • UART_ABRMOD_1 : ald_uart.h
  • UART_ABRMOD_1_TO_0 : ald_uart.h
  • UART_DMA_REQ_RX : ald_uart.h
  • UART_DMA_REQ_TX : ald_uart.h
  • UART_ERROR_DMA : ald_uart.h
  • UART_ERROR_FE : ald_uart.h
  • UART_ERROR_NE : ald_uart.h
  • UART_ERROR_NONE : ald_uart.h
  • UART_ERROR_ORE : ald_uart.h
  • UART_ERROR_PE : ald_uart.h
  • UART_HW_FLOW_CTL_DISABLE : ald_uart.h
  • UART_HW_FLOW_CTL_ENABLE : ald_uart.h
  • UART_IF_ABEND : ald_uart.h
  • UART_IF_ABTO : ald_uart.h
  • UART_IF_ADDRM : ald_uart.h
  • UART_IF_DCTS : ald_uart.h
  • UART_IF_EOB : ald_uart.h
  • UART_IF_LINBK : ald_uart.h
  • UART_IF_NOISE : ald_uart.h
  • UART_IF_RFFULL : ald_uart.h
  • UART_IF_RFOERR : ald_uart.h
  • UART_IF_RFTH : ald_uart.h
  • UART_IF_RFUERR : ald_uart.h
  • UART_IF_RXBERR : ald_uart.h
  • UART_IF_RXTO : ald_uart.h
  • UART_IF_TBC : ald_uart.h
  • UART_IF_TFEMPTY : ald_uart.h
  • UART_IF_TFOVER : ald_uart.h
  • UART_IF_TFTH : ald_uart.h
  • UART_IT_ABEND : ald_uart.h
  • UART_IT_ABTO : ald_uart.h
  • UART_IT_ADDRM : ald_uart.h
  • UART_IT_DCTS : ald_uart.h
  • UART_IT_EOB : ald_uart.h
  • UART_IT_LINBK : ald_uart.h
  • UART_IT_NOISE : ald_uart.h
  • UART_IT_RFFULL : ald_uart.h
  • UART_IT_RFOERR : ald_uart.h
  • UART_IT_RFTH : ald_uart.h
  • UART_IT_RFUERR : ald_uart.h
  • UART_IT_RXBERR : ald_uart.h
  • UART_IT_RXTO : ald_uart.h
  • UART_IT_TFEMPTY : ald_uart.h
  • UART_IT_TFOVER : ald_uart.h
  • UART_IT_TFTH : ald_uart.h
  • UART_IT_TSEMPTY : ald_uart.h
  • UART_MODE_HDSEL : ald_uart.h
  • UART_MODE_IrDA : ald_uart.h
  • UART_MODE_LIN : ald_uart.h
  • UART_MODE_RS485 : ald_uart.h
  • UART_MODE_SCARD : ald_uart.h
  • UART_MODE_UART : ald_uart.h
  • UART_PARITY_EVEN : ald_uart.h
  • UART_PARITY_NONE : ald_uart.h
  • UART_PARITY_ODD : ald_uart.h
  • UART_RXFIFO_14BYTE : ald_uart.h
  • UART_RXFIFO_1BYTE : ald_uart.h
  • UART_RXFIFO_4BYTE : ald_uart.h
  • UART_RXFIFO_8BYTE : ald_uart.h
  • UART_STATE_BUSY : ald_uart.h
  • UART_STATE_BUSY_RX : ald_uart.h
  • UART_STATE_BUSY_TX : ald_uart.h
  • UART_STATE_BUSY_TX_RX : ald_uart.h
  • UART_STATE_ERROR : ald_uart.h
  • UART_STATE_READY : ald_uart.h
  • UART_STATE_RESET : ald_uart.h
  • UART_STATE_TIMEOUT : ald_uart.h
  • UART_STATUS_BKERR : ald_uart.h
  • UART_STATUS_CTSSTA : ald_uart.h
  • UART_STATUS_FERR : ald_uart.h
  • UART_STATUS_PERR : ald_uart.h
  • UART_STATUS_RFEMPTY : ald_uart.h
  • UART_STATUS_RFFULL : ald_uart.h
  • UART_STATUS_RFOERR : ald_uart.h
  • UART_STATUS_RFTH : ald_uart.h
  • UART_STATUS_RFUERR : ald_uart.h
  • UART_STATUS_RSBUSY : ald_uart.h
  • UART_STATUS_TFEMPTY : ald_uart.h
  • UART_STATUS_TFFULL : ald_uart.h
  • UART_STATUS_TFOERR : ald_uart.h
  • UART_STATUS_TFTH : ald_uart.h
  • UART_STATUS_TSBUSY : ald_uart.h
  • UART_STOP_BITS_0_5 : ald_uart.h
  • UART_STOP_BITS_1 : ald_uart.h
  • UART_STOP_BITS_1_5 : ald_uart.h
  • UART_STOP_BITS_2 : ald_uart.h
  • UART_TXFIFO_2BYTE : ald_uart.h
  • UART_TXFIFO_4BYTE : ald_uart.h
  • UART_TXFIFO_8BYTE : ald_uart.h
  • UART_TXFIFO_EMPTY : ald_uart.h
  • UART_WORD_LENGTH_5B : ald_uart.h
  • UART_WORD_LENGTH_6B : ald_uart.h
  • UART_WORD_LENGTH_7B : ald_uart.h
  • UART_WORD_LENGTH_8B : ald_uart.h
  • UNLOCK : type.h


ALD User Manual: Globals

- w -

  • WWDT_WIN_00 : ald_wdt.h
  • WWDT_WIN_25 : ald_wdt.h
  • WWDT_WIN_50 : ald_wdt.h
  • WWDT_WIN_75 : ald_wdt.h


ALD User Manual: Globals

- _ -

  • __ALD_VERSION : utils.c
  • __ALD_VERSION_MAIN : utils.c
  • __ALD_VERSION_RC : utils.c
  • __ALD_VERSION_SUB1 : utils.c
  • __ALD_VERSION_SUB2 : utils.c
  • __INLINE__ : type.h
  • __isr__ : type.h
  • __LOCK : utils.h
  • __RAMFUNC : ald_flash.c
  • __STATIC_INLINE__ : type.h
  • __UNLOCK : utils.h


ALD User Manual: Globals

- a -

  • ACMP_DISABLE : ald_acmp.h
  • ACMP_ENABLE : ald_acmp.h
  • ADC_CALIBRATE_DISABLE : ald_adc.h
  • ADC_CALIBRATE_ENABLE : ald_adc.h
  • ADC_DISABLE : ald_adc.h
  • ADC_ENABLE : ald_adc.h
  • ADC_IETS_DISABLE : ald_adc.h
  • ADC_IETS_ENABLE : ald_adc.h
  • ADC_IH_TRIG_BY_SOFT : ald_adc.h
  • ADC_NETS_DISABLE : ald_adc.h
  • ADC_NETS_ENABLE : ald_adc.h
  • ADC_NH_TRIG_BY_SOFT : ald_adc.h
  • ADC_RESET_HANDLE_STATE : ald_adc.h
  • ADC_SPEED_HIGH_DISABLE : ald_adc.h
  • ADC_SPEED_HIGH_ENABLE : ald_adc.h
  • ADC_VREF_OUT_DISABLE : ald_adc.h
  • ADC_VREF_OUT_ENABLE : ald_adc.h
  • ADDR_1ST_CYCLE : ald_nand.h
  • ADDR_2ND_CYCLE : ald_nand.h
  • ADDR_3RD_CYCLE : ald_nand.h
  • ADDR_4TH_CYCLE : ald_nand.h
  • ADDR_AREA : ald_nand.h
  • ALARM_MASK_ALL : ald_rtc.h
  • ALD_ACMP : ald_conf.h
  • ALD_ADC : ald_conf.h
  • ALD_BKPC : ald_conf.h
  • ALD_CALC : ald_conf.h
  • ALD_CAN : ald_conf.h
  • ALD_CMU : ald_conf.h
  • ALD_CRC : ald_conf.h
  • ALD_CRYPT : ald_conf.h
  • ALD_DAC : ald_conf.h
  • ALD_DMA : ald_conf.h
  • ALD_EBI : ald_conf.h
  • ALD_ECC : ald_conf.h
  • ALD_FLASH : ald_conf.h
  • ALD_GPIO : ald_conf.h
  • ALD_I2C : ald_conf.h
  • ALD_I2S : ald_conf.h
  • ALD_IAP : ald_conf.h
  • ALD_LCD : ald_conf.h
  • ALD_LPTIM : ald_conf.h
  • ALD_LPUART : ald_conf.h
  • ALD_MAX_DELAY : utils.h
  • ALD_NAND : ald_conf.h
  • ALD_NOR : ald_conf.h
  • ALD_OPAMP : ald_conf.h
  • ALD_PANIC : utils.h
  • ALD_PIS : ald_conf.h
  • ALD_PMU : ald_conf.h
  • ALD_QSPI : ald_conf.h
  • ALD_RMU : ald_conf.h
  • ALD_RTC : ald_conf.h
  • ALD_SPI : ald_conf.h
  • ALD_SRAM : ald_conf.h
  • ALD_TIMER : ald_conf.h
  • ALD_TRNG : ald_conf.h
  • ALD_TSENSE : ald_conf.h
  • ALD_UART : ald_conf.h
  • ALD_USB : ald_conf.h
  • ALD_WDT : ald_conf.h
  • ARRAY_ADDRESS : ald_nand.h
  • assert_param : type.h


ALD User Manual: Globals

- b -

  • BCTRLR_CLEAR_MASK : ald_ebi.h
  • BIT : type.h
  • BITBAND_PER_BASE : type.h
  • BITBAND_RAM_BASE : type.h
  • BITS : type.h
  • BKPC_LOCK : ald_bkpc.h
  • BKPC_LOSC_DISABLE : ald_bkpc.h
  • BKPC_LOSC_ENABLE : ald_bkpc.h
  • BKPC_LOSM_DISABLE : ald_bkpc.h
  • BKPC_LOSM_ENABLE : ald_bkpc.h
  • BKPC_LRC_DISABLE : ald_bkpc.h
  • BKPC_LRC_ENABLE : ald_bkpc.h
  • BKPC_MRST_WAKEUP_DISABLE : ald_bkpc.h
  • BKPC_MRST_WAKEUP_ENABLE : ald_bkpc.h
  • BKPC_UNLOCK : ald_bkpc.h
  • BTR_CLEAR_MASK : ald_ebi.h
  • BWTR_CLEAR_MASK : ald_ebi.h


ALD User Manual: Globals

- c -

  • CAN_DBG_FREEZE : ald_can.h
  • CAN_RESET_HANDLE_STATE : ald_can.h
  • CAN_RX_MSG_PENDING : ald_can.h
  • CAN_STATE_RX0_MASK : ald_can.h
  • CAN_STATE_RX1_MASK : ald_can.h
  • CAN_STATE_TX_MASK : ald_can.h
  • CAN_TIMEOUT_VALUE : ald_can.h
  • CAN_TX_STAMP_DISABLE : ald_can.h
  • CAN_TX_STAMP_ENABLE : ald_can.h
  • CCER_CCxE_MASK : ald_timer.h
  • CCER_CCxNE_MASK : ald_timer.h
  • CFI1_ADDRESS : ald_nor_lcd.h
  • CFI2_ADDRESS : ald_nor_lcd.h
  • CFI3_ADDRESS : ald_nor_lcd.h
  • CFI4_ADDRESS : ald_nor_lcd.h
  • CLEAR_BIT : type.h
  • CLEAR_REG : type.h
  • CMD_AREA : ald_nand.h
  • CMU_HOSC_DIV_1MHZ_DISABLE : ald_cmu.h
  • CMU_HOSC_DIV_1MHZ_ENABLE : ald_cmu.h
  • CMU_HRC_DIV_1MHZ_DISABLE : ald_cmu.h
  • CMU_HRC_DIV_1MHZ_ENABLE : ald_cmu.h
  • CMU_HRC_SEL_BY_CFGW : ald_cmu.h
  • CMU_HRC_SEL_BY_SW : ald_cmu.h
  • CMU_LOSC_DISABLE : ald_cmu.h
  • CMU_LOSC_ENABLE : ald_cmu.h
  • CMU_LP_HOSC_DISABLE : ald_cmu.h
  • CMU_LP_HOSC_ENABLE : ald_cmu.h
  • CMU_LP_HRC_DISABLE : ald_cmu.h
  • CMU_LP_HRC_ENABLE : ald_cmu.h
  • CMU_LP_LOSC_DISABLE : ald_cmu.h
  • CMU_LP_LOSC_ENABLE : ald_cmu.h
  • CMU_LP_LRC_DISABLE : ald_cmu.h
  • CMU_LP_LRC_ENABLE : ald_cmu.h
  • CMU_LRC_DISABLE : ald_cmu.h
  • CMU_LRC_ENABLE : ald_cmu.h
  • CMU_ULRC_DISABLE : ald_cmu.h
  • CMU_ULRC_ENABLE : ald_cmu.h
  • COLUMN_1ST_CYCLE : ald_nand.h
  • COLUMN_2ND_CYCLE : ald_nand.h
  • COLUMN_ADDRESS : ald_nand.h
  • CRC_CLEAR_ERROR_FLAG : ald_crc.h
  • CRC_DISABLE : ald_crc.h
  • CRC_DMA_DISABLE : ald_crc.h
  • CRC_DMA_ENABLE : ald_crc.h
  • CRC_ENABLE : ald_crc.h
  • CRC_RESET : ald_crc.h
  • CRYPT_DMA_DISABLE : ald_crypt.h
  • CRYPT_DMA_ENABLE : ald_crypt.h
  • CRYPT_FIFOEN_DISABLE : ald_crypt.h
  • CRYPT_FIFOEN_ENABLE : ald_crypt.h
  • CRYPT_GO : ald_crypt.h
  • CRYPT_IE_DISABLE : ald_crypt.h
  • CRYPT_IE_ENABLE : ald_crypt.h
  • CRYPT_IVEN_DISABLE : ald_crypt.h
  • CRYPT_IVEN_ENABLE : ald_crypt.h
  • CRYPT_READ_FIFO : ald_crypt.h
  • CRYPT_SETDIR : ald_crypt.h
  • CRYPT_WRITE_FIFO : ald_crypt.h


ALD User Manual: Globals

- d -

  • DAC_CH0_DISABLE : ald_dac.h
  • DAC_CH0_ENABLE : ald_dac.h
  • DAC_CH1_DISABLE : ald_dac.h
  • DAC_CH1_ENABLE : ald_dac.h
  • DAC_EVENT_CH0_CPLT : ald_dac.h
  • DAC_EVENT_CH0_UF : ald_dac.h
  • DAC_EVENT_CH1_CPLT : ald_dac.h
  • DAC_EVENT_CH1_UF : ald_dac.h
  • DEM_CR : utils.h
  • DEM_CR_TRCENA : utils.h
  • DEVICE_CODE1_ADDR : ald_nor_lcd.h
  • DEVICE_CODE2_ADDR : ald_nor_lcd.h
  • DEVICE_CODE3_ADDR : ald_nor_lcd.h
  • DISABLE_NAK_LIMIT : ald_usb.h
  • DMA_CH_COUNT : ald_dma.h
  • DMA_ERR : ald_dma.h
  • DWT_CR : utils.h
  • DWT_CR_CYCCNTEA : utils.h
  • DWT_CYCCNT : utils.h


ALD User Manual: Globals

- e -

  • EBI_LCD_DEVICE : ald_ebi.h
  • EBI_LCD_TypeDef : ald_ebi.h
  • EBI_NAND_BANK2 : ald_ebi.h
  • EBI_NAND_BANK3 : ald_ebi.h
  • EBI_NAND_DEVICE : ald_ebi.h
  • EBI_NAND_TypeDef : ald_ebi.h
  • EBI_NOR_SRAM_DEVICE : ald_ebi.h
  • EBI_NOR_SRAM_EXTENDED_DEVICE : ald_ebi.h
  • EBI_NOR_SRAM_EXTENDED_TypeDef : ald_ebi.h
  • EBI_NOR_SRAM_TypeDef : ald_ebi.h


ALD User Manual: Globals

- f -

  • FLASH_BASE_ADDR : ald_flash.h
  • FLASH_FIFO : ald_flash.h
  • FLASH_IAP_DISABLE : ald_flash.h
  • FLASH_IAP_ENABLE : ald_flash.h
  • FLASH_PAGE_ADDR : ald_flash.h
  • FLASH_PAGE_MASK : ald_flash.h
  • FLASH_PAGE_SIZE : ald_flash.h
  • FLASH_PAGEEND_ADDR : ald_flash.h
  • FLASH_REG_UNLOCK : ald_flash.h
  • FLASH_REQ : ald_flash.h
  • FLASH_REQ_FIN : ald_flash.h
  • FLASH_TOTAL_SIZE : ald_flash.h
  • FLASH_WORD_ADDR : ald_flash.h
  • FLASH_WORD_MASK : ald_flash.h
  • FLASH_WORD_SIZE : ald_flash.h
  • FLASH_WORDEND_ADDR : ald_flash.h


ALD User Manual: Globals

- g -

  • GET_SYSCFG_LOCK : ald_syscfg.h
  • GPIO_PIN_0 : ald_gpio.h
  • GPIO_PIN_1 : ald_gpio.h
  • GPIO_PIN_10 : ald_gpio.h
  • GPIO_PIN_11 : ald_gpio.h
  • GPIO_PIN_12 : ald_gpio.h
  • GPIO_PIN_13 : ald_gpio.h
  • GPIO_PIN_14 : ald_gpio.h
  • GPIO_PIN_15 : ald_gpio.h
  • GPIO_PIN_2 : ald_gpio.h
  • GPIO_PIN_3 : ald_gpio.h
  • GPIO_PIN_4 : ald_gpio.h
  • GPIO_PIN_5 : ald_gpio.h
  • GPIO_PIN_6 : ald_gpio.h
  • GPIO_PIN_7 : ald_gpio.h
  • GPIO_PIN_8 : ald_gpio.h
  • GPIO_PIN_9 : ald_gpio.h
  • GPIO_PIN_ALL : ald_gpio.h


ALD User Manual: Globals

- i -

  • I2C_CLEAR_IT : ald_i2c.h
  • I2C_DISABLE : ald_i2c.h
  • I2C_DISABLE_IT : ald_i2c.h
  • I2C_ENABLE : ald_i2c.h
  • I2C_ENABLE_IT : ald_i2c.h
  • I2C_FLAG_MASK : ald_i2c.h
  • I2C_FREQ_RANGE : ald_i2c.h
  • I2C_GET_FLAG : ald_i2c.h
  • I2C_GET_IT_FLAG : ald_i2c.h
  • I2C_GET_IT_SOURCE : ald_i2c.h
  • I2C_MASTER_GET_DIR : ald_i2c.h
  • I2C_MAX_DELAY : ald_i2c.c
  • I2C_MEM_ADD_LSB : ald_i2c.h
  • I2C_MEM_ADD_MSB : ald_i2c.h
  • I2C_RESET_HANDLE_STATE : ald_i2c.h
  • I2C_SLAVE_GET_DIR : ald_i2c.h
  • I2C_TIMEOUT_ADDR_SLAVE : ald_i2c.c
  • I2C_TIMEOUT_BUSY_FLAG : ald_i2c.c
  • I2C_TIMEOUT_FLAG : ald_i2c.c
  • I2S_DISABLE : ald_i2s.h
  • I2S_ENABLE : ald_i2s.h
  • I2S_RESET_HANDLE_STATE : ald_i2s.h
  • IAP_DWP_ADDR : ald_iap.h
  • IAP_PE_ADDR : ald_iap.h
  • IAP_WP_ADDR : ald_iap.h
  • IAP_WSP_ADDR : ald_iap.h
  • IndexToUSBEP : ald_usb.h
  • INFO_PAGE_ADDR : ald_flash.h
  • INFO_PAGE_MASK : ald_flash.h
  • INFO_PAGE_SIZE : ald_flash.h
  • IS_4BYTES_ALIGN : ald_flash.h
  • IS_ACMP_EDGE_TYPE : ald_acmp.h
  • IS_ACMP_FLAG_TYPE : ald_acmp.h
  • IS_ACMP_HYSTSEL_TYPE : ald_acmp.h
  • IS_ACMP_INACTVAL_TYPE : ald_acmp.h
  • IS_ACMP_IT_TYPE : ald_acmp.h
  • IS_ACMP_MODE_TYPE : ald_acmp.h
  • IS_ACMP_NEG_INPUT_TYPE : ald_acmp.h
  • IS_ACMP_POS_INPUT_TYPE : ald_acmp.h
  • IS_ACMP_STATUS_TYPE : ald_acmp.h
  • IS_ACMP_TYPE : ald_acmp.h
  • IS_ACMP_WARM_UP_TIME_TYPE : ald_acmp.h
  • IS_ADC_ANALOG_WTD_MODE_TYPE : ald_adc.h
  • IS_ADC_CHANNELS_TYPE : ald_adc.h
  • IS_ADC_CLK_DIV_TYPE : ald_adc.h
  • IS_ADC_CONV_BIT_TYPE : ald_adc.h
  • IS_ADC_DATA_ALIGN_TYPE : ald_adc.h
  • IS_ADC_DISC_NR_TYPE : ald_adc.h
  • IS_ADC_EVENT_TYPE : ald_adc.h
  • IS_ADC_FLAGS_TYPE : ald_adc.h
  • IS_ADC_ICH_IDX_TYPE : ald_adc.h
  • IS_ADC_ICH_NR_TYPE : ald_adc.h
  • IS_ADC_IST_OFFSET_TYPE : ald_adc.h
  • IS_ADC_IT_TYPE : ald_adc.h
  • IS_ADC_NCH_IDX_TYPE : ald_adc.h
  • IS_ADC_NCH_NR_TYPE : ald_adc.h
  • IS_ADC_NCHESEL_MODE_TYPE : ald_adc.h
  • IS_ADC_NEG_REF_VOLTAGE_TYPE : ald_adc.h
  • IS_ADC_SAMPLING_TIMES_TYPE : ald_adc.h
  • IS_ADC_TYPE : ald_adc.h
  • IS_BIT_CLR : utils.h
  • IS_BIT_SET : utils.h
  • IS_BKPC_PREH_CLOCK : ald_bkpc.h
  • IS_BKPC_RAM_IDX : ald_bkpc.h
  • IS_BKPC_WAKEUP_LEVEL : ald_bkpc.h
  • IS_BKPC_WAKEUP_PORT : ald_bkpc.h
  • IS_CAN_ALL : ald_can.h
  • IS_CAN_BS1 : ald_can.h
  • IS_CAN_BS2 : ald_can.h
  • IS_CAN_CLEAR_FLAG : ald_can.h
  • IS_CAN_DATA_LEN : ald_can.h
  • IS_CAN_EXTID : ald_can.h
  • IS_CAN_FIFO : ald_can.h
  • IS_CAN_FILTER_FIFO : ald_can.h
  • IS_CAN_FILTER_MODE : ald_can.h
  • IS_CAN_FILTER_NUMBER : ald_can.h
  • IS_CAN_FILTER_SCALE : ald_can.h
  • IS_CAN_GET_FLAG : ald_can.h
  • IS_CAN_IDTYPE : ald_can.h
  • IS_CAN_IT : ald_can.h
  • IS_CAN_MODE : ald_can.h
  • IS_CAN_PRESCALER : ald_can.h
  • IS_CAN_RTR : ald_can.h
  • IS_CAN_SJW : ald_can.h
  • IS_CAN_STDID : ald_can.h
  • IS_CAN_TX_MAILBOX : ald_can.h
  • IS_CMU_BUS : ald_cmu.h
  • IS_CMU_BUZZ_DIV : ald_cmu.h
  • IS_CMU_CLOCK : ald_cmu.h
  • IS_CMU_CLOCK_STATE : ald_cmu.h
  • IS_CMU_DIV : ald_cmu.h
  • IS_CMU_HOSC_RANGE : ald_cmu.h
  • IS_CMU_LCD_CLOCK_SEL : ald_cmu.h
  • IS_CMU_LP_PERH_CLOCK_SEL : ald_cmu.h
  • IS_CMU_OUTPUT_HIGH_DIV : ald_cmu.h
  • IS_CMU_OUTPUT_HIGH_SEL : ald_cmu.h
  • IS_CMU_OUTPUT_LOW_SEL : ald_cmu.h
  • IS_CMU_PERH : ald_cmu.h
  • IS_CMU_PLL1_INPUT : ald_cmu.h
  • IS_CMU_QSPI_CLOCK_SEL : ald_cmu.h
  • IS_CMU_SAFE_CLOCK_TYPE : ald_cmu.h
  • IS_CMU_STOP1_CLOCK : ald_cmu.h
  • IS_CMU_USB_CLOCK_SEL : ald_cmu.h
  • IS_CMU_USB_DIV : ald_cmu.h
  • IS_CRC : ald_crc.h
  • IS_CRC_MODE : ald_crc.h
  • IS_CRYPT : ald_crypt.h
  • IS_CRYPT_FLAG : ald_crypt.h
  • IS_CRYPT_IT : ald_crypt.h
  • IS_CRYPT_IV_LEN : ald_crypt.h
  • IS_CRYPT_KEY_LEN : ald_crypt.h
  • IS_CRYPT_KS : ald_crypt.h
  • IS_CRYPT_MODE : ald_crypt.h
  • IS_CYCLECTRL_TYPE : ald_dma.h
  • IS_DAC_CHANNEL_TYPE : ald_dac.h
  • IS_DAC_CONVERT_TYPE : ald_dac.h
  • IS_DAC_FLAG_TYPE : ald_dac.h
  • IS_DAC_INTERRUPT_TYPE : ald_dac.h
  • IS_DAC_NEG_REFRESH_TYPE : ald_dac.h
  • IS_DAC_OUTPUT_TYPE : ald_dac.h
  • IS_DAC_PISSEL_CH_TYPE : ald_dac.h
  • IS_DAC_POS_REFRESH_TYPE : ald_dac.h
  • IS_DAC_PRESCALE_TYPE : ald_dac.h
  • IS_DAC_REFRESH_TYPE : ald_dac.h
  • IS_DAC_STATUS_TYPE : ald_dac.h
  • IS_DAC_TRIGGER_TYPE : ald_dac.h
  • IS_DAC_TYPE : ald_dac.h
  • IS_DMA : ald_dma.h
  • IS_DMA_ARBITERCONFIG_TYPE : ald_dma.h
  • IS_DMA_CHANNEL : ald_dma.h
  • IS_DMA_DATA_SIZE : ald_dma.h
  • IS_DMA_DATAINC_TYPE : ald_dma.h
  • IS_DMA_DATASIZE_TYPE : ald_dma.h
  • IS_DMA_IT_TYPE : ald_dma.h
  • IS_DMA_MSEL_TYPE : ald_dma.h
  • IS_DMA_MSIGSEL_TYPE : ald_dma.h
  • IS_EBI_ACCESS_MODE : ald_ebi.h
  • IS_EBI_ADDRESS_HOLD_TIME : ald_ebi.h
  • IS_EBI_ADDRESS_SETUP_TIME : ald_ebi.h
  • IS_EBI_ASYNWAIT : ald_ebi.h
  • IS_EBI_BANK_NUMBER : ald_ebi.h
  • IS_EBI_BURSTMODE : ald_ebi.h
  • IS_EBI_CLK_DIV : ald_ebi.h
  • IS_EBI_DATA_CLOCK : ald_ebi.h
  • IS_EBI_DATA_ENABLE : ald_ebi.h
  • IS_EBI_DATA_LATENCY : ald_ebi.h
  • IS_EBI_DATASETUP_TIME : ald_ebi.h
  • IS_EBI_ECC_STATE : ald_ebi.h
  • IS_EBI_ECCPAGE_SIZE : ald_ebi.h
  • IS_EBI_EXTENDED_MODE : ald_ebi.h
  • IS_EBI_FRAME_LINE_NUMBER : ald_ebi.h
  • IS_EBI_FRAME_PIXEL_NUMBER : ald_ebi.h
  • IS_EBI_HIZ_TIME : ald_ebi.h
  • IS_EBI_HOLD_TIME : ald_ebi.h
  • IS_EBI_HORIZONTAL_SYNCH : ald_ebi.h
  • IS_EBI_HYSNC_PULSE_WIDTH : ald_ebi.h
  • IS_EBI_LCD_DATASETUP_TIME : ald_ebi.h
  • IS_EBI_LCD_DEVICE : ald_ebi.h
  • IS_EBI_LCD_ENABLE : ald_ebi.h
  • IS_EBI_LCD_RESET : ald_ebi.h
  • IS_EBI_MEMORY : ald_ebi.h
  • IS_EBI_MUX : ald_ebi.h
  • IS_EBI_NAND_BANK : ald_ebi.h
  • IS_EBI_NAND_DEVICE : ald_ebi.h
  • IS_EBI_NAND_MEMORY_WIDTH : ald_ebi.h
  • IS_EBI_NORSRAM_BANK : ald_ebi.h
  • IS_EBI_NORSRAM_DEVICE : ald_ebi.h
  • IS_EBI_NORSRAM_EXTENDED_DEVICE : ald_ebi.h
  • IS_EBI_NORSRAM_MEMORY_WIDTH : ald_ebi.h
  • IS_EBI_SETUP_TIME : ald_ebi.h
  • IS_EBI_TAR_TIME : ald_ebi.h
  • IS_EBI_TCLR_TIME : ald_ebi.h
  • IS_EBI_TURNAROUND_TIME : ald_ebi.h
  • IS_EBI_VERTICAL_SYNCH : ald_ebi.h
  • IS_EBI_VSYNC_PULSE_WIDTH : ald_ebi.h
  • IS_EBI_WAIT_FEATURE : ald_ebi.h
  • IS_EBI_WAIT_POLARITY : ald_ebi.h
  • IS_EBI_WAIT_SIGNAL_ACTIVE : ald_ebi.h
  • IS_EBI_WAIT_TIME : ald_ebi.h
  • IS_EBI_WAITE_SIGNAL : ald_ebi.h
  • IS_EBI_WRAP_MODE : ald_ebi.h
  • IS_EBI_WRITE_BURST : ald_ebi.h
  • IS_EBI_WRITE_OPERATION : ald_ebi.h
  • IS_EXTI_FLTCKS_TYPE : ald_gpio.h
  • IS_FLASH_ADDRESS : ald_flash.h
  • IS_FUNC_STATE : ald_wdt.h , type.h
  • IS_GPIO_FLT : ald_gpio.h
  • IS_GPIO_FUNC : ald_gpio.h
  • IS_GPIO_MODE : ald_gpio.h
  • IS_GPIO_ODOS : ald_gpio.h
  • IS_GPIO_ODRV : ald_gpio.h
  • IS_GPIO_PIN : ald_gpio.h
  • IS_GPIO_PORT : ald_gpio.h
  • IS_GPIO_PUPD : ald_gpio.h
  • IS_GPIO_TYPE : ald_gpio.h
  • IS_HTR_TYPE : ald_adc.h
  • IS_I2C_ADDRESSING_MODE : ald_i2c.h
  • IS_I2C_CLOCK_SPEED : ald_i2c.h
  • IS_I2C_DUAL_ADDRESS : ald_i2c.h
  • IS_I2C_GENERAL_CALL : ald_i2c.h
  • IS_I2C_IT : ald_i2c.h
  • IS_I2C_MEMADD_size : ald_i2c.h
  • IS_I2C_MODULE : ald_i2c.h
  • IS_I2C_NO_STRETCH : ald_i2c.h
  • IS_I2C_TYPE : ald_i2c.h
  • IS_I2S : ald_i2s.h
  • IS_I2S_CH_LEN : ald_i2s.h
  • IS_I2S_CPOL : ald_i2s.h
  • IS_I2S_DATE_LEN : ald_i2s.h
  • IS_I2S_DMA_REQ : ald_i2s.h
  • IS_I2S_FLAG : ald_i2s.h
  • IS_I2S_IF : ald_i2s.h
  • IS_I2S_IT : ald_i2s.h
  • IS_I2S_PCMS : ald_i2s.h
  • IS_I2S_STANDARD : ald_i2s.h
  • IS_I2S_STATUS : ald_i2s.h
  • IS_LOCK_STATE : type.h
  • IS_LTR_TYPE : ald_adc.h
  • IS_PIS : ald_pis.h
  • IS_PIS_CLOCK : ald_pis.h
  • IS_PIS_EDGE : ald_pis.h
  • IS_PIS_MODU_CHANNEL : ald_pis.h
  • IS_PIS_MODU_LEVEL : ald_pis.h
  • IS_PIS_MODU_SRC : ald_pis.h
  • IS_PIS_MODU_TARGET : ald_pis.h
  • IS_PIS_OUPUT_CH : ald_pis.h
  • IS_PIS_OUTPUT : ald_pis.h
  • IS_PIS_SIGNAL_MODE : ald_pis.h
  • IS_PIS_SRC : ald_pis.h
  • IS_PIS_TRIG : ald_pis.h
  • IS_PMU_LDO18_MODE : ald_pmu.h
  • IS_PMU_LDO_LPMODE_OUTPUT : ald_pmu.h
  • IS_PMU_LP_MODE : ald_pmu.h
  • IS_PMU_LVD_TRIGGER_MODE : ald_pmu.h
  • IS_PMU_LVD_VOL_SEL : ald_pmu.h
  • IS_PMU_PERH_POWER : ald_pmu.h
  • IS_PMU_STATUS : ald_pmu.h
  • IS_POS_REF_VOLTAGE_TYPE : ald_adc.h
  • IS_PREEMPT_PRIO : utils.h
  • IS_QSPI_ADDR_SIZE : ald_qspi.h
  • IS_QSPI_ALL : ald_qspi.h
  • IS_QSPI_BLOCK_SIZE : ald_qspi.h
  • IS_QSPI_CLOCK_PHASE : ald_qspi.h
  • IS_QSPI_CLOCK_POLARITY : ald_qspi.h
  • IS_QSPI_CLOCK_PRESCALER : ald_qspi.h
  • IS_QSPI_DCYLES : ald_qspi.h
  • IS_QSPI_DDR_BIT_ENABLE : ald_qspi.h
  • IS_QSPI_DEVICE_DELAY_CCSOT : ald_qspi.h
  • IS_QSPI_DEVICE_DELAY_CSDA : ald_qspi.h
  • IS_QSPI_DEVICE_DELAY_CSDADS : ald_qspi.h
  • IS_QSPI_DEVICE_DELAY_CSEOT : ald_qspi.h
  • IS_QSPI_IF : ald_qspi.h
  • IS_QSPI_INDIRECT_READ_STATUS : ald_qspi.h
  • IS_QSPI_INDIRECT_READ_WATERMARK : ald_qspi.h
  • IS_QSPI_INDIRECT_SRAM_FILL_TYPE : ald_qspi.h
  • IS_QSPI_INDIRECT_TRIGGER_RANGE : ald_qspi.h
  • IS_QSPI_INDIRECT_WRITE_STATUS : ald_qspi.h
  • IS_QSPI_IT : ald_qspi.h
  • IS_QSPI_MODE_BIT_ENABLE : ald_qspi.h
  • IS_QSPI_NSS_SIZE : ald_qspi.h
  • IS_QSPI_PAGE_SIZE : ald_qspi.h
  • IS_QSPI_RD_OPCODE : ald_qspi.h
  • IS_QSPI_READ_DATA_CAPTURE_DELAY_READ : ald_qspi.h
  • IS_QSPI_READ_DATA_DELAY_TRANSMIT : ald_qspi.h
  • IS_QSPI_READ_DATA_SAMPLE_EDGE : ald_qspi.h
  • IS_QSPI_SRAM_PARTITION : ald_qspi.h
  • IS_QSPI_WR_OPCODE : ald_qspi.h
  • IS_QSPI_XFER_TYPE : ald_qspi.h
  • IS_RMU_BORFLT : ald_rmu.h
  • IS_RMU_BORVOL : ald_rmu.h
  • IS_RMU_PERH : ald_rmu.h
  • IS_RMU_STATE : ald_rmu.h
  • IS_RMU_STATE_CLEAR : ald_rmu.h
  • IS_RTC_ALARM : ald_rtc.h
  • IS_RTC_ALARM_MASK : ald_rtc.h
  • IS_RTC_ALARM_SEL : ald_rtc.h
  • IS_RTC_ALARM_SS_MASK : ald_rtc.h
  • IS_RTC_CALC_FREQ : ald_rtc.h
  • IS_RTC_CALI_CALC : ald_rtc.h
  • IS_RTC_CALI_FREQ : ald_rtc.h
  • IS_RTC_CALI_TC : ald_rtc.h
  • IS_RTC_CLOCK_OUTPUT : ald_rtc.h
  • IS_RTC_DAY : ald_rtc.h
  • IS_RTC_FORMAT : ald_rtc.h
  • IS_RTC_HOUR : ald_rtc.h
  • IS_RTC_HOUR_FORMAT : ald_rtc.h
  • IS_RTC_IF : ald_rtc.h
  • IS_RTC_IT : ald_rtc.h
  • IS_RTC_MINUTE : ald_rtc.h
  • IS_RTC_MONTH : ald_rtc.h
  • IS_RTC_OUTPUT_POLARITY : ald_rtc.h
  • IS_RTC_OUTPUT_SEL : ald_rtc.h
  • IS_RTC_SECOND : ald_rtc.h
  • IS_RTC_SOURCE_SEL : ald_rtc.h
  • IS_RTC_TAMPER : ald_rtc.h
  • IS_RTC_TAMPER_DURATION : ald_rtc.h
  • IS_RTC_TAMPER_SAMPLING_FREQ : ald_rtc.h
  • IS_RTC_TAMPER_TRIGGER : ald_rtc.h
  • IS_RTC_TS_SIGNAL : ald_rtc.h
  • IS_RTC_TS_STYLE : ald_rtc.h
  • IS_RTC_WAKEUP_CLOCK : ald_rtc.h
  • IS_RTC_YEAR : ald_rtc.h
  • IS_SHIFT_SUB_SS : ald_rtc.h
  • IS_SPI : ald_spi.h
  • IS_SPI_BAUD : ald_spi.h
  • IS_SPI_BIDMODE : ald_spi.h
  • IS_SPI_BIDOE : ald_spi.h
  • IS_SPI_CPHA : ald_spi.h
  • IS_SPI_CPOL : ald_spi.h
  • IS_SPI_DATASIZE : ald_spi.h
  • IS_SPI_DIRECTION : ald_spi.h
  • IS_SPI_DMA_REQ : ald_spi.h
  • IS_SPI_FIRBIT : ald_spi.h
  • IS_SPI_FRAME : ald_spi.h
  • IS_SPI_IF : ald_spi.h
  • IS_SPI_IT : ald_spi.h
  • IS_SPI_MODE : ald_spi.h
  • IS_SPI_STATUS : ald_spi.h
  • IS_SUB_PRIO : utils.h
  • IS_SYSTICK_INTERVAL : utils.h
  • IS_TIMER_BREAK_POLARITY : ald_timer.h
  • IS_TIMER_CHANNELS : ald_timer.h
  • IS_TIMER_CHNREF_CLEAR : ald_timer.h
  • IS_TIMER_CLEAR_INPUT_POLARITY : ald_timer.h
  • IS_TIMER_CLEAR_INPUT_SOURCE : ald_timer.h
  • IS_TIMER_CLOCK_DIVISION : ald_timer.h
  • IS_TIMER_CLOCK_LEVEL : ald_timer.h
  • IS_TIMER_CLOCK_POLARITY : ald_timer.h
  • IS_TIMER_CLOCK_SOURCE : ald_timer.h
  • IS_TIMER_COUNTER_MODE : ald_timer.h
  • IS_TIMER_DEAD_TIMERE : ald_timer.h
  • IS_TIMER_DMA_REQ : ald_timer.h
  • IS_TIMER_ENCODER_MODE : ald_timer.h
  • IS_TIMER_ETR_PSC : ald_timer.h
  • IS_TIMER_EVENT_SOURCE : ald_timer.h
  • IS_TIMER_FLAG : ald_timer.h
  • IS_TIMER_IC_FILTER : ald_timer.h
  • IS_TIMER_IC_POLARITY : ald_timer.h
  • IS_TIMER_IC_PSC : ald_timer.h
  • IS_TIMER_IC_SELECT : ald_timer.h
  • IS_TIMER_IT : ald_timer.h
  • IS_TIMER_MASTER_MODE_SEL : ald_timer.h
  • IS_TIMER_OC_MODE : ald_timer.h
  • IS_TIMER_OC_POLARITY : ald_timer.h
  • IS_TIMER_OCIDLE_STATE : ald_timer.h
  • IS_TIMER_OCN_POLARITY : ald_timer.h
  • IS_TIMER_OCNIDLE_STATE : ald_timer.h
  • IS_TIMER_OP_MODE : ald_timer.h
  • IS_TIMER_OP_OUTPUT_CH : ald_timer.h
  • IS_TIMER_PWM_MODE : ald_timer.h
  • IS_TIMER_SLAVE_MODE : ald_timer.h
  • IS_TIMER_TS : ald_timer.h
  • IS_TRIGGER_STYLE : ald_gpio.h
  • IS_TRNG_ADJC : ald_trng.h
  • IS_TRNG_DATA_WIDTH : ald_trng.h
  • IS_TRNG_FLAG : ald_trng.h
  • IS_TRNG_IT : ald_trng.h
  • IS_TRNG_SEED_TYPE : ald_trng.h
  • IS_TRNG_STATUS : ald_trng.h
  • IS_TRNG_T_START : ald_trng.h
  • IS_TSENSE_SOURCE_SEL : ald_tsense.h
  • IS_UART_ALL : ald_uart.h
  • IS_UART_AUTO_BAUD_MODE : ald_uart.h
  • IS_UART_BAUDRATE : ald_uart.h
  • IS_UART_DATA : ald_uart.h
  • IS_UART_DMA_REQ : ald_uart.h
  • IS_UART_HARDWARE_FLOW_CONTROL : ald_uart.h
  • IS_UART_IF : ald_uart.h
  • IS_UART_IT : ald_uart.h
  • IS_UART_LIN_BREAK_LEN : ald_uart.h
  • IS_UART_MODE : ald_uart.h
  • IS_UART_PARITY : ald_uart.h
  • IS_UART_RXFIFO_TYPE : ald_uart.h
  • IS_UART_SCARD : ald_uart.h
  • IS_UART_SCARD_CLK : ald_uart.h
  • IS_UART_STATUS : ald_uart.h
  • IS_UART_STOPBITS : ald_uart.h
  • IS_UART_TXFIFO_TYPE : ald_uart.h
  • IS_UART_WORD_LENGTH : ald_uart.h
  • IS_WWDT_WIN_TYPE : ald_wdt.h
  • IWDT_LOCK : ald_wdt.h
  • IWDT_UNLOCK : ald_wdt.h


ALD User Manual: Globals

- l -

  • LCDCTRL_CLEAR_MASK : ald_ebi.h


ALD User Manual: Globals

- m -

  • MAX_NAK_LIMIT : ald_usb.h
  • MAX_PACKET_SIZE_EP0 : ald_usb.h
  • MC_ADDRESS : ald_nor_lcd.h
  • MCU_CHIPID_ADDR : utils.h
  • MCU_UID0_ADDR : utils.h
  • MCU_UID1_ADDR : utils.h
  • MCU_UID2_ADDR : utils.h
  • MODIFY_REG : type.h


ALD User Manual: Globals

- n -

  • NAND_BUSY : ald_nand.h
  • NAND_CMD_AREA_A : ald_nand.h
  • NAND_CMD_AREA_B : ald_nand.h
  • NAND_CMD_AREA_C : ald_nand.h
  • NAND_CMD_AREA_TRUE1 : ald_nand.h
  • NAND_CMD_ERASE0 : ald_nand.h
  • NAND_CMD_ERASE1 : ald_nand.h
  • NAND_CMD_LOCK_STATUS : ald_nand.h
  • NAND_CMD_READID : ald_nand.h
  • NAND_CMD_RESET : ald_nand.h
  • NAND_CMD_STATUS : ald_nand.h
  • NAND_CMD_WRITE0 : ald_nand.h
  • NAND_CMD_WRITE_TRUE1 : ald_nand.h
  • NAND_DEVICE1 : ald_nand.h
  • NAND_DEVICE2 : ald_nand.h
  • NAND_ERROR : ald_nand.h
  • NAND_INVALID_ADDRESS : ald_nand.h
  • NAND_READY : ald_nand.h
  • NAND_TIMEOUT_ERROR : ald_nand.h
  • NAND_VALID_ADDRESS : ald_nand.h
  • NAND_WRITE_TIMEOUT : ald_nand.h
  • NOR_ADDR_SHIFT : ald_nor_lcd.h
  • NOR_CMD_ADDRESS_FIFTH : ald_nor_lcd.h
  • NOR_CMD_ADDRESS_FIRST : ald_nor_lcd.h
  • NOR_CMD_ADDRESS_FIRST_CFI : ald_nor_lcd.h
  • NOR_CMD_ADDRESS_FOURTH : ald_nor_lcd.h
  • NOR_CMD_ADDRESS_SECOND : ald_nor_lcd.h
  • NOR_CMD_ADDRESS_SIXTH : ald_nor_lcd.h
  • NOR_CMD_ADDRESS_THIRD : ald_nor_lcd.h
  • NOR_CMD_DATA_AUTO_SELECT : ald_nor_lcd.h
  • NOR_CMD_DATA_BLOCK_ERASE : ald_nor_lcd.h
  • NOR_CMD_DATA_BUFFER_AND_PROG : ald_nor_lcd.h
  • NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM : ald_nor_lcd.h
  • NOR_CMD_DATA_CFI : ald_nor_lcd.h
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH : ald_nor_lcd.h
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH : ald_nor_lcd.h
  • NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD : ald_nor_lcd.h
  • NOR_CMD_DATA_CHIP_ERASE : ald_nor_lcd.h
  • NOR_CMD_DATA_FIRST : ald_nor_lcd.h
  • NOR_CMD_DATA_PROGRAM : ald_nor_lcd.h
  • NOR_CMD_DATA_READ_RESET : ald_nor_lcd.h
  • NOR_CMD_DATA_SECOND : ald_nor_lcd.h
  • NOR_MASK_STATUS_DQ5 : ald_nor_lcd.h
  • NOR_MASK_STATUS_DQ6 : ald_nor_lcd.h
  • NOR_MEMORY_16B : ald_nor_lcd.h
  • NOR_MEMORY_8B : ald_nor_lcd.h
  • NOR_MEMORY_ADRESS1 : ald_nor_lcd.h
  • NOR_MEMORY_ADRESS2 : ald_nor_lcd.h
  • NOR_MEMORY_ADRESS3 : ald_nor_lcd.h
  • NOR_MEMORY_ADRESS4 : ald_nor_lcd.h
  • NOR_TMEOUT : ald_nor_lcd.h
  • NOR_WRITE : ald_nor_lcd.h
  • NUM_USB_EP : ald_usb.h


ALD User Manual: Globals

- p -

  • PATTR_CLEAR_MASK : ald_ebi.h
  • PCTRLR_CLEAR_MASK : ald_ebi.h
  • PER_MEM_BASE : type.h
  • PIN_MASK : ald_gpio.h
  • PMEMR_CLEAR_MASK : ald_ebi.h
  • PMU_FLASH_MODE_IDLE : ald_pmu.h
  • PMU_FLASH_MODE_WAIT : ald_pmu.h
  • PMU_GET_LVD_STATUS : ald_pmu.h
  • PMU_LPSTOP_DISABLE : ald_pmu.h
  • PMU_LPSTOP_ENABLE : ald_pmu.h
  • PMU_MTSTOP_DISABLE : ald_pmu.h
  • PMU_MTSTOP_ENABLE : ald_pmu.h
  • PMU_VREF_DISABLE : ald_pmu.h
  • PMU_VREF_ENABLE : ald_pmu.h


ALD User Manual: Globals

- q -

  • QSPI_AUTO_POLL_DISABLE : ald_qspi.h
  • QSPI_AUTO_POLL_ENABLE : ald_qspi.h
  • QSPI_CANCEL_INDIRECT_READ : ald_qspi.h
  • QSPI_DAC_DISABLE : ald_qspi.h
  • QSPI_DAC_ENABLE : ald_qspi.h
  • QSPI_DISABLE : ald_qspi.h
  • QSPI_DMA_DISABLE : ald_qspi.h
  • QSPI_DMA_ENABLE : ald_qspi.h
  • QSPI_ENABLE : ald_qspi.h
  • QSPI_LEGACY_SPI_DISABLE : ald_qspi.h
  • QSPI_LEGACY_SPI_ENABLE : ald_qspi.h
  • QSPI_MEMORY_ADDRESS : ald_qspi.h
  • QSPI_SRAM_DEPTH : ald_qspi.h
  • QSPI_SRAM_SIZE : ald_qspi.h
  • QSPI_TIMEOUT_DEFAULT_VALUE : ald_qspi.h
  • QSPI_WRITE_PROTECT_DISABLE : ald_qspi.h
  • QSPI_WRITE_PROTECT_ENABLE : ald_qspi.h


ALD User Manual: Globals

- r -

  • RAM_MEM_BASE : type.h
  • READ_BIT : type.h
  • READ_BITS : type.h
  • READ_REG : type.h
  • RESET_HANDLE_STATE : utils.h
  • RTC_BY_PASS_DISABLE : ald_rtc.h
  • RTC_BY_PASS_ENABLE : ald_rtc.h
  • RTC_CALI_LOCK : ald_rtc.h
  • RTC_CALI_UNLOCK : ald_rtc.h
  • RTC_LOCK : ald_rtc.h
  • RTC_SUMMER_TIME_DISABLE : ald_rtc.h
  • RTC_SUMMER_TIME_ENABLE : ald_rtc.h
  • RTC_TIMEOUT_VALUE : ald_rtc.h
  • RTC_UNLOCK : ald_rtc.h
  • RTC_WINTER_TIME_DISABLE : ald_rtc.h
  • RTC_WINTER_TIME_ENABLE : ald_rtc.h
  • RTCINFO : ald_rtchw.h


ALD User Manual: Globals

- s -

  • SET_BIT : type.h
  • SPI_1LINE_RX : ald_spi.h
  • SPI_1LINE_TX : ald_spi.h
  • SPI_CRC_RESET : ald_spi.h
  • SPI_CRCNEXT_DISABLE : ald_spi.h
  • SPI_CRCNEXT_ENABLE : ald_spi.h
  • SPI_DISABLE : ald_spi.h
  • SPI_ENABLE : ald_spi.h
  • SPI_RESET_HANDLE_STATE : ald_spi.h
  • SPI_RXONLY_DISABLE : ald_spi.h
  • SPI_RXONLY_ENABLE : ald_spi.h
  • SPI_SSI_HIGH : ald_spi.h
  • SPI_SSI_LOW : ald_spi.h
  • SPI_SSOE_DISABLE : ald_spi.h
  • SPI_SSOE_ENABLE : ald_spi.h
  • SYSCFG_BOOTFLASH_MAPPING_DISABLE : ald_syscfg.h
  • SYSCFG_BOOTFLASH_MAPPING_ENABLE : ald_syscfg.h
  • SYSCFG_LOCK : ald_syscfg.h
  • SYSCFG_UNLOCK : ald_syscfg.h


ALD User Manual: Globals

- t -

  • TICK_INT_PRIORITY : ald_conf.h
  • TIMER_CCx_DISABLE : ald_timer.h
  • TIMER_CCx_DMA_REQ_CCx : ald_timer.h
  • TIMER_CCx_DMA_REQ_UPDATE : ald_timer.h
  • TIMER_CCx_ENABLE : ald_timer.h
  • TIMER_CCxN_DISABLE : ald_timer.h
  • TIMER_CCxN_ENABLE : ald_timer.h
  • TIMER_DISABLE : ald_timer.h
  • TIMER_ENABLE : ald_timer.h
  • TIMER_GET_AUTORELOAD : ald_timer.h
  • TIMER_GET_CNT : ald_timer.h
  • TIMER_GET_DIR : ald_timer.h
  • TIMER_MOE_DISABLE : ald_timer.h
  • TIMER_MOE_ENABLE : ald_timer.h
  • TIMER_RESET_HANDLE_STATE : ald_timer.h
  • TIMER_SET_AUTORELOAD : ald_timer.h
  • TRNG_ADJM_DISABLE : ald_trng.h
  • TRNG_ADJM_ENABLE : ald_trng.h
  • TRNG_DISABLE : ald_trng.h
  • TRNG_ENABLE : ald_trng.h
  • TSENSE_CTN_DISABLE : ald_tsense.h
  • TSENSE_CTN_ENABLE : ald_tsense.h
  • TSENSE_DISABLE : ald_tsense.h
  • TSENSE_ENABLE : ald_tsense.h
  • TSENSE_HTGR_WR : ald_tsense.h
  • TSENSE_LOCK : ald_tsense.h , ald_rtchw.h
  • TSENSE_LTGR_WR : ald_tsense.h
  • TSENSE_REQ_DISABLE : ald_tsense.h
  • TSENSE_REQ_ENABLE : ald_tsense.h
  • TSENSE_RESET : ald_tsense.h
  • TSENSE_TBDR_WR : ald_tsense.h
  • TSENSE_TCALBDR_WR : ald_tsense.h
  • TSENSE_UNLOCK : ald_tsense.h , ald_rtchw.h


ALD User Manual: Globals

- u -

  • UART_AUTOBR_DISABLE : ald_uart.h
  • UART_AUTOBR_ENABLE : ald_uart.h
  • UART_AUTOBR_REPT : ald_uart.h
  • UART_DATA_INV_DISABLE : ald_uart.h
  • UART_DATA_INV_ENABLE : ald_uart.h
  • UART_DISABLE_SCARD_CLK : ald_uart.h
  • UART_DISABLE_SCARD_NACK : ald_uart.h
  • UART_ENABLE_SCARD_CLK : ald_uart.h
  • UART_ENABLE_SCARD_NACK : ald_uart.h
  • UART_FIFO_RX_RESET : ald_uart.h
  • UART_FIFO_TX_RESET : ald_uart.h
  • UART_GET_BRR_VALUE : ald_uart.h
  • UART_HDSEL_DISABLE : ald_uart.h
  • UART_HDSEL_ENABLE : ald_uart.h
  • UART_LPBMOD_DISABLE : ald_uart.h
  • UART_LPBMOD_ENABLE : ald_uart.h
  • UART_MSB_FIRST_DISABLE : ald_uart.h
  • UART_MSB_FIRST_ENABLE : ald_uart.h
  • UART_RX_DISABLE : ald_uart.h
  • UART_RX_ENABLE : ald_uart.h
  • UART_RX_INV_DISABLE : ald_uart.h
  • UART_RX_INV_ENABLE : ald_uart.h
  • UART_RX_TIMEOUT_DISABLE : ald_uart.h
  • UART_RX_TIMEOUT_ENABLE : ald_uart.h
  • UART_SCARD_DISABLE : ald_uart.h
  • UART_SCARD_ENABLE : ald_uart.h
  • UART_SET_TIMEOUT_VALUE : ald_uart.h
  • UART_STATE_RX_MASK : ald_uart.h
  • UART_STATE_TX_MASK : ald_uart.h
  • UART_TX_DISABLE : ald_uart.h
  • UART_TX_ENABLE : ald_uart.h
  • UART_TX_INV_DISABLE : ald_uart.h
  • UART_TX_INV_ENABLE : ald_uart.h
  • UART_TX_RX_SWAP_DISABLE : ald_uart.h
  • UART_TX_RX_SWAP_ENABLE : ald_uart.h
  • UNLOCK_KEY : ald_gpio.h
  • UNUSED : type.h
  • USB_CSRH0_DISPING : ald_usb.h
  • USB_CSRH0_DT : ald_usb.h
  • USB_CSRH0_DTWE : ald_usb.h
  • USB_CSRH0_FLUSH : ald_usb.h
  • USB_CSRL0_DATAEND : ald_usb.h
  • USB_CSRL0_ERROR : ald_usb.h
  • USB_CSRL0_NAKTO : ald_usb.h
  • USB_CSRL0_REQPKT : ald_usb.h
  • USB_CSRL0_RXRDY : ald_usb.h
  • USB_CSRL0_RXRDYC : ald_usb.h
  • USB_CSRL0_SETEND : ald_usb.h
  • USB_CSRL0_SETENDC : ald_usb.h
  • USB_CSRL0_SETUP : ald_usb.h
  • USB_CSRL0_STALL : ald_usb.h
  • USB_CSRL0_STALLED : ald_usb.h
  • USB_CSRL0_STATUS : ald_usb.h
  • USB_CSRL0_TXRDY : ald_usb.h
  • USB_DEV_EP0_IN_PKTPEND : ald_usb.h
  • USB_DEV_EP0_OUT_PKTRDY : ald_usb.h
  • USB_DEV_EP0_SENT_STALL : ald_usb.h
  • USB_DEV_EP0_SETUP_END : ald_usb.h
  • USB_DEV_LPM_EN : ald_usb.h
  • USB_DEV_LPM_EXTONLY : ald_usb.h
  • USB_DEV_LPM_LS_L1 : ald_usb.h
  • USB_DEV_LPM_LS_RMTWAKE : ald_usb.h
  • USB_DEV_LPM_NAK : ald_usb.h
  • USB_DEV_LPM_NONE : ald_usb.h
  • USB_DEV_RX_DATA_ERROR : ald_usb.h
  • USB_DEV_RX_FIFO_FULL : ald_usb.h
  • USB_DEV_RX_OVERRUN : ald_usb.h
  • USB_DEV_RX_PID_ERROR : ald_usb.h
  • USB_DEV_RX_PKT_RDY : ald_usb.h
  • USB_DEV_RX_SENT_STALL : ald_usb.h
  • USB_DEV_TX_FIFO_NE : ald_usb.h
  • USB_DEV_TX_NOT_COMP : ald_usb.h
  • USB_DEV_TX_SENT_STALL : ald_usb.h
  • USB_DEV_TX_TXPKTRDY : ald_usb.h
  • USB_DEV_TX_UNDERRUN : ald_usb.h
  • USB_DEVCTL_DEV : ald_usb.h
  • USB_DEVCTL_FSDEV : ald_usb.h
  • USB_DEVCTL_HOST : ald_usb.h
  • USB_DEVCTL_HOSTREQ : ald_usb.h
  • USB_DEVCTL_LSDEV : ald_usb.h
  • USB_DEVCTL_SESSION : ald_usb.h
  • USB_DEVCTL_VBUS_AVALID : ald_usb.h
  • USB_DEVCTL_VBUS_M : ald_usb.h
  • USB_DEVCTL_VBUS_NONE : ald_usb.h
  • USB_DEVCTL_VBUS_SEND : ald_usb.h
  • USB_DEVCTL_VBUS_VALID : ald_usb.h
  • USB_DMA_CFG_BURST_16 : ald_usb.h
  • USB_DMA_CFG_BURST_4 : ald_usb.h
  • USB_DMA_CFG_BURST_8 : ald_usb.h
  • USB_DMA_CFG_BURST_NONE : ald_usb.h
  • USB_DMA_CFG_DIR_RD : ald_usb.h
  • USB_DMA_CFG_DIR_WR : ald_usb.h
  • USB_DMA_CFG_EP_1 : ald_usb.h
  • USB_DMA_CFG_EP_2 : ald_usb.h
  • USB_DMA_CFG_EP_3 : ald_usb.h
  • USB_DMA_CFG_EP_4 : ald_usb.h
  • USB_DMA_CFG_EP_5 : ald_usb.h
  • USB_DMA_CFG_EP_MSK : ald_usb.h
  • USB_DMA_CFG_EP_POS : ald_usb.h
  • USB_DMA_CFG_IE_DIS : ald_usb.h
  • USB_DMA_CFG_IE_EN : ald_usb.h
  • USB_DMA_CFG_MODE_0 : ald_usb.h
  • USB_DMA_CFG_MODE_1 : ald_usb.h
  • USB_DMA_CFG_MODE_MSK : ald_usb.h
  • USB_DMA_CFG_START : ald_usb.h
  • USB_DMA_CFG_START_NO : ald_usb.h
  • USB_DMA_CH_ERR_MSK : ald_usb.h
  • USB_DMA_EP_CFG_RX_DEV : ald_usb.h
  • USB_DMA_EP_CFG_RX_HOST : ald_usb.h
  • USB_DMA_EP_CFG_TX : ald_usb.h
  • USB_DMA_EP_RX_DEV_MSK : ald_usb.h
  • USB_DMA_EP_RX_HOST_MSK : ald_usb.h
  • USB_DMA_EP_TX_MSK : ald_usb.h
  • USB_DMA_INT_CH1 : ald_usb.h
  • USB_DMA_INT_CH2 : ald_usb.h
  • USB_DMA_INT_CH3 : ald_usb.h
  • USB_DMA_INT_CH4 : ald_usb.h
  • USB_DMA_INT_CH5 : ald_usb.h
  • USB_DMA_INT_CH6 : ald_usb.h
  • USB_DMA_INT_CH7 : ald_usb.h
  • USB_DMA_INT_CH8 : ald_usb.h
  • USB_DMA_STATUS_ERROR : ald_usb.h
  • USB_DUAL_MODE_DEVICE : ald_usb.h
  • USB_DUAL_MODE_HOST : ald_usb.h
  • USB_DUAL_MODE_NONE : ald_usb.h
  • USB_EP_0 : ald_usb.h
  • USB_EP_1 : ald_usb.h
  • USB_EP_2 : ald_usb.h
  • USB_EP_3 : ald_usb.h
  • USB_EP_4 : ald_usb.h
  • USB_EP_5 : ald_usb.h
  • USB_EP_AUTO_CLEAR : ald_usb.h
  • USB_EP_AUTO_REQUEST : ald_usb.h
  • USB_EP_AUTO_SET : ald_usb.h
  • USB_EP_DEV_IN : ald_usb.h
  • USB_EP_DEV_OUT : ald_usb.h
  • USB_EP_DIS_NYET : ald_usb.h
  • USB_EP_DMA_MODE_0 : ald_usb.h
  • USB_EP_DMA_MODE_1 : ald_usb.h
  • USB_EP_HOST_IN : ald_usb.h
  • USB_EP_HOST_OUT : ald_usb.h
  • USB_EP_MODE_BULK : ald_usb.h
  • USB_EP_MODE_CTRL : ald_usb.h
  • USB_EP_MODE_INT : ald_usb.h
  • USB_EP_MODE_ISOC : ald_usb.h
  • USB_EP_MODE_MASK : ald_usb.h
  • USB_EP_SPEED_FULL : ald_usb.h
  • USB_EP_SPEED_HIGH : ald_usb.h
  • USB_EP_SPEED_LOW : ald_usb.h
  • USB_FIFO_SZ_1024 : ald_usb.h
  • USB_FIFO_SZ_128 : ald_usb.h
  • USB_FIFO_SZ_16 : ald_usb.h
  • USB_FIFO_SZ_2048 : ald_usb.h
  • USB_FIFO_SZ_256 : ald_usb.h
  • USB_FIFO_SZ_32 : ald_usb.h
  • USB_FIFO_SZ_512 : ald_usb.h
  • USB_FIFO_SZ_64 : ald_usb.h
  • USB_FIFO_SZ_8 : ald_usb.h
  • USB_FULL_SPEED : ald_usb.h
  • USB_HIGH_SPEED : ald_usb.h
  • USB_HOST_EP0_ERROR : ald_usb.h
  • USB_HOST_EP0_NAK_TO : ald_usb.h
  • USB_HOST_EP0_RX_STALL : ald_usb.h
  • USB_HOST_EP0_RXPKTRDY : ald_usb.h
  • USB_HOST_EP0_STATUS : ald_usb.h
  • USB_HOST_IN_DATA_ERROR : ald_usb.h
  • USB_HOST_IN_ERROR : ald_usb.h
  • USB_HOST_IN_FIFO_FULL : ald_usb.h
  • USB_HOST_IN_NAK_TO : ald_usb.h
  • USB_HOST_IN_NOT_COMP : ald_usb.h
  • USB_HOST_IN_PID_ERROR : ald_usb.h
  • USB_HOST_IN_PKTRDY : ald_usb.h
  • USB_HOST_IN_STALL : ald_usb.h
  • USB_HOST_IN_STATUS : ald_usb.h
  • USB_HOST_LPM_L1 : ald_usb.h
  • USB_HOST_LPM_RMTWAKE : ald_usb.h
  • USB_HOST_OUT_ERROR : ald_usb.h
  • USB_HOST_OUT_FIFO_NE : ald_usb.h
  • USB_HOST_OUT_NAK_TO : ald_usb.h
  • USB_HOST_OUT_NOT_COMP : ald_usb.h
  • USB_HOST_OUT_PKTPEND : ald_usb.h
  • USB_HOST_OUT_STALL : ald_usb.h
  • USB_HOST_OUT_STATUS : ald_usb.h
  • USB_HOST_PWREN_AUTOHIGH : ald_usb.h
  • USB_HOST_PWREN_AUTOLOW : ald_usb.h
  • USB_HOST_PWREN_FILTER : ald_usb.h
  • USB_HOST_PWREN_MAN_HIGH : ald_usb.h
  • USB_HOST_PWREN_MAN_LOW : ald_usb.h
  • USB_HOST_PWRFLT_EP_HIGH : ald_usb.h
  • USB_HOST_PWRFLT_EP_LOW : ald_usb.h
  • USB_HOST_PWRFLT_EP_NONE : ald_usb.h
  • USB_HOST_PWRFLT_EP_TRI : ald_usb.h
  • USB_HOST_PWRFLT_HIGH : ald_usb.h
  • USB_HOST_PWRFLT_LOW : ald_usb.h
  • USB_INTCTRL_ALL : ald_usb.h
  • USB_INTCTRL_BABBLE : ald_usb.h
  • USB_INTCTRL_CONNECT : ald_usb.h
  • USB_INTCTRL_DISCONNECT : ald_usb.h
  • USB_INTCTRL_MODE_DETECT : ald_usb.h
  • USB_INTCTRL_POWER_FAULT : ald_usb.h
  • USB_INTCTRL_RESET : ald_usb.h
  • USB_INTCTRL_RESUME : ald_usb.h
  • USB_INTCTRL_SESSION : ald_usb.h
  • USB_INTCTRL_SESSION_END : ald_usb.h
  • USB_INTCTRL_SOF : ald_usb.h
  • USB_INTCTRL_STATUS : ald_usb.h
  • USB_INTCTRL_SUSPEND : ald_usb.h
  • USB_INTCTRL_VBUS_ERR : ald_usb.h
  • USB_INTEP_0 : ald_usb.h
  • USB_INTEP_ALL : ald_usb.h
  • USB_INTEP_DEV_IN : ald_usb.h
  • USB_INTEP_DEV_IN_1 : ald_usb.h
  • USB_INTEP_DEV_IN_10 : ald_usb.h
  • USB_INTEP_DEV_IN_11 : ald_usb.h
  • USB_INTEP_DEV_IN_12 : ald_usb.h
  • USB_INTEP_DEV_IN_13 : ald_usb.h
  • USB_INTEP_DEV_IN_14 : ald_usb.h
  • USB_INTEP_DEV_IN_15 : ald_usb.h
  • USB_INTEP_DEV_IN_2 : ald_usb.h
  • USB_INTEP_DEV_IN_3 : ald_usb.h
  • USB_INTEP_DEV_IN_4 : ald_usb.h
  • USB_INTEP_DEV_IN_5 : ald_usb.h
  • USB_INTEP_DEV_IN_6 : ald_usb.h
  • USB_INTEP_DEV_IN_7 : ald_usb.h
  • USB_INTEP_DEV_IN_8 : ald_usb.h
  • USB_INTEP_DEV_IN_9 : ald_usb.h
  • USB_INTEP_DEV_OUT : ald_usb.h
  • USB_INTEP_DEV_OUT_1 : ald_usb.h
  • USB_INTEP_DEV_OUT_10 : ald_usb.h
  • USB_INTEP_DEV_OUT_11 : ald_usb.h
  • USB_INTEP_DEV_OUT_12 : ald_usb.h
  • USB_INTEP_DEV_OUT_13 : ald_usb.h
  • USB_INTEP_DEV_OUT_14 : ald_usb.h
  • USB_INTEP_DEV_OUT_15 : ald_usb.h
  • USB_INTEP_DEV_OUT_2 : ald_usb.h
  • USB_INTEP_DEV_OUT_3 : ald_usb.h
  • USB_INTEP_DEV_OUT_4 : ald_usb.h
  • USB_INTEP_DEV_OUT_5 : ald_usb.h
  • USB_INTEP_DEV_OUT_6 : ald_usb.h
  • USB_INTEP_DEV_OUT_7 : ald_usb.h
  • USB_INTEP_DEV_OUT_8 : ald_usb.h
  • USB_INTEP_DEV_OUT_9 : ald_usb.h
  • USB_INTEP_HOST_IN : ald_usb.h
  • USB_INTEP_HOST_IN_1 : ald_usb.h
  • USB_INTEP_HOST_IN_10 : ald_usb.h
  • USB_INTEP_HOST_IN_11 : ald_usb.h
  • USB_INTEP_HOST_IN_12 : ald_usb.h
  • USB_INTEP_HOST_IN_13 : ald_usb.h
  • USB_INTEP_HOST_IN_14 : ald_usb.h
  • USB_INTEP_HOST_IN_15 : ald_usb.h
  • USB_INTEP_HOST_IN_2 : ald_usb.h
  • USB_INTEP_HOST_IN_3 : ald_usb.h
  • USB_INTEP_HOST_IN_4 : ald_usb.h
  • USB_INTEP_HOST_IN_5 : ald_usb.h
  • USB_INTEP_HOST_IN_6 : ald_usb.h
  • USB_INTEP_HOST_IN_7 : ald_usb.h
  • USB_INTEP_HOST_IN_8 : ald_usb.h
  • USB_INTEP_HOST_IN_9 : ald_usb.h
  • USB_INTEP_HOST_OUT : ald_usb.h
  • USB_INTEP_HOST_OUT_1 : ald_usb.h
  • USB_INTEP_HOST_OUT_10 : ald_usb.h
  • USB_INTEP_HOST_OUT_11 : ald_usb.h
  • USB_INTEP_HOST_OUT_12 : ald_usb.h
  • USB_INTEP_HOST_OUT_13 : ald_usb.h
  • USB_INTEP_HOST_OUT_14 : ald_usb.h
  • USB_INTEP_HOST_OUT_15 : ald_usb.h
  • USB_INTEP_HOST_OUT_2 : ald_usb.h
  • USB_INTEP_HOST_OUT_3 : ald_usb.h
  • USB_INTEP_HOST_OUT_4 : ald_usb.h
  • USB_INTEP_HOST_OUT_5 : ald_usb.h
  • USB_INTEP_HOST_OUT_6 : ald_usb.h
  • USB_INTEP_HOST_OUT_7 : ald_usb.h
  • USB_INTEP_HOST_OUT_8 : ald_usb.h
  • USB_INTEP_HOST_OUT_9 : ald_usb.h
  • USB_INTEP_RX_SHIFT : ald_usb.h
  • USB_INTLPM_ACK : ald_usb.h
  • USB_INTLPM_ERROR : ald_usb.h
  • USB_INTLPM_INCOMPLETE : ald_usb.h
  • USB_INTLPM_NYET : ald_usb.h
  • USB_INTLPM_RESUME : ald_usb.h
  • USB_INTLPM_STALL : ald_usb.h
  • USB_LOW_SPEED : ald_usb.h
  • USB_LPMATTR_ENDPT_M : ald_usb.h
  • USB_LPMATTR_ENDPT_S : ald_usb.h
  • USB_LPMATTR_HIRD_M : ald_usb.h
  • USB_LPMATTR_HIRD_S : ald_usb.h
  • USB_LPMATTR_LS_L1 : ald_usb.h
  • USB_LPMATTR_LS_M : ald_usb.h
  • USB_LPMATTR_RMTWAK : ald_usb.h
  • USB_LPMCNTRL_DISABLE : ald_usb.h
  • USB_LPMCNTRL_ENABLE : ald_usb.h
  • USB_LPMCNTRL_LPMRES : ald_usb.h
  • USB_LPMCNTRL_LPMXMT : ald_usb.h
  • USB_MODE_DEV : ald_usb.h
  • USB_MODE_DEV_VBUS : ald_usb.h
  • USB_MODE_HOST : ald_usb.h
  • USB_MODE_HOST_VBUS : ald_usb.h
  • USB_MODE_OTG : ald_usb.h
  • USB_OTG_MODE_ASIDE_AVAL : ald_usb.h
  • USB_OTG_MODE_ASIDE_DEV : ald_usb.h
  • USB_OTG_MODE_ASIDE_HOST : ald_usb.h
  • USB_OTG_MODE_ASIDE_NPWR : ald_usb.h
  • USB_OTG_MODE_ASIDE_SESS : ald_usb.h
  • USB_OTG_MODE_BSIDE_DEV : ald_usb.h
  • USB_OTG_MODE_BSIDE_HOST : ald_usb.h
  • USB_OTG_MODE_BSIDE_NPWR : ald_usb.h
  • USB_OTG_MODE_NONE : ald_usb.h
  • USB_POWER_HS_EN : ald_usb.h
  • USB_POWER_HS_M : ald_usb.h
  • USB_POWER_ISOUP : ald_usb.h
  • USB_POWER_PWRDNPHY : ald_usb.h
  • USB_POWER_RESET : ald_usb.h
  • USB_POWER_RESUME : ald_usb.h
  • USB_POWER_SOFTCONN : ald_usb.h
  • USB_POWER_SUSPEND : ald_usb.h
  • USB_RX_EPSTATUS_SHIFT : ald_usb.h
  • USB_RXCSRH1_AUTOCL : ald_usb.h
  • USB_RXCSRH1_AUTORQ : ald_usb.h
  • USB_RXCSRH1_DISNYET : ald_usb.h
  • USB_RXCSRH1_DMAEN : ald_usb.h
  • USB_RXCSRH1_DMAMOD : ald_usb.h
  • USB_RXCSRH1_DT : ald_usb.h
  • USB_RXCSRH1_DTWE : ald_usb.h
  • USB_RXCSRH1_INCOMPRX : ald_usb.h
  • USB_RXCSRH1_ISO : ald_usb.h
  • USB_RXCSRH1_PIDERR : ald_usb.h
  • USB_RXCSRL1_CLRDT : ald_usb.h
  • USB_RXCSRL1_DATAERR : ald_usb.h
  • USB_RXCSRL1_ERROR : ald_usb.h
  • USB_RXCSRL1_FLUSH : ald_usb.h
  • USB_RXCSRL1_FULL : ald_usb.h
  • USB_RXCSRL1_NAKTO : ald_usb.h
  • USB_RXCSRL1_OVER : ald_usb.h
  • USB_RXCSRL1_REQPKT : ald_usb.h
  • USB_RXCSRL1_RXRDY : ald_usb.h
  • USB_RXCSRL1_STALL : ald_usb.h
  • USB_RXCSRL1_STALLED : ald_usb.h
  • USB_TRANS_IN : ald_usb.h
  • USB_TRANS_IN_LAST : ald_usb.h
  • USB_TRANS_OUT : ald_usb.h
  • USB_TRANS_SETUP : ald_usb.h
  • USB_TRANS_STATUS : ald_usb.h
  • USB_TXCSRH1_AUTOSET : ald_usb.h
  • USB_TXCSRH1_DMAEN : ald_usb.h
  • USB_TXCSRH1_DMAMOD : ald_usb.h
  • USB_TXCSRH1_DT : ald_usb.h
  • USB_TXCSRH1_DTWE : ald_usb.h
  • USB_TXCSRH1_FDT : ald_usb.h
  • USB_TXCSRH1_ISO : ald_usb.h
  • USB_TXCSRH1_MODE : ald_usb.h
  • USB_TXCSRL1_CLRDT : ald_usb.h
  • USB_TXCSRL1_ERROR : ald_usb.h
  • USB_TXCSRL1_FIFONE : ald_usb.h
  • USB_TXCSRL1_FLUSH : ald_usb.h
  • USB_TXCSRL1_NAKTO : ald_usb.h
  • USB_TXCSRL1_SETUP : ald_usb.h
  • USB_TXCSRL1_STALL : ald_usb.h
  • USB_TXCSRL1_STALLED : ald_usb.h
  • USB_TXCSRL1_TXRDY : ald_usb.h
  • USB_TXCSRL1_UNDRN : ald_usb.h
  • USB_TXTYPE1_PROTO_BULK : ald_usb.h
  • USB_TXTYPE1_PROTO_CTRL : ald_usb.h
  • USB_TXTYPE1_PROTO_INT : ald_usb.h
  • USB_TXTYPE1_PROTO_ISOC : ald_usb.h
  • USB_TXTYPE1_PROTO_M : ald_usb.h
  • USB_TXTYPE1_SPEED_DFLT : ald_usb.h
  • USB_TXTYPE1_SPEED_FULL : ald_usb.h
  • USB_TXTYPE1_SPEED_HIGH : ald_usb.h
  • USB_TXTYPE1_SPEED_LOW : ald_usb.h
  • USB_TXTYPE1_SPEED_M : ald_usb.h
  • USB_TXTYPE1_TEP_M : ald_usb.h
  • USB_TXTYPE1_TEP_S : ald_usb.h
  • USB_TYPE0_SPEED_FULL : ald_usb.h
  • USB_TYPE0_SPEED_HIGH : ald_usb.h
  • USB_TYPE0_SPEED_LOW : ald_usb.h
  • USB_TYPE0_SPEED_M : ald_usb.h
  • USB_UNDEF_SPEED : ald_usb.h
  • USBEPToIndex : ald_usb.h
  • USBFIFOSizeToBytes : ald_usb.h


ALD User Manual: Globals

- w -

  • WRITE_REG : type.h
  • WWDT_LOCK : ald_wdt.h
  • WWDT_UNLOCK : ald_wdt.h


ALD User Manual: D:/svn/src/ald_acmp.c Source File

  • D:
  • svn
  • src
ald_acmp.c
Go to the documentation of this file.
1
17 #include "ald_acmp.h"
18
27 #ifdef ALD_ACMP
28
45 ald_status_t ald_acmp_init(acmp_handle_t *hperh)
46 {
47 uint32_t tmp = 0;
48
49 assert_param(IS_ACMP_TYPE(hperh->perh));
50 assert_param(IS_ACMP_MODE_TYPE(hperh->init.mode));
51 assert_param(IS_ACMP_WARM_UP_TIME_TYPE(hperh->init.warm_time));
52 assert_param(IS_ACMP_HYSTSEL_TYPE(hperh->init.hystsel));
53 assert_param(IS_ACMP_POS_INPUT_TYPE(hperh->init.p_port));
54 assert_param(IS_ACMP_NEG_INPUT_TYPE(hperh->init.n_port));
55 assert_param(IS_ACMP_INACTVAL_TYPE(hperh->init.inactval));
56 assert_param(IS_FUNC_STATE(hperh->init.out_inv));
57 assert_param(IS_ACMP_EDGE_TYPE(hperh->init.edge));
58 assert_param(hperh->init.vdd_level < 64);
59
60 __LOCK(hperh);
61 tmp = ((hperh->init.mode << ACMP_CON_MODSEL_POSS) | (hperh->init.warm_time << ACMP_CON_WARMUPT_POSS) |
62 (hperh->init.inactval << ACMP_CON_INACTV_POS) | (hperh->init.hystsel << ACMP_CON_HYSTSEL_POSS));
63
64 hperh->perh->CON = tmp;
65
66 tmp |= ((hperh->init.p_port << ACMP_INPUTSEL_PSEL_POSS) | (hperh->init.n_port << ACMP_INPUTSEL_NSEL_POSS) |
67 (hperh->init.vdd_level << ACMP_INPUTSEL_VDDLVL_POSS));
68 hperh->perh->INPUTSEL = tmp;
69
70 if (hperh->init.out_inv)
71 SET_BIT(hperh->perh->CON, ACMP_CON_OUTINV_MSK);
72 else
73 CLEAR_BIT(hperh->perh->CON, ACMP_CON_OUTINV_MSK);
74
75 switch (hperh->init.edge) {
76 case ACMP_EDGE_NONE:
77 CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
78 CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
79 break;
80
81 case ACMP_EDGE_FALL:
82 SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
83 CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
84 break;
85
86 case ACMP_EDGE_RISE:
87 CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
88 SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
89 break;
90
91 case ACMP_EDGE_ALL:
92 SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
93 SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
94 break;
95
96 default:
97 break;
98 }
99
100 SET_BIT(hperh->perh->CON, ACMP_CON_EN_MSK);
101
102 tmp = 0;
103 while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0) {
104 if (tmp++ >= 600000) {
105 __UNLOCK(hperh);
106 return ERROR;
107 }
108 }
109
110 __UNLOCK(hperh);
111 return OK;
112 }
133 void ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state)
134 {
135 assert_param(IS_ACMP_TYPE(hperh->perh));
136 assert_param(IS_ACMP_IT_TYPE(it));
137 assert_param(IS_FUNC_STATE(state));
138
139 if (state)
140 hperh->perh->IES = it;
141 else
142 hperh->perh->IEC = it;
143
144 return;
145 }
146
157 it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it)
158 {
159 assert_param(IS_ACMP_TYPE(hperh->perh));
160 assert_param(IS_ACMP_IT_TYPE(it));
161
162 if (hperh->perh->IEV & it)
163 return SET;
164
165 return RESET;
166 }
167
178 flag_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
179 {
180 assert_param(IS_ACMP_TYPE(hperh->perh));
181 assert_param(IS_ACMP_FLAG_TYPE(flag));
182
183 if (hperh->perh->RIF & flag)
184 return SET;
185
186 return RESET;
187 }
188
198 flag_status_t ald_acmp_get_mask_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
199 {
200 assert_param(IS_ACMP_TYPE(hperh->perh));
201 assert_param(IS_ACMP_FLAG_TYPE(flag));
202
203 if (hperh->perh->IFM & flag)
204 return SET;
205
206 return RESET;
207 }
208
216 void ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
217 {
218 assert_param(IS_ACMP_TYPE(hperh->perh));
219 assert_param(IS_ACMP_FLAG_TYPE(flag));
220
221 hperh->perh->IFC = flag;
222 return;
223 }
237 void ald_acmp_irq_handler(acmp_handle_t *hperh)
238 {
239 if ((ald_acmp_get_mask_flag_status(hperh, ACMP_FLAG_WARMUP)) == SET) {
240 ald_acmp_clear_flag_status(hperh, ACMP_FLAG_WARMUP);
241
242 if (hperh->acmp_warmup_cplt_cbk)
243 hperh->acmp_warmup_cplt_cbk(hperh);
244 }
245
246 if ((ald_acmp_get_mask_flag_status(hperh, ACMP_FLAG_EDGE)) == SET) {
247 ald_acmp_clear_flag_status(hperh, ACMP_FLAG_EDGE);
248
249 if (hperh->acmp_edge_cplt_cbk)
250 hperh->acmp_edge_cplt_cbk(hperh);
251 }
252
253 return;
254 }
255
263 void ald_acmp_out_config(acmp_handle_t *hperh, type_func_t state)
264 {
265 assert_param(IS_ACMP_TYPE(hperh->perh));
266 assert_param(IS_FUNC_STATE(state));
267
268 if (state)
269 SET_BIT(hperh->perh->PORT, ACMP_PORT_PEN_MSK);
270 else
271 CLEAR_BIT(hperh->perh->PORT, ACMP_PORT_PEN_MSK);
272
273 return;
274 }
275
282 uint8_t ald_acmp_out_result(acmp_handle_t *hperh)
283 {
284 assert_param(IS_ACMP_TYPE(hperh->perh));
285
286 return (READ_BIT(hperh->perh->STAT, ACMP_STAT_OUT_MSK) >> ACMP_STAT_OUT_POS);
287 }
288
298 flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status)
299 {
300 assert_param(IS_ACMP_TYPE(hperh->perh));
301 assert_param(IS_ACMP_STATUS_TYPE(status));
302
303 if (hperh->perh->STAT & status)
304 return SET;
305
306 return RESET;
307 }
314 #endif /* ALD_ACMP */
315
ACMP_EDGE_NONE
Definition: ald_acmp.h:143
IS_ACMP_STATUS_TYPE
#define IS_ACMP_STATUS_TYPE(x)
Definition: ald_acmp.h:210
acmp_init_t::p_port
acmp_pos_input_t p_port
Definition: ald_acmp.h:164
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_ACMP_IT_TYPE
#define IS_ACMP_IT_TYPE(x)
Definition: ald_acmp.h:206
SET
Definition: type.h:39
ald_acmp_init
ald_status_t ald_acmp_init(acmp_handle_t *hperh)
Initializes the ACMP mode according to the specified parameters in the acmp_init_t and create the ass...
Definition: ald_acmp.c:45
ACMP_EDGE_RISE
Definition: ald_acmp.h:145
type_func_t
type_func_t
Definition: type.h:47
IS_ACMP_WARM_UP_TIME_TYPE
#define IS_ACMP_WARM_UP_TIME_TYPE(x)
Definition: ald_acmp.h:231
acmp_init_t::n_port
acmp_neg_input_t n_port
Definition: ald_acmp.h:165
acmp_handle_s::perh
ACMP_TypeDef * perh
Definition: ald_acmp.h:176
IS_ACMP_MODE_TYPE
#define IS_ACMP_MODE_TYPE(x)
Definition: ald_acmp.h:202
ald_acmp_get_status
flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status)
Check whether the specified ACMP flag is set or not.
Definition: ald_acmp.c:298
IS_ACMP_NEG_INPUT_TYPE
#define IS_ACMP_NEG_INPUT_TYPE(x)
Definition: ald_acmp.h:220
RESET
Definition: type.h:38
ald_acmp_out_result
uint8_t ald_acmp_out_result(acmp_handle_t *hperh)
This function output acmp result.
Definition: ald_acmp.c:282
acmp_init_t::mode
acmp_mode_t mode
Definition: ald_acmp.h:161
acmp_init_t::out_inv
type_func_t out_inv
Definition: ald_acmp.h:167
ald_acmp_clear_flag_status
void ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
Clear the specified ACMP it flags.
Definition: ald_acmp.c:216
it_status_t
enum flag_status_t it_status_t
ald_acmp_out_config
void ald_acmp_out_config(acmp_handle_t *hperh, type_func_t state)
This function config acmp output.
Definition: ald_acmp.c:263
IS_ACMP_FLAG_TYPE
#define IS_ACMP_FLAG_TYPE(x)
Definition: ald_acmp.h:208
ald_acmp_get_flag_status
flag_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
Checks whether the specified ACMP interrupt has occurred or not.
Definition: ald_acmp.c:178
ald_acmp_interrupt_config
void ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state)
Enables or disables the specified ACMP interrupts.
Definition: ald_acmp.c:133
acmp_it_t
acmp_it_t
ACMP interrupt.
Definition: ald_acmp.h:41
acmp_flag_t
acmp_flag_t
ACMP interrupt flag.
Definition: ald_acmp.h:49
acmp_init_t::hystsel
acmp_hystsel_t hystsel
Definition: ald_acmp.h:163
IS_ACMP_POS_INPUT_TYPE
#define IS_ACMP_POS_INPUT_TYPE(x)
Definition: ald_acmp.h:212
ald_acmp_get_mask_flag_status
flag_status_t ald_acmp_get_mask_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
Get the status of interrupt flag and interupt source.
Definition: ald_acmp.c:198
ACMP_EDGE_ALL
Definition: ald_acmp.h:146
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
ald_acmp.h
Header file of ACMP module driver.
acmp_handle_s::init
acmp_init_t init
Definition: ald_acmp.h:177
ald_acmp_get_it_status
it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it)
Checks whether the specified ACMP interrupt has set or not.
Definition: ald_acmp.c:157
ACMP_FLAG_WARMUP
Definition: ald_acmp.h:51
acmp_handle_s::acmp_warmup_cplt_cbk
void(* acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg)
Definition: ald_acmp.h:180
acmp_handle_s::acmp_edge_cplt_cbk
void(* acmp_edge_cplt_cbk)(struct acmp_handle_s *arg)
Definition: ald_acmp.h:181
ACMP_EDGE_FALL
Definition: ald_acmp.h:144
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_ACMP_TYPE
#define IS_ACMP_TYPE(x)
Definition: ald_acmp.h:199
IS_ACMP_INACTVAL_TYPE
#define IS_ACMP_INACTVAL_TYPE(x)
Definition: ald_acmp.h:247
IS_ACMP_HYSTSEL_TYPE
#define IS_ACMP_HYSTSEL_TYPE(x)
Definition: ald_acmp.h:239
IS_ACMP_EDGE_TYPE
#define IS_ACMP_EDGE_TYPE(x)
Definition: ald_acmp.h:249
flag_status_t
flag_status_t
Definition: type.h:37
acmp_init_t::edge
acmp_edge_t edge
Definition: ald_acmp.h:168
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
acmp_init_t::warm_time
acmp_warm_time_t warm_time
Definition: ald_acmp.h:162
acmp_init_t::vdd_level
uint8_t vdd_level
Definition: ald_acmp.h:169
__LOCK
#define __LOCK(x)
Definition: utils.h:92
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
ERROR
Definition: utils.h:56
ald_acmp_irq_handler
void ald_acmp_irq_handler(acmp_handle_t *hperh)
This function handles ACMP interrupt request.
Definition: ald_acmp.c:237
ACMP_FLAG_EDGE
Definition: ald_acmp.h:50
acmp_handle_s
ACMP Handle Structure definition.
Definition: ald_acmp.h:175
acmp_init_t::inactval
acmp_inactval_t inactval
Definition: ald_acmp.h:166
acmp_status_t
acmp_status_t
ACMP status flag.
Definition: ald_acmp.h:57


ALD User Manual: D:/svn/src/ald_acmp.h Source File

  • D:
  • svn
  • src
ald_acmp.h
Go to the documentation of this file.
1
17 #ifndef __ALD_ACMP_H__
18 #define __ALD_ACMP_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25
41 typedef enum {
42 ACMP_IT_EDGE = (1U << 0),
43 ACMP_IT_WARMUP = (1U << 1),
44 } acmp_it_t;
45
49 typedef enum {
50 ACMP_FLAG_EDGE = (1U << 0),
51 ACMP_FLAG_WARMUP = (1U << 1),
52 } acmp_flag_t;
53
57 typedef enum {
58 ACMP_STATUS_ACT = (1U << 0),
59 ACMP_STATUS_OUT = (1U << 1),
60 } acmp_status_t;
61
65 typedef enum {
66 ACMP_POS_CH0 = 0x0U,
67 ACMP_POS_CH1 = 0x1U,
68 ACMP_POS_CH2 = 0x2U,
69 ACMP_POS_CH3 = 0x3U,
70 ACMP_POS_CH4 = 0x4U,
71 ACMP_POS_CH5 = 0x5U,
72 ACMP_POS_CH6 = 0x6U,
73 ACMP_POS_CH7 = 0x7U,
74 } acmp_pos_input_t;
75
79 typedef enum {
80 ACMP_NEG_CH0 = 0x0U,
81 ACMP_NEG_CH1 = 0x1U,
82 ACMP_NEG_CH2 = 0x2U,
83 ACMP_NEG_CH3 = 0x3U,
84 ACMP_NEG_CH4 = 0x4U,
85 ACMP_NEG_CH5 = 0x5U,
86 ACMP_NEG_CH6 = 0x6U,
87 ACMP_NEG_CH7 = 0x7U,
88 ACMP_NEG_1V25 = 0x8U,
89 ACMP_NEG_2V5 = 0x9U,
90 ACMP_NEG_VDD = 0xAU,
91 } acmp_neg_input_t;
92
96 typedef enum {
97 ACMP_ULTRA_LOW_POWER = 0x0U,
98 ACMP_LOW_POWER = 0x1U,
99 ACMP_MIDDLE_POWER = 0x2U,
100 ACMP_HIGH_POWER = 0x3U,
101 } acmp_mode_t;
102
106 typedef enum {
107 ACMP_4_PCLK = 0x0U,
108 ACMP_8_PCLK = 0x1U,
109 ACMP_16_PCLK = 0x2U,
110 ACMP_32_PCLK = 0x3U,
111 ACMP_64_PCLK = 0x4U,
112 ACMP_128_PCLK = 0x5U,
113 ACMP_256_PCLK = 0x6U,
114 ACMP_512_PCLK = 0x7U,
115 } acmp_warm_time_t;
116
120 typedef enum {
121 ACMP_HYST_0 = 0x0U,
122 ACMP_HYST_15 = 0x1U,
123 ACMP_HYST_22 = 0x2U,
124 ACMP_HYST_29 = 0x3U,
125 ACMP_HYST_36 = 0x4U,
126 ACMP_HYST_43 = 0x5U,
127 ACMP_HYST_50 = 0x6U,
128 ACMP_HYST_57 = 0x7U,
129 } acmp_hystsel_t;
130
134 typedef enum {
135 ACMP_INACTVAL_LOW = 0x0U,
136 ACMP_INACTVAL_HIGH = 0x1U,
137 } acmp_inactval_t;
138
142 typedef enum {
143 ACMP_EDGE_NONE = 0x0U,
144 ACMP_EDGE_FALL = 0x1U,
145 ACMP_EDGE_RISE = 0x2U,
146 ACMP_EDGE_ALL = 0x3U,
147 } acmp_edge_t;
148
152 typedef enum {
153 ACMP_OUT_DISABLE = 0x0U,
154 ACMP_OUT_ENABLE = 0x1U,
155 } acmp_out_func_t;
156
160 typedef struct {
161 acmp_mode_t mode;
162 acmp_warm_time_t warm_time;
163 acmp_hystsel_t hystsel;
164 acmp_pos_input_t p_port;
165 acmp_neg_input_t n_port;
166 acmp_inactval_t inactval;
167 type_func_t out_inv;
168 acmp_edge_t edge;
169 uint8_t vdd_level;
170 } acmp_init_t;
171
175 typedef struct acmp_handle_s {
176 ACMP_TypeDef *perh;
177 acmp_init_t init;
178 lock_state_t lock;
180 void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg);
181 void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg);
182 } acmp_handle_t;
190 #define ACMP_ENABLE(handle) (SET_BIT((handle)->perh->CON, ACMP_CON_EN_MSK))
191 #define ACMP_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, ACMP_CON_EN_MSK))
192
199 #define IS_ACMP_TYPE(x) (((x) == ACMP0) || \
200 ((x) == ACMP1) || \
201 ((x) == ACMP2))
202 #define IS_ACMP_MODE_TYPE(x) (((x) == ACMP_ULTRA_LOW_POWER) || \
203 ((x) == ACMP_LOW_POWER) || \
204 ((x) == ACMP_MIDDLE_POWER) || \
205 ((x) == ACMP_HIGH_POWER))
206 #define IS_ACMP_IT_TYPE(x) (((x) == ACMP_IT_EDGE) || \
207 ((x) == ACMP_IT_WARMUP))
208 #define IS_ACMP_FLAG_TYPE(x) (((x) == ACMP_FLAG_EDGE) || \
209 ((x) == ACMP_FLAG_WARMUP))
210 #define IS_ACMP_STATUS_TYPE(x) (((x) == ACMP_STATUS_ACT) || \
211 ((x) == ACMP_STATUS_OUT))
212 #define IS_ACMP_POS_INPUT_TYPE(x) (((x) == ACMP_POS_CH0) || \
213 ((x) == ACMP_POS_CH1) || \
214 ((x) == ACMP_POS_CH2) || \
215 ((x) == ACMP_POS_CH3) || \
216 ((x) == ACMP_POS_CH4) || \
217 ((x) == ACMP_POS_CH5) || \
218 ((x) == ACMP_POS_CH6) || \
219 ((x) == ACMP_POS_CH7))
220 #define IS_ACMP_NEG_INPUT_TYPE(x) (((x) == ACMP_NEG_CH0) || \
221 ((x) == ACMP_NEG_CH1) || \
222 ((x) == ACMP_NEG_CH2) || \
223 ((x) == ACMP_NEG_CH3) || \
224 ((x) == ACMP_NEG_CH4) || \
225 ((x) == ACMP_NEG_CH5) || \
226 ((x) == ACMP_NEG_CH6) || \
227 ((x) == ACMP_NEG_CH7) || \
228 ((x) == ACMP_NEG_1V25) || \
229 ((x) == ACMP_NEG_2V5) || \
230 ((x) == ACMP_NEG_VDD))
231 #define IS_ACMP_WARM_UP_TIME_TYPE(x) (((x) == ACMP_4_PCLK) || \
232 ((x) == ACMP_8_PCLK) || \
233 ((x) == ACMP_16_PCLK) || \
234 ((x) == ACMP_32_PCLK) || \
235 ((x) == ACMP_64_PCLK) || \
236 ((x) == ACMP_128_PCLK) || \
237 ((x) == ACMP_256_PCLK) || \
238 ((x) == ACMP_512_PCLK))
239 #define IS_ACMP_HYSTSEL_TYPE(x) (((x) == ACMP_HYST_0) || \
240 ((x) == ACMP_HYST_15) || \
241 ((x) == ACMP_HYST_22) || \
242 ((x) == ACMP_HYST_29) || \
243 ((x) == ACMP_HYST_36) || \
244 ((x) == ACMP_HYST_43) || \
245 ((x) == ACMP_HYST_50) || \
246 ((x) == ACMP_HYST_57))
247 #define IS_ACMP_INACTVAL_TYPE(x) (((x) == ACMP_INACTVAL_LOW) || \
248 ((x) == ACMP_INACTVAL_HIGH))
249 #define IS_ACMP_EDGE_TYPE(x) (((x) == ACMP_EDGE_NONE) || \
250 ((x) == ACMP_EDGE_FALL) || \
251 ((x) == ACMP_EDGE_RISE) || \
252 ((x) == ACMP_EDGE_ALL))
253
264 ald_status_t ald_acmp_init(acmp_handle_t *hperh);
271 void ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state);
272 it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it);
273 flag_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag);
274 flag_status_t ald_acmp_get_mask_flag_status(acmp_handle_t *hperh, acmp_flag_t flag);
275 void ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag);
282 void ald_acmp_irq_handler(acmp_handle_t *hperh);
283 void ald_acmp_out_config(acmp_handle_t *hperh, type_func_t state);
284 uint8_t ald_acmp_out_result(acmp_handle_t *hperh);
285 flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status);
298 #ifdef __cplusplus
299 extern "C" }
300 #endif
301 #endif
ACMP_EDGE_NONE
Definition: ald_acmp.h:143
ACMP_NEG_1V25
Definition: ald_acmp.h:88
ACMP_NEG_CH0
Definition: ald_acmp.h:80
acmp_init_t::p_port
acmp_pos_input_t p_port
Definition: ald_acmp.h:164
ACMP_INACTVAL_HIGH
Definition: ald_acmp.h:136
ACMP_NEG_CH2
Definition: ald_acmp.h:82
ald_acmp_init
ald_status_t ald_acmp_init(acmp_handle_t *hperh)
Initializes the ACMP mode according to the specified parameters in the acmp_init_t and create the ass...
Definition: ald_acmp.c:45
acmp_handle_s::lock
lock_state_t lock
Definition: ald_acmp.h:178
ACMP_EDGE_RISE
Definition: ald_acmp.h:145
type_func_t
type_func_t
Definition: type.h:47
ACMP_POS_CH3
Definition: ald_acmp.h:69
ACMP_NEG_CH4
Definition: ald_acmp.h:84
acmp_handle_t
struct acmp_handle_s acmp_handle_t
ACMP Handle Structure definition.
ACMP_HYST_0
Definition: ald_acmp.h:121
acmp_init_t::n_port
acmp_neg_input_t n_port
Definition: ald_acmp.h:165
ACMP_POS_CH4
Definition: ald_acmp.h:70
acmp_handle_s::perh
ACMP_TypeDef * perh
Definition: ald_acmp.h:176
ACMP_NEG_2V5
Definition: ald_acmp.h:89
ald_acmp_get_status
flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status)
Check whether the specified ACMP flag is set or not.
Definition: ald_acmp.c:298
ACMP_8_PCLK
Definition: ald_acmp.h:108
ACMP_HYST_15
Definition: ald_acmp.h:122
ACMP_NEG_CH7
Definition: ald_acmp.h:87
ACMP_MIDDLE_POWER
Definition: ald_acmp.h:99
ald_acmp_out_result
uint8_t ald_acmp_out_result(acmp_handle_t *hperh)
This function output acmp result.
Definition: ald_acmp.c:282
ACMP_256_PCLK
Definition: ald_acmp.h:113
ACMP_LOW_POWER
Definition: ald_acmp.h:98
utils.h
This file contains the Utilities functions/types for the driver.
ACMP_POS_CH2
Definition: ald_acmp.h:68
ACMP_POS_CH0
Definition: ald_acmp.h:66
acmp_init_t::mode
acmp_mode_t mode
Definition: ald_acmp.h:161
ACMP_POS_CH1
Definition: ald_acmp.h:67
ACMP_4_PCLK
Definition: ald_acmp.h:107
ACMP_INACTVAL_LOW
Definition: ald_acmp.h:135
ACMP_512_PCLK
Definition: ald_acmp.h:114
acmp_init_t::out_inv
type_func_t out_inv
Definition: ald_acmp.h:167
ald_acmp_clear_flag_status
void ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
Clear the specified ACMP it flags.
Definition: ald_acmp.c:216
it_status_t
enum flag_status_t it_status_t
ald_acmp_out_config
void ald_acmp_out_config(acmp_handle_t *hperh, type_func_t state)
This function config acmp output.
Definition: ald_acmp.c:263
acmp_mode_t
acmp_mode_t
ACMP mode.
Definition: ald_acmp.h:96
ACMP_STATUS_ACT
Definition: ald_acmp.h:58
ACMP_OUT_ENABLE
Definition: ald_acmp.h:154
ald_acmp_get_flag_status
flag_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
Checks whether the specified ACMP interrupt has occurred or not.
Definition: ald_acmp.c:178
acmp_warm_time_t
acmp_warm_time_t
ACMP warm-up time.
Definition: ald_acmp.h:106
acmp_neg_input_t
acmp_neg_input_t
ACMP negative input.
Definition: ald_acmp.h:79
ald_acmp_interrupt_config
void ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state)
Enables or disables the specified ACMP interrupts.
Definition: ald_acmp.c:133
acmp_it_t
acmp_it_t
ACMP interrupt.
Definition: ald_acmp.h:41
acmp_flag_t
acmp_flag_t
ACMP interrupt flag.
Definition: ald_acmp.h:49
acmp_init_t::hystsel
acmp_hystsel_t hystsel
Definition: ald_acmp.h:163
ACMP_POS_CH5
Definition: ald_acmp.h:71
ACMP_HYST_50
Definition: ald_acmp.h:127
ald_acmp_get_mask_flag_status
flag_status_t ald_acmp_get_mask_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
Get the status of interrupt flag and interupt source.
Definition: ald_acmp.c:198
ACMP_EDGE_ALL
Definition: ald_acmp.h:146
ACMP_IT_EDGE
Definition: ald_acmp.h:42
acmp_edge_t
acmp_edge_t
which edges set up interrupt
Definition: ald_acmp.h:142
lock_state_t
lock_state_t
Definition: type.h:58
ACMP_NEG_CH5
Definition: ald_acmp.h:85
ACMP_NEG_VDD
Definition: ald_acmp.h:90
ACMP_IT_WARMUP
Definition: ald_acmp.h:43
ACMP_HYST_22
Definition: ald_acmp.h:123
ACMP_64_PCLK
Definition: ald_acmp.h:111
ACMP_128_PCLK
Definition: ald_acmp.h:112
acmp_init_t
ACMP init structure definition.
Definition: ald_acmp.h:160
acmp_handle_s::init
acmp_init_t init
Definition: ald_acmp.h:177
ACMP_16_PCLK
Definition: ald_acmp.h:109
ald_acmp_get_it_status
it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it)
Checks whether the specified ACMP interrupt has set or not.
Definition: ald_acmp.c:157
ACMP_FLAG_WARMUP
Definition: ald_acmp.h:51
acmp_handle_s::acmp_warmup_cplt_cbk
void(* acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg)
Definition: ald_acmp.h:180
acmp_inactval_t
acmp_inactval_t
ACMP inactive state.
Definition: ald_acmp.h:134
acmp_handle_s::acmp_edge_cplt_cbk
void(* acmp_edge_cplt_cbk)(struct acmp_handle_s *arg)
Definition: ald_acmp.h:181
ACMP_HYST_29
Definition: ald_acmp.h:124
ACMP_EDGE_FALL
Definition: ald_acmp.h:144
ACMP_POS_CH6
Definition: ald_acmp.h:72
ACMP_32_PCLK
Definition: ald_acmp.h:110
ACMP_ULTRA_LOW_POWER
Definition: ald_acmp.h:97
ACMP_HIGH_POWER
Definition: ald_acmp.h:100
acmp_pos_input_t
acmp_pos_input_t
ACMP positive input.
Definition: ald_acmp.h:65
acmp_out_func_t
acmp_out_func_t
ACMP output function.
Definition: ald_acmp.h:152
flag_status_t
flag_status_t
Definition: type.h:37
acmp_init_t::edge
acmp_edge_t edge
Definition: ald_acmp.h:168
ACMP_HYST_36
Definition: ald_acmp.h:125
ACMP_NEG_CH3
Definition: ald_acmp.h:83
ACMP_HYST_43
Definition: ald_acmp.h:126
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
acmp_init_t::warm_time
acmp_warm_time_t warm_time
Definition: ald_acmp.h:162
acmp_init_t::vdd_level
uint8_t vdd_level
Definition: ald_acmp.h:169
ACMP_STATUS_OUT
Definition: ald_acmp.h:59
ald_acmp_irq_handler
void ald_acmp_irq_handler(acmp_handle_t *hperh)
This function handles ACMP interrupt request.
Definition: ald_acmp.c:237
ACMP_NEG_CH6
Definition: ald_acmp.h:86
acmp_handle_s
ACMP Handle Structure definition.
Definition: ald_acmp.h:175
ACMP_FLAG_EDGE
Definition: ald_acmp.h:50
acmp_init_t::inactval
acmp_inactval_t inactval
Definition: ald_acmp.h:166
ACMP_NEG_CH1
Definition: ald_acmp.h:81
ACMP_OUT_DISABLE
Definition: ald_acmp.h:153
acmp_hystsel_t
acmp_hystsel_t
ACMP hysteresis level.
Definition: ald_acmp.h:120
ACMP_HYST_57
Definition: ald_acmp.h:128
acmp_status_t
acmp_status_t
ACMP status flag.
Definition: ald_acmp.h:57
ACMP_POS_CH7
Definition: ald_acmp.h:73


ALD User Manual: D:/svn/src/ald_adc.c Source File

  • D:
  • svn
  • src
ald_adc.c
Go to the documentation of this file.
1
31 #include "ald_cmu.h"
32 #include "ald_adc.h"
33
34
44 #ifdef ALD_ADC
45
49 #ifdef ALD_DMA
50 static void adc_dma_normal_conv_cplt(void *arg);
51 static void adc_dma_error(void *arg);
52 #endif
53
74 ald_status_t ald_adc_init(adc_handle_t *hperh)
75 {
76 assert_param(IS_ADC_TYPE(hperh->perh));
77 assert_param(IS_ADC_DATA_ALIGN_TYPE(hperh->init.align));
78 assert_param(IS_FUNC_STATE(hperh->init.scan));
79 assert_param(IS_ADC_CLK_DIV_TYPE(hperh->init.div));
80 assert_param(IS_ADC_NEG_REF_VOLTAGE_TYPE(hperh->init.n_ref));
81 assert_param(IS_POS_REF_VOLTAGE_TYPE(hperh->init.p_ref));
82 assert_param(IS_ADC_CONV_BIT_TYPE(hperh->init.data_bit));
83 assert_param(IS_ADC_NCH_NR_TYPE(hperh->init.nch_nr));
84 assert_param(IS_ADC_DISC_NR_TYPE(hperh->init.disc_nr));
85 assert_param(IS_FUNC_STATE(hperh->init.cont));
86 assert_param(IS_ADC_NCHESEL_MODE_TYPE(hperh->init.nche_sel));
87
88 if (hperh->state == ADC_STATE_RESET ) {
89 hperh->error_code = ADC_ERROR_NONE;
90 hperh->lock = UNLOCK;
91 }
92
93 ADC_DISABLE(hperh);
94 ald_adc_reset(hperh);
95 hperh->state = ADC_STATE_BUSY;
96 MODIFY_REG(hperh->perh->CON1, ADC_CON1_ALIGN_MSK, hperh->init.align << ADC_CON1_ALIGN_POS);
97 MODIFY_REG(hperh->perh->CON0, ADC_CON0_RSEL_MSK, hperh->init.data_bit << ADC_CON0_RSEL_POSS);
98
99 /* Enable discontinuous mode only if continuous mode is disable */
100 if (hperh->init.disc == ADC_NCH_DISC_EN) {
101 hperh->init.scan = ENABLE;
102 hperh->init.cont = DISABLE;
103 SET_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK);
104 MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nr << ADC_CON0_ETRGN_POSS);
105 }
106 else if (hperh->init.disc == ADC_ICH_DISC_EN) {
107 hperh->init.scan = ENABLE;
108 hperh->init.cont = DISABLE;
109 SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK);
110 MODIFY_REG(hperh->perh->CON0, ADC_CON0_ETRGN_MSK, hperh->init.disc_nr << ADC_CON0_ETRGN_POSS);
111 }
112 else {
113 CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHDCEN_MSK);
114 CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK);
115 }
116
117 if ((hperh->init.scan == ENABLE) || (hperh->init.disc == ADC_NCH_DISC_EN))
118 MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_NSL_MSK, hperh->init.nch_nr << ADC_CHSL_NSL_POSS);
119
120 MODIFY_REG(hperh->perh->CON1, ADC_CON1_CM_MSK, hperh->init.cont << ADC_CON1_CM_POS);
121 MODIFY_REG(hperh->perh->CON0, ADC_CON0_SCANEN_MSK, hperh->init.scan << ADC_CON0_SCANEN_POS);
122 MODIFY_REG(hperh->perh->CCR, ADC_CCR_GAINCALEN_MSK, DISABLE << ADC_CCR_GAINCALEN_POS);
123 MODIFY_REG(hperh->perh->CCR, ADC_CCR_OFFCALEN_MSK, DISABLE << ADC_CCR_OFFCALEN_POS);
124 MODIFY_REG(hperh->perh->CCR, ADC_CCR_DIFFEN_MSK, DISABLE << ADC_CCR_DIFFEN_POS);
125 /* if the ADC clock less than 1MHz,PWRMOD should be disable*/
126 MODIFY_REG(hperh->perh->CCR, ADC_CCR_PWRMODSEL_MSK, DISABLE << ADC_CCR_PWRMODSEL_POS);
127 MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRBUFEN_MSK, ENABLE << ADC_CCR_VRBUFEN_POS);
128 MODIFY_REG(hperh->perh->CCR, ADC_CCR_VCMBUFEN_MSK, ENABLE << ADC_CCR_VCMBUFEN_POS);
129 MODIFY_REG(hperh->perh->CCR, ADC_CCR_VREFEN_MSK, ENABLE << ADC_CCR_VREFEN_POS);
130 MODIFY_REG(hperh->perh->CCR, ADC_CCR_IREFEN_MSK, ENABLE << ADC_CCR_IREFEN_POS);
131 MODIFY_REG(hperh->perh->CCR, ADC_CCR_CKDIV_MSK, hperh->init.div << ADC_CCR_CKDIV_POSS);
132 MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS);
133 MODIFY_REG(hperh->perh->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POSS);
134 MODIFY_REG(hperh->perh->CON1, ADC_CON1_NCHESEL_MSK, hperh->init.nche_sel << ADC_CON1_NCHESEL_POS);
135 ald_adc_interrupt_config(hperh, ADC_IT_OVR, ENABLE);
136 ADC_ENABLE(hperh);
137
138 hperh->error_code = ADC_ERROR_NONE;
139 hperh->state = ADC_STATE_READY;
140 return OK;
141 }
142
150 ald_status_t ald_adc_reset(adc_handle_t *hperh)
151 {
152 assert_param(IS_ADC_TYPE(hperh->perh));
153
154 ADC_DISABLE(hperh);
155 WRITE_REG(hperh->perh->CLR, 0x30F);
156 WRITE_REG(hperh->perh->CON0, 0x0);
157 WRITE_REG(hperh->perh->CON1, 0x0);
158 WRITE_REG(hperh->perh->CCR, 0x0);
159 WRITE_REG(hperh->perh->WDTH, 0xFFF);
160 WRITE_REG(hperh->perh->WDTL, 0x0);
161 WRITE_REG(hperh->perh->ICHOFF1, 0x0);
162 WRITE_REG(hperh->perh->ICHOFF2, 0x0);
163 WRITE_REG(hperh->perh->ICHOFF3, 0x0);
164 WRITE_REG(hperh->perh->ICHOFF4, 0x0);
165 WRITE_REG(hperh->perh->ICHS, 0x0);
166 WRITE_REG(hperh->perh->NCHS1, 0x0);
167 WRITE_REG(hperh->perh->NCHS2, 0x0);
168 WRITE_REG(hperh->perh->NCHS3, 0x0);
169 WRITE_REG(hperh->perh->NCHS4, 0x0);
170 WRITE_REG(hperh->perh->SMPT1, 0x0);
171 WRITE_REG(hperh->perh->SMPT2, 0x0);
172 WRITE_REG(hperh->perh->CHSL, 0x0);
173
174 hperh->state = ADC_STATE_RESET;
175 hperh->error_code = ADC_ERROR_NONE;
176 return OK;
177 }
193 ald_status_t ald_adc_normal_start(adc_handle_t *hperh)
194 {
195 assert_param(IS_ADC_TYPE(hperh->perh));
196
197 ADC_ENABLE(hperh);
198 WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH | ADC_FLAG_NCHS);
199 SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK);
200
201 return OK;
202 }
203
214 ald_status_t ald_adc_normal_stop(adc_handle_t *hperh)
215 {
216 assert_param(IS_ADC_TYPE(hperh->perh));
217
218 ADC_DISABLE(hperh);
219 hperh->state = ADC_STATE_READY;
220
221 return OK;
222 }
223
236 ald_status_t ald_adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout)
237 {
238 uint32_t _tick;
239
240 assert_param(IS_ADC_TYPE(hperh->perh));
241
242 _tick = ald_get_tick();
243 while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_NCHE_MSK))) {
244 if (timeout != ALD_MAX_DELAY ) {
245 if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) {
246 hperh->state = ADC_STATE_TIMEOUT;
247 return TIMEOUT;
248 }
249 }
250 }
251
252 WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCHS | ADC_FLAG_NCH);
253 return OK;
254 }
255
266 ald_status_t ald_adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout)
267 {
268 uint32_t _tick;
269
270 assert_param(IS_ADC_TYPE(hperh->perh));
271 assert_param(IS_ADC_EVENT_TYPE(event_type));
272
273 _tick = ald_get_tick();
274 while (ald_adc_get_flag_status(hperh, (adc_flag_t)event_type) == RESET) {
275 if (timeout != ALD_MAX_DELAY ) {
276 if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) {
277 hperh->state = ADC_STATE_TIMEOUT;
278 return TIMEOUT;
279 }
280 }
281 }
282
283 CLEAR_BIT(hperh->state, ADC_STATE_BUSY_WDG);
284 return OK;
285 }
286
296 ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh)
297 {
298 assert_param(IS_ADC_TYPE(hperh->perh));
299
300 SET_BIT(hperh->state, ADC_STATE_BUSY_N);
301 ADC_ENABLE(hperh);
302 WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH);
303 ald_adc_interrupt_config(hperh, ADC_IT_NCH, ENABLE);
304 SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK);
305
306 return OK;
307 }
308
317 ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh)
318 {
319 assert_param(IS_ADC_TYPE(hperh->perh));
320
321 ADC_DISABLE(hperh);
322 ald_adc_interrupt_config(hperh, ADC_IT_NCH, DISABLE);
323 CLEAR_BIT(hperh->state, ADC_STATE_BUSY_N);
324
325 return OK;
326 }
327
328 #ifdef ALD_DMA
329
339 ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel)
340 {
341 if ((buf == NULL) || (size == 0))
342 return ERROR;
343
344 assert_param(IS_ADC_TYPE(hperh->perh));
345
346 SET_BIT(hperh->state, ADC_STATE_BUSY_N);
347
348 if (hperh->hdma.perh == NULL)
349 hperh->hdma.perh = DMA0;
350
351 hperh->hdma.cplt_cbk = adc_dma_normal_conv_cplt;
352 hperh->hdma.cplt_arg = hperh;
353 hperh->hdma.err_cbk = adc_dma_error;
354 hperh->hdma.err_arg = hperh;
355
356 ald_dma_config_struct(&hperh->hdma.config);
357 hperh->hdma.config.src = (void *)&hperh->perh->NCHDR;
358 hperh->hdma.config.dst = (void *)buf;
359 hperh->hdma.config.size = size;
360 hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD;
361 hperh->hdma.config.src_inc = DMA_DATA_INC_NONE;
362 hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD;
363 hperh->hdma.config.msel = hperh->perh == ADC0 ? DMA_MSEL_ADC0 : DMA_MSEL_ADC1;
364 hperh->hdma.config.msigsel = DMA_MSIGSEL_ADC;
365 hperh->hdma.config.burst = ENABLE;
366 hperh->hdma.config.channel = channel;
367 ald_dma_config_basic(&hperh->hdma);
368
369 ADC_ENABLE(hperh);
370 SET_BIT(hperh->perh->CON1, ADC_CON1_DMA_MSK);
371 SET_BIT(hperh->perh->CON1, ADC_CON1_NCHTRG_MSK);
372
373 return OK;
374 }
375
385 ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh, uint8_t channel)
386 {
387 assert_param(IS_ADC_TYPE(hperh->perh));
388
389 ADC_DISABLE(hperh);
390 CLEAR_BIT(hperh->perh->CON1, ADC_CON1_DMA_MSK);
391 ald_dma_channel_config(hperh->hdma.perh, channel, DISABLE);
392 CLEAR_BIT(hperh->state, ADC_STATE_BUSY_N);
393
394 return OK;
395 }
396
402 static void adc_dma_timer_trigger_cplt(void *arg)
403 {
404 adc_timer_config_t *hperh = (adc_timer_config_t *)arg;
405
406 ald_timer_base_stop(&hperh->h_timer);
407 CLEAR_BIT(hperh->h_adc.perh->CON1, ADC_CON1_DMA_MSK);
408 ADC_DISABLE(&hperh->h_adc);
409 ald_dma_channel_config(hperh->h_dma.perh, hperh->dma_ch, DISABLE);
410 CLEAR_BIT(hperh->h_adc.state, ADC_STATE_BUSY_N);
411
412 if (hperh->h_adc.normal_cplt_cbk)
413 hperh->h_adc.normal_cplt_cbk(&hperh->h_adc);
414
415 return;
416 }
417
418
425 ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config)
426 {
427 config->h_pis.perh = PIS;
428 config->h_pis.init.producer_clk = PIS_CLK_PCLK1;
429 config->h_pis.init.producer_edge = PIS_EDGE_NONE;
430 config->h_pis.init.consumer_clk = PIS_CLK_PCLK2;
431
432 #if defined(ES32F36xx)
433 if (config->p_timer == AD16C4T0)
434 config->h_pis.init.producer_src = PIS_TIMER0_UPDATA;
435 else if (config->p_timer == AD16C4T1)
436 config->h_pis.init.producer_src = PIS_TIMER1_UPDATA;
437 else if (config->p_timer == GP32C4T0)
438 config->h_pis.init.producer_src = PIS_TIMER2_UPDATA;
439 else if (config->p_timer == GP32C4T1)
440 config->h_pis.init.producer_src = PIS_TIMER3_UPDATA;
441 else
442 return ERROR;
443 #elif defined(ES32F39xx) || defined(ES32F336x)
444 if (config->p_timer == GP16C4T0)
445 config->h_pis.init.producer_src = PIS_TIMER0_UPDATA;
446 else if (config->p_timer == GP16C4T1)
447 config->h_pis.init.producer_src = PIS_TIMER1_UPDATA;
448 else if (config->p_timer == GP32C4T0)
449 config->h_pis.init.producer_src = PIS_TIMER2_UPDATA;
450 else if (config->p_timer == GP32C4T1)
451 config->h_pis.init.producer_src = PIS_TIMER3_UPDATA;
452 else
453 return ERROR;
454 #endif
455
456 if (config->p_adc == ADC0)
457 config->h_pis.init.consumer_trig = PIS_CH6_ADC0_NORMAL;
458 else
459 return ERROR;
460
461 ald_pis_create(&config->h_pis);
462
463 /* Initialize TIMER0 */
464 config->h_timer.perh = config->p_timer;
465 config->h_timer.init.prescaler = 0;
466 config->h_timer.init.mode = TIMER_CNT_MODE_UP;
467 config->h_timer.init.period = ((ald_cmu_get_pclk1_clock() / 1000000) * config->time);
468 config->h_timer.init.clk_div = TIMER_CLOCK_DIV1;
469 config->h_timer.init.re_cnt = 0;
470 ald_timer_base_init(&config->h_timer);
471
472 config->h_adc.perh = config->p_adc;
473 config->h_adc.init.align = ADC_DATAALIGN_RIGHT;
474 config->h_adc.init.scan = DISABLE;
475 config->h_adc.init.cont = DISABLE;
476 config->h_adc.init.nch_nr = ADC_NCH_NR_1;
477 config->h_adc.init.disc = ADC_ALL_DISABLE;
478 config->h_adc.init.disc_nr = ADC_DISC_NR_1;
479 config->h_adc.init.data_bit = ADC_CONV_BIT_12;
480 config->h_adc.init.div = ADC_CKDIV_128;
481 config->h_adc.init.nche_sel = ADC_NCHESEL_MODE_ONE;
482 config->h_adc.init.n_ref = config->n_ref;
483 config->h_adc.init.p_ref = config->p_ref;
484 config->h_adc.normal_cplt_cbk = config->cplt_cbk;
485 config->h_adc.insert_cplt_cbk = NULL;
486 config->h_adc.wdg_cbk = NULL;
487 config->h_adc.error_cbk = NULL;
488 config->h_adc.ovr_cbk = NULL;
489 ald_adc_init(&config->h_adc);
490
491
492
493 config->h_adc.perh->CON1 |= 0x10000000;
494 config->config.ch = config->adc_ch;
495 config->config.idx = ADC_NCH_IDX_1;
496 config->config.samp = ADC_SAMPLETIME_4;
497 ald_adc_normal_channel_config(&config->h_adc, &config->config);
498
499 config->h_dma.cplt_cbk = adc_dma_timer_trigger_cplt;
500 config->h_dma.cplt_arg = config;
501 config->h_dma.err_cbk = adc_dma_error;
502 config->h_dma.err_arg = &config->h_adc;
503
504 ald_dma_config_struct(&config->h_dma.config);
505 config->h_dma.perh = DMA0;
506 config->h_dma.config.src = (void *)&config->h_adc.perh->NCHDR;
507 config->h_dma.config.dst = (void *)config->buf;
508 config->h_dma.config.size = config->size;
509 config->h_dma.config.data_width = DMA_DATA_SIZE_HALFWORD;
510 config->h_dma.config.src_inc = DMA_DATA_INC_NONE;
511 config->h_dma.config.dst_inc = DMA_DATA_INC_HALFWORD;
512 config->h_dma.config.msel = config->p_adc == ADC0 ? DMA_MSEL_ADC0 : DMA_MSEL_ADC1;
513 config->h_dma.config.msigsel = DMA_MSIGSEL_ADC;
514 config->h_dma.config.burst = ENABLE;
515 config->h_dma.config.channel = config->dma_ch;
516 ald_dma_config_basic(&config->h_dma);
517
518 SET_BIT(config->h_adc.perh->CON1, ADC_CON1_DMA_MSK);
519 ADC_ENABLE(&config->h_adc);
520 ald_timer_base_start(&config->h_timer);
521
522 return OK;
523 }
524 #endif
525
532 uint32_t ald_adc_normal_get_value(adc_handle_t *hperh)
533 {
534 assert_param(IS_ADC_TYPE(hperh->perh));
535
536 return hperh->perh->NCHDR;
537 }
538
546 ald_status_t ald_adc_insert_start(adc_handle_t *hperh)
547 {
548 assert_param(IS_ADC_TYPE(hperh->perh));
549
550 ADC_ENABLE(hperh);
551 WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICH);
552
553 if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)))
554 SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK);
555
556 return OK;
557 }
558
571 ald_status_t ald_adc_insert_stop(adc_handle_t *hperh)
572 {
573 assert_param(IS_ADC_TYPE(hperh->perh));
574
575 ADC_DISABLE(hperh);
576 hperh->state = ADC_STATE_READY;
577 return OK;
578 }
579
587 ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout)
588 {
589 uint32_t _tick;
590
591 assert_param(IS_ADC_TYPE(hperh->perh));
592
593 _tick = ald_get_tick();
594
595 while (!(READ_BIT(hperh->perh->STAT, ADC_STAT_ICHE_MSK))) {
596 if (timeout != ALD_MAX_DELAY) {
597 if ((timeout == 0) || ((ald_get_tick() - _tick) > timeout)) {
598 hperh->state |= ADC_STATE_TIMEOUT;
599 return TIMEOUT;
600 }
601 }
602 }
603
604 WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICHS | ADC_FLAG_ICH);
605 return OK;
606 }
607
616 ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh)
617 {
618 assert_param(IS_ADC_TYPE(hperh->perh));
619
620 SET_BIT(hperh->state, ADC_STATE_BUSY_I);
621 ADC_ENABLE(hperh);
622 WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICHS | ADC_FLAG_ICH);
623 ald_adc_interrupt_config(hperh, ADC_IT_ICH, ENABLE);
624
625 if (!(READ_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK)))
626 SET_BIT(hperh->perh->CON1, ADC_CON1_ICHTRG_MSK);
627
628 return OK;
629 }
630
644 ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh)
645 {
646 assert_param(IS_ADC_TYPE(hperh->perh));
647
648 CLEAR_BIT(hperh->state, ADC_STATE_BUSY_I);
649 ADC_DISABLE(hperh);
650 ald_adc_interrupt_config(hperh, ADC_IT_ICH, DISABLE);
651 return OK;
652 }
653
661 uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_idx_t idx)
662 {
663 uint32_t tmp;
664
665 assert_param(IS_ADC_TYPE(hperh->perh));
666 assert_param(IS_ADC_ICH_IDX_TYPE(idx));
667
668 switch (idx) {
669 case ADC_ICH_IDX_1:
670 tmp = hperh->perh->ICHDR1;
671 break;
672 case ADC_ICH_IDX_2:
673 tmp = hperh->perh->ICHDR2;
674 break;
675 case ADC_ICH_IDX_3:
676 tmp = hperh->perh->ICHDR3;
677 break;
678 case ADC_ICH_IDX_4:
679 tmp = hperh->perh->ICHDR4;
680 break;
681 default:
682 tmp = hperh->perh->ICHDR1;
683 break;
684 }
685
686 return tmp;
687 }
688
695 void ald_adc_irq_handler(adc_handle_t *hperh)
696 {
697 assert_param(IS_ADC_TYPE(hperh->perh));
698
699 if (ald_adc_get_it_status(hperh, ADC_IT_NCH) && ald_adc_get_flag_status(hperh, ADC_FLAG_NCH)) {
700 WRITE_REG(hperh->perh->CLR, ADC_FLAG_NCH | ADC_FLAG_NCHS);
701 CLEAR_BIT(hperh->state, ADC_STATE_BUSY_N);
702
703 if (hperh->normal_cplt_cbk)
704 hperh->normal_cplt_cbk(hperh);
705 }
706
707 if (ald_adc_get_it_status(hperh, ADC_IT_ICH) && ald_adc_get_flag_status(hperh, ADC_FLAG_ICH)) {
708 WRITE_REG(hperh->perh->CLR, ADC_FLAG_ICH | ADC_FLAG_ICHS);
709 CLEAR_BIT(hperh->state, ADC_STATE_BUSY_I);
710
711 if (hperh->insert_cplt_cbk)
712 hperh->insert_cplt_cbk(hperh);
713 }
714
715 if (ald_adc_get_it_status(hperh, ADC_IT_AWD) && ald_adc_get_flag_status(hperh, ADC_FLAG_AWD)) {
716 CLEAR_BIT(hperh->state, ADC_STATE_BUSY_WDG);
717 WRITE_REG(hperh->perh->CLR, ADC_FLAG_AWD);
718
719 if (hperh->wdg_cbk)
720 hperh->wdg_cbk(hperh);
721 }
722
723 if (ald_adc_get_it_status(hperh, ADC_IT_OVR) && ald_adc_get_flag_status(hperh, ADC_FLAG_OVR)) {
724 WRITE_REG(hperh->perh->CLR, ADC_FLAG_OVR);
725 hperh->error_code |= ADC_ERROR_OVR;
726 hperh->state |= ADC_STATE_ERROR;
727
728 if (hperh->ovr_cbk)
729 hperh->ovr_cbk(hperh);
730 }
731 }
732
750 ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t *config)
751 {
752 assert_param(IS_ADC_TYPE(hperh->perh));
753 assert_param(IS_ADC_CHANNELS_TYPE(config->ch));
754 assert_param(IS_ADC_NCH_IDX_TYPE(config->idx));
755 assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp));
756
757 if (config->idx <= ADC_NCH_IDX_4 ) {
758 hperh->perh->NCHS1 &= ~(0x1f << (uint32_t)((config->idx - 1) << 3));
759 hperh->perh->NCHS1 |= (config->ch << (uint32_t)((config->idx - 1) << 3));
760 }
761 else if (config->idx <= ADC_NCH_IDX_8) {
762 hperh->perh->NCHS2 &= ~(0x1f << (uint32_t)((config->idx - 5) << 3));
763 hperh->perh->NCHS2 |= (config->ch << (uint32_t)((config->idx - 5) << 3));
764 }
765 else if (config->idx <= ADC_NCH_IDX_12) {
766 hperh->perh->NCHS3 &= ~(0x1f << (uint32_t)((config->idx - 9) << 3));
767 hperh->perh->NCHS3 |= (config->ch << (uint32_t)((config->idx - 9) << 3));
768 }
769 else {
770 hperh->perh->NCHS4 &= ~(0x1f << (uint32_t)((config->idx - 13) << 3));
771 hperh->perh->NCHS4 |= (config->ch << (uint32_t)((config->idx - 13) << 3));
772 }
773
774 if (config->ch < 8) {
775 hperh->perh->SMPT1 &= ~(0x0f << (uint32_t)(config->ch << 2));
776 hperh->perh->SMPT1 |= config->samp << (uint32_t)(config->ch << 2);
777 }
778 else if (config->ch < 16) {
779 hperh->perh->SMPT2 &= ~(0x0f << (uint32_t)((config->ch - 8) << 2));
780 hperh->perh->SMPT2 |= config->samp << (uint32_t)((config->ch - 8) << 2);
781 }
782 else {
783 hperh->perh->SMPT3 &= ~(0x0f << (uint32_t)((config->ch - 16) << 2));
784 hperh->perh->SMPT3 |= config->samp << (uint32_t)((config->ch - 16) << 2);
785 }
786
787 return OK;
788 }
789
798 ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t *config)
799 {
800 ald_status_t tmp_status = OK;
801
802 assert_param(IS_ADC_TYPE(hperh->perh));
803 assert_param(IS_ADC_CHANNELS_TYPE(config->ch));
804 assert_param(IS_ADC_ICH_IDX_TYPE(config->idx));
805 assert_param(IS_ADC_SAMPLING_TIMES_TYPE(config->samp));
806 assert_param(IS_ADC_IST_OFFSET_TYPE(config->offset));
807 assert_param(IS_ADC_ICH_NR_TYPE(config->nr));
808 assert_param(IS_FUNC_STATE(config->auto_m));
809
810 MODIFY_REG(hperh->perh->CHSL, ADC_CHSL_ISL_MSK, config->nr << ADC_CHSL_ISL_POSS);
811 hperh->perh->ICHS &= ~(0x1f << (uint32_t)((config->idx - 1) << 3));
812 hperh->perh->ICHS |= config->ch << (uint32_t)((config->idx - 1) << 3);
813
814 if (config->auto_m == ENABLE)
815 SET_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK);
816 else
817 CLEAR_BIT(hperh->perh->CON0, ADC_CON0_IAUTO_MSK);
818
819 if (hperh->init.disc == ADC_ICH_DISC_EN) {
820 if (config->auto_m == DISABLE) {
821 SET_BIT(hperh->perh->CON0, ADC_CON0_ICHDCEN_MSK);
822 }
823 else {
824 hperh->state |= ADC_STATE_ERROR;
825 hperh->error_code |= ADC_ERROR_INTERNAL;
826 tmp_status = ERROR;
827 }
828 }
829
830 if (config->ch < 8) {
831 hperh->perh->SMPT1 &= ~(0x0f << (uint32_t)(config->ch << 2));
832 hperh->perh->SMPT1 |= config->samp << (uint32_t)(config->ch << 2);
833 }
834 else if (config->ch < 16) {
835 hperh->perh->SMPT2 &= ~(0x0f << (uint32_t)((config->ch - 8) << 2));
836 hperh->perh->SMPT2 |= config->samp << (uint32_t)((config->ch - 8) << 2);
837 }
838 else {
839 hperh->perh->SMPT3 &= ~(0x0f << (uint32_t)((config->ch - 16) << 2));
840 hperh->perh->SMPT3 |= config->samp << (uint32_t)((config->ch - 16) << 2);
841 }
842
843 switch (config->idx) {
844 case ADC_ICH_IDX_1:
845 hperh->perh->ICHOFF1 = config->offset;
846 break;
847 case ADC_ICH_IDX_2:
848 hperh->perh->ICHOFF2 = config->offset;
849 break;
850 case ADC_ICH_IDX_3:
851 hperh->perh->ICHOFF3 = config->offset;
852 break;
853 case ADC_ICH_IDX_4:
854 hperh->perh->ICHOFF4 = config->offset;
855 break;
856 default:
857 break;
858 }
859
860 return tmp_status;
861 }
862
870 ald_status_t ald_adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config)
871 {
872 assert_param(IS_ADC_TYPE(hperh->perh));
873 assert_param(IS_ADC_ANALOG_WTD_MODE_TYPE(config->mode));
874 assert_param(IS_FUNC_STATE(config->interrupt));
875 assert_param(IS_HTR_TYPE(config->high_thrd));
876 assert_param(IS_LTR_TYPE(config->low_thrd));
877
878 if ((config->mode == ADC_ANAWTD_SING_NM)
879 || (config->mode == ADC_ANAWTD_SING_IST)
880 || (config->mode == ADC_ANAWTD_SING_NMIST))
881 assert_param(IS_ADC_CHANNELS_TYPE(config->ch));
882
883 if (config->interrupt == DISABLE)
884 ald_adc_interrupt_config(hperh, ADC_IT_AWD, DISABLE);
885 else
886 ald_adc_interrupt_config(hperh, ADC_IT_AWD, ENABLE);
887
888 CLEAR_BIT(hperh->perh->CON0, ADC_CON0_ICHWDTEN_MSK);
889 CLEAR_BIT(hperh->perh->CON0, ADC_CON0_NCHWDEN_MSK);
890 CLEAR_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK);
891 hperh->perh->CON0 |= config->mode;
892
893 if (READ_BIT(hperh->perh->CON0, ADC_CON0_AWDSGL_MSK))
894 MODIFY_REG(hperh->perh->CON0, ADC_CON0_AWDCH_MSK, config->ch << ADC_CON0_AWDCH_POSS);
895
896 WRITE_REG(hperh->perh->WDTL, config->low_thrd);
897 WRITE_REG(hperh->perh->WDTH, config->high_thrd);
898 SET_BIT(hperh->state, ADC_STATE_BUSY_WDG);
899
900 return OK;
901 }
902
913 void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state)
914 {
915 assert_param(IS_ADC_TYPE(hperh->perh));
916 assert_param(IS_ADC_IT_TYPE(it));
917 assert_param(IS_FUNC_STATE(state));
918
919 if (state == ENABLE)
920 SET_BIT(hperh->perh->CON0, it);
921 else
922 CLEAR_BIT(hperh->perh->CON0, it);
923
924 return;
925 }
926
936 it_status_t ald_adc_get_it_status(adc_handle_t *hperh, adc_it_t it)
937 {
938 assert_param(IS_ADC_TYPE(hperh->perh));
939 assert_param(IS_ADC_IT_TYPE(it));
940
941 if (READ_BIT(hperh->perh->CON0, it))
942 return SET;
943
944 return RESET;
945 }
946
955 flag_status_t ald_adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag)
956 {
957 assert_param(IS_ADC_TYPE(hperh->perh));
958 assert_param(IS_ADC_FLAGS_TYPE(flag));
959
960 if (READ_BIT(hperh->perh->STAT, flag))
961 return SET;
962
963 return RESET;
964 }
965
972 void ald_adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag)
973 {
974 assert_param(IS_ADC_TYPE(hperh->perh));
975 assert_param(IS_ADC_FLAGS_TYPE(flag));
976
977 WRITE_REG(hperh->perh->CLR, flag);
978 return;
979 }
995 uint32_t ald_adc_get_state(adc_handle_t *hperh)
996 {
997 return hperh->state;
998 }
999
1006 uint32_t ald_adc_get_error(adc_handle_t *hperh)
1007 {
1008 return hperh->error_code;
1009 }
1010
1023 #ifdef ALD_DMA
1024
1029 static void adc_dma_normal_conv_cplt(void *arg)
1030 {
1031 adc_handle_t *hperh = (adc_handle_t *)arg;
1032
1033 CLEAR_BIT(hperh->perh->CON1, ADC_CON1_DMA_MSK);
1034
1035 if (hperh->normal_cplt_cbk)
1036 hperh->normal_cplt_cbk(hperh);
1037
1038 }
1039
1045 static void adc_dma_error(void *arg)
1046 {
1047 adc_handle_t *hperh = (adc_handle_t *)arg;
1048 hperh->state |= ADC_STATE_ERROR;
1049 hperh->error_code |= ADC_ERROR_DMA;
1050
1051 if (hperh->error_cbk)
1052 hperh->error_cbk(hperh);
1053 }
1054 #endif
1055
1059 #endif /* ALD_ADC */
1060
adc_flag_t
adc_flag_t
ADC flags definition.
Definition: ald_adc.h:180
ald_adc_stop_by_dma
ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh, uint8_t channel)
Stop ADC conversion of normal group (and insert group in case of auto_insert mode), disable ADC DMA transfer, disable ADC peripheral.
Definition: ald_adc.c:385
ADC_STATE_TIMEOUT
Definition: ald_adc.h:47
adc_handle_s
ADC handle Structure definition.
Definition: ald_adc.h:353
adc_timer_config_t::adc_ch
adc_channel_t adc_ch
Definition: ald_adc.h:380
ADC_ENABLE
#define ADC_ENABLE(handle)
Definition: ald_adc.h:401
IS_ADC_IST_OFFSET_TYPE
#define IS_ADC_IST_OFFSET_TYPE(x)
Definition: ald_adc.h:475
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
adc_timer_config_t::h_dma
dma_handle_t h_dma
Definition: ald_adc.h:389
ADC_ANAWTD_SING_IST
Definition: ald_adc.h:153
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
PIS_TIMER0_UPDATA
Definition: ald_pis.h:128
PIS_TIMER1_UPDATA
Definition: ald_pis.h:138
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
PIS_TIMER2_UPDATA
Definition: ald_pis.h:148
ADC_CONV_BIT_12
Definition: ald_adc.h:283
adc_ich_conf_t
ADC Configuration insert Channel structure definition.
Definition: ald_adc.h:341
ADC_ICH_IDX_1
Definition: ald_adc.h:141
ald_adc_start_by_dma
ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel)
Enables ADC, starts conversion of normal group and transfers result through DMA.
Definition: ald_adc.c:339
ADC_ANAWTD_SING_NM
Definition: ald_adc.h:152
ADC_IT_AWD
Definition: ald_adc.h:172
timer_base_init_t::re_cnt
uint32_t re_cnt
Definition: ald_timer.h:141
adc_init_t::scan
type_func_t scan
Definition: ald_adc.h:306
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
ald_adc_normal_poll_for_conversion
ald_status_t ald_adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout)
Wait for normal group conversion to be completed.
Definition: ald_adc.c:236
adc_timer_config_t::size
uint16_t size
Definition: ald_adc.h:376
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
ADC_ERROR_DMA
Definition: ald_adc.h:61
adc_init_t::disc
adc_disc_mode_t disc
Definition: ald_adc.h:309
ald_adc_init
ald_status_t ald_adc_init(adc_handle_t *hperh)
Initializes the ADC peripheral and normal group according to parameters specified in structure "adc_h...
Definition: ald_adc.c:74
adc_handle_s::hdma
dma_handle_t hdma
Definition: ald_adc.h:357
adc_timer_config_t
Timer trigger adc config structure definition.
Definition: ald_adc.h:374
SET
Definition: type.h:39
adc_init_t::nche_sel
adc_nchesel_t nche_sel
Definition: ald_adc.h:313
timer_base_init_t::clk_div
timer_clock_division_t clk_div
Definition: ald_timer.h:140
adc_nch_conf_t
Structure definition of ADC channel for normal group.
Definition: ald_adc.h:321
ALD_MAX_DELAY
#define ALD_MAX_DELAY
Definition: utils.h:88
adc_handle_s::wdg_cbk
void(* wdg_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:366
type_func_t
type_func_t
Definition: type.h:47
adc_ich_conf_t::ch
adc_channel_t ch
Definition: ald_adc.h:342
ADC_STATE_ERROR
Definition: ald_adc.h:48
ADC_IT_ICH
Definition: ald_adc.h:173
ADC_FLAG_ICH
Definition: ald_adc.h:183
DISABLE
Definition: type.h:48
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
PIS_CLK_PCLK1
Definition: ald_pis.h:251
ald_timer_base_init
ald_status_t ald_timer_base_init(timer_handle_t *hperh)
Initializes the TIMER Time base Unit according to the specified parameters in the timer_handle_t and ...
Definition: ald_timer.c:97
IS_ADC_CLK_DIV_TYPE
#define IS_ADC_CLK_DIV_TYPE(x)
Definition: ald_adc.h:449
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
adc_nch_conf_t::ch
adc_channel_t ch
Definition: ald_adc.h:322
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
adc_dma_normal_conv_cplt
static void adc_dma_normal_conv_cplt(void *arg)
DMA transfer complete callback.
Definition: ald_adc.c:1029
adc_init_t::data_bit
adc_conv_bit_t data_bit
Definition: ald_adc.h:311
adc_timer_config_t::n_ref
adc_neg_ref_t n_ref
Definition: ald_adc.h:378
ADC_ERROR_OVR
Definition: ald_adc.h:60
ADC_STATE_BUSY_N
Definition: ald_adc.h:49
ald_adc_normal_stop_by_it
ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh)
Stop ADC conversion of normal group (and insert group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
Definition: ald_adc.c:317
adc_event_type_t
adc_event_type_t
ADC Event type.
Definition: ald_adc.h:163
IS_ADC_IT_TYPE
#define IS_ADC_IT_TYPE(x)
Definition: ald_adc.h:439
dma_config_t::src
void * src
Definition: ald_dma.h:278
IS_ADC_DISC_NR_TYPE
#define IS_ADC_DISC_NR_TYPE(x)
Definition: ald_adc.h:465
adc_handle_s::ovr_cbk
void(* ovr_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:368
adc_timer_config_t::buf
uint16_t * buf
Definition: ald_adc.h:377
pis_init_t::producer_src
pis_src_t producer_src
Definition: ald_pis.h:396
adc_nch_conf_t::samp
adc_samp_t samp
Definition: ald_adc.h:324
adc_init_t::div
adc_clk_div_t div
Definition: ald_adc.h:312
adc_timer_config_t::time
uint32_t time
Definition: ald_adc.h:375
adc_analog_wdg_conf_t::interrupt
type_func_t interrupt
Definition: ald_adc.h:333
ald_adc_get_error
uint32_t ald_adc_get_error(adc_handle_t *hperh)
Return the ADC error code.
Definition: ald_adc.c:1006
timer_base_init_t::period
uint32_t period
Definition: ald_timer.h:139
ald_adc_reset
ald_status_t ald_adc_reset(adc_handle_t *hperh)
Deinitialize the ADC peripheral registers to their default reset values.
Definition: ald_adc.c:150
timer_handle_s::init
timer_base_init_t init
Definition: ald_timer.h:184
ADC_FLAG_AWD
Definition: ald_adc.h:181
adc_it_t
adc_it_t
ADC interrupts definition.
Definition: ald_adc.h:170
adc_ich_conf_t::samp
adc_samp_t samp
Definition: ald_adc.h:344
ald_adc_insert_start
ald_status_t ald_adc_insert_start(adc_handle_t *hperh)
Enables ADC, starts conversion of insert group. Interruptions enabled in this function: None...
Definition: ald_adc.c:546
UNLOCK
Definition: type.h:59
RESET
Definition: type.h:38
adc_ich_idx_t
adc_ich_idx_t
ADC index channel in insert group.
Definition: ald_adc.h:140
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
adc_ich_conf_t::auto_m
type_func_t auto_m
Definition: ald_adc.h:347
ald_adc_timer_trigger_adc_by_dma
ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config)
Config Timer trigger adc function.
Definition: ald_adc.c:425
ald_timer_base_start
void ald_timer_base_start(timer_handle_t *hperh)
Starts the TIMER Base generation.
Definition: ald_timer.c:138
TIMER_CLOCK_DIV1
Definition: ald_timer.h:55
adc_init_t::cont
type_func_t cont
Definition: ald_adc.h:307
IS_ADC_NCH_NR_TYPE
#define IS_ADC_NCH_NR_TYPE(x)
Definition: ald_adc.h:463
ADC_FLAG_ICHS
Definition: ald_adc.h:186
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
adc_analog_wdg_conf_t::high_thrd
uint32_t high_thrd
Definition: ald_adc.h:334
adc_nch_conf_t::idx
adc_nch_idx_t idx
Definition: ald_adc.h:323
adc_dma_timer_trigger_cplt
static void adc_dma_timer_trigger_cplt(void *arg)
DMA transfer complete callback.
Definition: ald_adc.c:402
ald_adc_get_it_status
it_status_t ald_adc_get_it_status(adc_handle_t *hperh, adc_it_t it)
Checks whether the specified ADC interrupt has occurred or not.
Definition: ald_adc.c:936
ald_adc_normal_stop
ald_status_t ald_adc_normal_stop(adc_handle_t *hperh)
Stop ADC conversion of normal group (and insert channels in case of auto_injection mode)...
Definition: ald_adc.c:214
adc_handle_s::insert_cplt_cbk
void(* insert_cplt_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:365
it_status_t
enum flag_status_t it_status_t
adc_handle_s::init
adc_init_t init
Definition: ald_adc.h:355
adc_analog_wdg_conf_t
ADC Configuration analog watchdog definition.
Definition: ald_adc.h:330
adc_ich_conf_t::nr
adc_ich_nr_t nr
Definition: ald_adc.h:346
IS_ADC_NCHESEL_MODE_TYPE
#define IS_ADC_NCHESEL_MODE_TYPE(x)
Definition: ald_adc.h:472
ADC_FLAG_OVR
Definition: ald_adc.h:184
ald_adc_insert_start_by_it
ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh)
Enables ADC, starts conversion of insert group with interruption.
Definition: ald_adc.c:616
IS_ADC_NEG_REF_VOLTAGE_TYPE
#define IS_ADC_NEG_REF_VOLTAGE_TYPE(x)
Definition: ald_adc.h:457
adc_timer_config_t::p_timer
TIMER_TypeDef * p_timer
Definition: ald_adc.h:382
adc_ich_conf_t::idx
adc_ich_idx_t idx
Definition: ald_adc.h:343
adc_analog_wdg_conf_t::mode
adc_ana_wdg_t mode
Definition: ald_adc.h:331
timer_base_init_t::prescaler
uint32_t prescaler
Definition: ald_timer.h:137
IS_ADC_CHANNELS_TYPE
#define IS_ADC_CHANNELS_TYPE(x)
Definition: ald_adc.h:429
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
adc_init_t::align
adc_align_t align
Definition: ald_adc.h:305
IS_ADC_CONV_BIT_TYPE
#define IS_ADC_CONV_BIT_TYPE(x)
Definition: ald_adc.h:466
ald_adc_analog_wdg_config
ald_status_t ald_adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config)
Configures the analog watchdog.
Definition: ald_adc.c:870
ADC_IT_NCH
Definition: ald_adc.h:171
ADC_STATE_BUSY
Definition: ald_adc.h:46
adc_timer_config_t::p_adc
ADC_TypeDef * p_adc
Definition: ald_adc.h:383
ald_adc_insert_poll_for_conversion
ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout)
Wait for insert group conversion to be completed.
Definition: ald_adc.c:587
DMA_MSEL_ADC1
Definition: ald_dma.h:104
TIMER_CNT_MODE_UP
Definition: ald_timer.h:44
ADC_ANAWTD_SING_NMIST
Definition: ald_adc.h:154
ald_cmu.h
Header file of CMU module driver.
adc_init_t::nch_nr
adc_nch_nr_t nch_nr
Definition: ald_adc.h:308
ADC_STATE_READY
Definition: ald_adc.h:45
adc_dma_error
static void adc_dma_error(void *arg)
DMA error callback.
Definition: ald_adc.c:1045
PIS_EDGE_NONE
Definition: ald_pis.h:261
IS_ADC_SAMPLING_TIMES_TYPE
#define IS_ADC_SAMPLING_TIMES_TYPE(x)
Definition: ald_adc.h:425
ald_adc_insert_stop
ald_status_t ald_adc_insert_stop(adc_handle_t *hperh)
Stop conversion of insert channels. Disable ADC peripheral if no normal conversion is on going...
Definition: ald_adc.c:571
ADC_ICH_IDX_3
Definition: ald_adc.h:143
PIS_CH6_ADC0_NORMAL
Definition: ald_pis.h:202
pis_init_t::producer_edge
pis_edge_t producer_edge
Definition: ald_pis.h:399
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
ald_adc_insert_get_value
uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_idx_t idx)
Get ADC insert group conversion result.
Definition: ald_adc.c:661
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
ADC_ICH_DISC_EN
Definition: ald_adc.h:259
adc_timer_config_t::h_timer
timer_handle_t h_timer
Definition: ald_adc.h:390
ADC_NCH_IDX_8
Definition: ald_adc.h:126
ADC_ERROR_INTERNAL
Definition: ald_adc.h:59
ADC_FLAG_NCHS
Definition: ald_adc.h:185
IS_ADC_DATA_ALIGN_TYPE
#define IS_ADC_DATA_ALIGN_TYPE(x)
Definition: ald_adc.h:430
ADC_NCH_IDX_12
Definition: ald_adc.h:130
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
ADC_FLAG_NCH
Definition: ald_adc.h:182
ald_adc_normal_channel_config
ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t *config)
Configures the the selected channel to be linked to the normal group.
Definition: ald_adc.c:750
ald_cmu_get_pclk1_clock
uint32_t ald_cmu_get_pclk1_clock(void)
Get APB1 clock.
Definition: ald_cmu.c:627
ald_adc_insert_channel_config
ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t *config)
Configures the the selected channel to be linked to the insert group.
Definition: ald_adc.c:798
ADC_DISC_NR_1
Definition: ald_adc.h:266
adc_timer_config_t::h_pis
pis_handle_t h_pis
Definition: ald_adc.h:388
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
ald_pis_create
ald_status_t ald_pis_create(pis_handle_t *hperh)
Create the PIS mode according to the specified parameters in the pis_handle_t and create the associat...
Definition: ald_pis.c:45
ald_adc.h
Header file of ADC Module library.
adc_timer_config_t::cplt_cbk
void(* cplt_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:384
IS_ADC_NCH_IDX_TYPE
#define IS_ADC_NCH_IDX_TYPE(x)
Definition: ald_adc.h:424
ald_adc_clear_flag_status
void ald_adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag)
Clear the specified ADC pending flags.
Definition: ald_adc.c:972
ald_adc_poll_for_event
ald_status_t ald_adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout)
Poll for conversion event.
Definition: ald_adc.c:266
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
ald_adc_interrupt_config
void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state)
Enables or disables the specified ADC interrupts.
Definition: ald_adc.c:913
IS_HTR_TYPE
#define IS_HTR_TYPE(x)
Definition: ald_adc.h:476
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
adc_init_t::p_ref
adc_pos_ref_t p_ref
Definition: ald_adc.h:315
adc_init_t::n_ref
adc_neg_ref_t n_ref
Definition: ald_adc.h:314
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
ald_adc_normal_get_value
uint32_t ald_adc_normal_get_value(adc_handle_t *hperh)
Get ADC normal group conversion result.
Definition: ald_adc.c:532
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
ald_adc_get_flag_status
flag_status_t ald_adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag)
Check whether the specified ADC flag is set or not.
Definition: ald_adc.c:955
PIS_CLK_PCLK2
Definition: ald_pis.h:252
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
ADC_ICH_IDX_4
Definition: ald_adc.h:144
ADC_ALL_DISABLE
Definition: ald_adc.h:257
ADC_NCHESEL_MODE_ONE
Definition: ald_adc.h:77
ADC_SAMPLETIME_4
Definition: ald_adc.h:111
ald_timer_base_stop
void ald_timer_base_stop(timer_handle_t *hperh)
Stops the TIMER Base generation.
Definition: ald_timer.c:154
adc_timer_config_t::h_adc
adc_handle_t h_adc
Definition: ald_adc.h:391
adc_timer_config_t::p_ref
adc_pos_ref_t p_ref
Definition: ald_adc.h:379
pis_handle_s::perh
PIS_TypeDef * perh
Definition: ald_pis.h:419
ald_adc_irq_handler
void ald_adc_irq_handler(adc_handle_t *hperh)
Handles ADC interrupt request.
Definition: ald_adc.c:695
DMA_MSIGSEL_ADC
Definition: ald_dma.h:136
DMA_MSEL_ADC0
Definition: ald_dma.h:82
adc_ich_conf_t::offset
uint32_t offset
Definition: ald_adc.h:345
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
ald_adc_get_state
uint32_t ald_adc_get_state(adc_handle_t *hperh)
return the ADC state
Definition: ald_adc.c:995
flag_status_t
flag_status_t
Definition: type.h:37
ADC_CKDIV_128
Definition: ald_adc.h:200
ald_adc_normal_start_by_it
ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh)
Enables ADC, starts conversion of normal group with interruption. Interruptions enabled in this funct...
Definition: ald_adc.c:296
IS_POS_REF_VOLTAGE_TYPE
#define IS_POS_REF_VOLTAGE_TYPE(x)
Definition: ald_adc.h:459
timer_base_init_t::mode
timer_cnt_mode_t mode
Definition: ald_timer.h:138
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
pis_init_t::producer_clk
pis_clock_t producer_clk
Definition: ald_pis.h:398
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
pis_handle_s::init
pis_init_t init
Definition: ald_pis.h:420
IS_ADC_TYPE
#define IS_ADC_TYPE(x)
Definition: ald_adc.h:470
ADC_STATE_BUSY_I
Definition: ald_adc.h:50
ald_adc_normal_start
ald_status_t ald_adc_normal_start(adc_handle_t *hperh)
Enables ADC, starts conversion of normal group.
Definition: ald_adc.c:193
adc_timer_config_t::config
adc_nch_conf_t config
Definition: ald_adc.h:392
ald_adc_insert_stop_by_it
ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh)
Stop conversion of insert channels, disable interruption of end-of-conversion. Disable ADC peripheral...
Definition: ald_adc.c:644
adc_handle_s::lock
lock_state_t lock
Definition: ald_adc.h:360
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
ADC_DISABLE
#define ADC_DISABLE(handle)
Definition: ald_adc.h:402
IS_ADC_ICH_NR_TYPE
#define IS_ADC_ICH_NR_TYPE(x)
Definition: ald_adc.h:464
ADC_NCH_IDX_1
Definition: ald_adc.h:119
pis_init_t::consumer_trig
pis_trig_t consumer_trig
Definition: ald_pis.h:400
ADC_NCH_IDX_4
Definition: ald_adc.h:122
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
adc_handle_s::error_cbk
void(* error_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:367
adc_analog_wdg_conf_t::ch
adc_channel_t ch
Definition: ald_adc.h:332
ADC_IT_OVR
Definition: ald_adc.h:174
adc_timer_config_t::dma_ch
uint8_t dma_ch
Definition: ald_adc.h:381
adc_init_t::disc_nr
adc_disc_nr_t disc_nr
Definition: ald_adc.h:310
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
IS_ADC_ANALOG_WTD_MODE_TYPE
#define IS_ADC_ANALOG_WTD_MODE_TYPE(x)
Definition: ald_adc.h:432
ADC_NCH_DISC_EN
Definition: ald_adc.h:258
adc_handle_s::error_code
adc_error_t error_code
Definition: ald_adc.h:362
IS_LTR_TYPE
#define IS_LTR_TYPE(x)
Definition: ald_adc.h:477
PIS_TIMER3_UPDATA
Definition: ald_pis.h:158
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
adc_handle_s::normal_cplt_cbk
void(* normal_cplt_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:364
ADC_STATE_RESET
Definition: ald_adc.h:44
IS_ADC_EVENT_TYPE
#define IS_ADC_EVENT_TYPE(x)
Definition: ald_adc.h:474
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
pis_init_t::consumer_clk
pis_clock_t consumer_clk
Definition: ald_pis.h:401
IS_ADC_FLAGS_TYPE
#define IS_ADC_FLAGS_TYPE(x)
Definition: ald_adc.h:443
ADC_DATAALIGN_RIGHT
Definition: ald_adc.h:68
ADC_NCH_NR_1
Definition: ald_adc.h:225
ADC_STATE_BUSY_WDG
Definition: ald_adc.h:51
adc_analog_wdg_conf_t::low_thrd
uint32_t low_thrd
Definition: ald_adc.h:335
ADC_ICH_IDX_2
Definition: ald_adc.h:142
IS_ADC_ICH_IDX_TYPE
#define IS_ADC_ICH_IDX_TYPE(x)
Definition: ald_adc.h:423
ADC_ERROR_NONE
Definition: ald_adc.h:58
ald_dma_channel_config
void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state)
Configure channel enable or disable. It will unbind descriptor with channel, when channel has been di...
Definition: ald_dma.c:850


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1
16 #ifndef __ALD_ADC_H__
17 #define __ALD_ADC_H__
18
19 #ifdef __cplusplus
20 extern "C" {
21 #endif
22
23 #include "utils.h"
24 #include "ald_dma.h"
25 #include "ald_pis.h"
26 #include "ald_timer.h"
27
43 typedef enum {
44 ADC_STATE_RESET = 0x0U,
45 ADC_STATE_READY = 0x1U,
46 ADC_STATE_BUSY = 0x2U,
47 ADC_STATE_TIMEOUT = 0x4U,
48 ADC_STATE_ERROR = 0x8U,
49 ADC_STATE_BUSY_N = 0x10U,
50 ADC_STATE_BUSY_I = 0x20U,
51 ADC_STATE_BUSY_WDG = 0x40U,
52 } adc_state_t;
53
57 typedef enum {
58 ADC_ERROR_NONE = 0x0U,
59 ADC_ERROR_INTERNAL = 0x1U,
60 ADC_ERROR_OVR = 0x2U,
61 ADC_ERROR_DMA = 0x4U,
62 } adc_error_t;
63
67 typedef enum {
68 ADC_DATAALIGN_RIGHT = 0x0U,
69 ADC_DATAALIGN_LEFT = 0x1U,
70 } adc_align_t;
71
75 typedef enum {
76 ADC_NCHESEL_MODE_ALL = 0x0U,
77 ADC_NCHESEL_MODE_ONE = 0x1U,
78 } adc_nchesel_t;
79
83 typedef enum {
84 ADC_CHANNEL_0 = 0x0U,
85 ADC_CHANNEL_1 = 0x1U,
86 ADC_CHANNEL_2 = 0x2U,
87 ADC_CHANNEL_3 = 0x3U,
88 ADC_CHANNEL_4 = 0x4U,
89 ADC_CHANNEL_5 = 0x5U,
90 ADC_CHANNEL_6 = 0x6U,
91 ADC_CHANNEL_7 = 0x7U,
92 ADC_CHANNEL_8 = 0x8U,
93 ADC_CHANNEL_9 = 0x9U,
94 ADC_CHANNEL_10 = 0xAU,
95 ADC_CHANNEL_11 = 0xBU,
96 ADC_CHANNEL_12 = 0xCU,
97 ADC_CHANNEL_13 = 0xDU,
98 ADC_CHANNEL_14 = 0xEU,
99 ADC_CHANNEL_15 = 0xFU,
100 ADC_CHANNEL_16 = 0x10U,
101 ADC_CHANNEL_17 = 0x11U,
102 ADC_CHANNEL_18 = 0x12U,
103 } adc_channel_t;
104
108 typedef enum {
109 ADC_SAMPLETIME_1 = 0x0U,
110 ADC_SAMPLETIME_2 = 0x1U,
111 ADC_SAMPLETIME_4 = 0x2U,
112 ADC_SAMPLETIME_15 = 0x3U,
113 } adc_samp_t;
114
118 typedef enum {
119 ADC_NCH_IDX_1 = 0x1U,
120 ADC_NCH_IDX_2 = 0x2U,
121 ADC_NCH_IDX_3 = 0x3U,
122 ADC_NCH_IDX_4 = 0x4U,
123 ADC_NCH_IDX_5 = 0x5U,
124 ADC_NCH_IDX_6 = 0x6U,
125 ADC_NCH_IDX_7 = 0x7U,
126 ADC_NCH_IDX_8 = 0x8U,
127 ADC_NCH_IDX_9 = 0x9U,
128 ADC_NCH_IDX_10 = 0xAU,
129 ADC_NCH_IDX_11 = 0xBU,
130 ADC_NCH_IDX_12 = 0xCU,
131 ADC_NCH_IDX_13 = 0xDU,
132 ADC_NCH_IDX_14 = 0xEU,
133 ADC_NCH_IDX_15 = 0xFU,
134 ADC_NCH_IDX_16 = 0x10U,
135 } adc_nch_idx_t;
136
140 typedef enum {
141 ADC_ICH_IDX_1 = 0x1U,
142 ADC_ICH_IDX_2 = 0x2U,
143 ADC_ICH_IDX_3 = 0x3U,
144 ADC_ICH_IDX_4 = 0x4U,
145 } adc_ich_idx_t;
146
150 typedef enum {
151 ADC_ANAWTD_NONE = 0x0U,
152 ADC_ANAWTD_SING_NM = 0x800200U,
153 ADC_ANAWTD_SING_IST = 0x400200U,
154 ADC_ANAWTD_SING_NMIST = 0xC00200U,
155 ADC_ANAWTD_ALL_NM = 0x800000U,
156 ADC_ANAWTD_ALL_IST = 0x400000U,
157 ADC_ANAWTD_ALL_NMIST = 0xC00000U,
158 } adc_ana_wdg_t;
159
163 typedef enum {
164 ADC_AWD_EVENT = (1U << 0),
165 } adc_event_type_t;
166
170 typedef enum {
171 ADC_IT_NCH = (1U << 5),
172 ADC_IT_AWD = (1U << 6),
173 ADC_IT_ICH = (1U << 7),
174 ADC_IT_OVR = (1U << 26),
175 } adc_it_t;
176
180 typedef enum {
181 ADC_FLAG_AWD = (1U << 0),
182 ADC_FLAG_NCH = (1U << 1),
183 ADC_FLAG_ICH = (1U << 2),
184 ADC_FLAG_OVR = (1U << 3),
185 ADC_FLAG_NCHS = (1U << 8),
186 ADC_FLAG_ICHS = (1U << 9),
187 } adc_flag_t;
188
192 typedef enum {
193 ADC_CKDIV_1 = 0x0U,
194 ADC_CKDIV_2 = 0x1U,
195 ADC_CKDIV_4 = 0x2U,
196 ADC_CKDIV_8 = 0x3U,
197 ADC_CKDIV_16 = 0x4U,
198 ADC_CKDIV_32 = 0x5U,
199 ADC_CKDIV_64 = 0x6U,
200 ADC_CKDIV_128 = 0x7U,
201 } adc_clk_div_t;
202
206 typedef enum {
207 ADC_NEG_REF_VSS = 0x0U,
208 ADC_NEG_REF_VREFN = 0x1U,
209 } adc_neg_ref_t;
210
214 typedef enum {
215 ADC_POS_REF_VDD = 0x0U,
216 ADC_POS_REF_2V = 0x1U,
217 ADC_POS_REF_VREEFP = 0x2U,
218 ADC_POS_REF_VREEFP_BUF = 0x3U,
219 } adc_pos_ref_t;
220
224 typedef enum {
225 ADC_NCH_NR_1 = 0x0U,
226 ADC_NCH_NR_2 = 0x1U,
227 ADC_NCH_NR_3 = 0x2U,
228 ADC_NCH_NR_4 = 0x3U,
229 ADC_NCH_NR_5 = 0x4U,
230 ADC_NCH_NR_6 = 0x5U,
231 ADC_NCH_NR_7 = 0x6U,
232 ADC_NCH_NR_8 = 0x7U,
233 ADC_NCH_NR_9 = 0x8U,
234 ADC_NCH_NR_10 = 0x9U,
235 ADC_NCH_NR_11 = 0xAU,
236 ADC_NCH_NR_12 = 0xBU,
237 ADC_NCH_NR_13 = 0xCU,
238 ADC_NCH_NR_14 = 0xDU,
239 ADC_NCH_NR_15 = 0xEU,
240 ADC_NCH_NR_16 = 0xFU,
241 } adc_nch_nr_t;
242
246 typedef enum {
247 ADC_ICH_NR_1 = 0x0U,
248 ADC_ICH_NR_2 = 0x1U,
249 ADC_ICH_NR_3 = 0x2U,
250 ADC_ICH_NR_4 = 0x3U,
251 } adc_ich_nr_t;
252
256 typedef enum {
257 ADC_ALL_DISABLE = 0x0U,
258 ADC_NCH_DISC_EN = 0x1U,
259 ADC_ICH_DISC_EN = 0x2U,
260 } adc_disc_mode_t;
261
265 typedef enum {
266 ADC_DISC_NR_1 = 0x0U,
267 ADC_DISC_NR_2 = 0x1U,
268 ADC_DISC_NR_3 = 0x2U,
269 ADC_DISC_NR_4 = 0x3U,
270 ADC_DISC_NR_5 = 0x4U,
271 ADC_DISC_NR_6 = 0x5U,
272 ADC_DISC_NR_7 = 0x6U,
273 ADC_DISC_NR_8 = 0x7U,
274 } adc_disc_nr_t;
275
279 typedef enum {
280 ADC_CONV_BIT_6 = 0x0U,
281 ADC_CONV_BIT_8 = 0x1U,
282 ADC_CONV_BIT_10 = 0x2U,
283 ADC_CONV_BIT_12 = 0x3U,
284 } adc_conv_bit_t;
285
289 typedef enum {
290 ADC_ETS_DISABLE = 0x0U,
291 ADC_ETS_RISE = 0x1U,
292 ADC_ETS_FALL = 0x2U,
293 ADC_ETS_RISE_FALL = 0x3U,
294 } adc_ets_t;
295
304 typedef struct {
305 adc_align_t align;
306 type_func_t scan;
307 type_func_t cont;
308 adc_nch_nr_t nch_nr;
309 adc_disc_mode_t disc;
310 adc_disc_nr_t disc_nr;
311 adc_conv_bit_t data_bit;
312 adc_clk_div_t div;
313 adc_nchesel_t nche_sel;
314 adc_neg_ref_t n_ref;
315 adc_pos_ref_t p_ref;
316 } adc_init_t;
317
321 typedef struct {
322 adc_channel_t ch;
323 adc_nch_idx_t idx;
324 adc_samp_t samp;
325 } adc_nch_conf_t;
326
330 typedef struct {
331 adc_ana_wdg_t mode;
332 adc_channel_t ch;
333 type_func_t interrupt;
334 uint32_t high_thrd;
335 uint32_t low_thrd;
336 } adc_analog_wdg_conf_t;
337
341 typedef struct {
342 adc_channel_t ch;
343 adc_ich_idx_t idx;
344 adc_samp_t samp;
345 uint32_t offset;
346 adc_ich_nr_t nr;
347 type_func_t auto_m;
348 } adc_ich_conf_t;
349
353 typedef struct adc_handle_s {
354 ADC_TypeDef *perh;
355 adc_init_t init;
356 #ifdef ALD_DMA
357 dma_handle_t hdma;
358 pis_handle_t hpis;
359 #endif
360 lock_state_t lock;
361 adc_state_t state;
362 adc_error_t error_code;
364 void (*normal_cplt_cbk)( struct adc_handle_s *arg);
365 void (*insert_cplt_cbk)( struct adc_handle_s *arg);
366 void (*wdg_cbk)( struct adc_handle_s *arg);
367 void (*error_cbk)(struct adc_handle_s *arg);
368 void (*ovr_cbk)(struct adc_handle_s *arg);
369 } adc_handle_t;
370
374 typedef struct {
375 uint32_t time;
376 uint16_t size;
377 uint16_t *buf;
378 adc_neg_ref_t n_ref;
379 adc_pos_ref_t p_ref;
380 adc_channel_t adc_ch;
381 uint8_t dma_ch;
382 TIMER_TypeDef *p_timer;
383 ADC_TypeDef *p_adc;
384 void (*cplt_cbk)( struct adc_handle_s *arg);
386 /* private variable */
387 lock_state_t lock;
388 pis_handle_t h_pis;
389 dma_handle_t h_dma;
390 timer_handle_t h_timer;
391 adc_handle_t h_adc;
392 adc_nch_conf_t config;
393 } adc_timer_config_t;
401 #define ADC_ENABLE(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK))
402 #define ADC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK))
403 #define ADC_NH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK))
404 #define ADC_IH_TRIG_BY_SOFT(handle) (SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK))
405 #define ADC_RESET_HANDLE_STATE(handle) ((handle)->state = ADC_STATE_RESET)
406 #define ADC_VREF_OUT_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK))
407 #define ADC_VREF_OUT_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK))
408 #define ADC_NETS_ENABLE(handle, mode) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, (mode) << ADC_CON1_NETS_POSS))
409 #define ADC_IETS_ENABLE(handle, mode) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, (mode) << ADC_CON1_IETS_POSS))
410 #define ADC_NETS_DISABLE(handle) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_NETS_MSK, 0 << ADC_CON1_NETS_POSS))
411 #define ADC_IETS_DISABLE(handle) (MODIFY_REG((handle)->perh->CON1, ADC_CON1_IETS_MSK, 0 << ADC_CON1_IETS_POSS))
412 #define ADC_SPEED_HIGH_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK))
413 #define ADC_SPEED_HIGH_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK))
414 #define ADC_CALIBRATE_ENABLE(handle) (SET_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK))
415 #define ADC_CALIBRATE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK))
416
423 #define IS_ADC_ICH_IDX_TYPE(x) ((x) <= ADC_ICH_IDX_4)
424 #define IS_ADC_NCH_IDX_TYPE(x) ((x) <= ADC_NCH_IDX_16)
425 #define IS_ADC_SAMPLING_TIMES_TYPE(x) (((x) == ADC_SAMPLETIME_1) || \
426 ((x) == ADC_SAMPLETIME_2) || \
427 ((x) == ADC_SAMPLETIME_4) || \
428 ((x) == ADC_SAMPLETIME_15))
429 #define IS_ADC_CHANNELS_TYPE(x) ((x) <= ADC_CHANNEL_18)
430 #define IS_ADC_DATA_ALIGN_TYPE(x) (((x) == ADC_DATAALIGN_RIGHT) || \
431 ((x) == ADC_DATAALIGN_LEFT))
432 #define IS_ADC_ANALOG_WTD_MODE_TYPE(x) (((x) == ADC_ANAWTD_NONE) || \
433 ((x) == ADC_ANAWTD_SING_NM) || \
434 ((x) == ADC_ANAWTD_SING_IST) || \
435 ((x) == ADC_ANAWTD_SING_NMIST) || \
436 ((x) == ADC_ANAWTD_ALL_NM) || \
437 ((x) == ADC_ANAWTD_ALL_IST) || \
438 ((x) == ADC_ANAWTD_ALL_NMIST))
439 #define IS_ADC_IT_TYPE(x) (((x) == ADC_IT_NCH) || \
440 ((x) == ADC_IT_AWD) || \
441 ((x) == ADC_IT_ICH) || \
442 ((x) == ADC_IT_OVR ))
443 #define IS_ADC_FLAGS_TYPE(x) (((x) == ADC_FLAG_AWD) || \
444 ((x) == ADC_FLAG_NCH) || \
445 ((x) == ADC_FLAG_ICH) || \
446 ((x) == ADC_FLAG_OVR) || \
447 ((x) == ADC_FLAG_NCHS) || \
448 ((x) == ADC_FLAG_ICHS))
449 #define IS_ADC_CLK_DIV_TYPE(x) (((x) == ADC_CKDIV_1) || \
450 ((x) == ADC_CKDIV_2) || \
451 ((x) == ADC_CKDIV_4) || \
452 ((x) == ADC_CKDIV_8) || \
453 ((x) == ADC_CKDIV_16) || \
454 ((x) == ADC_CKDIV_32) || \
455 ((x) == ADC_CKDIV_64) || \
456 ((x) == ADC_CKDIV_128))
457 #define IS_ADC_NEG_REF_VOLTAGE_TYPE(x) (((x) == ADC_NEG_REF_VSS ) || \
458 ((x) == ADC_NEG_REF_VREFN ))
459 #define IS_POS_REF_VOLTAGE_TYPE(x) (((x) == ADC_POS_REF_VDD) || \
460 ((x) == ADC_POS_REF_2V) || \
461 ((x) == ADC_POS_REF_VREEFP) || \
462 ((x) == ADC_POS_REF_VREEFP_BUF))
463 #define IS_ADC_NCH_NR_TYPE(x) ((x) <= ADC_NCH_NR_16)
464 #define IS_ADC_ICH_NR_TYPE(x) ((x) <= ADC_ICH_NR_4)
465 #define IS_ADC_DISC_NR_TYPE(x) ((x) <= ADC_DISC_NR_8)
466 #define IS_ADC_CONV_BIT_TYPE(x) (((x) == ADC_CONV_BIT_12) || \
467 ((x) == ADC_CONV_BIT_6) || \
468 ((x) == ADC_CONV_BIT_8) || \
469 ((x) == ADC_CONV_BIT_10))
470 #define IS_ADC_TYPE(x) (((x) == ADC0) || \
471 ((x) == ADC1))
472 #define IS_ADC_NCHESEL_MODE_TYPE(x) (((x) == ADC_NCHESEL_MODE_ALL) || \
473 ((x) == ADC_NCHESEL_MODE_ONE))
474 #define IS_ADC_EVENT_TYPE(x) ((x) == ADC_AWD_EVENT)
475 #define IS_ADC_IST_OFFSET_TYPE(x) ((x) <= 0xfff)
476 #define IS_HTR_TYPE(x) ((x) <= 0xfff)
477 #define IS_LTR_TYPE(x) ((x) <= 0xfff)
478
489 ald_status_t ald_adc_init(adc_handle_t *hperh);
490 ald_status_t ald_adc_reset(adc_handle_t *hperh);
498 ald_status_t ald_adc_normal_start(adc_handle_t *hperh);
499 ald_status_t ald_adc_normal_stop(adc_handle_t *hperh);
500 ald_status_t ald_adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout);
501 ald_status_t ald_adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout);
502 ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh);
503 ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh);
504 #ifdef ALD_DMA
505 ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel);
506 ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh, uint8_t channel);
507 ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config);
508 #endif
509 uint32_t ald_adc_normal_get_value(adc_handle_t *hperh);
510 ald_status_t ald_adc_insert_start(adc_handle_t *hperh);
511 ald_status_t ald_adc_insert_stop(adc_handle_t *hperh);
512 ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout);
513 ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh);
514 ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh);
515 uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_idx_t ih_rank);
516 void ald_adc_irq_handler(adc_handle_t *hperh);
524 ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t *config);
525 ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t *config);
526 ald_status_t ald_adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config);
527 void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state);
528 it_status_t ald_adc_get_it_status(adc_handle_t *hperh, adc_it_t it);
529 flag_status_t ald_adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag);
530 void ald_adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag);
538 uint32_t ald_adc_get_state(adc_handle_t *hperh);
539 uint32_t ald_adc_get_error(adc_handle_t *hperh);
555 #ifdef __cplusplus
556 extern "C" }
557 #endif
558
559 #endif /* __ALD_ADC_H */
adc_flag_t
adc_flag_t
ADC flags definition.
Definition: ald_adc.h:180
ald_adc_stop_by_dma
ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh, uint8_t channel)
Stop ADC conversion of normal group (and insert group in case of auto_insert mode), disable ADC DMA transfer, disable ADC peripheral.
Definition: ald_adc.c:385
ADC_STATE_TIMEOUT
Definition: ald_adc.h:47
ADC_NCH_IDX_11
Definition: ald_adc.h:129
adc_handle_s
ADC handle Structure definition.
Definition: ald_adc.h:353
ADC_CKDIV_4
Definition: ald_adc.h:195
adc_channel_t
adc_channel_t
ADC channels.
Definition: ald_adc.h:83
adc_timer_config_t::adc_ch
adc_channel_t adc_ch
Definition: ald_adc.h:380
ADC_NCH_NR_8
Definition: ald_adc.h:232
adc_timer_config_t::h_dma
dma_handle_t h_dma
Definition: ald_adc.h:389
ADC_ANAWTD_SING_IST
Definition: ald_adc.h:153
ADC_NCH_NR_4
Definition: ald_adc.h:228
ADC_CHANNEL_15
Definition: ald_adc.h:99
adc_pos_ref_t
adc_pos_ref_t
ADC positive reference voltage definition.
Definition: ald_adc.h:214
ADC_CHANNEL_2
Definition: ald_adc.h:86
ADC_NCH_NR_16
Definition: ald_adc.h:240
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
ADC_CONV_BIT_12
Definition: ald_adc.h:283
adc_ich_conf_t
ADC Configuration insert Channel structure definition.
Definition: ald_adc.h:341
ADC_DISC_NR_3
Definition: ald_adc.h:268
ADC_NCH_NR_5
Definition: ald_adc.h:229
ADC_ICH_IDX_1
Definition: ald_adc.h:141
ald_adc_start_by_dma
ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel)
Enables ADC, starts conversion of normal group and transfers result through DMA.
Definition: ald_adc.c:339
ADC_NCH_IDX_10
Definition: ald_adc.h:128
dma_handle_t
DMA handle structure definition.
Definition: ald_dma.h:297
ADC_ANAWTD_SING_NM
Definition: ald_adc.h:152
ADC_IT_AWD
Definition: ald_adc.h:172
adc_init_t::scan
type_func_t scan
Definition: ald_adc.h:306
adc_nch_idx_t
adc_nch_idx_t
ADC index channel in normal group.
Definition: ald_adc.h:118
adc_ets_t
adc_ets_t
ADC external trigger mode choose.
Definition: ald_adc.h:289
ADC_NCH_IDX_5
Definition: ald_adc.h:123
ald_adc_normal_poll_for_conversion
ald_status_t ald_adc_normal_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout)
Wait for normal group conversion to be completed.
Definition: ald_adc.c:236
ADC_NCH_IDX_15
Definition: ald_adc.h:133
adc_timer_config_t::size
uint16_t size
Definition: ald_adc.h:376
ADC_ERROR_DMA
Definition: ald_adc.h:61
adc_init_t::disc
adc_disc_mode_t disc
Definition: ald_adc.h:309
ald_adc_init
ald_status_t ald_adc_init(adc_handle_t *hperh)
Initializes the ADC peripheral and normal group according to parameters specified in structure "adc_h...
Definition: ald_adc.c:74
adc_handle_s::hdma
dma_handle_t hdma
Definition: ald_adc.h:357
adc_timer_config_t
Timer trigger adc config structure definition.
Definition: ald_adc.h:374
adc_init_t::nche_sel
adc_nchesel_t nche_sel
Definition: ald_adc.h:313
ADC_CHANNEL_16
Definition: ald_adc.h:100
adc_nch_conf_t
Structure definition of ADC channel for normal group.
Definition: ald_adc.h:321
adc_handle_s::wdg_cbk
void(* wdg_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:366
type_func_t
type_func_t
Definition: type.h:47
adc_ich_conf_t::ch
adc_channel_t ch
Definition: ald_adc.h:342
ADC_STATE_ERROR
Definition: ald_adc.h:48
ADC_IT_ICH
Definition: ald_adc.h:173
adc_ich_nr_t
adc_ich_nr_t
ADC numbers of insert conversion channals.
Definition: ald_adc.h:246
ADC_FLAG_ICH
Definition: ald_adc.h:183
ADC_DATAALIGN_LEFT
Definition: ald_adc.h:69
ADC_DISC_NR_2
Definition: ald_adc.h:267
ADC_SAMPLETIME_15
Definition: ald_adc.h:112
adc_nch_conf_t::ch
adc_channel_t ch
Definition: ald_adc.h:322
adc_handle_s::perh
ADC_TypeDef * perh
Definition: ald_adc.h:354
adc_init_t::data_bit
adc_conv_bit_t data_bit
Definition: ald_adc.h:311
ADC_CONV_BIT_6
Definition: ald_adc.h:280
ADC_NCH_IDX_2
Definition: ald_adc.h:120
ADC_ANAWTD_ALL_IST
Definition: ald_adc.h:156
adc_timer_config_t::n_ref
adc_neg_ref_t n_ref
Definition: ald_adc.h:378
ADC_ERROR_OVR
Definition: ald_adc.h:60
ADC_STATE_BUSY_N
Definition: ald_adc.h:49
ald_adc_normal_stop_by_it
ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh)
Stop ADC conversion of normal group (and insert group in case of auto_injection mode), disable interrution of end-of-conversion, disable ADC peripheral.
Definition: ald_adc.c:317
adc_ana_wdg_t
adc_ana_wdg_t
ADC analog watchdog mode.
Definition: ald_adc.h:150
adc_event_type_t
adc_event_type_t
ADC Event type.
Definition: ald_adc.h:163
ADC_CONV_BIT_8
Definition: ald_adc.h:281
ADC_NEG_REF_VSS
Definition: ald_adc.h:207
adc_handle_s::ovr_cbk
void(* ovr_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:368
ADC_NCH_IDX_14
Definition: ald_adc.h:132
adc_timer_config_t::buf
uint16_t * buf
Definition: ald_adc.h:377
ADC_CHANNEL_3
Definition: ald_adc.h:87
ADC_DISC_NR_4
Definition: ald_adc.h:269
adc_nch_conf_t::samp
adc_samp_t samp
Definition: ald_adc.h:324
adc_init_t::div
adc_clk_div_t div
Definition: ald_adc.h:312
adc_state_t
adc_state_t
ADC State structures definition.
Definition: ald_adc.h:43
adc_timer_config_t::time
uint32_t time
Definition: ald_adc.h:375
adc_analog_wdg_conf_t::interrupt
type_func_t interrupt
Definition: ald_adc.h:333
ald_adc_get_error
uint32_t ald_adc_get_error(adc_handle_t *hperh)
Return the ADC error code.
Definition: ald_adc.c:1006
ADC_CHANNEL_8
Definition: ald_adc.h:92
ald_adc_reset
ald_status_t ald_adc_reset(adc_handle_t *hperh)
Deinitialize the ADC peripheral registers to their default reset values.
Definition: ald_adc.c:150
ADC_FLAG_AWD
Definition: ald_adc.h:181
adc_it_t
adc_it_t
ADC interrupts definition.
Definition: ald_adc.h:170
ADC_NCH_NR_12
Definition: ald_adc.h:236
pis_handle_s
PIS Handle Structure definition.
Definition: ald_pis.h:418
adc_ich_conf_t::samp
adc_samp_t samp
Definition: ald_adc.h:344
ald_adc_insert_start
ald_status_t ald_adc_insert_start(adc_handle_t *hperh)
Enables ADC, starts conversion of insert group. Interruptions enabled in this function: None...
Definition: ald_adc.c:546
ADC_POS_REF_VREEFP_BUF
Definition: ald_adc.h:218
adc_samp_t
adc_samp_t
ADC sampling times.
Definition: ald_adc.h:108
ADC_NCH_NR_11
Definition: ald_adc.h:235
ADC_CKDIV_16
Definition: ald_adc.h:197
ADC_NCH_NR_6
Definition: ald_adc.h:230
adc_ich_idx_t
adc_ich_idx_t
ADC index channel in insert group.
Definition: ald_adc.h:140
ADC_ICH_NR_2
Definition: ald_adc.h:248
timer_handle_s
TIMER time base handle structure definition.
Definition: ald_timer.h:182
ald_adc_timer_trigger_adc_by_dma
ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config)
Config Timer trigger adc function.
Definition: ald_adc.c:425
adc_ich_conf_t::auto_m
type_func_t auto_m
Definition: ald_adc.h:347
ADC_NEG_REF_VREFN
Definition: ald_adc.h:208
utils.h
This file contains the Utilities functions/types for the driver.
adc_init_t::cont
type_func_t cont
Definition: ald_adc.h:307
ADC_ETS_RISE
Definition: ald_adc.h:291
ADC_FLAG_ICHS
Definition: ald_adc.h:186
ADC_CHANNEL_7
Definition: ald_adc.h:91
adc_analog_wdg_conf_t::high_thrd
uint32_t high_thrd
Definition: ald_adc.h:334
adc_nch_conf_t::idx
adc_nch_idx_t idx
Definition: ald_adc.h:323
ald_adc_get_it_status
it_status_t ald_adc_get_it_status(adc_handle_t *hperh, adc_it_t it)
Checks whether the specified ADC interrupt has occurred or not.
Definition: ald_adc.c:936
adc_neg_ref_t
adc_neg_ref_t
ADC negative reference voltage definition.
Definition: ald_adc.h:206
adc_error_t
adc_error_t
ADC Error Code.
Definition: ald_adc.h:57
ADC_CHANNEL_10
Definition: ald_adc.h:94
ald_adc_normal_stop
ald_status_t ald_adc_normal_stop(adc_handle_t *hperh)
Stop ADC conversion of normal group (and insert channels in case of auto_injection mode)...
Definition: ald_adc.c:214
adc_handle_s::insert_cplt_cbk
void(* insert_cplt_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:365
it_status_t
enum flag_status_t it_status_t
adc_handle_s::init
adc_init_t init
Definition: ald_adc.h:355
adc_analog_wdg_conf_t
ADC Configuration analog watchdog definition.
Definition: ald_adc.h:330
ADC_DISC_NR_7
Definition: ald_adc.h:272
adc_ich_conf_t::nr
adc_ich_nr_t nr
Definition: ald_adc.h:346
ADC_FLAG_OVR
Definition: ald_adc.h:184
ADC_NCH_IDX_7
Definition: ald_adc.h:125
ald_adc_insert_start_by_it
ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh)
Enables ADC, starts conversion of insert group with interruption.
Definition: ald_adc.c:616
ADC_CHANNEL_4
Definition: ald_adc.h:88
ADC_ANAWTD_ALL_NM
Definition: ald_adc.h:155
adc_timer_config_t::p_timer
TIMER_TypeDef * p_timer
Definition: ald_adc.h:382
ADC_CKDIV_1
Definition: ald_adc.h:193
ADC_DISC_NR_8
Definition: ald_adc.h:273
adc_ich_conf_t::idx
adc_ich_idx_t idx
Definition: ald_adc.h:343
adc_analog_wdg_conf_t::mode
adc_ana_wdg_t mode
Definition: ald_adc.h:331
adc_handle_s::hpis
pis_handle_t hpis
Definition: ald_adc.h:358
adc_init_t::align
adc_align_t align
Definition: ald_adc.h:305
ald_adc_analog_wdg_config
ald_status_t ald_adc_analog_wdg_config(adc_handle_t *hperh, adc_analog_wdg_conf_t *config)
Configures the analog watchdog.
Definition: ald_adc.c:870
ADC_SAMPLETIME_1
Definition: ald_adc.h:109
ADC_IT_NCH
Definition: ald_adc.h:171
ADC_STATE_BUSY
Definition: ald_adc.h:46
adc_timer_config_t::p_adc
ADC_TypeDef * p_adc
Definition: ald_adc.h:383
ald_adc_insert_poll_for_conversion
ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout)
Wait for insert group conversion to be completed.
Definition: ald_adc.c:587
ADC_AWD_EVENT
Definition: ald_adc.h:164
adc_align_t
adc_align_t
ADC data alignment.
Definition: ald_adc.h:67
ADC_CHANNEL_14
Definition: ald_adc.h:98
ADC_ANAWTD_SING_NMIST
Definition: ald_adc.h:154
ADC_NCH_IDX_13
Definition: ald_adc.h:131
lock_state_t
lock_state_t
Definition: type.h:58
adc_init_t::nch_nr
adc_nch_nr_t nch_nr
Definition: ald_adc.h:308
ADC_STATE_READY
Definition: ald_adc.h:45
ADC_ETS_DISABLE
Definition: ald_adc.h:290
ald_dma.h
DMA module Library.
ald_adc_insert_stop
ald_status_t ald_adc_insert_stop(adc_handle_t *hperh)
Stop conversion of insert channels. Disable ADC peripheral if no normal conversion is on going...
Definition: ald_adc.c:571
ADC_CHANNEL_12
Definition: ald_adc.h:96
ADC_ICH_IDX_3
Definition: ald_adc.h:143
ADC_ANAWTD_ALL_NMIST
Definition: ald_adc.h:157
ADC_CHANNEL_0
Definition: ald_adc.h:84
ald_pis.h
Header file of PIS driver.
ADC_CHANNEL_5
Definition: ald_adc.h:89
ADC_NCH_IDX_16
Definition: ald_adc.h:134
adc_init_t
ADC trigger conversion mode.
Definition: ald_adc.h:304
ADC_NCH_IDX_9
Definition: ald_adc.h:127
ald_adc_insert_get_value
uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_idx_t idx)
Get ADC insert group conversion result.
Definition: ald_adc.c:661
ADC_ICH_DISC_EN
Definition: ald_adc.h:259
adc_timer_config_t::h_timer
timer_handle_t h_timer
Definition: ald_adc.h:390
ADC_ICH_NR_4
Definition: ald_adc.h:250
ADC_CKDIV_8
Definition: ald_adc.h:196
ADC_NCH_IDX_8
Definition: ald_adc.h:126
ADC_ERROR_INTERNAL
Definition: ald_adc.h:59
ADC_ANAWTD_NONE
Definition: ald_adc.h:151
ADC_FLAG_NCHS
Definition: ald_adc.h:185
adc_timer_config_t::lock
lock_state_t lock
Definition: ald_adc.h:387
ADC_NCH_IDX_12
Definition: ald_adc.h:130
ADC_NCH_NR_2
Definition: ald_adc.h:226
ADC_NCH_NR_15
Definition: ald_adc.h:239
adc_clk_div_t
adc_clk_div_t
ADC CLD DIV definition.
Definition: ald_adc.h:192
ADC_FLAG_NCH
Definition: ald_adc.h:182
ADC_ICH_NR_3
Definition: ald_adc.h:249
ald_adc_normal_channel_config
ald_status_t ald_adc_normal_channel_config(adc_handle_t *hperh, adc_nch_conf_t *config)
Configures the the selected channel to be linked to the normal group.
Definition: ald_adc.c:750
ald_adc_insert_channel_config
ald_status_t ald_adc_insert_channel_config(adc_handle_t *hperh, adc_ich_conf_t *config)
Configures the the selected channel to be linked to the insert group.
Definition: ald_adc.c:798
ADC_DISC_NR_1
Definition: ald_adc.h:266
adc_timer_config_t::h_pis
pis_handle_t h_pis
Definition: ald_adc.h:388
ald_adc_clear_flag_status
void ald_adc_clear_flag_status(adc_handle_t *hperh, adc_flag_t flag)
Clear the specified ADC pending flags.
Definition: ald_adc.c:972
ADC_CKDIV_32
Definition: ald_adc.h:198
ald_adc_poll_for_event
ald_status_t ald_adc_poll_for_event(adc_handle_t *hperh, adc_event_type_t event_type, uint32_t timeout)
Poll for conversion event.
Definition: ald_adc.c:266
ADC_POS_REF_VDD
Definition: ald_adc.h:215
ADC_POS_REF_2V
Definition: ald_adc.h:216
ald_adc_interrupt_config
void ald_adc_interrupt_config(adc_handle_t *hperh, adc_it_t it, type_func_t state)
Enables or disables the specified ADC interrupts.
Definition: ald_adc.c:913
ADC_CKDIV_2
Definition: ald_adc.h:194
adc_disc_mode_t
adc_disc_mode_t
ADC discontinuous mode choose.
Definition: ald_adc.h:256
adc_init_t::p_ref
adc_pos_ref_t p_ref
Definition: ald_adc.h:315
adc_init_t::n_ref
adc_neg_ref_t n_ref
Definition: ald_adc.h:314
ald_adc_normal_get_value
uint32_t ald_adc_normal_get_value(adc_handle_t *hperh)
Get ADC normal group conversion result.
Definition: ald_adc.c:532
ADC_ICH_NR_1
Definition: ald_adc.h:247
adc_conv_bit_t
adc_conv_bit_t
ADC resolution of conversion.
Definition: ald_adc.h:279
ADC_CKDIV_64
Definition: ald_adc.h:199
ald_adc_get_flag_status
flag_status_t ald_adc_get_flag_status(adc_handle_t *hperh, adc_flag_t flag)
Check whether the specified ADC flag is set or not.
Definition: ald_adc.c:955
ADC_NCH_NR_9
Definition: ald_adc.h:233
ADC_CHANNEL_6
Definition: ald_adc.h:90
ADC_ICH_IDX_4
Definition: ald_adc.h:144
ADC_DISC_NR_5
Definition: ald_adc.h:270
ADC_POS_REF_VREEFP
Definition: ald_adc.h:217
ADC_ETS_FALL
Definition: ald_adc.h:292
ADC_ALL_DISABLE
Definition: ald_adc.h:257
ADC_NCHESEL_MODE_ONE
Definition: ald_adc.h:77
ADC_SAMPLETIME_4
Definition: ald_adc.h:111
ADC_ETS_RISE_FALL
Definition: ald_adc.h:293
adc_timer_config_t::h_adc
adc_handle_t h_adc
Definition: ald_adc.h:391
adc_timer_config_t::p_ref
adc_pos_ref_t p_ref
Definition: ald_adc.h:379
ald_adc_irq_handler
void ald_adc_irq_handler(adc_handle_t *hperh)
Handles ADC interrupt request.
Definition: ald_adc.c:695
adc_ich_conf_t::offset
uint32_t offset
Definition: ald_adc.h:345
ADC_NCH_IDX_6
Definition: ald_adc.h:124
ald_adc_get_state
uint32_t ald_adc_get_state(adc_handle_t *hperh)
return the ADC state
Definition: ald_adc.c:995
adc_handle_t
struct adc_handle_s adc_handle_t
ADC handle Structure definition.
flag_status_t
flag_status_t
Definition: type.h:37
ADC_CONV_BIT_10
Definition: ald_adc.h:282
ADC_NCH_NR_10
Definition: ald_adc.h:234
ADC_CKDIV_128
Definition: ald_adc.h:200
ADC_CHANNEL_13
Definition: ald_adc.h:97
ald_adc_normal_start_by_it
ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh)
Enables ADC, starts conversion of normal group with interruption. Interruptions enabled in this funct...
Definition: ald_adc.c:296
adc_nchesel_t
adc_nchesel_t
ADC config hannal trigger the EOC IT mode.
Definition: ald_adc.h:75
ADC_DISC_NR_6
Definition: ald_adc.h:271
ADC_CHANNEL_18
Definition: ald_adc.h:102
ADC_STATE_BUSY_I
Definition: ald_adc.h:50
ADC_NCH_NR_14
Definition: ald_adc.h:238
ald_adc_normal_start
ald_status_t ald_adc_normal_start(adc_handle_t *hperh)
Enables ADC, starts conversion of normal group.
Definition: ald_adc.c:193
adc_timer_config_t::config
adc_nch_conf_t config
Definition: ald_adc.h:392
ald_adc_insert_stop_by_it
ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh)
Stop conversion of insert channels, disable interruption of end-of-conversion. Disable ADC peripheral...
Definition: ald_adc.c:644
adc_handle_s::lock
lock_state_t lock
Definition: ald_adc.h:360
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
adc_nch_nr_t
adc_nch_nr_t
ADC numbers of normal conversion channals.
Definition: ald_adc.h:224
ADC_NCH_IDX_1
Definition: ald_adc.h:119
ADC_NCH_IDX_4
Definition: ald_adc.h:122
ADC_NCH_NR_3
Definition: ald_adc.h:227
adc_handle_s::error_cbk
void(* error_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:367
adc_analog_wdg_conf_t::ch
adc_channel_t ch
Definition: ald_adc.h:332
ADC_IT_OVR
Definition: ald_adc.h:174
ADC_SAMPLETIME_2
Definition: ald_adc.h:110
adc_timer_config_t::dma_ch
uint8_t dma_ch
Definition: ald_adc.h:381
adc_init_t::disc_nr
adc_disc_nr_t disc_nr
Definition: ald_adc.h:310
ADC_NCH_NR_13
Definition: ald_adc.h:237
ADC_NCH_NR_7
Definition: ald_adc.h:231
ADC_CHANNEL_17
Definition: ald_adc.h:101
ADC_NCH_DISC_EN
Definition: ald_adc.h:258
ADC_NCHESEL_MODE_ALL
Definition: ald_adc.h:76
adc_handle_s::error_code
adc_error_t error_code
Definition: ald_adc.h:362
ald_timer.h
TIMER module driver. This is the common part of the TIMER initialization.
ADC_STATE_RESET
Definition: ald_adc.h:44
ADC_NCH_IDX_3
Definition: ald_adc.h:121
adc_disc_nr_t
adc_disc_nr_t
ADC numbers of channals in discontinuous conversion mode.
Definition: ald_adc.h:265
ADC_CHANNEL_1
Definition: ald_adc.h:85
ADC_DATAALIGN_RIGHT
Definition: ald_adc.h:68
ADC_CHANNEL_11
Definition: ald_adc.h:95
ADC_NCH_NR_1
Definition: ald_adc.h:225
ADC_CHANNEL_9
Definition: ald_adc.h:93
ADC_STATE_BUSY_WDG
Definition: ald_adc.h:51
adc_analog_wdg_conf_t::low_thrd
uint32_t low_thrd
Definition: ald_adc.h:335
ADC_ICH_IDX_2
Definition: ald_adc.h:142
ADC_ERROR_NONE
Definition: ald_adc.h:58


ALD User Manual: D:/svn/src/ald_bkpc.c Source File

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  • svn
  • src
ald_bkpc.c
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1
17 #include "ald_bkpc.h"
18 #include "ald_rtc.h"
19
20
29 #ifdef ALD_BKPC
30
57 void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
58 {
59 assert_param(IS_BKPC_WAKEUP_PORT(port));
60 assert_param(IS_BKPC_WAKEUP_LEVEL(level));
61
62 if (port == PMU_STANDBY_PORT_SEL_NONE) {
63 BKPC_UNLOCK();
64 CLEAR_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK);
65 SET_BIT(BKPC->CR, BKPC_CR_MRST_WKPEN_MSK);
66 BKPC_LOCK();
67 return;
68 }
69
70 BKPC_UNLOCK();
71 SET_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK | BKPC_CR_MRST_WKPEN_MSK);
72 MODIFY_REG(BKPC->CR, BKPC_CR_WKPS_MSK, port << BKPC_CR_WKPS_POSS);
73 MODIFY_REG(BKPC->CR, BKPC_CR_WKPOL_MSK, level << BKPC_CR_WKPOL_POS);
74 BKPC_LOCK();
75
76 return;
77 }
78
84 void ald_bkpc_rtc_clock_config(bkpc_preh_clk_t clock)
85 {
86 assert_param(IS_BKPC_PREH_CLOCK(clock));
87
88 BKPC_UNLOCK();
89 MODIFY_REG(BKPC->PCCR, BKPC_PCCR_RTCCS_MSK, clock << BKPC_PCCR_RTCCS_POSS);
90 BKPC_LOCK();
91
92 return;
93 }
94
100 void ald_bkpc_tsense_clock_config(bkpc_preh_clk_t clock)
101 {
102 assert_param(IS_BKPC_PREH_CLOCK(clock));
103
104 BKPC_UNLOCK();
105 MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TSENSECS_MSK, clock << BKPC_PCCR_TSENSECS_POSS);
106 BKPC_LOCK();
107
108 return;
109 }
135 void ald_bkpc_write_ram(uint8_t idx, uint32_t value)
136 {
137 assert_param(IS_BKPC_RAM_IDX(idx));
138
139 RTC_UNLOCK();
140 WRITE_REG(RTC->BKPR[idx], value);
141 RTC_LOCK();
142
143 return;
144 }
145
151 uint32_t ald_bkpc_read_ram(uint8_t idx)
152 {
153 assert_param(IS_BKPC_RAM_IDX(idx));
154
155 return READ_REG(RTC->BKPR[idx]);
156 }
164 #endif /* ALD_BKPC */
165
bkpc_wakeup_port_t
bkpc_wakeup_port_t
Standby wakeup port select.
Definition: ald_bkpc.h:111
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
READ_REG
#define READ_REG(reg)
Definition: type.h:73
IS_BKPC_PREH_CLOCK
#define IS_BKPC_PREH_CLOCK(x)
Definition: ald_bkpc.h:150
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
ald_bkpc_standby_wakeup_config
void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
Configure standby wakeup in backup field.
Definition: ald_bkpc.c:57
ald_bkpc_rtc_clock_config
void ald_bkpc_rtc_clock_config(bkpc_preh_clk_t clock)
Configure rtc clock in backup field.
Definition: ald_bkpc.c:84
ald_rtc.h
Header file of RTC Module driver.
ald_bkpc.h
Header file of BKPC module driver.
ald_bkpc_tsense_clock_config
void ald_bkpc_tsense_clock_config(bkpc_preh_clk_t clock)
Configure tsense clock in backup field.
Definition: ald_bkpc.c:100
IS_BKPC_WAKEUP_PORT
#define IS_BKPC_WAKEUP_PORT(x)
Definition: ald_bkpc.h:139
IS_BKPC_WAKEUP_LEVEL
#define IS_BKPC_WAKEUP_LEVEL(x)
Definition: ald_bkpc.h:148
BKPC_LOCK
#define BKPC_LOCK()
Definition: ald_bkpc.h:38
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
BKPC_UNLOCK
#define BKPC_UNLOCK()
Definition: ald_bkpc.h:39
ald_bkpc_write_ram
void ald_bkpc_write_ram(uint8_t idx, uint32_t value)
Write data into backup ram.
Definition: ald_bkpc.c:135
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
bkpc_wakeup_level_t
bkpc_wakeup_level_t
Standby wakeup level.
Definition: ald_bkpc.h:126
IS_BKPC_RAM_IDX
#define IS_BKPC_RAM_IDX(x)
Definition: ald_bkpc.h:154
bkpc_preh_clk_t
bkpc_preh_clk_t
BKPC preipheral clock select.
Definition: ald_bkpc.h:101
PMU_STANDBY_PORT_SEL_NONE
Definition: ald_bkpc.h:120
ald_bkpc_read_ram
uint32_t ald_bkpc_read_ram(uint8_t idx)
Read data from backup ram.
Definition: ald_bkpc.c:151


ALD User Manual: D:/svn/src/ald_bkpc.h Source File

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  • svn
  • src
ald_bkpc.h
Go to the documentation of this file.
1
17 #ifndef __ALD_BKPC_H__
18 #define __ALD_BKPC_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25
26
38 #define BKPC_LOCK() (WRITE_REG(BKPC->PROT, 0U))
39 #define BKPC_UNLOCK() (WRITE_REG(BKPC->PROT, 0x9669AA55U))
40 #define BKPC_LRC_ENABLE() \
41 do { \
42 BKPC_UNLOCK(); \
43 SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \
44 BKPC_LOCK(); \
45 } while (0)
46 #define BKPC_LRC_DISABLE() \
47 do { \
48 BKPC_UNLOCK(); \
49 CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK); \
50 BKPC_LOCK(); \
51 } while (0)
52 #define BKPC_LOSM_ENABLE() \
53 do { \
54 BKPC_UNLOCK(); \
55 SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK); \
56 BKPC_LOCK(); \
57 } while (0)
58 #define BKPC_LOSM_DISABLE() \
59 do { \
60 BKPC_UNLOCK(); \
61 CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\
62 BKPC_LOCK(); \
63 } while (0)
64 #define BKPC_LOSC_ENABLE() \
65 do { \
66 BKPC_UNLOCK(); \
67 SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK); \
68 BKPC_LOCK(); \
69 } while (0)
70 #define BKPC_LOSC_DISABLE() \
71 do { \
72 BKPC_UNLOCK(); \
73 CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\
74 BKPC_LOCK(); \
75 } while (0)
76
77
78 #define BKPC_MRST_WAKEUP_ENABLE() \
79 do { \
80 BKPC_UNLOCK(); \
81 SET_BIT(BKPC->CR, BKPC_CR_MRST_WKPEN_MSK); \
82 BKPC_LOCK(); \
83 } while (0)
84 #define BKPC_MRST_WAKEUP_DISABLE() \
85 do { \
86 BKPC_UNLOCK(); \
87 CLEAR_BIT(BKPC->CR, BKPC_CR_MRST_WKPEN_MSK); \
88 BKPC_LOCK(); \
89 } while (0)
90
101 typedef enum {
102 BKPC_PREH_CLK_LOSM = 0x0U,
103 BKPC_PREH_CLK_LRC = 0x1U,
104 BKPC_PREH_CLK_HRC_1M = 0x2U,
105 BKPC_PREH_CLK_HOSC_1M = 0x3U,
106 } bkpc_preh_clk_t;
107
111 typedef enum {
112 PMU_STANDBY_PORT_SEL_PA0 = 0x0U,
113 PMU_STANDBY_PORT_SEL_PA1 = 0x1U,
114 PMU_STANDBY_PORT_SEL_PA2 = 0x2U,
115 PMU_STANDBY_PORT_SEL_PA3 = 0x3U,
116 PMU_STANDBY_PORT_SEL_PA4 = 0x4U,
117 PMU_STANDBY_PORT_SEL_PA5 = 0x5U,
118 PMU_STANDBY_PORT_SEL_PA6 = 0x6U,
119 PMU_STANDBY_PORT_SEL_PA7 = 0x7U,
120 PMU_STANDBY_PORT_SEL_NONE = 0xFU,
121 } bkpc_wakeup_port_t;
122
126 typedef enum {
127 PMU_STANDBY_LEVEL_HIGH = 0x0U,
128 PMU_STANDBY_LEVEL_LOW = 0x1U,
129 } bkpc_wakeup_level_t;
130
139 #define IS_BKPC_WAKEUP_PORT(x) (((x) == PMU_STANDBY_PORT_SEL_PA0) || \
140 ((x) == PMU_STANDBY_PORT_SEL_PA1) || \
141 ((x) == PMU_STANDBY_PORT_SEL_PA2) || \
142 ((x) == PMU_STANDBY_PORT_SEL_PA3) || \
143 ((x) == PMU_STANDBY_PORT_SEL_PA4) || \
144 ((x) == PMU_STANDBY_PORT_SEL_PA5) || \
145 ((x) == PMU_STANDBY_PORT_SEL_PA6) || \
146 ((x) == PMU_STANDBY_PORT_SEL_PA7) || \
147 ((x) == PMU_STANDBY_PORT_SEL_NONE))
148 #define IS_BKPC_WAKEUP_LEVEL(x) (((x) == PMU_STANDBY_LEVEL_HIGH) || \
149 ((x) == PMU_STANDBY_LEVEL_LOW))
150 #define IS_BKPC_PREH_CLOCK(x) (((x) == BKPC_PREH_CLK_LOSM) || \
151 ((x) == BKPC_PREH_CLK_LRC) || \
152 ((x) == BKPC_PREH_CLK_HRC_1M) || \
153 ((x) == BKPC_PREH_CLK_HOSC_1M))
154 #define IS_BKPC_RAM_IDX(x) ((x) < 32)
155
165 /* control functions */
166 extern void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level);
167 extern void ald_bkpc_rtc_clock_config(bkpc_preh_clk_t clock);
168 extern void ald_bkpc_tsense_clock_config(bkpc_preh_clk_t clock);
175 /* IO operation functions */
176 extern void ald_bkpc_write_ram(uint8_t idx, uint32_t value);
177 extern uint32_t ald_bkpc_read_ram(uint8_t idx);
192 #ifdef __cplusplus
193 }
194 #endif
195
196 #endif /* __ALD_BKPC_H__ */
bkpc_wakeup_port_t
bkpc_wakeup_port_t
Standby wakeup port select.
Definition: ald_bkpc.h:111
PMU_STANDBY_PORT_SEL_PA0
Definition: ald_bkpc.h:112
PMU_STANDBY_PORT_SEL_PA5
Definition: ald_bkpc.h:117
PMU_STANDBY_PORT_SEL_PA3
Definition: ald_bkpc.h:115
BKPC_PREH_CLK_LRC
Definition: ald_bkpc.h:103
PMU_STANDBY_PORT_SEL_PA6
Definition: ald_bkpc.h:118
PMU_STANDBY_PORT_SEL_PA7
Definition: ald_bkpc.h:119
ald_bkpc_standby_wakeup_config
void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
Configure standby wakeup in backup field.
Definition: ald_bkpc.c:57
ald_bkpc_rtc_clock_config
void ald_bkpc_rtc_clock_config(bkpc_preh_clk_t clock)
Configure rtc clock in backup field.
Definition: ald_bkpc.c:84
PMU_STANDBY_LEVEL_LOW
Definition: ald_bkpc.h:128
utils.h
This file contains the Utilities functions/types for the driver.
BKPC_PREH_CLK_HOSC_1M
Definition: ald_bkpc.h:105
PMU_STANDBY_PORT_SEL_PA4
Definition: ald_bkpc.h:116
PMU_STANDBY_PORT_SEL_PA2
Definition: ald_bkpc.h:114
PMU_STANDBY_LEVEL_HIGH
Definition: ald_bkpc.h:127
ald_bkpc_tsense_clock_config
void ald_bkpc_tsense_clock_config(bkpc_preh_clk_t clock)
Configure tsense clock in backup field.
Definition: ald_bkpc.c:100
PMU_STANDBY_PORT_SEL_PA1
Definition: ald_bkpc.h:113
BKPC_PREH_CLK_HRC_1M
Definition: ald_bkpc.h:104
BKPC_PREH_CLK_LOSM
Definition: ald_bkpc.h:102
ald_bkpc_write_ram
void ald_bkpc_write_ram(uint8_t idx, uint32_t value)
Write data into backup ram.
Definition: ald_bkpc.c:135
bkpc_wakeup_level_t
bkpc_wakeup_level_t
Standby wakeup level.
Definition: ald_bkpc.h:126
bkpc_preh_clk_t
bkpc_preh_clk_t
BKPC preipheral clock select.
Definition: ald_bkpc.h:101
PMU_STANDBY_PORT_SEL_NONE
Definition: ald_bkpc.h:120
ald_bkpc_read_ram
uint32_t ald_bkpc_read_ram(uint8_t idx)
Read data from backup ram.
Definition: ald_bkpc.c:151


ALD User Manual: D:/svn/src/ald_calc.c Source File

  • D:
  • svn
  • src
ald_calc.c
Go to the documentation of this file.
1
17 #include "ald_calc.h"
18
19
28 #ifdef ALD_CALC
29
51 uint32_t ald_calc_sqrt(uint32_t data)
52 {
53 WRITE_REG(CALC->RDCND, data);
54 while (READ_BIT(CALC->SQRTSR, CALC_SQRTSR_BUSY_MSK));
55
56 return READ_REG(CALC->SQRTRES);
57 }
58
66 uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder)
67 {
68 CLEAR_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK);
69 SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK);
70 WRITE_REG(CALC->DIVDR, dividend);
71 WRITE_REG(CALC->DIVSR, divisor);
72
73 while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK));
74
75 *remainder = READ_REG(CALC->DIVRR);
76 return READ_REG(CALC->DIVQR);
77 }
78
86 int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder)
87 {
88 SET_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK);
89 SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK);
90 WRITE_REG(CALC->DIVDR, dividend);
91 WRITE_REG(CALC->DIVSR, divisor);
92
93 while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK));
94
95 *remainder = READ_REG(CALC->DIVRR);
96 return READ_REG(CALC->DIVQR);
97 }
98
103 flag_status_t ald_calc_get_dz_status(void)
104 {
105 if (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_DZ_MSK))
106 return SET;
107
108 return RESET;
109 }
110
114 #endif /* ALD_CALC */
115
ald_calc_get_dz_status
flag_status_t ald_calc_get_dz_status(void)
Get the flag of divisor is zero.
Definition: ald_calc.c:103
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
READ_REG
#define READ_REG(reg)
Definition: type.h:73
SET
Definition: type.h:39
RESET
Definition: type.h:38
ald_calc.h
Header file of CALC module driver.
ald_calc_div
uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder)
Calculating division.
Definition: ald_calc.c:66
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
ald_calc_sqrt
uint32_t ald_calc_sqrt(uint32_t data)
Square root operation.
Definition: ald_calc.c:51
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
ald_calc_div_sign
int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder)
Calculating division.
Definition: ald_calc.c:86
flag_status_t
flag_status_t
Definition: type.h:37


ALD User Manual: D:/svn/src/ald_calc.h Source File

  • D:
  • svn
  • src
ald_calc.h
Go to the documentation of this file.
1
17 #ifndef __ALD_CALC_H__
18 #define __ALD_CALC_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25
26
38 extern uint32_t ald_calc_sqrt(uint32_t data);
39 extern uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder);
40 extern int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder);
41 extern flag_status_t ald_calc_get_dz_status(void);
53 #ifdef __cplusplus
54 }
55 #endif
56
57 #endif /* __ALD_CALC_H__ */
ald_calc_get_dz_status
flag_status_t ald_calc_get_dz_status(void)
Get the flag of divisor is zero.
Definition: ald_calc.c:103
utils.h
This file contains the Utilities functions/types for the driver.
ald_calc_div
uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder)
Calculating division.
Definition: ald_calc.c:66
ald_calc_sqrt
uint32_t ald_calc_sqrt(uint32_t data)
Square root operation.
Definition: ald_calc.c:51
ald_calc_div_sign
int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder)
Calculating division.
Definition: ald_calc.c:86
flag_status_t
flag_status_t
Definition: type.h:37


ALD User Manual: D:/svn/src/ald_can.c Source File

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  • svn
  • src
ald_can.c
Go to the documentation of this file.
1
69 #include "ald_can.h"
70
71
80 #ifdef ALD_CAN
81
85 static void can_rx_fifo_release(can_handle_t *hperh, can_rx_fifo_t num);
86 static ald_status_t __can_send_by_it(can_handle_t *hperh, uint8_t err);
87 static ald_status_t __can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num);
119 ald_status_t ald_can_init(can_handle_t *hperh)
120 {
121 uint32_t tickstart = 0;
122
123 assert_param(IS_CAN_ALL(hperh->perh));
124 assert_param(IS_FUNC_STATE(hperh->init.ttcm));
125 assert_param(IS_FUNC_STATE(hperh->init.abom));
126 assert_param(IS_FUNC_STATE(hperh->init.awk));
127 assert_param(IS_FUNC_STATE(hperh->init.abom));
128 assert_param(IS_FUNC_STATE(hperh->init.rfom));
129 assert_param(IS_FUNC_STATE(hperh->init.txmp));
130 assert_param(IS_CAN_MODE(hperh->init.mode));
131 assert_param(IS_CAN_SJW(hperh->init.sjw));
132 assert_param(IS_CAN_BS1(hperh->init.seg1));
133 assert_param(IS_CAN_BS2(hperh->init.seg2));
134 assert_param(IS_CAN_PRESCALER(hperh->init.psc));
135
136 if (hperh->state == CAN_STATE_RESET)
137 hperh->lock = UNLOCK;
138
139 hperh->state = CAN_STATE_BUSY;
140 tickstart = ald_get_tick();
141
142 CLEAR_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK);
143 SET_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK);
144
145 while (!READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) {
146 if ((ald_get_tick() - tickstart) > CAN_TIMEOUT_VALUE) {
147 hperh->state = CAN_STATE_TIMEOUT;
148 __UNLOCK(hperh);
149
150 return TIMEOUT;
151 }
152 }
153
154 MODIFY_REG(hperh->perh->CON, CAN_CON_TTCEN_MSK, hperh->init.ttcm << CAN_CON_TTCEN_POS);
155 MODIFY_REG(hperh->perh->CON, CAN_CON_ABOFFEN_MSK, hperh->init.abom << CAN_CON_ABOFFEN_POS);
156 MODIFY_REG(hperh->perh->CON, CAN_CON_AWKEN_MSK, hperh->init.awk << CAN_CON_AWKEN_POS);
157 MODIFY_REG(hperh->perh->CON, CAN_CON_ARTXDIS_MSK, hperh->init.artx << CAN_CON_ARTXDIS_POS);
158 MODIFY_REG(hperh->perh->CON, CAN_CON_RXFOPM_MSK, hperh->init.rfom << CAN_CON_RXFOPM_POS);
159 MODIFY_REG(hperh->perh->CON, CAN_CON_TXMP_MSK, hperh->init.txmp << CAN_CON_TXMP_POS);
160 MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_LOOP_MSK, (hperh->init.mode & 0x1) << CAN_BTIME_LOOP_POS);
161 MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_SILENT_MSK, ((hperh->init.mode >> 1) & 0x1) << CAN_BTIME_SILENT_POS);
162 MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_RESJW_MSK, hperh->init.sjw << CAN_BTIME_RESJW_POSS);
163 MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_SEG1_MSK, hperh->init.seg1 << CAN_BTIME_SEG1_POSS);
164 MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_SEG2_MSK, hperh->init.seg2 << CAN_BTIME_SEG2_POSS);
165 MODIFY_REG(hperh->perh->BTIME, CAN_BTIME_BPSC_MSK, (hperh->init.psc - 1) << CAN_BTIME_BPSC_POSS);
166
167 CLEAR_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK);
168 tickstart = ald_get_tick();
169
170 while (READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) {
171 if ((ald_get_tick() - tickstart) > CAN_TIMEOUT_VALUE) {
172 hperh->state = CAN_STATE_TIMEOUT;
173 __UNLOCK(hperh);
174
175 return TIMEOUT;
176 }
177 }
178
179 hperh->err = CAN_ERROR_NONE;
180 hperh->state = CAN_STATE_READY;
181
182 return OK;
183 }
184
193 ald_status_t ald_can_filter_config(can_handle_t *hperh, can_filter_t *config)
194 {
195 uint32_t pos;
196
197 assert_param(IS_CAN_ALL(hperh->perh));
198 assert_param(IS_CAN_FILTER_NUMBER(config->number));
199 assert_param(IS_CAN_FILTER_MODE(config->mode));
200 assert_param(IS_CAN_FILTER_SCALE(config->scale));
201 assert_param(IS_CAN_FILTER_FIFO(config->fifo));
202 assert_param(IS_FUNC_STATE(config->active));
203
204 pos = 1 << config->number;
205 SET_BIT(hperh->perh->FLTCON, CAN_FLTCON_FLTINI_MSK);
206 CLEAR_BIT(hperh->perh->FLTGO, pos);
207
208 if (config->scale == CAN_FILTER_SCALE_16) {
209 CLEAR_BIT(hperh->perh->FLTWS, pos);
210 hperh->perh->Filter[config->number].FLT1 =
211 ((0xFFFF & config->mask_id_low) << 16) |
212 (0xFFFF & config->id_low);
213
214 hperh->perh->Filter[config->number].FLT2 =
215 ((0xFFFF & config->mask_id_high) << 16) |
216 (0xFFFF & config->id_high);
217 }
218
219 if (config->scale == CAN_FILTER_SCALE_32) {
220 SET_BIT(hperh->perh->FLTWS, pos);
221 hperh->perh->Filter[config->number].FLT1 =
222 ((0xFFFF & config->id_high) << 16) |
223 (0xFFFF & config->id_low);
224 hperh->perh->Filter[config->number].FLT2 =
225 ((0xFFFF & config->mask_id_high) << 16) |
226 (0xFFFF & config->mask_id_low);
227 }
228
229 MODIFY_REG(hperh->perh->FLTM, pos, config->mode << config->number);
230 MODIFY_REG(hperh->perh->FLTAS, pos, config->fifo << config->number);
231 MODIFY_REG(hperh->perh->FLTGO, pos, config->active << config->number);
232 CLEAR_BIT(hperh->perh->FLTCON, CAN_FLTCON_FLTINI_MSK);
233
234 return OK;
235 }
236
242 void ald_can_reset(can_handle_t *hperh)
243 {
244 assert_param(IS_CAN_ALL(hperh->perh));
245
246 hperh->state = CAN_STATE_RESET;
247 __UNLOCK(hperh);
248
249 return;
250 }
251
280 ald_status_t ald_can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout)
281 {
282 uint32_t tick;
283 can_tx_mailbox_t idx;
284
285 assert_param(IS_CAN_ALL(hperh->perh));
286 assert_param(IS_CAN_IDTYPE(msg->type));
287 assert_param(IS_CAN_RTR(msg->rtr));
288 assert_param(IS_CAN_DATA_LEN(msg->len));
289
290 __LOCK(hperh);
291 SET_BIT(hperh->state, CAN_STATE_TX_MASK);
292
293 if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK))
294 idx = CAN_TX_MAILBOX_0;
295 else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK))
296 idx = CAN_TX_MAILBOX_1;
297 else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK))
298 idx = CAN_TX_MAILBOX_2;
299 else
300 idx = CAN_TX_MAILBOX_NONE;
301
302 if (idx == CAN_TX_MAILBOX_NONE) {
303 hperh->state = CAN_STATE_ERROR;
304 __UNLOCK(hperh);
305 return ERROR;
306 }
307
308 CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK);
309 MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_IDE_MSK, msg->type << CAN_TXID0_IDE_POS);
310 MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_RTR_MSK, msg->rtr << CAN_TXID0_RTR_POS);
311
312 if (msg->type == CAN_ID_STD) {
313 assert_param(IS_CAN_STDID(msg->std));
314 MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, msg->std << CAN_TXID0_STDID_POSS);
315 CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK);
316 }
317 else {
318 assert_param(IS_CAN_EXTID(msg->ext));
319 MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, ((msg->ext >> 18) & 0x7FF) << CAN_TXID0_STDID_POSS);
320 MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK, (msg->ext & 0x3FFFF) << CAN_TXID0_EXID_POSS);
321 }
322 MODIFY_REG(hperh->perh->TxMailBox[idx].TXFCON, CAN_TXFCON0_DLEN_MSK, (msg->len & 0xF) << CAN_TXFCON0_DLEN_POSS);
323 WRITE_REG(hperh->perh->TxMailBox[idx].TXDL, msg->data[0] | (msg->data[1] << 8) | (msg->data[2] << 16) | (msg->data[3] << 24));
324 WRITE_REG(hperh->perh->TxMailBox[idx].TXDH, msg->data[4] | (msg->data[5] << 8) | (msg->data[6] << 16) | (msg->data[7] << 24));
325 SET_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK);
326 tick = ald_get_tick();
327
328 while (!(ald_can_get_tx_status(hperh, idx))) {
329 if ((timeout == 0) || ((ald_get_tick() - tick) > timeout)) {
330 hperh->state = CAN_STATE_TIMEOUT;
331 __UNLOCK(hperh);
332 return TIMEOUT;
333 }
334 }
335
336 CLEAR_BIT(hperh->state, CAN_STATE_TX_MASK);
337 __UNLOCK(hperh);
338 return OK;
339 }
340
347 ald_status_t ald_can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg)
348 {
349 uint8_t idx = CAN_TX_MAILBOX_NONE;
350
351 assert_param(IS_CAN_ALL(hperh->perh));
352 assert_param(IS_CAN_IDTYPE(msg->type));
353 assert_param(IS_CAN_RTR(msg->rtr));
354 assert_param(IS_CAN_DATA_LEN(msg->len));
355
356 if ((hperh->state & CAN_STATE_TX_MASK) || ((hperh->state & 0xF) != CAN_STATE_READY))
357 return BUSY;
358
359 if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK))
360 idx = CAN_TX_MAILBOX_0;
361 else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK))
362 idx = CAN_TX_MAILBOX_1;
363 else if (READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK))
364 idx = CAN_TX_MAILBOX_2;
365 else
366 idx = CAN_TX_MAILBOX_NONE;
367
368 if (idx == CAN_TX_MAILBOX_NONE)
369 return BUSY;
370
371 CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK);
372 MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_IDE_MSK, msg->type << CAN_TXID0_IDE_POS);
373 MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_RTR_MSK, msg->rtr << CAN_TXID0_RTR_POS);
374
375 if (msg->type == CAN_ID_STD) {
376 assert_param(IS_CAN_STDID(msg->std));
377 MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, msg->std << CAN_TXID0_STDID_POSS);
378 CLEAR_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK);
379 }
380 else {
381 assert_param(IS_CAN_EXTID(msg->ext));
382 MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_STDID_MSK, ((msg->ext >> 18) & 0x7FF) << CAN_TXID0_STDID_POSS);
383 MODIFY_REG(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_EXID_MSK, (msg->ext & 0x3FFFF) << CAN_TXID0_EXID_POSS);
384 }
385
386 MODIFY_REG(hperh->perh->TxMailBox[idx].TXFCON, CAN_TXFCON0_DLEN_MSK, (msg->len & 0xF) << CAN_TXFCON0_DLEN_POSS);
387 WRITE_REG(hperh->perh->TxMailBox[idx].TXDL, msg->data[0] | (msg->data[1] << 8) | (msg->data[2] << 16) | (msg->data[3] << 24));
388 WRITE_REG(hperh->perh->TxMailBox[idx].TXDH, msg->data[4] | (msg->data[5] << 8) | (msg->data[6] << 16) | (msg->data[7] << 24));
389
390 SET_BIT(hperh->state, CAN_STATE_TX_MASK);
391
392 ald_can_interrupt_config(hperh, CAN_IT_WARN, ENABLE);
393 ald_can_interrupt_config(hperh, CAN_IT_PERR, ENABLE);
394 ald_can_interrupt_config(hperh, CAN_IT_BOF, ENABLE);
395 ald_can_interrupt_config(hperh, CAN_IT_PRERR, ENABLE);
396 ald_can_interrupt_config(hperh, CAN_IT_ERR, ENABLE);
397 ald_can_interrupt_config(hperh, CAN_IT_TXM, ENABLE);
398
399 SET_BIT(hperh->perh->TxMailBox[idx].TXID, CAN_TXID0_TXMREQ_MSK);
400 return OK;
401 }
402
411 ald_status_t ald_can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout)
412 {
413 uint32_t tick, stid, exid;
414
415 assert_param(IS_CAN_ALL(hperh->perh));
416 assert_param(IS_CAN_FIFO(num));
417 assert_param(msg != NULL);
418
419 __LOCK(hperh);
420 SET_BIT(hperh->state, num == CAN_RX_FIFO0 ? CAN_STATE_RX0_MASK : CAN_STATE_RX1_MASK);
421 tick = ald_get_tick();
422
423 while (CAN_RX_MSG_PENDING(hperh, num) == 0) {
424 if ((timeout == 0) || ((ald_get_tick() - tick) > timeout)) {
425 hperh->state = CAN_STATE_TIMEOUT;
426 __UNLOCK(hperh);
427 return TIMEOUT;
428 }
429 }
430
431 stid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_STDID_MSK, CAN_RXF0ID_STDID_POSS);
432 exid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_EXID_MSK, CAN_RXF0ID_EXID_POSS);
433 msg->type = (can_id_type_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_IDE_MSK, CAN_RXF0ID_IDE_POS);
434
435 if (msg->type == CAN_ID_STD)
436 msg->std = stid;
437 else
438 msg->ext = (stid << 18) | exid;
439
440 msg->rtr = (can_remote_req_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_RTR_MSK, CAN_RXF0ID_RTR_POS);
441 msg->len = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_DLEN_MSK, CAN_RXF0INF_DLEN_POSS);
442 msg->fmi = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_FLTIDX_MSK, CAN_RXF0INF_FLTIDX_POSS);
443 msg->data[0] = hperh->perh->RxFIFO[num].RXFDL & 0xFF;
444 msg->data[1] = (hperh->perh->RxFIFO[num].RXFDL >> 8) & 0xFF;
445 msg->data[2] = (hperh->perh->RxFIFO[num].RXFDL >> 16) & 0xFF;
446 msg->data[3] = (hperh->perh->RxFIFO[num].RXFDL >> 24) & 0xFF;
447 msg->data[4] = hperh->perh->RxFIFO[num].RXFDH & 0xFF;
448 msg->data[5] = (hperh->perh->RxFIFO[num].RXFDH >> 8) & 0xFF;
449 msg->data[6] = (hperh->perh->RxFIFO[num].RXFDH >> 16) & 0xFF;
450 msg->data[7] = (hperh->perh->RxFIFO[num].RXFDH >> 24) & 0xFF;
451
452 can_rx_fifo_release(hperh, num);
453 CLEAR_BIT(hperh->state, num == CAN_RX_FIFO0 ? CAN_STATE_RX0_MASK : CAN_STATE_RX1_MASK);
454 __UNLOCK(hperh);
455
456 return OK;
457 }
458
466 ald_status_t ald_can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg)
467 {
468 assert_param(IS_CAN_ALL(hperh->perh));
469 assert_param(IS_CAN_FIFO(num));
470 assert_param(msg != NULL);
471
472 if (num == CAN_RX_FIFO0) {
473 if ((hperh->state & CAN_STATE_RX0_MASK) || ((hperh->state & 0xF) != CAN_STATE_READY))
474 return BUSY;
475
476 SET_BIT(hperh->state, CAN_STATE_RX0_MASK);
477 hperh->rx0_msg = msg;
478 }
479 else {
480 if ((hperh->state & CAN_STATE_RX1_MASK) || ((hperh->state & 0xF) != CAN_STATE_READY))
481 return BUSY;
482
483 SET_BIT(hperh->state, CAN_STATE_RX1_MASK);
484 hperh->rx1_msg = msg;
485 }
486
487 ald_can_interrupt_config(hperh, CAN_IT_WARN, ENABLE);
488 ald_can_interrupt_config(hperh, CAN_IT_PERR, ENABLE);
489 ald_can_interrupt_config(hperh, CAN_IT_BOF, ENABLE);
490 ald_can_interrupt_config(hperh, CAN_IT_PRERR, ENABLE);
491 ald_can_interrupt_config(hperh, CAN_IT_ERR, ENABLE);
492
493 if (num == CAN_RX_FIFO0)
494 ald_can_interrupt_config(hperh, CAN_IT_FP0, ENABLE);
495 else
496 ald_can_interrupt_config(hperh, CAN_IT_FP1, ENABLE);
497
498 return OK;
499 }
532 ald_status_t ald_can_sleep(can_handle_t *hperh)
533 {
534 uint32_t tick;
535
536 assert_param(IS_CAN_ALL(hperh->perh));
537
538 __LOCK(hperh);
539 hperh->state = CAN_STATE_BUSY;
540
541 CLEAR_BIT(hperh->perh->CON, CAN_CON_INIREQ_MSK);
542 SET_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK);
543 tick = ald_get_tick();
544
545 while ((!(READ_BIT(hperh->perh->STAT, CAN_STAT_SLPSTAT_MSK))) || READ_BIT(hperh->perh->STAT, CAN_STAT_INISTAT_MSK)) {
546 if ((ald_get_tick() - tick) > CAN_TIMEOUT_VALUE) {
547 hperh->state = CAN_STATE_TIMEOUT;
548 __UNLOCK(hperh);
549 return TIMEOUT;
550 }
551 }
552
553 hperh->state = CAN_STATE_READY;
554 __UNLOCK(hperh);
555
556 return OK;
557 }
558
565 ald_status_t ald_can_wake_up(can_handle_t *hperh)
566 {
567 uint32_t tick;
568
569 assert_param(IS_CAN_ALL(hperh->perh));
570
571 __LOCK(hperh);
572 hperh->state = CAN_STATE_BUSY;
573
574 CLEAR_BIT(hperh->perh->CON, CAN_CON_SLPREQ_MSK);
575 tick = ald_get_tick();
576
577 while (READ_BIT(hperh->perh->STAT, CAN_STAT_SLPSTAT_MSK)) {
578 if ((ald_get_tick() - tick) > CAN_TIMEOUT_VALUE) {
579 hperh->state = CAN_STATE_TIMEOUT;
580 __UNLOCK(hperh);
581 return TIMEOUT;
582 }
583 }
584
585 hperh->state = CAN_STATE_READY;
586 __UNLOCK(hperh);
587
588 return OK;
589 }
590
596 void ald_can_irq_handler(can_handle_t* hperh)
597 {
598 if (ald_can_get_it_status(hperh, CAN_IT_TXM)) {
599 if ((ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_0))
600 || (ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_1))
601 || (ald_can_get_tx_status(hperh, CAN_TX_MAILBOX_2)))
602 __can_send_by_it(hperh, 0);
603 if (hperh->perh->TXSTAT & CAN_TXSTAT_M0TXERR_MSK) {
604 SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M0REQC_MSK);
605 __can_send_by_it(hperh, 1);
606 }
607 if (hperh->perh->TXSTAT & CAN_TXSTAT_M1TXERR_MSK) {
608 SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M1REQC_MSK);
609 __can_send_by_it(hperh, 1);
610 }
611 if (hperh->perh->TXSTAT & CAN_TXSTAT_M2TXERR_MSK) {
612 SET_BIT(hperh->perh->TXSTATC, CAN_TXSTATC_M2REQC_MSK);
613 __can_send_by_it(hperh, 1);
614 }
615 }
616
617 if ((ald_can_get_it_status(hperh, CAN_IT_FP0))
618 && (CAN_RX_MSG_PENDING(hperh, CAN_RX_FIFO0) != 0))
619 __can_recv_by_it(hperh, CAN_RX_FIFO0);
620
621 if ((ald_can_get_it_status(hperh, CAN_IT_FP1))
622 && (CAN_RX_MSG_PENDING(hperh, CAN_RX_FIFO1) != 0))
623 __can_recv_by_it(hperh, CAN_RX_FIFO1);
624
625 if ((ald_can_get_flag_status(hperh, CAN_FLAG_WARN))
626 && (ald_can_get_it_status(hperh, CAN_IT_WARN))
627 && (ald_can_get_it_status(hperh, CAN_IT_ERR)))
628 hperh->err |= CAN_ERROR_EWG;
629
630 if ((ald_can_get_flag_status(hperh, CAN_FLAG_PERR))
631 && (ald_can_get_it_status(hperh, CAN_IT_PERR))
632 && (ald_can_get_it_status(hperh, CAN_IT_ERR)))
633 hperh->err |= CAN_ERROR_EPV;
634
635 if ((ald_can_get_flag_status(hperh, CAN_FLAG_BOF))
636 && (ald_can_get_it_status(hperh, CAN_IT_BOF))
637 && (ald_can_get_it_status(hperh, CAN_IT_ERR)))
638 hperh->err |= CAN_ERROR_BOF;
639
640 if (READ_BIT(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK)
641 && (ald_can_get_it_status(hperh, CAN_IT_PRERR))
642 && (ald_can_get_it_status(hperh, CAN_IT_ERR))) {
643
644 switch (READ_BITS(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK, CAN_ERRSTAT_PRERRF_POSS)) {
645 case(1):
646 hperh->err |= CAN_ERROR_STF;
647 break;
648 case(2):
649 hperh->err |= CAN_ERROR_FOR;
650 break;
651 case(3):
652 hperh->err |= CAN_ERROR_ACK;
653 break;
654 case(4):
655 hperh->err |= CAN_ERROR_BR;
656 break;
657 case(5):
658 hperh->err |= CAN_ERROR_BD;
659 break;
660 case(6):
661 hperh->err |= CAN_ERROR_CRC;
662 break;
663 default:
664 break;
665 }
666
667 CLEAR_BIT(hperh->perh->ERRSTAT, CAN_ERRSTAT_PRERRF_MSK);
668
669 if (READ_BIT(hperh->perh->IE, CAN_IE_TXMEIE_MSK))
670 ald_can_interrupt_config(hperh, CAN_IT_TXM, DISABLE);
671
672 if (READ_BIT(hperh->perh->IE, CAN_IE_F0PIE_MSK))
673 ald_can_interrupt_config(hperh, CAN_IT_FP0, DISABLE);
674
675 if (READ_BIT(hperh->perh->IE, CAN_IE_F1PIE_MSK))
676 ald_can_interrupt_config(hperh, CAN_IT_FP1, DISABLE);
677 }
678
679 if ((ald_can_get_flag_status(hperh, CAN_FLAG_ERR)) && (hperh->err == CAN_ERROR_NONE))
680 hperh->err = CAN_ERROR_UNK;
681
682 if (hperh->err != CAN_ERROR_NONE) {
683 SET_BIT(hperh->perh->IFC, CAN_IFC_ERRIFC_MSK);
684 hperh->state = CAN_STATE_READY;
685
686 if (hperh->error_cbk != NULL)
687 hperh->error_cbk(hperh);
688 }
689 }
690
697 type_bool_t ald_can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box)
698 {
699 assert_param(IS_CAN_ALL(hperh->perh));
700 assert_param(IS_CAN_TX_MAILBOX(box));
701
702 switch (box) {
703 case CAN_TX_MAILBOX_0:
704 if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0REQC_MSK))
705 return FALSE;
706 if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0TXC_MSK))
707 return FALSE;
708 if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM0EF_MSK))
709 return FALSE;
710
711 return TRUE;
712
713 case CAN_TX_MAILBOX_1:
714 if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1REQC_MSK))
715 return FALSE;
716 if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1TXC_MSK))
717 return FALSE;
718 if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM1EF_MSK))
719 return FALSE;
720
721 return TRUE;
722
723 case CAN_TX_MAILBOX_2:
724 if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2REQC_MSK))
725 return FALSE;
726 if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2TXC_MSK))
727 return FALSE;
728 if (!READ_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_TXM2EF_MSK))
729 return FALSE;
730
731 return TRUE;
732
733 default:
734 break;
735 }
736
737 return FALSE;
738 }
739
746 void ald_can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box)
747 {
748 assert_param(IS_CAN_ALL(hperh->perh));
749 assert_param(IS_CAN_TX_MAILBOX(box));
750
751 switch (box) {
752 case CAN_TX_MAILBOX_0:
753 SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M0STPREQ_MSK);
754 break;
755 case CAN_TX_MAILBOX_1:
756 SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M1STPREQ_MSK);
757 break;
758 case CAN_TX_MAILBOX_2:
759 SET_BIT(hperh->perh->TXSTAT, CAN_TXSTAT_M2STPREQ_MSK);
760 break;
761 default:
762 break;
763 }
764
765 return;
766 }
767
779 void ald_can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state)
780 {
781 assert_param(IS_CAN_ALL(hperh->perh));
782 assert_param(IS_CAN_IT(it));
783 assert_param(IS_FUNC_STATE(state));
784
785 if (state == ENABLE)
786 SET_BIT(hperh->perh->IE, it);
787 else
788 CLEAR_BIT(hperh->perh->IE, it);
789
790 return;
791 }
792
802 it_status_t ald_can_get_it_status(can_handle_t *hperh, can_it_t it)
803 {
804 assert_param(IS_CAN_ALL(hperh->perh));
805 assert_param(IS_CAN_IT(it));
806
807 if (READ_BIT(hperh->perh->IE, it))
808 return SET;
809
810 return RESET;
811 }
812
822 flag_status_t ald_can_get_flag_status(can_handle_t *hperh, can_flag_t flag)
823 {
824 uint32_t idx = (flag >> 20) & 0x7;
825 uint32_t _flag = flag & 0xFF8FFFFF;
826
827 assert_param(IS_CAN_GET_FLAG(flag));
828
829 switch (idx) {
830 case 0:
831 if (READ_BIT(hperh->perh->STAT, _flag))
832 return SET;
833
834 break;
835 case 1:
836 if (READ_BIT(hperh->perh->TXSTAT, _flag))
837 return SET;
838
839 break;
840 case 2:
841 if (READ_BIT(hperh->perh->RXF0, _flag))
842 return SET;
843
844 break;
845 case 3:
846 if (READ_BIT(hperh->perh->RXF1, _flag))
847 return SET;
848
849 break;
850 case 4:
851 if (READ_BIT(hperh->perh->ERRSTAT, _flag))
852 return SET;
853
854 break;
855 default:
856 break;
857 }
858
859 return RESET;
860 }
861
867 void can_clear_flag(can_handle_t *hperh, can_flag_t flag)
868 {
869 uint32_t idx = ((uint32_t)flag >> 20) & 0x7;
870 uint32_t _flag = flag & 0xFF8FFFFFU;
871
872 assert_param(IS_CAN_CLEAR_FLAG(flag));
873
874 switch (idx) {
875 case 0:
876 WRITE_REG(hperh->perh->IFC, _flag);
877 break;
878 case 1:
879 WRITE_REG(hperh->perh->TXSTATC, _flag);
880 break;
881 case 2:
882 WRITE_REG(hperh->perh->RXF0C, _flag);
883 break;
884 case 3:
885 WRITE_REG(hperh->perh->RXF1C, _flag);
886 break;
887 default:
888 break;
889 }
890
891 return;
892 }
917 can_state_t ald_can_get_state(can_handle_t *hperh)
918 {
919 return hperh->state;
920 }
921
927 can_error_t ald_can_get_error(can_handle_t *hperh)
928 {
929 return hperh->err;
930 }
931
950 static void can_rx_fifo_release(can_handle_t *hperh, can_rx_fifo_t num)
951 {
952 if (num == CAN_RX_FIFO0)
953 SET_BIT(hperh->perh->RXF0, CAN_RXF0_FREE_MSK);
954 else
955 SET_BIT(hperh->perh->RXF1, CAN_RXF1_FREE_MSK);
956 }
957
958
965 static ald_status_t __can_send_by_it(can_handle_t *hperh, uint8_t err)
966 {
967 ald_can_interrupt_config(hperh, CAN_IT_TXM, DISABLE);
968
969 if (hperh->state == CAN_STATE_BUSY_TX) {
970 ald_can_interrupt_config(hperh, CAN_IT_WARN, DISABLE);
971 ald_can_interrupt_config(hperh, CAN_IT_PERR, DISABLE);
972 ald_can_interrupt_config(hperh, CAN_IT_BOF, DISABLE);
973 ald_can_interrupt_config(hperh, CAN_IT_PRERR, DISABLE);
974 ald_can_interrupt_config(hperh, CAN_IT_ERR, DISABLE);
975 }
976
977 CLEAR_BIT(hperh->state, CAN_STATE_TX_MASK);
978
979 if ((err == 0) && (hperh->tx_cplt_cbk))
980 hperh->tx_cplt_cbk(hperh);
981
982 if ((err) && (hperh->error_cbk != NULL)) {
983 hperh->err = CAN_ERROR_UNK;
984 hperh->error_cbk(hperh);
985 }
986
987 return OK;
988 }
989
998 static int __can_rx_check(can_handle_t *hperh, can_rx_fifo_t num)
999 {
1000 int i;
1001
1002 if (!(hperh->perh->RESERVED0[0] & 0x200000U))
1003 return 0;
1004
1005 if (num == CAN_RX_FIFO0) {
1006 for (i = 0; i < 3; ++i) {
1007 if (hperh->perh->RXF0 & 0x3)
1008 SET_BIT(hperh->perh->RXF0, CAN_RXF0_FREE_MSK);
1009 else
1010 break;
1011 }
1012 }
1013 else {
1014 for (i = 0; i < 3; ++i) {
1015 if (hperh->perh->RXF1 & 0x3)
1016 SET_BIT(hperh->perh->RXF1, CAN_RXF1_FREE_MSK);
1017 else
1018 break;
1019 }
1020 }
1021
1022 hperh->perh->RESERVED0[0] |= 0x200000U;
1023 return 1;
1024 }
1025
1032 static ald_status_t __can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num)
1033 {
1034 uint32_t stid, exid;
1035 can_rx_msg_t *_msg;
1036
1037 if (__can_rx_check(hperh, num))
1038 return ERROR;
1039
1040 stid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_STDID_MSK, CAN_RXF0ID_STDID_POSS);
1041 exid = READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_EXID_MSK, CAN_RXF0ID_EXID_POSS);
1042
1043 _msg = num == CAN_RX_FIFO0 ? hperh->rx0_msg : hperh->rx1_msg;
1044 _msg->type = (can_id_type_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_IDE_MSK, CAN_RXF0ID_IDE_POS);
1045
1046 if (_msg->type == CAN_ID_STD)
1047 _msg->std = stid;
1048 else
1049 _msg->ext = (stid << 18) | exid;
1050
1051 _msg->rtr = (can_remote_req_t)READ_BITS(hperh->perh->RxFIFO[num].RXFID, CAN_RXF0ID_RTR_MSK, CAN_RXF0ID_RTR_POS);
1052 _msg->len = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_DLEN_MSK, CAN_RXF0INF_DLEN_POSS);
1053 _msg->fmi = READ_BITS(hperh->perh->RxFIFO[num].RXFINF, CAN_RXF0INF_FLTIDX_MSK, CAN_RXF0INF_FLTIDX_POSS);
1054 _msg->data[0] = hperh->perh->RxFIFO[num].RXFDL & 0xFF;
1055 _msg->data[1] = (hperh->perh->RxFIFO[num].RXFDL >> 8) & 0xFF;
1056 _msg->data[2] = (hperh->perh->RxFIFO[num].RXFDL >> 16) & 0xFF;
1057 _msg->data[3] = (hperh->perh->RxFIFO[num].RXFDL >> 24) & 0xFF;
1058 _msg->data[4] = hperh->perh->RxFIFO[num].RXFDH & 0xFF;
1059 _msg->data[5] = (hperh->perh->RxFIFO[num].RXFDH >> 8) & 0xFF;
1060 _msg->data[6] = (hperh->perh->RxFIFO[num].RXFDH >> 16) & 0xFF;
1061 _msg->data[7] = (hperh->perh->RxFIFO[num].RXFDH >> 24) & 0xFF;
1062
1063 if (num == CAN_RX_FIFO0) {
1064 can_rx_fifo_release(hperh, CAN_RX_FIFO0);
1065 ald_can_interrupt_config(hperh, CAN_IT_FP0, DISABLE);
1066 CLEAR_BIT(hperh->state, CAN_STATE_RX0_MASK);
1067 }
1068 else {
1069 can_rx_fifo_release(hperh, CAN_RX_FIFO1);
1070 ald_can_interrupt_config(hperh, CAN_IT_FP1, DISABLE);
1071 CLEAR_BIT(hperh->state, CAN_STATE_RX1_MASK);
1072 }
1073
1074 if (hperh->state == CAN_STATE_READY) {
1075 ald_can_interrupt_config(hperh, CAN_IT_WARN, DISABLE);
1076 ald_can_interrupt_config(hperh, CAN_IT_PERR, DISABLE);
1077 ald_can_interrupt_config(hperh, CAN_IT_BOF, DISABLE);
1078 ald_can_interrupt_config(hperh, CAN_IT_PRERR, DISABLE);
1079 ald_can_interrupt_config(hperh, CAN_IT_ERR, DISABLE);
1080 }
1081
1082 if (hperh->rx_cplt_cbk)
1083 hperh->rx_cplt_cbk(hperh, num);
1084
1085 return OK;
1086 }
1091 #endif /* ALD_CAN */
1092
CAN_ERROR_UNK
Definition: ald_can.h:68
CAN_ERROR_BR
Definition: ald_can.h:65
can_rx_msg_t::ext
uint32_t ext
Definition: ald_can.h:281
IS_CAN_FILTER_MODE
#define IS_CAN_FILTER_MODE(x)
Definition: ald_can.h:338
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
CAN_FLAG_ERR
Definition: ald_can.h:190
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
can_tx_mailbox_t
can_tx_mailbox_t
CAN Transmit Constants.
Definition: ald_can.h:170
CAN_IT_FP1
Definition: ald_can.h:219
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
can_init_t::artx
type_func_t artx
Definition: ald_can.h:259
can_init_t::psc
uint32_t psc
Definition: ald_can.h:250
can_handle_s::rx1_msg
can_rx_msg_t * rx1_msg
Definition: ald_can.h:297
can_init_t::seg2
can_seg2_t seg2
Definition: ald_can.h:255
CAN_RX_MSG_PENDING
#define CAN_RX_MSG_PENDING(x, y)
Definition: ald_can.h:314
can_tx_msg_t::type
can_id_type_t type
Definition: ald_can.h:270
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
FALSE
Definition: type.h:54
IS_CAN_STDID
#define IS_CAN_STDID(x)
Definition: ald_can.h:349
ald_can_cancel_send
void ald_can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box)
Cancel transmission.
Definition: ald_can.c:746
BUSY
Definition: utils.h:57
ald_can_get_flag_status
flag_status_t ald_can_get_flag_status(can_handle_t *hperh, can_flag_t flag)
Get the status of CAN interrupt flag.
Definition: ald_can.c:822
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
CAN_FILTER_SCALE_16
Definition: ald_can.h:139
can_init_t::seg1
can_seg1_t seg1
Definition: ald_can.h:254
can_tx_msg_t::ext
uint32_t ext
Definition: ald_can.h:269
SET
Definition: type.h:39
can_rx_msg_t::fmi
uint32_t fmi
Definition: ald_can.h:286
CAN_TX_MAILBOX_NONE
Definition: ald_can.h:174
can_init_t::ttcm
type_func_t ttcm
Definition: ald_can.h:256
type_func_t
type_func_t
Definition: type.h:47
type_bool_t
type_bool_t
Definition: type.h:53
CAN_ERROR_BD
Definition: ald_can.h:66
DISABLE
Definition: type.h:48
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
can_filter_t::fifo
can_filter_fifo_t fifo
Definition: ald_can.h:239
CAN_ERROR_EWG
Definition: ald_can.h:59
can_error_t
can_error_t
CAN Error Code.
Definition: ald_can.h:57
can_filter_t::mask_id_high
uint32_t mask_id_high
Definition: ald_can.h:237
IS_CAN_BS2
#define IS_CAN_BS2(x)
Definition: ald_can.h:337
can_init_t::txmp
type_func_t txmp
Definition: ald_can.h:261
CAN_STATE_ERROR
Definition: ald_can.h:51
can_handle_s::lock
lock_state_t lock
Definition: ald_can.h:298
can_filter_t
CAN filter configuration structure definition.
Definition: ald_can.h:234
ald_can_init
ald_status_t ald_can_init(can_handle_t *hperh)
Initializes the CAN peripheral according to the specified parameters in the CAN_init_t.
Definition: ald_can.c:119
IS_CAN_FILTER_NUMBER
#define IS_CAN_FILTER_NUMBER(x)
Definition: ald_can.h:327
CAN_ERROR_NONE
Definition: ald_can.h:58
UNLOCK
Definition: type.h:59
can_filter_t::mode
can_filter_mode_t mode
Definition: ald_can.h:241
CAN_ERROR_ACK
Definition: ald_can.h:64
can_handle_s::init
can_init_t init
Definition: ald_can.h:295
CAN_ERROR_CRC
Definition: ald_can.h:67
can_init_t::mode
can_operate_mode_t mode
Definition: ald_can.h:251
can_handle_s::rx0_msg
can_rx_msg_t * rx0_msg
Definition: ald_can.h:296
RESET
Definition: type.h:38
can_init_t::awk
type_func_t awk
Definition: ald_can.h:258
IS_CAN_SJW
#define IS_CAN_SJW(x)
Definition: ald_can.h:332
CAN_IT_ERR
Definition: ald_can.h:226
can_init_t::abom
type_func_t abom
Definition: ald_can.h:257
can_init_t::sjw
can_sjw_t sjw
Definition: ald_can.h:252
TRUE
Definition: type.h:55
IS_CAN_CLEAR_FLAG
#define IS_CAN_CLEAR_FLAG(x)
Definition: ald_can.h:373
CAN_STATE_READY
Definition: ald_can.h:41
CAN_STATE_RX0_MASK
#define CAN_STATE_RX0_MASK
Definition: ald_can.h:399
can_init_t::rfom
type_func_t rfom
Definition: ald_can.h:260
ald_can_filter_config
ald_status_t ald_can_filter_config(can_handle_t *hperh, can_filter_t *config)
Configures the CAN reception filter according to the specified parameters in the can_filter_t.
Definition: ald_can.c:193
CAN_STATE_TIMEOUT
Definition: ald_can.h:50
ald_can_send_by_it
ald_status_t ald_can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg)
Send a CAN frame message using interrupt.
Definition: ald_can.c:347
CAN_TX_MAILBOX_2
Definition: ald_can.h:173
it_status_t
enum flag_status_t it_status_t
can_flag_t
can_flag_t
CAN Flags.
Definition: ald_can.h:188
can_filter_t::id_low
uint32_t id_low
Definition: ald_can.h:236
IS_CAN_EXTID
#define IS_CAN_EXTID(x)
Definition: ald_can.h:350
can_tx_msg_t
CAN Tx message structure definition.
Definition: ald_can.h:267
CAN_IT_WARN
Definition: ald_can.h:222
IS_CAN_RTR
#define IS_CAN_RTR(x)
Definition: ald_can.h:346
can_clear_flag
void can_clear_flag(can_handle_t *hperh, can_flag_t flag)
Clear the specified CAN pending flag.
Definition: ald_can.c:867
ald_can_get_tx_status
type_bool_t ald_can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box)
Check the transmission status of a CAN Frame.
Definition: ald_can.c:697
ald_can_recv_by_it
ald_status_t ald_can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg)
Receives a correct CAN frame using interrupt.
Definition: ald_can.c:466
can_rx_msg_t::std
uint32_t std
Definition: ald_can.h:280
CAN_ERROR_BOF
Definition: ald_can.h:61
ald_can_recv
ald_status_t ald_can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout)
Receives a correct CAN frame.
Definition: ald_can.c:411
CAN_FLAG_BOF
Definition: ald_can.h:208
can_it_t
can_it_t
CAN Interrupts.
Definition: ald_can.h:214
can_rx_msg_t
CAN Rx message structure definition.
Definition: ald_can.h:279
IS_CAN_FILTER_FIFO
#define IS_CAN_FILTER_FIFO(x)
Definition: ald_can.h:342
CAN_TX_MAILBOX_1
Definition: ald_can.h:172
CAN_STATE_BUSY_TX
Definition: ald_can.h:43
CAN_IT_TXM
Definition: ald_can.h:215
IS_CAN_PRESCALER
#define IS_CAN_PRESCALER(x)
Definition: ald_can.h:352
ald_can_get_state
can_state_t ald_can_get_state(can_handle_t *hperh)
return the CAN state
Definition: ald_can.c:917
can_tx_msg_t::std
uint32_t std
Definition: ald_can.h:268
can_handle_s::rx_cplt_cbk
void(* rx_cplt_cbk)(struct can_handle_s *arg, can_rx_fifo_t num)
Definition: ald_can.h:303
ald_can.h
Header file of CAN Module driver.
CAN_ERROR_EPV
Definition: ald_can.h:60
can_tx_msg_t::rtr
can_remote_req_t rtr
Definition: ald_can.h:271
can_state_t
can_state_t
ALD State structures definition.
Definition: ald_can.h:39
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
CAN_RX_FIFO1
Definition: ald_can.h:182
can_filter_t::mask_id_low
uint32_t mask_id_low
Definition: ald_can.h:238
can_rx_fifo_t
can_rx_fifo_t
CAN Receive fifo Number.
Definition: ald_can.h:180
IS_CAN_FILTER_SCALE
#define IS_CAN_FILTER_SCALE(x)
Definition: ald_can.h:340
ald_can_get_it_status
it_status_t ald_can_get_it_status(can_handle_t *hperh, can_it_t it)
Get the status of CAN interrupt source.
Definition: ald_can.c:802
IS_CAN_DATA_LEN
#define IS_CAN_DATA_LEN(x)
Definition: ald_can.h:351
IS_CAN_IT
#define IS_CAN_IT(x)
Definition: ald_can.h:383
CAN_STATE_RX1_MASK
#define CAN_STATE_RX1_MASK
Definition: ald_can.h:400
CAN_IT_PRERR
Definition: ald_can.h:225
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
can_handle_s::err
can_error_t err
Definition: ald_can.h:300
ald_can_get_error
can_error_t ald_can_get_error(can_handle_t *hperh)
Return the CAN error code.
Definition: ald_can.c:927
can_rx_msg_t::len
uint32_t len
Definition: ald_can.h:284
IS_CAN_GET_FLAG
#define IS_CAN_GET_FLAG(x)
Definition: ald_can.h:353
CAN_TIMEOUT_VALUE
#define CAN_TIMEOUT_VALUE
Definition: ald_can.h:397
can_filter_t::scale
can_filter_scale_t scale
Definition: ald_can.h:242
IS_CAN_FIFO
#define IS_CAN_FIFO(x)
Definition: ald_can.h:347
CAN_TX_MAILBOX_0
Definition: ald_can.h:171
CAN_IT_PERR
Definition: ald_can.h:223
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
can_handle_s::state
can_state_t state
Definition: ald_can.h:299
CAN_STATE_BUSY
Definition: ald_can.h:42
can_rx_fifo_release
static void can_rx_fifo_release(can_handle_t *hperh, can_rx_fifo_t num)
Release rx FIFO.
Definition: ald_can.c:950
__can_recv_by_it
static ald_status_t __can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num)
Receives a correct CAN frame using interrupt.
Definition: ald_can.c:1032
ald_can_send
ald_status_t ald_can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout)
Send a CAN frame message.
Definition: ald_can.c:280
can_rx_msg_t::data
uint8_t data[8]
Definition: ald_can.h:285
ald_can_irq_handler
void ald_can_irq_handler(can_handle_t *hperh)
Handles CAN interrupt request.
Definition: ald_can.c:596
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
CAN_FLAG_PERR
Definition: ald_can.h:207
can_tx_msg_t::len
uint32_t len
Definition: ald_can.h:272
flag_status_t
flag_status_t
Definition: type.h:37
CAN_ERROR_FOR
Definition: ald_can.h:63
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
can_handle_s::tx_cplt_cbk
void(* tx_cplt_cbk)(struct can_handle_s *arg)
Definition: ald_can.h:302
ald_can_wake_up
ald_status_t ald_can_wake_up(can_handle_t *hperh)
Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral is in the normal mode...
Definition: ald_can.c:565
can_filter_t::active
type_func_t active
Definition: ald_can.h:243
can_tx_msg_t::data
uint8_t data[8]
Definition: ald_can.h:273
CAN_FILTER_SCALE_32
Definition: ald_can.h:140
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
can_remote_req_t
can_remote_req_t
CAN Remote Transmission Request.
Definition: ald_can.h:162
IS_CAN_BS1
#define IS_CAN_BS1(x)
Definition: ald_can.h:336
can_rx_msg_t::rtr
can_remote_req_t rtr
Definition: ald_can.h:283
CAN_FLAG_WARN
Definition: ald_can.h:206
IS_CAN_ALL
#define IS_CAN_ALL(x)
Definition: ald_can.h:326
ald_can_interrupt_config
void ald_can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state)
Enable/disable the specified CAN interrupts.
Definition: ald_can.c:779
CAN_ID_STD
Definition: ald_can.h:155
__can_send_by_it
static ald_status_t __can_send_by_it(can_handle_t *hperh, uint8_t err)
transmits a CAN frame message using interrupt.
Definition: ald_can.c:965
can_filter_t::id_high
uint32_t id_high
Definition: ald_can.h:235
can_handle_s::error_cbk
void(* error_cbk)(struct can_handle_s *arg)
Definition: ald_can.h:304
ald_can_reset
void ald_can_reset(can_handle_t *hperh)
Reset the CAN peripheral.
Definition: ald_can.c:242
CAN_STATE_RESET
Definition: ald_can.h:40
__LOCK
#define __LOCK(x)
Definition: utils.h:92
CAN_RX_FIFO0
Definition: ald_can.h:181
IS_CAN_TX_MAILBOX
#define IS_CAN_TX_MAILBOX(x)
Definition: ald_can.h:348
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
ERROR
Definition: utils.h:56
CAN_ERROR_STF
Definition: ald_can.h:62
CAN_IT_BOF
Definition: ald_can.h:224
ald_can_sleep
ald_status_t ald_can_sleep(can_handle_t *hperh)
Enters the Sleep(low power) mode.
Definition: ald_can.c:532
IS_CAN_IDTYPE
#define IS_CAN_IDTYPE(x)
Definition: ald_can.h:344
can_filter_t::number
uint32_t number
Definition: ald_can.h:240
CAN_STATE_TX_MASK
#define CAN_STATE_TX_MASK
Definition: ald_can.h:398
CAN_IT_FP0
Definition: ald_can.h:216
IS_CAN_MODE
#define IS_CAN_MODE(x)
Definition: ald_can.h:328
can_handle_s
CAN handle Structure definition.
Definition: ald_can.h:293
__can_rx_check
static int __can_rx_check(can_handle_t *hperh, can_rx_fifo_t num)
Check whether the data in the mailbox is contaminated.
Definition: ald_can.c:998
can_rx_msg_t::type
can_id_type_t type
Definition: ald_can.h:282
can_id_type_t
can_id_type_t
CAN Identifier Type.
Definition: ald_can.h:154


ALD User Manual: D:/svn/src/ald_can.h Source File

  • D:
  • svn
  • src
ald_can.h
Go to the documentation of this file.
1
16 #ifndef __ALD_CAN_H
17 #define __ALD_CAN_H
18
19 #ifdef __cplusplus
20 extern "C" {
21 #endif
22
23 #include "utils.h"
24
39 typedef enum {
40 CAN_STATE_RESET = 0x00U,
41 CAN_STATE_READY = 0x01U,
42 CAN_STATE_BUSY = 0x02U,
43 CAN_STATE_BUSY_TX = 0x11U,
44 CAN_STATE_BUSY_RX0 = 0x21U,
45 CAN_STATE_BUSY_RX1 = 0x41U,
46 CAN_STATE_BUSY_TX_RX0 = 0x31U,
47 CAN_STATE_BUSY_TX_RX1 = 0x51U,
48 CAN_STATE_BUSY_RX0_RX1 = 0x61U,
49 CAN_STATE_BUSY_TX_RX0_RX1 = 0x71U,
50 CAN_STATE_TIMEOUT = 0x04U,
51 CAN_STATE_ERROR = 0x08U,
52 } can_state_t;
53
57 typedef enum {
58 CAN_ERROR_NONE = 0x00U,
59 CAN_ERROR_EWG = 0x01U,
60 CAN_ERROR_EPV = 0x02U,
61 CAN_ERROR_BOF = 0x04U,
62 CAN_ERROR_STF = 0x08U,
63 CAN_ERROR_FOR = 0x10U,
64 CAN_ERROR_ACK = 0x20U,
65 CAN_ERROR_BR = 0x40U,
66 CAN_ERROR_BD = 0x80U,
67 CAN_ERROR_CRC = 0x100U,
68 CAN_ERROR_UNK = 0x200U,
69 } can_error_t;
70
74 typedef enum {
75 CAN_MODE_NORMAL = 0x00U,
76 CAN_MODE_LOOPBACK = 0x01U,
77 CAN_MODE_SILENT = 0x02U,
78 CAN_MODE_SILENT_LOOPBACK = 0x03U,
79 } can_operate_mode_t;
80
84 typedef enum {
85 CAN_SJW_1 = 0x0U,
86 CAN_SJW_2 = 0x1U,
87 CAN_SJW_3 = 0x2U,
88 CAN_SJW_4 = 0x3U,
89 } can_sjw_t;
90
94 typedef enum {
95 CAN_SEG1_1 = 0x0U,
96 CAN_SEG1_2 = 0x1U,
97 CAN_SEG1_3 = 0x2U,
98 CAN_SEG1_4 = 0x3U,
99 CAN_SEG1_5 = 0x4U,
100 CAN_SEG1_6 = 0x5U,
101 CAN_SEG1_7 = 0x6U,
102 CAN_SEG1_8 = 0x7U,
103 CAN_SEG1_9 = 0x8U,
104 CAN_SEG1_10 = 0x9U,
105 CAN_SEG1_11 = 0xAU,
106 CAN_SEG1_12 = 0xBU,
107 CAN_SEG1_13 = 0xCU,
108 CAN_SEG1_14 = 0xDU,
109 CAN_SEG1_15 = 0xEU,
110 CAN_SEG1_16 = 0xFU,
111 } can_seg1_t;
112
116 typedef enum {
117 CAN_SEG2_1 = 0x0U,
118 CAN_SEG2_2 = 0x1U,
119 CAN_SEG2_3 = 0x2U,
120 CAN_SEG2_4 = 0x3U,
121 CAN_SEG2_5 = 0x4U,
122 CAN_SEG2_6 = 0x5U,
123 CAN_SEG2_7 = 0x6U,
124 CAN_SEG2_8 = 0x7U,
125 } can_seg2_t;
126
130 typedef enum {
131 CAN_FILTER_MODE_MASK = 0x0U,
132 CAN_FILTER_MODE_LIST = 0x1U,
133 } can_filter_mode_t;
134
138 typedef enum {
139 CAN_FILTER_SCALE_16 = 0x0U,
140 CAN_FILTER_SCALE_32 = 0x1U,
141 } can_filter_scale_t;
142
146 typedef enum {
147 CAN_FILTER_FIFO0 = 0x0U,
148 CAN_FILTER_FIFO1 = 0x1U,
149 } can_filter_fifo_t;
150
154 typedef enum {
155 CAN_ID_STD = 0x0U,
156 CAN_ID_EXT = 0x1U,
157 } can_id_type_t;
158
162 typedef enum {
163 CAN_RTR_DATA = 0x0U,
164 CAN_RTR_REMOTE = 0x1U,
165 } can_remote_req_t;
166
170 typedef enum {
171 CAN_TX_MAILBOX_0 = 0x0U,
172 CAN_TX_MAILBOX_1 = 0x1U,
173 CAN_TX_MAILBOX_2 = 0x2U,
174 CAN_TX_MAILBOX_NONE = 0x3U,
175 } can_tx_mailbox_t;
176
180 typedef enum {
181 CAN_RX_FIFO0 = 0x0U,
182 CAN_RX_FIFO1 = 0x1U,
183 } can_rx_fifo_t;
184
188 typedef enum {
189 CAN_FLAG_SLPS = (1U << 1),
190 CAN_FLAG_ERR = (1U << 2),
191 CAN_FLAG_WK = (1U << 3),
192 CAN_FLAG_SLP = (1U << 4),
193 CAN_FLAG_M0REQC = (1U << 20) | (1U << 0),
194 CAN_FLAG_M0TXC = (1U << 20) | (1U << 1),
195 CAN_FLAG_M1REQC = (1U << 20) | (1U << 8),
196 CAN_FLAG_M1TXC = (1U << 20) | (1U << 9),
197 CAN_FLAG_M2REQC = (1U << 20) | (1U << 16),
198 CAN_FLAG_M2TXC = (1U << 20) | (1U << 17),
199 CAN_FLAG_TXM0 = (1U << 20) | (1U << 26),
200 CAN_FLAG_TXM1 = (1U << 20) | (1U << 27),
201 CAN_FLAG_TXM2 = (1U << 20) | (1U << 28),
202 CAN_FLAG_FF0 = (2U << 20) | (1U << 3),
203 CAN_FLAG_FOV0 = (2U << 20) | (1U << 4),
204 CAN_FLAG_FF1 = (3U << 20) | (1U << 3),
205 CAN_FLAG_FOV1 = (3U << 20) | (1U << 4),
206 CAN_FLAG_WARN = (4U << 20) | (1U << 0),
207 CAN_FLAG_PERR = (4U << 20) | (1U << 1),
208 CAN_FLAG_BOF = (4U << 20) | (1U << 2),
209 } can_flag_t;
210
214 typedef enum {
215 CAN_IT_TXM = (1U << 0),
216 CAN_IT_FP0 = (1U << 1),
217 CAN_IT_FF0 = (1U << 2),
218 CAN_IT_FOV0 = (1U << 3),
219 CAN_IT_FP1 = (1U << 4),
220 CAN_IT_FF1 = (1U << 5),
221 CAN_IT_FOV1 = (1U << 6),
222 CAN_IT_WARN = (1U << 8),
223 CAN_IT_PERR = (1U << 9),
224 CAN_IT_BOF = (1U << 10),
225 CAN_IT_PRERR = (1U << 11),
226 CAN_IT_ERR = (1U << 15),
227 CAN_IT_WK = (1U << 16),
228 CAN_IT_SLP = (1U << 17),
229 } can_it_t;
230
234 typedef struct {
235 uint32_t id_high;
236 uint32_t id_low;
237 uint32_t mask_id_high;
238 uint32_t mask_id_low;
239 can_filter_fifo_t fifo;
240 uint32_t number;
241 can_filter_mode_t mode;
242 can_filter_scale_t scale;
243 type_func_t active;
244 } can_filter_t;
245
249 typedef struct {
250 uint32_t psc;
251 can_operate_mode_t mode;
252 can_sjw_t sjw;
254 can_seg1_t seg1;
255 can_seg2_t seg2;
256 type_func_t ttcm;
257 type_func_t abom;
258 type_func_t awk;
259 type_func_t artx;
260 type_func_t rfom;
261 type_func_t txmp;
262 } can_init_t;
263
267 typedef struct {
268 uint32_t std;
269 uint32_t ext;
270 can_id_type_t type;
271 can_remote_req_t rtr;
272 uint32_t len;
273 uint8_t data[8];
274 } can_tx_msg_t;
275
279 typedef struct {
280 uint32_t std;
281 uint32_t ext;
282 can_id_type_t type;
283 can_remote_req_t rtr;
284 uint32_t len;
285 uint8_t data[8];
286 uint32_t fmi;
287 can_rx_fifo_t num;
288 } can_rx_msg_t;
289
293 typedef struct can_handle_s {
294 CAN_TypeDef *perh;
295 can_init_t init;
296 can_rx_msg_t *rx0_msg;
297 can_rx_msg_t *rx1_msg;
298 lock_state_t lock;
299 can_state_t state;
300 can_error_t err;
302 void (*tx_cplt_cbk)(struct can_handle_s *arg);
303 void (*rx_cplt_cbk)(struct can_handle_s *arg, can_rx_fifo_t num);
304 void (*error_cbk)(struct can_handle_s *arg);
305 } can_handle_t;
313 #define CAN_RESET_HANDLE_STATE(x) ((x)->state = CAN_STATE_RESET)
314 #define CAN_RX_MSG_PENDING(x, y) (((y) == CAN_RX_FIFO0) ? \
315 (READ_BIT((x)->perh->RXF0, CAN_RXF0_PEND_MSK)) : (READ_BIT((x)->perh->RXF1, CAN_RXF1_PEND_MSK)))
316 #define CAN_DBG_FREEZE(x, y) (MODIFY_REG((x)->perh->CON, CAN_CON_DBGSTP_MSK, (y) << CAN_CON_DBGSTP_POS))
317 #define CAN_TX_STAMP_ENABLE(x, y) (SET_BIT((x)->perh->TxMailBox[(y)].TXFCON, CAN_TXFCON0_TXGT_MSK))
318 #define CAN_TX_STAMP_DISABLE(x, y) (CLEAR_BIT((x)->perh->TxMailBox[(y)].TXFCON, CAN_TXFCON0_TXGT_MSK))
319
326 #define IS_CAN_ALL(x) ((x) == CAN0)
327 #define IS_CAN_FILTER_NUMBER(x) ((x) <= 13)
328 #define IS_CAN_MODE(x) (((x) == CAN_MODE_NORMAL) || \
329 ((x) == CAN_MODE_LOOPBACK) || \
330 ((x) == CAN_MODE_SILENT) || \
331 ((x) == CAN_MODE_SILENT_LOOPBACK))
332 #define IS_CAN_SJW(x) (((x) == CAN_SJW_1) || \
333 ((x) == CAN_SJW_2) || \
334 ((x) == CAN_SJW_3) || \
335 ((x) == CAN_SJW_4))
336 #define IS_CAN_BS1(x) ((x) <= CAN_SEG1_16)
337 #define IS_CAN_BS2(x) ((x) <= CAN_SEG2_8)
338 #define IS_CAN_FILTER_MODE(x) (((x) == CAN_FILTER_MODE_MASK) || \
339 ((x) == CAN_FILTER_MODE_LIST))
340 #define IS_CAN_FILTER_SCALE(x) (((x) == CAN_FILTER_SCALE_16) || \
341 ((x) == CAN_FILTER_SCALE_32))
342 #define IS_CAN_FILTER_FIFO(x) (((x) == CAN_FILTER_FIFO0) || \
343 ((x) == CAN_FILTER_FIFO1))
344 #define IS_CAN_IDTYPE(x) (((x) == CAN_ID_STD) || \
345 ((x) == CAN_ID_EXT))
346 #define IS_CAN_RTR(x) (((x) == CAN_RTR_DATA) || ((x) == CAN_RTR_REMOTE))
347 #define IS_CAN_FIFO(x) (((x) == CAN_RX_FIFO0) || ((x) == CAN_RX_FIFO1))
348 #define IS_CAN_TX_MAILBOX(x) ((x) <= CAN_TX_MAILBOX_NONE)
349 #define IS_CAN_STDID(x) ((x) <= ((uint32_t)0x7FF))
350 #define IS_CAN_EXTID(x) ((x) <= ((uint32_t)0x1FFFFFFF))
351 #define IS_CAN_DATA_LEN(x) ((x) <= ((uint8_t)0x08))
352 #define IS_CAN_PRESCALER(x) (((x) >= 1) && ((x) <= 1024))
353 #define IS_CAN_GET_FLAG(x) (((x) == CAN_FLAG_SLPS) || \
354 ((x) == CAN_FLAG_ERR) || \
355 ((x) == CAN_FLAG_WK) || \
356 ((x) == CAN_FLAG_SLP) || \
357 ((x) == CAN_FLAG_M0REQC) || \
358 ((x) == CAN_FLAG_M0TXC) || \
359 ((x) == CAN_FLAG_M1REQC) || \
360 ((x) == CAN_FLAG_M1TXC) || \
361 ((x) == CAN_FLAG_M2REQC) || \
362 ((x) == CAN_FLAG_M2TXC) || \
363 ((x) == CAN_FLAG_TXM0) || \
364 ((x) == CAN_FLAG_TXM1) || \
365 ((x) == CAN_FLAG_TXM2) || \
366 ((x) == CAN_FLAG_FF0) || \
367 ((x) == CAN_FLAG_FOV0) || \
368 ((x) == CAN_FLAG_FF1) || \
369 ((x) == CAN_FLAG_FOV1) || \
370 ((x) == CAN_FLAG_WARN) || \
371 ((x) == CAN_FLAG_PERR) || \
372 ((x) == CAN_FLAG_BOF))
373 #define IS_CAN_CLEAR_FLAG(x) (((x) == CAN_FLAG_ERR) || \
374 ((x) == CAN_FLAG_WK) || \
375 ((x) == CAN_FLAG_SLP) || \
376 ((x) == CAN_FLAG_M0REQC) || \
377 ((x) == CAN_FLAG_M1REQC) || \
378 ((x) == CAN_FLAG_M2REQC) || \
379 ((x) == CAN_FLAG_FF0) || \
380 ((x) == CAN_FLAG_FOV0) || \
381 ((x) == CAN_FLAG_FF1) || \
382 ((x) == CAN_FLAG_FOV1))
383 #define IS_CAN_IT(x) (((x) == CAN_IT_TXM) || \
384 ((x) == CAN_IT_FP0) || \
385 ((x) == CAN_IT_FF0) || \
386 ((x) == CAN_IT_FOV0) || \
387 ((x) == CAN_IT_FP1) || \
388 ((x) == CAN_IT_FF1) || \
389 ((x) == CAN_IT_FOV1) || \
390 ((x) == CAN_IT_WARN) || \
391 ((x) == CAN_IT_PERR) || \
392 ((x) == CAN_IT_BOF) || \
393 ((x) == CAN_IT_PRERR) || \
394 ((x) == CAN_IT_ERR) || \
395 ((x) == CAN_IT_WK) || \
396 ((x) == CAN_IT_SLP))
397 #define CAN_TIMEOUT_VALUE 100
398 #define CAN_STATE_TX_MASK (1U << 4)
399 #define CAN_STATE_RX0_MASK (1U << 5)
400 #define CAN_STATE_RX1_MASK (1U << 6)
401
413 /* Initialization functions */
414 void ald_can_reset(can_handle_t *hperh);
415 ald_status_t ald_can_init(can_handle_t *hperh);
416 ald_status_t ald_can_filter_config(can_handle_t *hperh, can_filter_t *config);
424 /* IO operation functions */
425 ald_status_t ald_can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout);
426 ald_status_t ald_can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg);
427 ald_status_t ald_can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout);
428 ald_status_t ald_can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg);
436 /* Control function */
437 ald_status_t ald_can_sleep(can_handle_t *hperh);
438 ald_status_t ald_can_wake_up(can_handle_t *hperh);
439 void ald_can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box);
440 void ald_can_irq_handler(can_handle_t *hperh);
441 type_bool_t ald_can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box);
442 void ald_can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state);
443 it_status_t ald_can_get_it_status(can_handle_t *hperh, can_it_t it);
444 flag_status_t ald_can_get_flag_status(can_handle_t *hperh, can_flag_t flag);
445 void ald_can_clear_flag_status(can_handle_t *hperh, can_flag_t flag);
453 /* State and Error functions */
454 can_state_t ald_can_get_state(can_handle_t *hperh);
455 can_error_t ald_can_get_error(can_handle_t *hperh);
472 #ifdef __cplusplus
473 }
474 #endif
475
476 #endif /* __ALD_CAN_H */
CAN_SEG2_3
Definition: ald_can.h:119
CAN_STATE_BUSY_RX1
Definition: ald_can.h:45
CAN_ERROR_UNK
Definition: ald_can.h:68
CAN_ERROR_BR
Definition: ald_can.h:65
CAN_SEG1_16
Definition: ald_can.h:110
CAN_FILTER_MODE_MASK
Definition: ald_can.h:131
can_rx_msg_t::ext
uint32_t ext
Definition: ald_can.h:281
CAN_FLAG_SLPS
Definition: ald_can.h:189
CAN_FLAG_ERR
Definition: ald_can.h:190
CAN_SEG2_5
Definition: ald_can.h:121
CAN_FLAG_M2REQC
Definition: ald_can.h:197
CAN_FILTER_FIFO0
Definition: ald_can.h:147
can_filter_scale_t
can_filter_scale_t
CAN Filter Scale.
Definition: ald_can.h:138
can_tx_mailbox_t
can_tx_mailbox_t
CAN Transmit Constants.
Definition: ald_can.h:170
CAN_IT_FP1
Definition: ald_can.h:219
adc_handle_s::state
adc_state_t state
Definition: ald_adc.h:361
can_init_t::artx
type_func_t artx
Definition: ald_can.h:259
can_init_t::psc
uint32_t psc
Definition: ald_can.h:250
can_handle_s::rx1_msg
can_rx_msg_t * rx1_msg
Definition: ald_can.h:297
CAN_MODE_SILENT_LOOPBACK
Definition: ald_can.h:78
can_init_t::seg2
can_seg2_t seg2
Definition: ald_can.h:255
can_tx_msg_t::type
can_id_type_t type
Definition: ald_can.h:270
CAN_SEG1_8
Definition: ald_can.h:102
can_filter_fifo_t
can_filter_fifo_t
CAN Filter fifo.
Definition: ald_can.h:146
ald_can_cancel_send
void ald_can_cancel_send(can_handle_t *hperh, can_tx_mailbox_t box)
Cancel transmission.
Definition: ald_can.c:746
ald_can_get_flag_status
flag_status_t ald_can_get_flag_status(can_handle_t *hperh, can_flag_t flag)
Get the status of CAN interrupt flag.
Definition: ald_can.c:822
CAN_FILTER_SCALE_16
Definition: ald_can.h:139
CAN_FLAG_M2TXC
Definition: ald_can.h:198
can_init_t::seg1
can_seg1_t seg1
Definition: ald_can.h:254
CAN_STATE_BUSY_TX_RX0
Definition: ald_can.h:46
can_tx_msg_t::ext
uint32_t ext
Definition: ald_can.h:269
can_rx_msg_t::fmi
uint32_t fmi
Definition: ald_can.h:286
CAN_TX_MAILBOX_NONE
Definition: ald_can.h:174
CAN_SEG1_11
Definition: ald_can.h:105
CAN_SEG1_13
Definition: ald_can.h:107
can_init_t::ttcm
type_func_t ttcm
Definition: ald_can.h:256
type_func_t
type_func_t
Definition: type.h:47
type_bool_t
type_bool_t
Definition: type.h:53
CAN_IT_FF0
Definition: ald_can.h:217
CAN_ERROR_BD
Definition: ald_can.h:66
can_seg1_t
can_seg1_t
CAN Time Quantum in Bit Segment 1.
Definition: ald_can.h:94
CAN_SEG1_14
Definition: ald_can.h:108
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
CAN_FLAG_SLP
Definition: ald_can.h:192
CAN_SEG1_3
Definition: ald_can.h:97
can_filter_t::fifo
can_filter_fifo_t fifo
Definition: ald_can.h:239
CAN_MODE_SILENT
Definition: ald_can.h:77
CAN_ERROR_EWG
Definition: ald_can.h:59
CAN_SEG2_2
Definition: ald_can.h:118
can_error_t
can_error_t
CAN Error Code.
Definition: ald_can.h:57
can_filter_t::mask_id_high
uint32_t mask_id_high
Definition: ald_can.h:237
CAN_FLAG_FF0
Definition: ald_can.h:202
CAN_SEG1_7
Definition: ald_can.h:101
can_init_t::txmp
type_func_t txmp
Definition: ald_can.h:261
CAN_FLAG_TXM0
Definition: ald_can.h:199
CAN_STATE_ERROR
Definition: ald_can.h:51
can_handle_s::lock
lock_state_t lock
Definition: ald_can.h:298
can_handle_t
struct can_handle_s can_handle_t
CAN handle Structure definition.
ald_can_init
ald_status_t ald_can_init(can_handle_t *hperh)
Initializes the CAN peripheral according to the specified parameters in the CAN_init_t.
Definition: ald_can.c:119
can_filter_t
CAN filter configuration structure definition.
Definition: ald_can.h:234
CAN_SJW_3
Definition: ald_can.h:87
CAN_ERROR_NONE
Definition: ald_can.h:58
CAN_IT_SLP
Definition: ald_can.h:228
can_filter_t::mode
can_filter_mode_t mode
Definition: ald_can.h:241
CAN_ERROR_ACK
Definition: ald_can.h:64
can_handle_s::init
can_init_t init
Definition: ald_can.h:295
CAN_FLAG_M0TXC
Definition: ald_can.h:194
CAN_ERROR_CRC
Definition: ald_can.h:67
CAN_FLAG_WK
Definition: ald_can.h:191
can_init_t::mode
can_operate_mode_t mode
Definition: ald_can.h:251
can_handle_s::rx0_msg
can_rx_msg_t * rx0_msg
Definition: ald_can.h:296
can_init_t::awk
type_func_t awk
Definition: ald_can.h:258
CAN_IT_ERR
Definition: ald_can.h:226
can_init_t::abom
type_func_t abom
Definition: ald_can.h:257
CAN_RTR_DATA
Definition: ald_can.h:163
can_init_t::sjw
can_sjw_t sjw
Definition: ald_can.h:252
utils.h
This file contains the Utilities functions/types for the driver.
CAN_SEG2_1
Definition: ald_can.h:117
CAN_STATE_READY
Definition: ald_can.h:41
can_init_t::rfom
type_func_t rfom
Definition: ald_can.h:260
ald_can_filter_config
ald_status_t ald_can_filter_config(can_handle_t *hperh, can_filter_t *config)
Configures the CAN reception filter according to the specified parameters in the can_filter_t.
Definition: ald_can.c:193
ald_can_clear_flag_status
void ald_can_clear_flag_status(can_handle_t *hperh, can_flag_t flag)
CAN_STATE_TIMEOUT
Definition: ald_can.h:50
ald_can_send_by_it
ald_status_t ald_can_send_by_it(can_handle_t *hperh, can_tx_msg_t *msg)
Send a CAN frame message using interrupt.
Definition: ald_can.c:347
CAN_TX_MAILBOX_2
Definition: ald_can.h:173
can_seg2_t
can_seg2_t
CAN Time Quantum in Bit Segment 2.
Definition: ald_can.h:116
it_status_t
enum flag_status_t it_status_t
CAN_SJW_1
Definition: ald_can.h:85
can_flag_t
can_flag_t
CAN Flags.
Definition: ald_can.h:188
can_filter_t::id_low
uint32_t id_low
Definition: ald_can.h:236
CAN_IT_WK
Definition: ald_can.h:227
CAN_IT_FF1
Definition: ald_can.h:220
can_tx_msg_t
CAN Tx message structure definition.
Definition: ald_can.h:267
CAN_IT_WARN
Definition: ald_can.h:222
ald_can_get_tx_status
type_bool_t ald_can_get_tx_status(can_handle_t *hperh, can_tx_mailbox_t box)
Check the transmission status of a CAN Frame.
Definition: ald_can.c:697
CAN_SEG1_4
Definition: ald_can.h:98
ald_can_recv_by_it
ald_status_t ald_can_recv_by_it(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg)
Receives a correct CAN frame using interrupt.
Definition: ald_can.c:466
can_rx_msg_t::std
uint32_t std
Definition: ald_can.h:280
CAN_SEG1_2
Definition: ald_can.h:96
CAN_ERROR_BOF
Definition: ald_can.h:61
ald_can_recv
ald_status_t ald_can_recv(can_handle_t *hperh, can_rx_fifo_t num, can_rx_msg_t *msg, uint32_t timeout)
Receives a correct CAN frame.
Definition: ald_can.c:411
CAN_FLAG_BOF
Definition: ald_can.h:208
can_it_t
can_it_t
CAN Interrupts.
Definition: ald_can.h:214
CAN_FLAG_M1TXC
Definition: ald_can.h:196
can_rx_msg_t
CAN Rx message structure definition.
Definition: ald_can.h:279
CAN_FLAG_M1REQC
Definition: ald_can.h:195
CAN_TX_MAILBOX_1
Definition: ald_can.h:172
CAN_FLAG_M0REQC
Definition: ald_can.h:193
CAN_STATE_BUSY_TX
Definition: ald_can.h:43
CAN_RTR_REMOTE
Definition: ald_can.h:164
CAN_IT_TXM
Definition: ald_can.h:215
CAN_SJW_4
Definition: ald_can.h:88
CAN_STATE_BUSY_RX0_RX1
Definition: ald_can.h:48
lock_state_t
lock_state_t
Definition: type.h:58
ald_can_get_state
can_state_t ald_can_get_state(can_handle_t *hperh)
return the CAN state
Definition: ald_can.c:917
CAN_SJW_2
Definition: ald_can.h:86
can_tx_msg_t::std
uint32_t std
Definition: ald_can.h:268
CAN_SEG1_12
Definition: ald_can.h:106
can_handle_s::rx_cplt_cbk
void(* rx_cplt_cbk)(struct can_handle_s *arg, can_rx_fifo_t num)
Definition: ald_can.h:303
CAN_SEG2_4
Definition: ald_can.h:120
CAN_ERROR_EPV
Definition: ald_can.h:60
can_sjw_t
can_sjw_t
CAN Synchronization Jump Width.
Definition: ald_can.h:84
can_tx_msg_t::rtr
can_remote_req_t rtr
Definition: ald_can.h:271
can_state_t
can_state_t
ALD State structures definition.
Definition: ald_can.h:39
CAN_RX_FIFO1
Definition: ald_can.h:182
can_filter_t::mask_id_low
uint32_t mask_id_low
Definition: ald_can.h:238
can_rx_fifo_t
can_rx_fifo_t
CAN Receive fifo Number.
Definition: ald_can.h:180
CAN_FILTER_FIFO1
Definition: ald_can.h:148
CAN_SEG1_6
Definition: ald_can.h:100
ald_can_get_it_status
it_status_t ald_can_get_it_status(can_handle_t *hperh, can_it_t it)
Get the status of CAN interrupt source.
Definition: ald_can.c:802
CAN_FLAG_TXM1
Definition: ald_can.h:200
CAN_SEG2_6
Definition: ald_can.h:122
CAN_IT_PRERR
Definition: ald_can.h:225
CAN_MODE_LOOPBACK
Definition: ald_can.h:76
can_handle_s::err
can_error_t err
Definition: ald_can.h:300
CAN_FLAG_FOV0
Definition: ald_can.h:203
ald_can_get_error
can_error_t ald_can_get_error(can_handle_t *hperh)
Return the CAN error code.
Definition: ald_can.c:927
can_rx_msg_t::len
uint32_t len
Definition: ald_can.h:284
CAN_SEG1_15
Definition: ald_can.h:109
can_filter_t::scale
can_filter_scale_t scale
Definition: ald_can.h:242
CAN_TX_MAILBOX_0
Definition: ald_can.h:171
CAN_IT_PERR
Definition: ald_can.h:223
CAN_FLAG_FF1
Definition: ald_can.h:204
can_handle_s::state
can_state_t state
Definition: ald_can.h:299
CAN_STATE_BUSY
Definition: ald_can.h:42
CAN_SEG1_5
Definition: ald_can.h:99
ald_can_send
ald_status_t ald_can_send(can_handle_t *hperh, can_tx_msg_t *msg, uint32_t timeout)
Send a CAN frame message.
Definition: ald_can.c:280
CAN_MODE_NORMAL
Definition: ald_can.h:75
ald_can_irq_handler
void ald_can_irq_handler(can_handle_t *hperh)
Handles CAN interrupt request.
Definition: ald_can.c:596
CAN_FLAG_PERR
Definition: ald_can.h:207
can_tx_msg_t::len
uint32_t len
Definition: ald_can.h:272
CAN_STATE_BUSY_RX0
Definition: ald_can.h:44
can_filter_mode_t
can_filter_mode_t
CAN Filter Mode.
Definition: ald_can.h:130
CAN_FLAG_TXM2
Definition: ald_can.h:201
flag_status_t
flag_status_t
Definition: type.h:37
CAN_ERROR_FOR
Definition: ald_can.h:63
can_operate_mode_t
can_operate_mode_t
CAN Operating Mode.
Definition: ald_can.h:74
CAN_SEG1_1
Definition: ald_can.h:95
CAN_SEG1_10
Definition: ald_can.h:104
CAN_SEG2_7
Definition: ald_can.h:123
CAN_IT_FOV1
Definition: ald_can.h:221
ald_can_wake_up
ald_status_t ald_can_wake_up(can_handle_t *hperh)
Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral is in the normal mode...
Definition: ald_can.c:565
can_filter_t::active
type_func_t active
Definition: ald_can.h:243
CAN_FILTER_SCALE_32
Definition: ald_can.h:140
can_init_t
CAN init structure definition.
Definition: ald_can.h:249
CAN_IT_FOV0
Definition: ald_can.h:218
CAN_STATE_BUSY_TX_RX0_RX1
Definition: ald_can.h:49
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
can_remote_req_t
can_remote_req_t
CAN Remote Transmission Request.
Definition: ald_can.h:162
can_rx_msg_t::rtr
can_remote_req_t rtr
Definition: ald_can.h:283
CAN_FLAG_WARN
Definition: ald_can.h:206
can_rx_msg_t::num
can_rx_fifo_t num
Definition: ald_can.h:287
ald_can_interrupt_config
void ald_can_interrupt_config(can_handle_t *hperh, can_it_t it, type_func_t state)
Enable/disable the specified CAN interrupts.
Definition: ald_can.c:779
CAN_ID_STD
Definition: ald_can.h:155
CAN_SEG1_9
Definition: ald_can.h:103
CAN_STATE_BUSY_TX_RX1
Definition: ald_can.h:47
can_filter_t::id_high
uint32_t id_high
Definition: ald_can.h:235
CAN_FILTER_MODE_LIST
Definition: ald_can.h:132
adc_handle_s::error_cbk
void(* error_cbk)(struct adc_handle_s *arg)
Definition: ald_adc.h:367
ald_can_reset
void ald_can_reset(can_handle_t *hperh)
Reset the CAN peripheral.
Definition: ald_can.c:242
CAN_STATE_RESET
Definition: ald_can.h:40
CAN_RX_FIFO0
Definition: ald_can.h:181
CAN_ID_EXT
Definition: ald_can.h:156
CAN_ERROR_STF
Definition: ald_can.h:62
CAN_IT_BOF
Definition: ald_can.h:224
ald_can_sleep
ald_status_t ald_can_sleep(can_handle_t *hperh)
Enters the Sleep(low power) mode.
Definition: ald_can.c:532
CAN_FLAG_FOV1
Definition: ald_can.h:205
can_filter_t::number
uint32_t number
Definition: ald_can.h:240
CAN_SEG2_8
Definition: ald_can.h:124
CAN_IT_FP0
Definition: ald_can.h:216
can_handle_s
CAN handle Structure definition.
Definition: ald_can.h:293
can_rx_msg_t::type
can_id_type_t type
Definition: ald_can.h:282
can_id_type_t
can_id_type_t
CAN Identifier Type.
Definition: ald_can.h:154


ALD User Manual: D:/svn/src/ald_cmu.c Source File

  • D:
  • svn
  • src
ald_cmu.c
Go to the documentation of this file.
1
127 #include "ald_cmu.h"
128 #include "ald_flash.h"
129
130
144 uint32_t __system_clock = 24000000U;
160 static void cmu_clock_update(uint32_t clock)
161 {
162 __system_clock = clock;
163
164 if (clock > 1000000)
165 ald_tick_init(TICK_INT_PRIORITY);
166
167 return;
168 }
169
174 void ald_cmu_irq_handler(void)
175 {
176 /* HOSC stop */
177 if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK)) {
178 SYSCFG_UNLOCK();
179 SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK);
180 SYSCFG_LOCK();
181
182 if ((READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK))
183 && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1)
184 || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))))
185 cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000);
186 ald_cmu_irq_cbk(CMU_HOSC_STOP);
187 }
188
189 /* HOSC start */
190 if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK) && READ_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIE_MSK)) {
191 SYSCFG_UNLOCK();
192 SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STRIF_MSK);
193 SYSCFG_LOCK();
194
195 if (!(READ_BIT(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK))
196 && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5)))
197 cmu_clock_update((READ_BITS(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, CMU_HOSCCFG_FREQ_POSS) + 1) * 1000000);
198 ald_cmu_irq_cbk(CMU_HOSC_START);
199 }
200
201 /* LOSC stop */
202 if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK)) {
203 SYSCFG_UNLOCK();
204 SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK);
205 SYSCFG_LOCK();
206 ald_cmu_irq_cbk(CMU_LOSC_STOP);
207 }
208
209 /* LOSC start */
210 if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK) && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIE_MSK)) {
211 SYSCFG_UNLOCK();
212 SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STRIF_MSK);
213 SYSCFG_LOCK();
214 ald_cmu_irq_cbk(CMU_LOSC_START);
215 }
216
217 /* PLL1 lose */
218 if (READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK) && READ_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK)) {
219 SYSCFG_UNLOCK();
220 SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK);
221 SYSCFG_LOCK();
222
223 if (READ_BIT(CMU->PULMCR, CMU_PULMCR_CLKS_MSK)
224 && ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 1)
225 || ((READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) == 5))))
226 cmu_clock_update(READ_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK) ? 2000000 : 24000000);
227 ald_cmu_irq_cbk(CMU_PLL1_UNLOCK);
228 }
229
230 return;
231 }
263 ald_status_t ald_cmu_clock_config_default(void)
264 {
265 uint32_t cnt = 4000, tmp;
266
267 SYSCFG_UNLOCK();
268
269 /* Select HRC */
270 MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS);
271
272 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
273
274 if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) {
275 SYSCFG_LOCK();
276 return ERROR;
277 }
278
279 WRITE_REG(CMU->CFGR, 0x0);
280 CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFST_MSK); /* Select 24Mhz */
281
282 tmp = READ_REG(CMU->CLKENR);
283 /* Enable HRC/LRC/LOSC */
284 SET_BIT(tmp, CMU_CLKENR_HRCEN_MSK | CMU_CLKENR_LRCEN_MSK | CMU_CLKENR_LOSCEN_MSK);
285 WRITE_REG(CMU->CLKENR, tmp);
286 /* Reset LRC */
287 for (cnt = 0; cnt < 10000; ++cnt);
288 CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK);
289 SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK);
290
291 SYSCFG_LOCK();
292 return OK;
293 }
294
307 ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock)
308 {
309 uint32_t cnt = 4000;
310
311 assert_param(IS_CMU_CLOCK(clk));
312 SYSCFG_UNLOCK();
313
314 switch (clk) {
315 case CMU_CLOCK_HRC:
316 assert_param(clock == 24000000 || clock == 2000000);
317
318 MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HRC << CMU_CSR_SYS_CMD_POSS);
319 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
320
321 if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HRC) {
322 SYSCFG_LOCK();
323 return ERROR;
324 }
325
326 if (clock == 24000000)
327 CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK);
328 else
329 SET_BIT(CMU->CFGR, CMU_CFGR_HRCFSW_MSK);
330
331 SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK);
332
333 for (cnt = 4000; cnt; --cnt);
334 cnt = 4000;
335 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCACT_MSK))) && (--cnt));
336 cnt = 4000;
337 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HRCRDY_MSK))) && (--cnt));
338
339 cmu_clock_update(clock);
340 break;
341
342 case CMU_CLOCK_LRC:
343 /* Close SysTick interrupt in lower clock */
344 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
345
346 MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LRC << CMU_CSR_SYS_CMD_POSS);
347 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
348
349 if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LRC) {
350 SYSCFG_LOCK();
351 return ERROR;
352 }
353
354 SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK);
355
356 cnt = 4000;
357 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCACT_MSK))) && (--cnt));
358 cnt = 4000;
359 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LRCRDY_MSK))) && (--cnt));
360
361 cmu_clock_update(32768);
362 break;
363
364 case CMU_CLOCK_LOSC:
365 /* Close SysTick interrupt in lower clock */
366 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
367
368 MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_LOSC << CMU_CSR_SYS_CMD_POSS);
369 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
370
371 if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_LOSC) {
372 SYSCFG_LOCK();
373 return ERROR;
374 }
375
376 SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK);
377
378 cnt = 4000;
379 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCACT_MSK))) && (--cnt));
380 cnt = 4000;
381 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_LOSCRDY_MSK))) && (--cnt));
382
383 cmu_clock_update(32768);
384 break;
385
386 case CMU_CLOCK_PLL1:
387 for (cnt = 0; cnt < 5000; ++cnt);
388 MODIFY_REG(CMU->CSR, CMU_CSR_CFT_CMD_MSK, 0xAA << CMU_CSR_CFT_CMD_POSS);
389 MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_PLL1 << CMU_CSR_SYS_CMD_POSS);
390 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
391
392 if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_PLL1) {
393 SYSCFG_LOCK();
394 return ERROR;
395 }
396
397 SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK);
398
399 for (cnt = 0; cnt < 5000; ++cnt);
400 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1ACT_MSK))) && (--cnt));
401 cnt = 4000;
402 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt));
403
404 if (clock == 96000000) {
405 ald_cmu_div_config(CMU_HCLK_1, CMU_DIV_2);
406 ald_cmu_div_config(CMU_HCLK_2, CMU_DIV_2);
407 ald_cmu_div_config(CMU_PCLK_1, CMU_DIV_2);
408 ald_cmu_div_config(CMU_PCLK_2, CMU_DIV_4);
409 for (cnt = 0; cnt < 20000; ++cnt);
410 }
411 if (clock == 72000000) {
412 ald_cmu_div_config(CMU_PCLK_2, CMU_DIV_4);
413 }
414 if ((clock == 48000000) || (clock == 36000000)) {
415 ald_cmu_div_config(CMU_PCLK_2, CMU_DIV_2);
416 }
417
418 cmu_clock_update(clock);
419 break;
420
421 case CMU_CLOCK_HOSC:
422 assert_param(clock <= 24000000);
423
424 MODIFY_REG(CMU->CSR, CMU_CSR_SYS_CMD_MSK, CMU_CLOCK_HOSC << CMU_CSR_SYS_CMD_POSS);
425 while (READ_BIT(CMU->CSR, CMU_CSR_SYS_RDYN_MSK) && (--cnt));
426
427 if (READ_BITS(CMU->CSR, CMU_CSR_SYS_STU_MSK, CMU_CSR_SYS_STU_POSS) != CMU_CLOCK_HOSC) {
428 SYSCFG_LOCK();
429 return ERROR;
430 }
431
432 SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK);
433 MODIFY_REG(CMU->HOSCCFG, CMU_HOSCCFG_FREQ_MSK, clock / 1000000 - 1);
434
435 for (cnt = 8000; cnt; --cnt);
436 cnt = 4000;
437 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCACT_MSK))) && (--cnt));
438 cnt = 4000;
439 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt));
440
441 cmu_clock_update(clock);
442 break;
443
444 default:
445 break;
446 }
447
448 SYSCFG_LOCK();
449 return OK;
450 }
451
452
453
462 void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output)
463 {
464 uint32_t cnt = 4000;
465
466 assert_param(IS_CMU_PLL1_INPUT(input));
467 assert_param(IS_CMU_PLL1_OUTPUT(output));
468
469 SYSCFG_UNLOCK();
470
471 if (input == CMU_PLL1_INPUT_HRC_6) {
472 SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK);
473 }
474 else if (input == CMU_PLL1_INPUT_PLL2) {
475 SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK);
476 CLEAR_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2RFS_MSK);
477 SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK);
478 }
479 else {
480 SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK);
481 for (cnt = 0; cnt < 10000; ++cnt);
482 cnt = 20000;
483 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_HOSCRDY_MSK))) && (--cnt));
484 }
485
486 MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1RFS_MSK, input << CMU_PLLCFG_PLL1RFS_POSS);
487 MODIFY_REG(CMU->PLLCFG, CMU_PLLCFG_PLL1OS_MSK, output << CMU_PLLCFG_PLL1OS_POSS);
488 SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK);
489
490 for (cnt = 0; cnt < 4000; ++cnt);
491 while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL1LCKN_MSK)) && (--cnt));
492 cnt = 4000;
493 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL1RDY_MSK))) && (--cnt));
494
495 SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK);
496 MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 0x3 << CMU_PULMCR_MODE_POSS);
497
498 SYSCFG_LOCK();
499 return;
500 }
501
506 uint32_t ald_cmu_get_clock(void)
507 {
508 return __system_clock;
509 }
510
543 void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div)
544 {
545 assert_param(IS_CMU_BUS(bus));
546 assert_param(IS_CMU_DIV(div));
547
548 SYSCFG_UNLOCK();
549
550 switch (bus) {
551 case CMU_HCLK_1:
552 MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, div << CMU_CFGR_HCLK1DIV_POSS);
553 break;
554
555 case CMU_HCLK_2:
556 MODIFY_REG(CMU->CFGR, CMU_CFGR_HCLK2DIV_MSK, div << CMU_CFGR_HCLK2DIV_POSS);
557 break;
558
559 case CMU_SYS:
560 MODIFY_REG(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, div << CMU_CFGR_SYSDIV_POSS);
561
562 if ((__system_clock >> div) <= 1000000) {
563 /* Close SysTick interrupt in lower clock */
564 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
565 }
566 else {
567 ald_tick_init(TICK_INT_PRIORITY);
568 }
569
570 break;
571
572 case CMU_PCLK_1:
573 MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, div << CMU_CFGR_PCLK1DIV_POSS);
574 break;
575
576 case CMU_PCLK_2:
577 MODIFY_REG(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, div << CMU_CFGR_PCLK2DIV_POSS);
578 break;
579
580 default:
581 break;
582 }
583
584 SYSCFG_LOCK();
585 return;
586 }
587
592 uint32_t ald_cmu_get_hclk1_clock(void)
593 {
594 uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS);
595 uint32_t ahb_div = READ_BITS(CMU->CFGR, CMU_CFGR_HCLK1DIV_MSK, CMU_CFGR_HCLK1DIV_POSS);
596
597 return (__system_clock >> sys_div) >> ahb_div;
598 }
599
604 uint32_t ald_cmu_get_hclk2_clock(void)
605 {
606 uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS);
607 uint32_t ahb_div = READ_BITS(CMU->CFGR, CMU_CFGR_HCLK2DIV_MSK, CMU_CFGR_HCLK2DIV_POSS);
608
609 return (__system_clock >> sys_div) >> ahb_div;
610 }
611
616 uint32_t ald_cmu_get_sys_clock(void)
617 {
618 uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS);
619
620 return __system_clock >> sys_div;
621 }
622
627 uint32_t ald_cmu_get_pclk1_clock(void)
628 {
629 uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS);
630 uint32_t apb1_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK1DIV_MSK, CMU_CFGR_PCLK1DIV_POSS);
631
632 return (__system_clock >> sys_div) >> apb1_div;
633 }
634
639 uint32_t ald_cmu_get_pclk2_clock(void)
640 {
641 uint32_t sys_div = READ_BITS(CMU->CFGR, CMU_CFGR_SYSDIV_MSK, CMU_CFGR_SYSDIV_POSS);
642 uint32_t apb2_div = READ_BITS(CMU->CFGR, CMU_CFGR_PCLK2DIV_MSK, CMU_CFGR_PCLK2DIV_POSS);
643
644 return (__system_clock >> sys_div) >> apb2_div;
645 }
673 void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status)
674 {
675 assert_param(IS_CMU_HOSC_RANGE(clock));
676 assert_param(IS_FUNC_STATE(status));
677
678 SYSCFG_UNLOCK();
679
680 if (status) {
681 SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIF_MSK);
682 MODIFY_REG(CMU->HOSMCR, CMU_HOSMCR_FRQS_MSK, clock << CMU_HOSMCR_FRQS_POSS);
683 SET_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK);
684 SET_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK);
685
686 ald_mcu_irq_config(CMU_IRQn, 3, 3, ENABLE);
687 }
688 else {
689 CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK);
690 CLEAR_BIT(CMU->HOSMCR, CMU_HOSMCR_STPIE_MSK);
691
692 if (READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0)
693 ald_mcu_irq_config(CMU_IRQn, 3, 3, DISABLE);
694 }
695
696 SYSCFG_LOCK();
697 return;
698 }
699
705 void ald_cmu_losc_safe_config(type_func_t status)
706 {
707 assert_param(IS_FUNC_STATE(status));
708 SYSCFG_UNLOCK();
709
710 if (status) {
711 SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIF_MSK);
712 SET_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK);
713 SET_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK);
714
715 ald_mcu_irq_config(CMU_IRQn, 3, 3, ENABLE);
716 }
717 else {
718 CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK);
719 CLEAR_BIT(CMU->LOSMCR, CMU_LOSMCR_STPIE_MSK);
720
721 if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK) == 0)
722 ald_mcu_irq_config(CMU_IRQn, 3, 3, DISABLE);
723 }
724
725 SYSCFG_LOCK();
726 return;
727 }
728
734 void ald_cmu_pll_safe_config(type_func_t status)
735 {
736 assert_param(IS_FUNC_STATE(status));
737 SYSCFG_UNLOCK();
738
739 if (status) {
740 SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIF_MSK);
741 MODIFY_REG(CMU->PULMCR, CMU_PULMCR_MODE_MSK, 2 << CMU_PULMCR_MODE_POSS);
742 SET_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK);
743 SET_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK);
744
745 ald_mcu_irq_config(CMU_IRQn, 3, 3, ENABLE);
746 }
747 else {
748 CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_EN_MSK);
749 CLEAR_BIT(CMU->PULMCR, CMU_PULMCR_ULKIE_MSK);
750
751 if (READ_BIT(CMU->HOSMCR, CMU_HOSMCR_EN_MSK) == 0 && READ_BIT(CMU->LOSMCR, CMU_LOSMCR_EN_MSK) == 0)
752 ald_mcu_irq_config(CMU_IRQn, 3, 3, DISABLE);
753 }
754
755 SYSCFG_LOCK();
756 return;
757 }
758
766 uint32_t ald_cmu_current_clock_source_get(cmu_clock_safe_type_t type)
767 {
768 assert_param(IS_CMU_SAFE_CLOCK_TYPE(type));
769
770 if (type == CMU_SAFE_CLK_HOSC)
771 return READ_BITS(CMU->HOSMCR, CMU_HOSMCR_CLKS_MSK, CMU_HOSMCR_CLKS_POS);
772 else if (type == CMU_SAFE_CLK_LOSC)
773 return READ_BITS(CMU->LOSMCR, CMU_LOSMCR_CLKS_MSK, CMU_LOSMCR_CLKS_POS);
774 else
775 return READ_BITS(CMU->PULMCR, CMU_PULMCR_CLKS_MSK, CMU_PULMCR_CLKS_POS);
776 }
777
783 flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr)
784 {
785 assert_param(IS_CMU_CLOCK_STATE(sr));
786
787 if (READ_BIT(CMU->CLKSR, sr))
788 return SET;
789
790 return RESET;
791 }
792
799 __weak void ald_cmu_irq_cbk(cmu_security_t se)
800 {
801 return;
802 }
845 void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel,
846 cmu_output_high_div_t div, type_func_t status)
847 {
848 assert_param(IS_CMU_OUTPUT_HIGH_SEL(sel));
849 assert_param(IS_CMU_OUTPUT_HIGH_DIV(div));
850 assert_param(IS_FUNC_STATE(status));
851
852 SYSCFG_UNLOCK();
853
854 if (status) {
855 MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCOS_MSK, sel << CMU_CLKOCR_HSCOS_POSS);
856 MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_HSCODIV_MSK, div << CMU_CLKOCR_HSCODIV_POSS);
857 SET_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK);
858 }
859 else {
860 CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_HSCOEN_MSK);
861 }
862
863 SYSCFG_LOCK();
864 return;
865 }
866
878 void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status)
879 {
880 assert_param(IS_CMU_OUTPUT_LOW_SEL(sel));
881 assert_param(IS_FUNC_STATE(status));
882
883 SYSCFG_UNLOCK();
884
885 if (status) {
886 MODIFY_REG(CMU->CLKOCR, CMU_CLKOCR_LSCOS_MSK, sel << CMU_CLKOCR_LSCOS_POSS);
887 SET_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK);
888 }
889 else {
890 CLEAR_BIT(CMU->CLKOCR, CMU_CLKOCR_LSCOEN_MSK);
891 }
892
893 SYSCFG_LOCK();
894 return;
895 }
926 void ald_cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status)
927 {
928 assert_param(IS_CMU_BUZZ_DIV(div));
929 assert_param(IS_FUNC_STATE(status));
930
931 SYSCFG_UNLOCK();
932
933 if (status) {
934 MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DIV_MSK, div << CMU_BUZZCR_DIV_POSS);
935 MODIFY_REG(CMU->BUZZCR, CMU_BUZZCR_DAT_MSK, dat << CMU_BUZZCR_DAT_POSS);
936 SET_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK);
937 }
938 else {
939 CLEAR_BIT(CMU->BUZZCR, CMU_BUZZCR_EN_MSK);
940 }
941
942 SYSCFG_LOCK();
943 return;
944 }
945
963 void ald_cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock)
964 {
965 assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock));
966
967 SYSCFG_UNLOCK();
968 MODIFY_REG(CMU->PERICR, CMU_PERICR_LPTIM0_MSK, clock << CMU_PERICR_LPTIM0_POSS);
969 SYSCFG_LOCK();
970
971 return;
972 }
973
991 void ald_cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock)
992 {
993 assert_param(IS_CMU_LP_PERH_CLOCK_SEL(clock));
994
995 SYSCFG_UNLOCK();
996 MODIFY_REG(CMU->PERICR, CMU_PERICR_LPUART0_MSK, clock << CMU_PERICR_LPUART0_POSS);
997 SYSCFG_LOCK();
998
999 return;
1000 }
1001
1013 void ald_cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock)
1014 {
1015 assert_param(IS_CMU_LCD_CLOCK_SEL(clock));
1016
1017 SYSCFG_UNLOCK();
1018 MODIFY_REG(CMU->PERICR, CMU_PERICR_LCD_MSK, clock << CMU_PERICR_LCD_POSS);
1019 SYSCFG_LOCK();
1020
1021 return;
1022 }
1023
1029 void ald_cmu_qspi_clock_select(cmu_qspi_clock_sel_t clock)
1030 {
1031 assert_param(IS_CMU_QSPI_CLOCK_SEL(clock));
1032
1033 SYSCFG_UNLOCK();
1034 MODIFY_REG(CMU->PERICR, CMU_PERICR_QSPICS_MSK, clock << CMU_PERICR_QSPICS_POSS);
1035 SYSCFG_LOCK();
1036
1037 return;
1038 }
1039
1046 void ald_cmu_usb_clock_config(cmu_usb_clock_sel_t clock, cmu_usb_div_t div)
1047 {
1048 assert_param(IS_CMU_USB_CLOCK_SEL(clock));
1049 assert_param(IS_CMU_USB_DIV(div));
1050
1051 SYSCFG_UNLOCK();
1052
1053 if (clock == CMU_USB_CLOCK_SEL_HRC)
1054 SET_BIT(SYSCFG->USBCFG, SYSCFG_USBCFG_CLKRDYBP_MSK);
1055 else
1056 CLEAR_BIT(SYSCFG->USBCFG, SYSCFG_USBCFG_CLKRDYBP_MSK);
1057
1058 MODIFY_REG(CMU->PERICR, CMU_PERICR_USBPHYCS_MSK, clock << CMU_PERICR_USBPHYCS_POSS);
1059 MODIFY_REG(CMU->PERIDIVR, CMU_PERIDIVR_USBPHYDIV_MSK, div << CMU_PERIDIVR_USBPHYDIV_POSS);
1060 SYSCFG_LOCK();
1061
1062 return;
1063 }
1064
1071 void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status)
1072 {
1073 uint32_t idx, pos;
1074
1075 assert_param(IS_CMU_PERH(perh));
1076 assert_param(IS_FUNC_STATE(status));
1077
1078 SYSCFG_UNLOCK();
1079
1080 if (perh == CMU_PERH_ALL) {
1081 if (status) {
1082 WRITE_REG(CMU->AHB1ENR, ~0);
1083 WRITE_REG(CMU->APB1ENR, ~0);
1084 WRITE_REG(CMU->APB2ENR, ~0);
1085 }
1086 else {
1087 WRITE_REG(CMU->AHB1ENR, 0);
1088 WRITE_REG(CMU->APB1ENR, 0);
1089 WRITE_REG(CMU->APB2ENR, 0);
1090 }
1091
1092 SYSCFG_LOCK();
1093 return;
1094 }
1095
1096 idx = (perh >> 27) & 0x3;
1097 pos = perh & ~(0x3 << 27);
1098
1099 if (status) {
1100 switch (idx) {
1101 case 0:
1102 SET_BIT(CMU->AHB1ENR, pos);
1103 break;
1104
1105 case 1:
1106 SET_BIT(CMU->APB1ENR, pos);
1107 break;
1108
1109 case 2:
1110 SET_BIT(CMU->APB2ENR, pos);
1111 break;
1112
1113 default:
1114 break;
1115 }
1116 }
1117 else {
1118 switch (idx) {
1119 case 0:
1120 CLEAR_BIT(CMU->AHB1ENR, pos);
1121 break;
1122
1123 case 1:
1124 CLEAR_BIT(CMU->APB1ENR, pos);
1125 break;
1126
1127 case 2:
1128 CLEAR_BIT(CMU->APB2ENR, pos);
1129 break;
1130
1131 default:
1132 break;
1133 }
1134 }
1135
1136 SYSCFG_LOCK();
1137 return;
1138 }
1139
1145 void ald_cmu_stop1_clock_sel(cmu_stop1_clock_t clock)
1146 {
1147 assert_param(IS_CMU_STOP1_CLOCK(clock));
1148
1149 SYSCFG_UNLOCK();
1150 MODIFY_REG(CMU->LPENR, CMU_LPENR_STOP1CS_MSK, clock << CMU_LPENR_STOP1CS_POSS);
1151 SYSCFG_LOCK();
1152 return;
1153 }
ald_cmu_hosc_safe_config
void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status)
Enable/Disable outer high crystal safe mode.
Definition: ald_cmu.c:673
ald_cmu_get_clock
uint32_t ald_cmu_get_clock(void)
Gets current system clock.
Definition: ald_cmu.c:506
ald_cmu_losc_safe_config
void ald_cmu_losc_safe_config(type_func_t status)
Enable/Disable outer low crystal safe mode.
Definition: ald_cmu.c:705
IS_CMU_LP_PERH_CLOCK_SEL
#define IS_CMU_LP_PERH_CLOCK_SEL(x)
Definition: ald_cmu.h:589
CMU_LOSC_STOP
Definition: ald_cmu.h:464
ald_cmu_stop1_clock_sel
void ald_cmu_stop1_clock_sel(cmu_stop1_clock_t clock)
Select stop1 clock.
Definition: ald_cmu.c:1145
ald_cmu_pll_safe_config
void ald_cmu_pll_safe_config(type_func_t status)
Enable/Disable PLL1 safe mode.
Definition: ald_cmu.c:734
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
ald_cmu_get_clock_state
flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr)
Get clock state.
Definition: ald_cmu.c:783
CMU_DIV_2
Definition: ald_cmu.h:231
IS_CMU_OUTPUT_HIGH_DIV
#define IS_CMU_OUTPUT_HIGH_DIV(x)
Definition: ald_cmu.h:565
ald_cmu_get_hclk1_clock
uint32_t ald_cmu_get_hclk1_clock(void)
Get AHB1 clock.
Definition: ald_cmu.c:592
ald_cmu_qspi_clock_select
void ald_cmu_qspi_clock_select(cmu_qspi_clock_sel_t clock)
Select QSPI clock source.
Definition: ald_cmu.c:1029
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
cmu_output_high_sel_t
cmu_output_high_sel_t
Output high clock select.
Definition: ald_cmu.h:259
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
cmu_pll1_output_t
cmu_pll1_output_t
PLL1 output clock.
Definition: ald_cmu.h:183
READ_REG
#define READ_REG(reg)
Definition: type.h:73
ald_cmu_lpuart0_clock_select
void ald_cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock)
Select lpuart0 clock source.
Definition: ald_cmu.c:991
SET
Definition: type.h:39
CMU_CLOCK_HOSC
Definition: ald_cmu.h:177
IS_CMU_PERH
#define IS_CMU_PERH(x)
Definition: ald_cmu.h:631
CMU_CLOCK_HRC
Definition: ald_cmu.h:173
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
CMU_CLOCK_LOSC
Definition: ald_cmu.h:175
type_func_t
type_func_t
Definition: type.h:47
DISABLE
Definition: type.h:48
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
cmu_hosc_range_t
cmu_hosc_range_t
HOSC range.
Definition: ald_cmu.h:209
ald_cmu_get_hclk2_clock
uint32_t ald_cmu_get_hclk2_clock(void)
Get AHB2 clock.
Definition: ald_cmu.c:604
CMU_HOSC_START
Definition: ald_cmu.h:468
IS_CMU_PLL1_INPUT
#define IS_CMU_PLL1_INPUT(x)
Definition: ald_cmu.h:526
IS_CMU_QSPI_CLOCK_SEL
#define IS_CMU_QSPI_CLOCK_SEL(x)
Definition: ald_cmu.h:607
IS_CMU_CLOCK
#define IS_CMU_CLOCK(x)
Definition: ald_cmu.h:511
CMU_PLL1_UNLOCK
Definition: ald_cmu.h:466
CMU_SAFE_CLK_LOSC
Definition: ald_cmu.h:222
ald_cmu_output_low_clock_config
void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status)
Configure the low-speed clock output.
Definition: ald_cmu.c:878
ald_flash.h
Header file of FLASH driver.
ald_cmu_get_sys_clock
uint32_t ald_cmu_get_sys_clock(void)
Get SYS clock.
Definition: ald_cmu.c:616
ald_cmu_clock_config_default
ald_status_t ald_cmu_clock_config_default(void)
Configure system clock using default. Select CMU_CLOCK_HRC(24MHz) as system clock and enable CMU_CLOC...
Definition: ald_cmu.c:263
cmu_clock_t
cmu_clock_t
CMU state structure definition.
Definition: ald_cmu.h:172
cmu_usb_div_t
cmu_usb_div_t
USB clock division.
Definition: ald_cmu.h:365
cmu_usb_clock_sel_t
cmu_usb_clock_sel_t
USB clock select.
Definition: ald_cmu.h:354
__system_clock
uint32_t __system_clock
Definition: ald_cmu.c:144
RESET
Definition: type.h:38
cmu_bus_t
cmu_bus_t
Bus type.
Definition: ald_cmu.h:248
ald_cmu_buzz_config
void ald_cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status)
Configure buzz clock. freq = sysclk / (2^(div + 1) * (dat + 1))
Definition: ald_cmu.c:926
cmu_security_t
cmu_security_t
CMU interrupt type.
Definition: ald_cmu.h:463
cmu_output_low_sel_t
cmu_output_low_sel_t
Output low clock select.
Definition: ald_cmu.h:287
cmu_output_high_div_t
cmu_output_high_div_t
Output frequency division.
Definition: ald_cmu.h:273
CMU_CLOCK_PLL1
Definition: ald_cmu.h:176
ald_tick_init
__weak void ald_tick_init(uint32_t prio)
This function configures the source of the time base. The time source is configured to have 1ms time ...
Definition: utils.c:138
IS_CMU_HOSC_RANGE
#define IS_CMU_HOSC_RANGE(x)
Definition: ald_cmu.h:534
IS_CMU_USB_DIV
#define IS_CMU_USB_DIV(x)
Definition: ald_cmu.h:618
IS_CMU_OUTPUT_HIGH_SEL
#define IS_CMU_OUTPUT_HIGH_SEL(x)
Definition: ald_cmu.h:557
cmu_clock_state_t
cmu_clock_state_t
CMU clock state type.
Definition: ald_cmu.h:474
ald_cmu_current_clock_source_get
uint32_t ald_cmu_current_clock_source_get(cmu_clock_safe_type_t type)
Get current clock source.
Definition: ald_cmu.c:766
CMU_PLL1_INPUT_HRC_6
Definition: ald_cmu.h:196
ald_cmu_lptim0_clock_select
void ald_cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock)
Select lptim0 clock source.
Definition: ald_cmu.c:963
CMU_PLL1_INPUT_PLL2
Definition: ald_cmu.h:197
CMU_CLOCK_LRC
Definition: ald_cmu.h:174
CMU_PERH_ALL
Definition: ald_cmu.h:457
ald_cmu_get_pclk2_clock
uint32_t ald_cmu_get_pclk2_clock(void)
Get APB2 clock.
Definition: ald_cmu.c:639
ald_mcu_irq_config
void ald_mcu_irq_config(IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, type_func_t status)
Configure interrupt.
Definition: utils.c:375
ald_cmu.h
Header file of CMU module driver.
CMU_HCLK_1
Definition: ald_cmu.h:249
CMU_SAFE_CLK_HOSC
Definition: ald_cmu.h:221
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
IS_CMU_STOP1_CLOCK
#define IS_CMU_STOP1_CLOCK(x)
Definition: ald_cmu.h:693
IS_CMU_DIV
#define IS_CMU_DIV(x)
Definition: ald_cmu.h:539
IS_CMU_SAFE_CLOCK_TYPE
#define IS_CMU_SAFE_CLOCK_TYPE(x)
Definition: ald_cmu.h:578
CMU_HCLK_2
Definition: ald_cmu.h:250
ald_cmu_pll1_config
void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output)
Configure PLL1 using specified parameters.
Definition: ald_cmu.c:462
ald_cmu_get_pclk1_clock
uint32_t ald_cmu_get_pclk1_clock(void)
Get APB1 clock.
Definition: ald_cmu.c:627
cmu_pll1_input_t
cmu_pll1_input_t
PLL1 referance clock.
Definition: ald_cmu.h:195
ald_cmu_div_config
void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div)
Configure the bus division.
Definition: ald_cmu.c:543
CMU_PCLK_1
Definition: ald_cmu.h:252
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
CMU_HOSC_STOP
Definition: ald_cmu.h:465
IS_CMU_LCD_CLOCK_SEL
#define IS_CMU_LCD_CLOCK_SEL(x)
Definition: ald_cmu.h:601
cmu_div_t
cmu_div_t
Frequency division select bit.
Definition: ald_cmu.h:229
IS_CMU_BUZZ_DIV
#define IS_CMU_BUZZ_DIV(x)
Definition: ald_cmu.h:581
ald_cmu_irq_handler
void ald_cmu_irq_handler(void)
CMU module interrupt handler.
Definition: ald_cmu.c:174
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
IS_CMU_OUTPUT_LOW_SEL
#define IS_CMU_OUTPUT_LOW_SEL(x)
Definition: ald_cmu.h:573
IS_CMU_USB_CLOCK_SEL
#define IS_CMU_USB_CLOCK_SEL(x)
Definition: ald_cmu.h:613
CMU_LOSC_START
Definition: ald_cmu.h:467
cmu_clock_update
static void cmu_clock_update(uint32_t clock)
Update the current system clock. This function will be invoked, when system clock has changed...
Definition: ald_cmu.c:160
CMU_PCLK_2
Definition: ald_cmu.h:253
cmu_stop1_clock_t
cmu_stop1_clock_t
Stop1 clock select type.
Definition: ald_cmu.h:493
ald_cmu_output_high_clock_config
void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel, cmu_output_high_div_t div, type_func_t status)
Configure the high-speed clock output.
Definition: ald_cmu.c:845
cmu_lcd_clock_sel_t
cmu_lcd_clock_sel_t
LCD clock select.
Definition: ald_cmu.h:330
flag_status_t
flag_status_t
Definition: type.h:37
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
CMU_SYS
Definition: ald_cmu.h:251
ald_cmu_clock_config
ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock)
Configure system clock using specified parameters.
Definition: ald_cmu.c:307
cmu_lp_perh_clock_sel_t
cmu_lp_perh_clock_sel_t
Low power peripheral clock select.
Definition: ald_cmu.h:312
CMU_DIV_4
Definition: ald_cmu.h:232
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
cmu_perh_t
cmu_perh_t
Peripheral clock enable/disable.
Definition: ald_cmu.h:408
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
ald_cmu_irq_cbk
__weak void ald_cmu_irq_cbk(cmu_security_t se)
Interrupt callback function.
Definition: ald_cmu.c:799
IS_CMU_CLOCK_STATE
#define IS_CMU_CLOCK_STATE(x)
Definition: ald_cmu.h:680
TICK_INT_PRIORITY
#define TICK_INT_PRIORITY
Definition: ald_conf.h:62
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
ERROR
Definition: utils.h:56
cmu_clock_safe_type_t
cmu_clock_safe_type_t
Safe clock source type.
Definition: ald_cmu.h:220
CMU_USB_CLOCK_SEL_HRC
Definition: ald_cmu.h:356
IS_CMU_BUS
#define IS_CMU_BUS(x)
Definition: ald_cmu.h:552
ald_cmu_lcd_clock_select
void ald_cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock)
Select lcd clock source.
Definition: ald_cmu.c:1013
ald_cmu_perh_clock_config
void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status)
Enable/Disable peripheral clock.
Definition: ald_cmu.c:1071
cmu_qspi_clock_sel_t
cmu_qspi_clock_sel_t
QSPI clock select.
Definition: ald_cmu.h:342
ald_cmu_usb_clock_config
void ald_cmu_usb_clock_config(cmu_usb_clock_sel_t clock, cmu_usb_div_t div)
Configure USB clock source.
Definition: ald_cmu.c:1046
cmu_buzz_div_t
cmu_buzz_div_t
BUZZ frequency division.
Definition: ald_cmu.h:298


ALD User Manual: D:/svn/src/ald_cmu.h Source File

  • D:
  • svn
  • src
ald_cmu.h
Go to the documentation of this file.
1
17 #ifndef __ALD_CMU_H__
18 #define __ALD_CMU_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25 #include "ald_syscfg.h"
26
27
39 #define CMU_HRC_SEL_BY_SW() \
40 do { \
41 SYSCFG_UNLOCK(); \
42 SET_BIT(CMU->CFGR, CMU_CFGR_HRCFCS_MSK); \
43 SYSCFG_LOCK(); \
44 } while (0)
45 #define CMU_HRC_SEL_BY_CFGW() \
46 do { \
47 SYSCFG_UNLOCK(); \
48 CLEAR_BIT(CMU->CFGR, CMU_CFGR_HRCFCS_MSK); \
49 SYSCFG_LOCK(); \
50 } while (0)
51 #define CMU_HRC_DIV_1MHZ_ENABLE() \
52 do { \
53 SYSCFG_UNLOCK(); \
54 SET_BIT(CMU->CLKENR, CMU_CLKENR_HRC1MEN_MSK); \
55 SYSCFG_LOCK(); \
56 } while (0)
57 #define CMU_HRC_DIV_1MHZ_DISABLE() \
58 do { \
59 SYSCFG_UNLOCK(); \
60 CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HRC1MEN_MSK); \
61 SYSCFG_LOCK(); \
62 } while (0)
63 #define CMU_HOSC_DIV_1MHZ_ENABLE() \
64 do { \
65 SYSCFG_UNLOCK(); \
66 SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSC1MEN_MSK); \
67 SYSCFG_LOCK(); \
68 } while (0)
69 #define CMU_HOSC_DIV_1MHZ_DISABLE() \
70 do { \
71 SYSCFG_UNLOCK(); \
72 CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HOSC1MEN_MSK);\
73 SYSCFG_LOCK(); \
74 } while (0)
75 #define CMU_LOSC_ENABLE() \
76 do { \
77 SYSCFG_UNLOCK(); \
78 SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \
79 SYSCFG_LOCK(); \
80 } while (0)
81 #define CMU_LOSC_DISABLE() \
82 do { \
83 SYSCFG_UNLOCK(); \
84 CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK); \
85 SYSCFG_LOCK(); \
86 } while (0)
87 #define CMU_LRC_ENABLE() \
88 do { \
89 SYSCFG_UNLOCK(); \
90 SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \
91 SYSCFG_LOCK(); \
92 } while (0)
93 #define CMU_LRC_DISABLE() \
94 do { \
95 SYSCFG_UNLOCK(); \
96 CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK); \
97 SYSCFG_LOCK(); \
98 } while (0)
99 #define CMU_ULRC_ENABLE() \
100 do { \
101 SYSCFG_UNLOCK(); \
102 SET_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \
103 SYSCFG_LOCK(); \
104 } while (0)
105 #define CMU_ULRC_DISABLE() \
106 do { \
107 SYSCFG_UNLOCK(); \
108 CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK); \
109 SYSCFG_LOCK(); \
110 } while (0)
111
112 /* Low power mode control */
113 #define CMU_LP_LRC_ENABLE() \
114 do { \
115 SYSCFG_UNLOCK(); \
116 SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \
117 SYSCFG_LOCK(); \
118 } while (0)
119 #define CMU_LP_LRC_DISABLE() \
120 do { \
121 SYSCFG_UNLOCK(); \
122 CLEAR_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK); \
123 SYSCFG_LOCK(); \
124 } while (0)
125 #define CMU_LP_LOSC_ENABLE() \
126 do { \
127 SYSCFG_UNLOCK(); \
128 SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \
129 SYSCFG_LOCK(); \
130 } while (0)
131 #define CMU_LP_LOSC_DISABLE() \
132 do { \
133 SYSCFG_UNLOCK(); \
134 CLEAR_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK); \
135 SYSCFG_LOCK(); \
136 } while (0)
137 #define CMU_LP_HRC_ENABLE() \
138 do { \
139 SYSCFG_UNLOCK(); \
140 SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \
141 SYSCFG_LOCK(); \
142 } while (0)
143 #define CMU_LP_HRC_DISABLE() \
144 do { \
145 SYSCFG_UNLOCK(); \
146 CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK); \
147 SYSCFG_LOCK(); \
148 } while (0)
149 #define CMU_LP_HOSC_ENABLE() \
150 do { \
151 SYSCFG_UNLOCK(); \
152 SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \
153 SYSCFG_LOCK(); \
154 } while (0)
155 #define CMU_LP_HOSC_DISABLE() \
156 do { \
157 SYSCFG_UNLOCK(); \
158 CLEAR_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK); \
159 SYSCFG_LOCK(); \
160 } while (0)
161
172 typedef enum {
173 CMU_CLOCK_HRC = 0x1U,
174 CMU_CLOCK_LRC = 0x2U,
175 CMU_CLOCK_LOSC = 0x3U,
176 CMU_CLOCK_PLL1 = 0x4U,
177 CMU_CLOCK_HOSC = 0x5U,
178 } cmu_clock_t;
179
183 typedef enum {
184 CMU_PLL1_OUTPUT_36M = 0x0U,
185 CMU_PLL1_OUTPUT_48M = 0x1U,
186 #if defined(ES32F36xx) || defined(ES32F39xx)
187 CMU_PLL1_OUTPUT_72M = 0x2U,
188 CMU_PLL1_OUTPUT_96M = 0x3U,
189 #endif
190 } cmu_pll1_output_t;
191
195 typedef enum {
196 CMU_PLL1_INPUT_HRC_6 = 0x0U,
197 CMU_PLL1_INPUT_PLL2 = 0x1U,
198 CMU_PLL1_INPUT_HOSC = 0x2U,
199 CMU_PLL1_INPUT_HOSC_2 = 0x3U,
200 CMU_PLL1_INPUT_HOSC_3 = 0x4U,
201 CMU_PLL1_INPUT_HOSC_4 = 0x5U,
202 CMU_PLL1_INPUT_HOSC_5 = 0x6U,
203 CMU_PLL1_INPUT_HOSC_6 = 0x7U,
204 } cmu_pll1_input_t;
205
209 typedef enum {
210 CMU_HOSC_2M = 0x0U,
211 CMU_HOSC_4M = 0x1U,
212 CMU_HOSC_8M = 0x2U,
213 CMU_HOSC_16M = 0x3U,
214 CMU_HOSC_24M = 0x4U,
215 } cmu_hosc_range_t;
216
220 typedef enum {
221 CMU_SAFE_CLK_HOSC = 0x0U,
222 CMU_SAFE_CLK_LOSC = 0x1U,
223 CMU_SAFE_CLK_PLL = 0x2U,
224 } cmu_clock_safe_type_t;
225
229 typedef enum {
230 CMU_DIV_1 = 0x0U,
231 CMU_DIV_2 = 0x1U,
232 CMU_DIV_4 = 0x2U,
233 CMU_DIV_8 = 0x3U,
234 CMU_DIV_16 = 0x4U,
235 CMU_DIV_32 = 0x5U,
236 CMU_DIV_64 = 0x6U,
237 CMU_DIV_128 = 0x7U,
238 CMU_DIV_256 = 0x8U,
239 CMU_DIV_512 = 0x9U,
240 CMU_DIV_1024 = 0xAU,
241 CMU_DIV_2048 = 0xBU,
242 CMU_DIV_4096 = 0xCU,
243 } cmu_div_t;
244
248 typedef enum {
249 CMU_HCLK_1 = 0x0U,
250 CMU_HCLK_2 = 0x1U,
251 CMU_SYS = 0x2U,
252 CMU_PCLK_1 = 0x3U,
253 CMU_PCLK_2 = 0x4U,
254 } cmu_bus_t;
255
259 typedef enum {
260 CMU_OUTPUT_HIGH_SEL_HOSC = 0x0U,
261 CMU_OUTPUT_HIGH_SEL_LOSC = 0x1U,
262 CMU_OUTPUT_HIGH_SEL_HRC = 0x2U,
263 CMU_OUTPUT_HIGH_SEL_LRC = 0x3U,
264 CMU_OUTPUT_HIGH_SEL_HOSM = 0x4U,
265 CMU_OUTPUT_HIGH_SEL_PLL1 = 0x5U,
266 CMU_OUTPUT_HIGH_SEL_PLL2 = 0x6U,
267 CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7U,
268 } cmu_output_high_sel_t;
269
273 typedef enum {
274 CMU_OUTPUT_DIV_1 = 0x0U,
275 CMU_OUTPUT_DIV_2 = 0x1U,
276 CMU_OUTPUT_DIV_4 = 0x2U,
277 CMU_OUTPUT_DIV_8 = 0x3U,
278 CMU_OUTPUT_DIV_16 = 0x4U,
279 CMU_OUTPUT_DIV_32 = 0x5U,
280 CMU_OUTPUT_DIV_64 = 0x6U,
281 CMU_OUTPUT_DIV_128 = 0x7U,
282 } cmu_output_high_div_t;
283
287 typedef enum {
288 CMU_OUTPUT_LOW_SEL_LOSC = 0x0U,
289 CMU_OUTPUT_LOW_SEL_LRC = 0x1U,
290 CMU_OUTPUT_LOW_SEL_LOSM = 0x2U,
291 CMU_OUTPUT_LOW_SEL_BUZZ = 0x3U,
292 CMU_OUTPUT_LOW_SEL_ULRC = 0x4U,
293 } cmu_output_low_sel_t;
294
298 typedef enum {
299 CMU_BUZZ_DIV_2 = 0x0U,
300 CMU_BUZZ_DIV_4 = 0x1U,
301 CMU_BUZZ_DIV_8 = 0x2U,
302 CMU_BUZZ_DIV_16 = 0x3U,
303 CMU_BUZZ_DIV_32 = 0x4U,
304 CMU_BUZZ_DIV_64 = 0x5U,
305 CMU_BUZZ_DIV_128 = 0x6U,
306 CMU_BUZZ_DIV_256 = 0x7U,
307 } cmu_buzz_div_t;
308
312 typedef enum {
313 CMU_LP_PERH_CLOCK_SEL_PCLK2 = 0x0U,
314 CMU_LP_PERH_CLOCK_SEL_PLL1 = 0x1U,
315 CMU_LP_PERH_CLOCK_SEL_PLL2 = 0x2U,
316 CMU_LP_PERH_CLOCK_SEL_HRC = 0x3U,
317 CMU_LP_PERH_CLOCK_SEL_HOSC = 0x4U,
318 CMU_LP_PERH_CLOCK_SEL_LRC = 0x5U,
319 CMU_LP_PERH_CLOCK_SEL_LOSC = 0x6U,
320 CMU_LP_PERH_CLOCK_SEL_ULRC = 0x7U,
321 CMU_LP_PERH_CLOCK_SEL_HRC_1M = 0x8U,
322 CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9U,
323 CMU_LP_PERH_CLOCK_SEL_LOSM = 0xAU,
324 CMU_LP_PERH_CLOCK_SEL_HOSM = 0xBU,
325 } cmu_lp_perh_clock_sel_t;
326
330 typedef enum {
331 CMU_LCD_SEL_LOSM = 0x0U,
332 CMU_LCD_SEL_LOSC = 0x1U,
333 CMU_LCD_SEL_LRC = 0x2U,
334 CMU_LCD_SEL_ULRC = 0x3U,
335 CMU_LCD_SEL_HRC_1M = 0x4U,
336 CMU_LCD_SEL_HOSC_1M = 0x5U,
337 } cmu_lcd_clock_sel_t;
338
342 typedef enum {
343 CMU_QSPI_CLOCK_SEL_PCLK1 = 0x0U,
344 CMU_QSPI_CLOCK_SEL_HCLK2 = 0x1U,
345 CMU_QSPI_CLOCK_SEL_HRC = 0x2U,
346 CMU_QSPI_CLOCK_SEL_HOSC = 0x3U,
347 CMU_QSPI_CLOCK_SEL_PLL1 = 0x4U,
348 CMU_QSPI_CLOCK_SEL_HOSM = 0x5U,
349 } cmu_qspi_clock_sel_t;
350
354 typedef enum {
355 CMU_USB_CLOCK_SEL_HOSC = 0x0U,
356 CMU_USB_CLOCK_SEL_HRC = 0x1U,
357 CMU_USB_CLOCK_SEL_PCLK1 = 0x2U,
358 CMU_USB_CLOCK_SEL_PLL1 = 0x3U,
359 CMU_USB_CLOCK_SEL_HOSM = 0x4U,
360 } cmu_usb_clock_sel_t;
361
365 typedef enum {
366 CMU_USB_DIV_1 = 0x0U,
367 CMU_USB_DIV_2 = 0x1U,
368 CMU_USB_DIV_4 = 0x2U,
369 CMU_USB_DIV_8 = 0x3U,
370 CMU_USB_DIV_16 = 0x4U,
371 CMU_USB_DIV_32 = 0x5U,
372 CMU_USB_DIV_64 = 0x6U,
373 CMU_USB_DIV_128 = 0x7U,
374 CMU_USB_DIV_256 = 0x8U,
375 CMU_USB_DIV_512 = 0x9U,
376 CMU_USB_DIV_1024 = 0xAU,
377 CMU_USB_DIV_2048 = 0xBU,
378 CMU_USB_DIV_4096 = 0xCU,
379 } cmu_usb_div_t;
380
408 typedef enum {
409 CMU_PERH_GPIO = (1U << 0),
410 CMU_PERH_CRC = (1U << 1),
411 CMU_PERH_CALC = (1U << 2),
412 CMU_PERH_CRYPT = (1U << 3),
413 CMU_PERH_TRNG = (1U << 4),
414 CMU_PERH_PIS = (1U << 5),
415 CMU_PERH_EBI = (1U << 6),
416 CMU_PERH_QSPI_H = (1U << 7),
417 CMU_PERH_DMA = (1U << 8),
418 CMU_PERH_USB = (1U << 10),
419 CMU_PERH_ECC = (1U << 11),
420 CMU_PERH_TIMER0 = (1U << 0) | (1U << 27),
421 CMU_PERH_TIMER1 = (1U << 1) | (1U << 27),
422 CMU_PERH_TIMER2 = (1U << 2) | (1U << 27),
423 CMU_PERH_TIMER3 = (1U << 3) | (1U << 27),
424 CMU_PERH_TIMER4 = (1U << 4) | (1U << 27),
425 CMU_PERH_TIMER5 = (1U << 5) | (1U << 27),
426 CMU_PERH_TIMER6 = (1U << 6) | (1U << 27),
427 CMU_PERH_TIMER7 = (1U << 7) | (1U << 27),
428 CMU_PERH_UART0 = (1U << 8) | (1U << 27),
429 CMU_PERH_UART1 = (1U << 9) | (1U << 27),
430 CMU_PERH_UART2 = (1U << 10) | (1U << 27),
431 CMU_PERH_UART3 = (1U << 11) | (1U << 27),
432 CMU_PERH_UART4 = (1U << 12) | (1U << 27),
433 CMU_PERH_UART5 = (1U << 13) | (1U << 27),
434 CMU_PERH_SPI0 = (1U << 16) | (1U << 27),
435 CMU_PERH_SPI1 = (1U << 17) | (1U << 27),
436 CMU_PERH_SPI2 = (1U << 18) | (1U << 27),
437 CMU_PERH_I2C0 = (1U << 20) | (1U << 27),
438 CMU_PERH_I2C1 = (1U << 21) | (1U << 27),
439 CMU_PERH_CAN = (1U << 24) | (1U << 27),
440 CMU_PERH_QSPI_P = (1U << 25) | (1U << 27),
441 CMU_PERH_LPTIM0 = (1U << 0) | (1U << 28),
442 CMU_PERH_LPUART0 = (1U << 2) | (1U << 28),
443 CMU_PERH_ADC0 = (1U << 4) | (1U << 28),
444 CMU_PERH_ADC1 = (1U << 5) | (1U << 28),
445 CMU_PERH_ACMP0 = (1U << 6) | (1U << 28),
446 CMU_PERH_ACMP1 = (1U << 7) | (1U << 28),
447 CMU_PERH_OPAMP = (1U << 8) | (1U << 28),
448 CMU_PERH_DAC0 = (1U << 9) | (1U << 28),
449 CMU_PERH_ACMP2 = (1U << 11) | (1U << 28),
450 CMU_PERH_WWDT = (1U << 12) | (1U << 28),
451 CMU_PERH_LCD = (1U << 13) | (1U << 28),
452 CMU_PERH_IWDT = (1U << 14) | (1U << 28),
453 CMU_PERH_RTC = (1U << 15) | (1U << 28),
454 CMU_PERH_TSENSE = (1U << 16) | (1U << 28),
455 CMU_PERH_BKPC = (1U << 17) | (1U << 28),
456 CMU_PERH_DBGC = (1U << 19) | (1U << 28),
457 CMU_PERH_ALL = (0x7FFFFFFFU),
458 } cmu_perh_t;
459
463 typedef enum {
464 CMU_LOSC_STOP = 0x0U,
465 CMU_HOSC_STOP = 0x1U,
466 CMU_PLL1_UNLOCK = 0x2U,
467 CMU_LOSC_START = 0x3U,
468 CMU_HOSC_START = 0x4U,
469 } cmu_security_t;
470
474 typedef enum {
475 CMU_CLOCK_STATE_HOSCACT = (1U << 0),
476 CMU_CLOCK_STATE_LOSCACT = (1U << 1),
477 CMU_CLOCK_STATE_HRCACT = (1U << 2),
478 CMU_CLOCK_STATE_LRCACT = (1U << 3),
479 CMU_CLOCK_STATE_ULRCACT = (1U << 4),
480 CMU_CLOCK_STATE_PLL1ACT = (1U << 8),
481 CMU_CLOCK_STATE_PLL2ACT = (1U << 9),
482 CMU_CLOCK_STATE_HOSCRDY = (1U << 16),
483 CMU_CLOCK_STATE_LOSCRDY = (1U << 17),
484 CMU_CLOCK_STATE_HRCRDY = (1U << 18),
485 CMU_CLOCK_STATE_LRCRDY = (1U << 19),
486 CMU_CLOCK_STATE_PLL1RDY = (1U << 24),
487 CMU_CLOCK_STATE_PLL2RDY = (1U << 25),
488 } cmu_clock_state_t;
489
493 typedef enum {
494 CMU_STOP1_CLOCK_LRC = 0x0U,
495 CMU_STOP1_CLOCK_HRC_24M = 0x1U,
496 CMU_STOP1_CLOCK_HRC_2M = 0x2U,
497 CMU_STOP1_CLOCK_HRC_1M = 0x3U,
498 CMU_STOP1_CLOCK_HOSC = 0x4U,
499 CMU_STOP1_CLOCK_HOSC_1M = 0x5U,
500 CMU_STOP1_CLOCK_HOSCM = 0x6U,
501 } cmu_stop1_clock_t;
502
511 #define IS_CMU_CLOCK(x) (((x) == CMU_CLOCK_HRC) || \
512 ((x) == CMU_CLOCK_LRC) || \
513 ((x) == CMU_CLOCK_LOSC) || \
514 ((x) == CMU_CLOCK_PLL1) || \
515 ((x) == CMU_CLOCK_HOSC))
516 #if defined(ES32F36xx) || defined(ES32F39xx)
517 #define IS_CMU_PLL1_OUTPUT(x) (((x) == CMU_PLL1_OUTPUT_36M) || \
518 ((x) == CMU_PLL1_OUTPUT_48M) || \
519 ((x) == CMU_PLL1_OUTPUT_72M) || \
520 ((x) == CMU_PLL1_OUTPUT_96M))
521 #endif
522 #ifdef ES32F336x
523 #define IS_CMU_PLL1_OUTPUT(x) (((x) == CMU_PLL1_OUTPUT_36M) || \
524 ((x) == CMU_PLL1_OUTPUT_48M))
525 #endif
526 #define IS_CMU_PLL1_INPUT(x) (((x) == CMU_PLL1_INPUT_HRC_6) || \
527 ((x) == CMU_PLL1_INPUT_PLL2) || \
528 ((x) == CMU_PLL1_INPUT_HOSC) || \
529 ((x) == CMU_PLL1_INPUT_HOSC_2) || \
530 ((x) == CMU_PLL1_INPUT_HOSC_3) || \
531 ((x) == CMU_PLL1_INPUT_HOSC_4) || \
532 ((x) == CMU_PLL1_INPUT_HOSC_5) || \
533 ((x) == CMU_PLL1_INPUT_HOSC_6))
534 #define IS_CMU_HOSC_RANGE(x) (((x) == CMU_HOSC_2M) || \
535 ((x) == CMU_HOSC_4M) || \
536 ((x) == CMU_HOSC_8M) || \
537 ((x) == CMU_HOSC_16M) || \
538 ((x) == CMU_HOSC_24M))
539 #define IS_CMU_DIV(x) (((x) == CMU_DIV_1) || \
540 ((x) == CMU_DIV_2) || \
541 ((x) == CMU_DIV_4) || \
542 ((x) == CMU_DIV_8) || \
543 ((x) == CMU_DIV_16) || \
544 ((x) == CMU_DIV_32) || \
545 ((x) == CMU_DIV_64) || \
546 ((x) == CMU_DIV_128) || \
547 ((x) == CMU_DIV_256) || \
548 ((x) == CMU_DIV_512) || \
549 ((x) == CMU_DIV_1024) || \
550 ((x) == CMU_DIV_2048) || \
551 ((x) == CMU_DIV_4096))
552 #define IS_CMU_BUS(x) (((x) == CMU_HCLK_1) || \
553 ((x) == CMU_HCLK_2) || \
554 ((x) == CMU_SYS) || \
555 ((x) == CMU_PCLK_1) || \
556 ((x) == CMU_PCLK_2))
557 #define IS_CMU_OUTPUT_HIGH_SEL(x) (((x) == CMU_OUTPUT_HIGH_SEL_HOSC) || \
558 ((x) == CMU_OUTPUT_HIGH_SEL_LOSC) || \
559 ((x) == CMU_OUTPUT_HIGH_SEL_HRC) || \
560 ((x) == CMU_OUTPUT_HIGH_SEL_LRC) || \
561 ((x) == CMU_OUTPUT_HIGH_SEL_HOSM) || \
562 ((x) == CMU_OUTPUT_HIGH_SEL_PLL1) || \
563 ((x) == CMU_OUTPUT_HIGH_SEL_PLL2) || \
564 ((x) == CMU_OUTPUT_HIGH_SEL_SYSCLK))
565 #define IS_CMU_OUTPUT_HIGH_DIV(x) (((x) == CMU_OUTPUT_DIV_1) || \
566 ((x) == CMU_OUTPUT_DIV_2) || \
567 ((x) == CMU_OUTPUT_DIV_4) || \
568 ((x) == CMU_OUTPUT_DIV_8) || \
569 ((x) == CMU_OUTPUT_DIV_16) || \
570 ((x) == CMU_OUTPUT_DIV_32) || \
571 ((x) == CMU_OUTPUT_DIV_64) || \
572 ((x) == CMU_OUTPUT_DIV_128))
573 #define IS_CMU_OUTPUT_LOW_SEL(x) (((x) == CMU_OUTPUT_LOW_SEL_LOSC) || \
574 ((x) == CMU_OUTPUT_LOW_SEL_LRC ) || \
575 ((x) == CMU_OUTPUT_LOW_SEL_LOSM) || \
576 ((x) == CMU_OUTPUT_LOW_SEL_BUZZ) || \
577 ((x) == CMU_OUTPUT_LOW_SEL_ULRC))
578 #define IS_CMU_SAFE_CLOCK_TYPE(x) (((x) == CMU_SAFE_CLK_HOSC) || \
579 ((x) == CMU_SAFE_CLK_LOSC) || \
580 ((x) == CMU_SAFE_CLK_PLL))
581 #define IS_CMU_BUZZ_DIV(x) (((x) == CMU_BUZZ_DIV_2) || \
582 ((x) == CMU_BUZZ_DIV_4) || \
583 ((x) == CMU_BUZZ_DIV_8) || \
584 ((x) == CMU_BUZZ_DIV_16) || \
585 ((x) == CMU_BUZZ_DIV_32) || \
586 ((x) == CMU_BUZZ_DIV_64) || \
587 ((x) == CMU_BUZZ_DIV_128) || \
588 ((x) == CMU_BUZZ_DIV_256))
589 #define IS_CMU_LP_PERH_CLOCK_SEL(x) (((x) == CMU_LP_PERH_CLOCK_SEL_PCLK2) || \
590 ((x) == CMU_LP_PERH_CLOCK_SEL_PLL1) || \
591 ((x) == CMU_LP_PERH_CLOCK_SEL_PLL2) || \
592 ((x) == CMU_LP_PERH_CLOCK_SEL_HRC) || \
593 ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC) || \
594 ((x) == CMU_LP_PERH_CLOCK_SEL_LRC) || \
595 ((x) == CMU_LP_PERH_CLOCK_SEL_LOSC) || \
596 ((x) == CMU_LP_PERH_CLOCK_SEL_ULRC) || \
597 ((x) == CMU_LP_PERH_CLOCK_SEL_HRC_1M) || \
598 ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC_1M) || \
599 ((x) == CMU_LP_PERH_CLOCK_SEL_LOSM) || \
600 ((x) == CMU_LP_PERH_CLOCK_SEL_HOSM))
601 #define IS_CMU_LCD_CLOCK_SEL(x) (((x) == CMU_LCD_SEL_LOSM) || \
602 ((x) == CMU_LCD_SEL_LOSC) || \
603 ((x) == CMU_LCD_SEL_LRC) || \
604 ((x) == CMU_LCD_SEL_ULRC) || \
605 ((x) == CMU_LCD_SEL_HRC_1M) || \
606 ((x) == CMU_LCD_SEL_HOSC_1M))
607 #define IS_CMU_QSPI_CLOCK_SEL(x) (((x) == CMU_QSPI_CLOCK_SEL_PCLK1) || \
608 ((x) == CMU_QSPI_CLOCK_SEL_HCLK2) || \
609 ((x) == CMU_QSPI_CLOCK_SEL_HRC) || \
610 ((x) == CMU_QSPI_CLOCK_SEL_HOSC) || \
611 ((x) == CMU_QSPI_CLOCK_SEL_PLL1) || \
612 ((x) == CMU_QSPI_CLOCK_SEL_HOSM))
613 #define IS_CMU_USB_CLOCK_SEL(x) (((x) == CMU_USB_CLOCK_SEL_HOSC) || \
614 ((x) == CMU_USB_CLOCK_SEL_HRC) || \
615 ((x) == CMU_USB_CLOCK_SEL_PCLK1) || \
616 ((x) == CMU_USB_CLOCK_SEL_PLL1) || \
617 ((x) == CMU_USB_CLOCK_SEL_HOSM))
618 #define IS_CMU_USB_DIV(x) (((x) == CMU_USB_DIV_1) || \
619 ((x) == CMU_USB_DIV_2) || \
620 ((x) == CMU_USB_DIV_4) || \
621 ((x) == CMU_USB_DIV_8) || \
622 ((x) == CMU_USB_DIV_16) || \
623 ((x) == CMU_USB_DIV_32) || \
624 ((x) == CMU_USB_DIV_64) || \
625 ((x) == CMU_USB_DIV_128) || \
626 ((x) == CMU_USB_DIV_256) || \
627 ((x) == CMU_USB_DIV_512) || \
628 ((x) == CMU_USB_DIV_1024) || \
629 ((x) == CMU_USB_DIV_2048) || \
630 ((x) == CMU_USB_DIV_4096))
631 #define IS_CMU_PERH(x) (((x) == CMU_PERH_GPIO) || \
632 ((x) == CMU_PERH_CRC) || \
633 ((x) == CMU_PERH_CALC) || \
634 ((x) == CMU_PERH_CRYPT) || \
635 ((x) == CMU_PERH_TRNG) || \
636 ((x) == CMU_PERH_PIS) || \
637 ((x) == CMU_PERH_EBI) || \
638 ((x) == CMU_PERH_QSPI_H) || \
639 ((x) == CMU_PERH_DMA) || \
640 ((x) == CMU_PERH_USB) || \
641 ((x) == CMU_PERH_ECC) || \
642 ((x) == CMU_PERH_TIMER0) || \
643 ((x) == CMU_PERH_TIMER1) || \
644 ((x) == CMU_PERH_TIMER2) || \
645 ((x) == CMU_PERH_TIMER3) || \
646 ((x) == CMU_PERH_TIMER4) || \
647 ((x) == CMU_PERH_TIMER5) || \
648 ((x) == CMU_PERH_TIMER6) || \
649 ((x) == CMU_PERH_TIMER7) || \
650 ((x) == CMU_PERH_UART0) || \
651 ((x) == CMU_PERH_UART1) || \
652 ((x) == CMU_PERH_UART2) || \
653 ((x) == CMU_PERH_UART3) || \
654 ((x) == CMU_PERH_UART4) || \
655 ((x) == CMU_PERH_UART5) || \
656 ((x) == CMU_PERH_SPI0) || \
657 ((x) == CMU_PERH_SPI1) || \
658 ((x) == CMU_PERH_SPI2) || \
659 ((x) == CMU_PERH_I2C0) || \
660 ((x) == CMU_PERH_I2C1) || \
661 ((x) == CMU_PERH_CAN) || \
662 ((x) == CMU_PERH_QSPI_P) || \
663 ((x) == CMU_PERH_LPTIM0) || \
664 ((x) == CMU_PERH_LPUART0) || \
665 ((x) == CMU_PERH_ADC0) || \
666 ((x) == CMU_PERH_ADC1) || \
667 ((x) == CMU_PERH_ACMP0) || \
668 ((x) == CMU_PERH_ACMP1) || \
669 ((x) == CMU_PERH_OPAMP) || \
670 ((x) == CMU_PERH_DAC0) || \
671 ((x) == CMU_PERH_ACMP2) || \
672 ((x) == CMU_PERH_WWDT) || \
673 ((x) == CMU_PERH_LCD) || \
674 ((x) == CMU_PERH_IWDT) || \
675 ((x) == CMU_PERH_RTC) || \
676 ((x) == CMU_PERH_TSENSE) || \
677 ((x) == CMU_PERH_BKPC) || \
678 ((x) == CMU_PERH_DBGC) || \
679 ((x) == CMU_PERH_ALL))
680 #define IS_CMU_CLOCK_STATE(x) (((x) == CMU_CLOCK_STATE_HOSCACT) || \
681 ((x) == CMU_CLOCK_STATE_LOSCACT) || \
682 ((x) == CMU_CLOCK_STATE_HRCACT) || \
683 ((x) == CMU_CLOCK_STATE_LRCACT) || \
684 ((x) == CMU_CLOCK_STATE_ULRCACT) || \
685 ((x) == CMU_CLOCK_STATE_PLL1ACT) || \
686 ((x) == CMU_CLOCK_STATE_PLL2ACT) || \
687 ((x) == CMU_CLOCK_STATE_HOSCRDY) || \
688 ((x) == CMU_CLOCK_STATE_LOSCRDY) || \
689 ((x) == CMU_CLOCK_STATE_HRCRDY) || \
690 ((x) == CMU_CLOCK_STATE_LRCRDY) || \
691 ((x) == CMU_CLOCK_STATE_PLL1RDY) || \
692 ((x) == CMU_CLOCK_STATE_PLL2RDY))
693 #define IS_CMU_STOP1_CLOCK(x) (((x) == CMU_STOP1_CLOCK_LRC) || \
694 ((x) == CMU_STOP1_CLOCK_HRC_24M) || \
695 ((x) == CMU_STOP1_CLOCK_HRC_2M) || \
696 ((x) == CMU_STOP1_CLOCK_HRC_1M) || \
697 ((x) == CMU_STOP1_CLOCK_HOSC) || \
698 ((x) == CMU_STOP1_CLOCK_HOSC_1M) || \
699 ((x) == CMU_STOP1_CLOCK_HOSCM))
700
710 /* System clock configure */
711 ald_status_t ald_cmu_clock_config_default(void);
712 ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock);
713 void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output);
714 uint32_t ald_cmu_get_clock(void);
722 /* BUS division control */
723 void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div);
724 uint32_t ald_cmu_get_hclk1_clock(void);
725 uint32_t ald_cmu_get_hclk2_clock(void);
726 uint32_t ald_cmu_get_sys_clock(void);
727 uint32_t ald_cmu_get_pclk1_clock(void);
728 uint32_t ald_cmu_get_pclk2_clock(void);
736 /* Clock safe configure */
737 void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status);
738 void ald_cmu_losc_safe_config(type_func_t status);
739 void ald_cmu_pll_safe_config(type_func_t status);
740 uint32_t ald_cmu_current_clock_source_get(cmu_clock_safe_type_t type);
741 flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr);
742 void ald_cmu_irq_handler(void);
743 void ald_cmu_irq_cbk(cmu_security_t se);
751 /* Clock output configure */
752 void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel,
753 cmu_output_high_div_t div, type_func_t status);
754 void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status);
762 /* Peripheral Clock configure */
763 void ald_cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status);
764 void ald_cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock);
765 void ald_cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock);
766 void ald_cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock);
767 void ald_cmu_qspi_clock_select(cmu_qspi_clock_sel_t clock);
768 void ald_cmu_usb_clock_config(cmu_usb_clock_sel_t clock, cmu_usb_div_t div);
769 void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status);
770 void ald_cmu_stop1_clock_sel(cmu_stop1_clock_t clock);
785 #ifdef __cplusplus
786 }
787 #endif
788
789 #endif /* __ALD_CMU_H__ */
ald_cmu_hosc_safe_config
void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status)
Enable/Disable outer high crystal safe mode.
Definition: ald_cmu.c:673
ald_cmu_get_clock
uint32_t ald_cmu_get_clock(void)
Gets current system clock.
Definition: ald_cmu.c:506
CMU_PERH_UART4
Definition: ald_cmu.h:432
CMU_LCD_SEL_LOSM
Definition: ald_cmu.h:331
CMU_PERH_EBI
Definition: ald_cmu.h:415
ald_cmu_losc_safe_config
void ald_cmu_losc_safe_config(type_func_t status)
Enable/Disable outer low crystal safe mode.
Definition: ald_cmu.c:705
CMU_BUZZ_DIV_2
Definition: ald_cmu.h:299
CMU_SAFE_CLK_PLL
Definition: ald_cmu.h:223
CMU_LOSC_STOP
Definition: ald_cmu.h:464
ald_cmu_stop1_clock_sel
void ald_cmu_stop1_clock_sel(cmu_stop1_clock_t clock)
Select stop1 clock.
Definition: ald_cmu.c:1145
ald_cmu_pll_safe_config
void ald_cmu_pll_safe_config(type_func_t status)
Enable/Disable PLL1 safe mode.
Definition: ald_cmu.c:734
CMU_OUTPUT_HIGH_SEL_HOSC
Definition: ald_cmu.h:260
ald_cmu_get_clock_state
flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr)
Get clock state.
Definition: ald_cmu.c:783
CMU_CLOCK_STATE_LRCRDY
Definition: ald_cmu.h:485
CMU_DIV_2
Definition: ald_cmu.h:231
ald_cmu_irq_handler
void ald_cmu_irq_handler(void)
CMU module interrupt handler.
Definition: ald_cmu.c:174
CMU_PERH_DBGC
Definition: ald_cmu.h:456
CMU_USB_CLOCK_SEL_HOSM
Definition: ald_cmu.h:359
CMU_PLL1_OUTPUT_36M
Definition: ald_cmu.h:184
ald_cmu_get_hclk1_clock
uint32_t ald_cmu_get_hclk1_clock(void)
Get AHB1 clock.
Definition: ald_cmu.c:592
CMU_PERH_TIMER5
Definition: ald_cmu.h:425
CMU_PERH_LPUART0
Definition: ald_cmu.h:442
CMU_PERH_PIS
Definition: ald_cmu.h:414
CMU_PERH_TIMER4
Definition: ald_cmu.h:424
CMU_BUZZ_DIV_256
Definition: ald_cmu.h:306
ald_cmu_qspi_clock_select
void ald_cmu_qspi_clock_select(cmu_qspi_clock_sel_t clock)
Select QSPI clock source.
Definition: ald_cmu.c:1029
cmu_output_high_sel_t
cmu_output_high_sel_t
Output high clock select.
Definition: ald_cmu.h:259
CMU_USB_DIV_32
Definition: ald_cmu.h:371
CMU_DIV_256
Definition: ald_cmu.h:238
CMU_PLL1_INPUT_HOSC_2
Definition: ald_cmu.h:199
CMU_QSPI_CLOCK_SEL_HRC
Definition: ald_cmu.h:345
cmu_pll1_output_t
cmu_pll1_output_t
PLL1 output clock.
Definition: ald_cmu.h:183
CMU_PERH_ECC
Definition: ald_cmu.h:419
ald_cmu_lpuart0_clock_select
void ald_cmu_lpuart0_clock_select(cmu_lp_perh_clock_sel_t clock)
Select lpuart0 clock source.
Definition: ald_cmu.c:991
CMU_CLOCK_HOSC
Definition: ald_cmu.h:177
CMU_CLOCK_HRC
Definition: ald_cmu.h:173
CMU_CLOCK_LOSC
Definition: ald_cmu.h:175
type_func_t
type_func_t
Definition: type.h:47
CMU_STOP1_CLOCK_HRC_1M
Definition: ald_cmu.h:497
CMU_OUTPUT_HIGH_SEL_PLL1
Definition: ald_cmu.h:265
can_handle_s::perh
CAN_TypeDef * perh
Definition: ald_can.h:294
cmu_hosc_range_t
cmu_hosc_range_t
HOSC range.
Definition: ald_cmu.h:209
CMU_PERH_CAN
Definition: ald_cmu.h:439
ald_cmu_get_hclk2_clock
uint32_t ald_cmu_get_hclk2_clock(void)
Get AHB2 clock.
Definition: ald_cmu.c:604
CMU_HOSC_START
Definition: ald_cmu.h:468
CMU_QSPI_CLOCK_SEL_HOSM
Definition: ald_cmu.h:348
CMU_USB_DIV_16
Definition: ald_cmu.h:370
CMU_PERH_ACMP0
Definition: ald_cmu.h:445
CMU_PERH_IWDT
Definition: ald_cmu.h:452
CMU_LP_PERH_CLOCK_SEL_HRC_1M
Definition: ald_cmu.h:321
CMU_PLL1_UNLOCK
Definition: ald_cmu.h:466
CMU_SAFE_CLK_LOSC
Definition: ald_cmu.h:222
ald_cmu_output_low_clock_config
void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status)
Configure the low-speed clock output.
Definition: ald_cmu.c:878
CMU_USB_DIV_1024
Definition: ald_cmu.h:376
CMU_QSPI_CLOCK_SEL_HOSC
Definition: ald_cmu.h:346
CMU_LP_PERH_CLOCK_SEL_LOSC
Definition: ald_cmu.h:319
CMU_DIV_8
Definition: ald_cmu.h:233
CMU_LCD_SEL_HOSC_1M
Definition: ald_cmu.h:336
ald_cmu_get_sys_clock
uint32_t ald_cmu_get_sys_clock(void)
Get SYS clock.
Definition: ald_cmu.c:616
CMU_DIV_4096
Definition: ald_cmu.h:242
ald_cmu_clock_config_default
ald_status_t ald_cmu_clock_config_default(void)
Configure system clock using default. Select CMU_CLOCK_HRC(24MHz) as system clock and enable CMU_CLOC...
Definition: ald_cmu.c:263
cmu_clock_t
cmu_clock_t
CMU state structure definition.
Definition: ald_cmu.h:172
cmu_usb_div_t
cmu_usb_div_t
USB clock division.
Definition: ald_cmu.h:365
CMU_HOSC_4M
Definition: ald_cmu.h:211
CMU_OUTPUT_DIV_16
Definition: ald_cmu.h:278
CMU_PERH_TIMER6
Definition: ald_cmu.h:426
CMU_CLOCK_STATE_HRCACT
Definition: ald_cmu.h:477
cmu_usb_clock_sel_t
cmu_usb_clock_sel_t
USB clock select.
Definition: ald_cmu.h:354
CMU_PERH_TIMER3
Definition: ald_cmu.h:423
cmu_bus_t
cmu_bus_t
Bus type.
Definition: ald_cmu.h:248
CMU_PERH_TIMER0
Definition: ald_cmu.h:420
CMU_HOSC_8M
Definition: ald_cmu.h:212
CMU_OUTPUT_DIV_32
Definition: ald_cmu.h:279
ald_cmu_buzz_config
void ald_cmu_buzz_config(cmu_buzz_div_t div, uint16_t dat, type_func_t status)
Configure buzz clock. freq = sysclk / (2^(div + 1) * (dat + 1))
Definition: ald_cmu.c:926
CMU_USB_DIV_1
Definition: ald_cmu.h:366
CMU_QSPI_CLOCK_SEL_HCLK2
Definition: ald_cmu.h:344
cmu_security_t
cmu_security_t
CMU interrupt type.
Definition: ald_cmu.h:463
CMU_LCD_SEL_LRC
Definition: ald_cmu.h:333
CMU_PERH_ADC0
Definition: ald_cmu.h:443
CMU_USB_CLOCK_SEL_HOSC
Definition: ald_cmu.h:355
CMU_STOP1_CLOCK_LRC
Definition: ald_cmu.h:494
cmu_output_low_sel_t
cmu_output_low_sel_t
Output low clock select.
Definition: ald_cmu.h:287
cmu_output_high_div_t
cmu_output_high_div_t
Output frequency division.
Definition: ald_cmu.h:273
utils.h
This file contains the Utilities functions/types for the driver.
CMU_STOP1_CLOCK_HOSCM
Definition: ald_cmu.h:500
CMU_DIV_1
Definition: ald_cmu.h:230
CMU_LCD_SEL_ULRC
Definition: ald_cmu.h:334
CMU_QSPI_CLOCK_SEL_PCLK1
Definition: ald_cmu.h:343
CMU_USB_CLOCK_SEL_PCLK1
Definition: ald_cmu.h:357
CMU_CLOCK_PLL1
Definition: ald_cmu.h:176
CMU_LP_PERH_CLOCK_SEL_PLL1
Definition: ald_cmu.h:314
CMU_OUTPUT_LOW_SEL_LOSM
Definition: ald_cmu.h:290
CMU_USB_DIV_2048
Definition: ald_cmu.h:377
CMU_CLOCK_STATE_PLL1ACT
Definition: ald_cmu.h:480
CMU_LP_PERH_CLOCK_SEL_HOSC_1M
Definition: ald_cmu.h:322
CMU_DIV_16
Definition: ald_cmu.h:234
CMU_CLOCK_STATE_LOSCACT
Definition: ald_cmu.h:476
CMU_BUZZ_DIV_32
Definition: ald_cmu.h:303
CMU_PERH_CALC
Definition: ald_cmu.h:411
CMU_DIV_512
Definition: ald_cmu.h:239
CMU_USB_DIV_512
Definition: ald_cmu.h:375
cmu_clock_state_t
cmu_clock_state_t
CMU clock state type.
Definition: ald_cmu.h:474
ald_cmu_current_clock_source_get
uint32_t ald_cmu_current_clock_source_get(cmu_clock_safe_type_t type)
Get current clock source.
Definition: ald_cmu.c:766
CMU_PERH_UART5
Definition: ald_cmu.h:433
CMU_PLL1_INPUT_HRC_6
Definition: ald_cmu.h:196
CMU_STOP1_CLOCK_HOSC
Definition: ald_cmu.h:498
CMU_LCD_SEL_LOSC
Definition: ald_cmu.h:332
CMU_PERH_QSPI_H
Definition: ald_cmu.h:416
ald_cmu_lptim0_clock_select
void ald_cmu_lptim0_clock_select(cmu_lp_perh_clock_sel_t clock)
Select lptim0 clock source.
Definition: ald_cmu.c:963
CMU_PERH_UART0
Definition: ald_cmu.h:428
CMU_PERH_RTC
Definition: ald_cmu.h:453
CMU_OUTPUT_DIV_64
Definition: ald_cmu.h:280
CMU_PLL1_INPUT_PLL2
Definition: ald_cmu.h:197
CMU_USB_DIV_64
Definition: ald_cmu.h:372
CMU_CLOCK_LRC
Definition: ald_cmu.h:174
CMU_PERH_TIMER7
Definition: ald_cmu.h:427
CMU_LP_PERH_CLOCK_SEL_ULRC
Definition: ald_cmu.h:320
CMU_OUTPUT_DIV_8
Definition: ald_cmu.h:277
CMU_PERH_ALL
Definition: ald_cmu.h:457
ald_cmu_get_pclk2_clock
uint32_t ald_cmu_get_pclk2_clock(void)
Get APB2 clock.
Definition: ald_cmu.c:639
CMU_STOP1_CLOCK_HRC_2M
Definition: ald_cmu.h:496
CMU_HOSC_2M
Definition: ald_cmu.h:210
CMU_OUTPUT_LOW_SEL_LOSC
Definition: ald_cmu.h:288
CMU_OUTPUT_DIV_2
Definition: ald_cmu.h:275
CMU_OUTPUT_LOW_SEL_ULRC
Definition: ald_cmu.h:292
CMU_HCLK_1
Definition: ald_cmu.h:249
CMU_PERH_UART3
Definition: ald_cmu.h:431
CMU_DIV_2048
Definition: ald_cmu.h:241
CMU_PLL1_INPUT_HOSC_6
Definition: ald_cmu.h:203
CMU_PERH_ACMP1
Definition: ald_cmu.h:446
CMU_HOSC_24M
Definition: ald_cmu.h:214
CMU_SAFE_CLK_HOSC
Definition: ald_cmu.h:221
CMU_PERH_BKPC
Definition: ald_cmu.h:455
CMU_PERH_UART1
Definition: ald_cmu.h:429
CMU_LP_PERH_CLOCK_SEL_PCLK2
Definition: ald_cmu.h:313
CMU_OUTPUT_HIGH_SEL_HOSM
Definition: ald_cmu.h:264
CMU_DIV_1024
Definition: ald_cmu.h:240
ald_syscfg.h
SYSCFG module driver.
CMU_BUZZ_DIV_8
Definition: ald_cmu.h:301
CMU_DIV_128
Definition: ald_cmu.h:237
CMU_OUTPUT_DIV_4
Definition: ald_cmu.h:276
CMU_PERH_TSENSE
Definition: ald_cmu.h:454
CMU_OUTPUT_HIGH_SEL_SYSCLK
Definition: ald_cmu.h:267
CMU_PERH_GPIO
Definition: ald_cmu.h:409
CMU_STOP1_CLOCK_HOSC_1M
Definition: ald_cmu.h:499
CMU_USB_CLOCK_SEL_PLL1
Definition: ald_cmu.h:358
CMU_PERH_LPTIM0
Definition: ald_cmu.h:441
CMU_LP_PERH_CLOCK_SEL_PLL2
Definition: ald_cmu.h:315
CMU_CLOCK_STATE_HRCRDY
Definition: ald_cmu.h:484
CMU_HCLK_2
Definition: ald_cmu.h:250
CMU_CLOCK_STATE_PLL1RDY
Definition: ald_cmu.h:486
CMU_CLOCK_STATE_ULRCACT
Definition: ald_cmu.h:479
CMU_OUTPUT_LOW_SEL_BUZZ
Definition: ald_cmu.h:291
ald_cmu_pll1_config
void ald_cmu_pll1_config(cmu_pll1_input_t input, cmu_pll1_output_t output)
Configure PLL1 using specified parameters.
Definition: ald_cmu.c:462
CMU_PERH_SPI1
Definition: ald_cmu.h:435
CMU_OUTPUT_HIGH_SEL_HRC
Definition: ald_cmu.h:262
CMU_PERH_I2C1
Definition: ald_cmu.h:438
CMU_OUTPUT_HIGH_SEL_LOSC
Definition: ald_cmu.h:261
ald_cmu_get_pclk1_clock
uint32_t ald_cmu_get_pclk1_clock(void)
Get APB1 clock.
Definition: ald_cmu.c:627
CMU_OUTPUT_DIV_1
Definition: ald_cmu.h:274
cmu_pll1_input_t
cmu_pll1_input_t
PLL1 referance clock.
Definition: ald_cmu.h:195
CMU_PERH_SPI0
Definition: ald_cmu.h:434
CMU_PERH_DAC0
Definition: ald_cmu.h:448
ald_cmu_div_config
void ald_cmu_div_config(cmu_bus_t bus, cmu_div_t div)
Configure the bus division.
Definition: ald_cmu.c:543
CMU_OUTPUT_DIV_128
Definition: ald_cmu.h:281
CMU_PCLK_1
Definition: ald_cmu.h:252
CMU_DIV_64
Definition: ald_cmu.h:236
CMU_PERH_OPAMP
Definition: ald_cmu.h:447
CMU_PERH_USB
Definition: ald_cmu.h:418
CMU_PERH_LCD
Definition: ald_cmu.h:451
CMU_BUZZ_DIV_4
Definition: ald_cmu.h:300
CMU_PLL1_INPUT_HOSC_4
Definition: ald_cmu.h:201
CMU_HOSC_STOP
Definition: ald_cmu.h:465
CMU_PLL1_INPUT_HOSC_5
Definition: ald_cmu.h:202
CMU_USB_DIV_2
Definition: ald_cmu.h:367
cmu_div_t
cmu_div_t
Frequency division select bit.
Definition: ald_cmu.h:229
CMU_USB_DIV_8
Definition: ald_cmu.h:369
CMU_QSPI_CLOCK_SEL_PLL1
Definition: ald_cmu.h:347
CMU_PERH_WWDT
Definition: ald_cmu.h:450
CMU_PERH_SPI2
Definition: ald_cmu.h:436
CMU_OUTPUT_HIGH_SEL_LRC
Definition: ald_cmu.h:263
CMU_USB_DIV_256
Definition: ald_cmu.h:374
CMU_PERH_ADC1
Definition: ald_cmu.h:444
CMU_PERH_CRYPT
Definition: ald_cmu.h:412
CMU_PERH_UART2
Definition: ald_cmu.h:430
CMU_BUZZ_DIV_64
Definition: ald_cmu.h:304
CMU_OUTPUT_LOW_SEL_LRC
Definition: ald_cmu.h:289
CMU_PERH_TRNG
Definition: ald_cmu.h:413
CMU_LOSC_START
Definition: ald_cmu.h:467
CMU_CLOCK_STATE_LRCACT
Definition: ald_cmu.h:478
CMU_PCLK_2
Definition: ald_cmu.h:253
CMU_LP_PERH_CLOCK_SEL_LOSM
Definition: ald_cmu.h:323
cmu_stop1_clock_t
cmu_stop1_clock_t
Stop1 clock select type.
Definition: ald_cmu.h:493
CMU_PERH_TIMER1
Definition: ald_cmu.h:421
CMU_PLL1_INPUT_HOSC
Definition: ald_cmu.h:198
CMU_HOSC_16M
Definition: ald_cmu.h:213
CMU_PERH_DMA
Definition: ald_cmu.h:417
ald_cmu_output_high_clock_config
void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel, cmu_output_high_div_t div, type_func_t status)
Configure the high-speed clock output.
Definition: ald_cmu.c:845
cmu_lcd_clock_sel_t
cmu_lcd_clock_sel_t
LCD clock select.
Definition: ald_cmu.h:330
flag_status_t
flag_status_t
Definition: type.h:37
CMU_PERH_QSPI_P
Definition: ald_cmu.h:440
CMU_BUZZ_DIV_16
Definition: ald_cmu.h:302
CMU_LCD_SEL_HRC_1M
Definition: ald_cmu.h:335
CMU_LP_PERH_CLOCK_SEL_HOSM
Definition: ald_cmu.h:324
CMU_PERH_CRC
Definition: ald_cmu.h:410
CMU_SYS
Definition: ald_cmu.h:251
CMU_CLOCK_STATE_HOSCACT
Definition: ald_cmu.h:475
CMU_CLOCK_STATE_LOSCRDY
Definition: ald_cmu.h:483
ald_cmu_clock_config
ald_status_t ald_cmu_clock_config(cmu_clock_t clk, uint32_t clock)
Configure system clock using specified parameters.
Definition: ald_cmu.c:307
CMU_PERH_I2C0
Definition: ald_cmu.h:437
CMU_OUTPUT_HIGH_SEL_PLL2
Definition: ald_cmu.h:266
cmu_lp_perh_clock_sel_t
cmu_lp_perh_clock_sel_t
Low power peripheral clock select.
Definition: ald_cmu.h:312
CMU_DIV_4
Definition: ald_cmu.h:232
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
cmu_perh_t
cmu_perh_t
Peripheral clock enable/disable.
Definition: ald_cmu.h:408
ald_cmu_irq_cbk
__weak void ald_cmu_irq_cbk(cmu_security_t se)
Interrupt callback function.
Definition: ald_cmu.c:799
CMU_LP_PERH_CLOCK_SEL_HRC
Definition: ald_cmu.h:316
CMU_LP_PERH_CLOCK_SEL_LRC
Definition: ald_cmu.h:318
CMU_PLL1_INPUT_HOSC_3
Definition: ald_cmu.h:200
CMU_CLOCK_STATE_PLL2RDY
Definition: ald_cmu.h:487
CMU_STOP1_CLOCK_HRC_24M
Definition: ald_cmu.h:495
CMU_USB_DIV_4096
Definition: ald_cmu.h:378
cmu_clock_safe_type_t
cmu_clock_safe_type_t
Safe clock source type.
Definition: ald_cmu.h:220
CMU_USB_CLOCK_SEL_HRC
Definition: ald_cmu.h:356
CMU_CLOCK_STATE_PLL2ACT
Definition: ald_cmu.h:481
CMU_USB_DIV_128
Definition: ald_cmu.h:373
CMU_USB_DIV_4
Definition: ald_cmu.h:368
ald_cmu_lcd_clock_select
void ald_cmu_lcd_clock_select(cmu_lcd_clock_sel_t clock)
Select lcd clock source.
Definition: ald_cmu.c:1013
CMU_LP_PERH_CLOCK_SEL_HOSC
Definition: ald_cmu.h:317
CMU_PLL1_OUTPUT_48M
Definition: ald_cmu.h:185
ald_cmu_perh_clock_config
void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status)
Enable/Disable peripheral clock.
Definition: ald_cmu.c:1071
CMU_PERH_ACMP2
Definition: ald_cmu.h:449
CMU_CLOCK_STATE_HOSCRDY
Definition: ald_cmu.h:482
CMU_PERH_TIMER2
Definition: ald_cmu.h:422
cmu_qspi_clock_sel_t
cmu_qspi_clock_sel_t
QSPI clock select.
Definition: ald_cmu.h:342
CMU_BUZZ_DIV_128
Definition: ald_cmu.h:305
ald_cmu_usb_clock_config
void ald_cmu_usb_clock_config(cmu_usb_clock_sel_t clock, cmu_usb_div_t div)
Configure USB clock source.
Definition: ald_cmu.c:1046
CMU_DIV_32
Definition: ald_cmu.h:235
cmu_buzz_div_t
cmu_buzz_div_t
BUZZ frequency division.
Definition: ald_cmu.h:298


ALD User Manual: D:/svn/src/ald_conf.h Source File

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  • svn
  • src
ald_conf.h
Go to the documentation of this file.
1
18 #ifndef __ALD_CONF_H__
19 #define __ALD_CONF_H__
20
21
22 #define ALD_DMA
23 #define ALD_GPIO
24 #define ALD_UART
25 #define ALD_LPUART
26 #define ALD_I2C
27 #define ALD_CMU
28 #define ALD_RMU
29 #define ALD_PMU
30 #define ALD_WDT
31 #define ALD_LCD
32 #define ALD_RTC
33 #define ALD_CAN
34 #define ALD_FLASH
35 #define ALD_ADC
36 #define ALD_CRC
37 #define ALD_CRYPT
38 #define ALD_TIMER
39 #define ALD_LPTIM
40 #define ALD_PIS
41 #define ALD_SPI
42 #define ALD_CALC
43 #define ALD_ACMP
44 #define ALD_OPAMP
45 #define ALD_TRNG
46 #define ALD_TSENSE
47 #define ALD_BKPC
48 #define ALD_DAC
49 #define ALD_IAP
50 #define ALD_I2S
51 #define ALD_ECC
52 #define ALD_NAND
53 #define ALD_QSPI
54 #define ALD_NOR
55 #define ALD_SRAM
56 #define ALD_USB
57
58 #if defined(ALD_NAND) || defined(ALD_NOR) || defined(ALD_SRAM)
59 #define ALD_EBI
60 #endif
61
62 #define TICK_INT_PRIORITY 3
63
64 #endif


ALD User Manual: D:/svn/src/ald_crc.c Source File

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ald_crc.c
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1
17 #include "ald_crc.h"
18
27 #ifdef ALD_CRC
28
32 void ald_crc_reset(crc_handle_t *hperh);
33 #ifdef ALD_DMA
34 static void crc_dma_calculate_cplt(void *arg);
35 static void crc_dma_error(void *arg);
36 #endif
37
58 ald_status_t ald_crc_init(crc_handle_t *hperh)
59 {
60 uint32_t tmp = 0;
61
62 if (hperh == NULL)
63 return ERROR;
64
65 assert_param(IS_CRC(hperh->perh));
66 assert_param(IS_CRC_MODE(hperh->init.mode));
67 assert_param(IS_FUNC_STATE(hperh->init.chs_rev));
68 assert_param(IS_FUNC_STATE(hperh->init.data_inv));
69 assert_param(IS_FUNC_STATE(hperh->init.data_rev));
70 assert_param(IS_FUNC_STATE(hperh->init.chs_inv));
71
72 ald_crc_reset(hperh);
73 __LOCK(hperh);
74
75 CRC_ENABLE(hperh);
76
77 tmp = hperh->perh->CR;
78
79 tmp |= ((hperh->init.chs_rev << CRC_CR_CHSREV_POS) | (hperh->init.data_inv << CRC_CR_DATREV_POS) |
80 (hperh->init.chs_inv << CRC_CR_CHSINV_POS) | (hperh->init.mode << CRC_CR_MODE_POSS) |
81 (CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS) | (hperh->init.data_rev << CRC_CR_DATREV_POS) |
82 (0 << CRC_CR_BYTORD_POS));
83
84 hperh->perh->CR = tmp;
85 hperh->perh->SEED = hperh->init.seed;
86 CRC_RESET(hperh);
87
88 hperh->state = CRC_STATE_READY;
89
90 __UNLOCK(hperh);
91 return OK;
92 }
93
111 uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size)
112 {
113 uint32_t i;
114 uint32_t ret;
115
116 assert_param(IS_CRC(hperh->perh));
117
118 if (buf == NULL || size == 0)
119 return 0;
120
121 __LOCK(hperh);
122 MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS);
123 hperh->state = CRC_STATE_BUSY;
124
125 for (i = 0; i < size; i++)
126 *((volatile uint8_t *)&(hperh->perh->DATA)) = buf[i];
127
128 ret = CRC->CHECKSUM;
129 hperh->state = CRC_STATE_READY;
130 __UNLOCK(hperh);
131
132 return ret;
133 }
134
143 uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t size)
144 {
145 uint32_t i;
146 uint32_t ret;
147
148 assert_param(IS_CRC(hperh->perh));
149
150 if (buf == NULL || size == 0)
151 return 0;
152
153 __LOCK(hperh);
154 MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS);
155 hperh->state = CRC_STATE_BUSY;
156
157 for (i = 0; i < size; i++)
158 *((volatile uint16_t *)&(hperh->perh->DATA)) = buf[i];
159
160 ret = CRC->CHECKSUM;
161 hperh->state = CRC_STATE_READY;
162 __UNLOCK(hperh);
163
164 return ret;
165 }
166
175 uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t size)
176 {
177 uint32_t i;
178 uint32_t ret;
179
180 assert_param(IS_CRC(hperh->perh));
181
182 if (buf == NULL || size == 0)
183 return 0;
184
185 __LOCK(hperh);
186 MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS);
187 hperh->state = CRC_STATE_BUSY;
188
189 for (i = 0; i < size; i++)
190 CRC->DATA = buf[i];
191
192 for (i = 0; i < 3; i++);
193
194 ret = CRC->CHECKSUM;
195 hperh->state = CRC_STATE_READY;
196 __UNLOCK(hperh);
197
198 return ret;
199 }
200
205 #ifdef ALD_DMA
206
221 ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
222 {
223 if (hperh->state != CRC_STATE_READY)
224 return BUSY;
225
226 if (buf == NULL || size == 0)
227 return ERROR;
228
229 __LOCK(hperh);
230 MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS);
231
232 hperh->state = CRC_STATE_BUSY;
233
234 hperh->cal_buf = buf;
235 hperh->cal_res = res;
236
237 if (hperh->hdma.perh == NULL)
238 hperh->hdma.perh = DMA0;
239
240 hperh->hdma.cplt_arg = (void *)hperh;
241 hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt;
242 hperh->hdma.err_arg = (void *)hperh;
243 hperh->hdma.err_cbk = &crc_dma_error;
244
245 ald_dma_config_struct(&(hperh->hdma.config));
246 hperh->hdma.config.data_width = DMA_DATA_SIZE_BYTE;
247 hperh->hdma.config.src = (void *)buf;
248 hperh->hdma.config.dst = (void *)&hperh->perh->DATA;
249 hperh->hdma.config.size = size;
250 hperh->hdma.config.src_inc = DMA_DATA_INC_BYTE;
251 hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE;
252 hperh->hdma.config.msel = DMA_MSEL_CRC;
253 hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE;
254 hperh->hdma.config.channel = channel;
255 hperh->hdma.config.burst = ENABLE;
256 ald_dma_config_basic(&(hperh->hdma));
257
258 __UNLOCK(hperh);
259 CRC_DMA_ENABLE(hperh);
260
261 return OK;
262 }
263
274 ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
275 {
276 if (hperh->state != CRC_STATE_READY)
277 return BUSY;
278
279 if (buf == NULL || size == 0)
280 return ERROR;
281
282 __LOCK(hperh);
283 MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS);
284
285 hperh->state = CRC_STATE_BUSY;
286
287 hperh->cal_buf = (uint8_t *)buf;
288 hperh->cal_res = res;
289
290 if (hperh->hdma.perh == NULL)
291 hperh->hdma.perh = DMA0;
292
293 hperh->hdma.cplt_arg = (void *)hperh;
294 hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt;
295 hperh->hdma.err_arg = (void *)hperh;
296 hperh->hdma.err_cbk = &crc_dma_error;
297
298 ald_dma_config_struct(&(hperh->hdma.config));
299 hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD;
300 hperh->hdma.config.src = (void *)buf;
301 hperh->hdma.config.dst = (void *)&hperh->perh->DATA;
302 hperh->hdma.config.size = size;
303 hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD;
304 hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE;
305 hperh->hdma.config.msel = DMA_MSEL_CRC;
306 hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE;
307 hperh->hdma.config.channel = channel;
308 hperh->hdma.config.burst = ENABLE;
309 ald_dma_config_basic(&(hperh->hdma));
310
311 __UNLOCK(hperh);
312 CRC_DMA_ENABLE(hperh);
313
314 return OK;
315 }
316
327 ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
328 {
329 if (hperh->state != CRC_STATE_READY)
330 return BUSY;
331
332 if (buf == NULL || size == 0)
333 return ERROR;
334
335 __LOCK(hperh);
336 MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS);
337
338 hperh->state = CRC_STATE_BUSY;
339
340 hperh->cal_buf = (uint8_t *)buf;
341 hperh->cal_res = res;
342
343 if (hperh->hdma.perh == NULL)
344 hperh->hdma.perh = DMA0;
345
346 hperh->hdma.cplt_arg = (void *)hperh;
347 hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt;
348 hperh->hdma.err_arg = (void *)hperh;
349 hperh->hdma.err_cbk = &crc_dma_error;
350
351 ald_dma_config_struct(&(hperh->hdma.config));
352 hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD;
353 hperh->hdma.config.src = (void *)buf;
354 hperh->hdma.config.dst = (void *)&hperh->perh->DATA;
355 hperh->hdma.config.size = size;
356 hperh->hdma.config.src_inc = DMA_DATA_INC_WORD;
357 hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE;
358 hperh->hdma.config.msel = DMA_MSEL_CRC;
359 hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE;
360 hperh->hdma.config.channel = channel;
361 hperh->hdma.config.burst = ENABLE;
362 ald_dma_config_basic(&(hperh->hdma));
363
364 __UNLOCK(hperh);
365 CRC_DMA_ENABLE(hperh);
366
367 return OK;
368 }
369
370
377 ald_status_t ald_crc_dma_pause(crc_handle_t *hperh)
378 {
379 __LOCK(hperh);
380 CRC_DMA_DISABLE(hperh);
381 __UNLOCK(hperh);
382
383 return OK;
384 }
385
392 ald_status_t ald_crc_dma_resume(crc_handle_t *hperh)
393 {
394 __LOCK(hperh);
395 CRC_DMA_ENABLE(hperh);
396 __UNLOCK(hperh);
397
398 return OK;
399 }
400
407 ald_status_t ald_crc_dma_stop(crc_handle_t *hperh)
408 {
409 __LOCK(hperh);
410 CRC_DMA_DISABLE(hperh);
411 __UNLOCK(hperh);
412
413 hperh->state = CRC_STATE_READY;
414 return OK;
415 }
416
420 #endif
421
433 crc_state_t ald_crc_get_state(crc_handle_t *hperh)
434 {
435 assert_param(IS_CRC(hperh->perh));
436
437 return hperh->state;
438 }
458 void ald_crc_reset(crc_handle_t *hperh)
459 {
460 hperh->perh->DATA = 0x0;
461 hperh->perh->CR = 0x2;
462 hperh->perh->SEED = 0xFFFFFFFF;
463
464 hperh->state = CRC_STATE_READY;
465 __UNLOCK(hperh);
466 return;
467 }
468
469 #ifdef ALD_DMA
470
476 static void crc_dma_calculate_cplt(void *arg)
477 {
478 crc_handle_t *hperh = (crc_handle_t *)arg;
479
480 *(hperh->cal_res) = CRC->CHECKSUM;
481 CRC_DMA_DISABLE(hperh);
482
483 hperh->state = CRC_STATE_READY;
484
485 if (hperh->cal_cplt_cbk)
486 hperh->cal_cplt_cbk(hperh);
487 }
488
495 static void crc_dma_error(void *arg)
496 {
497 crc_handle_t *hperh = (crc_handle_t *)arg;
498
499 CRC_CLEAR_ERROR_FLAG(hperh);
500 CRC_DMA_DISABLE(hperh);
501
502 hperh->state = CRC_STATE_READY;
503
504 if (hperh->err_cplt_cbk)
505 hperh->err_cplt_cbk(hperh);
506 }
507 #endif
508
511 #endif /* ALD_CRC */
512
crc_handle_s::init
crc_init_t init
Definition: ald_crc.h:94
CRC_DATASIZE_16
Definition: ald_crc.h:55
crc_init_t::chs_inv
type_func_t chs_inv
Definition: ald_crc.h:85
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
crc_init_t::data_rev
type_func_t data_rev
Definition: ald_crc.h:82
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
crc_handle_s
CRC Handle Structure definition.
Definition: ald_crc.h:92
crc_dma_calculate_cplt
static void crc_dma_calculate_cplt(void *arg)
DMA CRC calculate process complete callback.
Definition: ald_crc.c:476
ald_crc_calculate_word_by_dma
ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
Calculate an amount of data used dma channel,data width is word.
Definition: ald_crc.c:327
crc_handle_s::cal_cplt_cbk
void(* cal_cplt_cbk)(struct crc_handle_s *arg)
Definition: ald_crc.h:103
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
ald_crc_reset
void ald_crc_reset(crc_handle_t *hperh)
Reset the CRC peripheral.
Definition: ald_crc.c:458
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
CRC_CLEAR_ERROR_FLAG
#define CRC_CLEAR_ERROR_FLAG(handle)
Definition: ald_crc.h:118
dma_config_t::src
void * src
Definition: ald_dma.h:278
ald_crc.h
Header file of CRC module driver.
crc_handle_s::err_cplt_cbk
void(* err_cplt_cbk)(struct crc_handle_s *arg)
Definition: ald_crc.h:104
ald_crc_calculate_by_dma
ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
Calculate an amount of data used dma channel.
Definition: ald_crc.c:221
DMA_DATA_INC_WORD
Definition: ald_dma.h:219
DMA_DATA_SIZE_WORD
Definition: ald_dma.h:229
crc_handle_s::cal_buf
uint8_t * cal_buf
Definition: ald_crc.h:95
DMA_DATA_SIZE_BYTE
Definition: ald_dma.h:227
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
ald_crc_dma_resume
ald_status_t ald_crc_dma_resume(crc_handle_t *hperh)
Resumes the DMA Transfer.
Definition: ald_crc.c:392
crc_init_t::mode
crc_mode_t mode
Definition: ald_crc.h:81
IS_CRC_MODE
#define IS_CRC_MODE(x)
Definition: ald_crc.h:127
CRC_DMA_ENABLE
#define CRC_DMA_ENABLE(handle)
Definition: ald_crc.h:116
ald_crc_calculate
uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size)
Calculate the crc value of data by byte.
Definition: ald_crc.c:111
crc_dma_error
static void crc_dma_error(void *arg)
DMA CRC communication error callback.
Definition: ald_crc.c:495
CRC_DATASIZE_8
Definition: ald_crc.h:54
CRC_RESET
#define CRC_RESET(handle)
Definition: ald_crc.h:115
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
ald_crc_init
ald_status_t ald_crc_init(crc_handle_t *hperh)
Initializes the CRC mode according to the specified parameters in the crc_handle_t and create the ass...
Definition: ald_crc.c:58
CRC_DMA_DISABLE
#define CRC_DMA_DISABLE(handle)
Definition: ald_crc.h:117
crc_init_t::seed
uint32_t seed
Definition: ald_crc.h:86
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
crc_init_t::chs_rev
type_func_t chs_rev
Definition: ald_crc.h:84
CRC_STATE_BUSY
Definition: ald_crc.h:73
DMA_DATA_INC_BYTE
Definition: ald_dma.h:217
CRC_ENABLE
#define CRC_ENABLE(handle)
Definition: ald_crc.h:113
crc_handle_s::cal_res
uint32_t * cal_res
Definition: ald_crc.h:96
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
ald_crc_dma_pause
ald_status_t ald_crc_dma_pause(crc_handle_t *hperh)
Pauses the DMA Transfer.
Definition: ald_crc.c:377
crc_handle_s::perh
CRC_TypeDef * perh
Definition: ald_crc.h:93
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
DMA_MSEL_CRC
Definition: ald_dma.h:83
ald_crc_calculate_halfword
uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t size)
Calculate the crc value of data by halfword.
Definition: ald_crc.c:143
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
DMA_MSIGSEL_NONE
Definition: ald_dma.h:115
ald_crc_calculate_halfword_by_dma
ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
Calculate an amount of data used dma channel,data width is half-word.
Definition: ald_crc.c:274
crc_init_t::data_inv
type_func_t data_inv
Definition: ald_crc.h:83
ald_crc_dma_stop
ald_status_t ald_crc_dma_stop(crc_handle_t *hperh)
Stops the DMA Transfer.
Definition: ald_crc.c:407
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
ald_crc_calculate_word
uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t size)
Calculate the crc value of data by word.
Definition: ald_crc.c:175
crc_handle_s::hdma
dma_handle_t hdma
Definition: ald_crc.h:98
ald_crc_get_state
crc_state_t ald_crc_get_state(crc_handle_t *hperh)
Returns the CRC state.
Definition: ald_crc.c:433
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
crc_handle_s::state
crc_state_t state
Definition: ald_crc.h:101
CRC_DATASIZE_32
Definition: ald_crc.h:56
__LOCK
#define __LOCK(x)
Definition: utils.h:92
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
crc_state_t
crc_state_t
CRC state structures definition.
Definition: ald_crc.h:70
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
IS_CRC
#define IS_CRC(x)
Definition: ald_crc.h:126
CRC_STATE_READY
Definition: ald_crc.h:72


ALD User Manual: D:/svn/src/ald_crc.h Source File

  • D:
  • svn
  • src
ald_crc.h
Go to the documentation of this file.
1
17 #ifndef __ALD_CRC_H__
18 #define __ALD_CRC_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25 #include "ald_dma.h"
26
42 typedef enum {
43 CRC_MODE_CCITT = 0U,
44 CRC_MODE_8 = 1U,
45 CRC_MODE_16 = 2U,
46 CRC_MODE_32 = 3U,
47 } crc_mode_t;
48
52 typedef enum {
53 CRC_LEN_AUTO = 0U,
54 CRC_DATASIZE_8 = 1U,
55 CRC_DATASIZE_16 = 2U,
56 CRC_DATASIZE_32 = 3U,
57 } crc_datasize_t;
58
62 typedef enum {
63 CRC_WERR_NO = 0U,
64 CRC_WERR_ERR = 1U,
65 } crc_werr_t;
66
70 typedef enum {
71 CRC_STATE_RESET = 0x0U,
72 CRC_STATE_READY = 0x1U,
73 CRC_STATE_BUSY = 0x2U,
74 CRC_STATE_ERROR = 0x4U,
75 } crc_state_t;
76
80 typedef struct {
81 crc_mode_t mode;
82 type_func_t data_rev;
83 type_func_t data_inv;
84 type_func_t chs_rev;
85 type_func_t chs_inv;
86 uint32_t seed;
87 } crc_init_t;
88
92 typedef struct crc_handle_s {
93 CRC_TypeDef *perh;
94 crc_init_t init;
95 uint8_t *cal_buf;
96 uint32_t *cal_res;
97 #ifdef ALD_DMA
98 dma_handle_t hdma;
99 #endif
100 lock_state_t lock;
101 crc_state_t state;
103 void (*cal_cplt_cbk)(struct crc_handle_s *arg);
104 void (*err_cplt_cbk)(struct crc_handle_s *arg);
105 } crc_handle_t;
113 #define CRC_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
114 #define CRC_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_EN_MSK))
115 #define CRC_RESET(handle) (SET_BIT((handle)->perh->CR, CRC_CR_RST_MSK))
116 #define CRC_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
117 #define CRC_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CR, CRC_CR_DMAEN_MSK))
118 #define CRC_CLEAR_ERROR_FLAG(handle) (SET_BIT((handle)->perh->CR, CRC_CR_WERR_MSK))
119
126 #define IS_CRC(x) ((x) == CRC)
127 #define IS_CRC_MODE(x) (((x) == CRC_MODE_CCITT) || \
128 ((x) == CRC_MODE_8) || \
129 ((x) == CRC_MODE_16) || \
130 ((x) == CRC_MODE_32))
131
142 ald_status_t ald_crc_init(crc_handle_t *hperh);
143 void ald_crc_reset(crc_handle_t *hperh);
151 uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size);
152 uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t size);
153 uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t size);
158 #ifdef ALD_DMA
159
162 ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel);
163 ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel);
164 ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel);
165 ald_status_t ald_crc_dma_pause(crc_handle_t *hperh);
166 ald_status_t ald_crc_dma_resume(crc_handle_t *hperh);
167 ald_status_t ald_crc_dma_stop(crc_handle_t *hperh);
171 #endif
172
175 crc_state_t ald_crc_get_state(crc_handle_t *hperh);
192 #ifdef __cplusplus
193 }
194 #endif
195
196 #endif /* __ALD_CRC_H__ */
crc_handle_s::init
crc_init_t init
Definition: ald_crc.h:94
CRC_DATASIZE_16
Definition: ald_crc.h:55
crc_init_t::chs_inv
type_func_t chs_inv
Definition: ald_crc.h:85
crc_werr_t
crc_werr_t
CRC whether write error or no.
Definition: ald_crc.h:62
dma_handle_t
DMA handle structure definition.
Definition: ald_dma.h:297
crc_init_t::data_rev
type_func_t data_rev
Definition: ald_crc.h:82
crc_handle_s
CRC Handle Structure definition.
Definition: ald_crc.h:92
ald_crc_calculate_word_by_dma
ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
Calculate an amount of data used dma channel,data width is word.
Definition: ald_crc.c:327
type_func_t
type_func_t
Definition: type.h:47
crc_handle_t
struct crc_handle_s crc_handle_t
CRC Handle Structure definition.
crc_mode_t
crc_mode_t
CRC mode.
Definition: ald_crc.h:42
crc_handle_s::err_cplt_cbk
void(* err_cplt_cbk)(struct crc_handle_s *arg)
Definition: ald_crc.h:104
ald_crc_calculate_by_dma
ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
Calculate an amount of data used dma channel.
Definition: ald_crc.c:221
crc_handle_s::cal_buf
uint8_t * cal_buf
Definition: ald_crc.h:95
ald_crc_dma_resume
ald_status_t ald_crc_dma_resume(crc_handle_t *hperh)
Resumes the DMA Transfer.
Definition: ald_crc.c:392
utils.h
This file contains the Utilities functions/types for the driver.
crc_init_t::mode
crc_mode_t mode
Definition: ald_crc.h:81
ald_crc_calculate
uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size)
Calculate the crc value of data by byte.
Definition: ald_crc.c:111
CRC_DATASIZE_8
Definition: ald_crc.h:54
CRC_WERR_ERR
Definition: ald_crc.h:64
CRC_STATE_ERROR
Definition: ald_crc.h:74
CRC_WERR_NO
Definition: ald_crc.h:63
CRC_STATE_RESET
Definition: ald_crc.h:71
ald_crc_init
ald_status_t ald_crc_init(crc_handle_t *hperh)
Initializes the CRC mode according to the specified parameters in the crc_handle_t and create the ass...
Definition: ald_crc.c:58
lock_state_t
lock_state_t
Definition: type.h:58
crc_init_t
CRC init structure definition.
Definition: ald_crc.h:80
ald_dma.h
DMA module Library.
CRC_MODE_8
Definition: ald_crc.h:44
crc_handle_s::lock
lock_state_t lock
Definition: ald_crc.h:100
crc_init_t::seed
uint32_t seed
Definition: ald_crc.h:86
crc_init_t::chs_rev
type_func_t chs_rev
Definition: ald_crc.h:84
CRC_STATE_BUSY
Definition: ald_crc.h:73
crc_handle_s::cal_res
uint32_t * cal_res
Definition: ald_crc.h:96
ald_crc_dma_pause
ald_status_t ald_crc_dma_pause(crc_handle_t *hperh)
Pauses the DMA Transfer.
Definition: ald_crc.c:377
crc_handle_s::perh
CRC_TypeDef * perh
Definition: ald_crc.h:93
CRC_LEN_AUTO
Definition: ald_crc.h:53
CRC_MODE_16
Definition: ald_crc.h:45
CRC_MODE_CCITT
Definition: ald_crc.h:43
ald_crc_calculate_halfword
uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t size)
Calculate the crc value of data by halfword.
Definition: ald_crc.c:143
CRC_MODE_32
Definition: ald_crc.h:46
ald_crc_calculate_halfword_by_dma
ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
Calculate an amount of data used dma channel,data width is half-word.
Definition: ald_crc.c:274
crc_init_t::data_inv
type_func_t data_inv
Definition: ald_crc.h:83
ald_crc_dma_stop
ald_status_t ald_crc_dma_stop(crc_handle_t *hperh)
Stops the DMA Transfer.
Definition: ald_crc.c:407
ald_crc_calculate_word
uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t size)
Calculate the crc value of data by word.
Definition: ald_crc.c:175
crc_handle_s::hdma
dma_handle_t hdma
Definition: ald_crc.h:98
ald_crc_get_state
crc_state_t ald_crc_get_state(crc_handle_t *hperh)
Returns the CRC state.
Definition: ald_crc.c:433
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
crc_datasize_t
crc_datasize_t
CRC input length.
Definition: ald_crc.h:52
crc_handle_s::state
crc_state_t state
Definition: ald_crc.h:101
CRC_DATASIZE_32
Definition: ald_crc.h:56
crc_state_t
crc_state_t
CRC state structures definition.
Definition: ald_crc.h:70
ald_crc_reset
void ald_crc_reset(crc_handle_t *hperh)
Reset the CRC peripheral.
Definition: ald_crc.c:458
CRC_STATE_READY
Definition: ald_crc.h:72


ALD User Manual: D:/svn/src/ald_crypt.c Source File

  • D:
  • svn
  • src
ald_crypt.c
Go to the documentation of this file.
1
19 #include "ald_crypt.h"
20
21
30 #ifdef ALD_CRYPT
31
35 void crypt_reset(crypt_handle_t *hperh);
36 #ifdef ALD_DMA
37 static void crypt_dma_crypt_cplt(void *arg);
38 static void crypt_dma_error(void *arg);
39 #endif
40
61 ald_status_t ald_crypt_init(crypt_handle_t *hperh)
62 {
63 uint32_t tmp = 0;
64
65 if (hperh == NULL)
66 return ERROR;
67
68 assert_param(IS_CRYPT(hperh->perh));
69 assert_param(IS_CRYPT_MODE(hperh->init.mode));
70 assert_param(IS_CRYPT_KS(hperh->init.key));
71
72 if ((hperh->init.key == CRYPT_DES_KEYS_1 || hperh->init.key == CRYPT_DES_KEYS_2 || hperh->init.key == CRYPT_DES_KEYS_3)
73 && (hperh->init.mode == CRYPT_MODE_CTR)) {
74 return ERROR;
75 }
76
77 __LOCK(hperh);
78 crypt_reset(hperh);
79
80 if (hperh->state == CRYPT_STATE_RESET)
81 __UNLOCK(hperh);
82
83 tmp = hperh->perh->CON;
84 switch (hperh->init.key) {
85 case CRYPT_AES_BITS_128:
86 tmp |= ((CRYPT_CRYSEL_AES << CRYPT_CON_CRYSEL_POS) | \
87 (CRYPT_BITS_128 << CRYPT_CON_AESKS_POSS));
88 hperh->step = 4;
89 break;
90
91 case CRYPT_AES_BITS_192:
92 tmp |= ((CRYPT_CRYSEL_AES << CRYPT_CON_CRYSEL_POS) | \
93 (CRYPT_BITS_192 << CRYPT_CON_AESKS_POSS));
94 hperh->step = 4;
95 break;
96
97 case CRYPT_AES_BITS_256:
98 tmp |= ((CRYPT_CRYSEL_AES << CRYPT_CON_CRYSEL_POS) | \
99 (CRYPT_BITS_256 << CRYPT_CON_AESKS_POSS));
100 hperh->step = 4;
101 break;
102
103 case CRYPT_DES_KEYS_1:
104 SET_BIT(tmp, CRYPT_CON_CRYSEL_MSK);
105 hperh->step = 2;
106 break;
107
108 case CRYPT_DES_KEYS_2:
109 SET_BIT(tmp, CRYPT_CON_CRYSEL_MSK);
110 tmp |= ((1 << CRYPT_CON_TDES_POS) | (CRYPT_KEYS_2 << CRYPT_CON_DESKS_POS));
111 hperh->step = 2;
112 break;
113
114 case CRYPT_DES_KEYS_3:
115 SET_BIT(tmp, CRYPT_CON_CRYSEL_MSK);
116 tmp |= ((1 << CRYPT_CON_TDES_POS) | (CRYPT_KEYS_3 << CRYPT_CON_DESKS_POS));
117 hperh->step = 2;
118 break;
119
120 default:
121 hperh->state = CRYPT_STATE_ERROR;
122 __UNLOCK(hperh);
123 return ERROR;
124 }
125
126 tmp |= ((1 << CRYPT_CON_FIFOODR_POS) | (hperh->init.mode << CRYPT_CON_MODE_POSS) | \
127 (hperh->init.type << CRYPT_CON_TYPE_POSS) | (1 << CRYPT_CON_FIFOEN_POS));
128 hperh->perh->CON = tmp;
129
130 hperh->state = CRYPT_STATE_READY;
131 __UNLOCK(hperh);
132 return OK;
133 }
134
143 ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t * key, crypt_key_len_t len)
144 {
145 uint32_t *temp = key;
146 uint32_t i;
147
148 if ((hperh == NULL) || (key == NULL))
149 return ERROR;
150 if (hperh->state == CRYPT_STATE_BUSY)
151 return BUSY;
152
153 assert_param(IS_CRYPT(hperh->perh));
154 assert_param(IS_CRYPT_KEY_LEN(len));
155
156 if ((hperh->init.key & 0xF) != len)
157 return ERROR;
158
159 switch (len) {
160 case KEY_8_LEN:
161 hperh->perh->KEY[7] = *temp++;
162 hperh->perh->KEY[6] = *temp++;
163 hperh->perh->KEY[5] = *temp++;
164 hperh->perh->KEY[4] = *temp++;
165 hperh->perh->KEY[3] = *temp++;
166 hperh->perh->KEY[2] = *temp++;
167 hperh->perh->KEY[1] = *temp++;
168 hperh->perh->KEY[0] = *temp;
169 break;
170
171 case KEY_6_LEN:
172 hperh->perh->KEY[5] = *temp++;
173 hperh->perh->KEY[4] = *temp++;
174 hperh->perh->KEY[3] = *temp++;
175 hperh->perh->KEY[2] = *temp++;
176 hperh->perh->KEY[1] = *temp++;
177 hperh->perh->KEY[0] = *temp;
178 break;
179
180 case KEY_4_LEN:
181 hperh->perh->KEY[3] = *temp++;
182 hperh->perh->KEY[2] = *temp++;
183 hperh->perh->KEY[1] = *temp++;
184 hperh->perh->KEY[0] = *temp;
185 break;
186
187 case KEY_2_LEN:
188 hperh->perh->KEY[1] = *temp++;
189 hperh->perh->KEY[0] = *temp;
190 break;
191
192 default:
193 break;
194 }
195
196 for (i = 0; i < len; i++)
197 hperh->key[i] = *key++;
198
199 hperh->key_size = len;
200
201 return OK;
202 }
203
212 ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t * key, crypt_key_len_t len)
213 {
214 uint32_t *temp = key;
215
216 if ((hperh == NULL) || (key == NULL))
217 return ERROR;
218 if (hperh->state == CRYPT_STATE_BUSY)
219 return BUSY;
220
221 assert_param(IS_CRYPT(hperh->perh));
222 assert_param(IS_CRYPT_KEY_LEN(len));
223
224 switch (len) {
225 case KEY_8_LEN:
226 *temp++ = hperh->perh->KEY[7];
227 *temp++ = hperh->perh->KEY[6];
228 *temp++ = hperh->perh->KEY[5];
229 *temp++ = hperh->perh->KEY[4];
230 *temp++ = hperh->perh->KEY[3];
231 *temp++ = hperh->perh->KEY[2];
232 *temp++ = hperh->perh->KEY[1];
233 *temp = hperh->perh->KEY[0];
234 break;
235
236 case KEY_6_LEN:
237 *temp++ = hperh->perh->KEY[5];
238 *temp++ = hperh->perh->KEY[4];
239 *temp++ = hperh->perh->KEY[3];
240 *temp++ = hperh->perh->KEY[2];
241 *temp++ = hperh->perh->KEY[1];
242 *temp = hperh->perh->KEY[0];
243 break;
244
245 case KEY_4_LEN:
246 *temp++ = hperh->perh->KEY[3];
247 *temp++ = hperh->perh->KEY[2];
248 *temp++ = hperh->perh->KEY[1];
249 *temp = hperh->perh->KEY[0];
250 break;
251
252 case KEY_2_LEN:
253 *temp++ = hperh->perh->KEY[1];
254 *temp = hperh->perh->KEY[0];
255 break;
256
257 default:
258 break;
259 }
260
261 return OK;
262 }
263
272 ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t * iv, crypt_ivr_len_t len)
273 {
274 uint32_t *temp = iv;
275 uint32_t i;
276
277 if ((hperh == NULL) || (iv == NULL))
278 return ERROR;
279 if (hperh->state == CRYPT_STATE_BUSY)
280 return BUSY;
281
282 assert_param(IS_CRYPT(hperh->perh));
283 assert_param(IS_CRYPT_IV_LEN(len));
284
285 switch (len) {
286 case IV_4_LEN:
287 hperh->perh->IV[3] = *temp++;
288 hperh->perh->IV[2] = *temp++;
289 hperh->perh->IV[1] = *temp++;
290 hperh->perh->IV[0] = *temp;
291 break;
292
293 case IV_2_LEN:
294 hperh->perh->IV[1] = *temp++;
295 hperh->perh->IV[0] = *temp;
296 break;
297
298 default:
299 break;
300 }
301
302 for (i = 0; i < len; i++)
303 hperh->iv[i] = *iv++;
304
305 hperh->iv_size = len;
306
307 CRYPT_IVEN_ENABLE(hperh);
308 return OK;
309 }
310
319 ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv, crypt_ivr_len_t len)
320 {
321 uint32_t *temp = iv;
322
323 if ((hperh == NULL) || (iv == NULL))
324 return ERROR;
325 if (hperh->state == CRYPT_STATE_BUSY)
326 return BUSY;
327
328 assert_param(IS_CRYPT(hperh->perh));
329 assert_param(IS_CRYPT_IV_LEN(len));
330
331 switch (len) {
332 case IV_4_LEN:
333 *temp++ = hperh->perh->IV[3];
334 *temp++ = hperh->perh->IV[2];
335 *temp++ = hperh->perh->IV[1];
336 *temp = hperh->perh->IV[0];
337 break;
338
339 case IV_2_LEN:
340 *temp++ = hperh->perh->IV[1];
341 *temp = hperh->perh->IV[0];
342 break;
343
344 default:
345 break;
346 }
347
348 return OK;
349 }
350
370 ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t * plain_text, uint8_t * cipher_text, uint32_t size)
371 {
372 uint32_t count = 0;
373 uint32_t i;
374 uint32_t *plain_buf = (uint32_t *)plain_text;
375 uint32_t *cipher_buf = (uint32_t *)cipher_text;
376
377 if (hperh->state != CRYPT_STATE_READY)
378 return ERROR;
379
380 if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0))
381 return ERROR;
382
383 assert_param(IS_CRYPT(hperh->perh));
384
385 __LOCK(hperh);
386 hperh->state = CRYPT_STATE_BUSY;
387 CRYPT_SETDIR(hperh, CRYPT_ENCRYPT);
388 count = size / (4 * hperh->step);
389
390 while (count--) {
391 for (i = 0; i < hperh->step; i++) {
392 CRYPT_WRITE_FIFO(hperh, *plain_buf);
393 plain_buf++;
394 }
395
396 while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET);
397
398 for (i = 0; i < hperh->step; i++)
399 *cipher_buf++ = CRYPT_READ_FIFO(hperh);
400 }
401
402 hperh->state = CRYPT_STATE_READY;
403 __UNLOCK(hperh);
404
405 return OK;
406 }
407
418 ald_status_t ald_crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size)
419 {
420 uint32_t count = 0;
421 uint32_t i;
422 uint32_t *plain_buf = (uint32_t*)plain_text;
423 uint32_t *cipher_buf = (uint32_t*)cipher_text;
424
425 if (hperh->init.mode == CRYPT_MODE_CTR) {
426 return ald_crypt_encrypt(hperh, cipher_text, plain_text, size);
427 }
428
429 if (hperh->state != CRYPT_STATE_READY)
430 return ERROR;
431
432 if ((plain_buf == NULL) || (cipher_buf == NULL) || (size == 0))
433 return ERROR;
434
435 assert_param(IS_CRYPT(hperh->perh));
436
437 __LOCK(hperh);
438 hperh->state = CRYPT_STATE_BUSY;
439 CRYPT_SETDIR(hperh, CRYPT_DECRYPT);
440 count = size / (4 * hperh->step);
441
442 while (count--) {
443 for (i = 0; i < hperh->step; i++) {
444 CRYPT_WRITE_FIFO(hperh, *cipher_buf);
445 cipher_buf++;
446 }
447
448 while (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DONE) == SET);
449
450 for (i = 0; i < hperh->step; i++)
451 *plain_buf++ = CRYPT_READ_FIFO(hperh);
452 }
453
454 hperh->state = CRYPT_STATE_READY;
455 __UNLOCK(hperh);
456
457 return OK;
458 }
459
460 void gcm_mul(uint32_t *res, uint32_t *data, uint32_t *iv)
461 {
462 CRYPT->CON = 0;
463 CRYPT->DATA[0] = data[3];
464 CRYPT->DATA[1] = data[2];
465 CRYPT->DATA[2] = data[1];
466 CRYPT->DATA[3] = data[0];
467 CRYPT->IV[0] = iv[3];
468 CRYPT->IV[1] = iv[2];
469 CRYPT->IV[2] = iv[1];
470 CRYPT->IV[3] = iv[0];
471 CRYPT->CON |= ((1 << CRYPT_CON_RESCLR_POS) | (3 << CRYPT_CON_MODE_POSS) | \
472 (1 << CRYPT_CON_GO_POS));
473
474 while (READ_BIT(CRYPT->IF, CRYPT_IF_MULTHIF_MSK) == 0);
475
476 res[3] = CRYPT->RES[0];
477 res[2] = CRYPT->RES[1];
478 res[1] = CRYPT->RES[2];
479 res[0] = CRYPT->RES[3];
480
481 SET_BIT(CRYPT->IFC, CRYPT_IFC_MULTHIFC_MSK);
482 return;
483 }
484
496 ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag)
497 {
498 uint8_t GCM_HASH_in[0x60] = {0} ;
499 uint8_t ecb[16] = {0} ;
500 uint32_t x_temp[4];
501 uint64_t u, v;
502 uint32_t len = 0;
503 uint32_t j, i, k;
504 uint32_t *tag_temp, *cipher_text_temp;
505
506 /* calculate u and v */
507 u = 128 * ((size % 16) ? (size / 16 + 1) : size / 16) - size * 8;
508 v = 128 * ((alen % 16) ? (alen / 16 + 1): alen / 16) - alen * 8;
509
510 /* get the input of GHASH algorithm,the input:A||0^v||C||0^u||[len(A)]_64||[len(C)]_64 */
511 for (i = 0; i < alen; i++) {
512 GCM_HASH_in [i] = * (aadata + i);
513 }
514 len += alen;
515 for (i = 0; i < v / 8; i++) {
516 GCM_HASH_in[i + len] = 0;
517 }
518 len += v / 8;
519 for (i = 0; i < size; i++) {
520 GCM_HASH_in[i + len] = * (cipher_text + i);
521 }
522 len += size;
523 for (i = 0; i < u / 8; i++) {
524 GCM_HASH_in[i + len] = 0;
525 }
526 len += u / 8;
527
528 for (i = 0; i < 4; i++) {
529 GCM_HASH_in[i + len] = 0;
530 }
531 len += 4;
532
533 for (i = 0; i < 4; i++) {
534 GCM_HASH_in[i + len] = ((alen * 8) >> (8 * i)) & 0xFF;
535 }
536 len += 4;
537
538 for (i = 0; i < 4; i++) {
539 GCM_HASH_in[i + len] = 0;
540 }
541 len += 4;
542
543 for (i = 0; i < 4; i++) {
544 GCM_HASH_in[i + len] = ((size * 8) >> (8 * i)) & 0xFF;
545 }
546 len += 4;
547
548 CRYPT->CON &= ~(3U << CRYPT_CON_MODE_POSS);
549 CRYPT->CON |= (CRYPT_MODE_ECB << CRYPT_CON_MODE_POSS);
550
551 ald_crypt_encrypt(hperh, ecb, ecb, 16);
552
553 k = len / 16;
554 for (i = 0; i < 16; i++) {
555 tag[i] = 0;
556 }
557
558 cipher_text_temp = (uint32_t *)GCM_HASH_in;
559 tag_temp = (uint32_t *)tag;
560 for (i = 0; i < k; i++) {
561 for (j = 0; j < 4; j++) {
562 x_temp[j] = (*cipher_text_temp) ^ tag_temp[j];
563 ++cipher_text_temp;
564 }
565
566 gcm_mul((uint32_t *)tag_temp, x_temp, (uint32_t *)ecb);
567 }
568
569 /* calculate the authentication tag T,
570 * T = CIPH_K(J0)^S,J0=IV||0^31||1,CIPH_K is the algorithm of AES in ECB mode
571 */
572 tag_temp = (uint32_t *)tag;
573 ald_crypt_init(hperh);
574 CRYPT->CON &= ~(3U << CRYPT_CON_MODE_POSS);
575 CRYPT->CON |= (CRYPT_MODE_CTR << CRYPT_CON_MODE_POSS);
576 ald_crypt_write_key(hperh, hperh->key, KEY_4_LEN);
577 hperh->iv[3] = 1;
578 ald_crypt_write_ivr(hperh, hperh->iv, IV_4_LEN);
579 ald_crypt_encrypt(hperh, tag, tag, 16);
580
581 return OK;
582 }
583
594 ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t * plain_text, uint8_t *cipher_text, uint32_t size)
595 {
596 uint32_t i;
597 uint32_t *plain_buf = (uint32_t *)plain_text;
598
599 if (hperh->state != CRYPT_STATE_READY)
600 return ERROR;
601
602 if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0))
603 return ERROR;
604
605 assert_param(IS_CRYPT(hperh->perh));
606
607 __LOCK(hperh);
608 hperh->state = CRYPT_STATE_BUSY;
609 CRYPT_SETDIR(hperh, CRYPT_ENCRYPT);
610 hperh->count = hperh->step;
611 hperh->plain_text = plain_text;
612 hperh->cipher_text = cipher_text;
613 hperh->size = size;
614 ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE);
615
616 for (i = 0; i < hperh->step; i++) {
617 CRYPT_WRITE_FIFO(hperh, *plain_buf);
618 ++plain_buf;
619 }
620
621 __UNLOCK(hperh);
622 return OK;
623 }
624
635 ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size)
636 {
637 uint32_t i;
638 uint32_t *cipher_buf = (uint32_t*)cipher_text;
639
640 if (hperh->init.mode == CRYPT_MODE_CTR) {
641 return ald_crypt_decrypt_by_it(hperh, cipher_text, plain_text, size);
642 }
643
644 if (hperh->state != CRYPT_STATE_READY)
645 return ERROR;
646
647 if ((plain_text == NULL) || (cipher_text == NULL) || (size == 0))
648 return ERROR;
649
650 assert_param(IS_CRYPT(hperh->perh));
651
652 __LOCK(hperh);
653 hperh->state = CRYPT_STATE_BUSY;
654 CRYPT_SETDIR(hperh, CRYPT_DECRYPT);
655 hperh->count = hperh->step;
656 hperh->plain_text = plain_text;
657 hperh->cipher_text = cipher_text;
658 hperh->size = size;
659 ald_crypt_interrupt_config(hperh, CRYPT_IT_IT, ENABLE);
660
661 for (i = 0; i < hperh->step; i++) {
662 CRYPT_WRITE_FIFO(hperh, *cipher_buf);
663 cipher_buf ++;
664 }
665
666 __UNLOCK(hperh);
667 return OK;
668 }
669
670 #ifdef ALD_DMA
671
683 ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t * plain_text,
684 uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m)
685 {
686 if (hperh->state != CRYPT_STATE_READY)
687 return ERROR;
688
689 if (plain_text == NULL || cipher_text == NULL || size == 0)
690 return ERROR;
691
692 assert_param(IS_CRYPT(hperh->perh));
693
694 __LOCK(hperh);
695 hperh->state = CRYPT_STATE_BUSY;
696
697 hperh->plain_text = plain_text;
698 hperh->cipher_text = cipher_text;
699 hperh->size = size;
700 hperh->count = size;
701
702 if (hperh->hdma_m2p.perh == NULL)
703 hperh->hdma_m2p.perh = DMA0;
704 if (hperh->hdma_p2m.perh == NULL)
705 hperh->hdma_p2m.perh = DMA0;
706
707 hperh->hdma_m2p.cplt_arg = NULL;
708 hperh->hdma_m2p.cplt_cbk = NULL;
709 hperh->hdma_m2p.err_arg = NULL;
710 hperh->hdma_m2p.err_cbk = NULL;
711
712 hperh->hdma_p2m.cplt_arg = (void *)hperh;
713 hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt;
714 hperh->hdma_p2m.err_arg = (void *)hperh;
715 hperh->hdma_p2m.err_cbk = &crypt_dma_error;
716
717 CRYPT_SETDIR(hperh, CRYPT_ENCRYPT);
718
719 ald_dma_config_struct(&hperh->hdma_m2p.config);
720 hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD;
721 hperh->hdma_m2p.config.src = (void *)hperh->plain_text;
722 hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO;
723 hperh->hdma_m2p.config.size = size / 4;
724 hperh->hdma_m2p.config.src_inc = DMA_DATA_INC_WORD;
725 hperh->hdma_m2p.config.dst_inc = DMA_DATA_INC_NONE;
726 hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT;
727 hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE;
728 hperh->hdma_m2p.config.burst = ENABLE;
729 hperh->hdma_m2p.config.channel = channel_m2p;
730 ald_dma_config_basic(&(hperh->hdma_m2p));
731
732 ald_dma_config_struct(&hperh->hdma_p2m.config);
733 hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD;
734 hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO;
735 hperh->hdma_p2m.config.dst = (void *)hperh->cipher_text;
736 hperh->hdma_p2m.config.size = size / 4;
737 hperh->hdma_p2m.config.src_inc = DMA_DATA_INC_NONE;
738 hperh->hdma_p2m.config.dst_inc = DMA_DATA_INC_WORD;
739 hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT;
740 hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ;
741 hperh->hdma_p2m.config.burst = ENABLE;
742 hperh->hdma_p2m.config.channel = channel_p2m;
743 ald_dma_config_basic(&(hperh->hdma_p2m));
744
745 CRYPT_DMA_ENABLE(hperh);
746 __UNLOCK(hperh);
747
748 return OK;
749 }
750
763 ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t * cipher_text,
764 uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m)
765 {
766 if (hperh->init.mode == CRYPT_MODE_CTR)
767 return ald_crypt_decrypt_by_dma(hperh, cipher_text, plain_text, size, channel_m2p, channel_p2m);
768
769 if (hperh->state != CRYPT_STATE_READY)
770 return ERROR;
771 if (plain_text == NULL || cipher_text == NULL || size == 0)
772 return ERROR;
773
774 __LOCK(hperh);
775 hperh->state = CRYPT_STATE_BUSY;
776
777 hperh->plain_text = plain_text;
778 hperh->cipher_text = cipher_text;
779 hperh->size = size;
780 hperh->count = size;
781
782 if (hperh->hdma_m2p.perh == NULL)
783 hperh->hdma_m2p.perh = DMA0;
784 if (hperh->hdma_p2m.perh == NULL)
785 hperh->hdma_p2m.perh = DMA0;
786
787
788 hperh->hdma_m2p.cplt_arg = NULL;
789 hperh->hdma_m2p.cplt_cbk = NULL;
790 hperh->hdma_m2p.err_arg = NULL;
791 hperh->hdma_m2p.err_cbk = NULL;
792
793 hperh->hdma_p2m.cplt_arg = (void *)hperh;
794 hperh->hdma_p2m.cplt_cbk = &crypt_dma_crypt_cplt;
795 hperh->hdma_p2m.err_arg = (void *)hperh;
796 hperh->hdma_p2m.err_cbk = &crypt_dma_error;
797
798 CRYPT_SETDIR(hperh, CRYPT_DECRYPT);
799
800 ald_dma_config_struct(&hperh->hdma_m2p.config);
801 hperh->hdma_m2p.config.data_width = DMA_DATA_SIZE_WORD;
802 hperh->hdma_m2p.config.src = (void *)hperh->cipher_text;
803 hperh->hdma_m2p.config.dst = (void *)&hperh->perh->FIFO;
804 hperh->hdma_m2p.config.size = size / 4;
805 hperh->hdma_m2p.config.src_inc = DMA_DATA_INC_WORD;
806 hperh->hdma_m2p.config.dst_inc = DMA_DATA_INC_NONE;
807 hperh->hdma_m2p.config.msel = DMA_MSEL_CRYPT;
808 hperh->hdma_m2p.config.msigsel = DMA_MSIGSEL_CRYPT_WRITE;
809 hperh->hdma_m2p.config.burst = ENABLE;
810 hperh->hdma_m2p.config.channel = channel_m2p;
811 ald_dma_config_basic(&(hperh->hdma_m2p));
812
813 ald_dma_config_struct(&hperh->hdma_p2m.config);
814 hperh->hdma_p2m.config.data_width = DMA_DATA_SIZE_WORD;
815 hperh->hdma_p2m.config.src = (void *)&hperh->perh->FIFO;
816 hperh->hdma_p2m.config.dst = (void *)hperh->plain_text;
817 hperh->hdma_p2m.config.size = size / 4;
818 hperh->hdma_p2m.config.src_inc = DMA_DATA_INC_NONE;
819 hperh->hdma_p2m.config.dst_inc = DMA_DATA_INC_WORD;
820 hperh->hdma_p2m.config.msel = DMA_MSEL_CRYPT;
821 hperh->hdma_p2m.config.msigsel = DMA_MSIGSEL_CRYPT_READ;
822 hperh->hdma_m2p.config.burst = ENABLE;
823 hperh->hdma_p2m.config.channel = channel_p2m;
824 ald_dma_config_basic(&(hperh->hdma_p2m));
825
826 CRYPT_DMA_ENABLE(hperh);
827 __UNLOCK(hperh);
828
829 return OK;
830 }
831
847 ald_status_t ald_crypt_dma_pause(crypt_handle_t *hperh)
848 {
849 __LOCK(hperh);
850 CRYPT_DMA_DISABLE(hperh);
851 __UNLOCK(hperh);
852
853 return OK;
854
855 }
856
863 ald_status_t ald_crypt_dma_resume(crypt_handle_t *hperh)
864 {
865 __LOCK(hperh);
866 CRYPT_DMA_ENABLE(hperh);
867 __UNLOCK(hperh);
868
869 return OK;
870 }
871
878 ald_status_t ald_crypt_dma_stop(crypt_handle_t *hperh)
879 {
880 __LOCK(hperh);
881 CRYPT_DMA_DISABLE(hperh);
882 __UNLOCK(hperh);
883
884 hperh->state = CRYPT_STATE_READY;
885 return OK;
886 }
887 #endif
888
895 void ald_crypt_irq_handler(crypt_handle_t *hperh)
896 {
897 uint32_t i;
898 uint32_t *in_buf = (uint32_t *)hperh->cipher_text;
899 uint32_t *out_buf = (uint32_t *)hperh->plain_text;
900
901 if (READ_BIT(hperh->perh->CON, CRYPT_CON_ENCS_MSK) == (CRYPT_DECRYPT << CRYPT_CON_ENCS_POS)) {
902 in_buf = (uint32_t *)hperh->cipher_text + hperh->count;
903 out_buf = (uint32_t *)hperh->plain_text + hperh->count - hperh->step;
904 }
905 else {
906 in_buf = (uint32_t *)hperh->plain_text + hperh->count;
907 out_buf = (uint32_t *)hperh->cipher_text + hperh->count - hperh->step;
908 }
909
910 if (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_AESIF) == SET) {
911 ald_crypt_clear_flag_status(hperh, CRYPT_FLAG_AESIF);
912 }
913
914 if (ald_crypt_get_flag_status(hperh, CRYPT_FLAG_DESIF) == SET) {
915 ald_crypt_clear_flag_status(hperh, CRYPT_FLAG_DESIF);
916 }
917
918 for (i = 0; i < hperh->step; i++)
919 *out_buf++ = CRYPT_READ_FIFO(hperh);
920
921 hperh->count = hperh->count + hperh->step;
922 if (hperh->count > (hperh->size / 4)) {
923 hperh->count = 0;
924 hperh->state = CRYPT_STATE_READY;
925 hperh->crypt_cplt_cbk(hperh);
926 }
927 else {
928 for (i = 0; i < hperh->step; i++) {
929 CRYPT_WRITE_FIFO(hperh, *in_buf);
930 ++in_buf;
931 }
932 }
933 }
955 void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state)
956 {
957 assert_param(IS_CRYPT(hperh->perh));
958
959 if (it == CRYPT_IT_IT) {
960 CLEAR_BIT(CRYPT->CON, CRYPT_CON_IE_MSK);
961 CRYPT->CON |= (state << CRYPT_CON_IE_POS);
962 }
963
964 return;
965 }
966
976 flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag)
977 {
978 assert_param(IS_CRYPT(hperh->perh));
979 assert_param(IS_CRYPT_FLAG(flag));
980
981 if (CRYPT->IF & flag)
982 return SET;
983
984 return RESET;
985 }
986
997 void ald_crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag)
998 {
999 assert_param(IS_CRYPT(hperh->perh));
1000 assert_param(IS_CRYPT_FLAG(flag));
1001
1002 CRYPT->IFC = (uint32_t)flag;
1003 return;
1004 }
1005
1017 it_status_t ald_crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it)
1018 {
1019 assert_param(IS_CRYPT_IT(it));
1020
1021 if (READ_BIT(CRYPT->CON, CRYPT_CON_IE_MSK))
1022 return SET;
1023
1024 return RESET;
1025 }
1026
1027
1043 crypt_state_t ald_crypt_get_state(crypt_handle_t *hperh)
1044 {
1045 assert_param(IS_CRYPT(hperh->perh));
1046
1047 return hperh->state;
1048 }
1049
1069 void crypt_reset(crypt_handle_t *hperh)
1070 {
1071 hperh->perh->DATA[0] = 0x0;
1072 hperh->perh->DATA[1] = 0x0;
1073 hperh->perh->DATA[2] = 0x0;
1074 hperh->perh->DATA[3] = 0x0;
1075 hperh->perh->KEY[0] = 0x0;
1076 hperh->perh->KEY[1] = 0x0;
1077 hperh->perh->KEY[2] = 0x0;
1078 hperh->perh->KEY[3] = 0x0;
1079 hperh->perh->KEY[4] = 0x0;
1080 hperh->perh->KEY[5] = 0x0;
1081 hperh->perh->KEY[6] = 0x0;
1082 hperh->perh->KEY[7] = 0x0;
1083 hperh->perh->IV[0] = 0x0;
1084 hperh->perh->IV[1] = 0x0;
1085 hperh->perh->IV[2] = 0x0;
1086 hperh->perh->IV[3] = 0x0;
1087 hperh->perh->CON = 0x0;
1088
1089 hperh->state = CRYPT_STATE_READY;
1090 __UNLOCK(hperh);
1091 }
1092
1093 #ifdef ALD_DMA
1094
1100 static void crypt_dma_crypt_cplt(void *arg)
1101 {
1102 crypt_handle_t *hperh = (crypt_handle_t *)arg;
1103
1104 CRYPT_DMA_DISABLE(hperh);
1105 hperh->count = 0;
1106 hperh->plain_text = NULL;
1107 hperh->cipher_text = NULL;
1108 hperh->size = 0;
1109
1110 hperh->state = CRYPT_STATE_READY;
1111
1112 if (hperh->crypt_cplt_cbk)
1113 hperh->crypt_cplt_cbk(hperh);
1114 }
1115
1122 static void crypt_dma_error(void *arg)
1123 {
1124 crypt_handle_t *hperh = (crypt_handle_t *)arg;
1125 CRYPT_DMA_DISABLE(hperh);
1126
1127 hperh->count = 0;
1128 hperh->plain_text = NULL;
1129 hperh->cipher_text = NULL;
1130 hperh->size = 0;
1131
1132 hperh->state = CRYPT_STATE_READY;
1133
1134 if (hperh->err_cplt_cbk)
1135 hperh->err_cplt_cbk(hperh);
1136 }
1137 #endif
1138
1142 #endif /* ALD_CRYPT */
1143
IV_2_LEN
Definition: ald_crypt.h:144
CRYPT_ENCRYPT
Definition: ald_crypt.h:44
CRYPT_DES_KEYS_3
Definition: ald_crypt.h:117
IV_4_LEN
Definition: ald_crypt.h:145
crypt_init_t::key
crypt_ks_t key
Definition: ald_crypt.h:164
crypt_handle_s::step
uint32_t step
Definition: ald_crypt.h:181
KEY_6_LEN
Definition: ald_crypt.h:136
crypt_handle_s::iv_size
uint32_t iv_size
Definition: ald_crypt.h:184
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
crypt_handle_s::iv
uint32_t iv[4]
Definition: ald_crypt.h:183
ald_crypt_read_key
ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t *key, crypt_key_len_t len)
Read the Content of KEY.
Definition: ald_crypt.c:212
crypt_init_t::mode
crypt_mode_t mode
Definition: ald_crypt.h:162
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
crypt_handle_s::crypt_cplt_cbk
void(* crypt_cplt_cbk)(struct crypt_handle_s *arg)
Definition: ald_crypt.h:190
CRYPT_STATE_RESET
Definition: ald_crypt.h:124
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
CRYPT_BITS_128
Definition: ald_crypt.h:51
ald_crypt_encrypt_by_dma
ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m)
Encrypt an amount of data in non-blocking mode.
Definition: ald_crypt.c:683
SET
Definition: type.h:39
crypt_handle_s::err_cplt_cbk
void(* err_cplt_cbk)(struct crypt_handle_s *arg)
Definition: ald_crypt.h:191
ald_crypt_read_ivr
ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv, crypt_ivr_len_t len)
Read the Content of IV.
Definition: ald_crypt.c:319
crypt_handle_s::plain_text
uint8_t * plain_text
Definition: ald_crypt.h:177
CRYPT_KEYS_2
Definition: ald_crypt.h:79
type_func_t
type_func_t
Definition: type.h:47
crypt_dma_error
static void crypt_dma_error(void *arg)
DMA CRYPT communication error callback.
Definition: ald_crypt.c:1122
ald_crypt_encrypt
ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size)
Encrypt an amount of data in blocking mode.
Definition: ald_crypt.c:370
crypt_handle_s::state
crypt_state_t state
Definition: ald_crypt.h:188
crypt_handle_s::size
uint32_t size
Definition: ald_crypt.h:179
IS_CRYPT_IV_LEN
#define IS_CRYPT_IV_LEN(x)
Definition: ald_crypt.h:234
CRYPT_STATE_BUSY
Definition: ald_crypt.h:126
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
ald_crypt_write_ivr
ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv, crypt_ivr_len_t len)
Write the Content of IV if you use CBC mode.
Definition: ald_crypt.c:272
CRYPT_MODE_ECB
Definition: ald_crypt.h:60
ald_crypt_decrypt_by_dma
ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m)
Decrypt an amount of data in non-blocking mode.
Definition: ald_crypt.c:763
dma_config_t::src
void * src
Definition: ald_dma.h:278
CRYPT_FLAG_AESIF
Definition: ald_crypt.h:103
ald_crypt_encrypt_by_it
ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size)
Encrypt an amount of data in non-blocking mode.
Definition: ald_crypt.c:594
CRYPT_BITS_192
Definition: ald_crypt.h:52
DMA_DATA_INC_WORD
Definition: ald_dma.h:219
DMA_DATA_SIZE_WORD
Definition: ald_dma.h:229
crypt_reset
void crypt_reset(crypt_handle_t *hperh)
Reset the CRYPT peripheral.
Definition: ald_crypt.c:1069
CRYPT_FLAG_DONE
Definition: ald_crypt.h:105
ald_crypt_clear_flag_status
void ald_crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag)
Clear the specified CRYPT pending flags.
Definition: ald_crypt.c:997
CRYPT_STATE_ERROR
Definition: ald_crypt.h:127
RESET
Definition: type.h:38
ald_crypt_get_it_status
it_status_t ald_crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it)
Checks whether the specified CRYPT interrupt has occurred or not.
Definition: ald_crypt.c:1017
CRYPT_FLAG_DESIF
Definition: ald_crypt.h:104
ald_crypt_init
ald_status_t ald_crypt_init(crypt_handle_t *hperh)
Initializes the CRYPT mode according to the specified parameters in the crypt_init_t and create the a...
Definition: ald_crypt.c:61
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
ald_crypt_get_flag_status
flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag)
Check whether the specified CRYPT flag is set or not.
Definition: ald_crypt.c:976
IS_CRYPT_FLAG
#define IS_CRYPT_FLAG(x)
Definition: ald_crypt.h:231
crypt_handle_s::perh
CRYPT_TypeDef * perh
Definition: ald_crypt.h:171
IS_CRYPT
#define IS_CRYPT(x)
Definition: ald_crypt.h:220
CRYPT_DMA_DISABLE
#define CRYPT_DMA_DISABLE(handle)
Definition: ald_crypt.h:208
KEY_8_LEN
Definition: ald_crypt.h:137
crypt_flag_t
crypt_flag_t
CRYPT interrupt flag.
Definition: ald_crypt.h:102
crypt_state_t
crypt_state_t
CRYPT state structures definition.
Definition: ald_crypt.h:123
it_status_t
enum flag_status_t it_status_t
CRYPT_SETDIR
#define CRYPT_SETDIR(handle, dir)
Definition: ald_crypt.h:209
IS_CRYPT_KEY_LEN
#define IS_CRYPT_KEY_LEN(x)
Definition: ald_crypt.h:236
ald_crypt_dma_stop
ald_status_t ald_crypt_dma_stop(crypt_handle_t *hperh)
Stops the DMA Transfer.
Definition: ald_crypt.c:878
crypt_handle_s::hdma_m2p
dma_handle_t hdma_m2p
Definition: ald_crypt.h:174
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
crypt_handle_s::cipher_text
uint8_t * cipher_text
Definition: ald_crypt.h:178
CRYPT_IT_IT
Definition: ald_crypt.h:96
ald_crypt_interrupt_config
void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state)
Enables or disables the specified CRYPT interrupts.
Definition: ald_crypt.c:955
CRYPT_DECRYPT
Definition: ald_crypt.h:43
ald_crypt_dma_pause
ald_status_t ald_crypt_dma_pause(crypt_handle_t *hperh)
Pauses the DMA Transfer.
Definition: ald_crypt.c:847
KEY_4_LEN
Definition: ald_crypt.h:135
ald_crypt.h
Header file of CRYPT module driver.
crypt_handle_s::init
crypt_init_t init
Definition: ald_crypt.h:172
CRYPT_WRITE_FIFO
#define CRYPT_WRITE_FIFO(handle, data)
Definition: ald_crypt.h:211
CRYPT_STATE_READY
Definition: ald_crypt.h:125
CRYPT_AES_BITS_128
Definition: ald_crypt.h:112
CRYPT_AES_BITS_256
Definition: ald_crypt.h:114
CRYPT_READ_FIFO
#define CRYPT_READ_FIFO(handle)
Definition: ald_crypt.h:212
CRYPT_MODE_CTR
Definition: ald_crypt.h:62
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
crypt_it_t
crypt_it_t
CRYPT interrupt.
Definition: ald_crypt.h:95
crypt_dma_crypt_cplt
static void crypt_dma_crypt_cplt(void *arg)
DMA CRYPT encrypt or decrypt process complete callback.
Definition: ald_crypt.c:1100
crypt_handle_s::hdma_p2m
dma_handle_t hdma_p2m
Definition: ald_crypt.h:175
CRYPT_AES_BITS_192
Definition: ald_crypt.h:113
crypt_init_t::type
crypt_data_t type
Definition: ald_crypt.h:163
DMA_MSIGSEL_CRYPT_WRITE
Definition: ald_dma.h:132
crypt_ivr_len_t
crypt_ivr_len_t
CRYPT iv length.
Definition: ald_crypt.h:143
ald_crypt_write_key
ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t *key, crypt_key_len_t len)
Write the Content of KEY.
Definition: ald_crypt.c:143
IS_CRYPT_KS
#define IS_CRYPT_KS(x)
Definition: ald_crypt.h:224
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
crypt_handle_s::key
uint32_t key[8]
Definition: ald_crypt.h:185
ald_crypt_dma_resume
ald_status_t ald_crypt_dma_resume(crypt_handle_t *hperh)
Resumes the DMA Transfer.
Definition: ald_crypt.c:863
DMA_MSEL_CRYPT
Definition: ald_dma.h:80
CRYPT_KEYS_3
Definition: ald_crypt.h:80
CRYPT_CRYSEL_AES
Definition: ald_crypt.h:88
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
CRYPT_DMA_ENABLE
#define CRYPT_DMA_ENABLE(handle)
Definition: ald_crypt.h:207
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
IS_CRYPT_MODE
#define IS_CRYPT_MODE(x)
Definition: ald_crypt.h:221
gcm_mul
void gcm_mul(uint32_t *res, uint32_t *data, uint32_t *iv)
Definition: ald_crypt.c:460
ald_crypt_decrypt_by_it
ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size)
Decrypt an amount of data in non-blocking mode.
Definition: ald_crypt.c:635
KEY_2_LEN
Definition: ald_crypt.h:134
crypt_handle_s::count
uint32_t count
Definition: ald_crypt.h:180
CRYPT_BITS_256
Definition: ald_crypt.h:53
crypt_handle_s::key_size
uint32_t key_size
Definition: ald_crypt.h:186
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
flag_status_t
flag_status_t
Definition: type.h:37
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
ald_crypt_decrypt
ald_status_t ald_crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size)
Decrypt an amount of data in blocking mode.
Definition: ald_crypt.c:418
CRYPT_DES_KEYS_2
Definition: ald_crypt.h:116
ald_crypt_irq_handler
void ald_crypt_irq_handler(crypt_handle_t *hperh)
This function handles CRYPT interrupt request.
Definition: ald_crypt.c:895
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
IS_CRYPT_IT
#define IS_CRYPT_IT(x)
Definition: ald_crypt.h:230
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
crc_handle_s::state
crc_state_t state
Definition: ald_crc.h:101
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
DMA_MSIGSEL_CRYPT_READ
Definition: ald_dma.h:133
CRYPT_DES_KEYS_1
Definition: ald_crypt.h:115
CRYPT_IVEN_ENABLE
#define CRYPT_IVEN_ENABLE(handle)
Definition: ald_crypt.h:203
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_crypt_gcm_verify
ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag)
verify an amount of data in gcm mode.
Definition: ald_crypt.c:496
ald_crypt_get_state
crypt_state_t ald_crypt_get_state(crypt_handle_t *hperh)
Returns the CRYPT state.
Definition: ald_crypt.c:1043
crypt_handle_s
CRYPT Handle Structure definition.
Definition: ald_crypt.h:170
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
crypt_key_len_t
crypt_key_len_t
CRYPT key length.
Definition: ald_crypt.h:133


ALD User Manual: D:/svn/src/ald_crypt.h Source File

  • D:
  • svn
  • src
ald_crypt.h
Go to the documentation of this file.
1
17 #ifndef __ALD_CRYPT_H__
18 #define __ALD_CRYPT_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25 #include "ald_dma.h"
26
42 typedef enum {
43 CRYPT_DECRYPT = 0U,
44 CRYPT_ENCRYPT = 1U,
45 } crypt_encs_t;
46
50 typedef enum {
51 CRYPT_BITS_128 = 0U,
52 CRYPT_BITS_192 = 1U,
53 CRYPT_BITS_256 = 2U,
54 } crypt_aesks_t;
55
59 typedef enum {
60 CRYPT_MODE_ECB = 0U,
61 CRYPT_MODE_CBC = 1U,
62 CRYPT_MODE_CTR = 2U,
63 } crypt_mode_t;
64
68 typedef enum {
69 CRYPT_DATA_CHANGE_NO = 0U,
70 CRYPT_DATA_CHANGE_16 = 1U,
71 CRYPT_DATA_CHANGE_8 = 2U,
72 CRYPT_DATA_CHANGE_1 = 3U,
73 } crypt_datatype_t;
74
78 typedef enum {
79 CRYPT_KEYS_2 = 0U,
80 CRYPT_KEYS_3 = 1U,
81 CRYPT_KEYS_1 = 2U,
82 } crypt_desks_t;
83
87 typedef enum {
88 CRYPT_CRYSEL_AES = 0U,
89 CRYPT_CRYSEL_DES = 1U,
90 } crypt_crysel_t;
91
95 typedef enum {
96 CRYPT_IT_IT = 0x80U,
97 } crypt_it_t;
98
102 typedef enum {
103 CRYPT_FLAG_AESIF = 0x1U,
104 CRYPT_FLAG_DESIF = 0x2U,
105 CRYPT_FLAG_DONE = 0x100U,
106 } crypt_flag_t;
107
111 typedef enum {
112 CRYPT_AES_BITS_128 = 0x4U,
113 CRYPT_AES_BITS_192 = 0x6U,
114 CRYPT_AES_BITS_256 = 0x8U,
115 CRYPT_DES_KEYS_1 = 0x12U,
116 CRYPT_DES_KEYS_2 = 0x14U,
117 CRYPT_DES_KEYS_3 = 0x16U,
118 } crypt_ks_t;
119
123 typedef enum {
124 CRYPT_STATE_RESET = 0x0U,
125 CRYPT_STATE_READY = 0x1U,
126 CRYPT_STATE_BUSY = 0x2U,
127 CRYPT_STATE_ERROR = 0x4U,
128 } crypt_state_t;
129
133 typedef enum {
134 KEY_2_LEN = 2U,
135 KEY_4_LEN = 4U,
136 KEY_6_LEN = 6U,
137 KEY_8_LEN = 8U,
138 } crypt_key_len_t;
139
143 typedef enum {
144 IV_2_LEN = 2U,
145 IV_4_LEN = 4U,
146 } crypt_ivr_len_t;
147
151 typedef enum {
152 DATA_32_BIT = 0U,
153 DATA_16_BIT = 1U,
154 DATA_8_BIT = 2U,
155 DATA_1_BIT = 3U,
156 } crypt_data_t;
157
161 typedef struct {
162 crypt_mode_t mode;
163 crypt_data_t type;
164 crypt_ks_t key;
165 } crypt_init_t;
166
170 typedef struct crypt_handle_s {
171 CRYPT_TypeDef *perh;
172 crypt_init_t init;
173 #ifdef ALD_DMA
174 dma_handle_t hdma_m2p;
175 dma_handle_t hdma_p2m;
176 #endif
177 uint8_t *plain_text;
178 uint8_t *cipher_text;
179 uint32_t size;
180 uint32_t count;
181 uint32_t step;
182 uint32_t dir;
183 uint32_t iv[4];
184 uint32_t iv_size;
185 uint32_t key[8];
186 uint32_t key_size;
187 lock_state_t lock;
188 crypt_state_t state;
190 void (*crypt_cplt_cbk)(struct crypt_handle_s *arg);
191 void (*err_cplt_cbk)(struct crypt_handle_s *arg);
192 } crypt_handle_t;
200 #define CRYPT_GO(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK))
201 #define CRYPT_FIFOEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
202 #define CRYPT_FIFOEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
203 #define CRYPT_IVEN_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
204 #define CRYPT_IVEN_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
205 #define CRYPT_IE_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK))
206 #define CRYPT_IE_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK))
207 #define CRYPT_DMA_ENABLE(handle) (SET_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))
208 #define CRYPT_DMA_DISABLE(handle) (CLEAR_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))
209 #define CRYPT_SETDIR(handle, dir) do {(handle)->perh->CON &= ~(0x1 << CRYPT_CON_ENCS_POS); \
210 (handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0)
211 #define CRYPT_WRITE_FIFO(handle, data) ((handle)->perh->FIFO = (data))
212 #define CRYPT_READ_FIFO(handle) ((handle)->perh->FIFO)
213
220 #define IS_CRYPT(x) ((x) == CRYPT)
221 #define IS_CRYPT_MODE(x) (((x) == CRYPT_MODE_ECB) || \
222 ((x) == CRYPT_MODE_CBC) || \
223 ((x) == CRYPT_MODE_CTR))
224 #define IS_CRYPT_KS(x) (((x) == CRYPT_AES_BITS_128) || \
225 ((x) == CRYPT_AES_BITS_192) || \
226 ((x) == CRYPT_AES_BITS_256) || \
227 ((x) == CRYPT_DES_KEYS_1) || \
228 ((x) == CRYPT_DES_KEYS_2) || \
229 ((x) == CRYPT_DES_KEYS_3))
230 #define IS_CRYPT_IT(x) ((x) == CRYPT_IT_IT)
231 #define IS_CRYPT_FLAG(x) (((x) == CRYPT_FLAG_AESIF) || \
232 ((x) == CRYPT_FLAG_DESIF) || \
233 ((x) == CRYPT_FLAG_DONE))
234 #define IS_CRYPT_IV_LEN(x) (((x) == IV_2_LEN) || \
235 ((x) == IV_4_LEN))
236 #define IS_CRYPT_KEY_LEN(x) (((x) == KEY_2_LEN) || \
237 ((x) == KEY_4_LEN) || \
238 ((x) == KEY_6_LEN) || \
239 ((x) == KEY_8_LEN))
240
251 extern ald_status_t ald_crypt_init(crypt_handle_t *hperh);
252 extern ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t * key, crypt_key_len_t len);
253 extern ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t * key, crypt_key_len_t len);
254 extern ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t * iv, crypt_ivr_len_t len);
255 extern ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t * iv, crypt_ivr_len_t len);
263 extern ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t * plain_text, uint8_t * cipher_text, uint32_t size);
264 extern ald_status_t ald_crypt_decrypt(crypt_handle_t *hperh, uint8_t * cipher_text, uint8_t * plain_text, uint32_t size);
265 extern ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag);
266 extern ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size);
267 extern ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size);
268 #ifdef ALD_DMA
269 extern ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t * plain_text,
270 uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m);
271 extern ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t * cipher_text,
272 uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m);
273 #endif
274
281 #ifdef ALD_DMA
282 extern ald_status_t ald_crypt_dma_pause(crypt_handle_t *hperh);
283 extern ald_status_t ald_crypt_dma_resume(crypt_handle_t *hperh);
284 extern ald_status_t ald_crypt_dma_stop(crypt_handle_t *hperh);
285 #endif
286 extern void ald_crypt_irq_handler(crypt_handle_t *hperh);
294 extern void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state);
295 extern flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag);
296 extern void ald_crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag);
297 extern it_status_t ald_crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it);
305 extern crypt_state_t ald_crypt_get_state(crypt_handle_t *hperh);
322 #ifdef __cplusplus
323 }
324 #endif
325
326 #endif
IV_2_LEN
Definition: ald_crypt.h:144
CRYPT_ENCRYPT
Definition: ald_crypt.h:44
CRYPT_DES_KEYS_3
Definition: ald_crypt.h:117
IV_4_LEN
Definition: ald_crypt.h:145
crypt_init_t::key
crypt_ks_t key
Definition: ald_crypt.h:164
crypt_handle_s::step
uint32_t step
Definition: ald_crypt.h:181
KEY_6_LEN
Definition: ald_crypt.h:136
crypt_handle_s::iv_size
uint32_t iv_size
Definition: ald_crypt.h:184
CRYPT_MODE_CBC
Definition: ald_crypt.h:61
crypt_handle_s::iv
uint32_t iv[4]
Definition: ald_crypt.h:183
DATA_16_BIT
Definition: ald_crypt.h:153
ald_crypt_read_key
ald_status_t ald_crypt_read_key(crypt_handle_t *hperh, uint32_t *key, crypt_key_len_t len)
Read the Content of KEY.
Definition: ald_crypt.c:212
dma_handle_t
DMA handle structure definition.
Definition: ald_dma.h:297
crypt_init_t::mode
crypt_mode_t mode
Definition: ald_crypt.h:162
CRYPT_DATA_CHANGE_8
Definition: ald_crypt.h:71
crypt_mode_t
crypt_mode_t
CRYPT mode select.
Definition: ald_crypt.h:59
CRYPT_STATE_RESET
Definition: ald_crypt.h:124
CRYPT_BITS_128
Definition: ald_crypt.h:51
ald_crypt_encrypt_by_dma
ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m)
Encrypt an amount of data in non-blocking mode.
Definition: ald_crypt.c:683
crypt_ks_t
crypt_ks_t
CRYPT key select.
Definition: ald_crypt.h:111
ald_crypt_read_ivr
ald_status_t ald_crypt_read_ivr(crypt_handle_t *hperh, uint32_t *iv, crypt_ivr_len_t len)
Read the Content of IV.
Definition: ald_crypt.c:319
crypt_handle_s::plain_text
uint8_t * plain_text
Definition: ald_crypt.h:177
CRYPT_KEYS_2
Definition: ald_crypt.h:79
type_func_t
type_func_t
Definition: type.h:47
ald_crypt_encrypt
ald_status_t ald_crypt_encrypt(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size)
Encrypt an amount of data in blocking mode.
Definition: ald_crypt.c:370
crypt_handle_s::state
crypt_state_t state
Definition: ald_crypt.h:188
crypt_handle_s::size
uint32_t size
Definition: ald_crypt.h:179
CRYPT_STATE_BUSY
Definition: ald_crypt.h:126
CRYPT_DATA_CHANGE_NO
Definition: ald_crypt.h:69
ald_crypt_write_ivr
ald_status_t ald_crypt_write_ivr(crypt_handle_t *hperh, uint32_t *iv, crypt_ivr_len_t len)
Write the Content of IV if you use CBC mode.
Definition: ald_crypt.c:272
crypt_encs_t
crypt_encs_t
CRYPT encrypt or decrypt select.
Definition: ald_crypt.h:42
CRYPT_MODE_ECB
Definition: ald_crypt.h:60
ald_crypt_decrypt_by_dma
ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m)
Decrypt an amount of data in non-blocking mode.
Definition: ald_crypt.c:763
DATA_8_BIT
Definition: ald_crypt.h:154
CRYPT_FLAG_AESIF
Definition: ald_crypt.h:103
ald_crypt_encrypt_by_it
ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text, uint8_t *cipher_text, uint32_t size)
Encrypt an amount of data in non-blocking mode.
Definition: ald_crypt.c:594
crc_handle_s::err_cplt_cbk
void(* err_cplt_cbk)(struct crc_handle_s *arg)
Definition: ald_crc.h:104
CRYPT_BITS_192
Definition: ald_crypt.h:52
CRYPT_FLAG_DONE
Definition: ald_crypt.h:105
DATA_32_BIT
Definition: ald_crypt.h:152
crypt_desks_t
crypt_desks_t
CRYPT des key select.
Definition: ald_crypt.h:78
ald_crypt_clear_flag_status
void ald_crypt_clear_flag_status(crypt_handle_t *hperh, crypt_flag_t flag)
Clear the specified CRYPT pending flags.
Definition: ald_crypt.c:997
CRYPT_STATE_ERROR
Definition: ald_crypt.h:127
ald_crypt_get_it_status
it_status_t ald_crypt_get_it_status(crypt_handle_t *hperh, crypt_it_t it)
Checks whether the specified CRYPT interrupt has occurred or not.
Definition: ald_crypt.c:1017
CRYPT_FLAG_DESIF
Definition: ald_crypt.h:104
ald_crypt_init
ald_status_t ald_crypt_init(crypt_handle_t *hperh)
Initializes the CRYPT mode according to the specified parameters in the crypt_init_t and create the a...
Definition: ald_crypt.c:61
ald_crypt_get_flag_status
flag_status_t ald_crypt_get_flag_status(crypt_handle_t *hperh, crypt_flag_t flag)
Check whether the specified CRYPT flag is set or not.
Definition: ald_crypt.c:976
utils.h
This file contains the Utilities functions/types for the driver.
crypt_handle_s::perh
CRYPT_TypeDef * perh
Definition: ald_crypt.h:171
KEY_8_LEN
Definition: ald_crypt.h:137
CRYPT_DATA_CHANGE_1
Definition: ald_crypt.h:72
crypt_flag_t
crypt_flag_t
CRYPT interrupt flag.
Definition: ald_crypt.h:102
crypt_state_t
crypt_state_t
CRYPT state structures definition.
Definition: ald_crypt.h:123
it_status_t
enum flag_status_t it_status_t
crypt_aesks_t
crypt_aesks_t
CRYPT aes key select.
Definition: ald_crypt.h:50
crypt_crysel_t
crypt_crysel_t
CRYPT crypt select.
Definition: ald_crypt.h:87
ald_crypt_dma_stop
ald_status_t ald_crypt_dma_stop(crypt_handle_t *hperh)
Stops the DMA Transfer.
Definition: ald_crypt.c:878
crypt_handle_s::hdma_m2p
dma_handle_t hdma_m2p
Definition: ald_crypt.h:174
crypt_handle_s::cipher_text
uint8_t * cipher_text
Definition: ald_crypt.h:178
CRYPT_CRYSEL_DES
Definition: ald_crypt.h:89
CRYPT_IT_IT
Definition: ald_crypt.h:96
ald_crypt_interrupt_config
void ald_crypt_interrupt_config(crypt_handle_t *hperh, crypt_it_t it, type_func_t state)
Enables or disables the specified CRYPT interrupts.
Definition: ald_crypt.c:955
CRYPT_DECRYPT
Definition: ald_crypt.h:43
ald_crypt_dma_pause
ald_status_t ald_crypt_dma_pause(crypt_handle_t *hperh)
Pauses the DMA Transfer.
Definition: ald_crypt.c:847
KEY_4_LEN
Definition: ald_crypt.h:135
lock_state_t
lock_state_t
Definition: type.h:58
crypt_handle_s::init
crypt_init_t init
Definition: ald_crypt.h:172
CRYPT_STATE_READY
Definition: ald_crypt.h:125
CRYPT_AES_BITS_128
Definition: ald_crypt.h:112
ald_dma.h
DMA module Library.
CRYPT_AES_BITS_256
Definition: ald_crypt.h:114
CRYPT_MODE_CTR
Definition: ald_crypt.h:62
crypt_it_t
crypt_it_t
CRYPT interrupt.
Definition: ald_crypt.h:95
crypt_handle_s::hdma_p2m
dma_handle_t hdma_p2m
Definition: ald_crypt.h:175
CRYPT_AES_BITS_192
Definition: ald_crypt.h:113
crypt_handle_t
struct crypt_handle_s crypt_handle_t
CRYPT Handle Structure definition.
crypt_handle_s::dir
uint32_t dir
Definition: ald_crypt.h:182
crypt_init_t::type
crypt_data_t type
Definition: ald_crypt.h:163
crypt_ivr_len_t
crypt_ivr_len_t
CRYPT iv length.
Definition: ald_crypt.h:143
crypt_datatype_t
crypt_datatype_t
CRYPT data type.
Definition: ald_crypt.h:68
crypt_data_t
crypt_data_t
CRYPT data type.
Definition: ald_crypt.h:151
ald_crypt_write_key
ald_status_t ald_crypt_write_key(crypt_handle_t *hperh, uint32_t *key, crypt_key_len_t len)
Write the Content of KEY.
Definition: ald_crypt.c:143
crypt_handle_s::key
uint32_t key[8]
Definition: ald_crypt.h:185
ald_crypt_dma_resume
ald_status_t ald_crypt_dma_resume(crypt_handle_t *hperh)
Resumes the DMA Transfer.
Definition: ald_crypt.c:863
CRYPT_KEYS_3
Definition: ald_crypt.h:80
CRYPT_CRYSEL_AES
Definition: ald_crypt.h:88
ald_crypt_decrypt_by_it
ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size)
Decrypt an amount of data in non-blocking mode.
Definition: ald_crypt.c:635
KEY_2_LEN
Definition: ald_crypt.h:134
crypt_handle_s::count
uint32_t count
Definition: ald_crypt.h:180
CRYPT_BITS_256
Definition: ald_crypt.h:53
crypt_handle_s::key_size
uint32_t key_size
Definition: ald_crypt.h:186
flag_status_t
flag_status_t
Definition: type.h:37
ald_crypt_decrypt
ald_status_t ald_crypt_decrypt(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size)
Decrypt an amount of data in blocking mode.
Definition: ald_crypt.c:418
CRYPT_DES_KEYS_2
Definition: ald_crypt.h:116
ald_crypt_irq_handler
void ald_crypt_irq_handler(crypt_handle_t *hperh)
This function handles CRYPT interrupt request.
Definition: ald_crypt.c:895
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
crc_handle_s::state
crc_state_t state
Definition: ald_crc.h:101
DATA_1_BIT
Definition: ald_crypt.h:155
CRYPT_DATA_CHANGE_16
Definition: ald_crypt.h:70
crypt_handle_s::lock
lock_state_t lock
Definition: ald_crypt.h:187
CRYPT_KEYS_1
Definition: ald_crypt.h:81
CRYPT_DES_KEYS_1
Definition: ald_crypt.h:115
ald_crypt_gcm_verify
ald_status_t ald_crypt_gcm_verify(crypt_handle_t *hperh, uint8_t *cipher_text, uint32_t size, uint8_t *aadata, uint32_t alen, uint8_t *tag)
verify an amount of data in gcm mode.
Definition: ald_crypt.c:496
ald_crypt_get_state
crypt_state_t ald_crypt_get_state(crypt_handle_t *hperh)
Returns the CRYPT state.
Definition: ald_crypt.c:1043
crypt_handle_s
CRYPT Handle Structure definition.
Definition: ald_crypt.h:170
crypt_init_t
CRYPT init structure definition.
Definition: ald_crypt.h:161
crypt_key_len_t
crypt_key_len_t
CRYPT key length.
Definition: ald_crypt.h:133


ALD User Manual: D:/svn/src/ald_dac.c Source File

  • D:
  • svn
  • src
ald_dac.c
Go to the documentation of this file.
1
16 #include "ald_dac.h"
17
18
27 #ifdef ALD_DAC
28
38 ald_status_t ald_dac_reset(dac_handle_t *hperh)
39 {
40 assert_param(IS_DAC_TYPE(hperh->perh));
41
42 hperh->perh->CON = 0;
43 hperh->perh->CH0CTRL = 0;
44 hperh->perh->CH1CTRL = 0;
45 hperh->perh->IES = 0;
46 hperh->perh->IEC = 0xFF;
47 hperh->perh->IFC = 0xFF;
48 hperh->perh->CAL = 0;
49
50 return OK;
51 }
52
59 ald_status_t ald_dac_init(dac_handle_t *hperh)
60 {
61 uint32_t tmp;
62
63 assert_param(IS_DAC_TYPE(hperh->perh));
64 assert_param(IS_DAC_CONVERT_TYPE(hperh->init.conv_mode));
65 assert_param(IS_DAC_OUTPUT_TYPE(hperh->init.out_mode));
66 assert_param(IS_DAC_NEG_REFRESH_TYPE(hperh->init.n_ref));
67 assert_param(IS_DAC_POS_REFRESH_TYPE(hperh->init.p_ref));
68 assert_param(IS_DAC_REFRESH_TYPE(hperh->init.refresh));
69 assert_param(IS_DAC_PRESCALE_TYPE(hperh->init.div));
70 assert_param(IS_FUNC_STATE(hperh->init.ch0_reset));
71 assert_param(IS_FUNC_STATE(hperh->init.o_ctrl_pis));
72 assert_param(IS_FUNC_STATE(hperh->init.sine));
73 assert_param(IS_FUNC_STATE(hperh->init.diff));
74
75 __LOCK(hperh);
76 ald_dac_reset(hperh);
77 DAC_CH0_DISABLE();
78 DAC_CH1_DISABLE();
79
80 MODIFY_REG(ADC0->CCR, ADC_CCR_VREFEN_MSK, 1 << ADC_CCR_VREFEN_POS);
81
82 if (hperh->init.p_ref == DAC_POS_REF_VREEFP_BUF || hperh->init.p_ref == DAC_POS_REF_2V)
83 SET_BIT(ADC0->CCR, (ADC_CCR_IREFEN_MSK | ADC_CCR_VRBUFEN_MSK | ADC_CCR_VCMBUFEN_MSK));
84
85 MODIFY_REG(ADC0->CCR, ADC_CCR_VRNSEL_MSK, hperh->init.n_ref << ADC_CCR_VRNSEL_POS);
86 MODIFY_REG(ADC0->CCR, ADC_CCR_VRPSEL_MSK, hperh->init.p_ref << ADC_CCR_VRPSEL_POSS);
87
88 tmp = ((hperh->init.refresh << DAC_CON_RCYCLSEL_POSS) | (hperh->init.div << DAC_CON_PRES_POSS) |
89 (hperh->init.ch0_reset << DAC_CON_CH0PRESRST_POS) | ( hperh->init.o_ctrl_pis << DAC_CON_OUTENPIS_POS) |
90 (hperh->init.out_mode << DAC_CON_OUTMD_POSS) | (hperh->init.conv_mode << DAC_CON_CONVMD_POSS) |
91 (hperh->init.sine << DAC_CON_SINEMD_POS) | (hperh->init.diff << DAC_CON_DIFEN_POS));
92 hperh->perh->CON = tmp;
93
94 /* Automatic calibration */
95 SET_BIT(hperh->perh->CAL, DAC_CAL_SELF_CALEN_MSK);
96 for (tmp = 0; tmp < 1000; ++tmp);
97 CLEAR_BIT(hperh->perh->CAL, DAC_CAL_SELF_CALEN_MSK);
98
99 __UNLOCK(hperh);
100 return OK;
101 }
102
112 ald_status_t ald_dac_channel_config(dac_handle_t *hperh, dac_channel_config_t *config, dac_channel_t ch)
113 {
114 uint32_t tmp;
115
116 if ((hperh == NULL) || (config == NULL))
117 return ERROR;
118
119 assert_param(IS_DAC_TYPE(hperh->perh));
120 assert_param(IS_FUNC_STATE(config->enable));
121 assert_param(IS_DAC_TRIGGER_TYPE(config->trigger));
122 assert_param(IS_FUNC_STATE(config->refresh_en));
123 assert_param(IS_DAC_PISSEL_CH_TYPE(config->pis_ch));
124
125 __LOCK(hperh);
126 tmp = ((config->pis_ch << DAC_CH0CTRL_PISSEL_POSS) | (config->trigger << DAC_CH0CTRL_PISEN_POS) |
127 (config->refresh_en << DAC_CH0CTRL_RCYCLEN_POS) | (config->enable << DAC_CH0CTRL_EN_POS));
128
129 switch (ch) {
130 case DAC_CHANNEL_0:
131 hperh->perh->CH0CTRL = tmp;
132 break;
133
134 case DAC_CHANNEL_1:
135 hperh->perh->CH1CTRL = tmp;
136 break;
137
138 default:
139 break;
140 }
141
142 __UNLOCK(hperh);
143 return OK;
144 }
145
154 void ald_dac_output_set(dac_handle_t *hperh, dac_channel_t ch, uint32_t value)
155 {
156 assert_param(IS_DAC_TYPE(hperh->perh));
157 assert_param(IS_DAC_CHANNEL_TYPE(ch));
158
159 switch (ch) {
160 case DAC_CHANNEL_0:
161 hperh->perh->CH0DATA = value;
162 break;
163
164 case DAC_CHANNEL_1:
165 hperh->perh->CH1DATA = value;
166 break;
167
168 case DAC_CHANNEL_COMB:
169 hperh->perh->COMBDATA = value;
170 break;
171
172 default:
173 break;
174 }
175
176 return;
177 }
178
186 flag_status_t ald_dac_get_status(dac_handle_t *hperh, dac_status_t status)
187 {
188 assert_param(IS_DAC_TYPE(hperh->perh));
189 assert_param(IS_DAC_STATUS_TYPE(status));
190
191 return hperh->perh->STAT & status ? SET : RESET;
192 }
193
207 void ald_dac_interrupt_config(dac_handle_t *hperh, dac_it_t it, type_func_t state)
208 {
209 assert_param(IS_DAC_TYPE(hperh->perh));
210 assert_param(IS_DAC_INTERRUPT_TYPE(it));
211 assert_param(IS_FUNC_STATE(state));
212
213 if (state)
214 hperh->perh->IES |= it;
215 else
216 hperh->perh->IEC = it;
217
218 return;
219 }
220
230 it_status_t ald_dac_get_it_status(dac_handle_t *hperh, dac_it_t it)
231 {
232 assert_param(IS_DAC_TYPE(hperh->perh));
233 assert_param(IS_DAC_INTERRUPT_TYPE(it));
234
235 return hperh->perh->IEV & it ? SET : RESET;
236 }
237
245 flag_status_t ald_dac_get_flag_status(dac_handle_t *hperh, dac_flag_t flag)
246 {
247 assert_param(IS_DAC_TYPE(hperh->perh));
248 assert_param(IS_DAC_FLAG_TYPE(flag));
249
250 return hperh->perh->RIF & flag ? SET : RESET;
251 }
252
262 flag_status_t ald_dac_get_mask_flag_status(dac_handle_t *hperh, dac_flag_t flag)
263 {
264 assert_param(IS_DAC_TYPE(hperh->perh));
265 assert_param(IS_DAC_FLAG_TYPE(flag));
266
267 return hperh->perh->IFM & flag ? SET : RESET;
268 }
269
277 void ald_dac_clear_flag_status(dac_handle_t *hperh, dac_flag_t flag)
278 {
279 assert_param(IS_DAC_TYPE(hperh->perh));
280 assert_param(IS_DAC_FLAG_TYPE(flag));
281
282 hperh->perh->IFC = flag;
283 return;
284 }
285
292 void ald_dac_irq_handler(dac_handle_t *hperh)
293 {
294 if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH0)) {
295 ald_dac_clear_flag_status(hperh, DAC_FLAG_CH0);
296
297 if (hperh->cbk)
298 hperh->cbk(hperh, DAC_EVENT_CH0_CPLT);
299 }
300
301 if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH1)) {
302 ald_dac_clear_flag_status(hperh, DAC_FLAG_CH1);
303
304 if (hperh->cbk)
305 hperh->cbk(hperh, DAC_EVENT_CH1_CPLT);
306 }
307
308 if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH0_UF)) {
309 ald_dac_clear_flag_status(hperh, DAC_FLAG_CH0_UF);
310
311 if (hperh->cbk)
312 hperh->cbk(hperh, DAC_EVENT_CH0_UF);
313 }
314
315 if (ald_dac_get_mask_flag_status(hperh, DAC_FLAG_CH1_UF)) {
316 ald_dac_clear_flag_status(hperh, DAC_FLAG_CH1_UF);
317
318 if (hperh->cbk)
319 hperh->cbk(hperh, DAC_EVENT_CH1_UF);
320 }
321
322 return;
323 }
327 #endif /* ALD_DAC */
328
dac_init_t::conv_mode
dac_conv_mode_t conv_mode
Definition: ald_dac.h:166
DAC_CH0_DISABLE
#define DAC_CH0_DISABLE()
Definition: ald_dac.h:207
DAC_EVENT_CH0_UF
#define DAC_EVENT_CH0_UF
Definition: ald_dac.h:212
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
ald_dac.h
Header file of DAC Module library.
dac_init_t::n_ref
dac_neg_ref_t n_ref
Definition: ald_dac.h:174
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
ald_dac_clear_flag_status
void ald_dac_clear_flag_status(dac_handle_t *hperh, dac_flag_t flag)
Clear interrupt state flag.
Definition: ald_dac.c:277
assert_param
#define assert_param(x)
Definition: type.h:88
IS_DAC_FLAG_TYPE
#define IS_DAC_FLAG_TYPE(x)
Definition: ald_dac.h:254
SET
Definition: type.h:39
type_func_t
type_func_t
Definition: type.h:47
IS_DAC_NEG_REFRESH_TYPE
#define IS_DAC_NEG_REFRESH_TYPE(x)
Definition: ald_dac.h:229
crypt_handle_s::state
crypt_state_t state
Definition: ald_crypt.h:188
dac_flag_t
dac_flag_t
DAC interrupt flag type.
Definition: ald_dac.h:147
dac_init_t::refresh
dac_refresh_t refresh
Definition: ald_dac.h:168
DAC_CHANNEL_0
Definition: ald_dac.h:42
ald_dac_init
ald_status_t ald_dac_init(dac_handle_t *hperh)
Initializes the DAC peripheral.
Definition: ald_dac.c:59
IS_DAC_POS_REFRESH_TYPE
#define IS_DAC_POS_REFRESH_TYPE(x)
Definition: ald_dac.h:231
ald_dac_reset
ald_status_t ald_dac_reset(dac_handle_t *hperh)
Reset the dac mode.
Definition: ald_dac.c:38
dac_handle_s::perh
DAC_TypeDef * perh
Definition: ald_dac.h:192
IS_DAC_REFRESH_TYPE
#define IS_DAC_REFRESH_TYPE(x)
Definition: ald_dac.h:235
ald_dac_output_set
void ald_dac_output_set(dac_handle_t *hperh, dac_channel_t ch, uint32_t value)
Set dac channel output value.
Definition: ald_dac.c:154
DAC_FLAG_CH0
Definition: ald_dac.h:148
RESET
Definition: type.h:38
dac_channel_config_t
DAC channel initialize structure definition.
Definition: ald_dac.h:181
ald_dac_interrupt_config
void ald_dac_interrupt_config(dac_handle_t *hperh, dac_it_t it, type_func_t state)
Enable or disable the specified interrupt.
Definition: ald_dac.c:207
dac_handle_s
DAC handle Structure definition.
Definition: ald_dac.h:191
DAC_CHANNEL_COMB
Definition: ald_dac.h:44
IS_DAC_PRESCALE_TYPE
#define IS_DAC_PRESCALE_TYPE(x)
Definition: ald_dac.h:242
it_status_t
enum flag_status_t it_status_t
DAC_FLAG_CH0_UF
Definition: ald_dac.h:150
IS_DAC_CONVERT_TYPE
#define IS_DAC_CONVERT_TYPE(x)
Definition: ald_dac.h:222
dac_init_t::o_ctrl_pis
type_func_t o_ctrl_pis
Definition: ald_dac.h:171
ald_dac_channel_config
ald_status_t ald_dac_channel_config(dac_handle_t *hperh, dac_channel_config_t *config, dac_channel_t ch)
Configure dac channel.
Definition: ald_dac.c:112
IS_DAC_CHANNEL_TYPE
#define IS_DAC_CHANNEL_TYPE(x)
Definition: ald_dac.h:239
ald_dac_irq_handler
void ald_dac_irq_handler(dac_handle_t *hperh)
This function handles DAC event interrupt request.
Definition: ald_dac.c:292
ald_dac_get_mask_flag_status
flag_status_t ald_dac_get_mask_flag_status(dac_handle_t *hperh, dac_flag_t flag)
Get the status of interrupt flag and interupt source.
Definition: ald_dac.c:262
dac_init_t::ch0_reset
type_func_t ch0_reset
Definition: ald_dac.h:170
ald_dac_get_it_status
it_status_t ald_dac_get_it_status(dac_handle_t *hperh, dac_it_t it)
Get the status of DAC interrupt source.
Definition: ald_dac.c:230
DAC_FLAG_CH1_UF
Definition: ald_dac.h:151
DAC_EVENT_CH1_UF
#define DAC_EVENT_CH1_UF
Definition: ald_dac.h:213
dac_channel_config_t::trigger
dac_trigger_t trigger
Definition: ald_dac.h:183
ald_dac_get_flag_status
flag_status_t ald_dac_get_flag_status(dac_handle_t *hperh, dac_flag_t flag)
Checks whether the specified interrupt has occurred or not.
Definition: ald_dac.c:245
dac_it_t
dac_it_t
DAC interrupt type.
Definition: ald_dac.h:137
IS_DAC_PISSEL_CH_TYPE
#define IS_DAC_PISSEL_CH_TYPE(x)
Definition: ald_dac.h:258
dac_init_t::out_mode
dac_out_mode_t out_mode
Definition: ald_dac.h:167
IS_DAC_INTERRUPT_TYPE
#define IS_DAC_INTERRUPT_TYPE(x)
Definition: ald_dac.h:250
dac_handle_s::init
dac_init_t init
Definition: ald_dac.h:193
DAC_CHANNEL_1
Definition: ald_dac.h:43
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_DAC_OUTPUT_TYPE
#define IS_DAC_OUTPUT_TYPE(x)
Definition: ald_dac.h:225
DAC_POS_REF_VREEFP_BUF
Definition: ald_dac.h:99
IS_DAC_STATUS_TYPE
#define IS_DAC_STATUS_TYPE(x)
Definition: ald_dac.h:270
DAC_POS_REF_2V
Definition: ald_dac.h:97
dac_init_t::diff
type_func_t diff
Definition: ald_dac.h:173
flag_status_t
flag_status_t
Definition: type.h:37
dac_channel_t
dac_channel_t
DAC channel.
Definition: ald_dac.h:41
dac_init_t::p_ref
dac_pos_ref_t p_ref
Definition: ald_dac.h:175
DAC_FLAG_CH1
Definition: ald_dac.h:149
IS_DAC_TYPE
#define IS_DAC_TYPE(x)
Definition: ald_dac.h:221
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dac_channel_config_t::enable
type_func_t enable
Definition: ald_dac.h:182
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
dac_handle_s::cbk
void(* cbk)(struct dac_handle_s *arg, uint32_t event)
Definition: ald_dac.h:196
dac_init_t::sine
type_func_t sine
Definition: ald_dac.h:172
__LOCK
#define __LOCK(x)
Definition: utils.h:92
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
ERROR
Definition: utils.h:56
IS_DAC_TRIGGER_TYPE
#define IS_DAC_TRIGGER_TYPE(x)
Definition: ald_dac.h:272
dac_status_t
dac_status_t
DAC state flag.
Definition: ald_dac.h:157
DAC_CH1_DISABLE
#define DAC_CH1_DISABLE()
Definition: ald_dac.h:208
dac_channel_config_t::pis_ch
dac_pissel_t pis_ch
Definition: ald_dac.h:185
dac_channel_config_t::refresh_en
type_func_t refresh_en
Definition: ald_dac.h:184
dac_init_t::div
dac_prescale_div_t div
Definition: ald_dac.h:169
DAC_EVENT_CH0_CPLT
#define DAC_EVENT_CH0_CPLT
Definition: ald_dac.h:210
ald_dac_get_status
flag_status_t ald_dac_get_status(dac_handle_t *hperh, dac_status_t status)
Checks whether the specified DAC flag is set or not.
Definition: ald_dac.c:186
DAC_EVENT_CH1_CPLT
#define DAC_EVENT_CH1_CPLT
Definition: ald_dac.h:211


ALD User Manual: D:/svn/src/ald_dac.h Source File

  • D:
  • svn
  • src
ald_dac.h
Go to the documentation of this file.
1
16 #ifndef __ALD_DAC_H__
17 #define __ALD_DAC_H__
18
19 #ifdef __cplusplus
20 extern "C" {
21 #endif
22
23 #include "utils.h"
24 #include "ald_dma.h"
25 #include "ald_pis.h"
26
41 typedef enum {
42 DAC_CHANNEL_0 = 1U,
43 DAC_CHANNEL_1 = 2U,
44 DAC_CHANNEL_COMB = 3U,
45 } dac_channel_t;
46
50 typedef enum {
51 DAC_CONV_MODE_CONTINUOUS = 0U,
52 DAC_CONV_MODE_SAMPLEHOLD = 1U,
53 DAC_CONV_MODE_SAMPLEOFF = 2U,
54 } dac_conv_mode_t;
55
59 typedef enum {
60 DAC_OUTPUT_DISABLE = 0U,
61 DAC_OUTPUT_PIN = 1U,
62 DAC_OUTPUT_ADC = 2U,
63 DAC_OUTPUT_PIN_ADC = 3U,
64 } dac_out_mode_t;
65
69 typedef enum {
70 DAC_PIS_CH_0 = 0U,
71 DAC_PIS_CH_1 = 1U,
72 DAC_PIS_CH_2 = 2U,
73 DAC_PIS_CH_3 = 3U,
74 DAC_PIS_CH_4 = 4U,
75 DAC_PIS_CH_5 = 5U,
76 DAC_PIS_CH_6 = 6U,
77 DAC_PIS_CH_7 = 7U,
78 DAC_PIS_CH_8 = 8U,
79 DAC_PIS_CH_9 = 9U,
80 DAC_PIS_CH_10 = 10U,
81 DAC_PIS_CH_11 = 11U,
82 } dac_pissel_t;
83
87 typedef enum {
88 DAC_NEG_REF_VSS = 0x0U,
89 DAC_NEG_REF_VREFN = 0x1U,
90 } dac_neg_ref_t;
91
95 typedef enum {
96 DAC_POS_REF_VDD = 0x0U,
97 DAC_POS_REF_2V = 0x1U,
98 DAC_POS_REF_VREEFP = 0x2U,
99 DAC_POS_REF_VREEFP_BUF = 0x3U,
100 } dac_pos_ref_t;
101
105 typedef enum {
106 DAC_REFRESH_8 = 0U,
107 DAC_REFRESH_16 = 1U,
108 DAC_REFRESH_32 = 2U,
109 DAC_REFRESH_64 = 3U,
110 } dac_refresh_t;
111
115 typedef enum {
116 DAC_PRES_DIV_1 = 0U,
117 DAC_PRES_DIV_2 = 1U,
118 DAC_PRES_DIV_4 = 2U,
119 DAC_PRES_DIV_8 = 3U,
120 DAC_PRES_DIV_16 = 4U,
121 DAC_PRES_DIV_32 = 5U,
122 DAC_PRES_DIV_64 = 6U,
123 DAC_PRES_DIV_128 = 7U,
124 } dac_prescale_div_t;
125
129 typedef enum {
130 DAC_TRIGGER_BY_DATA = 0U,
131 DAC_TRIGGER_BY_PIS = 1U,
132 } dac_trigger_t;
133
137 typedef enum {
138 DAC_IT_CH0 = (1U << 0),
139 DAC_IT_CH1 = (1U << 1),
140 DAC_IT_CH0_UF = (1U << 4),
141 DAC_IT_CH1_UF = (1U << 5),
142 } dac_it_t;
143
147 typedef enum {
148 DAC_FLAG_CH0 = (1U << 0),
149 DAC_FLAG_CH1 = (1U << 1),
150 DAC_FLAG_CH0_UF = (1U << 4),
151 DAC_FLAG_CH1_UF = (1U << 5),
152 } dac_flag_t;
153
157 typedef enum {
158 DAC_CH0_BSY = (1U << 0),
159 DAC_CH1_BSY = (1U << 1),
160 } dac_status_t;
161
165 typedef struct {
166 dac_conv_mode_t conv_mode;
167 dac_out_mode_t out_mode;
168 dac_refresh_t refresh;
169 dac_prescale_div_t div;
170 type_func_t ch0_reset;
171 type_func_t o_ctrl_pis;
172 type_func_t sine;
173 type_func_t diff;
174 dac_neg_ref_t n_ref;
175 dac_pos_ref_t p_ref;
176 } dac_init_t;
177
181 typedef struct {
182 type_func_t enable;
183 dac_trigger_t trigger;
184 type_func_t refresh_en;
185 dac_pissel_t pis_ch;
186 } dac_channel_config_t;
187
191 typedef struct dac_handle_s {
192 DAC_TypeDef *perh;
193 dac_init_t init;
194 lock_state_t lock;
196 void (*cbk)(struct dac_handle_s *arg, uint32_t event);
197 } dac_handle_t;
205 #define DAC_CH0_ENABLE() (SET_BIT(DAC0->CH0CTRL, DAC_CH0CTRL_EN_MSK))
206 #define DAC_CH1_ENABLE() (SET_BIT(DAC0->CH1CTRL, DAC_CH1CTRL_EN_MSK))
207 #define DAC_CH0_DISABLE() (CLEAR_BIT(DAC0->CH0CTRL, DAC_CH0CTRL_EN_MSK))
208 #define DAC_CH1_DISABLE() (CLEAR_BIT(DAC0->CH1CTRL, DAC_CH1CTRL_EN_MSK))
209
210 #define DAC_EVENT_CH0_CPLT 0x0
211 #define DAC_EVENT_CH1_CPLT 0x1
212 #define DAC_EVENT_CH0_UF 0x2
213 #define DAC_EVENT_CH1_UF 0x3
214
221 #define IS_DAC_TYPE(x) ((x) == DAC0)
222 #define IS_DAC_CONVERT_TYPE(x) (((x) == DAC_CONV_MODE_CONTINUOUS) || \
223 ((x) == DAC_CONV_MODE_SAMPLEHOLD) || \
224 ((x) == DAC_CONV_MODE_SAMPLEOFF))
225 #define IS_DAC_OUTPUT_TYPE(x) (((x) == DAC_OUTPUT_DISABLE) || \
226 ((x) == DAC_OUTPUT_PIN) || \
227 ((x) == DAC_OUTPUT_ADC) || \
228 ((x) == DAC_OUTPUT_PIN_ADC))
229 #define IS_DAC_NEG_REFRESH_TYPE(x) (((x) == DAC_NEG_REF_VSS) || \
230 ((x) == DAC_NEG_REF_VREFN))
231 #define IS_DAC_POS_REFRESH_TYPE(x) (((x) == DAC_POS_REF_VDD) || \
232 ((x) == DAC_POS_REF_2V) || \
233 ((x) == DAC_POS_REF_VREEFP) || \
234 ((x) == DAC_POS_REF_VREEFP_BUF))
235 #define IS_DAC_REFRESH_TYPE(x) (((x) == DAC_REFRESH_8) || \
236 ((x) == DAC_REFRESH_16) || \
237 ((x) == DAC_REFRESH_32) || \
238 ((x) == DAC_REFRESH_64))
239 #define IS_DAC_CHANNEL_TYPE(x) (((x) == DAC_CHANNEL_0) || \
240 ((x) == DAC_CHANNEL_1) || \
241 ((x) == DAC_CHANNEL_COMB))
242 #define IS_DAC_PRESCALE_TYPE(x) (((x) == DAC_PRES_DIV_1) || \
243 ((x) == DAC_PRES_DIV_2) || \
244 ((x) == DAC_PRES_DIV_4) || \
245 ((x) == DAC_PRES_DIV_8) || \
246 ((x) == DAC_PRES_DIV_16) || \
247 ((x) == DAC_PRES_DIV_32) || \
248 ((x) == DAC_PRES_DIV_64) || \
249 ((x) == DAC_PRES_DIV_128))
250 #define IS_DAC_INTERRUPT_TYPE(x) (((x) == DAC_IT_CH0) || \
251 ((x) == DAC_IT_CH1) || \
252 ((x) == DAC_IT_CH0_UF) || \
253 ((x) == DAC_IT_CH1_UF))
254 #define IS_DAC_FLAG_TYPE(x) (((x) == DAC_FLAG_CH0) || \
255 ((x) == DAC_FLAG_CH1) || \
256 ((x) == DAC_FLAG_CH0_UF) || \
257 ((x) == DAC_FLAG_CH1_UF))
258 #define IS_DAC_PISSEL_CH_TYPE(x) (((x) == DAC_PIS_CH_0) || \
259 ((x) == DAC_PIS_CH_1) || \
260 ((x) == DAC_PIS_CH_2) || \
261 ((x) == DAC_PIS_CH_3) || \
262 ((x) == DAC_PIS_CH_4) || \
263 ((x) == DAC_PIS_CH_5) || \
264 ((x) == DAC_PIS_CH_6) || \
265 ((x) == DAC_PIS_CH_7) || \
266 ((x) == DAC_PIS_CH_8) || \
267 ((x) == DAC_PIS_CH_9) || \
268 ((x) == DAC_PIS_CH_10) || \
269 ((x) == DAC_PIS_CH_11))
270 #define IS_DAC_STATUS_TYPE(x) (((x) == DAC_CH0_BSY) || \
271 ((x) == DAC_CH1_BSY))
272 #define IS_DAC_TRIGGER_TYPE(x) (((x) == DAC_TRIGGER_BY_DATA) || \
273 ((x) == DAC_TRIGGER_BY_PIS))
274
281 ald_status_t ald_dac_reset(dac_handle_t *hperh);
282 ald_status_t ald_dac_init(dac_handle_t *hperh);
283 ald_status_t ald_dac_channel_config(dac_handle_t *hperh, dac_channel_config_t *config, dac_channel_t ch);
284 void ald_dac_output_set(dac_handle_t *hperh, dac_channel_t ch, uint32_t value);
285 flag_status_t ald_dac_get_status(dac_handle_t *hperh, dac_status_t status);
286 void ald_dac_interrupt_config(dac_handle_t *hperh, dac_it_t it, type_func_t state);
287 it_status_t ald_dac_get_it_status(dac_handle_t *hperh, dac_it_t it);
288 flag_status_t ald_dac_get_flag_status(dac_handle_t *hperh, dac_flag_t flag);
289 flag_status_t ald_dac_get_mask_flag_status(dac_handle_t *hperh, dac_flag_t flag);
290 void ald_dac_clear_flag_status(dac_handle_t *hperh, dac_flag_t flag);
291 void ald_dac_irq_handler(dac_handle_t *hperh);
303 #ifdef __cplusplus
304 extern "C" }
305 #endif
306
307 #endif /* __ALD_DAC_H */
DAC_REFRESH_8
Definition: ald_dac.h:106
dac_init_t::conv_mode
dac_conv_mode_t conv_mode
Definition: ald_dac.h:166
DAC_REFRESH_16
Definition: ald_dac.h:107
DAC_PRES_DIV_8
Definition: ald_dac.h:119
DAC_PRES_DIV_32
Definition: ald_dac.h:121
dac_conv_mode_t
dac_conv_mode_t
DAC convert mode.
Definition: ald_dac.h:50
dac_refresh_t
dac_refresh_t
Refresh interval select.
Definition: ald_dac.h:105
DAC_IT_CH1
Definition: ald_dac.h:139
dac_init_t::n_ref
dac_neg_ref_t n_ref
Definition: ald_dac.h:174
ald_dac_clear_flag_status
void ald_dac_clear_flag_status(dac_handle_t *hperh, dac_flag_t flag)
Clear interrupt state flag.
Definition: ald_dac.c:277
DAC_NEG_REF_VREFN
Definition: ald_dac.h:89
DAC_PRES_DIV_4
Definition: ald_dac.h:118
DAC_CONV_MODE_SAMPLEOFF
Definition: ald_dac.h:53
type_func_t
type_func_t
Definition: type.h:47
crypt_handle_s::state
crypt_state_t state
Definition: ald_crypt.h:188
dac_flag_t
dac_flag_t
DAC interrupt flag type.
Definition: ald_dac.h:147
DAC_CONV_MODE_CONTINUOUS
Definition: ald_dac.h:51
dac_init_t::refresh
dac_refresh_t refresh
Definition: ald_dac.h:168
dac_handle_t
struct dac_handle_s dac_handle_t
DAC handle Structure definition.
DAC_CHANNEL_0
Definition: ald_dac.h:42
DAC_IT_CH1_UF
Definition: ald_dac.h:141
DAC_PIS_CH_9
Definition: ald_dac.h:79
DAC_POS_REF_VREEFP
Definition: ald_dac.h:98
ald_dac_init
ald_status_t ald_dac_init(dac_handle_t *hperh)
Initializes the DAC peripheral.
Definition: ald_dac.c:59
DAC_PRES_DIV_2
Definition: ald_dac.h:117
ald_dac_reset
ald_status_t ald_dac_reset(dac_handle_t *hperh)
Reset the dac mode.
Definition: ald_dac.c:38
dac_handle_s::perh
DAC_TypeDef * perh
Definition: ald_dac.h:192
DAC_REFRESH_64
Definition: ald_dac.h:109
dac_pos_ref_t
dac_pos_ref_t
DAC positive reference voltage definition.
Definition: ald_dac.h:95
ald_dac_output_set
void ald_dac_output_set(dac_handle_t *hperh, dac_channel_t ch, uint32_t value)
Set dac channel output value.
Definition: ald_dac.c:154
DAC_FLAG_CH0
Definition: ald_dac.h:148
DAC_PIS_CH_11
Definition: ald_dac.h:81
dac_channel_config_t
DAC channel initialize structure definition.
Definition: ald_dac.h:181
ald_dac_interrupt_config
void ald_dac_interrupt_config(dac_handle_t *hperh, dac_it_t it, type_func_t state)
Enable or disable the specified interrupt.
Definition: ald_dac.c:207
DAC_PIS_CH_0
Definition: ald_dac.h:70
utils.h
This file contains the Utilities functions/types for the driver.
dac_handle_s
DAC handle Structure definition.
Definition: ald_dac.h:191
DAC_PRES_DIV_64
Definition: ald_dac.h:122
DAC_CHANNEL_COMB
Definition: ald_dac.h:44
DAC_PIS_CH_6
Definition: ald_dac.h:76
it_status_t
enum flag_status_t it_status_t
DAC_OUTPUT_ADC
Definition: ald_dac.h:62
DAC_POS_REF_VDD
Definition: ald_dac.h:96
DAC_FLAG_CH0_UF
Definition: ald_dac.h:150
dac_init_t::o_ctrl_pis
type_func_t o_ctrl_pis
Definition: ald_dac.h:171
ald_dac_channel_config
ald_status_t ald_dac_channel_config(dac_handle_t *hperh, dac_channel_config_t *config, dac_channel_t ch)
Configure dac channel.
Definition: ald_dac.c:112
ald_dac_irq_handler
void ald_dac_irq_handler(dac_handle_t *hperh)
This function handles DAC event interrupt request.
Definition: ald_dac.c:292
ald_dac_get_mask_flag_status
flag_status_t ald_dac_get_mask_flag_status(dac_handle_t *hperh, dac_flag_t flag)
Get the status of interrupt flag and interupt source.
Definition: ald_dac.c:262
dac_init_t::ch0_reset
type_func_t ch0_reset
Definition: ald_dac.h:170
ald_dac_get_it_status
it_status_t ald_dac_get_it_status(dac_handle_t *hperh, dac_it_t it)
Get the status of DAC interrupt source.
Definition: ald_dac.c:230
DAC_CONV_MODE_SAMPLEHOLD
Definition: ald_dac.h:52
DAC_FLAG_CH1_UF
Definition: ald_dac.h:151
DAC_PIS_CH_3
Definition: ald_dac.h:73
dac_trigger_t
dac_trigger_t
DAC output trigger select.
Definition: ald_dac.h:129
lock_state_t
lock_state_t
Definition: type.h:58
ald_dma.h
DMA module Library.
dac_channel_config_t::trigger
dac_trigger_t trigger
Definition: ald_dac.h:183
ald_pis.h
Header file of PIS driver.
ald_dac_get_flag_status
flag_status_t ald_dac_get_flag_status(dac_handle_t *hperh, dac_flag_t flag)
Checks whether the specified interrupt has occurred or not.
Definition: ald_dac.c:245
DAC_PRES_DIV_1
Definition: ald_dac.h:116
dac_it_t
dac_it_t
DAC interrupt type.
Definition: ald_dac.h:137
dac_init_t::out_mode
dac_out_mode_t out_mode
Definition: ald_dac.h:167
DAC_PIS_CH_10
Definition: ald_dac.h:80
dac_prescale_div_t
dac_prescale_div_t
DAC prescale.
Definition: ald_dac.h:115
dac_handle_s::init
dac_init_t init
Definition: ald_dac.h:193
DAC_IT_CH0
Definition: ald_dac.h:138
dac_pissel_t
dac_pissel_t
DAC pis input channel.
Definition: ald_dac.h:69
DAC_PIS_CH_7
Definition: ald_dac.h:77
DAC_CH0_BSY
Definition: ald_dac.h:158
dac_neg_ref_t
dac_neg_ref_t
DAC negative reference voltage definition.
Definition: ald_dac.h:87
DAC_CHANNEL_1
Definition: ald_dac.h:43
DAC_REFRESH_32
Definition: ald_dac.h:108
DAC_OUTPUT_PIN
Definition: ald_dac.h:61
DAC_IT_CH0_UF
Definition: ald_dac.h:140
dac_handle_s::lock
lock_state_t lock
Definition: ald_dac.h:194
DAC_POS_REF_VREEFP_BUF
Definition: ald_dac.h:99
DAC_POS_REF_2V
Definition: ald_dac.h:97
dac_init_t::diff
type_func_t diff
Definition: ald_dac.h:173
flag_status_t
flag_status_t
Definition: type.h:37
dac_channel_t
dac_channel_t
DAC channel.
Definition: ald_dac.h:41
dac_init_t::p_ref
dac_pos_ref_t p_ref
Definition: ald_dac.h:175
DAC_FLAG_CH1
Definition: ald_dac.h:149
DAC_PIS_CH_2
Definition: ald_dac.h:72
dac_init_t
DAC init structure definition.
Definition: ald_dac.h:165
DAC_PIS_CH_8
Definition: ald_dac.h:78
DAC_CH1_BSY
Definition: ald_dac.h:159
dac_channel_config_t::enable
type_func_t enable
Definition: ald_dac.h:182
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
dac_out_mode_t
dac_out_mode_t
DAC out mode.
Definition: ald_dac.h:59
dac_init_t::sine
type_func_t sine
Definition: ald_dac.h:172
DAC_TRIGGER_BY_DATA
Definition: ald_dac.h:130
DAC_PRES_DIV_128
Definition: ald_dac.h:123
DAC_PIS_CH_4
Definition: ald_dac.h:74
DAC_PRES_DIV_16
Definition: ald_dac.h:120
DAC_PIS_CH_1
Definition: ald_dac.h:71
DAC_TRIGGER_BY_PIS
Definition: ald_dac.h:131
DAC_NEG_REF_VSS
Definition: ald_dac.h:88
dac_status_t
dac_status_t
DAC state flag.
Definition: ald_dac.h:157
dac_channel_config_t::pis_ch
dac_pissel_t pis_ch
Definition: ald_dac.h:185
DAC_OUTPUT_DISABLE
Definition: ald_dac.h:60
dac_channel_config_t::refresh_en
type_func_t refresh_en
Definition: ald_dac.h:184
dac_init_t::div
dac_prescale_div_t div
Definition: ald_dac.h:169
DAC_PIS_CH_5
Definition: ald_dac.h:75
DAC_OUTPUT_PIN_ADC
Definition: ald_dac.h:63
ald_dac_get_status
flag_status_t ald_dac_get_status(dac_handle_t *hperh, dac_status_t status)
Checks whether the specified DAC flag is set or not.
Definition: ald_dac.c:186


ALD User Manual: D:/svn/src/ald_dbgc.h Source File

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  • svn
  • src
ald_dbgc.h
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1
17 #ifndef __ALD_DBGC_H__
18 #define __ALD_DBGC_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25
26
44 typedef enum {
45 DEBC_MODE_SLEEP = (1U << 0),
46 DEBC_MODE_STOP1 = (1U << 1),
47 DEBC_MODE_STOP2 = (1U << 2),
48 DEBC_MODE_STANDBY = (1U << 3),
49 } dbgc_mode_t;
50
54 typedef enum {
55 DEBC_PERH_TIMER0 = (1U << 0),
56 DEBC_PERH_TIMER1 = (1U << 1),
57 DEBC_PERH_TIMER2 = (1U << 2),
58 DEBC_PERH_TIMER3 = (1U << 3),
59 DEBC_PERH_TIMER4 = (1U << 4),
60 DEBC_PERH_TIMER5 = (1U << 5),
61 DEBC_PERH_TIMER6 = (1U << 6),
62 DEBC_PERH_TIMER7 = (1U << 7),
63 DEBC_PERH_I2C0 = (1U << 8),
64 DEBC_PERH_I2C1 = (1U << 9),
65 DEBC_PERH_CAN = (1U << 12),
66 DEBC_PERH_LPTIM0 = (1U << 0) | (1U << 16),
67 DEBC_PERH_IWDT = (1U << 8) | (1U << 16),
68 DEBC_PERH_WWDT = (1U << 9) | (1U << 16),
69 DEBC_PERH_RTC = (1U << 10) | (1U << 16),
70 } dbgc_perh_t;
82 __INLINE uint32_t ald_dbgc_get_rev_id(void)
83 {
84 return (DBGC->IDCODE >> 16);
85 }
86
91 __INLINE uint32_t ald_dbgc_get_core_id(void)
92 {
93 return (DBGC->IDCODE >> 12) & 0xF;
94 }
95
100 __INLINE uint32_t ald_dbgc_get_device_id(void)
101 {
102 return DBGC->IDCODE & 0xFFF;
103 }
104
111 __INLINE void ald_dbgc_mode_config(dbgc_mode_t mode, type_func_t state)
112 {
113 if (state)
114 SET_BIT(DBGC->CR, mode);
115 else
116 CLEAR_BIT(DBGC->CR, mode);
117 }
118
125 __INLINE void ald_dbgc_perh_config(dbgc_perh_t perh, type_func_t state)
126 {
127 if ((perh >> 16) & 0x1) {
128 if (state)
129 SET_BIT(DBGC->APB2FZ, perh);
130 else
131 CLEAR_BIT(DBGC->APB2FZ, perh);
132 }
133 else {
134 if (state)
135 SET_BIT(DBGC->APB1FZ, perh);
136 else
137 CLEAR_BIT(DBGC->APB1FZ, perh);
138 }
139 }
152 #ifdef __cplusplus
153 }
154 #endif
155
156 #endif
DEBC_PERH_RTC
Definition: ald_dbgc.h:69
ald_dbgc_get_core_id
__INLINE uint32_t ald_dbgc_get_core_id(void)
Gets core id.
Definition: ald_dbgc.h:91
DEBC_MODE_SLEEP
Definition: ald_dbgc.h:45
DEBC_MODE_STOP1
Definition: ald_dbgc.h:46
DEBC_PERH_TIMER2
Definition: ald_dbgc.h:57
DEBC_PERH_IWDT
Definition: ald_dbgc.h:67
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
DEBC_PERH_WWDT
Definition: ald_dbgc.h:68
DEBC_PERH_TIMER6
Definition: ald_dbgc.h:61
type_func_t
type_func_t
Definition: type.h:47
DEBC_PERH_I2C0
Definition: ald_dbgc.h:63
DEBC_PERH_TIMER4
Definition: ald_dbgc.h:59
dac_handle_s::perh
DAC_TypeDef * perh
Definition: ald_dac.h:192
DEBC_PERH_I2C1
Definition: ald_dbgc.h:64
utils.h
This file contains the Utilities functions/types for the driver.
dbgc_perh_t
dbgc_perh_t
Debug peripheral select.
Definition: ald_dbgc.h:54
ald_dbgc_perh_config
__INLINE void ald_dbgc_perh_config(dbgc_perh_t perh, type_func_t state)
Configures peripheral debug mode.
Definition: ald_dbgc.h:125
DEBC_PERH_CAN
Definition: ald_dbgc.h:65
dbgc_mode_t
dbgc_mode_t
Debug mode select.
Definition: ald_dbgc.h:44
DEBC_PERH_TIMER0
Definition: ald_dbgc.h:55
DEBC_PERH_TIMER1
Definition: ald_dbgc.h:56
DEBC_PERH_TIMER3
Definition: ald_dbgc.h:58
DEBC_PERH_TIMER7
Definition: ald_dbgc.h:62
ald_dbgc_mode_config
__INLINE void ald_dbgc_mode_config(dbgc_mode_t mode, type_func_t state)
Configures low power debug mode.
Definition: ald_dbgc.h:111
ald_dbgc_get_rev_id
__INLINE uint32_t ald_dbgc_get_rev_id(void)
Gets version.
Definition: ald_dbgc.h:82
DEBC_MODE_STANDBY
Definition: ald_dbgc.h:48
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
ald_dbgc_get_device_id
__INLINE uint32_t ald_dbgc_get_device_id(void)
Gets device id.
Definition: ald_dbgc.h:100
DEBC_PERH_TIMER5
Definition: ald_dbgc.h:60
DEBC_MODE_STOP2
Definition: ald_dbgc.h:47
DEBC_PERH_LPTIM0
Definition: ald_dbgc.h:66


ALD User Manual: D:/svn/src/ald_dma.c Source File

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  • svn
  • src
ald_dma.c
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1
58 #include <string.h>
59 #include "ald_conf.h"
60 #include "ald_dma.h"
61
62
72 #ifdef ALD_DMA
73
76 dma_descriptor_t dma0_ctrl_base[28] __attribute__ ((aligned(512)));
77 dma_call_back_t dma0_cbk[12];
94 static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config_t *p)
95 {
96 dma_descriptor_t *descr;
97
98 assert_param(IS_DMA(DMAx));
99 assert_param(IS_CYCLECTRL_TYPE(mode));
100 assert_param(p->src != NULL);
101 assert_param(p->dst != NULL);
102 assert_param(IS_DMA_DATA_SIZE(p->size));
103 assert_param(IS_DMA_DATASIZE_TYPE(p->data_width));
104 assert_param(IS_DMA_DATAINC_TYPE(p->src_inc));
105 assert_param(IS_DMA_DATAINC_TYPE(p->dst_inc));
106 assert_param(IS_DMA_ARBITERCONFIG_TYPE(p->R_power));
107 assert_param(IS_FUNC_STATE(p->primary));
108 assert_param(IS_FUNC_STATE(p->burst));
109 assert_param(IS_FUNC_STATE(p->high_prio));
110 assert_param(IS_FUNC_STATE(p->interrupt));
111 assert_param(IS_DMA_MSEL_TYPE(p->msel));
112 assert_param(IS_DMA_MSIGSEL_TYPE(p->msigsel));
113 assert_param(IS_DMA_CHANNEL(p->channel));
114
115 if (p->primary)
116 descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + p->channel;
117 else
118 descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + p->channel;
119
120 if (p->src_inc == DMA_DATA_INC_NONE)
121 descr->src = p->src;
122 else
123 descr->src = (void *)((uint32_t)p->src + ((p->size - 1) << (uint32_t)p->src_inc));
124
125 if (p->dst_inc == DMA_DATA_INC_NONE)
126 descr->dst = p->dst;
127 else
128 descr->dst = (void *)((uint32_t)p->dst + ((p->size - 1) << (uint32_t)p->dst_inc));
129
130 descr->ctrl.cycle_ctrl = mode;
131 descr->ctrl.next_useburst = 0;
132 descr->ctrl.n_minus_1 = p->size - 1;
133 descr->ctrl.R_power = p->R_power;
134 descr->ctrl.src_prot_ctrl = 0,
135 descr->ctrl.dst_prot_ctrl = 0,
136 descr->ctrl.src_size = p->data_width;
137 descr->ctrl.src_inc = p->src_inc;
138 descr->ctrl.dst_size = p->data_width;
139 descr->ctrl.dst_inc = p->dst_inc;
140
141 if (p->primary)
142 WRITE_REG(DMAx->CHPRIALTCLR, (1 << p->channel));
143 else
144 WRITE_REG(DMAx->CHPRIALTSET, (1 << p->channel));
145
146 if (p->burst)
147 WRITE_REG(DMAx->CHUSEBURSTSET, (1 << p->channel));
148 else
149 WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << p->channel));
150
151 if (p->high_prio)
152 WRITE_REG(DMAx->CHPRSET, (1 << p->channel));
153 else
154 WRITE_REG(DMAx->CHPRCLR, (1 << p->channel));
155
156 if (p->interrupt)
157 SET_BIT(DMAx->IER, (1 << p->channel));
158 else
159 CLEAR_BIT(DMAx->IER, (1 << p->channel));
160
161 MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSEL_MSK, p->msel << DMA_CH0_SELCON_MSEL_POSS);
162 MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSIGSEL_MSK, p->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS);
163 return;
164 }
165
170 void ald_dma_irq_handler(void)
171 {
172 uint32_t i, reg = DMA0->IFLAG;
173
174 for (i = 0; i < DMA_CH_COUNT; ++i) {
175 if (READ_BIT(reg, (1 << i))) {
176 if (dma0_cbk[i].cplt_cbk != NULL)
177 dma0_cbk[i].cplt_cbk(dma0_cbk[i].cplt_arg);
178
179 ald_dma_clear_flag_status(DMA0, i);
180 }
181 }
182
183 if (READ_BIT(reg, (1U << DMA_ERR))) {
184 ald_dma_clear_flag_status(DMA0, DMA_ERR);
185
186 for (i = 0; i < DMA_CH_COUNT; ++i) {
187 if (((DMA0->CHENSET >> i) & 0x1) && (dma0_cbk[i].err_cbk != NULL))
188 dma0_cbk[i].err_cbk(dma0_cbk[i].err_arg);
189 }
190 }
191
192 return;
193 }
242 void ald_dma_reset(DMA_TypeDef *DMAx)
243 {
244 uint32_t i;
245
246 assert_param(IS_DMA(DMAx));
247
248 WRITE_REG(DMAx->CFG, 0x0);
249 WRITE_REG(DMAx->CHUSEBURSTCLR, 0xFFF);
250 WRITE_REG(DMAx->CHREQMASKCLR, 0xFFF);
251 WRITE_REG(DMAx->CHENCLR, 0xFFF);
252 WRITE_REG(DMAx->CHPRIALTCLR, 0xFFF);
253 WRITE_REG(DMAx->CHPRCLR, 0xFFF);
254 WRITE_REG(DMAx->ERRCLR, 0x1);
255 WRITE_REG(DMAx->IER, 0x0);
256 WRITE_REG(DMAx->ICFR, 0x80000FFF);
257
258 for (i = 0; i < DMA_CH_COUNT; ++i)
259 WRITE_REG(DMAx->CH_SELCON[i], 0x0);
260
261 return;
262 }
263
270 void ald_dma_init(DMA_TypeDef *DMAx)
271 {
272 assert_param(IS_DMA(DMAx));
273
274 memset(dma0_ctrl_base, 0x0, sizeof(dma0_ctrl_base));
275 memset(dma0_cbk, 0x0, sizeof(dma0_cbk));
276
277 ald_dma_reset(DMAx);
278 NVIC_SetPriority(DMA_IRQn, 2);
279 NVIC_EnableIRQ(DMA_IRQn);
280 SET_BIT(DMAx->IER, DMA_IER_DMAERRIE_MSK);
281
282 WRITE_REG(DMAx->CTRLBASE, (uint32_t)&dma0_ctrl_base);
283 SET_BIT(DMAx->CFG, DMA_CFG_MASTER_ENABLE_MSK);
284
285 return;
286 }
287
294 void ald_dma_config_struct(dma_config_t *p)
295 {
296 p->data_width = DMA_DATA_SIZE_BYTE;
297 p->src_inc = DMA_DATA_INC_BYTE;
298 p->dst_inc = DMA_DATA_INC_BYTE;
299 p->R_power = DMA_R_POWER_1;
300 p->primary = ENABLE;
301 p->burst = DISABLE;
302 p->high_prio = DISABLE;
303 p->interrupt = ENABLE;
304
305 return;
306 }
307
316 void ald_dma_config_sg_alt_desc(dma_descriptor_t *desc, dma_config_t *config, uint8_t memory)
317 {
318 if ((desc == NULL) || (config == NULL))
319 return;
320
321 if (config->src_inc == DMA_DATA_INC_NONE)
322 desc->src = config->src;
323 else
324 desc->src = (void *)((uint32_t)config->src + ((config->size - 1) << (uint32_t)config->data_width));
325
326 if (config->dst_inc == DMA_DATA_INC_NONE)
327 desc->dst = config->dst;
328 else
329 desc->dst = (void *)((uint32_t)config->dst + ((config->size - 1) << (uint32_t)config->data_width));
330
331 desc->ctrl.cycle_ctrl = memory ? DMA_CYCLE_CTRL_MEM_SG_ALTERNATE : DMA_CYCLE_CTRL_PER_SG_ALTERNATE;
332 desc->ctrl.next_useburst = memory ? 0 : 1;
333 desc->ctrl.n_minus_1 = config->size - 1;
334 desc->ctrl.R_power = config->R_power;
335 desc->ctrl.src_prot_ctrl = 0;
336 desc->ctrl.dst_prot_ctrl = 0;
337 desc->ctrl.src_size = config->data_width;
338 desc->ctrl.src_inc = config->src_inc;
339 desc->ctrl.dst_size = config->data_width;
340 desc->ctrl.dst_inc = config->dst_inc;
341
342 return;
343 }
344
392 void ald_dma_config_auto(dma_handle_t *hperh)
393 {
394 dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk;
395 dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk;
396 dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg;
397 dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg;
398 dma_config_base(hperh->perh, DMA_CYCLE_CTRL_AUTO, &hperh->config);
399
400 ald_dma_clear_flag_status(hperh->perh, hperh->config.channel);
401 WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel));
402 SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel));
403
404 return;
405 }
406
417 void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size)
418 {
419 dma_descriptor_t *descr;
420
421 if (hperh->config.primary)
422 descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel;
423 else
424 descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel;
425
426 if (src) {
427 if (hperh->config.src_inc == DMA_DATA_INC_NONE)
428 descr->src = src;
429 else
430 descr->src = (void *)((uint32_t)src + ((size - 1) << (uint32_t)hperh->config.data_width));
431 }
432
433 if (dst) {
434 if (hperh->config.dst_inc == DMA_DATA_INC_NONE)
435 descr->dst = dst;
436 else
437 descr->dst = (void *)((uint32_t)dst + ((size - 1) << (uint32_t)hperh->config.data_width));
438 }
439
440 ald_dma_clear_flag_status(hperh->perh, hperh->config.channel);
441 descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO;
442 descr->ctrl.n_minus_1 = size - 1;
443 WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel));
444 SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel));
445 return;
446 }
447
448
449
464 void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst,
465 uint16_t size, uint8_t channel, void (*cbk)(void *arg))
466 {
467 dma_handle_t hperh;
468
469 assert_param(IS_DMA(DMAx));
470
471 ald_dma_config_struct(&hperh.config);
472 hperh.config.src = src;
473 hperh.config.dst = dst;
474 hperh.config.size = size;
475 hperh.config.msel = DMA_MSEL_NONE;
476 hperh.config.msigsel = DMA_MSIGSEL_NONE;
477 hperh.config.channel = channel;
478
479 hperh.perh = DMAx;
480 hperh.cplt_cbk = cbk;
481 hperh.cplt_arg = NULL;
482 hperh.err_cbk = NULL;
483
484 ald_dma_clear_flag_status(DMAx, channel);
485 ald_dma_config_auto(&hperh);
486
487 return;
488 }
489
499 void ald_dma_config_basic(dma_handle_t *hperh)
500 {
501 dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk;
502 dma0_cbk[hperh->config.channel].err_cbk = hperh->err_cbk;
503 dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg;
504 dma0_cbk[hperh->config.channel].err_arg = hperh->err_arg;
505
506 ald_dma_clear_flag_status(hperh->perh, hperh->config.channel);
507 dma_config_base(hperh->perh, DMA_CYCLE_CTRL_BASIC, &hperh->config);
508 WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel));
509
510 return;
511 }
512
523 void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size)
524 {
525 dma_descriptor_t *descr;
526
527 if (hperh->config.primary)
528 descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel;
529 else
530 descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel;
531
532 if (src) {
533 if (hperh->config.src_inc == DMA_DATA_INC_NONE)
534 descr->src = src;
535 else
536 descr->src = (void *)((uint32_t)src + ((size - 1) << (uint32_t)hperh->config.data_width));
537 }
538
539 if (dst) {
540 if (hperh->config.dst_inc == DMA_DATA_INC_NONE)
541 descr->dst = dst;
542 else
543 descr->dst = (void *)((uint32_t)dst + ((size - 1) << (uint32_t)hperh->config.data_width));
544 }
545
546 ald_dma_clear_flag_status(hperh->perh, hperh->config.channel);
547 descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC;
548 descr->ctrl.n_minus_1 = size - 1;
549 WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel));
550
551 return;
552 }
553
571 void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel,
572 dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg))
573 {
574 dma_handle_t hperh;
575
576 assert_param(IS_DMA(DMAx));
577 ald_dma_config_struct(&hperh.config);
578
579 if (((uint32_t)src) >= 0x40000000)
580 hperh.config.src_inc = DMA_DATA_INC_NONE;
581
582 if (((uint32_t)dst) >= 0x40000000)
583 hperh.config.dst_inc = DMA_DATA_INC_NONE;
584
585 hperh.config.src = src;
586 hperh.config.dst = dst;
587 hperh.config.size = size;
588 hperh.config.msel = msel;
589 hperh.config.msigsel = msigsel;
590 hperh.config.channel = channel;
591
592 hperh.perh = DMAx;
593 hperh.cplt_cbk = cbk;
594 hperh.cplt_arg = NULL;
595 hperh.err_cbk = NULL;
596
597 ald_dma_clear_flag_status(DMAx, channel);
598 ald_dma_config_basic(&hperh);
599
600 return;
601 }
602
614 void ald_dma_config_ping_pong(DMA_TypeDef *DMAx, dma_config_t *config,
615 uint8_t first, void (*cbk)(void *arg))
616 {
617 dma_descriptor_t *desc;
618
619 assert_param(IS_DMA(DMAx));
620 assert_param(config->src != NULL);
621 assert_param(config->dst != NULL);
622 assert_param(IS_DMA_DATA_SIZE(config->size));
623 assert_param(IS_DMA_DATASIZE_TYPE(config->data_width));
624 assert_param(IS_DMA_DATAINC_TYPE(config->src_inc));
625 assert_param(IS_DMA_DATAINC_TYPE(config->dst_inc));
626 assert_param(IS_DMA_ARBITERCONFIG_TYPE(config->R_power));
627 assert_param(IS_FUNC_STATE(config->primary));
628 assert_param(IS_FUNC_STATE(config->burst));
629 assert_param(IS_FUNC_STATE(config->high_prio));
630 assert_param(IS_FUNC_STATE(config->interrupt));
631 assert_param(IS_DMA_MSEL_TYPE(config->msel));
632 assert_param(IS_DMA_MSIGSEL_TYPE(config->msigsel));
633 assert_param(IS_DMA_CHANNEL(config->channel));
634
635 dma0_cbk[config->channel].cplt_cbk = cbk;
636 dma0_cbk[config->channel].err_cbk = NULL;
637 dma0_cbk[config->channel].cplt_arg = NULL;
638 dma0_cbk[config->channel].err_arg = NULL;
639
640 if (config->primary)
641 desc = (dma_descriptor_t *)(DMAx->CTRLBASE) + config->channel;
642 else
643 desc = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + config->channel;
644
645 if (config->src_inc == DMA_DATA_INC_NONE)
646 desc->src = config->src;
647 else
648 desc->src = (void *)((uint32_t)config->src + ((config->size - 1) << (uint32_t)config->data_width));
649
650 if (config->dst_inc == DMA_DATA_INC_NONE)
651 desc->dst = config->dst;
652 else
653 desc->dst = (void *)((uint32_t)config->dst + ((config->size - 1) << (uint32_t)config->data_width));
654
655 desc->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_PINGPONG;
656 desc->ctrl.next_useburst = 0;
657 desc->ctrl.n_minus_1 = config->size - 1;
658 desc->ctrl.R_power = config->R_power;
659 desc->ctrl.src_prot_ctrl = 0,
660 desc->ctrl.dst_prot_ctrl = 0,
661 desc->ctrl.src_size = config->data_width;
662 desc->ctrl.src_inc = config->src_inc;
663 desc->ctrl.dst_size = config->data_width;
664 desc->ctrl.dst_inc = config->dst_inc;
665
666 if (!first)
667 return;
668
669 if (config->primary)
670 WRITE_REG(DMAx->CHPRIALTCLR, (1 << config->channel));
671 else
672 WRITE_REG(DMAx->CHPRIALTSET, (1 << config->channel));
673
674 if (config->burst)
675 WRITE_REG(DMAx->CHUSEBURSTSET, (1 << config->channel));
676 else
677 WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << config->channel));
678
679 if (config->high_prio)
680 WRITE_REG(DMAx->CHPRSET, (1 << config->channel));
681 else
682 WRITE_REG(DMAx->CHPRCLR, (1 << config->channel));
683
684 if (config->interrupt)
685 SET_BIT(DMAx->IER, (1 << config->channel));
686 else
687 CLEAR_BIT(DMAx->IER, (1 << config->channel));
688
689 MODIFY_REG(DMAx->CH_SELCON[config->channel], DMA_CH0_SELCON_MSEL_MSK, config->msel << DMA_CH0_SELCON_MSEL_POSS);
690 MODIFY_REG(DMAx->CH_SELCON[config->channel], DMA_CH0_SELCON_MSIGSEL_MSK, config->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS);
691
692 WRITE_REG(DMAx->ICFR, (1 << config->channel));
693 WRITE_REG(DMAx->CHENSET, (1 << config->channel));
694
695 return;
696 }
697
708 void ald_dma_config_sg_mem(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr,
709 uint8_t channel, void (*cbk)(void *arg))
710 {
711 dma_descriptor_t *tmp = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel;
712 dma_descriptor_t *_tmp = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel;
713
714 assert_param(IS_DMA(DMAx));
715 assert_param(IS_DMA_CHANNEL(channel));
716
717 if ((desc == NULL) || (nr == 0))
718 return;
719
720 dma0_cbk[channel].cplt_cbk = cbk;
721 dma0_cbk[channel].err_cbk = NULL;
722 dma0_cbk[channel].cplt_arg = NULL;
723 dma0_cbk[channel].err_arg = NULL;
724
725 tmp->src = (void *)((uint32_t)desc + (((nr << 2) - 1) << DMA_DATA_INC_WORD));
726 tmp->dst = (void *)((uint32_t)_tmp + ((4 - 1) << DMA_DATA_INC_WORD));
727 tmp->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_MEM_SG_PRIMARY;
728 tmp->ctrl.next_useburst = 0;
729 tmp->ctrl.n_minus_1 = (nr << 2) - 1;
730 tmp->ctrl.R_power = DMA_R_POWER_4;
731 tmp->ctrl.src_prot_ctrl = 0,
732 tmp->ctrl.dst_prot_ctrl = 0,
733 tmp->ctrl.src_size = DMA_DATA_SIZE_WORD;
734 tmp->ctrl.src_inc = DMA_DATA_INC_WORD;
735 tmp->ctrl.dst_size = DMA_DATA_SIZE_WORD;
736 tmp->ctrl.dst_inc = DMA_DATA_INC_WORD;
737
738 desc[nr - 1].ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO;
739 WRITE_REG(DMAx->CHPRIALTCLR, (1 << channel));
740 WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << channel));
741 WRITE_REG(DMAx->CHPRCLR, (1 << channel));
742
743 WRITE_REG(DMAx->ICFR, (1 << channel));
744 SET_BIT(DMAx->IER, (1 << channel));
745 WRITE_REG(DMAx->CHENSET, (1 << channel));
746 SET_BIT(DMAx->CHSWREQ, (1 << channel));
747
748 return;
749 }
750
765 void ald_dma_config_sg_per(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst,
766 dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg))
767 {
768 dma_descriptor_t *tmp = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel;
769 dma_descriptor_t *_tmp = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel;
770
771 assert_param(IS_DMA(DMAx));
772 assert_param(IS_DMA_MSEL_TYPE(msel));
773 assert_param(IS_DMA_MSIGSEL_TYPE(msigsel));
774 assert_param(IS_DMA_CHANNEL(channel));
775
776 if ((desc == NULL) || (nr == 0))
777 return;
778
779 dma0_cbk[channel].cplt_cbk = cbk;
780 dma0_cbk[channel].err_cbk = NULL;
781 dma0_cbk[channel].cplt_arg = NULL;
782 dma0_cbk[channel].err_arg = NULL;
783
784 tmp->src = (void *)((uint32_t)desc + (((nr << 2) - 1) << DMA_DATA_INC_WORD));
785 tmp->dst = (void *)((uint32_t)_tmp + ((4 - 1) << DMA_DATA_INC_WORD));
786 tmp->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_PER_SG_PRIMARY;
787 tmp->ctrl.next_useburst = 0;
788 tmp->ctrl.n_minus_1 = (nr << 2) - 1;
789 tmp->ctrl.R_power = DMA_R_POWER_4;
790 tmp->ctrl.src_prot_ctrl = 0,
791 tmp->ctrl.dst_prot_ctrl = 0,
792 tmp->ctrl.src_size = DMA_DATA_SIZE_WORD;
793 tmp->ctrl.src_inc = DMA_DATA_INC_WORD;
794 tmp->ctrl.dst_size = DMA_DATA_SIZE_WORD;
795 tmp->ctrl.dst_inc = DMA_DATA_INC_WORD;
796
797 desc[nr - 1].ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC;
798 WRITE_REG(DMAx->CHPRIALTCLR, (1 << channel));
799 burst ? (DMAx->CHUSEBURSTSET = (1 << channel)) : (DMAx->CHUSEBURSTCLR, (1 << channel));
800 WRITE_REG(DMAx->CHPRCLR, (1 << channel));
801
802 MODIFY_REG(DMAx->CH_SELCON[channel], DMA_CH0_SELCON_MSEL_MSK, msel << DMA_CH0_SELCON_MSEL_POSS);
803 MODIFY_REG(DMAx->CH_SELCON[channel], DMA_CH0_SELCON_MSIGSEL_MSK, msigsel << DMA_CH0_SELCON_MSIGSEL_POSS);
804
805 WRITE_REG(DMAx->ICFR, (1 << channel));
806 SET_BIT(DMAx->IER, (1 << channel));
807 WRITE_REG(DMAx->CHENSET, (1 << channel));
808
809 return;
810 }
850 void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state)
851 {
852 dma_descriptor_t *descr, *alt_descr;
853
854 assert_param(IS_DMA(DMAx));
855 assert_param(IS_DMA_CHANNEL(channel));
856 assert_param(IS_FUNC_STATE(state));
857
858 descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel;
859 alt_descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel;
860
861 if (state) {
862 WRITE_REG(DMAx->CHENSET, (1 << channel));
863 }
864 else {
865 memset(descr, 0x00, sizeof(dma_descriptor_t));
866 memset(alt_descr, 0x00, sizeof(dma_descriptor_t));
867 WRITE_REG(DMAx->CH_SELCON[channel], 0x0);
868 WRITE_REG(DMAx->CHENCLR, (1 << channel));
869 }
870
871 return;
872 }
873
886 void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state)
887 {
888 assert_param(IS_DMA(DMAx));
889 assert_param(IS_DMA_IT_TYPE(channel));
890 assert_param(IS_FUNC_STATE(state));
891
892 if (state)
893 SET_BIT(DMAx->IER, (1 << channel));
894 else
895 CLEAR_BIT(DMAx->IER, (1 << channel));
896
897 return;
898 }
899
911 it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel)
912 {
913 assert_param(IS_DMA(DMAx));
914 assert_param(IS_DMA_IT_TYPE(channel));
915
916 if (READ_BIT(DMAx->IER, (1 << channel)))
917 return SET;
918
919 return RESET;
920 }
921
933 flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel)
934 {
935 assert_param(IS_DMA(DMAx));
936 assert_param(IS_DMA_IT_TYPE(channel));
937
938 if (READ_BIT(DMAx->IFLAG, (1 << channel)))
939 return SET;
940
941 return RESET;
942 }
943
952 void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel)
953 {
954 assert_param(IS_DMA(DMAx));
955 assert_param(IS_DMA_IT_TYPE(channel));
956
957 WRITE_REG(DMAx->ICFR, (1 << channel));
958 return;
959 }
960
970 dma_descrp_cplt_t ald_dma_descriptor_cplt_get(DMA_TypeDef *DMAx, uint8_t channel)
971 {
972 uint8_t pri, alt;
973 dma_descriptor_t *desc;
974
975 assert_param(IS_DMA(DMAx));
976 assert_param(IS_DMA_IT_TYPE(channel));
977
978 desc = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel;
979 pri = desc->ctrl.cycle_ctrl;
980 desc = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel;
981 alt = desc->ctrl.cycle_ctrl;
982
983 if ((pri == 0) && (alt == 0))
984 return DMA_DESCP_CPLT_ALL;
985
986 if (pri == 0)
987 return DMA_DESCP_CPLT_PRI;
988 else
989 return DMA_DESCP_CPLT_ALT;
990 }
998 #endif /* ALD_DMA */
999
ald_dma_config_ping_pong
void ald_dma_config_ping_pong(DMA_TypeDef *DMAx, dma_config_t *config, uint8_t first, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is ping-pong.
Definition: ald_dma.c:614
ald_dma_config_sg_mem
void ald_dma_config_sg_mem(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t channel, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is memory scatter-gather...
Definition: ald_dma.c:708
DMA_R_POWER_4
Definition: ald_dma.h:253
dma_ctrl_t::src_size
uint32_t src_size
Definition: ald_dma.h:195
dma_call_back_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:270
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
dma_ctrl_t::dst_size
uint32_t dst_size
Definition: ald_dma.h:197
dma_ctrl_t::src_prot_ctrl
uint32_t src_prot_ctrl
Definition: ald_dma.h:193
DMA_MSEL_NONE
Definition: ald_dma.h:78
dma_config_t::high_prio
type_func_t high_prio
Definition: ald_dma.h:287
dma_call_back_t::err_arg
void * err_arg
Definition: ald_dma.h:271
dma_config_t::R_power
dma_arbiter_config_t R_power
Definition: ald_dma.h:284
dma_handle_t
DMA handle structure definition.
Definition: ald_dma.h:297
dma_call_back_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:269
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
dma_ctrl_t::src_inc
uint32_t src_inc
Definition: ald_dma.h:196
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_DMA_DATASIZE_TYPE
#define IS_DMA_DATASIZE_TYPE(x)
Definition: ald_dma.h:328
dma_ctrl_t::next_useburst
uint32_t next_useburst
Definition: ald_dma.h:190
ald_dma_init
void ald_dma_init(DMA_TypeDef *DMAx)
DMA module initialization, this function is invoked by ald_cmu_init().
Definition: ald_dma.c:270
IS_CYCLECTRL_TYPE
#define IS_CYCLECTRL_TYPE(x)
Definition: ald_dma.h:331
IS_DMA_DATA_SIZE
#define IS_DMA_DATA_SIZE(x)
Definition: ald_dma.h:352
dma_ctrl_t::dst_inc
uint32_t dst_inc
Definition: ald_dma.h:198
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
DMA_CYCLE_CTRL_MEM_SG_PRIMARY
Definition: ald_dma.h:240
dma_call_back_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:268
SET
Definition: type.h:39
dma_config_base
static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config_t *p)
Configure DMA channel using dma_config_t structure.
Definition: ald_dma.c:94
dma_descriptor_t::dst
void * dst
Definition: ald_dma.h:208
type_func_t
type_func_t
Definition: type.h:47
DISABLE
Definition: type.h:48
dma_ctrl_t::dst_prot_ctrl
uint32_t dst_prot_ctrl
Definition: ald_dma.h:194
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
dma_config_t::src
void * src
Definition: ald_dma.h:278
ald_dma_config_basic_easy
void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is basic. This mode is used to carry data from peripheral to memory or negative direction. If user want use the dma easily, they can invoke this function.
Definition: ald_dma.c:571
DMA_DESCP_CPLT_PRI
Definition: ald_dma.h:310
IS_DMA_MSEL_TYPE
#define IS_DMA_MSEL_TYPE(x)
Definition: ald_dma.h:322
DMA_DATA_INC_WORD
Definition: ald_dma.h:219
DMA_DATA_SIZE_WORD
Definition: ald_dma.h:229
dma_config_t::primary
type_func_t primary
Definition: ald_dma.h:285
DMA_DATA_SIZE_BYTE
Definition: ald_dma.h:227
dma0_cbk
dma_call_back_t dma0_cbk[12]
Definition: ald_dma.c:77
RESET
Definition: type.h:38
DMA_DESCP_CPLT_ALL
Definition: ald_dma.h:312
ald_conf.h
Enable/Disable the peripheral module.
dma_descriptor_t::ctrl
dma_ctrl_t ctrl
Definition: ald_dma.h:209
dma_msigsel_t
dma_msigsel_t
Input signal to DMA channel.
Definition: ald_dma.h:114
IS_DMA_DATAINC_TYPE
#define IS_DMA_DATAINC_TYPE(x)
Definition: ald_dma.h:324
DMA_DESCP_CPLT_ALT
Definition: ald_dma.h:311
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
__attribute__
dma_descriptor_t dma0_ctrl_base [28] __attribute__((aligned(512)))
dma_config_t
DMA channal configure structure.
Definition: ald_dma.h:277
ald_dma_get_flag_status
flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel)
Check whether the specified channel flag is set or reset.
Definition: ald_dma.c:933
ald_dma_restart_basic
void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size)
Restart DMA transmitted. The DMA mode is basic. The other parameters have not changed except &#39;size&#39; a...
Definition: ald_dma.c:523
ald_dma_restart_auto
void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size)
Restart DMA transmitted. The DMA mode is automatic. The other parameters have not changed except &#39;siz...
Definition: ald_dma.c:417
it_status_t
enum flag_status_t it_status_t
ald_dma_descriptor_cplt_get
dma_descrp_cplt_t ald_dma_descriptor_cplt_get(DMA_TypeDef *DMAx, uint8_t channel)
Get the completion status of the descriptor.
Definition: ald_dma.c:970
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
ald_dma_config_sg_alt_desc
void ald_dma_config_sg_alt_desc(dma_descriptor_t *desc, dma_config_t *config, uint8_t memory)
Configure dma_descriptor_t structure using specified parameter.
Definition: ald_dma.c:316
ald_dma_interrupt_config
void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state)
Configure the interrupt enable or disable.
Definition: ald_dma.c:886
ald_dma.h
DMA module Library.
ald_dma_clear_flag_status
void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel)
Clear the specified channel pending flag.
Definition: ald_dma.c:952
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
DMA_CYCLE_CTRL_PER_SG_PRIMARY
Definition: ald_dma.h:242
DMA_CYCLE_CTRL_BASIC
Definition: ald_dma.h:237
dma_cycle_ctrl_t
dma_cycle_ctrl_t
The operating mode of the DMA cycle.
Definition: ald_dma.h:235
DMA_ERR
#define DMA_ERR
Definition: ald_dma.h:40
DMA_CH_COUNT
#define DMA_CH_COUNT
Definition: ald_dma.h:39
DMA_DATA_INC_BYTE
Definition: ald_dma.h:217
dma_descriptor_t::src
void * src
Definition: ald_dma.h:207
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
DMA_CYCLE_CTRL_PER_SG_ALTERNATE
Definition: ald_dma.h:243
IS_DMA_MSIGSEL_TYPE
#define IS_DMA_MSIGSEL_TYPE(x)
Definition: ald_dma.h:323
DMA_CYCLE_CTRL_PINGPONG
Definition: ald_dma.h:239
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_DMA_CHANNEL
#define IS_DMA_CHANNEL(x)
Definition: ald_dma.h:351
dma_descrp_cplt_t
dma_descrp_cplt_t
Descriptor complete state.
Definition: ald_dma.h:309
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
flag_status_t
flag_status_t
Definition: type.h:37
DMA_MSIGSEL_NONE
Definition: ald_dma.h:115
dma_descriptor_t
Channel control data structure.
Definition: ald_dma.h:206
dma_ctrl_t::cycle_ctrl
uint32_t cycle_ctrl
Definition: ald_dma.h:189
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
dma_ctrl_t::R_power
uint32_t R_power
Definition: ald_dma.h:192
dma_msel_t
dma_msel_t
Input source to DMA channel.
Definition: ald_dma.h:77
dac_handle_s::cbk
void(* cbk)(struct dac_handle_s *arg, uint32_t event)
Definition: ald_dac.h:196
IS_DMA_ARBITERCONFIG_TYPE
#define IS_DMA_ARBITERCONFIG_TYPE(x)
Definition: ald_dma.h:339
dma_config_t::interrupt
type_func_t interrupt
Definition: ald_dma.h:288
ald_dma_config_auto
void ald_dma_config_auto(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is automatic. This mode is used to carry data from memory to memory.
Definition: ald_dma.c:392
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
ald_dma_get_it_status
it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel)
Check whether the specified channel interrupt is set or reset.
Definition: ald_dma.c:911
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
DMA_CYCLE_CTRL_AUTO
Definition: ald_dma.h:238
ald_dma_config_sg_per
void ald_dma_config_sg_per(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst, dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is peripheral scatter-gather...
Definition: ald_dma.c:765
ald_dma_config_auto_easy
void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, uint8_t channel, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is automatic. This mode is used to carry data from memory to memory. If User want use the dma easily, they can invoke this function.
Definition: ald_dma.c:464
ald_dma_reset
void ald_dma_reset(DMA_TypeDef *DMAx)
Reset the DMA register.
Definition: ald_dma.c:242
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
dma_ctrl_t::n_minus_1
uint32_t n_minus_1
Definition: ald_dma.h:191
dma_call_back_t
Callback function pointer and param.
Definition: ald_dma.h:267
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
IS_DMA_IT_TYPE
#define IS_DMA_IT_TYPE(x)
Definition: ald_dma.h:353
DMA_R_POWER_1
Definition: ald_dma.h:251
DMA_CYCLE_CTRL_MEM_SG_ALTERNATE
Definition: ald_dma.h:241
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
ald_dma_irq_handler
void ald_dma_irq_handler(void)
Handle DMA interrupt.
Definition: ald_dma.c:170
IS_DMA
#define IS_DMA(x)
Definition: ald_dma.h:350
ald_dma_channel_config
void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state)
Configure channel enable or disable. It will unbind descriptor with channel, when channel has been di...
Definition: ald_dma.c:850


ALD User Manual: D:/svn/src/ald_dma.h Source File

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ald_dma.h
Go to the documentation of this file.
1
17 #ifndef __ALD_DMA_H__
18 #define __ALD_DMA_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25
26
39 #define DMA_CH_COUNT 12U
40 #define DMA_ERR 31U
41
77 typedef enum {
78 DMA_MSEL_NONE = 0x0U,
79 DMA_MSEL_GPIO = 0x1U,
80 DMA_MSEL_CRYPT = 0x2U,
81 DMA_MSEL_DAC0 = 0x4U,
82 DMA_MSEL_ADC0 = 0x6U,
83 DMA_MSEL_CRC = 0x7U,
84 DMA_MSEL_UART0 = 0x8U,
85 DMA_MSEL_UART1 = 0x9U,
86 DMA_MSEL_UART2 = 0xAU,
87 DMA_MSEL_UART3 = 0xBU,
88 DMA_MSEL_UART4 = 0xCU,
89 DMA_MSEL_UART5 = 0xDU,
90 DMA_MSEL_SPI0 = 0xEU,
91 DMA_MSEL_SPI1 = 0xFU,
92 DMA_MSEL_I2C0 = 0x10U,
93 DMA_MSEL_I2C1 = 0x11U,
94 DMA_MSEL_TIMER0 = 0x12U,
95 DMA_MSEL_TIMER1 = 0x13U,
96 DMA_MSEL_TIMER2 = 0x14U,
97 DMA_MSEL_TIMER3 = 0x15U,
98 DMA_MSEL_LPUART0 = 0x18U,
99 DMA_MSEL_SPI2 = 0x1AU,
100 DMA_MSEL_TIMER4 = 0x1BU,
101 DMA_MSEL_TIMER5 = 0x1CU,
102 DMA_MSEL_TIMER6 = 0x1DU,
103 DMA_MSEL_TIMER7 = 0x1EU,
104 DMA_MSEL_ADC1 = 0x1FU,
105 DMA_MSEL_PIS = 0x20U,
106 DMA_MSEL_TRNG = 0x21U,
107 DMA_MSEL_QSPI = 0x22U,
108 DMA_MSEL_USB = 0x23U,
109 } dma_msel_t;
110
114 typedef enum {
115 DMA_MSIGSEL_NONE = 0x0U,
116 DMA_MSIGSEL_EXTI_0 = 0x0U,
117 DMA_MSIGSEL_EXTI_1 = 0x1U,
118 DMA_MSIGSEL_EXTI_2 = 0x2U,
119 DMA_MSIGSEL_EXTI_3 = 0x3U,
120 DMA_MSIGSEL_EXTI_4 = 0x4U,
121 DMA_MSIGSEL_EXTI_5 = 0x5U,
122 DMA_MSIGSEL_EXTI_6 = 0x6U,
123 DMA_MSIGSEL_EXTI_7 = 0x7U,
124 DMA_MSIGSEL_EXTI_8 = 0x8U,
125 DMA_MSIGSEL_EXTI_9 = 0x9U,
126 DMA_MSIGSEL_EXTI_10 = 0xAU,
127 DMA_MSIGSEL_EXTI_11 = 0xBU,
128 DMA_MSIGSEL_EXTI_12 = 0xCU,
129 DMA_MSIGSEL_EXTI_13 = 0xDU,
130 DMA_MSIGSEL_EXTI_14 = 0xEU,
131 DMA_MSIGSEL_EXTI_15 = 0xFU,
132 DMA_MSIGSEL_CRYPT_WRITE = 0x0U,
133 DMA_MSIGSEL_CRYPT_READ = 0x1U,
134 DMA_MSIGSEL_DAC0_CH0 = 0x0U,
135 DMA_MSIGSEL_DAC0_CH1 = 0x1U,
136 DMA_MSIGSEL_ADC = 0x0U,
137 DMA_MSIGSEL_UART_TXEMPTY = 0x0U,
138 DMA_MSIGSEL_UART_RNR = 0x1U,
139 DMA_MSIGSEL_UART45_RNR = 0x0U,
140 DMA_MSIGSEL_UART45_TXEMPTY = 0x1U,
141 DMA_MSIGSEL_SPI_RNR = 0x0U,
142 DMA_MSIGSEL_SPI_TXEMPTY = 0x1U,
143 DMA_MSIGSEL_I2C_RNR = 0x0U,
144 DMA_MSIGSEL_I2C_TXEMPTY = 0x1U,
145 DMA_MSIGSEL_TIMER_CH1 = 0x0U,
146 DMA_MSIGSEL_TIMER_CH2 = 0x1U,
147 DMA_MSIGSEL_TIMER_CH3 = 0x2U,
148 DMA_MSIGSEL_TIMER_CH4 = 0x3U,
149 DMA_MSIGSEL_TIMER_TRI = 0x4U,
150 DMA_MSIGSEL_TIMER_COMP = 0x5U,
151 DMA_MSIGSEL_TIMER_UPDATE = 0x6U,
152 DMA_MSIGSEL_LPUART_RNR = 0x0U,
153 DMA_MSIGSEL_LPUART_TXEMPTY = 0x1U,
154 DMA_MSIGSEL_PIS_CH0 = 0x0U,
155 DMA_MSIGSEL_PIS_CH1 = 0x1U,
156 DMA_MSIGSEL_PIS_CH2 = 0x2U,
157 DMA_MSIGSEL_PIS_CH3 = 0x3U,
158 DMA_MSIGSEL_PIS_CH4 = 0x4U,
159 DMA_MSIGSEL_PIS_CH5 = 0x5U,
160 DMA_MSIGSEL_PIS_CH6 = 0x6U,
161 DMA_MSIGSEL_PIS_CH7 = 0x7U,
162 DMA_MSIGSEL_PIS_CH8 = 0x8U,
163 DMA_MSIGSEL_PIS_CH9 = 0x9U,
164 DMA_MSIGSEL_PIS_CH10 = 0xAU,
165 DMA_MSIGSEL_PIS_CH11 = 0xBU,
166 DMA_MSIGSEL_PIS_CH12 = 0xCU,
167 DMA_MSIGSEL_PIS_CH13 = 0xDU,
168 DMA_MSIGSEL_PIS_CH14 = 0xEU,
169 DMA_MSIGSEL_PIS_CH15 = 0xFU,
170 DMA_MSIGSEL_QSPI_WRITE = 0x0U,
171 DMA_MSIGSEL_QSPI_READ = 0x1U,
172 DMA_MSIGSEL_EP_TX1 = 0x0U,
173 DMA_MSIGSEL_EP_TX2 = 0x1U,
174 DMA_MSIGSEL_EP_TX3 = 0x2U,
175 DMA_MSIGSEL_EP_TX4 = 0x3U,
176 DMA_MSIGSEL_EP_TX5 = 0x4U,
177 DMA_MSIGSEL_EP_RX1 = 0x8U,
178 DMA_MSIGSEL_EP_RX2 = 0x9U,
179 DMA_MSIGSEL_EP_RX3 = 0xAU,
180 DMA_MSIGSEL_EP_RX4 = 0xBU,
181 DMA_MSIGSEL_EP_RX5 = 0xCU,
182 } dma_msigsel_t;
183
187 typedef union {
188 struct {
189 uint32_t cycle_ctrl :3;
190 uint32_t next_useburst :1;
191 uint32_t n_minus_1 :10;
192 uint32_t R_power :4;
193 uint32_t src_prot_ctrl :3;
194 uint32_t dst_prot_ctrl :3;
195 uint32_t src_size :2;
196 uint32_t src_inc :2;
197 uint32_t dst_size :2;
198 uint32_t dst_inc :2;
199 };
200 uint32_t word;
201 } dma_ctrl_t;
202
206 typedef struct {
207 void *src;
208 void *dst;
209 dma_ctrl_t ctrl;
210 uint32_t use;
211 } dma_descriptor_t;
212
216 typedef enum {
217 DMA_DATA_INC_BYTE = 0x0U,
218 DMA_DATA_INC_HALFWORD = 0x1U,
219 DMA_DATA_INC_WORD = 0x2U,
220 DMA_DATA_INC_NONE = 0x3U,
221 } dma_data_inc_t;
222
226 typedef enum {
227 DMA_DATA_SIZE_BYTE = 0x0U,
228 DMA_DATA_SIZE_HALFWORD = 0x1U,
229 DMA_DATA_SIZE_WORD = 0x2U,
230 } dma_data_size_t;
231
235 typedef enum {
236 DMA_CYCLE_CTRL_NONE = 0x0U,
237 DMA_CYCLE_CTRL_BASIC = 0x1U,
238 DMA_CYCLE_CTRL_AUTO = 0x2U,
239 DMA_CYCLE_CTRL_PINGPONG = 0x3U,
240 DMA_CYCLE_CTRL_MEM_SG_PRIMARY = 0x4U,
241 DMA_CYCLE_CTRL_MEM_SG_ALTERNATE = 0x5U,
242 DMA_CYCLE_CTRL_PER_SG_PRIMARY = 0x6U,
243 DMA_CYCLE_CTRL_PER_SG_ALTERNATE = 0x7U,
244 } dma_cycle_ctrl_t;
245
250 typedef enum {
251 DMA_R_POWER_1 = 0x0U,
252 DMA_R_POWER_2 = 0x1U,
253 DMA_R_POWER_4 = 0x2U,
254 DMA_R_POWER_8 = 0x3U,
255 DMA_R_POWER_16 = 0x4U,
256 DMA_R_POWER_32 = 0x5U,
257 DMA_R_POWER_64 = 0x6U,
258 DMA_R_POWER_128 = 0x7U,
259 DMA_R_POWER_256 = 0x8U,
260 DMA_R_POWER_512 = 0x9U,
261 DMA_R_POWER_1024 = 0xAU,
262 } dma_arbiter_config_t;
263
267 typedef struct {
268 void (*cplt_cbk)(void *arg);
269 void (*err_cbk)(void* arg);
270 void *cplt_arg;
271 void *err_arg;
272 } dma_call_back_t;
273
277 typedef struct {
278 void *src;
279 void *dst;
280 uint16_t size;
281 dma_data_size_t data_width;
282 dma_data_inc_t src_inc;
283 dma_data_inc_t dst_inc;
284 dma_arbiter_config_t R_power;
285 type_func_t primary;
286 type_func_t burst;
287 type_func_t high_prio;
288 type_func_t interrupt;
289 dma_msel_t msel;
290 dma_msigsel_t msigsel;
291 uint8_t channel;
292 } dma_config_t;
293
297 typedef struct {
298 DMA_TypeDef *perh;
299 dma_config_t config;
300 void (*cplt_cbk)(void *arg);
301 void (*err_cbk)(void *arg);
302 void *cplt_arg;
303 void *err_arg;
304 } dma_handle_t;
305
309 typedef enum {
310 DMA_DESCP_CPLT_PRI = 0x0U,
311 DMA_DESCP_CPLT_ALT = 0x1U,
312 DMA_DESCP_CPLT_ALL = 0x2U,
313 } dma_descrp_cplt_t;
322 #define IS_DMA_MSEL_TYPE(x) ((x) <= DMA_MSEL_USB)
323 #define IS_DMA_MSIGSEL_TYPE(x) ((x) <= 0xF)
324 #define IS_DMA_DATAINC_TYPE(x) (((x) == DMA_DATA_INC_BYTE) || \
325 ((x) == DMA_DATA_INC_HALFWORD) || \
326 ((x) == DMA_DATA_INC_WORD) || \
327 ((x) == DMA_DATA_INC_NONE))
328 #define IS_DMA_DATASIZE_TYPE(x) (((x) == DMA_DATA_SIZE_BYTE) || \
329 ((x) == DMA_DATA_SIZE_HALFWORD) || \
330 ((x) == DMA_DATA_SIZE_WORD))
331 #define IS_CYCLECTRL_TYPE(x) (((x) == DMA_CYCLE_CTRL_NONE) || \
332 ((x) == DMA_CYCLE_CTRL_BASIC) || \
333 ((x) == DMA_CYCLE_CTRL_AUTO) || \
334 ((x) == DMA_CYCLE_CTRL_PINGPONG) || \
335 ((x) == DMA_CYCLE_CTRL_MEM_SG_PRIMARY) || \
336 ((x) == DMA_CYCLE_CTRL_MEM_SG_ALTERNATE) || \
337 ((x) == DMA_CYCLE_CTRL_PER_SG_PRIMARY) || \
338 ((x) == DMA_CYCLE_CTRL_PER_SG_ALTERNATE))
339 #define IS_DMA_ARBITERCONFIG_TYPE(x) (((x) == DMA_R_POWER_1) || \
340 ((x) == DMA_R_POWER_2) || \
341 ((x) == DMA_R_POWER_4) || \
342 ((x) == DMA_R_POWER_8) || \
343 ((x) == DMA_R_POWER_16) || \
344 ((x) == DMA_R_POWER_32) || \
345 ((x) == DMA_R_POWER_64) || \
346 ((x) == DMA_R_POWER_128) || \
347 ((x) == DMA_R_POWER_256) || \
348 ((x) == DMA_R_POWER_512) || \
349 ((x) == DMA_R_POWER_1024))
350 #define IS_DMA(x) ((x) == DMA0)
351 #define IS_DMA_CHANNEL(x) ((x) <= 11)
352 #define IS_DMA_DATA_SIZE(x) ((x) <= 1024)
353 #define IS_DMA_IT_TYPE(x) (((x) <= 11) || ((x) == 31))
354
366 /* Initialization functions */
367 extern void ald_dma_reset(DMA_TypeDef *DMAx);
368 extern void ald_dma_init(DMA_TypeDef *DMAx);
369 extern void ald_dma_config_struct(dma_config_t *p);
370 extern void ald_dma_config_sg_alt_desc(dma_descriptor_t *desc, dma_config_t *config, uint8_t memory);
379 /* Configure DMA channel functions */
380 extern void ald_dma_config_auto(dma_handle_t *hperh);
381 extern void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size);
382 extern void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst,
383 uint16_t size, uint8_t channel, void (*cbk)(void *arg));
384 extern void ald_dma_config_basic(dma_handle_t *hperh);
385 extern void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size);
386 extern void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel,
387 dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg));
388 extern void ald_dma_config_ping_pong(DMA_TypeDef *DMAx, dma_config_t *config,
389 uint8_t first, void (*cbk)(void *arg));
390 extern void ald_dma_config_sg_mem(DMA_TypeDef *DMAx, dma_descriptor_t *desc,
391 uint32_t nr, uint8_t channel, void (*cbk)(void *arg));
392 extern void ald_dma_config_sg_per(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst,
393 dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg));
401 /* DMA control functions */
402 extern void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state);
403 extern void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state);
404 extern it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel);
405 extern flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel);
406 extern void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel);
407 extern dma_descrp_cplt_t ald_dma_descriptor_cplt_get(DMA_TypeDef *DMAx, uint8_t channel);
408 extern void ald_dma_irq_handler(void);
426 #ifdef __cplusplus
427 }
428 #endif
429
430 #endif /*__ALD_DMA_H__ */
ald_dma_config_ping_pong
void ald_dma_config_ping_pong(DMA_TypeDef *DMAx, dma_config_t *config, uint8_t first, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is ping-pong.
Definition: ald_dma.c:614
DMA_MSIGSEL_TIMER_CH1
Definition: ald_dma.h:145
DMA_MSEL_SPI1
Definition: ald_dma.h:91
DMA_MSIGSEL_PIS_CH11
Definition: ald_dma.h:165
DMA_MSIGSEL_EP_TX1
Definition: ald_dma.h:172
ald_dma_config_sg_mem
void ald_dma_config_sg_mem(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t channel, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is memory scatter-gather...
Definition: ald_dma.c:708
DMA_MSEL_TIMER2
Definition: ald_dma.h:96
DMA_MSIGSEL_EP_TX2
Definition: ald_dma.h:173
DMA_R_POWER_4
Definition: ald_dma.h:253
DMA_MSEL_UART4
Definition: ald_dma.h:88
DMA_MSIGSEL_EP_RX5
Definition: ald_dma.h:181
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
dma_ctrl_t::src_size
uint32_t src_size
Definition: ald_dma.h:195
dma_call_back_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:270
DMA_MSEL_USB
Definition: ald_dma.h:108
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
DMA_R_POWER_128
Definition: ald_dma.h:258
dma_ctrl_t::dst_size
uint32_t dst_size
Definition: ald_dma.h:197
DMA_MSEL_UART5
Definition: ald_dma.h:89
dma_ctrl_t::src_prot_ctrl
uint32_t src_prot_ctrl
Definition: ald_dma.h:193
DMA_MSIGSEL_EXTI_5
Definition: ald_dma.h:121
DMA_MSEL_NONE
Definition: ald_dma.h:78
DMA_MSIGSEL_EP_TX3
Definition: ald_dma.h:174
dma_config_t::high_prio
type_func_t high_prio
Definition: ald_dma.h:287
dma_call_back_t::err_arg
void * err_arg
Definition: ald_dma.h:271
DMA_MSIGSEL_TIMER_COMP
Definition: ald_dma.h:150
DMA_MSIGSEL_EXTI_9
Definition: ald_dma.h:125
dma_config_t::R_power
dma_arbiter_config_t R_power
Definition: ald_dma.h:284
dma_handle_t
DMA handle structure definition.
Definition: ald_dma.h:297
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
dma_ctrl_t::src_inc
uint32_t src_inc
Definition: ald_dma.h:196
DMA_MSIGSEL_PIS_CH8
Definition: ald_dma.h:162
dma_ctrl_t::next_useburst
uint32_t next_useburst
Definition: ald_dma.h:190
ald_dma_init
void ald_dma_init(DMA_TypeDef *DMAx)
DMA module initialization, this function is invoked by ald_cmu_init().
Definition: ald_dma.c:270
DMA_MSEL_TIMER4
Definition: ald_dma.h:100
dma_ctrl_t::dst_inc
uint32_t dst_inc
Definition: ald_dma.h:198
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
DMA_CYCLE_CTRL_MEM_SG_PRIMARY
Definition: ald_dma.h:240
dma_data_inc_t
dma_data_inc_t
data increment
Definition: ald_dma.h:216
dma_data_size_t
dma_data_size_t
Data size.
Definition: ald_dma.h:226
DMA_MSIGSEL_TIMER_UPDATE
Definition: ald_dma.h:151
DMA_MSIGSEL_EP_TX4
Definition: ald_dma.h:175
DMA_MSIGSEL_I2C_TXEMPTY
Definition: ald_dma.h:144
DMA_MSIGSEL_PIS_CH4
Definition: ald_dma.h:158
DMA_MSIGSEL_EXTI_1
Definition: ald_dma.h:117
dma_descriptor_t::dst
void * dst
Definition: ald_dma.h:208
type_func_t
type_func_t
Definition: type.h:47
DMA_MSIGSEL_UART45_RNR
Definition: ald_dma.h:139
DMA_MSEL_SPI2
Definition: ald_dma.h:99
dma_ctrl_t::dst_prot_ctrl
uint32_t dst_prot_ctrl
Definition: ald_dma.h:194
DMA_MSIGSEL_I2C_RNR
Definition: ald_dma.h:143
DMA_MSIGSEL_EXTI_11
Definition: ald_dma.h:127
DMA_MSIGSEL_EP_RX2
Definition: ald_dma.h:178
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
DMA_MSEL_UART1
Definition: ald_dma.h:85
ald_dma_irq_handler
void ald_dma_irq_handler(void)
Handle DMA interrupt.
Definition: ald_dma.c:170
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
DMA_MSEL_UART0
Definition: ald_dma.h:84
dma_ctrl_t
DMA Descriptor control type.
Definition: ald_dma.h:187
DMA_R_POWER_256
Definition: ald_dma.h:259
dma_config_t::src
void * src
Definition: ald_dma.h:278
ald_dma_config_basic_easy
void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is basic. This mode is used to carry data from peripheral to memory or negative direction. If user want use the dma easily, they can invoke this function.
Definition: ald_dma.c:571
DMA_DESCP_CPLT_PRI
Definition: ald_dma.h:310
DMA_MSIGSEL_PIS_CH3
Definition: ald_dma.h:157
DMA_DATA_INC_WORD
Definition: ald_dma.h:219
DMA_DATA_SIZE_WORD
Definition: ald_dma.h:229
DMA_MSIGSEL_UART_TXEMPTY
Definition: ald_dma.h:137
dma_config_t::primary
type_func_t primary
Definition: ald_dma.h:285
DMA_MSIGSEL_EP_RX3
Definition: ald_dma.h:179
DMA_MSEL_QSPI
Definition: ald_dma.h:107
DMA_MSIGSEL_EXTI_10
Definition: ald_dma.h:126
DMA_MSEL_PIS
Definition: ald_dma.h:105
DMA_R_POWER_512
Definition: ald_dma.h:260
DMA_DATA_SIZE_BYTE
Definition: ald_dma.h:227
DMA_MSIGSEL_DAC0_CH0
Definition: ald_dma.h:134
DMA_MSIGSEL_EXTI_13
Definition: ald_dma.h:129
DMA_DESCP_CPLT_ALL
Definition: ald_dma.h:312
dma_descriptor_t::ctrl
dma_ctrl_t ctrl
Definition: ald_dma.h:209
dma_msigsel_t
dma_msigsel_t
Input signal to DMA channel.
Definition: ald_dma.h:114
DMA_MSEL_TIMER6
Definition: ald_dma.h:102
DMA_DESCP_CPLT_ALT
Definition: ald_dma.h:311
DMA_MSIGSEL_TIMER_CH4
Definition: ald_dma.h:148
DMA_MSIGSEL_EXTI_12
Definition: ald_dma.h:128
DMA_MSEL_LPUART0
Definition: ald_dma.h:98
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
dma_config_t
DMA channal configure structure.
Definition: ald_dma.h:277
DMA_MSEL_TIMER7
Definition: ald_dma.h:103
utils.h
This file contains the Utilities functions/types for the driver.
ald_dma_get_flag_status
flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel)
Check whether the specified channel flag is set or reset.
Definition: ald_dma.c:933
DMA_MSIGSEL_PIS_CH13
Definition: ald_dma.h:167
ald_dma_restart_basic
void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size)
Restart DMA transmitted. The DMA mode is basic. The other parameters have not changed except &#39;size&#39; a...
Definition: ald_dma.c:523
ald_dma_restart_auto
void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size)
Restart DMA transmitted. The DMA mode is automatic. The other parameters have not changed except &#39;siz...
Definition: ald_dma.c:417
it_status_t
enum flag_status_t it_status_t
ald_dma_descriptor_cplt_get
dma_descrp_cplt_t ald_dma_descriptor_cplt_get(DMA_TypeDef *DMAx, uint8_t channel)
Get the completion status of the descriptor.
Definition: ald_dma.c:970
DMA_MSIGSEL_PIS_CH2
Definition: ald_dma.h:156
DMA_MSIGSEL_PIS_CH6
Definition: ald_dma.h:160
DMA_MSIGSEL_PIS_CH1
Definition: ald_dma.h:155
DMA_MSIGSEL_PIS_CH0
Definition: ald_dma.h:154
DMA_MSEL_I2C0
Definition: ald_dma.h:92
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
ald_dma_config_sg_alt_desc
void ald_dma_config_sg_alt_desc(dma_descriptor_t *desc, dma_config_t *config, uint8_t memory)
Configure dma_descriptor_t structure using specified parameter.
Definition: ald_dma.c:316
DMA_MSIGSEL_UART_RNR
Definition: ald_dma.h:138
DMA_MSEL_DAC0
Definition: ald_dma.h:81
DMA_MSIGSEL_TIMER_CH2
Definition: ald_dma.h:146
ald_dma_interrupt_config
void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state)
Configure the interrupt enable or disable.
Definition: ald_dma.c:886
DMA_MSEL_ADC1
Definition: ald_dma.h:104
DMA_MSIGSEL_PIS_CH7
Definition: ald_dma.h:161
dma_ctrl_t::word
uint32_t word
Definition: ald_dma.h:200
DMA_MSIGSEL_EP_RX1
Definition: ald_dma.h:177
DMA_R_POWER_64
Definition: ald_dma.h:257
DMA_MSIGSEL_EXTI_6
Definition: ald_dma.h:122
DMA_MSIGSEL_EXTI_15
Definition: ald_dma.h:131
DMA_MSEL_TRNG
Definition: ald_dma.h:106
DMA_MSIGSEL_PIS_CH10
Definition: ald_dma.h:164
DMA_MSIGSEL_UART45_TXEMPTY
Definition: ald_dma.h:140
ald_dma_clear_flag_status
void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel)
Clear the specified channel pending flag.
Definition: ald_dma.c:952
DMA_MSIGSEL_EXTI_0
Definition: ald_dma.h:116
DMA_CYCLE_CTRL_PER_SG_PRIMARY
Definition: ald_dma.h:242
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
DMA_CYCLE_CTRL_BASIC
Definition: ald_dma.h:237
dma_cycle_ctrl_t
dma_cycle_ctrl_t
The operating mode of the DMA cycle.
Definition: ald_dma.h:235
DMA_MSEL_TIMER0
Definition: ald_dma.h:94
DMA_R_POWER_1024
Definition: ald_dma.h:261
DMA_MSIGSEL_EXTI_3
Definition: ald_dma.h:119
DMA_MSIGSEL_CRYPT_WRITE
Definition: ald_dma.h:132
DMA_MSIGSEL_SPI_RNR
Definition: ald_dma.h:141
DMA_MSIGSEL_EXTI_8
Definition: ald_dma.h:124
DMA_DATA_INC_BYTE
Definition: ald_dma.h:217
dma_descriptor_t::use
uint32_t use
Definition: ald_dma.h:210
DMA_MSIGSEL_TIMER_CH3
Definition: ald_dma.h:147
DMA_MSEL_TIMER3
Definition: ald_dma.h:97
DMA_MSIGSEL_EXTI_4
Definition: ald_dma.h:120
dma_descriptor_t::src
void * src
Definition: ald_dma.h:207
DMA_MSIGSEL_QSPI_READ
Definition: ald_dma.h:171
DMA_MSEL_UART3
Definition: ald_dma.h:87
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
DMA_MSEL_GPIO
Definition: ald_dma.h:79
DMA_CYCLE_CTRL_PER_SG_ALTERNATE
Definition: ald_dma.h:243
DMA_MSEL_TIMER1
Definition: ald_dma.h:95
DMA_CYCLE_CTRL_PINGPONG
Definition: ald_dma.h:239
DMA_MSEL_CRYPT
Definition: ald_dma.h:80
DMA_MSIGSEL_PIS_CH9
Definition: ald_dma.h:163
dma_descrp_cplt_t
dma_descrp_cplt_t
Descriptor complete state.
Definition: ald_dma.h:309
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
DMA_MSIGSEL_EXTI_14
Definition: ald_dma.h:130
DMA_R_POWER_16
Definition: ald_dma.h:255
DMA_MSIGSEL_ADC
Definition: ald_dma.h:136
DMA_MSEL_ADC0
Definition: ald_dma.h:82
DMA_MSEL_CRC
Definition: ald_dma.h:83
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
flag_status_t
flag_status_t
Definition: type.h:37
DMA_MSIGSEL_NONE
Definition: ald_dma.h:115
dma_descriptor_t
Channel control data structure.
Definition: ald_dma.h:206
DMA_MSIGSEL_SPI_TXEMPTY
Definition: ald_dma.h:142
DMA_MSIGSEL_EP_RX4
Definition: ald_dma.h:180
dma_ctrl_t::cycle_ctrl
uint32_t cycle_ctrl
Definition: ald_dma.h:189
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
dma_arbiter_config_t
dma_arbiter_config_t
Control how many DMA transfers can occur before the controller re-arbitrates.
Definition: ald_dma.h:250
dma_ctrl_t::R_power
uint32_t R_power
Definition: ald_dma.h:192
DMA_CYCLE_CTRL_NONE
Definition: ald_dma.h:236
DMA_MSIGSEL_PIS_CH5
Definition: ald_dma.h:159
DMA_MSIGSEL_PIS_CH14
Definition: ald_dma.h:168
DMA_MSEL_I2C1
Definition: ald_dma.h:93
dma_msel_t
dma_msel_t
Input source to DMA channel.
Definition: ald_dma.h:77
DMA_MSIGSEL_DAC0_CH1
Definition: ald_dma.h:135
dac_handle_s::cbk
void(* cbk)(struct dac_handle_s *arg, uint32_t event)
Definition: ald_dac.h:196
DMA_MSIGSEL_TIMER_TRI
Definition: ald_dma.h:149
dma_config_t::interrupt
type_func_t interrupt
Definition: ald_dma.h:288
ald_dma_config_auto
void ald_dma_config_auto(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is automatic. This mode is used to carry data from memory to memory.
Definition: ald_dma.c:392
DMA_MSEL_TIMER5
Definition: ald_dma.h:101
ald_dma_get_it_status
it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel)
Check whether the specified channel interrupt is set or reset.
Definition: ald_dma.c:911
DMA_MSEL_SPI0
Definition: ald_dma.h:90
DMA_MSIGSEL_PIS_CH15
Definition: ald_dma.h:169
DMA_MSIGSEL_EXTI_2
Definition: ald_dma.h:118
DMA_MSIGSEL_EP_TX5
Definition: ald_dma.h:176
DMA_MSEL_UART2
Definition: ald_dma.h:86
DMA_CYCLE_CTRL_AUTO
Definition: ald_dma.h:238
ald_dma_config_sg_per
void ald_dma_config_sg_per(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst, dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is peripheral scatter-gather...
Definition: ald_dma.c:765
ald_dma_config_auto_easy
void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, uint8_t channel, void(*cbk)(void *arg))
Configure DMA channel according to the specified parameter. The DMA mode is automatic. This mode is used to carry data from memory to memory. If User want use the dma easily, they can invoke this function.
Definition: ald_dma.c:464
ald_dma_reset
void ald_dma_reset(DMA_TypeDef *DMAx)
Reset the DMA register.
Definition: ald_dma.c:242
DMA_MSIGSEL_CRYPT_READ
Definition: ald_dma.h:133
DMA_R_POWER_2
Definition: ald_dma.h:252
DMA_R_POWER_8
Definition: ald_dma.h:254
dma_ctrl_t::n_minus_1
uint32_t n_minus_1
Definition: ald_dma.h:191
dma_call_back_t
Callback function pointer and param.
Definition: ald_dma.h:267
DMA_MSIGSEL_LPUART_RNR
Definition: ald_dma.h:152
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
DMA_MSIGSEL_QSPI_WRITE
Definition: ald_dma.h:170
DMA_R_POWER_1
Definition: ald_dma.h:251
DMA_CYCLE_CTRL_MEM_SG_ALTERNATE
Definition: ald_dma.h:241
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
DMA_MSIGSEL_EXTI_7
Definition: ald_dma.h:123
DMA_MSIGSEL_PIS_CH12
Definition: ald_dma.h:166
DMA_MSIGSEL_LPUART_TXEMPTY
Definition: ald_dma.h:153
DMA_R_POWER_32
Definition: ald_dma.h:256
ald_dma_channel_config
void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state)
Configure channel enable or disable. It will unbind descriptor with channel, when channel has been di...
Definition: ald_dma.c:850


ALD User Manual: D:/svn/src/ald_ebi.c Source File

  • D:
  • svn
  • src
ald_ebi.c
Go to the documentation of this file.
1
16 #include "ald_ebi.h"
17
26 #ifdef ALD_EBI
27
43 void ald_ebi_nor_sram_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_init_t *init)
44 {
45 assert_param(IS_EBI_NORSRAM_DEVICE(dev));
46 assert_param(IS_EBI_NORSRAM_BANK(init->bank));
47 assert_param(IS_EBI_MUX(init->mux));
48 assert_param(IS_EBI_MEMORY(init->type));
49 assert_param(IS_EBI_NORSRAM_MEMORY_WIDTH(init->width));
50 assert_param(IS_EBI_BURSTMODE(init->acc_mode));
51 assert_param(IS_EBI_WAIT_POLARITY(init->polarity));
52 assert_param(IS_EBI_WRAP_MODE(init->wrap_mode));
53 assert_param(IS_EBI_WAIT_SIGNAL_ACTIVE(init->active));
54 assert_param(IS_EBI_WRITE_OPERATION(init->write));
55 assert_param(IS_EBI_WAITE_SIGNAL(init->signal));
56 assert_param(IS_EBI_EXTENDED_MODE(init->ext_mode));
57 assert_param(IS_EBI_ASYNWAIT(init->wait));
58 assert_param(IS_EBI_WRITE_BURST(init->burst));
59
60 /* Disable NORSRAM device */
61 ald_ebi_nor_sram_disable(dev, init->bank);
62
63 /* Set NORSRAM device control parameters */
64 if (init->type == EBI_MEMORY_TYPE_NOR) {
65 MODIFY_REG(dev->BTCR[init->bank], BCTRLR_CLEAR_MASK, (uint32_t)((uint32_t)EBI_NORSRAM_FLASH_ACCESS_ENABLE
66 | (uint32_t)init->mux
67 | (uint32_t)init->type
68 | (uint32_t)init->width
69 | (uint32_t)init->acc_mode
70 | (uint32_t)init->polarity
71 | (uint32_t)init->wrap_mode
72 | (uint32_t)init->active
73 | (uint32_t)init->write
74 | (uint32_t)init->signal
75 | (uint32_t)init->ext_mode
76 | (uint32_t)init->wait
77 | (uint32_t)init->burst));
78 }
79 else {
80 MODIFY_REG(dev->BTCR[init->bank], BCTRLR_CLEAR_MASK, (uint32_t)(EBI_NORSRAM_FLASH_ACCESS_DISABLE
81 | (uint32_t)init->mux
82 | (uint32_t)init->type
83 | (uint32_t)init->width
84 | (uint32_t)init->acc_mode
85 | (uint32_t)init->polarity
86 | (uint32_t)init->wrap_mode
87 | (uint32_t)init->active
88 | (uint32_t)init->write
89 | (uint32_t)init->signal
90 | (uint32_t)init->ext_mode
91 | (uint32_t)init->wait
92 | (uint32_t)init->burst));
93 }
94 }
95
104 void ald_ebi_nor_sram_timing_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank)
105 {
106 assert_param(IS_EBI_NORSRAM_DEVICE(dev));
107 assert_param(IS_EBI_ADDRESS_SETUP_TIME(timing->addr_setup));
108 assert_param(IS_EBI_ADDRESS_HOLD_TIME(timing->addr_hold));
109 assert_param(IS_EBI_DATASETUP_TIME(timing->data_setup));
110 assert_param(IS_EBI_TURNAROUND_TIME(timing->bus_dur));
111 assert_param(IS_EBI_DATA_LATENCY(timing->latency));
112 assert_param(IS_EBI_ACCESS_MODE(timing->mode));
113 assert_param(IS_EBI_NORSRAM_BANK(bank));
114
115 /* Set EBI_NORSRAM device timing parameters */
116 MODIFY_REG(dev->BTCR[bank + 1U], BTR_CLEAR_MASK, \
117 (uint32_t)(timing->addr_setup | \
118 ((timing->addr_hold) << EBI_BTRx_ADDHOLD_POSS) | \
119 ((timing->data_setup) << EBI_BTRx_DATAHOLD_POSS) | \
120 ((timing->bus_dur) << EBI_BTRx_BUSTURN_POSS) | \
121 (((timing->div) - 1U) << EBI_BTRx_CLKDIV_POSS) | \
122 (((timing->latency) - 1U) << EBI_BTRx_DATALAT_POSS) | \
123 (timing->mode)));
124 }
125
138 void ald_ebi_nor_sram_ext_timing_init(EBI_NOR_SRAM_EXTENDED_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank, uint32_t mode)
139 {
140 assert_param(IS_EBI_EXTENDED_MODE(mode));
141
142 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
143 if (mode == EBI_EXTENDED_MODE_ENABLE) {
144 assert_param(IS_EBI_NORSRAM_EXTENDED_DEVICE(dev));
145 assert_param(IS_EBI_ADDRESS_SETUP_TIME(timing->addr_setup));
146 assert_param(IS_EBI_ADDRESS_HOLD_TIME(timing->addr_hold));
147 assert_param(IS_EBI_DATASETUP_TIME(timing->data_setup));
148 assert_param(IS_EBI_TURNAROUND_TIME(timing->bus_dur));
149 assert_param(IS_EBI_ACCESS_MODE(timing->mode));
150 assert_param(IS_EBI_NORSRAM_BANK(bank));
151
152 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
153 MODIFY_REG(dev->BWTR[bank], BWTR_CLEAR_MASK, \
154 (uint32_t)(timing->addr_setup | \
155 ((timing->addr_hold) << EBI_BWRTRx_ADDHOLD_POSS) | \
156 ((timing->data_setup) << EBI_BWRTRx_DATAHOLD_POSS) | \
157 timing->mode | \
158 ((timing->bus_dur) << EBI_BWRTRx_BUSTURN_POSS)));
159 }
160 else {
161 dev->BWTR[bank] = 0x0FFFFFFFU;
162 }
163 }
164
172 ald_status_t ald_ebi_nor_sram_deinit(EBI_NOR_SRAM_TypeDef *dev, EBI_NOR_SRAM_EXTENDED_TypeDef *e_dev, uint32_t bank)
173 {
174 assert_param(IS_EBI_NORSRAM_DEVICE(dev));
175 assert_param(IS_EBI_NORSRAM_EXTENDED_DEVICE(e_dev));
176 assert_param(IS_EBI_NORSRAM_BANK(bank));
177
178 /* Disable the EBI_NOR/SRAM device */
179 ald_ebi_nor_sram_disable(dev, bank);
180
181 /* De-initialize the EBI_NOR/SRAM device */
182 if (bank == EBI_NORSRAM_BANK1)
183 dev->BTCR[bank] = 0x000030DBU;
184 else
185 dev->BTCR[bank] = 0x000030D2U;
186
187 dev->BTCR[bank + 1U] = 0x0FFFFFFFU;
188 e_dev->BWTR[bank] = 0x0FFFFFFFU;
189
190 return OK;
191 }
206 void ald_ebi_nor_sram_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
207 {
208 assert_param(IS_EBI_NORSRAM_DEVICE(dev));
209 assert_param(IS_EBI_NORSRAM_BANK(bank));
210
211 SET_BIT(dev->BTCR[bank], EBI_BCTRLRx_MEMBKEN_MSK);
212 }
213
220 void ald_ebi_nor_sram_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
221 {
222 assert_param(IS_EBI_NORSRAM_DEVICE(dev));
223 assert_param(IS_EBI_NORSRAM_BANK(bank));
224
225 CLEAR_BIT(dev->BTCR[bank], EBI_BCTRLRx_MEMBKEN_MSK);
226 }
227
234 void ald_ebi_nor_sram_write_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
235 {
236 assert_param(IS_EBI_NORSRAM_DEVICE(dev));
237 assert_param(IS_EBI_NORSRAM_BANK(bank));
238
239 /* Enable write operation */
240 SET_BIT(dev->BTCR[bank], EBI_WRITE_OPERATION_ENABLE);
241 }
242
249 void ald_ebi_nor_sram_write_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
250 {
251 assert_param(IS_EBI_NORSRAM_DEVICE(dev));
252 assert_param(IS_EBI_NORSRAM_BANK(bank));
253
254 /* Disable write operation */
255 CLEAR_BIT(dev->BTCR[bank], EBI_WRITE_OPERATION_ENABLE);
256 }
272 void ald_ebi_nand_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_init_t *init)
273 {
274 assert_param(IS_EBI_NAND_DEVICE(dev));
275 assert_param(IS_EBI_NAND_BANK(init->bank));
276 assert_param(IS_EBI_WAIT_FEATURE(init->wait));
277 assert_param(IS_EBI_NAND_MEMORY_WIDTH(init->width));
278 assert_param(IS_EBI_ECC_STATE(init->ecc));
279 assert_param(IS_EBI_ECCPAGE_SIZE(init->size));
280 assert_param(IS_EBI_TCLR_TIME(init->cle_time));
281 assert_param(IS_EBI_TAR_TIME(init->ale_time));
282
283 /* Set NAND device control parameters */
284 if (init->bank == EBI_NAND_BANK2) {
285 MODIFY_REG(dev->PCTRLR2, PCTRLR_CLEAR_MASK, ((uint32_t)init->wait |
286 (uint32_t)EBI_PCTRLR_MEMORY_TYPE_NAND |
287 (uint32_t)init->width |
288 (uint32_t)init->ecc |
289 (uint32_t)init->size |
290 (uint32_t)((init->cle_time) << EBI_PCTRLRx_CRDLY_POSS) |
291 (uint32_t)((init->ale_time) << EBI_PCTRLRx_ARDLY_POSS)));
292 }
293 else {
294 MODIFY_REG(dev->PCTRLR3, PCTRLR_CLEAR_MASK, ((uint32_t)init->wait |
295 (uint32_t)EBI_PCTRLR_MEMORY_TYPE_NAND |
296 (uint32_t)init->width |
297 (uint32_t)init->ecc |
298 (uint32_t)init->size |
299 (uint32_t)((init->cle_time) << EBI_PCTRLRx_CRDLY_POSS) |
300 (uint32_t)((init->ale_time) << EBI_PCTRLRx_ARDLY_POSS)));
301 }
302 }
303
312 void ald_ebi_nand_comm_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
313 {
314 assert_param(IS_EBI_NAND_DEVICE(dev));
315 assert_param(IS_EBI_SETUP_TIME(timing->time));
316 assert_param(IS_EBI_WAIT_TIME(timing->wait_time));
317 assert_param(IS_EBI_HOLD_TIME(timing->hold_time));
318 assert_param(IS_EBI_HIZ_TIME(timing->hiz_time));
319 assert_param(IS_EBI_NAND_BANK(bank));
320
321 /* Set EBI_NAND device timing parameters */
322 if (bank == EBI_NAND_BANK2) {
323 MODIFY_REG(dev->PMEMR2, PMEMR_CLEAR_MASK, (timing->time | \
324 ((timing->wait_time) << EBI_PMEMRx_MEMWAIT_POSS) | \
325 ((timing->hold_time) << EBI_PMEMRx_MEMHOLD_POSS) | \
326 ((timing->hiz_time) << EBI_PMEMRx_MEMHIZT_POSS)));
327 }
328 else {
329 MODIFY_REG(dev->PMEMR3, PMEMR_CLEAR_MASK, (timing->time | \
330 ((timing->wait_time) << EBI_PMEMRx_MEMWAIT_POSS) | \
331 ((timing->hold_time) << EBI_PMEMRx_MEMHOLD_POSS) | \
332 ((timing->hiz_time) << EBI_PMEMRx_MEMHIZT_POSS)));
333 }
334 }
335
344 void ald_ebi_nand_attr_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
345 {
346 assert_param(IS_EBI_NAND_DEVICE(dev));
347 assert_param(IS_EBI_SETUP_TIME(timing->time));
348 assert_param(IS_EBI_WAIT_TIME(timing->wait_time));
349 assert_param(IS_EBI_HOLD_TIME(timing->hold_time));
350 assert_param(IS_EBI_HIZ_TIME(timing->hiz_time));
351 assert_param(IS_EBI_NAND_BANK(bank));
352
353 /* Set FMC_NAND device timing parameters */
354 if (bank == EBI_NAND_BANK2) {
355 MODIFY_REG(dev->PATTR2, PATTR_CLEAR_MASK, (timing->time | \
356 ((timing->wait_time) << EBI_PATTRx_ATTWAIT_POSS) | \
357 ((timing->hold_time) << EBI_PATTRx_ATTHOLD_POSS) | \
358 ((timing->hiz_time) << EBI_PATTRx_ATTHIZT_POSS)));
359 }
360 else {
361 MODIFY_REG(dev->PATTR3, PATTR_CLEAR_MASK, (timing->time | \
362 ((timing->wait_time) << EBI_PATTRx_ATTWAIT_POSS) | \
363 ((timing->hold_time) << EBI_PATTRx_ATTHOLD_POSS) | \
364 ((timing->hiz_time) << EBI_PATTRx_ATTHIZT_POSS)));
365 }
366 }
367
374 void ald_ebi_nand_deinit(EBI_NAND_TypeDef *dev, uint32_t bank)
375 {
376 assert_param(IS_EBI_NAND_DEVICE(dev));
377 assert_param(IS_EBI_NAND_BANK(bank));
378
379 /* Disable the NAND Bank */
380 ald_ebi_nand_disable(dev, bank);
381
382 /* De-initialize the NAND Bank */
383 if (bank == EBI_NAND_BANK2) {
384 /* Set the EBI_NAND_BANK2 registers to their reset values */
385 WRITE_REG(dev->PCTRLR2, 0x00000018U);
386 WRITE_REG(dev->STAR2, 0x00000040U);
387 WRITE_REG(dev->PMEMR2, 0xFCFCFCFCU);
388 WRITE_REG(dev->PATTR2, 0xFCFCFCFCU);
389 }
390 /* EBI_Bank3_NAND */
391 else {
392 /* Set the EBI_NAND_BANK3 registers to their reset values */
393 WRITE_REG(dev->PCTRLR3, 0x00000018U);
394 WRITE_REG(dev->STAR3, 0x00000040U);
395 WRITE_REG(dev->PMEMR3, 0xFCFCFCFCU);
396 WRITE_REG(dev->PATTR3, 0xFCFCFCFCU);
397 }
398 }
413 void ald_ebi_nand_enable(EBI_NAND_TypeDef *dev, uint32_t bank)
414 {
415 assert_param(IS_EBI_NAND_DEVICE(dev));
416 assert_param(IS_EBI_NAND_BANK(bank));
417
418 if (bank == EBI_NAND_BANK2)
419 SET_BIT(dev->PCTRLR2, EBI_PCTRLRx_MEMBKEN_MSK);
420 else
421 SET_BIT(dev->PCTRLR3, EBI_PCTRLRx_MEMBKEN_MSK);
422 }
423
430 void ald_ebi_nand_disable(EBI_NAND_TypeDef *dev, uint32_t bank)
431 {
432 assert_param(IS_EBI_NAND_DEVICE(dev));
433 assert_param(IS_EBI_NAND_BANK(bank));
434
435 if (bank == EBI_NAND_BANK2)
436 CLEAR_BIT(dev->PCTRLR2, EBI_PCTRLRx_MEMBKEN_MSK);
437 else
438 CLEAR_BIT(dev->PCTRLR3, EBI_PCTRLRx_MEMBKEN_MSK);
439 }
440
452 void ald_ebi_nand_enable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it)
453 {
454 assert_param(IS_EBI_NAND_DEVICE(dev));
455 assert_param(IS_EBI_NAND_BANK(bank));
456
457 if (bank == EBI_NAND_BANK2)
458 SET_BIT(dev->STAR2, it);
459 else
460 SET_BIT(dev->STAR3, it);
461 }
462
474 void ald_ebi_nand_disable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it)
475 {
476 assert_param(IS_EBI_NAND_DEVICE(dev));
477 assert_param(IS_EBI_NAND_BANK(bank));
478
479 if (bank == EBI_NAND_BANK2)
480 CLEAR_BIT(dev->STAR2, it);
481 else
482 CLEAR_BIT(dev->STAR3, it);
483 }
484
491 void ald_ebi_nand_ecc_enable(EBI_NAND_TypeDef *dev, uint32_t bank)
492 {
493 assert_param(IS_EBI_NAND_DEVICE(dev));
494 assert_param(IS_EBI_NAND_BANK(bank));
495
496 /* Enable ECC feature */
497 if (bank == EBI_NAND_BANK2)
498 SET_BIT(dev->PCTRLR2, EBI_PCTRLRx_ECCEN_MSK);
499 else
500 SET_BIT(dev->PCTRLR3, EBI_PCTRLRx_ECCEN_MSK);
501 }
502
509 void ald_ebi_nand_ecc_disable(EBI_NAND_TypeDef *dev, uint32_t bank)
510 {
511 assert_param(IS_EBI_NAND_DEVICE(dev));
512 assert_param(IS_EBI_NAND_BANK(bank));
513
514 /* Disable ECC feature */
515 if (bank == EBI_NAND_BANK2)
516 CLEAR_BIT(dev->PCTRLR2, EBI_PCTRLRx_ECCEN_MSK);
517 else
518 CLEAR_BIT(dev->PCTRLR3, EBI_PCTRLRx_ECCEN_MSK);
519 }
520
529 ald_status_t ald_ebi_nand_get_ecc(EBI_NAND_TypeDef *dev, uint32_t *val, uint32_t bank, uint32_t timeout)
530 {
531 uint32_t tick;
532
533 assert_param(IS_EBI_NAND_DEVICE(dev));
534 assert_param(IS_EBI_NAND_BANK(bank));
535
536 tick = ald_get_tick();
537
538 /* Wait until FIFO is empty */
539 while (ald_ebi_nand_get_flag(dev, bank, EBI_FLAG_FEMPT) == RESET) {
540 if (timeout != ALD_MAX_DELAY) {
541 if ((timeout == 0U) || ((ald_get_tick() - tick) > timeout))
542 return TIMEOUT;
543 }
544 }
545
546 if (bank == EBI_NAND_BANK2)
547 *val = (uint32_t)dev->ECCRESULT2;
548 else
549 *val = (uint32_t)dev->ECCRESULT3;
550
551 return OK;
552 }
553
568 flag_status_t ald_ebi_nand_get_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
569 {
570 assert_param(IS_EBI_NAND_DEVICE(dev));
571 assert_param(IS_EBI_NAND_BANK(bank));
572
573 if (bank == EBI_NAND_BANK2) {
574 if (dev->STAR2 & flag)
575 return SET;
576 } else {
577 if (dev->STAR3 & flag)
578 return SET;
579 }
580
581 return RESET;
582 }
583
596 void ald_ebi_nand_clear_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
597 {
598 assert_param(IS_EBI_NAND_DEVICE(dev));
599 assert_param(IS_EBI_NAND_BANK(bank));
600
601 /* Enable ECC feature */
602 if (bank == EBI_NAND_BANK2)
603 CLEAR_BIT(dev->STAR2, flag);
604 else
605 CLEAR_BIT(dev->STAR3, flag);
606 }
621 void ald_ebi_lcd_init(ebi_lcd_handle_t *hlcd)
622 {
623 assert_param(IS_EBI_LCD_DEVICE(hlcd->inst));
624 assert_param(IS_EBI_BANK_NUMBER(hlcd->init.bank));
625 assert_param(IS_EBI_HORIZONTAL_SYNCH(hlcd->init.h_polarity));
626 assert_param(IS_EBI_VERTICAL_SYNCH(hlcd->init.v_polarity));
627 assert_param(IS_EBI_DATA_ENABLE(hlcd->init.data_polarity));
628 assert_param(IS_EBI_LCD_ENABLE(hlcd->init.enable));
629 assert_param(IS_EBI_DATA_CLOCK(hlcd->init.clk_polarity));
630 assert_param(IS_EBI_LCD_DATASETUP_TIME(hlcd->init.setup));
631 assert_param(IS_EBI_HYSNC_PULSE_WIDTH(hlcd->init.h_width));
632 assert_param(IS_EBI_VSYNC_PULSE_WIDTH(hlcd->init.v_width));
633 assert_param(IS_EBI_FRAME_LINE_NUMBER(hlcd->init.nr_line));
634 assert_param(IS_EBI_FRAME_PIXEL_NUMBER(hlcd->init.nr_pixel));
635
636 MODIFY_REG(hlcd->inst->LCDCRCFGS[(hlcd->init.bank - 1)*4], LCDCTRL_CLEAR_MASK,
637 ((uint32_t)hlcd->init.h_polarity |
638 (uint32_t)hlcd->init.v_polarity |
639 hlcd->init.data_polarity |
640 hlcd->init.enable |
641 hlcd->init.clk_polarity |
642 hlcd->init.setup << EBI_LCDCTRLx_DATASETUP_POSS |
643 hlcd->init.h_width << EBI_LCDCTRLx_VSYNCWID_POSS |
644 hlcd->init.v_width << EBI_LCDCTRLx_HSYNCWID_POSS));
645
646 WRITE_REG(hlcd->inst->LCDCRCFGS[(hlcd->init.bank - 1)*4 + 1],
647 (hlcd->init.nr_line << EBI_LCDSTx_LINECNT_POSS |
648 hlcd->init.nr_pixel << EBI_LCDSTx_PXLCNT_POSS));
649 }
650
656 void ald_ebi_lcd_reset(ebi_lcd_handle_t *hlcd)
657 {
658 assert_param(IS_EBI_LCD_RESET(hlcd->init.reset));
659 assert_param(IS_EBI_BANK_NUMBER(hlcd->init.bank));
660
661 SET_BIT(hlcd->inst->LCDCRCFGS[(hlcd->init.bank - 1)*4], hlcd->init.reset);
662 }
663
670 #endif
671
IS_EBI_MUX
#define IS_EBI_MUX(x)
Definition: ald_ebi.h:425
EBI_FLAG_FEMPT
Definition: ald_ebi.h:318
ebi_lcd_init_t::v_width
uint8_t v_width
Definition: ald_ebi.h:381
IS_EBI_TAR_TIME
#define IS_EBI_TAR_TIME(x)
Definition: ald_ebi.h:473
ald_ebi_nor_sram_init_t::mux
ebi_data_address_mux_t mux
Definition: ald_ebi.h:400
IS_EBI_WAIT_SIGNAL_ACTIVE
#define IS_EBI_WAIT_SIGNAL_ACTIVE(x)
Definition: ald_ebi.h:487
ald_ebi_nand_init_t::size
ebi_md_ecc_page_size_t size
Definition: ald_ebi.h:163
IS_EBI_EXTENDED_MODE
#define IS_EBI_EXTENDED_MODE(x)
Definition: ald_ebi.h:493
ald_ebi_nand_disable_it
void ald_ebi_nand_disable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it)
Disable the NAND device interrupt.
Definition: ald_ebi.c:474
OK
Definition: utils.h:55
EBI_NORSRAM_FLASH_ACCESS_ENABLE
Definition: ald_ebi.h:219
EBI_WRITE_OPERATION_ENABLE
Definition: ald_ebi.h:259
EBI_NOR_SRAM_TypeDef
#define EBI_NOR_SRAM_TypeDef
Definition: ald_ebi.h:40
ald_ebi_lcd_init
void ald_ebi_lcd_init(ebi_lcd_handle_t *hlcd)
Initializes the EBI_LCD device according to the specified control parameters in the nor_lcd_handle_t...
Definition: ald_ebi.c:621
IS_EBI_HYSNC_PULSE_WIDTH
#define IS_EBI_HYSNC_PULSE_WIDTH(x)
Definition: ald_ebi.h:467
IS_EBI_WAIT_FEATURE
#define IS_EBI_WAIT_FEATURE(x)
Definition: ald_ebi.h:441
EBI_NOR_SRAM_EXTENDED_TypeDef
#define EBI_NOR_SRAM_EXTENDED_TypeDef
Definition: ald_ebi.h:41
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_EBI_DATA_CLOCK
#define IS_EBI_DATA_CLOCK(x)
Definition: ald_ebi.h:464
ald_ebi_nand_ecc_disable
void ald_ebi_nand_ecc_disable(EBI_NAND_TypeDef *dev, uint32_t bank)
Disables dynamically EBI_NAND ECC feature.
Definition: ald_ebi.c:509
ald_ebi_nand_timing_t::hiz_time
uint32_t hiz_time
Definition: ald_ebi.h:175
IS_EBI_ECCPAGE_SIZE
#define IS_EBI_ECCPAGE_SIZE(x)
Definition: ald_ebi.h:447
SET
Definition: type.h:39
ebi_lcd_handle_t::init
ebi_lcd_init_t init
Definition: ald_ebi.h:392
IS_EBI_WAIT_POLARITY
#define IS_EBI_WAIT_POLARITY(x)
Definition: ald_ebi.h:483
ALD_MAX_DELAY
#define ALD_MAX_DELAY
Definition: utils.h:88
IS_EBI_ASYNWAIT
#define IS_EBI_ASYNWAIT(x)
Definition: ald_ebi.h:495
IS_EBI_DATASETUP_TIME
#define IS_EBI_DATASETUP_TIME(x)
Definition: ald_ebi.h:501
ebi_lcd_handle_t
NOR LCD handle Structure definition.
Definition: ald_ebi.h:390
BWTR_CLEAR_MASK
#define BWTR_CLEAR_MASK
Definition: ald_ebi.h:80
IS_EBI_NORSRAM_MEMORY_WIDTH
#define IS_EBI_NORSRAM_MEMORY_WIDTH(x)
Definition: ald_ebi.h:430
ald_ebi_nand_timing_t::time
uint32_t time
Definition: ald_ebi.h:172
ald_ebi_nand_disable
void ald_ebi_nand_disable(EBI_NAND_TypeDef *dev, uint32_t bank)
Disable the NAND device access.
Definition: ald_ebi.c:430
EBI_EXTENDED_MODE_ENABLE
Definition: ald_ebi.h:275
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
IS_EBI_WAITE_SIGNAL
#define IS_EBI_WAITE_SIGNAL(x)
Definition: ald_ebi.h:491
ald_ebi_nor_sram_deinit
ald_status_t ald_ebi_nor_sram_deinit(EBI_NOR_SRAM_TypeDef *dev, EBI_NOR_SRAM_EXTENDED_TypeDef *e_dev, uint32_t bank)
DeInitialize the EBI_NOR_SRAM peripheral.
Definition: ald_ebi.c:172
ald_ebi_nor_sram_init_t::signal
ebi_wait_signal_t signal
Definition: ald_ebi.h:408
IS_EBI_WAIT_TIME
#define IS_EBI_WAIT_TIME(x)
Definition: ald_ebi.h:475
BCTRLR_CLEAR_MASK
#define BCTRLR_CLEAR_MASK
Definition: ald_ebi.h:66
ald_ebi_nand_enable
void ald_ebi_nand_enable(EBI_NAND_TypeDef *dev, uint32_t bank)
Enable the NAND device access.
Definition: ald_ebi.c:413
ald_ebi_nor_sram_init_t
EBI NORSRAM Configuration Structure definition.
Definition: ald_ebi.h:398
IS_EBI_WRITE_OPERATION
#define IS_EBI_WRITE_OPERATION(x)
Definition: ald_ebi.h:489
ald_ebi_nor_sram_timing_t::addr_hold
uint32_t addr_hold
Definition: ald_ebi.h:111
IS_EBI_SETUP_TIME
#define IS_EBI_SETUP_TIME(x)
Definition: ald_ebi.h:474
RESET
Definition: type.h:38
ebi_lcd_init_t::nr_line
uint16_t nr_line
Definition: ald_ebi.h:383
ald_ebi_nor_sram_init_t::ext_mode
ebi_extended_mode_t ext_mode
Definition: ald_ebi.h:409
ald_ebi_nor_sram_timing_t::mode
ebi_access_mode_t mode
Definition: ald_ebi.h:116
ald_ebi_nand_init_t::ale_time
uint32_t ale_time
Definition: ald_ebi.h:165
ald_ebi_nor_sram_write_enable
void ald_ebi_nor_sram_write_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Enables dynamically NOR-FLASH/SRAM write operation.
Definition: ald_ebi.c:234
ald_ebi_nand_init_t::width
ebi_nand_mem_bus_width_t width
Definition: ald_ebi.h:161
IS_EBI_ECC_STATE
#define IS_EBI_ECC_STATE(x)
Definition: ald_ebi.h:445
ald_ebi_nor_sram_timing_t::data_setup
uint32_t data_setup
Definition: ald_ebi.h:112
IS_EBI_LCD_ENABLE
#define IS_EBI_LCD_ENABLE(x)
Definition: ald_ebi.h:460
ald_ebi_nor_sram_timing_init
void ald_ebi_nor_sram_timing_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank)
Initialize the EBI_NOR_SRAM Timing according to the specified parameters in the EBI_NOR_SRAM_TimingTy...
Definition: ald_ebi.c:104
ebi_lcd_init_t::nr_pixel
uint16_t nr_pixel
Definition: ald_ebi.h:384
ald_ebi_nor_sram_timing_t::div
uint32_t div
Definition: ald_ebi.h:114
ebi_lcd_init_t::reset
ebi_lcd_lcdint_t reset
Definition: ald_ebi.h:379
EBI_NORSRAM_FLASH_ACCESS_DISABLE
Definition: ald_ebi.h:218
ald_ebi_nand_comm_timing_init
void ald_ebi_nand_comm_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
Initializes the EBI_NAND Common space Timing according to the specified parameters in the EBI_NAND_Ti...
Definition: ald_ebi.c:312
ald_ebi_nand_enable_it
void ald_ebi_nand_enable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it)
Enable the NAND device interrupt.
Definition: ald_ebi.c:452
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159
ald_ebi_nand_timing_t::hold_time
uint32_t hold_time
Definition: ald_ebi.h:174
ald_ebi_nor_sram_init_t::burst
ebi_write_burst_t burst
Definition: ald_ebi.h:411
IS_EBI_DATA_LATENCY
#define IS_EBI_DATA_LATENCY(x)
Definition: ald_ebi.h:498
ald_ebi_nand_init_t
EBI NAND Configuration Structure definition.
Definition: ald_ebi.h:158
ald_ebi_nor_sram_init_t::polarity
ebi_wait_signal_polarity_t polarity
Definition: ald_ebi.h:404
ald_ebi_nor_sram_write_disable
void ald_ebi_nor_sram_write_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Disables dynamically EBI_NORSRAM write operation.
Definition: ald_ebi.c:249
EBI_NAND_TypeDef
#define EBI_NAND_TypeDef
Definition: ald_ebi.h:42
ald_ebi_nand_ecc_enable
void ald_ebi_nand_ecc_enable(EBI_NAND_TypeDef *dev, uint32_t bank)
Enables dynamically EBI_NAND ECC feature.
Definition: ald_ebi.c:491
IS_EBI_NAND_DEVICE
#define IS_EBI_NAND_DEVICE(x)
Definition: ald_ebi.h:480
BTR_CLEAR_MASK
#define BTR_CLEAR_MASK
Definition: ald_ebi.h:74
IS_EBI_LCD_RESET
#define IS_EBI_LCD_RESET(x)
Definition: ald_ebi.h:462
IS_EBI_VSYNC_PULSE_WIDTH
#define IS_EBI_VSYNC_PULSE_WIDTH(x)
Definition: ald_ebi.h:468
IS_EBI_FRAME_PIXEL_NUMBER
#define IS_EBI_FRAME_PIXEL_NUMBER(x)
Definition: ald_ebi.h:470
ebi_lcd_init_t::h_polarity
ebi_lcd_hsyncpol_t h_polarity
Definition: ald_ebi.h:374
IS_EBI_BANK_NUMBER
#define IS_EBI_BANK_NUMBER(x)
Definition: ald_ebi.h:503
ald_ebi_nor_sram_init_t::wait
ebi_asynchronous_wait_t wait
Definition: ald_ebi.h:410
PATTR_CLEAR_MASK
#define PATTR_CLEAR_MASK
Definition: ald_ebi.h:62
ald_ebi_nand_init
void ald_ebi_nand_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_init_t *init)
Initializes the EBI_NAND device according to the specified control parameters in the EBI_NAND_HandleT...
Definition: ald_ebi.c:272
IS_EBI_ADDRESS_HOLD_TIME
#define IS_EBI_ADDRESS_HOLD_TIME(x)
Definition: ald_ebi.h:500
ald_ebi_nor_sram_init_t::active
ebi_wait_timing_t active
Definition: ald_ebi.h:406
ald_ebi_nand_init_t::cle_time
uint32_t cle_time
Definition: ald_ebi.h:164
ald_ebi_nor_sram_timing_t::bus_dur
uint32_t bus_dur
Definition: ald_ebi.h:113
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
ebi_it_t
ebi_it_t
EBI Interrupt definition.
Definition: ald_ebi.h:305
ald_ebi_nor_sram_timing_t::latency
uint32_t latency
Definition: ald_ebi.h:115
IS_EBI_DATA_ENABLE
#define IS_EBI_DATA_ENABLE(x)
Definition: ald_ebi.h:458
ald_ebi_nor_sram_init_t::wrap_mode
ebi_wrap_mode_t wrap_mode
Definition: ald_ebi.h:405
ebi_lcd_init_t::bank
uint8_t bank
Definition: ald_ebi.h:373
IS_EBI_TCLR_TIME
#define IS_EBI_TCLR_TIME(x)
Definition: ald_ebi.h:472
PMEMR_CLEAR_MASK
#define PMEMR_CLEAR_MASK
Definition: ald_ebi.h:58
IS_EBI_NAND_MEMORY_WIDTH
#define IS_EBI_NAND_MEMORY_WIDTH(x)
Definition: ald_ebi.h:443
IS_EBI_VERTICAL_SYNCH
#define IS_EBI_VERTICAL_SYNCH(x)
Definition: ald_ebi.h:456
ebi_lcd_init_t::enable
ebi_lcd_lcden_t enable
Definition: ald_ebi.h:377
EBI_MEMORY_TYPE_NOR
Definition: ald_ebi.h:202
IS_EBI_HORIZONTAL_SYNCH
#define IS_EBI_HORIZONTAL_SYNCH(x)
Definition: ald_ebi.h:454
IS_EBI_LCD_DEVICE
#define IS_EBI_LCD_DEVICE(x)
Definition: ald_ebi.h:453
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
ald_ebi_nand_get_flag
flag_status_t ald_ebi_nand_get_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
Get flag status of the NAND device.
Definition: ald_ebi.c:568
ald_ebi_nand_attr_timing_init
void ald_ebi_nand_attr_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
Initializes the EBI_NAND Attribute space Timing according to the specified parameters in the EBI_NAND...
Definition: ald_ebi.c:344
ald_ebi_nand_clear_flag
void ald_ebi_nand_clear_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
Clear flag status of the NAND device.
Definition: ald_ebi.c:596
IS_EBI_ACCESS_MODE
#define IS_EBI_ACCESS_MODE(x)
Definition: ald_ebi.h:435
ald_ebi_nand_get_ecc
ald_status_t ald_ebi_nand_get_ecc(EBI_NAND_TypeDef *dev, uint32_t *val, uint32_t bank, uint32_t timeout)
Disables dynamically EBI_NAND ECC feature.
Definition: ald_ebi.c:529
ald_ebi_nand_deinit
void ald_ebi_nand_deinit(EBI_NAND_TypeDef *dev, uint32_t bank)
DeInitializes the EBI_NAND device.
Definition: ald_ebi.c:374
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
EBI_PCTRLR_MEMORY_TYPE_NAND
Definition: ald_ebi.h:299
IS_EBI_MEMORY
#define IS_EBI_MEMORY(x)
Definition: ald_ebi.h:427
IS_EBI_NORSRAM_BANK
#define IS_EBI_NORSRAM_BANK(x)
Definition: ald_ebi.h:421
ald_ebi_nor_sram_init_t::write
ebi_write_operation_t write
Definition: ald_ebi.h:407
ald_ebi_nor_sram_init
void ald_ebi_nor_sram_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_init_t *init)
Initialize the EBI_NOR_SRAM device according to the specified control parameters in the EBI_NOR_SRAM_...
Definition: ald_ebi.c:43
ebi_lcd_init_t::data_polarity
ebi_lcd_denpol_t data_polarity
Definition: ald_ebi.h:376
IS_EBI_WRAP_MODE
#define IS_EBI_WRAP_MODE(x)
Definition: ald_ebi.h:485
IS_EBI_NORSRAM_EXTENDED_DEVICE
#define IS_EBI_NORSRAM_EXTENDED_DEVICE(x)
Definition: ald_ebi.h:479
flag_status_t
flag_status_t
Definition: type.h:37
IS_EBI_LCD_DATASETUP_TIME
#define IS_EBI_LCD_DATASETUP_TIME(x)
Definition: ald_ebi.h:466
ald_ebi_nor_sram_init_t::acc_mode
ebi_burst_access_mode_t acc_mode
Definition: ald_ebi.h:403
ald_ebi_nand_init_t::ecc
ebi_nand_ecc_t ecc
Definition: ald_ebi.h:162
ald_ebi_nor_sram_init_t::width
ebi_norsram_mem_bus_width_t width
Definition: ald_ebi.h:402
IS_EBI_HOLD_TIME
#define IS_EBI_HOLD_TIME(x)
Definition: ald_ebi.h:476
ald_ebi_nand_timing_t
EBI NAND Timing parameters structure definition.
Definition: ald_ebi.h:171
ebi_lcd_init_t::v_polarity
ebi_lcd_vsyncpol_t v_polarity
Definition: ald_ebi.h:375
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
IS_EBI_BURSTMODE
#define IS_EBI_BURSTMODE(x)
Definition: ald_ebi.h:481
ebi_lcd_init_t::h_width
uint8_t h_width
Definition: ald_ebi.h:382
ald_ebi.h
Header file of EBI module driver.
LCDCTRL_CLEAR_MASK
#define LCDCTRL_CLEAR_MASK
Definition: ald_ebi.h:84
IS_EBI_NAND_BANK
#define IS_EBI_NAND_BANK(x)
Definition: ald_ebi.h:439
ebi_lcd_init_t::setup
uint8_t setup
Definition: ald_ebi.h:380
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
ald_ebi_nand_init_t::wait
ebi_nand_wait_feature_t wait
Definition: ald_ebi.h:160
ald_ebi_nor_sram_timing_t
EBI NORSRAM Timing parameters structure definition.
Definition: ald_ebi.h:109
ebi_flag_t
ebi_flag_t
EBI Flag definition.
Definition: ald_ebi.h:314
IS_EBI_WRITE_BURST
#define IS_EBI_WRITE_BURST(x)
Definition: ald_ebi.h:433
PCTRLR_CLEAR_MASK
#define PCTRLR_CLEAR_MASK
Definition: ald_ebi.h:52
ebi_lcd_handle_t::inst
EBI_LCD_TypeDef * inst
Definition: ald_ebi.h:391
ald_ebi_nor_sram_timing_t::addr_setup
uint32_t addr_setup
Definition: ald_ebi.h:110
ald_ebi_nor_sram_init_t::type
ebi_memory_type_t type
Definition: ald_ebi.h:401
ald_ebi_nor_sram_disable
void ald_ebi_nor_sram_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Disable the NORSRAM device access.
Definition: ald_ebi.c:220
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399
IS_EBI_HIZ_TIME
#define IS_EBI_HIZ_TIME(x)
Definition: ald_ebi.h:477
IS_EBI_NORSRAM_DEVICE
#define IS_EBI_NORSRAM_DEVICE(x)
Definition: ald_ebi.h:478
ald_ebi_nor_sram_enable
void ald_ebi_nor_sram_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Enable the NOR/SRAM device access.
Definition: ald_ebi.c:206
IS_EBI_ADDRESS_SETUP_TIME
#define IS_EBI_ADDRESS_SETUP_TIME(x)
Definition: ald_ebi.h:499
IS_EBI_FRAME_LINE_NUMBER
#define IS_EBI_FRAME_LINE_NUMBER(x)
Definition: ald_ebi.h:469
EBI_NORSRAM_BANK1
Definition: ald_ebi.h:190
ebi_lcd_init_t::clk_polarity
ebi_lcd_dclkpol_t clk_polarity
Definition: ald_ebi.h:378
IS_EBI_TURNAROUND_TIME
#define IS_EBI_TURNAROUND_TIME(x)
Definition: ald_ebi.h:502
ald_ebi_lcd_reset
void ald_ebi_lcd_reset(ebi_lcd_handle_t *hlcd)
Reset the EBI_LCD.
Definition: ald_ebi.c:656
ald_ebi_nor_sram_ext_timing_init
void ald_ebi_nor_sram_ext_timing_init(EBI_NOR_SRAM_EXTENDED_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank, uint32_t mode)
Initialize the EBI_NOR_SRAM Extended mode Timing according to the specified parameters in the EBI_NOR...
Definition: ald_ebi.c:138
ald_ebi_nand_timing_t::wait_time
uint32_t wait_time
Definition: ald_ebi.h:173


ALD User Manual: D:/svn/src/ald_ebi.h Source File

  • D:
  • svn
  • src
ald_ebi.h
Go to the documentation of this file.
1
18 #ifndef __ALD_EBI_H__
19 #define __ALD_EBI_H__
20
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24
25 #include "utils.h"
26
27
40 #define EBI_NOR_SRAM_TypeDef EBI_Bank1_TypeDef
41 #define EBI_NOR_SRAM_EXTENDED_TypeDef EBI_Bank1E_TypeDef
42 #define EBI_NAND_TypeDef EBI_Bank2_3_TypeDef
43 #define EBI_LCD_TypeDef EBI_Bank1_LCD_TypeDef
44 #define EBI_NOR_SRAM_DEVICE EBI_Bank1
45 #define EBI_NOR_SRAM_EXTENDED_DEVICE EBI_Bank1E
46 #define EBI_NAND_DEVICE EBI_Bank2_3
47 #define EBI_LCD_DEVICE EBI_Bank1_LCD
48 #define EBI_NAND_BANK2 0x00000010U
49 #define EBI_NAND_BANK3 0x00000100U
50
51 /* PCTRLR register clear mask */
52 #define PCTRLR_CLEAR_MASK ((uint32_t)(EBI_PCTRLRx_WAITEN_MSK | EBI_PCTRLRx_MEMBKEN_MSK | \
53 EBI_PCTRLRx_MEMTYP_MSK | EBI_PCTRLRx_DATBUSWID_MSK | \
54 EBI_PCTRLRx_ECCEN_MSK | EBI_PCTRLRx_CRDLY_MSK | \
55 EBI_PCTRLRx_ARDLY_MSK | EBI_PCTRLRx_ECCPSIZE_MSK))
56
57 /* PMEMR register clear mask */
58 #define PMEMR_CLEAR_MASK ((uint32_t)(EBI_PMEMRx_MEMSETUP_MSK | EBI_PMEMRx_MEMWAIT_MSK | \
59 EBI_PMEMRx_MEMHOLD_MSK | EBI_PMEMRx_MEMHIZT_MSK))
60
61 /* PATTR register clear mask */
62 #define PATTR_CLEAR_MASK ((uint32_t)(EBI_PATTRx_ATTSETUP_MSK | EBI_PATTRx_ATTWAIT_MSK | \
63 EBI_PATTRx_ATTHOLD_MSK | EBI_PATTRx_ATTHIZT_MSK))
64
65 /* BCTRLR register clear mask */
66 #define BCTRLR_CLEAR_MASK ((uint32_t)(EBI_BCTRLRx_FLASHACCEN_MSK | EBI_BCTRLRx_MUXEN_MSK | \
67 EBI_BCTRLRx_MEMTYP_MSK | EBI_BCTRLRx_MEMWID_MSK | \
68 EBI_BCTRLRx_BURSTEN_MSK | EBI_BCTRLRx_WAITPOL_MSK | \
69 EBI_BCTRLRx_WRAPMODE_MSK | EBI_BCTRLRx_WAITCFG_MSK | \
70 EBI_BCTRLRx_WREN_MSK | EBI_BCTRLRx_WAITEN_MSK | \
71 EBI_BCTRLRx_EXTMODEN_MSK | EBI_BCTRLRx_ASYNCWAIT_MSK | \
72 EBI_BCTRLRx_RWCBURSTEN_MSK))
73 /* BTR register clear mask */
74 #define BTR_CLEAR_MASK ((uint32_t)(EBI_BTRx_ADDATASETUP_MSK | EBI_BTRx_ADDHOLD_MSK | \
75 EBI_BTRx_DATAHOLD_MSK | EBI_BTRx_BUSTURN_MSK | \
76 EBI_BTRx_CLKDIV_MSK | EBI_BTRx_DATALAT_MSK | \
77 EBI_BTRx_ACCMODE_MSK))
78
79 /* BWRTR register clear mask */
80 #define BWTR_CLEAR_MASK ((uint32_t)(EBI_BWRTRx_ADDATASETUP_MSK | EBI_BWRTRx_ADDHOLD_MSK | \
81 EBI_BWRTRx_DATAHOLD_MSK | EBI_BWRTRx_BUSTURN_MSK | \
82 EBI_BWRTRx_ACCMODE_MSK))
83
84 #define LCDCTRL_CLEAR_MASK ((uint32_t)(EBI_LCDCTRLx_HSYNCPOL_POS | EBI_LCDCTRLx_VSYNCPOL_MSK | \
85 EBI_LCDCTRLx_DENPOL_MSK | EBI_LCDCTRLx_LCDEN_MSK | \
86 EBI_LCDCTRLx_LCDINT_MSK | EBI_LCDCTRLx_DCLKPOL_MSK | \
87 EBI_LCDCTRLx_DATASETUP_MSK))
88
99 typedef enum {
100 EBI_ACCESS_MODE_A = 0x0U,
101 EBI_ACCESS_MODE_B = (0x1U << 28),
102 EBI_ACCESS_MODE_C = (0x2U << 28),
103 EBI_ACCESS_MODE_D = (0x3U << 28),
104 } ebi_access_mode_t;
105
109 typedef struct {
110 uint32_t addr_setup;
111 uint32_t addr_hold;
112 uint32_t data_setup;
113 uint32_t bus_dur;
114 uint32_t div;
115 uint32_t latency;
116 ebi_access_mode_t mode;
117 } ald_ebi_nor_sram_timing_t;
118
122 typedef enum {
123 EBI_NAND_WAIT_FEATURE_DISABLE = 0x0U,
124 EBI_NAND_WAIT_FEATURE_ENABLE = (0x1U << 1),
125 } ebi_nand_wait_feature_t;
126
130 typedef enum {
131 EBI_NAND_MEM_BUS_WIDTH_8 = 0x0U,
132 EBI_NAND_MEM_BUS_WIDTH_16 = (0x3U << 4),
133 } ebi_nand_mem_bus_width_t;
134
138 typedef enum {
139 EBI_NAND_ECC_DISABLE = 0U,
140 EBI_NAND_ECC_ENABLE = (0x1U << 6),
141 } ebi_nand_ecc_t;
142
146 typedef enum {
147 EBI_NAND_ECC_PAGE_SIZE_256BYTE = 0U,
148 EBI_NAND_ECC_PAGE_SIZE_512BYTE = (0x1U << 17),
149 EBI_NAND_ECC_PAGE_SIZE_1024BYTE = (0x2U << 17),
150 EBI_NAND_ECC_PAGE_SIZE_2048BYTE = (0x3U << 17),
151 EBI_NAND_ECC_PAGE_SIZE_4096BYTE = (0x4U << 17),
152 EBI_NAND_ECC_PAGE_SIZE_8192BYTE = (0x5U << 17),
153 } ebi_md_ecc_page_size_t;
154
158 typedef struct {
159 uint32_t bank;
160 ebi_nand_wait_feature_t wait;
161 ebi_nand_mem_bus_width_t width;
162 ebi_nand_ecc_t ecc;
163 ebi_md_ecc_page_size_t size;
164 uint32_t cle_time;
165 uint32_t ale_time;
166 } ald_ebi_nand_init_t;
167
171 typedef struct {
172 uint32_t time;
173 uint32_t wait_time;
174 uint32_t hold_time;
175 uint32_t hiz_time;
176 } ald_ebi_nand_timing_t;
177
181 typedef enum {
182 EBI_DATA_ADDRESS_MUX_DISABLE = 0x0U,
183 EBI_DATA_ADDRESS_MUX_ENABLE = (0x1U << 1),
184 } ebi_data_address_mux_t;
185
189 typedef enum {
190 EBI_NORSRAM_BANK1 = 0x0U,
191 EBI_NORSRAM_BANK2 = 0x2U,
192 EBI_NORSRAM_BANK3 = 0x4U,
193 EBI_NORSRAM_BANK4 = 0x6U,
194 } ebi_norsram_bank_t;
195
199 typedef enum {
200 EBI_MEMORY_TYPE_SRAM = 0x0U,
201 EBI_MEMORY_TYPE_PSRAM = (0x1U << 2),
202 EBI_MEMORY_TYPE_NOR = (0x2U << 2),
203 } ebi_memory_type_t;
204
208 typedef enum {
209 EBI_NORSRAM_MEM_BUS_WIDTH_8 = 0x0U,
210 EBI_NORSRAM_MEM_BUS_WIDTH_16 = (0x1U << 4),
211 EBI_NORSRAM_MEM_BUS_WIDTH_32 = (0x2U << 4),
212 } ebi_norsram_mem_bus_width_t;
213
217 typedef enum {
218 EBI_NORSRAM_FLASH_ACCESS_DISABLE = 0x0U,
219 EBI_NORSRAM_FLASH_ACCESS_ENABLE = (0x1U << 6),
220 } ebi_norsram_flash_access_t;
221
225 typedef enum {
226 EBI_BURST_ACCESS_MODE_DISABLE = 0x0U,
227 EBI_BURST_ACCESS_MODE_ENABLE = (0x1U << 8),
228 } ebi_burst_access_mode_t;
229
233 typedef enum {
234 EBI_WAIT_SIGNAL_POLARITY_LOW = 0x0U,
235 EBI_WAIT_SIGNAL_POLARITY_HIGH = (0x1U << 9),
236 } ebi_wait_signal_polarity_t;
237
241 typedef enum {
242 EBI_WRAP_MODE_DISABLE = 0x0U,
243 EBI_WRAP_MODE_ENABLE = (0x1U << 10),
244 } ebi_wrap_mode_t;
245
249 typedef enum {
250 EBI_WAIT_TIMING_BEFORE_WS = 0x0U,
251 EBI_WAIT_TIMING_DURING_WS = (0x1U << 11),
252 } ebi_wait_timing_t;
253
257 typedef enum {
258 EBI_WRITE_OPERATION_DISABLE = 0x0U,
259 EBI_WRITE_OPERATION_ENABLE = (0x1U << 12),
260 } ebi_write_operation_t;
261
265 typedef enum {
266 EBI_WAIT_SIGNAL_DISABLE = 0x0U,
267 EBI_WAIT_SIGNAL_ENABLE = (0x1U << 13),
268 } ebi_wait_signal_t;
269
273 typedef enum {
274 EBI_EXTENDED_MODE_DISABLE = 0x0U,
275 EBI_EXTENDED_MODE_ENABLE = (0x1U << 14),
276 } ebi_extended_mode_t;
277
281 typedef enum {
282 EBI_ASYNCHRONOUS_WAIT_DISABLE = 0x0U,
283 EBI_ASYNCHRONOUS_WAIT_ENABLE = (0x1U << 15),
284 } ebi_asynchronous_wait_t;
285
289 typedef enum {
290 EBI_WRITE_BURST_DISABLE = 0x0U,
291 EBI_WRITE_BURST_ENABLE = (0x1U << 19),
292 } ebi_write_burst_t;
293
297 typedef enum {
298 EBI_PCTRLR_MEMORY_TYPE_None = 0x0U,
299 EBI_PCTRLR_MEMORY_TYPE_NAND = (0x1U << 3),
300 } ebi_pctrlr_memory_type_t;
301
305 typedef enum {
306 EBI_IT_RISING_EDGE = (1U << 3),
307 EBI_IT_LEVEL = (1U << 4),
308 EBI_IT_FALLING_EDGE = (1U << 5),
309 } ebi_it_t;
310
314 typedef enum {
315 EBI_FLAG_RISING_EDGE = (1U << 0),
316 EBI_FLAG_LEVEL = (1U << 1),
317 EBI_FLAG_FALLING_EDGE = (1U << 2),
318 EBI_FLAG_FEMPT = (1U << 6),
319 } ebi_flag_t;
320
324 typedef enum {
325 EBI_LCD_HSYNCPOL_LOW = 0x0U,
326 EBI_LCD_HSYNCPOL_HIGH = (0x1U << 29),
327 } ebi_lcd_hsyncpol_t;
328
332 typedef enum {
333 EBI_LCD_VSYNCPOL_LOW = 0x0U,
334 EBI_LCD_VSYNCPOL_HIGH = (0x1U << 28),
335 } ebi_lcd_vsyncpol_t;
336
340 typedef enum {
341 EBI_LCD_DENPOL_LOW = 0x0U,
342 EBI_LCD_DENPOL_HIGH = (0x1U << 27),
343 } ebi_lcd_denpol_t;
344
348 typedef enum {
349 EBI_LCD_LCDEN_DISABLE = 0x0U,
350 EBI_LCD_LCDEN_ENABLE = (0x1U << 26),
351 } ebi_lcd_lcden_t;
352
356 typedef enum {
357 EBI_LCD_LCDINT_DISABLE = 0x0U,
358 EBI_LCD_LCDINT_ENABLE = (0x1 << 25),
359 } ebi_lcd_lcdint_t;
360
364 typedef enum {
365 EBI_LCD_DCLKPOL_FALLING = 0x0U,
366 EBI_LCD_DCLKPOL_RISING = (0x1U << 24),
367 } ebi_lcd_dclkpol_t;
368
372 typedef struct {
373 uint8_t bank;
374 ebi_lcd_hsyncpol_t h_polarity;
375 ebi_lcd_vsyncpol_t v_polarity;
376 ebi_lcd_denpol_t data_polarity;
377 ebi_lcd_lcden_t enable;
378 ebi_lcd_dclkpol_t clk_polarity;
379 ebi_lcd_lcdint_t reset;
380 uint8_t setup;
381 uint8_t v_width;
382 uint8_t h_width;
383 uint16_t nr_line;
384 uint16_t nr_pixel;
385 } ebi_lcd_init_t;
386
390 typedef struct {
391 EBI_LCD_TypeDef *inst;
392 ebi_lcd_init_t init;
393 } ebi_lcd_handle_t;
394
398 typedef struct {
399 uint32_t bank;
400 ebi_data_address_mux_t mux;
401 ebi_memory_type_t type;
402 ebi_norsram_mem_bus_width_t width;
403 ebi_burst_access_mode_t acc_mode;
404 ebi_wait_signal_polarity_t polarity;
405 ebi_wrap_mode_t wrap_mode;
406 ebi_wait_timing_t active;
407 ebi_write_operation_t write;
408 ebi_wait_signal_t signal;
409 ebi_extended_mode_t ext_mode;
410 ebi_asynchronous_wait_t wait;
411 ebi_write_burst_t burst;
412 } ald_ebi_nor_sram_init_t;
413
421 #define IS_EBI_NORSRAM_BANK(x) (((x) == EBI_NORSRAM_BANK1) || \
422 ((x) == EBI_NORSRAM_BANK2) || \
423 ((x) == EBI_NORSRAM_BANK3) || \
424 ((x) == EBI_NORSRAM_BANK4))
425 #define IS_EBI_MUX(x) (((x) == EBI_DATA_ADDRESS_MUX_DISABLE) || \
426 ((x) == EBI_DATA_ADDRESS_MUX_ENABLE))
427 #define IS_EBI_MEMORY(x) (((x) == EBI_MEMORY_TYPE_SRAM) || \
428 ((x) == EBI_MEMORY_TYPE_PSRAM) || \
429 ((x) == EBI_MEMORY_TYPE_NOR))
430 #define IS_EBI_NORSRAM_MEMORY_WIDTH(x) (((x) == EBI_NORSRAM_MEM_BUS_WIDTH_8) || \
431 ((x) == EBI_NORSRAM_MEM_BUS_WIDTH_16) || \
432 ((x) == EBI_NORSRAM_MEM_BUS_WIDTH_32))
433 #define IS_EBI_WRITE_BURST(x) (((x) == EBI_WRITE_BURST_DISABLE) || \
434 ((x) == EBI_WRITE_BURST_ENABLE))
435 #define IS_EBI_ACCESS_MODE(x) (((x) == EBI_ACCESS_MODE_A) || \
436 ((x) == EBI_ACCESS_MODE_B) || \
437 ((x) == EBI_ACCESS_MODE_C) || \
438 ((x) == EBI_ACCESS_MODE_D))
439 #define IS_EBI_NAND_BANK(x) (((x) == EBI_NAND_BANK2) || \
440 ((x) == EBI_NAND_BANK3))
441 #define IS_EBI_WAIT_FEATURE(x) (((x) == EBI_NAND_WAIT_FEATURE_DISABLE) || \
442 ((x) == EBI_NAND_WAIT_FEATURE_ENABLE))
443 #define IS_EBI_NAND_MEMORY_WIDTH(x) (((x) == EBI_NAND_MEM_BUS_WIDTH_8) || \
444 ((x) == EBI_NAND_MEM_BUS_WIDTH_16))
445 #define IS_EBI_ECC_STATE(x) (((x) == EBI_NAND_ECC_DISABLE) || \
446 ((x) == EBI_NAND_ECC_ENABLE))
447 #define IS_EBI_ECCPAGE_SIZE(x) (((x) == EBI_NAND_ECC_PAGE_SIZE_256BYTE) || \
448 ((x) == EBI_NAND_ECC_PAGE_SIZE_512BYTE) || \
449 ((x) == EBI_NAND_ECC_PAGE_SIZE_1024BYTE) || \
450 ((x) == EBI_NAND_ECC_PAGE_SIZE_2048BYTE) || \
451 ((x) == EBI_NAND_ECC_PAGE_SIZE_4096BYTE) || \
452 ((x) == EBI_NAND_ECC_PAGE_SIZE_8192BYTE))
453 #define IS_EBI_LCD_DEVICE(x) ((x) == EBI_LCD_DEVICE)
454 #define IS_EBI_HORIZONTAL_SYNCH(x) (((x) == EBI_LCD_HSYNCPOL_LOW) || \
455 ((x) == EBI_LCD_HSYNCPOL_HIGH))
456 #define IS_EBI_VERTICAL_SYNCH(x) (((x) == EBI_LCD_VSYNCPOL_LOW) || \
457 ((x) == EBI_LCD_VSYNCPOL_HIGH))
458 #define IS_EBI_DATA_ENABLE(x) (((x) == EBI_LCD_DENPOL_LOW) || \
459 ((x) == EBI_LCD_DENPOL_HIGH))
460 #define IS_EBI_LCD_ENABLE(x) (((x) == EBI_LCD_LCDEN_DISABLE) || \
461 ((x) == EBI_LCD_LCDEN_ENABLE))
462 #define IS_EBI_LCD_RESET(x) (((x) == EBI_LCD_LCDINT_DISABLE) || \
463 ((x) == EBI_LCD_LCDINT_ENABLE))
464 #define IS_EBI_DATA_CLOCK(x) (((x) == EBI_LCD_DCLKPOL_FALLING) || \
465 ((x) == EBI_LCD_DCLKPOL_RISING))
466 #define IS_EBI_LCD_DATASETUP_TIME(x) ((x) < 255U)
467 #define IS_EBI_HYSNC_PULSE_WIDTH(x) ((x) < 255U)
468 #define IS_EBI_VSYNC_PULSE_WIDTH(x) ((x) < 255U)
469 #define IS_EBI_FRAME_LINE_NUMBER(x) (((x) >= 1U) && ((x) < 65535))
470 #define IS_EBI_FRAME_PIXEL_NUMBER(x) (((x) >= 1U) && ((x) < 65535))
471
472 #define IS_EBI_TCLR_TIME(x) ((x) <= 255U)
473 #define IS_EBI_TAR_TIME(x) ((x) <= 255U)
474 #define IS_EBI_SETUP_TIME(x) ((x) <= 255U)
475 #define IS_EBI_WAIT_TIME(x) ((x) <= 255U)
476 #define IS_EBI_HOLD_TIME(x) ((x) <= 255U)
477 #define IS_EBI_HIZ_TIME(x) ((x) <= 255U)
478 #define IS_EBI_NORSRAM_DEVICE(x) ((x) == EBI_NOR_SRAM_DEVICE)
479 #define IS_EBI_NORSRAM_EXTENDED_DEVICE(x) ((x) == EBI_NOR_SRAM_EXTENDED_DEVICE)
480 #define IS_EBI_NAND_DEVICE(x) ((x) == EBI_NAND_DEVICE)
481 #define IS_EBI_BURSTMODE(x) (((x) == EBI_BURST_ACCESS_MODE_DISABLE) || \
482 ((x) == EBI_BURST_ACCESS_MODE_ENABLE))
483 #define IS_EBI_WAIT_POLARITY(x) (((x) == EBI_WAIT_SIGNAL_POLARITY_LOW) || \
484 ((x) == EBI_WAIT_SIGNAL_POLARITY_HIGH))
485 #define IS_EBI_WRAP_MODE(x) (((x) == EBI_WRAP_MODE_DISABLE) || \
486 ((x) == EBI_WRAP_MODE_ENABLE))
487 #define IS_EBI_WAIT_SIGNAL_ACTIVE(x) (((x) == EBI_WAIT_TIMING_BEFORE_WS) || \
488 ((x) == EBI_WAIT_TIMING_DURING_WS))
489 #define IS_EBI_WRITE_OPERATION(x) (((x) == EBI_WRITE_OPERATION_DISABLE) || \
490 ((x) == EBI_WRITE_OPERATION_ENABLE))
491 #define IS_EBI_WAITE_SIGNAL(x) (((x) == EBI_WAIT_SIGNAL_DISABLE) || \
492 ((x) == EBI_WAIT_SIGNAL_ENABLE))
493 #define IS_EBI_EXTENDED_MODE(x) (((x) == EBI_EXTENDED_MODE_DISABLE) || \
494 ((x) == EBI_EXTENDED_MODE_ENABLE))
495 #define IS_EBI_ASYNWAIT(x) (((x) == EBI_ASYNCHRONOUS_WAIT_DISABLE) || \
496 ((x) == EBI_ASYNCHRONOUS_WAIT_ENABLE))
497 #define IS_EBI_CLK_DIV(x) (((x) >= 1U) && ((x) <= 16U))
498 #define IS_EBI_DATA_LATENCY(x) (((x) >= 1U) && ((x) <= 17U))
499 #define IS_EBI_ADDRESS_SETUP_TIME(x) ((x) <= 15U)
500 #define IS_EBI_ADDRESS_HOLD_TIME(x) (((x) > 0U) && ((x) <= 15U))
501 #define IS_EBI_DATASETUP_TIME(x) (((x) > 0U) && ((x) <= 255U))
502 #define IS_EBI_TURNAROUND_TIME(x) ((x) <= 15U)
503 #define IS_EBI_BANK_NUMBER(x) (((x) > 0U) && ((x) <= 4U))
504
515 /* NOR-FLASH SRAM initialize functions */
516 void ald_ebi_nor_sram_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_init_t *init);
517 void ald_ebi_nor_sram_timing_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank);
518 void ald_ebi_nor_sram_ext_timing_init(EBI_NOR_SRAM_EXTENDED_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank, uint32_t mode);
519 ald_status_t ald_ebi_nor_sram_deinit(EBI_NOR_SRAM_TypeDef *dev, EBI_NOR_SRAM_EXTENDED_TypeDef *e_dev, uint32_t bank);
527 /* NOR/SRAM Control functions */
528 void ald_ebi_nor_sram_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank);
529 void ald_ebi_nor_sram_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank);
530 void ald_ebi_nor_sram_write_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank);
531 void ald_ebi_nor_sram_write_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank);
539 /* NAND-FLASH initialize functions */
540 void ald_ebi_nand_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_init_t *init);
541 void ald_ebi_nand_comm_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank);
542 void ald_ebi_nand_attr_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank);
543 void ald_ebi_nand_deinit(EBI_NAND_TypeDef *dev, uint32_t bank);
551 /* NAND-FLASH control functions */
552 void ald_ebi_nand_enable(EBI_NAND_TypeDef *dev, uint32_t bank);
553 void ald_ebi_nand_disable(EBI_NAND_TypeDef *dev, uint32_t bank);
554 void ald_ebi_nand_enable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it);
555 void ald_ebi_nand_disable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it);
556 void ald_ebi_nand_ecc_enable(EBI_NAND_TypeDef *dev, uint32_t bank);
557 void ald_ebi_nand_ecc_disable(EBI_NAND_TypeDef *dev, uint32_t bank);
558 ald_status_t ald_ebi_nand_get_ecc(EBI_NAND_TypeDef *dev, uint32_t *val, uint32_t bank, uint32_t timeout);
559 flag_status_t ald_ebi_nand_get_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag);
560 void ald_ebi_nand_clear_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag);
568 void ald_ebi_lcd_init(ebi_lcd_handle_t *hlcd);
569 void ald_ebi_lcd_reset(ebi_lcd_handle_t *hlcd);
582 #ifdef __cplusplus
583 }
584 #endif
585
586 #endif /* __ALD_EBI_H__ */
EBI_FLAG_FEMPT
Definition: ald_ebi.h:318
ebi_norsram_mem_bus_width_t
ebi_norsram_mem_bus_width_t
EBI NOR/SRAM Data Width.
Definition: ald_ebi.h:208
ebi_lcd_init_t::v_width
uint8_t v_width
Definition: ald_ebi.h:381
EBI_NAND_ECC_PAGE_SIZE_8192BYTE
Definition: ald_ebi.h:152
ald_ebi_nor_sram_init_t::mux
ebi_data_address_mux_t mux
Definition: ald_ebi.h:400
ald_ebi_nand_init_t::size
ebi_md_ecc_page_size_t size
Definition: ald_ebi.h:163
EBI_DATA_ADDRESS_MUX_ENABLE
Definition: ald_ebi.h:183
ald_ebi_nand_disable_it
void ald_ebi_nand_disable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it)
Disable the NAND device interrupt.
Definition: ald_ebi.c:474
EBI_LCD_VSYNCPOL_HIGH
Definition: ald_ebi.h:334
EBI_NORSRAM_FLASH_ACCESS_ENABLE
Definition: ald_ebi.h:219
EBI_IT_RISING_EDGE
Definition: ald_ebi.h:306
EBI_WRITE_OPERATION_ENABLE
Definition: ald_ebi.h:259
EBI_NAND_WAIT_FEATURE_ENABLE
Definition: ald_ebi.h:124
EBI_NOR_SRAM_TypeDef
#define EBI_NOR_SRAM_TypeDef
Definition: ald_ebi.h:40
ald_ebi_lcd_init
void ald_ebi_lcd_init(ebi_lcd_handle_t *hlcd)
Initializes the EBI_LCD device according to the specified control parameters in the nor_lcd_handle_t...
Definition: ald_ebi.c:621
ebi_lcd_lcden_t
ebi_lcd_lcden_t
EBI LCD Enable definition.
Definition: ald_ebi.h:348
EBI_NOR_SRAM_EXTENDED_TypeDef
#define EBI_NOR_SRAM_EXTENDED_TypeDef
Definition: ald_ebi.h:41
ald_ebi_nand_ecc_disable
void ald_ebi_nand_ecc_disable(EBI_NAND_TypeDef *dev, uint32_t bank)
Disables dynamically EBI_NAND ECC feature.
Definition: ald_ebi.c:509
ald_ebi_nand_timing_t::hiz_time
uint32_t hiz_time
Definition: ald_ebi.h:175
EBI_WRITE_BURST_DISABLE
Definition: ald_ebi.h:290
ebi_lcd_denpol_t
ebi_lcd_denpol_t
EBI LCD Data Enable Polarity definition.
Definition: ald_ebi.h:340
EBI_ASYNCHRONOUS_WAIT_ENABLE
Definition: ald_ebi.h:283
ebi_asynchronous_wait_t
ebi_asynchronous_wait_t
EBI Asynchronous Wait.
Definition: ald_ebi.h:281
ebi_nand_mem_bus_width_t
ebi_nand_mem_bus_width_t
EBI NAND Data Width.
Definition: ald_ebi.h:130
ebi_lcd_handle_t::init
ebi_lcd_init_t init
Definition: ald_ebi.h:392
ebi_lcd_dclkpol_t
ebi_lcd_dclkpol_t
EBI LCD Data Clock definition.
Definition: ald_ebi.h:364
ebi_wrap_mode_t
ebi_wrap_mode_t
EBI Wrap Mode.
Definition: ald_ebi.h:241
ebi_lcd_handle_t
NOR LCD handle Structure definition.
Definition: ald_ebi.h:390
ald_ebi_nand_timing_t::time
uint32_t time
Definition: ald_ebi.h:172
EBI_ACCESS_MODE_D
Definition: ald_ebi.h:103
EBI_MEMORY_TYPE_PSRAM
Definition: ald_ebi.h:201
EBI_NORSRAM_BANK2
Definition: ald_ebi.h:191
ebi_write_operation_t
ebi_write_operation_t
EBI Write Operation State.
Definition: ald_ebi.h:257
EBI_MEMORY_TYPE_SRAM
Definition: ald_ebi.h:200
ebi_burst_access_mode_t
ebi_burst_access_mode_t
EBI Burst Access Mode.
Definition: ald_ebi.h:225
ebi_access_mode_t
ebi_access_mode_t
EBI Access Mode.
Definition: ald_ebi.h:99
ald_ebi_nand_disable
void ald_ebi_nand_disable(EBI_NAND_TypeDef *dev, uint32_t bank)
Disable the NAND device access.
Definition: ald_ebi.c:430
EBI_EXTENDED_MODE_ENABLE
Definition: ald_ebi.h:275
ald_ebi_nor_sram_deinit
ald_status_t ald_ebi_nor_sram_deinit(EBI_NOR_SRAM_TypeDef *dev, EBI_NOR_SRAM_EXTENDED_TypeDef *e_dev, uint32_t bank)
DeInitialize the EBI_NOR_SRAM peripheral.
Definition: ald_ebi.c:172
EBI_NAND_ECC_PAGE_SIZE_2048BYTE
Definition: ald_ebi.h:150
ald_ebi_nor_sram_init_t::signal
ebi_wait_signal_t signal
Definition: ald_ebi.h:408
ald_ebi_nand_enable
void ald_ebi_nand_enable(EBI_NAND_TypeDef *dev, uint32_t bank)
Enable the NAND device access.
Definition: ald_ebi.c:413
ald_ebi_nor_sram_init_t
EBI NORSRAM Configuration Structure definition.
Definition: ald_ebi.h:398
ebi_md_ecc_page_size_t
ebi_md_ecc_page_size_t
EBI ECC Page Size.
Definition: ald_ebi.h:146
EBI_WAIT_TIMING_DURING_WS
Definition: ald_ebi.h:251
ald_ebi_nor_sram_timing_t::addr_hold
uint32_t addr_hold
Definition: ald_ebi.h:111
EBI_NAND_ECC_DISABLE
Definition: ald_ebi.h:139
ebi_lcd_lcdint_t
ebi_lcd_lcdint_t
EBI LCD Init Enable definition.
Definition: ald_ebi.h:356
EBI_NORSRAM_BANK3
Definition: ald_ebi.h:192
EBI_LCD_LCDEN_DISABLE
Definition: ald_ebi.h:349
ebi_lcd_init_t::nr_line
uint16_t nr_line
Definition: ald_ebi.h:383
EBI_LCD_LCDEN_ENABLE
Definition: ald_ebi.h:350
ald_ebi_nor_sram_init_t::ext_mode
ebi_extended_mode_t ext_mode
Definition: ald_ebi.h:409
ald_ebi_nor_sram_timing_t::mode
ebi_access_mode_t mode
Definition: ald_ebi.h:116
EBI_PCTRLR_MEMORY_TYPE_None
Definition: ald_ebi.h:298
utils.h
This file contains the Utilities functions/types for the driver.
ald_ebi_nand_init_t::ale_time
uint32_t ale_time
Definition: ald_ebi.h:165
ald_ebi_nor_sram_write_enable
void ald_ebi_nor_sram_write_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Enables dynamically NOR-FLASH/SRAM write operation.
Definition: ald_ebi.c:234
ald_ebi_nand_init_t::width
ebi_nand_mem_bus_width_t width
Definition: ald_ebi.h:161
EBI_LCD_DCLKPOL_RISING
Definition: ald_ebi.h:366
ald_ebi_nor_sram_timing_t::data_setup
uint32_t data_setup
Definition: ald_ebi.h:112
ald_ebi_nor_sram_timing_init
void ald_ebi_nor_sram_timing_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank)
Initialize the EBI_NOR_SRAM Timing according to the specified parameters in the EBI_NOR_SRAM_TimingTy...
Definition: ald_ebi.c:104
ebi_pctrlr_memory_type_t
ebi_pctrlr_memory_type_t
EBI PCR Memory Type.
Definition: ald_ebi.h:297
EBI_LCD_HSYNCPOL_HIGH
Definition: ald_ebi.h:326
EBI_NAND_ECC_ENABLE
Definition: ald_ebi.h:140
ebi_lcd_init_t::nr_pixel
uint16_t nr_pixel
Definition: ald_ebi.h:384
EBI_WAIT_SIGNAL_ENABLE
Definition: ald_ebi.h:267
EBI_LCD_HSYNCPOL_LOW
Definition: ald_ebi.h:325
ald_ebi_nor_sram_timing_t::div
uint32_t div
Definition: ald_ebi.h:114
ebi_lcd_init_t::reset
ebi_lcd_lcdint_t reset
Definition: ald_ebi.h:379
EBI_WAIT_SIGNAL_DISABLE
Definition: ald_ebi.h:266
EBI_NORSRAM_FLASH_ACCESS_DISABLE
Definition: ald_ebi.h:218
ald_ebi_nand_comm_timing_init
void ald_ebi_nand_comm_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
Initializes the EBI_NAND Common space Timing according to the specified parameters in the EBI_NAND_Ti...
Definition: ald_ebi.c:312
EBI_NORSRAM_BANK4
Definition: ald_ebi.h:193
ald_ebi_nand_enable_it
void ald_ebi_nand_enable_it(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_it_t it)
Enable the NAND device interrupt.
Definition: ald_ebi.c:452
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159
ald_ebi_nand_timing_t::hold_time
uint32_t hold_time
Definition: ald_ebi.h:174
EBI_NAND_WAIT_FEATURE_DISABLE
Definition: ald_ebi.h:123
ald_ebi_nor_sram_init_t::burst
ebi_write_burst_t burst
Definition: ald_ebi.h:411
EBI_ACCESS_MODE_A
Definition: ald_ebi.h:100
EBI_EXTENDED_MODE_DISABLE
Definition: ald_ebi.h:274
ald_ebi_nand_init_t
EBI NAND Configuration Structure definition.
Definition: ald_ebi.h:158
ald_ebi_nor_sram_init_t::polarity
ebi_wait_signal_polarity_t polarity
Definition: ald_ebi.h:404
ald_ebi_nor_sram_write_disable
void ald_ebi_nor_sram_write_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Disables dynamically EBI_NORSRAM write operation.
Definition: ald_ebi.c:249
EBI_NAND_TypeDef
#define EBI_NAND_TypeDef
Definition: ald_ebi.h:42
ald_ebi_nand_ecc_enable
void ald_ebi_nand_ecc_enable(EBI_NAND_TypeDef *dev, uint32_t bank)
Enables dynamically EBI_NAND ECC feature.
Definition: ald_ebi.c:491
EBI_LCD_LCDINT_DISABLE
Definition: ald_ebi.h:357
EBI_NAND_MEM_BUS_WIDTH_16
Definition: ald_ebi.h:132
ebi_lcd_init_t
EBI LCD parameters structure definition.
Definition: ald_ebi.h:372
EBI_BURST_ACCESS_MODE_DISABLE
Definition: ald_ebi.h:226
EBI_NAND_ECC_PAGE_SIZE_512BYTE
Definition: ald_ebi.h:148
ebi_lcd_init_t::h_polarity
ebi_lcd_hsyncpol_t h_polarity
Definition: ald_ebi.h:374
ald_ebi_nor_sram_init_t::wait
ebi_asynchronous_wait_t wait
Definition: ald_ebi.h:410
ald_ebi_nand_init
void ald_ebi_nand_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_init_t *init)
Initializes the EBI_NAND device according to the specified control parameters in the EBI_NAND_HandleT...
Definition: ald_ebi.c:272
ald_ebi_nor_sram_init_t::active
ebi_wait_timing_t active
Definition: ald_ebi.h:406
ald_ebi_nand_init_t::cle_time
uint32_t cle_time
Definition: ald_ebi.h:164
EBI_LCD_DENPOL_LOW
Definition: ald_ebi.h:341
EBI_NORSRAM_MEM_BUS_WIDTH_8
Definition: ald_ebi.h:209
ald_ebi_nor_sram_timing_t::bus_dur
uint32_t bus_dur
Definition: ald_ebi.h:113
EBI_NAND_ECC_PAGE_SIZE_256BYTE
Definition: ald_ebi.h:147
ebi_it_t
ebi_it_t
EBI Interrupt definition.
Definition: ald_ebi.h:305
ebi_lcd_vsyncpol_t
ebi_lcd_vsyncpol_t
EBI LCD Vertical Synch Polarity definition.
Definition: ald_ebi.h:332
ald_ebi_nor_sram_timing_t::latency
uint32_t latency
Definition: ald_ebi.h:115
ebi_lcd_hsyncpol_t
ebi_lcd_hsyncpol_t
EBI LCD_Horizontal Synch Polarity definition.
Definition: ald_ebi.h:324
ald_ebi_nor_sram_init_t::wrap_mode
ebi_wrap_mode_t wrap_mode
Definition: ald_ebi.h:405
EBI_FLAG_FALLING_EDGE
Definition: ald_ebi.h:317
ebi_lcd_init_t::bank
uint8_t bank
Definition: ald_ebi.h:373
EBI_BURST_ACCESS_MODE_ENABLE
Definition: ald_ebi.h:227
ebi_lcd_init_t::enable
ebi_lcd_lcden_t enable
Definition: ald_ebi.h:377
EBI_MEMORY_TYPE_NOR
Definition: ald_ebi.h:202
EBI_WAIT_TIMING_BEFORE_WS
Definition: ald_ebi.h:250
EBI_NAND_MEM_BUS_WIDTH_8
Definition: ald_ebi.h:131
ald_ebi_nand_get_flag
flag_status_t ald_ebi_nand_get_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
Get flag status of the NAND device.
Definition: ald_ebi.c:568
ald_ebi_nand_attr_timing_init
void ald_ebi_nand_attr_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
Initializes the EBI_NAND Attribute space Timing according to the specified parameters in the EBI_NAND...
Definition: ald_ebi.c:344
ald_ebi_nand_clear_flag
void ald_ebi_nand_clear_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
Clear flag status of the NAND device.
Definition: ald_ebi.c:596
ebi_nand_wait_feature_t
ebi_nand_wait_feature_t
EBI_Wait_feature EBI Wait feature.
Definition: ald_ebi.h:122
ebi_memory_type_t
ebi_memory_type_t
EBI Memory Type.
Definition: ald_ebi.h:199
ald_ebi_nand_get_ecc
ald_status_t ald_ebi_nand_get_ecc(EBI_NAND_TypeDef *dev, uint32_t *val, uint32_t bank, uint32_t timeout)
Disables dynamically EBI_NAND ECC feature.
Definition: ald_ebi.c:529
ebi_norsram_bank_t
ebi_norsram_bank_t
EBI NOR/SRAM Bank.
Definition: ald_ebi.h:189
ald_ebi_nand_deinit
void ald_ebi_nand_deinit(EBI_NAND_TypeDef *dev, uint32_t bank)
DeInitializes the EBI_NAND device.
Definition: ald_ebi.c:374
EBI_NAND_ECC_PAGE_SIZE_1024BYTE
Definition: ald_ebi.h:149
EBI_PCTRLR_MEMORY_TYPE_NAND
Definition: ald_ebi.h:299
ebi_write_burst_t
ebi_write_burst_t
EBI Write Burst.
Definition: ald_ebi.h:289
EBI_NORSRAM_MEM_BUS_WIDTH_32
Definition: ald_ebi.h:211
ald_ebi_nor_sram_init_t::write
ebi_write_operation_t write
Definition: ald_ebi.h:407
EBI_IT_FALLING_EDGE
Definition: ald_ebi.h:308
ebi_extended_mode_t
ebi_extended_mode_t
EBI Extended Mode.
Definition: ald_ebi.h:273
EBI_WRITE_OPERATION_DISABLE
Definition: ald_ebi.h:258
ebi_data_address_mux_t
ebi_data_address_mux_t
EBI Data Address Bus Multiplexing.
Definition: ald_ebi.h:181
EBI_NORSRAM_MEM_BUS_WIDTH_16
Definition: ald_ebi.h:210
ald_ebi_nor_sram_init
void ald_ebi_nor_sram_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_init_t *init)
Initialize the EBI_NOR_SRAM device according to the specified control parameters in the EBI_NOR_SRAM_...
Definition: ald_ebi.c:43
ebi_wait_signal_polarity_t
ebi_wait_signal_polarity_t
EBI Wait Signal Polarity.
Definition: ald_ebi.h:233
EBI_WAIT_SIGNAL_POLARITY_HIGH
Definition: ald_ebi.h:235
EBI_LCD_LCDINT_ENABLE
Definition: ald_ebi.h:358
ebi_nand_ecc_t
ebi_nand_ecc_t
EBI NAND ECC STATE.
Definition: ald_ebi.h:138
ebi_lcd_init_t::data_polarity
ebi_lcd_denpol_t data_polarity
Definition: ald_ebi.h:376
flag_status_t
flag_status_t
Definition: type.h:37
ald_ebi_nor_sram_init_t::acc_mode
ebi_burst_access_mode_t acc_mode
Definition: ald_ebi.h:403
EBI_LCD_TypeDef
#define EBI_LCD_TypeDef
Definition: ald_ebi.h:43
ald_ebi_nand_init_t::ecc
ebi_nand_ecc_t ecc
Definition: ald_ebi.h:162
ald_ebi_nor_sram_init_t::width
ebi_norsram_mem_bus_width_t width
Definition: ald_ebi.h:402
EBI_WRITE_BURST_ENABLE
Definition: ald_ebi.h:291
ald_ebi_nand_timing_t
EBI NAND Timing parameters structure definition.
Definition: ald_ebi.h:171
ebi_lcd_init_t::v_polarity
ebi_lcd_vsyncpol_t v_polarity
Definition: ald_ebi.h:375
ebi_lcd_init_t::h_width
uint8_t h_width
Definition: ald_ebi.h:382
EBI_ACCESS_MODE_B
Definition: ald_ebi.h:101
EBI_NAND_ECC_PAGE_SIZE_4096BYTE
Definition: ald_ebi.h:151
EBI_FLAG_LEVEL
Definition: ald_ebi.h:316
ebi_norsram_flash_access_t
ebi_norsram_flash_access_t
EBI NOR/SRAM Flash Access.
Definition: ald_ebi.h:217
ebi_lcd_init_t::setup
uint8_t setup
Definition: ald_ebi.h:380
EBI_LCD_DCLKPOL_FALLING
Definition: ald_ebi.h:365
EBI_DATA_ADDRESS_MUX_DISABLE
Definition: ald_ebi.h:182
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
EBI_IT_LEVEL
Definition: ald_ebi.h:307
ald_ebi_nand_init_t::wait
ebi_nand_wait_feature_t wait
Definition: ald_ebi.h:160
EBI_FLAG_RISING_EDGE
Definition: ald_ebi.h:315
EBI_WAIT_SIGNAL_POLARITY_LOW
Definition: ald_ebi.h:234
ebi_wait_timing_t
ebi_wait_timing_t
EBI Wait Timing.
Definition: ald_ebi.h:249
ald_ebi_nor_sram_timing_t
EBI NORSRAM Timing parameters structure definition.
Definition: ald_ebi.h:109
ebi_flag_t
ebi_flag_t
EBI Flag definition.
Definition: ald_ebi.h:314
EBI_ASYNCHRONOUS_WAIT_DISABLE
Definition: ald_ebi.h:282
EBI_ACCESS_MODE_C
Definition: ald_ebi.h:102
ebi_lcd_handle_t::inst
EBI_LCD_TypeDef * inst
Definition: ald_ebi.h:391
ald_ebi_nor_sram_timing_t::addr_setup
uint32_t addr_setup
Definition: ald_ebi.h:110
EBI_WRAP_MODE_ENABLE
Definition: ald_ebi.h:243
ald_ebi_nor_sram_init_t::type
ebi_memory_type_t type
Definition: ald_ebi.h:401
ald_ebi_nor_sram_disable
void ald_ebi_nor_sram_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Disable the NORSRAM device access.
Definition: ald_ebi.c:220
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399
ald_ebi_nor_sram_enable
void ald_ebi_nor_sram_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Enable the NOR/SRAM device access.
Definition: ald_ebi.c:206
EBI_NORSRAM_BANK1
Definition: ald_ebi.h:190
ebi_lcd_init_t::clk_polarity
ebi_lcd_dclkpol_t clk_polarity
Definition: ald_ebi.h:378
ald_ebi_lcd_reset
void ald_ebi_lcd_reset(ebi_lcd_handle_t *hlcd)
Reset the EBI_LCD.
Definition: ald_ebi.c:656
ald_ebi_nor_sram_ext_timing_init
void ald_ebi_nor_sram_ext_timing_init(EBI_NOR_SRAM_EXTENDED_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank, uint32_t mode)
Initialize the EBI_NOR_SRAM Extended mode Timing according to the specified parameters in the EBI_NOR...
Definition: ald_ebi.c:138
EBI_LCD_DENPOL_HIGH
Definition: ald_ebi.h:342
ebi_wait_signal_t
ebi_wait_signal_t
EBI Wait Signal.
Definition: ald_ebi.h:265
ald_ebi_nand_timing_t::wait_time
uint32_t wait_time
Definition: ald_ebi.h:173
EBI_LCD_VSYNCPOL_LOW
Definition: ald_ebi.h:333
EBI_WRAP_MODE_DISABLE
Definition: ald_ebi.h:242


ALD User Manual: D:/svn/src/ald_flash.c Source File

  • D:
  • svn
  • src
ald_flash.c
Go to the documentation of this file.
1
36 #include "ald_flash.h"
37
38
48 #ifdef ALD_FLASH
49
50 #if defined ( __ICCARM__ )
51 #define __RAMFUNC __ramfunc
52 #else
53 #define __RAMFUNC
54 #endif
55
59 /* global variable*/
60 static op_cmd_type OP_CMD = OP_FLASH;
73 __RAMFUNC static ald_status_t flash_unlock(void)
74 {
75 uint16_t i;
76 uint16_t op_cmd = OP_CMD;
77
78 if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
79 return ERROR;
80
81 FLASH_REG_UNLOCK();
82 FLASH_IAP_ENABLE();
83 FLASH_REQ();
84
85 for (i = 0; i < 0xFFFF; i++) {
86 if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK))
87 break;
88 }
89
90 return i == 0xFFFF ? ERROR : OK;
91 }
92
97 __RAMFUNC static ald_status_t flash_lock(void)
98 {
99 uint16_t i;
100 uint16_t op_cmd = OP_CMD;
101
102 FLASH_REG_UNLOCK();
103 WRITE_REG(MSC->FLASHCR, 0x0);
104
105 for (i = 0; i < 0xFFFF; i++) {
106 if (!(READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK)))
107 break;
108 }
109
110 return i == 0xFFFF ? ERROR : OK;
111 }
112
118 __RAMFUNC ald_status_t flash_page_erase(uint32_t addr)
119 {
120 uint32_t i;
121 uint16_t op_cmd = OP_CMD;
122
123 if (flash_unlock() != OK)
124 goto end;
125
126 if (op_cmd == OP_FLASH) {
127 CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
128 MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, FLASH_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS);
129 }
130 else {
131 SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
132 MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, INFO_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS);
133 }
134
135 WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE);
136
137 for (i = 0; i < 0xFFFF; i++) {
138 if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
139 continue;
140 if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_ADDR_OV_MSK))
141 goto end;
142 if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_WRP_FLAG_MSK))
143 goto end;
144 if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_SERA_MSK))
145 break;
146 }
147
148 if (i == 0xFFFF)
149 goto end;
150
151 if (flash_lock() == ERROR)
152 goto end;
153
154 return OK;
155 end:
156 flash_lock();
157 return ERROR;
158 }
159
168 __RAMFUNC ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo)
169 {
170 uint16_t i = 0;
171 uint16_t prog_len;
172 uint32_t *p_data = data;
173 uint16_t op_cmd = OP_CMD;
174
175 if (flash_unlock() != OK)
176 goto end;
177
178 if (op_cmd == OP_FLASH)
179 CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
180 else
181 SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
182
183 MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, addr << MSC_FLASHADDR_ADDR_POSS);
184 MODIFY_REG(MSC->FLASHCR, MSC_FLASHCR_FIFOEN_MSK, fifo << MSC_FLASHCR_FIFOEN_POS);
185
186 for (prog_len = 0; prog_len < len; prog_len++) {
187 if (fifo) {
188 WRITE_REG(MSC->FLASHFIFO, p_data[0]);
189 WRITE_REG(MSC->FLASHFIFO, p_data[1]);
190 }
191 else {
192 WRITE_REG(MSC->FLASHDL, p_data[0]);
193 WRITE_REG(MSC->FLASHDH, p_data[1]);
194 WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP);
195 }
196
197 p_data += 2;
198
199 for (i = 0; i < 0xFFFF; i++) {
200 if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
201 continue;
202 if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_PROG_MSK))
203 break;
204 }
205 }
206 if (i == 0xFFFF)
207 goto end;
208
209 if (flash_lock() == ERROR)
210 goto end;
211
212 return OK;
213 end:
214 flash_lock();
215 return ERROR;
216 }
221 #endif
222
OK
Definition: utils.h:55
op_cmd_type
op_cmd_type
Definition: ald_flash.h:92
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
OP_FLASH
Definition: ald_flash.h:93
FLASH_PAGE_ADDR
#define FLASH_PAGE_ADDR(ADDR)
Definition: ald_flash.h:61
flash_page_erase
__RAMFUNC ald_status_t flash_page_erase(uint32_t addr)
Erase one page.
Definition: ald_flash.c:118
FLASH_REQ
#define FLASH_REQ()
Definition: ald_flash.h:49
ald_flash.h
Header file of FLASH driver.
__RAMFUNC
#define __RAMFUNC
Definition: ald_flash.c:53
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
flash_unlock
static __RAMFUNC ald_status_t flash_unlock(void)
Unlock the flash.
Definition: ald_flash.c:73
flash_word_program
__RAMFUNC ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo)
Programme a word.
Definition: ald_flash.c:168
FLASH_CMD_WP
Definition: ald_flash.h:84
flash_lock
static __RAMFUNC ald_status_t flash_lock(void)
Lock the flash.
Definition: ald_flash.c:97
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
FLASH_CMD_PE
Definition: ald_flash.h:83
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
INFO_PAGE_ADDR
#define INFO_PAGE_ADDR(ADDR)
Definition: ald_flash.h:67
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
ERROR
Definition: utils.h:56
FLASH_IAP_ENABLE
#define FLASH_IAP_ENABLE()
Definition: ald_flash.h:51
OP_CMD
static op_cmd_type OP_CMD
Definition: ald_flash.c:60
FLASH_REG_UNLOCK
#define FLASH_REG_UNLOCK()
Definition: ald_flash.h:38


ALD User Manual: D:/svn/src/ald_flash.h Source File

  • D:
  • svn
  • src
ald_flash.h
Go to the documentation of this file.
1
17 #ifndef __ALD_FLASH_H__
18 #define __ALD_FLASH_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25
38 #define FLASH_REG_UNLOCK() \
39 do { \
40 if (op_cmd == OP_FLASH) { \
41 WRITE_REG(MSC->FLASHKEY, 0x8ACE0246); \
42 WRITE_REG(MSC->FLASHKEY, 0x9BDF1357); \
43 } \
44 else { \
45 WRITE_REG(MSC->INFOKEY, 0x7153BFD9); \
46 WRITE_REG(MSC->INFOKEY, 0x0642CEA8); \
47 } \
48 } while (0)
49 #define FLASH_REQ() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
50 #define FLASH_REQ_FIN() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
51 #define FLASH_IAP_ENABLE() (SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
52 #define FLASH_IAP_DISABLE() (CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
53 #define FLASH_BASE_ADDR 0x00000000
54 #define FLASH_PAGE_SIZE 1024UL
55 #define FLASH_WORD_SIZE 8UL
56 #define FLASH_TOTAL_SIZE 512UL
57 #define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1)
58 #define FLASH_WORD_MASK (FLASH_WORD_SIZE - 1)
59 #define IS_FLASH_ADDRESS(ADDR) ((ADDR) < (FLASH_BASE_ADDR + FLASH_PAGE_SIZE * FLASH_TOTAL_SIZE))
60 #define IS_4BYTES_ALIGN(ADDR) (((uint32_t)(ADDR) & 0x3) == 0 ? 1 : 0)
61 #define FLASH_PAGE_ADDR(ADDR) ((ADDR) & (~FLASH_PAGE_MASK))
62 #define FLASH_PAGEEND_ADDR(ADDR) ((ADDR) | FLASH_PAGE_MASK)
63 #define FLASH_WORD_ADDR(ADDR) ((ADDR) & (~FLASH_WORD_MASK))
64 #define FLASH_WORDEND_ADDR(ADDR) ((ADDR) | FLASH_WORD_MASK)
65 #define INFO_PAGE_SIZE 1024UL
66 #define INFO_PAGE_MASK (INFO_PAGE_SIZE - 1)
67 #define INFO_PAGE_ADDR(ADDR) ((ADDR) & (~INFO_PAGE_MASK))
68
69 #ifdef USE_FLASH_FIFO
70 #define FLASH_FIFO 1
71 #else
72 #define FLASH_FIFO 0
73 #endif
74
81 typedef enum {
82 FLASH_CMD_AE = 0x000051AEU,
83 FLASH_CMD_PE = 0x00005EA1U,
84 FLASH_CMD_WP = 0x00005DA2U,
85 FLASH_CMD_WP_FAST = 0x00005CA3U,
86 FLASH_CMD_DATAPE = 0x00005BA4U,
87 FLASH_CMD_DATAWP = 0x00005AA5U,
88 FLASH_CMD_DATAWP_FAST = 0x000059A6U,
89 FLASH_CMD_NP_AE = 0x000050AFU,
90 } flash_cmd_type;
91
92 typedef enum {
93 OP_FLASH = 0U,
94 OP_INFO = 1U,
95 } op_cmd_type;
96
103 ald_status_t flash_page_erase(uint32_t addr);
104 ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo);
112 ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len);
113 ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len);
114 ald_status_t ald_flash_erase(uint32_t addr, uint16_t len);
126 #ifdef __cplusplus
127 }
128 #endif
129
130 #endif /* __ALD_FLASH_H__ */
op_cmd_type
op_cmd_type
Definition: ald_flash.h:92
OP_FLASH
Definition: ald_flash.h:93
ald_flash_read
ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len)
read the specified length bytes from flash, and store to the specified area.
Definition: ald_flash_ext.c:134
FLASH_CMD_WP_FAST
Definition: ald_flash.h:85
ald_flash_erase
ald_status_t ald_flash_erase(uint32_t addr, uint16_t len)
erase The flash between the given address section.
Definition: ald_flash_ext.c:250
flash_page_erase
__RAMFUNC ald_status_t flash_page_erase(uint32_t addr)
Erase one page.
Definition: ald_flash.c:118
FLASH_CMD_NP_AE
Definition: ald_flash.h:89
OP_INFO
Definition: ald_flash.h:94
ald_flash_write
ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len)
Write the give bytes to the given address section.
Definition: ald_flash_ext.c:162
utils.h
This file contains the Utilities functions/types for the driver.
FLASH_CMD_AE
Definition: ald_flash.h:82
flash_cmd_type
flash_cmd_type
Definition: ald_flash.h:81
FLASH_CMD_DATAWP_FAST
Definition: ald_flash.h:88
flash_word_program
__RAMFUNC ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo)
Programme a word.
Definition: ald_flash.c:168
FLASH_CMD_WP
Definition: ald_flash.h:84
FLASH_CMD_PE
Definition: ald_flash.h:83
FLASH_CMD_DATAWP
Definition: ald_flash.h:87
FLASH_CMD_DATAPE
Definition: ald_flash.h:86
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54


ALD User Manual: D:/svn/src/ald_flash_ext.c Source File

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  • svn
  • src
ald_flash_ext.c
Go to the documentation of this file.
1
49 #include "ald_flash.h"
50
51
60 #ifdef ALD_FLASH
61
65 /* opration buffer*/
66 static uint8_t write_buf[FLASH_PAGE_SIZE];
85 static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr)
86 {
87 uint8_t* addr_to_read;
88 uint8_t value;
89 uint32_t index;
90
91 /* Check the parameters */
92 assert_param(IS_FLASH_ADDRESS(begin_addr));
93 assert_param(IS_FLASH_ADDRESS(end_addr));
94
95 addr_to_read = (uint8_t *)begin_addr;
96 index = begin_addr;
97 value = 0xFF;
98
99 if (begin_addr > end_addr)
100 return FALSE;
101
102 while (index++ <= end_addr) {
103 value = *addr_to_read++;
104
105 if (value != 0xFF)
106 break;
107 }
108
109 return value == 0xFF ? FALSE : TRUE;
110 }
134 ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len)
135 {
136 uint32_t i;
137 uint32_t temp;
138
139 assert_param(IS_4BYTES_ALIGN(ram_addr));
140 assert_param(IS_FLASH_ADDRESS(addr));
141 assert_param(IS_FLASH_ADDRESS(addr + len - 1));
142
143 temp = (uint32_t)ram_addr;
144
145 if (((temp & 0x3) != 0) || (((addr) & 0x3) != 0))
146 return ERROR;
147
148 for (i = 0; i < len; i++)
149 ram_addr[i] = ((uint32_t *)addr)[i];
150
151 return OK;
152 }
153
162 ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len)
163 {
164 uint32_t index = 0;
165 uint32_t para = 0;
166 uint32_t index2 = 0;
167 uint32_t start_write_addr;
168 uint32_t end_write_addr;
169 uint32_t start_word_addr;
170 uint32_t end_word_addr;
171 uint16_t len_to_write;
172 uint32_t len_index;
173 type_bool_t need_erase_page;
174
175 assert_param(IS_FLASH_ADDRESS(addr));
176 assert_param(IS_FLASH_ADDRESS(addr + len - 1));
177
178 len_to_write = len;
179
180 __disable_irq();
181 while (len_to_write > 0) {
182 need_erase_page = FALSE;
183
184 for (index = 0; index < FLASH_PAGE_SIZE; index++)
185 write_buf[index] = 0xFF;
186
187 start_write_addr = addr + (len - len_to_write);
188 end_write_addr = addr + len - 1;
189 end_write_addr = FLASH_PAGE_ADDR(start_write_addr) == FLASH_PAGE_ADDR(end_write_addr)
190 ? end_write_addr : FLASH_PAGEEND_ADDR(start_write_addr);
191 need_erase_page = page_have_writen(FLASH_WORD_ADDR(start_write_addr),
192 FLASH_WORDEND_ADDR(end_write_addr));
193
194 if (need_erase_page) {
195 if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_write_addr),
196 FLASH_PAGE_SIZE >> 2)) {
197 __enable_irq();
198 return ERROR;
199 }
200
201 if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_write_addr))) {
202 __enable_irq();
203 return ERROR;
204 }
205
206 para = end_write_addr & (FLASH_PAGE_SIZE - 1);
207 index = start_write_addr & (FLASH_PAGE_SIZE - 1);
208 index2 = len - len_to_write;
209
210 while (index <= para)
211 write_buf[index++] = buf[index2++];
212
213 index2 = 0;
214 index = FLASH_PAGE_ADDR(start_write_addr);
215 len_index = FLASH_PAGE_SIZE;
216 }
217 else {
218 para = end_write_addr & (FLASH_PAGE_SIZE - 1);
219 index = start_write_addr & (FLASH_PAGE_SIZE - 1);
220 index2 = len - len_to_write;
221
222 while (index <= para)
223 write_buf[index++] = buf[index2++];
224
225 start_word_addr = FLASH_WORD_ADDR(start_write_addr);
226 end_word_addr = FLASH_WORDEND_ADDR(end_write_addr);
227 index2 = (FLASH_WORD_ADDR(start_word_addr) - FLASH_PAGE_ADDR(start_word_addr));
228 index = start_word_addr;
229 len_index = end_word_addr - start_word_addr + 1;
230 }
231
232 if (ERROR == flash_word_program(index, (uint32_t *)(write_buf + index2), (len_index >> 3), FLASH_FIFO)) {
233 __enable_irq();
234 return ERROR;
235 }
236
237 len_to_write = len_to_write - (end_write_addr - start_write_addr + 1);
238 }
239
240 __enable_irq();
241 return OK;
242 }
243
250 ald_status_t ald_flash_erase(uint32_t addr, uint16_t len)
251 {
252 uint32_t index;
253 int32_t para;
254 int32_t start_erase_addr;
255 int32_t end_erase_addr;
256 uint16_t len_not_erase;
257 uint32_t len_index;
258 type_bool_t page_need_save;
259
260 assert_param(IS_FLASH_ADDRESS(addr));
261 assert_param(IS_FLASH_ADDRESS(addr + len - 1));
262
263 len_not_erase = len;
264
265 __disable_irq();
266 while (len_not_erase > 0) {
267 page_need_save = FALSE;
268
269 start_erase_addr = addr + len - len_not_erase;
270 end_erase_addr = addr + len - 1;
271 end_erase_addr = (FLASH_PAGE_ADDR(start_erase_addr) == FLASH_PAGE_ADDR(end_erase_addr))
272 ? end_erase_addr : FLASH_PAGEEND_ADDR(start_erase_addr);
273
274 if (start_erase_addr != FLASH_PAGE_ADDR(start_erase_addr)) {
275 if (page_have_writen(FLASH_PAGE_ADDR(start_erase_addr), (start_erase_addr - 1)))
276 page_need_save = TRUE;
277 }
278 if (end_erase_addr != FLASH_PAGEEND_ADDR(end_erase_addr)) {
279 if (page_have_writen((end_erase_addr + 1), FLASH_PAGEEND_ADDR(end_erase_addr)))
280 page_need_save = TRUE;
281 }
282
283 if (page_need_save) {
284 if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_erase_addr),
285 FLASH_PAGE_SIZE >> 2)) {
286 __enable_irq();
287 return ERROR;
288 }
289 }
290
291 if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_erase_addr))) {
292 __enable_irq();
293 return ERROR;
294 }
295
296 if (page_need_save) {
297 para = end_erase_addr & (FLASH_PAGE_SIZE - 1);
298 index = start_erase_addr & (FLASH_PAGE_SIZE - 1);
299
300 while (index <= para)
301 write_buf[index++] = 0xFF;
302
303 index = FLASH_PAGE_ADDR(start_erase_addr);
304 len_index = FLASH_PAGE_SIZE;
305 if (ERROR == flash_word_program(index, (uint32_t *)write_buf, (len_index >> 3), FLASH_FIFO)) {
306 __enable_irq();
307 return ERROR;
308 }
309 }
310 len_not_erase = len_not_erase - (end_erase_addr - start_erase_addr + 1);
311 }
312
313 __enable_irq();
314 return OK;
315 }
321 #endif
322
OK
Definition: utils.h:55
assert_param
#define assert_param(x)
Definition: type.h:88
FALSE
Definition: type.h:54
ald_flash_read
ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len)
read the specified length bytes from flash, and store to the specified area.
Definition: ald_flash_ext.c:134
type_bool_t
type_bool_t
Definition: type.h:53
ald_flash_erase
ald_status_t ald_flash_erase(uint32_t addr, uint16_t len)
erase The flash between the given address section.
Definition: ald_flash_ext.c:250
FLASH_PAGE_ADDR
#define FLASH_PAGE_ADDR(ADDR)
Definition: ald_flash.h:61
flash_page_erase
__RAMFUNC ald_status_t flash_page_erase(uint32_t addr)
Erase one page.
Definition: ald_flash.c:118
ald_flash.h
Header file of FLASH driver.
ald_flash_write
ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len)
Write the give bytes to the given address section.
Definition: ald_flash_ext.c:162
TRUE
Definition: type.h:55
FLASH_WORD_ADDR
#define FLASH_WORD_ADDR(ADDR)
Definition: ald_flash.h:63
IS_FLASH_ADDRESS
#define IS_FLASH_ADDRESS(ADDR)
Definition: ald_flash.h:59
flash_word_program
__RAMFUNC ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo)
Programme a word.
Definition: ald_flash.c:168
FLASH_FIFO
#define FLASH_FIFO
Definition: ald_flash.h:72
FLASH_PAGE_SIZE
#define FLASH_PAGE_SIZE
Definition: ald_flash.h:54
FLASH_WORDEND_ADDR
#define FLASH_WORDEND_ADDR(ADDR)
Definition: ald_flash.h:64
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
write_buf
static uint8_t write_buf[FLASH_PAGE_SIZE]
Definition: ald_flash_ext.c:66
ERROR
Definition: utils.h:56
IS_4BYTES_ALIGN
#define IS_4BYTES_ALIGN(ADDR)
Definition: ald_flash.h:60
FLASH_PAGEEND_ADDR
#define FLASH_PAGEEND_ADDR(ADDR)
Definition: ald_flash.h:62
page_have_writen
static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr)
Check whether the flash between the given address section have been writen, if it have been writen...
Definition: ald_flash_ext.c:85


ALD User Manual: D:/svn/src/ald_gpio.c Source File

  • D:
  • svn
  • src
ald_gpio.c
Go to the documentation of this file.
1
127 #include "ald_conf.h"
128 #include "ald_gpio.h"
129
130
140 #ifdef ALD_GPIO
141
170 void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init)
171 {
172 uint32_t i, pos, mask, tmp;
173
174 assert_param(IS_GPIO_PORT(GPIOx));
175 assert_param(IS_GPIO_PIN(pin));
176 assert_param(IS_GPIO_MODE(init->mode));
177 assert_param(IS_GPIO_ODOS(init->odos));
178 assert_param(IS_GPIO_PUPD(init->pupd));
179 assert_param(IS_GPIO_ODRV(init->podrv));
180 assert_param(IS_GPIO_ODRV(init->nodrv));
181 assert_param(IS_GPIO_FLT(init->flt));
182 assert_param(IS_GPIO_TYPE(init->type));
183 assert_param(IS_GPIO_FUNC(init->func));
184
185 for (i = 0; i < 16; ++i) {
186 if (((pin >> i) & 0x1) == 0)
187 continue;
188
189 /* Get position and 2-bits mask */
190 pos = i << 1;
191 mask = 0x3 << pos;
192
193 /* Set PIN mode */
194 tmp = READ_REG(GPIOx->MODE);
195 tmp &= ~mask;
196 tmp |= (init->mode << pos);
197 WRITE_REG(GPIOx->MODE, tmp);
198
199 /* Set PIN open-drain or push-pull */
200 tmp = READ_REG(GPIOx->ODOS);
201 tmp &= ~mask;
202 tmp |= (init->odos << pos);
203 WRITE_REG(GPIOx->ODOS, tmp);
204
205 /* Set PIN push-up or/and push-down */
206 tmp = READ_REG(GPIOx->PUPD);
207 tmp &= ~mask;
208 tmp |= (init->pupd << pos);
209 WRITE_REG(GPIOx->PUPD, tmp);
210
211 /* Set PIN output P-MOS driver */
212 tmp = READ_REG(GPIOx->PODRV);
213 tmp &= ~mask;
214 tmp |= (init->podrv << pos);
215 WRITE_REG(GPIOx->PODRV, tmp);
216
217 /* Set PIN output N-MOS driver */
218 tmp = READ_REG(GPIOx->NODRV);
219 tmp &= ~mask;
220 tmp |= (init->nodrv << pos);
221 WRITE_REG(GPIOx->NODRV, tmp);
222
223 /* Get position and 1-bit mask */
224 pos = i;
225 mask = 0x1 << pos;
226
227 /* Set PIN filter enable or disable */
228 tmp = READ_REG(GPIOx->FLT);
229 tmp &= ~mask;
230 tmp |= (init->flt << pos);
231 WRITE_REG(GPIOx->FLT, tmp);
232
233 /* Set PIN type ttl or smit */
234 tmp = READ_REG(GPIOx->TYPE);
235 tmp &= ~mask;
236 tmp |= (init->type << pos);
237 WRITE_REG(GPIOx->TYPE, tmp);
238
239 /* Configure PIN function */
240 pos = i < 8 ? (i << 2) : ((i - 8) << 2);
241 mask = 0xF << pos;
242 tmp = i < 8 ? READ_REG(GPIOx->FUNC0) : READ_REG(GPIOx->FUNC1);
243 tmp &= ~mask;
244 tmp |= (init->func << pos);
245 i < 8 ? WRITE_REG(GPIOx->FUNC0, tmp) : WRITE_REG(GPIOx->FUNC1, tmp);
246 }
247
248 return;
249 }
250
257 void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin)
258 {
259 gpio_init_t init;
260
261 /* Fill GPIO_init_t structure with default parameter */
262 init.mode = GPIO_MODE_OUTPUT;
263 init.odos = GPIO_PUSH_PULL;
264 init.pupd = GPIO_PUSH_UP;
265 init.podrv = GPIO_OUT_DRIVE_6;
266 init.nodrv = GPIO_OUT_DRIVE_6;
267 init.flt = GPIO_FILTER_DISABLE;
268 init.type = GPIO_TYPE_CMOS;
269 init.func = GPIO_FUNC_1;
270
271 ald_gpio_init(GPIOx, pin, &init);
272 return;
273 }
274
280 void ald_gpio_func_default(GPIO_TypeDef *GPIOx)
281 {
282 WRITE_REG(GPIOx->FUNC0, 0x00);
283 WRITE_REG(GPIOx->FUNC1, 0x00);
284
285 return;
286 }
287
297 void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init)
298 {
299 uint8_t i;
300 uint8_t port;
301
302 assert_param(IS_GPIO_PORT(GPIOx));
303 assert_param(IS_GPIO_PIN(pin));
304 assert_param(IS_FUNC_STATE(init->filter));
305 assert_param(IS_EXTI_FLTCKS_TYPE(init->cks));
306
307 /* Get GPIO port */
308 if (GPIOx == GPIOA)
309 port = 0x0;
310 else if (GPIOx == GPIOB)
311 port = 0x1;
312 else if (GPIOx == GPIOC)
313 port = 2;
314 else if (GPIOx == GPIOD)
315 port = 3;
316 else if (GPIOx == GPIOE)
317 port = 4;
318 else if (GPIOx == GPIOF)
319 port = 5;
320 else if (GPIOx == GPIOG)
321 port = 6;
322 else if (GPIOx == GPIOH)
323 port = 7;
324 else
325 port = 0;
326
327 /* Get Pin index */
328 for (i = 0; i < 16; ++i) {
329 if (((pin >> i) & 0x1) == 0x1)
330 break;
331 }
332
333 /* Select external interrupt line */
334 if (i <= 7) {
335 EXTI->EXTIPSR0 &= ~(0x7U << (i * 4));
336 EXTI->EXTIPSR0 |= (port << (i * 4));
337 }
338 else {
339 i -= 8;
340 EXTI->EXTIPSR1 &= ~(0x7U << (i * 4));
341 EXTI->EXTIPSR1 |= (port << (i * 4));
342 }
343
344 /* Configure filter parameter */
345 if (init->filter == ENABLE) {
346 SET_BIT(EXTI->EXTIFLTCR, pin);
347 MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTCKS_MSK, init->cks << GPIO_EXTIFLTCR_FLTCKS_POSS);
348 MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTSEL_MSK, init->filter_time << GPIO_EXTIFLTCR_FLTSEL_POSS);
349 }
350 else {
351 CLEAR_BIT(EXTI->EXTIFLTCR, pin);
352 }
353
354 return;
355 }
380 uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
381 {
382 assert_param(IS_GPIO_PORT(GPIOx));
383 assert_param(IS_GPIO_PIN(pin));
384
385 if (READ_BIT(GPIOx->DIN, pin))
386 return 1;
387 else
388 return 0;
389 }
390
398 void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val)
399 {
400 assert_param(IS_GPIO_PORT(GPIOx));
401 assert_param(IS_GPIO_PIN(pin));
402
403 if ((val & (0x01)) == 0x00)
404 CLEAR_BIT(GPIOx->DOUT, pin);
405 else
406 SET_BIT(GPIOx->DOUT, pin);
407
408 return;
409 }
410
417 void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
418 {
419 assert_param(IS_GPIO_PORT(GPIOx));
420 assert_param(IS_GPIO_PIN(pin));
421
422 WRITE_REG(GPIOx->BIR, pin);
423 return;
424 }
425
432 void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin)
433 {
434 uint32_t i, pos, mask, tmp, value;
435
436 assert_param(IS_GPIO_PORT(GPIOx));
437 assert_param(IS_GPIO_PIN(pin));
438
439 for (i = 0; i < 16; ++i) {
440 if (((pin >> i) & 0x1) == 0)
441 continue;
442
443 /* Get position and 2-bits mask */
444 pos = i << 1;
445 mask = 0x3 << pos;
446
447 /* Get the new direction */
448 tmp = READ_REG(GPIOx->MODE);
449 value = (tmp >> pos) & 0x3;
450
451 if ((value == 2) || (value == 3))
452 value = 1;
453 else if (value == 1) {
454 value = 2;
455 }
456 else {
457 continue; /* do nothing */
458 }
459
460 /* Set PIN mode */
461 tmp &= ~mask;
462 tmp |= (value << pos);
463 WRITE_REG(GPIOx->MODE, tmp);
464 }
465
466 return;
467 }
468
477 void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
478 {
479 assert_param(IS_GPIO_PORT(GPIOx));
480 assert_param(IS_GPIO_PIN(pin));
481
482 MODIFY_REG(GPIOx->LOCK, GPIO_LOCK_KEY_MSK, UNLOCK_KEY << GPIO_LOCK_KEY_POSS);
483 WRITE_REG(GPIOx->LOCK, pin);
484
485 return;
486 }
487
493 uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx)
494 {
495 assert_param(IS_GPIO_PORT(GPIOx));
496
497 return READ_REG(GPIOx->DIN);
498 }
499
506 void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val)
507 {
508 assert_param(IS_GPIO_PORT(GPIOx));
509
510 WRITE_REG(GPIOx->DOUT, val);
511 return;
512 }
541 void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status)
542 {
543 assert_param(IS_GPIO_PIN(pin));
544 assert_param(IS_TRIGGER_STYLE(style));
545 assert_param(IS_FUNC_STATE(status));
546
547 if (status == ENABLE) {
548 if (style == EXTI_TRIGGER_RISING_EDGE) {
549 SET_BIT(EXTI->EXTIRER, pin);
550 }
551 else if (style == EXTI_TRIGGER_TRAILING_EDGE) {
552 SET_BIT(EXTI->EXTIFER, pin);
553 }
554 else if (style == EXTI_TRIGGER_BOTH_EDGE) {
555 SET_BIT(EXTI->EXTIRER, pin);
556 SET_BIT(EXTI->EXTIFER, pin);
557 }
558 else {
559 ; /* do nothing */
560 }
561
562 WRITE_REG(EXTI->EXTICFR, 0xffff);
563 SET_BIT(EXTI->EXTIEN, pin);
564 }
565 else {
566 if (style == EXTI_TRIGGER_RISING_EDGE) {
567 CLEAR_BIT(EXTI->EXTIRER, pin);
568 }
569 else if (style == EXTI_TRIGGER_TRAILING_EDGE) {
570 CLEAR_BIT(EXTI->EXTIFER, pin);
571 }
572 else if (style == EXTI_TRIGGER_BOTH_EDGE) {
573 CLEAR_BIT(EXTI->EXTIRER, pin);
574 CLEAR_BIT(EXTI->EXTIFER, pin);
575 }
576 else {
577 ; /* do nothing */
578 }
579
580 CLEAR_BIT(EXTI->EXTIEN, pin);
581 }
582
583 return;
584 }
585
593 flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin)
594 {
595 assert_param(IS_GPIO_PIN(pin));
596
597 if (READ_BIT(EXTI->EXTIFLAG, pin))
598 return SET;
599
600 return RESET;
601 }
602
608 void ald_gpio_exti_clear_flag_status(uint16_t pin)
609 {
610 assert_param(IS_GPIO_PIN(pin));
611
612 WRITE_REG(EXTI->EXTICFR, pin);
613 return;
614 }
623 #endif /* ALD_GPIO */
624
ENABLE
Definition: type.h:49
exti_init_t::cks
exti_filter_clock_t cks
Definition: ald_gpio.h:178
gpio_init_t::nodrv
gpio_out_drive_t nodrv
Definition: ald_gpio.h:146
ald_gpio_exti_get_flag_status
flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin)
Get the Flag about external interrupt.
Definition: ald_gpio.c:593
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
READ_REG
#define READ_REG(reg)
Definition: type.h:73
SET
Definition: type.h:39
exti_init_t::filter
type_func_t filter
Definition: ald_gpio.h:177
IS_GPIO_FLT
#define IS_GPIO_FLT(x)
Definition: ald_gpio.h:215
type_func_t
type_func_t
Definition: type.h:47
ald_gpio_init_default
void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin)
Initialize the GPIOx peripheral using the default parameters.
Definition: ald_gpio.c:257
IS_GPIO_FUNC
#define IS_GPIO_FUNC(x)
Definition: ald_gpio.h:224
GPIO_FUNC_1
Definition: ald_gpio.h:124
IS_TRIGGER_STYLE
#define IS_TRIGGER_STYLE(x)
Definition: ald_gpio.h:219
EXTI_TRIGGER_RISING_EDGE
Definition: ald_gpio.h:160
gpio_init_t::func
gpio_func_t func
Definition: ald_gpio.h:152
exti_trigger_style_t
exti_trigger_style_t
EXTI trigger style.
Definition: ald_gpio.h:159
ald_gpio_write_port
void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val)
Set or clear the select Pin data.
Definition: ald_gpio.c:506
EXTI_TRIGGER_TRAILING_EDGE
Definition: ald_gpio.h:161
RESET
Definition: type.h:38
ald_conf.h
Enable/Disable the peripheral module.
gpio_init_t::flt
gpio_filter_t flt
Definition: ald_gpio.h:148
IS_EXTI_FLTCKS_TYPE
#define IS_EXTI_FLTCKS_TYPE(x)
Definition: ald_gpio.h:222
ald_gpio.h
Header file of GPIO module driver.
ald_gpio_exti_interrupt_config
void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status)
Configure the interrupt according to the specified parameter.
Definition: ald_gpio.c:541
ald_gpio_toggle_dir
void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin)
Turn over the direction.
Definition: ald_gpio.c:432
exti_init_t::filter_time
uint8_t filter_time
Definition: ald_gpio.h:179
EXTI_TRIGGER_BOTH_EDGE
Definition: ald_gpio.h:162
GPIO_FILTER_DISABLE
Definition: ald_gpio.h:107
IS_GPIO_TYPE
#define IS_GPIO_TYPE(x)
Definition: ald_gpio.h:217
GPIO_PUSH_PULL
Definition: ald_gpio.h:78
ald_gpio_toggle_pin
void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
Turn over the select data.
Definition: ald_gpio.c:417
gpio_init_t::type
gpio_type_t type
Definition: ald_gpio.h:150
gpio_init_t
GPIO Init Structure definition.
Definition: ald_gpio.h:137
IS_GPIO_ODOS
#define IS_GPIO_ODOS(x)
Definition: ald_gpio.h:204
IS_GPIO_PIN
#define IS_GPIO_PIN(x)
Definition: ald_gpio.h:192
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
ald_gpio_lock_pin
void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
Lock the GPIO prot. Once locked, can only change the output data. Only when the CPU reset to unlock t...
Definition: ald_gpio.c:477
ald_gpio_exti_init
void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init)
Initialize the external interrupt according to the specified parameters in the exti_init_t.
Definition: ald_gpio.c:297
gpio_init_t::mode
gpio_mode_t mode
Definition: ald_gpio.h:138
gpio_init_t::pupd
gpio_push_t pupd
Definition: ald_gpio.h:142
GPIO_MODE_OUTPUT
Definition: ald_gpio.h:71
ald_gpio_exti_clear_flag_status
void ald_gpio_exti_clear_flag_status(uint16_t pin)
Clear the external interrupt flag.
Definition: ald_gpio.c:608
ald_gpio_read_pin
uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
Read the specified input port pin.
Definition: ald_gpio.c:380
ald_gpio_func_default
void ald_gpio_func_default(GPIO_TypeDef *GPIOx)
Sets GPIO function to default(func0).
Definition: ald_gpio.c:280
ald_gpio_write_pin
void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val)
Set or clear the select Pin data.
Definition: ald_gpio.c:398
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
GPIO_TYPE_CMOS
Definition: ald_gpio.h:115
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
flag_status_t
flag_status_t
Definition: type.h:37
exti_init_t
EXTI Init Structure definition.
Definition: ald_gpio.h:176
UNLOCK_KEY
#define UNLOCK_KEY
Definition: ald_gpio.h:190
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
gpio_init_t::podrv
gpio_out_drive_t podrv
Definition: ald_gpio.h:144
IS_GPIO_ODRV
#define IS_GPIO_ODRV(x)
Definition: ald_gpio.h:211
IS_GPIO_PUPD
#define IS_GPIO_PUPD(x)
Definition: ald_gpio.h:207
IS_GPIO_MODE
#define IS_GPIO_MODE(x)
Definition: ald_gpio.h:201
gpio_init_t::odos
gpio_odos_t odos
Definition: ald_gpio.h:140
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
ald_gpio_init
void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init)
Initialize the GPIOx peripheral according to the specified parameters in the gpio_init_t.
Definition: ald_gpio.c:170
IS_GPIO_PORT
#define IS_GPIO_PORT(GPIOx)
Definition: ald_gpio.h:193
GPIO_OUT_DRIVE_6
Definition: ald_gpio.h:99
ald_gpio_read_port
uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx)
Read the specified input port pin.
Definition: ald_gpio.c:493
GPIO_PUSH_UP
Definition: ald_gpio.h:88


ALD User Manual: D:/svn/src/ald_gpio.h Source File

  • D:
  • svn
  • src
ald_gpio.h
Go to the documentation of this file.
1
17 #ifndef __ALD_GPIO_H__
18 #define __ALD_GPIO_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25
26
39 #define GPIO_PIN_0 (1U << 0)
40 #define GPIO_PIN_1 (1U << 1)
41 #define GPIO_PIN_2 (1U << 2)
42 #define GPIO_PIN_3 (1U << 3)
43 #define GPIO_PIN_4 (1U << 4)
44 #define GPIO_PIN_5 (1U << 5)
45 #define GPIO_PIN_6 (1U << 6)
46 #define GPIO_PIN_7 (1U << 7)
47 #define GPIO_PIN_8 (1U << 8)
48 #define GPIO_PIN_9 (1U << 9)
49 #define GPIO_PIN_10 (1U << 10)
50 #define GPIO_PIN_11 (1U << 11)
51 #define GPIO_PIN_12 (1U << 12)
52 #define GPIO_PIN_13 (1U << 13)
53 #define GPIO_PIN_14 (1U << 14)
54 #define GPIO_PIN_15 (1U << 15)
55 #define GPIO_PIN_ALL (0xFFFF)
56
68 typedef enum {
69 GPIO_MODE_CLOSE = 0x0U,
70 GPIO_MODE_INPUT = 0x1U,
71 GPIO_MODE_OUTPUT = 0x2U,
72 } gpio_mode_t;
73
77 typedef enum {
78 GPIO_PUSH_PULL = 0x0U,
79 GPIO_OPEN_DRAIN = 0x2U,
80 GPIO_OPEN_SOURCE = 0x3U,
81 } gpio_odos_t;
82
86 typedef enum {
87 GPIO_FLOATING = 0x0U,
88 GPIO_PUSH_UP = 0x1U,
89 GPIO_PUSH_DOWN = 0x2U,
90 GPIO_PUSH_UP_DOWN = 0x3U,
91 } gpio_push_t;
92
96 typedef enum {
97 GPIO_OUT_DRIVE_0_1 = 0x0U,
98 GPIO_OUT_DRIVE_1 = 0x1U,
99 GPIO_OUT_DRIVE_6 = 0x2U,
100 GPIO_OUT_DRIVE_20 = 0x3U,
101 } gpio_out_drive_t;
102
106 typedef enum {
107 GPIO_FILTER_DISABLE = 0x0U,
108 GPIO_FILTER_ENABLE = 0x1U,
109 } gpio_filter_t;
110
114 typedef enum {
115 GPIO_TYPE_CMOS = 0x0U,
116 GPIO_TYPE_TTL = 0x1U,
117 } gpio_type_t;
118
122 typedef enum {
123 GPIO_FUNC_0 = 0U,
124 GPIO_FUNC_1 = 1U,
125 GPIO_FUNC_2 = 2U,
126 GPIO_FUNC_3 = 3U,
127 GPIO_FUNC_4 = 4U,
128 GPIO_FUNC_5 = 5U,
129 GPIO_FUNC_6 = 6U,
130 GPIO_FUNC_7 = 7U,
131 } gpio_func_t;
132
133
137 typedef struct {
138 gpio_mode_t mode;
140 gpio_odos_t odos;
142 gpio_push_t pupd;
144 gpio_out_drive_t podrv;
146 gpio_out_drive_t nodrv;
148 gpio_filter_t flt;
150 gpio_type_t type;
152 gpio_func_t func;
154 } gpio_init_t;
155
159 typedef enum {
160 EXTI_TRIGGER_RISING_EDGE = 0U,
161 EXTI_TRIGGER_TRAILING_EDGE = 1U,
162 EXTI_TRIGGER_BOTH_EDGE = 2U,
163 } exti_trigger_style_t;
164
168 typedef enum {
169 EXTI_FILTER_CLOCK_10K = 0U,
170 EXTI_FILTER_CLOCK_32K = 1U,
171 } exti_filter_clock_t;
172
176 typedef struct {
177 type_func_t filter;
178 exti_filter_clock_t cks;
179 uint8_t filter_time;
180 } exti_init_t;
189 #define PIN_MASK 0xFFFFU
190 #define UNLOCK_KEY 0x55AAU
191
192 #define IS_GPIO_PIN(x) ((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0))
193 #define IS_GPIO_PORT(GPIOx) ((GPIOx == GPIOA) || \
194 (GPIOx == GPIOB) || \
195 (GPIOx == GPIOC) || \
196 (GPIOx == GPIOD) || \
197 (GPIOx == GPIOE) || \
198 (GPIOx == GPIOF) || \
199 (GPIOx == GPIOG) || \
200 (GPIOx == GPIOH))
201 #define IS_GPIO_MODE(x) (((x) == GPIO_MODE_CLOSE) || \
202 ((x) == GPIO_MODE_INPUT) || \
203 ((x) == GPIO_MODE_OUTPUT))
204 #define IS_GPIO_ODOS(x) (((x) == GPIO_PUSH_PULL) || \
205 ((x) == GPIO_OPEN_DRAIN) || \
206 ((x) == GPIO_OPEN_SOURCE))
207 #define IS_GPIO_PUPD(x) (((x) == GPIO_FLOATING) || \
208 ((x) == GPIO_PUSH_UP) || \
209 ((x) == GPIO_PUSH_DOWN) || \
210 ((x) == GPIO_PUSH_UP_DOWN))
211 #define IS_GPIO_ODRV(x) (((x) == GPIO_OUT_DRIVE_0_1) || \
212 ((x) == GPIO_OUT_DRIVE_1) || \
213 ((x) == GPIO_OUT_DRIVE_6) || \
214 ((x) == GPIO_OUT_DRIVE_20))
215 #define IS_GPIO_FLT(x) (((x) == GPIO_FILTER_DISABLE) || \
216 ((x) == GPIO_FILTER_ENABLE))
217 #define IS_GPIO_TYPE(x) (((x) == GPIO_TYPE_TTL) || \
218 ((x) == GPIO_TYPE_CMOS))
219 #define IS_TRIGGER_STYLE(x) (((x) == EXTI_TRIGGER_RISING_EDGE) || \
220 ((x) == EXTI_TRIGGER_TRAILING_EDGE) || \
221 ((x) == EXTI_TRIGGER_BOTH_EDGE))
222 #define IS_EXTI_FLTCKS_TYPE(x) (((x) == EXTI_FILTER_CLOCK_10K) || \
223 ((x) == EXTI_FILTER_CLOCK_32K))
224 #define IS_GPIO_FUNC(x) ((x) <= 7)
225
236 void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init);
237 void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin);
238 void ald_gpio_func_default(GPIO_TypeDef *GPIOx);
239 void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init);
247 uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin);
248 void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val);
249 void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin);
250 void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin);
251 void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin);
252 uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx);
253 void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val);
261 void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status);
262 flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin);
263 void ald_gpio_exti_clear_flag_status(uint16_t pin);
279 #ifdef __cplusplus
280 }
281 #endif
282
283 #endif /* __ALD_GPIO_H__ */
GPIO_OUT_DRIVE_20
Definition: ald_gpio.h:100
gpio_func_t
gpio_func_t
GPIO functions.
Definition: ald_gpio.h:122
GPIO_FUNC_3
Definition: ald_gpio.h:126
exti_init_t::cks
exti_filter_clock_t cks
Definition: ald_gpio.h:178
gpio_init_t::nodrv
gpio_out_drive_t nodrv
Definition: ald_gpio.h:146
ald_gpio_exti_get_flag_status
flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin)
Get the Flag about external interrupt.
Definition: ald_gpio.c:593
gpio_mode_t
gpio_mode_t
GPIO mode.
Definition: ald_gpio.h:68
gpio_odos_t
gpio_odos_t
GPIO open-drain or push-pull.
Definition: ald_gpio.h:77
exti_init_t::filter
type_func_t filter
Definition: ald_gpio.h:177
GPIO_FUNC_2
Definition: ald_gpio.h:125
type_func_t
type_func_t
Definition: type.h:47
ald_gpio_init_default
void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin)
Initialize the GPIOx peripheral using the default parameters.
Definition: ald_gpio.c:257
GPIO_FUNC_1
Definition: ald_gpio.h:124
GPIO_OPEN_DRAIN
Definition: ald_gpio.h:79
EXTI_TRIGGER_RISING_EDGE
Definition: ald_gpio.h:160
gpio_init_t::func
gpio_func_t func
Definition: ald_gpio.h:152
exti_trigger_style_t
exti_trigger_style_t
EXTI trigger style.
Definition: ald_gpio.h:159
ald_gpio_write_port
void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val)
Set or clear the select Pin data.
Definition: ald_gpio.c:506
gpio_push_t
gpio_push_t
GPIO push-up or push-down.
Definition: ald_gpio.h:86
EXTI_TRIGGER_TRAILING_EDGE
Definition: ald_gpio.h:161
GPIO_FUNC_0
Definition: ald_gpio.h:123
GPIO_PUSH_DOWN
Definition: ald_gpio.h:89
gpio_init_t::flt
gpio_filter_t flt
Definition: ald_gpio.h:148
utils.h
This file contains the Utilities functions/types for the driver.
GPIO_OUT_DRIVE_0_1
Definition: ald_gpio.h:97
ald_gpio_exti_interrupt_config
void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status)
Configure the interrupt according to the specified parameter.
Definition: ald_gpio.c:541
ald_gpio_toggle_dir
void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin)
Turn over the direction.
Definition: ald_gpio.c:432
EXTI_FILTER_CLOCK_32K
Definition: ald_gpio.h:170
exti_init_t::filter_time
uint8_t filter_time
Definition: ald_gpio.h:179
EXTI_TRIGGER_BOTH_EDGE
Definition: ald_gpio.h:162
GPIO_FILTER_DISABLE
Definition: ald_gpio.h:107
GPIO_FUNC_7
Definition: ald_gpio.h:130
GPIO_MODE_CLOSE
Definition: ald_gpio.h:69
GPIO_PUSH_PULL
Definition: ald_gpio.h:78
ald_gpio_toggle_pin
void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
Turn over the select data.
Definition: ald_gpio.c:417
gpio_init_t::type
gpio_type_t type
Definition: ald_gpio.h:150
gpio_init_t
GPIO Init Structure definition.
Definition: ald_gpio.h:137
gpio_type_t
gpio_type_t
GPIO type.
Definition: ald_gpio.h:114
GPIO_OPEN_SOURCE
Definition: ald_gpio.h:80
ald_gpio_lock_pin
void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
Lock the GPIO prot. Once locked, can only change the output data. Only when the CPU reset to unlock t...
Definition: ald_gpio.c:477
ald_gpio_exti_init
void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init)
Initialize the external interrupt according to the specified parameters in the exti_init_t.
Definition: ald_gpio.c:297
gpio_init_t::mode
gpio_mode_t mode
Definition: ald_gpio.h:138
gpio_init_t::pupd
gpio_push_t pupd
Definition: ald_gpio.h:142
GPIO_MODE_OUTPUT
Definition: ald_gpio.h:71
ald_gpio_exti_clear_flag_status
void ald_gpio_exti_clear_flag_status(uint16_t pin)
Clear the external interrupt flag.
Definition: ald_gpio.c:608
ald_gpio_read_pin
uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
Read the specified input port pin.
Definition: ald_gpio.c:380
gpio_out_drive_t
gpio_out_drive_t
GPIO output drive.
Definition: ald_gpio.h:96
ald_gpio_func_default
void ald_gpio_func_default(GPIO_TypeDef *GPIOx)
Sets GPIO function to default(func0).
Definition: ald_gpio.c:280
ald_gpio_write_pin
void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val)
Set or clear the select Pin data.
Definition: ald_gpio.c:398
GPIO_MODE_INPUT
Definition: ald_gpio.h:70
GPIO_TYPE_TTL
Definition: ald_gpio.h:116
GPIO_TYPE_CMOS
Definition: ald_gpio.h:115
GPIO_FUNC_6
Definition: ald_gpio.h:129
GPIO_OUT_DRIVE_1
Definition: ald_gpio.h:98
gpio_filter_t
gpio_filter_t
GPIO filter.
Definition: ald_gpio.h:106
GPIO_PUSH_UP_DOWN
Definition: ald_gpio.h:90
flag_status_t
flag_status_t
Definition: type.h:37
exti_init_t
EXTI Init Structure definition.
Definition: ald_gpio.h:176
EXTI_FILTER_CLOCK_10K
Definition: ald_gpio.h:169
GPIO_FILTER_ENABLE
Definition: ald_gpio.h:108
GPIO_FUNC_5
Definition: ald_gpio.h:128
gpio_init_t::podrv
gpio_out_drive_t podrv
Definition: ald_gpio.h:144
GPIO_FUNC_4
Definition: ald_gpio.h:127
gpio_init_t::odos
gpio_odos_t odos
Definition: ald_gpio.h:140
ald_gpio_init
void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init)
Initialize the GPIOx peripheral according to the specified parameters in the gpio_init_t.
Definition: ald_gpio.c:170
exti_filter_clock_t
exti_filter_clock_t
EXTI filter clock select.
Definition: ald_gpio.h:168
GPIO_FLOATING
Definition: ald_gpio.h:87
GPIO_OUT_DRIVE_6
Definition: ald_gpio.h:99
ald_gpio_read_port
uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx)
Read the specified input port pin.
Definition: ald_gpio.c:493
GPIO_PUSH_UP
Definition: ald_gpio.h:88


ALD User Manual: D:/svn/src/ald_i2c.c Source File

  • D:
  • svn
  • src
ald_i2c.c
Go to the documentation of this file.
1
154 #include "ald_i2c.h"
155
165 #ifdef ALD_I2C
166
171 #define I2C_TIMEOUT_FLAG (__systick_interval / 20 + 1)
172 #define I2C_TIMEOUT_ADDR_SLAVE (__systick_interval * 10)
173 #define I2C_TIMEOUT_BUSY_FLAG (__systick_interval * 10)
174 #define I2C_MAX_DELAY 0xFFFFFFFF
175
184 #ifdef ALD_DMA
185 static void i2c_dma_master_send_cplt(void *argv);
186 static void i2c_dma_master_recv_cplt(void *argv);
187 static void i2c_dma_slave_send_cplt(void *argv);
188 static void i2c_dma_slave_recv_cplt(void *argv);
189 static void i2c_dma_mem_send_cplt(void *argv);
190 static void i2c_dma_mem_recv_cplt(void *argv);
191 static void i2c_dma_error(void *argv);
192 static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
193 uint16_t add_size, uint32_t timeout);
194 #endif
195 static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout);
196 static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout);
197 static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
198 uint16_t add_size, uint32_t timeout);
199 static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag,
200 flag_status_t status, uint32_t timeout);
201 static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, uint32_t flag, uint32_t timeout);
202 static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout);
203 static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeout);
204 static ald_status_t i2c_master_send_tc(i2c_handle_t *hperh);
205 static ald_status_t i2c_master_send_txe(i2c_handle_t *hperh);
206 static ald_status_t i2c_master_recv_tc(i2c_handle_t *hperh);
207 static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh);
208 static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh);
209 static ald_status_t i2c_slave_recv_rxne(i2c_handle_t *hperh);
210 static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh);
211
254 ald_status_t i2c_speed_init(i2c_handle_t *hperh, uint32_t freqrange)
255 {
256 float Tsync = 0;
257 float Tscl = 0;
258 float Tfre = 0;
259 uint32_t Tper = 0;
260 uint32_t presc = 0;
261 uint32_t tmp = 0;
262
263 if (hperh->init.module == I2C_MODULE_SLAVE) {
264 hperh->init.clk_speed = 450000;
265 }
266
267 if (hperh->init.clk_speed <= 100000) {
268 tmp = freqrange / 4000000;
269 freqrange = 4000000;
270 } else {
271 tmp = freqrange / 8000000;
272 freqrange = 8000000;
273 }
274
275 Tscl = 1000.0 / (hperh->init.clk_speed / 1000000.0);
276 Tfre = 1000.0 / I2C_FREQ_RANGE(freqrange);
277
278 Tsync = (READ_BITS(hperh->perh->CON2, I2C_CON1_DNF_MSK, I2C_CON1_DNF_POSS) + 2) * 2 * Tfre;
279
280 Tper = (uint32_t)((Tscl - Tsync) / Tfre);
281
282 while (Tper > 512) {
283 Tper = Tper - 512;
284 presc++;
285 }
286
287 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_PRESC_MSK, (presc + tmp ) << I2C_TIMINGR_PRESC_POSS);
288
289 if (hperh->init.clk_speed <= I2C_STANDARD_MODE_MAX_CLK) {
290 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SDADEL_MSK, 2 << I2C_TIMINGR_SDADEL_POSS);
291 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, 4 << I2C_TIMINGR_SCLDEL_POSS);
292 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLH_MSK, (((Tper - 2) / 2) - 4) << I2C_TIMINGR_SCLH_POSS);
293 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLL_MSK, (((Tper - 2) / 2) + 4) << I2C_TIMINGR_SCLL_POSS);
294 }
295 else {
296 if (hperh->init.clk_speed <= I2C_FAST_MODE_MAX_CLK) {
297 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SDADEL_MSK, 2 << I2C_TIMINGR_SDADEL_POSS);
298 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, 3 << I2C_TIMINGR_SCLDEL_POSS);
299 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLH_MSK, (((Tper - 2) / 2) - 6) << I2C_TIMINGR_SCLH_POSS);
300 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLL_MSK, (((Tper - 2) / 2) + 6) << I2C_TIMINGR_SCLL_POSS);
301 }
302 else {
303 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SDADEL_MSK, 0 << I2C_TIMINGR_SDADEL_POSS);
304 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLDEL_MSK, 1 << I2C_TIMINGR_SCLDEL_POSS);
305 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLH_MSK, (((Tper - 2) / 2) - 3) << I2C_TIMINGR_SCLH_POSS);
306 MODIFY_REG(hperh->perh->TIMINGR, I2C_TIMINGR_SCLL_MSK, (((Tper - 2) / 2) + 3) << I2C_TIMINGR_SCLL_POSS);
307 }
308 }
309
310 return OK;
311 }
319 ald_status_t ald_i2c_init(i2c_handle_t *hperh)
320 {
321 uint32_t freqrange = ald_cmu_get_pclk1_clock();
322
323 if (hperh == NULL)
324 return ERROR;
325
326 /* Check the parameters */
327 assert_param(IS_I2C_CLOCK_SPEED(hperh->init.clk_speed));
328 assert_param(IS_I2C_ADDRESSING_MODE(hperh->init.addr_mode));
329 assert_param(IS_I2C_GENERAL_CALL(hperh->init.general_call));
330 assert_param(IS_I2C_NO_STRETCH(hperh->init.no_stretch));
331 assert_param(IS_I2C_MODULE(hperh->init.module));
332
333 if (hperh->state == I2C_STATE_RESET)
334 hperh->lock = UNLOCK;
335
336 hperh->state = I2C_STATE_BUSY;
337
338 I2C_DISABLE(hperh);
339
340 i2c_speed_init(hperh, freqrange);
341 MODIFY_REG(hperh->perh->CON1, I2C_CON1_NOSTRETCH_MSK, (hperh->init.no_stretch) << I2C_CON1_NOSTRETCH_POS);
342 MODIFY_REG(hperh->perh->CON1, I2C_CON1_GCEN_MSK, (hperh->init.general_call) << I2C_CON1_GCEN_POS);
343
344 if (hperh->init.dual_addr == I2C_DUALADDR_ENABLE) {
345 CLEAR_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK);
346 MODIFY_REG(hperh->perh->ADDR1, I2C_ADDR1_OA1_MSK, (hperh->init.own_addr1 & 0x3FF) << I2C_ADDR1_OA1_POSS);
347 SET_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK);
348
349 CLEAR_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK);
350 MODIFY_REG(hperh->perh->ADDR2, I2C_ADDR2_OA2_MSK, (hperh->init.own_addr2 & 0x7F) << I2C_ADDR2_OA2_POSS);
351 SET_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK);
352 } else {
353 if (hperh->init.addr_mode == I2C_ADDR_10BIT) {
354 CLEAR_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK);
355 SET_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1MODE_MSK);
356 MODIFY_REG(hperh->perh->ADDR1, I2C_ADDR1_OA1_MSK, (hperh->init.own_addr1 & 0x3FF) << I2C_ADDR1_OA1_POSS);
357 SET_BIT(hperh->perh->ADDR1, I2C_ADDR1_OA1EN_MSK);
358 }
359 else {
360 CLEAR_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK);
361 MODIFY_REG(hperh->perh->ADDR2, I2C_ADDR2_OA2_MSK, (hperh->init.own_addr2 & 0x7F) << I2C_ADDR2_OA2_POSS);
362 SET_BIT(hperh->perh->ADDR2, I2C_ADDR2_OA2EN_MSK);
363 }
364 }
365
366 I2C_ENABLE(hperh);
367
368 hperh->error_code = I2C_ERROR_NONE;
369 hperh->state = I2C_STATE_READY;
370 hperh->mode = I2C_MODE_NONE;
371
372 return OK;
373 }
374
381 ald_status_t ald_i2c_reset(i2c_handle_t *hperh)
382 {
383 if (hperh == NULL)
384 return ERROR;
385
386 I2C_DISABLE(hperh);
387
388 hperh->error_code = I2C_ERROR_NONE;
389 hperh->state = I2C_STATE_READY;
390 hperh->mode = I2C_MODE_NONE;
391
392 __UNLOCK(hperh);
393
394 WRITE_REG(hperh->perh->CON1, 0);
395 WRITE_REG(hperh->perh->CON2, 0);
396 WRITE_REG(hperh->perh->ADDR1, 0);
397 WRITE_REG(hperh->perh->ADDR2, 0);
398 WRITE_REG(hperh->perh->TIMINGR, 0);
399 WRITE_REG(hperh->perh->TIMEOUTR, 0);
400 WRITE_REG(hperh->perh->FCON, 0);
401 WRITE_REG(hperh->perh->TXDATA, 0);
402 WRITE_REG(hperh->perh->IDR, I2C_FLAG_MASK);
403 WRITE_REG(hperh->perh->ICR, I2C_FLAG_MASK);
404
405 I2C_ENABLE(hperh);
406
407 return OK;
408 }
480 ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf,
481 uint32_t size, uint32_t timeout)
482 {
483 if (hperh->state != I2C_STATE_READY)
484 return BUSY;
485
486 if ((buf == NULL) || (size == 0))
487 return ERROR;
488
489 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
490 return BUSY;
491
492 assert_param(IS_I2C_TYPE(hperh->perh));
493 __LOCK(hperh);
494
495 hperh->state = I2C_STATE_BUSY_TX;
496 hperh->mode = I2C_MODE_MASTER;
497 hperh->error_code = I2C_ERROR_NONE;
498 hperh->p_buff = buf;
499 hperh->xfer_size = size;
500 hperh->xfer_count = 0;
501
502 i2c_master_req_write(hperh, dev_addr, timeout);
503
504 if (size <= 0xFF) {
505 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
506 }
507 else {
508 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
509 SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
510 }
511
512 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
513 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
514
515 while (size > 0) {
516 hperh->perh->TXDATA = (*buf++);
517 size--;
518 hperh->xfer_count++;
519
520 if (i2c_wait_txe_to_timeout(hperh, timeout) != OK)
521 goto ERROR;
522
523 if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) {
524 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TCR, RESET, I2C_TIMEOUT_FLAG) == OK) {
525 if (size > 0xFF) {
526 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
527 }
528 else {
529 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
530 CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
531 }
532 }
533 else {
534 goto ERROR;
535 }
536 }
537 }
538
539 if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK) == SET)
540 goto SUCCESS;
541
542 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == OK) {
543 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
544 goto SUCCESS;
545 }
546 else {
547 goto ERROR;
548 }
549
550 ERROR:
551 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
552 hperh->state = I2C_STATE_READY;
553 hperh->mode = I2C_MODE_NONE;
554 __UNLOCK(hperh);
555
556 return ERROR;
557
558 SUCCESS:
559 hperh->state = I2C_STATE_READY;
560 hperh->mode = I2C_MODE_NONE;
561 __UNLOCK(hperh);
562
563 return OK;
564 }
565
576 ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf,
577 uint32_t size, uint32_t timeout)
578 {
579 if (hperh->state != I2C_STATE_READY)
580 return BUSY;
581
582 if ((buf == NULL) || (size == 0))
583 return ERROR;
584
585 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
586 return BUSY;
587
588 assert_param(IS_I2C_TYPE(hperh->perh));
589 __LOCK(hperh);
590
591 hperh->state = I2C_STATE_BUSY_RX;
592 hperh->mode = I2C_MODE_MASTER;
593 hperh->error_code = I2C_ERROR_NONE;
594 hperh->p_buff = buf;
595 hperh->xfer_size = size;
596 hperh->xfer_count = 0;
597
598 i2c_master_req_read(hperh, dev_addr, timeout);
599
600 if (size <= 0xFF) {
601 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
602 }
603 else {
604 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
605 SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
606 }
607
608 SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK);
609 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
610
611 while (size > 0) {
612 if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK)
613 goto ERROR;
614
615 (*buf++) = hperh->perh->RXDATA;
616 size--;
617 hperh->xfer_count++;
618
619 if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) {
620 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TCR, RESET, I2C_TIMEOUT_FLAG) == OK) {
621 if (size > 0xFF) {
622 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
623 }
624 else {
625 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
626 CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
627 }
628 }
629 else {
630 goto ERROR;
631 }
632 }
633 }
634
635 if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK))
636 goto SUCCESS;
637
638 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
639 goto SUCCESS;
640
641 ERROR:
642 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
643 hperh->state = I2C_STATE_READY;
644 hperh->mode = I2C_MODE_NONE;
645 __UNLOCK(hperh);
646
647 return ERROR;
648
649 SUCCESS:
650 hperh->state = I2C_STATE_READY;
651 hperh->mode = I2C_MODE_NONE;
652 __UNLOCK(hperh);
653
654 return OK;
655 }
656
666 ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
667 {
668 uint8_t i = 0;
669
670 if (hperh->state != I2C_STATE_READY)
671 return BUSY;
672
673 if ((buf == NULL) || (size == 0))
674 return ERROR;
675
676 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
677 return BUSY;
678
679 assert_param(IS_I2C_TYPE(hperh->perh));
680 __LOCK(hperh);
681
682 hperh->state = I2C_STATE_BUSY_TX;
683 hperh->mode = I2C_MODE_SLAVE;
684 hperh->error_code = I2C_ERROR_NONE;
685 hperh->p_buff = buf;
686 hperh->xfer_size = size;
687 hperh->xfer_count = 0;
688
689 MODIFY_REG(hperh->perh->FCON, I2C_FCON_TXFTH_MSK, 0x03 << I2C_FCON_TXFTH_POSS);
690 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
691
692 for (i = 0; i < 16; i++) {
693 hperh->perh->TXDATA = (*buf++);
694 --size;
695 hperh->xfer_count++;
696
697 if (size == 0)
698 break;
699 }
700
701 if (i2c_wait_master_addr_to_timeout(hperh, I2C_IT_ADDR, timeout) == ERROR)
702 goto ERROR;
703
704 while (size > 0) {
705 if (i2c_wait_txe_to_timeout(hperh, timeout) == ERROR)
706 goto ERROR;
707
708 for (i = 0; i < 8; i++) {
709 hperh->perh->TXDATA = (*buf++);
710 --size;
711 hperh->xfer_count++;
712
713 if (size == 0)
714 break;
715 }
716 }
717
718 goto SUCCESS;
719
720 ERROR:
721 hperh->state = I2C_STATE_READY;
722 hperh->mode = I2C_MODE_NONE;
723 __UNLOCK(hperh);
724
725 return ERROR;
726
727 SUCCESS:
728 hperh->state = I2C_STATE_READY;
729 hperh->mode = I2C_MODE_NONE;
730 __UNLOCK(hperh);
731
732 return OK;
733 }
734
744 ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
745 {
746 if (hperh->state != I2C_STATE_READY)
747 return BUSY;
748
749 if ((buf == NULL) || (size == 0))
750 return ERROR;
751
752 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
753 return BUSY;
754
755 assert_param(IS_I2C_TYPE(hperh->perh));
756 __LOCK(hperh);
757
758 hperh->state = I2C_STATE_BUSY_RX;
759 hperh->mode = I2C_MODE_SLAVE;
760 hperh->error_code = I2C_ERROR_NONE;
761 hperh->p_buff = buf;
762 hperh->xfer_count = 0;
763 hperh->xfer_size = size;
764
765 SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK);
766
767 if (i2c_wait_master_addr_to_timeout(hperh, I2C_IT_ADDR, timeout) == ERROR)
768 goto ERROR;
769
770 while (size > 0) {
771 if (i2c_wait_rxne_to_timeout(hperh, timeout) == ERROR)
772 goto ERROR;
773
774 SET_BIT(hperh->perh->CON2, I2C_CON2_ACK_UPD_MSK);
775 (*buf++) = hperh->perh->RXDATA;
776 --size;
777 hperh->xfer_count++;
778 }
779
780 goto SUCCESS;
781
782 ERROR:
783 hperh->state = I2C_STATE_READY;
784 hperh->mode = I2C_MODE_NONE;
785 __UNLOCK(hperh);
786
787 return ERROR;
788
789 SUCCESS:
790 hperh->state = I2C_STATE_READY;
791 hperh->mode = I2C_MODE_NONE;
792 __UNLOCK(hperh);
793
794 return OK;
795 }
796
806 ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size)
807 {
808 if (hperh->state != I2C_STATE_READY)
809 return BUSY;
810
811 if ((buf == NULL) || (size == 0))
812 return ERROR;
813
814 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
815 return BUSY;
816
817 assert_param(IS_I2C_TYPE(hperh->perh));
818 __LOCK(hperh);
819
820 hperh->state = I2C_STATE_BUSY_TX;
821 hperh->mode = I2C_MODE_MASTER;
822 hperh->error_code = I2C_ERROR_NONE;
823 hperh->p_buff = buf;
824 hperh->xfer_size = size;
825 hperh->xfer_count = 0;
826
827 i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG);
828
829 if (size <= 0xff) {
830 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
831 }
832 else {
833 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
834 SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
835 }
836
837 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
838
839 I2C_CLEAR_IT(hperh , I2C_IT_TXTH);
840 I2C_CLEAR_IT(hperh , I2C_IT_NACK);
841 I2C_CLEAR_IT(hperh , I2C_IT_TC);
842 I2C_CLEAR_IT(hperh , I2C_IT_TCR);
843
844 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
845
846 I2C_DISABLE_IT(hperh, I2C_FLAG_MASK);
847 I2C_ENABLE_IT(hperh, I2C_IT_TXTH | I2C_IT_NACK | I2C_IT_TC | I2C_IT_TCR);
848
849 return OK;
850 }
851
861 ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size)
862 {
863 if (hperh->state != I2C_STATE_READY)
864 return BUSY;
865
866 if ((buf == NULL) || (size == 0))
867 return ERROR;
868
869 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
870 return BUSY;
871
872 assert_param(IS_I2C_TYPE(hperh->perh));
873 __LOCK(hperh);
874
875 hperh->state = I2C_STATE_BUSY_RX;
876 hperh->mode = I2C_MODE_MASTER;
877 hperh->error_code = I2C_ERROR_NONE;
878 hperh->p_buff = buf;
879 hperh->xfer_size = size;
880 hperh->xfer_count = 0;
881
882 i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG) ;
883
884 if (size <= 0xFF) {
885 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
886 }
887 else {
888 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
889 SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
890 }
891
892 SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK);
893
894 I2C_CLEAR_IT(hperh , I2C_IT_RXTH);
895 I2C_CLEAR_IT(hperh , I2C_IT_TCR);
896 I2C_CLEAR_IT(hperh , I2C_IT_TC);
897
898 I2C_DISABLE_IT(hperh, I2C_FLAG_MASK);
899 I2C_ENABLE_IT(hperh, I2C_IT_RXTH | I2C_IT_TCR | I2C_IT_TC);
900
901 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
902
903 return OK;
904 }
905
914 ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint32_t size)
915 {
916 if (hperh->state != I2C_STATE_READY)
917 return BUSY;
918
919 if ((buf == NULL) || (size == 0))
920 return ERROR;
921
922 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
923 return BUSY;
924
925 assert_param(IS_I2C_TYPE(hperh->perh));
926 __LOCK(hperh);
927
928 hperh->state = I2C_STATE_BUSY_TX;
929 hperh->mode = I2C_MODE_SLAVE;
930 hperh->error_code = I2C_ERROR_NONE;
931 hperh->p_buff = buf;
932 hperh->xfer_size = size;
933 hperh->xfer_count = 0;
934
935 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
936
937 I2C_CLEAR_IT(hperh , I2C_IT_TXTH);
938 I2C_CLEAR_IT(hperh , I2C_IT_ADDR);
939 I2C_CLEAR_IT(hperh , I2C_IT_NACK);
940 I2C_CLEAR_IT(hperh , I2C_IT_STOP);
941
942 I2C_DISABLE_IT(hperh, I2C_FLAG_MASK);
943 I2C_ENABLE_IT(hperh, I2C_IT_ADDR | I2C_IT_NACK | I2C_IT_STOP | I2C_IT_TXTH);
944
945 return OK;
946 }
947
956 ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint32_t size)
957 {
958 if (hperh->state != I2C_STATE_READY)
959 return BUSY;
960
961 if ((buf == NULL) || (size == 0))
962 return ERROR;
963
964 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
965 return BUSY;
966
967 assert_param(IS_I2C_TYPE(hperh->perh));
968 __LOCK(hperh);
969
970 hperh->state = I2C_STATE_BUSY_RX;
971 hperh->mode = I2C_MODE_SLAVE;
972 hperh->error_code = I2C_ERROR_NONE;
973 hperh->p_buff = buf;
974 hperh->xfer_size = size;
975 hperh->xfer_count = 0;
976
977 SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK);
978
979 I2C_CLEAR_IT(hperh , I2C_IT_RXTH);
980 I2C_CLEAR_IT(hperh , I2C_IT_ADDR);
981 I2C_CLEAR_IT(hperh , I2C_IT_STOP);
982
983 I2C_DISABLE_IT(hperh, I2C_FLAG_MASK);
984 I2C_ENABLE_IT(hperh, I2C_IT_RXTH | I2C_IT_ADDR | I2C_IT_STOP);
985
986 return OK;
987 }
988
989 #ifdef ALD_DMA
990
1001 ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf,
1002 uint8_t size, uint8_t channel)
1003 {
1004 if (hperh->state != I2C_STATE_READY)
1005 return BUSY;
1006
1007 if ((buf == NULL) || (size == 0))
1008 return ERROR;
1009
1010 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
1011 return BUSY;
1012
1013 assert_param(IS_I2C_TYPE(hperh->perh));
1014 __LOCK(hperh);
1015
1016 if (size >= 0xFF)
1017 size = 0xFF;
1018
1019 hperh->state = I2C_STATE_BUSY_TX;
1020 hperh->mode = I2C_MODE_MASTER;
1021 hperh->error_code = I2C_ERROR_NONE;
1022 hperh->p_buff = buf;
1023 hperh->xfer_size = size;
1024 hperh->xfer_count = 0;
1025
1026 if (hperh->hdmatx.perh == NULL)
1027 hperh->hdmatx.perh = DMA0;
1028
1029 hperh->hdmatx.cplt_cbk = i2c_dma_master_send_cplt;
1030 hperh->hdmatx.cplt_arg = hperh;
1031 hperh->hdmatx.err_cbk = i2c_dma_error;
1032 hperh->hdmatx.err_arg = hperh;
1033
1034 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
1035 hperh->hdmatx.config.size = size;
1036
1037 ald_dma_config_struct(&hperh->hdmatx.config);
1038 hperh->hdmatx.config.burst = ENABLE;
1039 hperh->hdmatx.config.src = (void *)hperh->p_buff;
1040 hperh->hdmatx.config.dst = (void *)&hperh->perh->TXDATA;
1041 hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE;
1042 hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE;
1043 hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
1044 hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1;
1045 hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY;
1046 hperh->hdmatx.config.channel = channel;
1047 ald_dma_config_basic(&hperh->hdmatx);
1048
1049 i2c_master_req_write(hperh, dev_addr, I2C_TIMEOUT_FLAG);
1050
1051 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
1052 SET_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK);
1053 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
1054
1055 __UNLOCK(hperh);
1056
1057 return OK;
1058 }
1059
1070 ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf,
1071 uint8_t size, uint8_t channel)
1072 {
1073 if (hperh->state != I2C_STATE_READY)
1074 return BUSY;
1075
1076 if ((buf == NULL) || (size == 0))
1077 return ERROR;
1078
1079 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
1080 return BUSY;
1081
1082 assert_param(IS_I2C_TYPE(hperh->perh));
1083 __LOCK(hperh);
1084
1085 if (size >= 0xFF)
1086 size = 0xFF;
1087
1088 hperh->state = I2C_STATE_BUSY_RX;
1089 hperh->mode = I2C_MODE_MASTER;
1090 hperh->error_code = I2C_ERROR_NONE;
1091 hperh->p_buff = buf;
1092 hperh->xfer_size = size;
1093 hperh->xfer_count = 0;
1094
1095 if (hperh->hdmarx.perh == NULL)
1096 hperh->hdmarx.perh = DMA0;
1097
1098 hperh->hdmarx.cplt_cbk = i2c_dma_master_recv_cplt;
1099 hperh->hdmarx.cplt_arg = (void *)hperh;
1100 hperh->hdmarx.err_cbk = i2c_dma_error;
1101 hperh->hdmarx.err_arg = (void *)hperh;
1102
1103 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
1104 hperh->hdmarx.config.size = size;
1105
1106 ald_dma_config_struct(&hperh->hdmarx.config);
1107 hperh->hdmarx.config.src = (void *)&hperh->perh->RXDATA;
1108 hperh->hdmarx.config.dst = (void *)buf;
1109 hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE;
1110 hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE;
1111 hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE;
1112 hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1;
1113 hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR;
1114 hperh->hdmarx.config.channel = channel;
1115 ald_dma_config_basic(&hperh->hdmarx);
1116
1117 i2c_master_req_read(hperh, dev_addr, I2C_TIMEOUT_FLAG);
1118
1119 SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK);
1120 SET_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK);
1121 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
1122
1123 return OK;
1124 }
1125
1135 ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel)
1136 {
1137 if (hperh->state != I2C_STATE_READY)
1138 return BUSY;
1139
1140 if ((buf == NULL) || (size == 0))
1141 return ERROR;
1142
1143 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
1144 return BUSY;
1145
1146 assert_param(IS_I2C_TYPE(hperh->perh));
1147 __LOCK(hperh);
1148
1149 hperh->state = I2C_STATE_BUSY_TX;
1150 hperh->mode = I2C_MODE_SLAVE;
1151 hperh->error_code = I2C_ERROR_NONE;
1152 hperh->p_buff = buf;
1153 hperh->xfer_size = size;
1154 hperh->xfer_count = 0;
1155
1156 if (size >= 0xFF)
1157 size = 0xFF;
1158
1159 if (hperh->hdmatx.perh == NULL)
1160 hperh->hdmatx.perh = DMA0;
1161
1162 hperh->hdmatx.cplt_cbk = i2c_dma_slave_send_cplt;
1163 hperh->hdmatx.cplt_arg = hperh;
1164 hperh->hdmatx.err_cbk = i2c_dma_error;
1165 hperh->hdmatx.err_arg = hperh;
1166
1167 ald_dma_config_struct(&hperh->hdmatx.config);
1168 hperh->hdmatx.config.burst = ENABLE;
1169 hperh->hdmatx.config.src = (void *)buf;
1170 hperh->hdmatx.config.dst = (void *)&hperh->perh->TXDATA;
1171 hperh->hdmatx.config.size = size;
1172 hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE;
1173 hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE;
1174 hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
1175 hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1;
1176 hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY;
1177 hperh->hdmatx.config.channel = channel;
1178 ald_dma_config_basic(&hperh->hdmatx);
1179
1180 if (i2c_wait_master_addr_to_timeout(hperh, I2C_IT_ADDR, I2C_TIMEOUT_ADDR_SLAVE) == ERROR) {
1181 hperh->state = I2C_STATE_READY;
1182 hperh->mode = I2C_MODE_NONE;
1183 __UNLOCK(hperh);
1184
1185 return ERROR;
1186 }
1187
1188 SET_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK);
1189
1190 return OK;
1191 }
1192
1202 ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel)
1203 {
1204 if (hperh->state != I2C_STATE_READY)
1205 return BUSY;
1206
1207 if ((buf == NULL) || (size == 0))
1208 return ERROR;
1209
1210 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
1211 return BUSY;
1212
1213 assert_param(IS_I2C_TYPE(hperh->perh));
1214 __LOCK(hperh);
1215
1216 hperh->state = I2C_STATE_BUSY_RX;
1217 hperh->mode = I2C_MODE_SLAVE;
1218 hperh->error_code = I2C_ERROR_NONE;
1219 hperh->p_buff = buf;
1220 hperh->xfer_size = size;
1221 hperh->xfer_count = 0;
1222
1223 if (size >= 0xFF)
1224 size = 0xFF;
1225
1226 if (hperh->hdmarx.perh == NULL)
1227 hperh->hdmarx.perh = DMA0;
1228
1229 hperh->hdmarx.cplt_cbk = i2c_dma_slave_recv_cplt;
1230 hperh->hdmarx.cplt_arg = (void *)hperh;
1231 hperh->hdmarx.err_cbk = i2c_dma_error;
1232 hperh->hdmarx.err_arg = (void *)hperh;
1233
1234 ald_dma_config_struct(&hperh->hdmarx.config);
1235 hperh->hdmarx.config.src = (void *)&hperh->perh->RXDATA;
1236 hperh->hdmarx.config.dst = (void *)buf;
1237 hperh->hdmarx.config.size = size;
1238 hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE;
1239 hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE;
1240 hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE;
1241 hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1;
1242 hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR;
1243 hperh->hdmarx.config.channel = channel;
1244 ald_dma_config_basic(&hperh->hdmarx);
1245
1246 if (i2c_wait_master_addr_to_timeout(hperh, I2C_IT_ADDR, I2C_TIMEOUT_ADDR_SLAVE) == ERROR) {
1247 hperh->state = I2C_STATE_READY;
1248 hperh->mode = I2C_MODE_NONE;
1249 __UNLOCK(hperh);
1250
1251 return ERROR;
1252 }
1253
1254 SET_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK);
1255
1256 return OK;
1257 }
1258 #endif
1259
1272 ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
1273 i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout)
1274 {
1275 uint32_t nbyte = 0;
1276
1277 assert_param(IS_I2C_MEMADD_size(add_size));
1278
1279 if (hperh->state != I2C_STATE_READY)
1280 return BUSY;
1281
1282 if ((buf == NULL) || (size == 0))
1283 return ERROR;
1284
1285 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
1286 return BUSY;
1287
1288 assert_param(IS_I2C_TYPE(hperh->perh));
1289 __LOCK(hperh);
1290
1291 hperh->state = I2C_STATE_BUSY_TX;
1292 hperh->mode = I2C_MODE_MEM;
1293 hperh->error_code = I2C_ERROR_NONE;
1294 hperh->xfer_size = size;
1295 hperh->xfer_count = 0;
1296
1297 i2c_master_req_write(hperh, dev_addr, timeout);
1298
1299 if (add_size == I2C_MEMADD_SIZE_8BIT) {
1300 nbyte = size + 1;
1301 }
1302 else {
1303 nbyte = size + 2;
1304 }
1305
1306 if (nbyte <= 0xFF) {
1307 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS);
1308 }
1309 else {
1310 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
1311 SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
1312 }
1313
1314 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
1315
1316 if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK)
1317 goto ERROR;
1318
1319 hperh->xfer_count += 2;
1320 while (size > 0) {
1321 hperh->perh->TXDATA = (*buf++);
1322 --size;
1323 hperh->xfer_count++;
1324
1325 if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) {
1326 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TCR, RESET, I2C_TIMEOUT_FLAG) == OK) {
1327 if (size > 0xFF) {
1328 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
1329 }
1330 else {
1331 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
1332 CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
1333 }
1334 }
1335 else {
1336 goto ERROR;
1337 }
1338 }
1339
1340 if (i2c_wait_txe_to_timeout(hperh, timeout) != OK)
1341 goto ERROR;
1342 }
1343
1344 if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK))
1345 goto SUCCESS;
1346
1347 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
1348 goto SUCCESS;
1349
1350 ERROR:
1351 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
1352 hperh->state = I2C_STATE_READY;
1353 hperh->mode = I2C_MODE_NONE;
1354 __UNLOCK(hperh);
1355
1356 return ERROR;
1357
1358 SUCCESS:
1359 hperh->state = I2C_STATE_READY;
1360 hperh->mode = I2C_MODE_NONE;
1361 __UNLOCK(hperh);
1362
1363 return OK;
1364 }
1365
1378 ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size,
1379 uint8_t *buf, uint32_t size, uint32_t timeout)
1380 {
1381 uint32_t nbyte = 0;
1382
1383 assert_param(IS_I2C_MEMADD_size(add_size));
1384
1385 if (hperh->state != I2C_STATE_READY)
1386 return BUSY;
1387
1388 if ((buf == NULL) || (size == 0))
1389 return ERROR;
1390
1391 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
1392 return BUSY;
1393
1394 assert_param(IS_I2C_TYPE(hperh->perh));
1395 __LOCK(hperh);
1396
1397 hperh->state = I2C_STATE_BUSY_RX;
1398 hperh->mode = I2C_MODE_MEM;
1399 hperh->error_code = I2C_ERROR_NONE;
1400 hperh->xfer_count = 0;
1401 hperh->xfer_size = size;
1402
1403 i2c_master_req_write(hperh, dev_addr, timeout);
1404
1405 nbyte = (add_size == I2C_MEMADD_SIZE_8BIT) ? 1 : 2;
1406 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS);
1407
1408 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
1409 SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK);
1410
1411 if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) {
1412 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
1413 hperh->state = I2C_STATE_READY;
1414 hperh->mode = I2C_MODE_NONE;
1415 __UNLOCK(hperh);
1416
1417 return ERROR;
1418 }
1419
1420 if (size <= 0xFF) {
1421 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
1422 }
1423 else {
1424 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
1425 SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
1426 }
1427
1428 SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK);
1429 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
1430
1431 while (size > 0) {
1432 if (i2c_wait_rxne_to_timeout(hperh, timeout) != OK)
1433 goto ERROR;
1434
1435 (*buf++) = hperh->perh->RXDATA;
1436 size--;
1437 hperh->xfer_count++;
1438
1439 if (((hperh->xfer_count % 0xFF) == 0) && (READ_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK))) {
1440 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TCR, RESET, I2C_TIMEOUT_FLAG) == OK) {
1441 if (size > 0xFF) {
1442 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
1443 }
1444 else {
1445 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
1446 CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
1447 }
1448 }
1449 else {
1450 goto ERROR;
1451 }
1452 }
1453 }
1454
1455 if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK))
1456 goto SUCCESS;
1457
1458 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
1459 goto SUCCESS;
1460
1461 ERROR:
1462 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
1463 hperh->state = I2C_STATE_READY;
1464 hperh->mode = I2C_MODE_NONE;
1465 __UNLOCK(hperh);
1466
1467 return ERROR;
1468
1469 SUCCESS:
1470 hperh->state = I2C_STATE_READY;
1471 hperh->mode = I2C_MODE_NONE;
1472 __UNLOCK(hperh);
1473
1474 return OK;
1475 }
1476
1488 ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
1489 i2c_addr_size_t add_size, uint8_t *buf, uint32_t size)
1490 {
1491 uint32_t nbyte = 0;
1492
1493 assert_param(IS_I2C_MEMADD_size(add_size));
1494
1495 if (hperh->state != I2C_STATE_READY)
1496 return BUSY;
1497
1498 if ((buf == NULL) || (size == 0))
1499 return ERROR;
1500
1501 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
1502 return BUSY;
1503
1504 assert_param(IS_I2C_TYPE(hperh->perh));
1505 __LOCK(hperh);
1506
1507 hperh->state = I2C_STATE_BUSY_TX;
1508 hperh->mode = I2C_MODE_MEM;
1509 hperh->error_code = I2C_ERROR_NONE;
1510 hperh->p_buff = buf;
1511 hperh->xfer_size = size;
1512 hperh->xfer_count = 0;
1513
1514 if (add_size == I2C_MEMADD_SIZE_8BIT) {
1515 nbyte = size + 1;
1516 }
1517 else {
1518 nbyte = size + 2;
1519 }
1520
1521 if (nbyte <= 0xFF) {
1522 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS);
1523 }
1524 else {
1525 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
1526 SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
1527 }
1528
1529 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
1530 SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK);
1531
1532 if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) {
1533 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
1534 hperh->state = I2C_STATE_READY;
1535 hperh->mode = I2C_MODE_NONE;
1536 __UNLOCK(hperh);
1537
1538 return ERROR;
1539 }
1540
1541 I2C_CLEAR_IT(hperh , I2C_IT_TXTH);
1542 I2C_CLEAR_IT(hperh , I2C_IT_NACK);
1543 I2C_CLEAR_IT(hperh , I2C_IT_TC);
1544 I2C_CLEAR_IT(hperh , I2C_IT_TCR);
1545
1546 hperh->perh->TXDATA = (*hperh->p_buff++);
1547 hperh->xfer_count++;
1548
1549 I2C_DISABLE_IT(hperh, I2C_FLAG_MASK);
1550 I2C_ENABLE_IT(hperh, I2C_IT_TXTH | I2C_IT_NACK | I2C_IT_TC | I2C_IT_TCR);
1551
1552 return OK;
1553 }
1554
1566 ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
1567 i2c_addr_size_t add_size, uint8_t *buf, uint32_t size)
1568 {
1569 uint32_t nbyte = 0;
1570
1571 assert_param(IS_I2C_MEMADD_size(add_size));
1572
1573 if (hperh->state != I2C_STATE_READY)
1574 return BUSY;
1575
1576 if ((buf == NULL) || (size == 0))
1577 return ERROR;
1578
1579 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
1580 return BUSY;
1581
1582 assert_param(IS_I2C_TYPE(hperh->perh));
1583 __LOCK(hperh);
1584
1585 hperh->state = I2C_STATE_BUSY_RX;
1586 hperh->mode = I2C_MODE_MEM;
1587 hperh->error_code = I2C_ERROR_NONE;
1588 hperh->p_buff = buf;
1589 hperh->xfer_size = size;
1590 hperh->xfer_count = 0;
1591
1592 nbyte = (add_size == I2C_MEMADD_SIZE_8BIT) ? 1 : 2;
1593 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS);
1594
1595 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
1596 SET_BIT(hperh->perh->FCON, I2C_FCON_RXFRST_MSK);
1597
1598 if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) {
1599 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
1600 hperh->state = I2C_STATE_READY;
1601 hperh->mode = I2C_MODE_NONE;
1602 __UNLOCK(hperh);
1603
1604 return ERROR;
1605 }
1606
1607 if (size <= 0xFF) {
1608 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
1609 }
1610 else {
1611 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
1612 SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
1613 }
1614
1615 I2C_CLEAR_IT(hperh , I2C_IT_RXTH);
1616 I2C_CLEAR_IT(hperh , I2C_IT_TC);
1617 I2C_CLEAR_IT(hperh , I2C_IT_TCR);
1618
1619 I2C_ENABLE_IT(hperh, I2C_IT_RXTH | I2C_IT_TC | I2C_IT_TCR);
1620
1621 SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK);
1622 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
1623
1624 return OK;
1625 }
1626
1627 #ifdef ALD_DMA
1628
1641 ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size,
1642 uint8_t *buf, uint8_t size, uint8_t channel)
1643 {
1644 uint32_t nbyte = 0;
1645
1646 if (hperh->state != I2C_STATE_READY)
1647 return BUSY;
1648
1649 if ((buf == NULL) || (size == 0))
1650 return ERROR;
1651
1652 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
1653 return BUSY;
1654
1655 assert_param(IS_I2C_MEMADD_size(add_size));
1656 __LOCK(hperh);
1657
1658 hperh->state = I2C_STATE_BUSY_TX;
1659 hperh->mode = I2C_MODE_MASTER;
1660 hperh->error_code = I2C_ERROR_NONE;
1661 hperh->p_buff = buf;
1662 hperh->xfer_size = size;
1663 hperh->xfer_count = 0;
1664
1665 if (hperh->hdmatx.perh == NULL)
1666 hperh->hdmatx.perh = DMA0;
1667
1668 hperh->hdmatx.cplt_cbk = i2c_dma_mem_send_cplt;
1669 hperh->hdmatx.cplt_arg = hperh;
1670 hperh->hdmatx.err_cbk = i2c_dma_error;
1671 hperh->hdmatx.err_arg = hperh;
1672
1673 nbyte = (add_size == I2C_MEMADD_SIZE_8BIT) ? 1 : 2;
1674 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, nbyte << I2C_CON2_NBYTES_POSS);
1675 SET_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
1676
1677 ald_dma_config_struct(&hperh->hdmatx.config);
1678 hperh->hdmatx.config.burst = ENABLE;
1679 hperh->hdmatx.config.src = (void *)hperh->p_buff;
1680 hperh->hdmatx.config.dst = (void *)&hperh->perh->TXDATA;
1681 hperh->hdmatx.config.size = size;
1682 hperh->hdmatx.config.data_width = DMA_DATA_SIZE_BYTE;
1683 hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE;
1684 hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
1685 hperh->hdmatx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1;
1686 hperh->hdmatx.config.msigsel = DMA_MSIGSEL_I2C_TXEMPTY;
1687 hperh->hdmatx.config.channel = channel;
1688 ald_dma_config_basic(&hperh->hdmatx);
1689
1690 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
1691
1692 if (i2c_req_mem_write(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) {
1693 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
1694 hperh->state = I2C_STATE_READY;
1695 hperh->mode = I2C_MODE_NONE;
1696 __UNLOCK(hperh);
1697
1698 return ERROR;
1699 }
1700
1701 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
1702 CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
1703
1704 SET_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK);
1705
1706 return OK;
1707 }
1708
1721 ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size,
1722 uint8_t *buf, uint8_t size, uint8_t channel)
1723 {
1724 if (hperh->state != I2C_STATE_READY)
1725 return BUSY;
1726
1727 if ((buf == NULL) || (size == 0))
1728 return ERROR;
1729
1730 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG) != OK)
1731 return BUSY;
1732
1733 assert_param(IS_I2C_MEMADD_size(add_size));
1734 __LOCK(hperh);
1735
1736 hperh->state = I2C_STATE_BUSY_RX;
1737 hperh->mode = I2C_MODE_MEM;
1738 hperh->error_code = I2C_ERROR_NONE;
1739 hperh->p_buff = buf;
1740 hperh->xfer_size = size;
1741 hperh->xfer_count = size;
1742
1743 if (hperh->hdmarx.perh == NULL)
1744 hperh->hdmarx.perh = DMA0;
1745
1746 hperh->hdmarx.cplt_cbk = i2c_dma_mem_recv_cplt;
1747 hperh->hdmarx.cplt_arg = (void *)hperh;
1748 hperh->hdmarx.err_cbk = i2c_dma_error;
1749 hperh->hdmarx.err_arg = (void *)hperh;
1750
1751 if (add_size == I2C_MEMADD_SIZE_16BIT) {
1752 hperh->hdmatx.config.size = size + 2;
1753 }
1754 else {
1755 hperh->hdmatx.config.size = size + 1;
1756 }
1757
1758 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
1759 hperh->hdmatx.config.size = size;
1760
1761 ald_dma_config_struct(&hperh->hdmarx.config);
1762 hperh->hdmatx.config.burst = ENABLE;
1763 hperh->hdmarx.config.src = (void *)&hperh->perh->RXDATA;
1764 hperh->hdmarx.config.dst = (void *)buf;
1765 hperh->hdmarx.config.data_width = DMA_DATA_SIZE_BYTE;
1766 hperh->hdmarx.config.size = size;
1767 hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE;
1768 hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE;
1769 hperh->hdmarx.config.msel = hperh->perh == I2C0 ? DMA_MSEL_I2C0 : DMA_MSEL_I2C1;
1770 hperh->hdmarx.config.msigsel = DMA_MSIGSEL_I2C_RNR;
1771 hperh->hdmarx.config.channel = channel;
1772 ald_dma_config_basic(&hperh->hdmarx);
1773
1774 if (!I2C_GET_FLAG(hperh, I2C_STAT_TXE)) {
1775 SET_BIT(hperh->perh->FCON, I2C_FCON_TXFRST_MSK);
1776 }
1777
1778 if (i2c_req_mem_read(hperh, dev_addr, mem_addr, add_size, I2C_TIMEOUT_FLAG) != OK) {
1779 if (hperh->error_code == I2C_ERROR_AF) {
1780 __UNLOCK(hperh);
1781 return ERROR;
1782 }
1783 else {
1784 __UNLOCK(hperh);
1785 return TIMEOUT;
1786 }
1787 }
1788
1789 SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK);
1790 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
1791 SET_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK);
1792
1793 __UNLOCK(hperh);
1794
1795 return OK;
1796 }
1797
1798 #endif
1799
1825 i2c_state_t ald_i2c_get_state(i2c_handle_t *hperh)
1826 {
1827 return hperh->state;
1828 }
1829
1836 uint32_t ald_i2c_get_error(i2c_handle_t *hperh)
1837 {
1838 return hperh->error_code;
1839 }
1854 void ald_i2c_ev_irq_handler(i2c_handle_t *hperh)
1855 {
1856 uint32_t size = hperh->xfer_size - hperh->xfer_count;
1857
1859 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TXTH) == SET) {
1860 ald_i2c_clear_flag_status(hperh, I2C_IT_TXTH);
1861 if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) {
1862 i2c_master_send_txe(hperh);
1863 }
1864 else if (hperh->mode == I2C_MODE_SLAVE) {
1865 i2c_slave_send_txe(hperh);
1866 }
1867 }
1868
1870 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_RXTH) == SET) {
1871 ald_i2c_clear_flag_status(hperh, I2C_IT_RXTH);
1872 if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) {
1873 i2c_master_recv_rxne(hperh);
1874 }
1875 else if (hperh->mode == I2C_MODE_SLAVE) {
1876 i2c_slave_recv_rxne(hperh);
1877 }
1878 }
1879
1881 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TC) == SET) {
1882 if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM)) {
1883 if (I2C_MASTER_GET_DIR(hperh) == RESET) {
1884 i2c_master_send_tc(hperh);
1885 }
1886 else {
1887 i2c_master_recv_tc(hperh);
1888 }
1889 }
1890
1891 ald_i2c_clear_flag_status(hperh, I2C_IT_TC);
1892 }
1893
1895 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TCR) == SET) {
1896 if (size > 0xFF) {
1897 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, 0xFF << I2C_CON2_NBYTES_POSS);
1898 }
1899 else {
1900 MODIFY_REG(hperh->perh->CON2, I2C_CON2_NBYTES_MSK, size << I2C_CON2_NBYTES_POSS);
1901 CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RELOAD_MSK);
1902 }
1903
1904 ald_i2c_clear_flag_status(hperh, I2C_IT_TCR);
1905 }
1906
1908 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TXE) == SET) {
1909 ald_i2c_clear_flag_status(hperh, I2C_IT_TXE);
1910 }
1911
1913 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_RXF) == SET) {
1914 ald_i2c_clear_flag_status(hperh, I2C_IT_RXF);
1915 }
1916
1918 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_ADDR) == SET) {
1919 ald_i2c_clear_flag_status(hperh, I2C_IT_ADDR);
1920 }
1921
1923 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_STOP) == SET) {
1924 i2c_slave_stopf(hperh);
1925 ald_i2c_clear_flag_status(hperh, I2C_IT_STOP);
1926 }
1927 }
1928
1935 void ald_i2c_er_irq_handler(i2c_handle_t *hperh)
1936 {
1938 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TXOV) == SET) {
1939 ald_i2c_clear_flag_status(hperh, I2C_IT_TXOV);
1940 hperh->error_code |= I2C_ERROR_TOV;
1941 }
1943 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TXUD) == SET) {
1944 ald_i2c_clear_flag_status(hperh, I2C_IT_TXUD);
1945 hperh->error_code |= I2C_ERROR_TUD;
1946 }
1947
1949 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_RXOV) == SET) {
1950 ald_i2c_clear_flag_status(hperh, I2C_IT_RXOV);
1951 hperh->error_code |= I2C_ERROR_ROV;
1952 }
1953
1955 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_RXUD) == SET) {
1956 ald_i2c_clear_flag_status(hperh, I2C_IT_RXUD);
1957 hperh->error_code |= I2C_ERROR_RUD;
1958 }
1959
1961 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_NACK) == SET) {
1962 if (hperh->xfer_count != hperh->xfer_size)
1963 hperh->state |= I2C_ERROR_AF;
1964
1965 if ((hperh->mode == I2C_MODE_MASTER) || (hperh->mode == I2C_MODE_MEM))
1966 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
1967
1968 I2C_DISABLE_IT(hperh, I2C_IT_TXTH | I2C_IT_NACK);
1969 ald_i2c_clear_flag_status(hperh, I2C_IT_NACK);
1970 }
1971
1973 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_BERR) == SET) {
1974 ald_i2c_clear_flag_status(hperh, I2C_IT_BERR);
1975 hperh->state |= I2C_ERROR_BERR;
1976 }
1977
1979 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_ARLO) == SET) {
1980 ald_i2c_clear_flag_status(hperh, I2C_IT_ARLO);
1981 hperh->state |= I2C_ERROR_ARLO;
1982 }
1983
1985 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_PECE) == SET) {
1986 ald_i2c_clear_flag_status(hperh, I2C_IT_PECE);
1987 }
1988
1990 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_TOUT) == SET) {
1991 ald_i2c_clear_flag_status(hperh, I2C_IT_TOUT);
1992 hperh->state |= I2C_ERROR_TIMEOUT;
1993 }
1994
1996 if (ald_i2c_get_mask_flag_status(hperh, I2C_IT_ALERT) == SET) {
1997 ald_i2c_clear_flag_status(hperh, I2C_IT_ALERT);
1998 }
1999
2000 hperh->state = I2C_STATE_READY;
2001 hperh->mode = I2C_MODE_NONE;
2002 __UNLOCK(hperh);
2003
2004 if (hperh->error_callback)
2005 hperh->error_callback(hperh);
2006 }
2007
2018 void ald_i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state)
2019 {
2020 assert_param(IS_I2C_TYPE(hperh->perh));
2021 assert_param(IS_I2C_IT(it));
2022 assert_param(IS_FUNC_STATE(state));
2023
2024 if (state == ENABLE)
2025 hperh->perh->IER = it;
2026 else
2027 hperh->perh->IDR = it;
2028
2029 return;
2030 }
2031
2041 it_status_t ald_i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it)
2042 {
2043 it_status_t status = RESET;
2044
2045 assert_param(IS_I2C_TYPE(hperh->perh));
2046 assert_param(IS_I2C_IT(it));
2047
2048 if (hperh->perh->IVS & it)
2049 status = SET;
2050
2051 return status;
2052 }
2053
2063 flag_status_t ald_i2c_get_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag)
2064 {
2065 assert_param(IS_I2C_TYPE(hperh->perh));
2066 assert_param(IS_I2C_IT(flag));
2067
2068 if (hperh->perh->RIF & flag)
2069 return SET;
2070
2071 return RESET;
2072 }
2073
2074
2084 flag_status_t ald_i2c_get_mask_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag)
2085 {
2086 assert_param(IS_I2C_TYPE(hperh->perh));
2087 assert_param(IS_I2C_IT(flag));
2088
2089 if (hperh->perh->IFM & flag)
2090 return SET;
2091
2092 return RESET;
2093 }
2094
2101 void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag)
2102 {
2103 assert_param(IS_I2C_TYPE(hperh->perh));
2104 assert_param(IS_I2C_IT(flag));
2105
2106 hperh->perh->ICR = flag;
2107 return;
2108 }
2109
2124 static ald_status_t i2c_master_send_tc(i2c_handle_t *hperh)
2125 {
2126 I2C_DISABLE_IT(hperh, I2C_IT_TXTH | I2C_IT_NACK | I2C_IT_TC | I2C_IT_TCR);
2127
2128 if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK) == RESET)
2129 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
2130
2131 __UNLOCK(hperh);
2132 hperh->state = I2C_STATE_READY;
2133
2134 if (hperh->mode == I2C_MODE_MEM) {
2135 if (hperh->mem_tx_cplt_cbk)
2136 hperh->mem_tx_cplt_cbk(hperh);
2137 }
2138 else {
2139 if (hperh->master_tx_cplt_cbk)
2140 hperh->master_tx_cplt_cbk(hperh);
2141 }
2142
2143 return OK;
2144 }
2145
2146
2153 static ald_status_t i2c_master_send_txe(i2c_handle_t *hperh)
2154 {
2155 if (hperh->xfer_count != hperh->xfer_size) {
2156 hperh->perh->TXDATA = (*hperh->p_buff++);
2157 hperh->xfer_count++;
2158 }
2159
2160 return OK;
2161 }
2162
2169 static ald_status_t i2c_master_recv_tc(i2c_handle_t *hperh)
2170 {
2171 I2C_DISABLE_IT(hperh, I2C_IT_RXTH | I2C_IT_TCR | I2C_IT_TC);
2172
2173 if (READ_BIT(hperh->perh->CON2, I2C_CON2_AUTOEND_MSK) == RESET)
2174 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
2175
2176 __UNLOCK(hperh);
2177 hperh->state = I2C_STATE_READY;
2178
2179 if (hperh->mode == I2C_MODE_MEM) {
2180 if (hperh->mem_rx_cplt_cbk)
2181 hperh->mem_rx_cplt_cbk(hperh);
2182 }
2183 else {
2184 if (hperh->master_rx_cplt_cbk)
2185 hperh->master_rx_cplt_cbk(hperh);
2186 }
2187
2188 return OK;
2189 }
2196 static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh)
2197 {
2198 if (hperh->xfer_size - hperh->xfer_count > 0) {
2199 (*hperh->p_buff++) = hperh->perh->RXDATA;
2200 hperh->xfer_count++;
2201 }
2202
2203 return OK;
2204 }
2205
2212 static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh)
2213 {
2214 if (hperh->xfer_size > hperh->xfer_count) {
2215 hperh->perh->TXDATA = (*hperh->p_buff++);
2216 hperh->xfer_count++;
2217 }
2218
2219 return OK;
2220 }
2221
2228 static ald_status_t i2c_slave_recv_rxne(i2c_handle_t *hperh)
2229 {
2230 if (hperh->xfer_size > hperh->xfer_count) {
2231 (*hperh->p_buff++) = hperh->perh->RXDATA;
2232 hperh->xfer_count++;
2233 }
2234
2235 return OK;
2236 }
2237
2244 static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh)
2245 {
2246 I2C_DISABLE_IT(hperh, I2C_IT_ADDR | I2C_IT_NACK | I2C_IT_RXTH | I2C_IT_TXTH | I2C_IT_STOP);
2247
2248 hperh->mode = I2C_MODE_NONE;
2249 hperh->error_code = I2C_ERROR_NONE;
2250 __UNLOCK(hperh);
2251
2252 if (hperh->state == I2C_STATE_BUSY_TX) {
2253 hperh->state = I2C_STATE_READY;
2254 if ((hperh->slave_tx_cplt_cbk) && (hperh->xfer_count != 0))
2255 hperh->slave_tx_cplt_cbk(hperh);
2256 }
2257 else if (hperh->state == I2C_STATE_BUSY_RX) {
2258 hperh->state = I2C_STATE_READY;
2259 if ((hperh->slave_rx_cplt_cbk) && (hperh->xfer_count != 0))
2260 hperh->slave_rx_cplt_cbk(hperh);
2261 }
2262
2263 return OK;
2264 }
2265
2266
2275 static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout)
2276 {
2277 if (hperh->init.addr_mode == I2C_ADDR_7BIT) {
2278 CLEAR_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK);
2279 }
2280 else {
2281 SET_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK);
2282 }
2283
2284 MODIFY_REG(hperh->perh->CON2, I2C_CON2_SADD_MSK, dev_addr << I2C_CON2_SADD_POSS);
2285 CLEAR_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK);
2286
2287 return OK;
2288 }
2289
2298 static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout)
2299 {
2300 if (hperh->init.addr_mode == I2C_ADDR_7BIT) {
2301 CLEAR_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK);
2302 }
2303 else {
2304 SET_BIT(hperh->perh->CON2, I2C_CON2_ADD10_MSK);
2305 }
2306
2307 MODIFY_REG(hperh->perh->CON2, I2C_CON2_SADD_MSK, dev_addr << I2C_CON2_SADD_POSS);
2308 SET_BIT(hperh->perh->CON2, I2C_CON2_RD_WRN_MSK);
2309
2310 return OK;
2311 }
2323 static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout)
2324 {
2325 i2c_master_req_write(hperh, dev_addr, timeout);
2326 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
2327
2328 if (add_size == I2C_MEMADD_SIZE_8BIT) {
2329 hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr);
2330 }
2331 else {
2332 hperh->perh->TXDATA = I2C_MEM_ADD_MSB(mem_addr);
2333
2334 if (i2c_wait_txe_to_timeout(hperh, timeout) != OK)
2335 return ERROR;
2336
2337 hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr);
2338 }
2339
2340 if (i2c_wait_txe_to_timeout(hperh, timeout) != OK)
2341 return ERROR;
2342
2343 return OK;
2344 }
2345 #ifdef ALD_DMA
2346
2356 static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout)
2357 {
2358 uint32_t tim_count = 0;
2359
2360 if (i2c_master_req_write(hperh, dev_addr, timeout) != OK) {
2361 __UNLOCK(hperh);
2362 return ERROR;
2363 }
2364
2365 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
2366
2367 if (add_size == I2C_MEMADD_SIZE_8BIT) {
2368 hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr);
2369 }
2370 else {
2371 hperh->perh->TXDATA = I2C_MEM_ADD_MSB(mem_addr);
2372
2373 if (i2c_wait_txe_to_timeout(hperh, timeout) != OK) {
2374 if (hperh->error_code == I2C_ERROR_AF) {
2375 SET_BIT(hperh->perh->CON2, I2C_CON2_START_MSK);
2376 return ERROR;
2377 }
2378 else {
2379 return TIMEOUT;
2380 }
2381 }
2382
2383 hperh->perh->TXDATA = I2C_MEM_ADD_LSB(mem_addr);
2384 }
2385
2386 while (!I2C_GET_FLAG(hperh, I2C_STAT_TXE)) {
2387 tim_count++;
2388
2389 if (tim_count > 0xFFFF)
2390 return TIMEOUT;
2391 }
2392 return OK;
2393 }
2394
2395
2401 static void i2c_dma_master_send_cplt(void *argv)
2402 {
2403 i2c_handle_t* hperh = (i2c_handle_t*)argv;
2404
2405 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == ERROR)
2406 hperh->error_code |= I2C_ERROR_TIMEOUT;
2407
2408 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
2409 CLEAR_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK);
2410
2411 hperh->xfer_count = 0;
2412 hperh->state = I2C_STATE_READY;
2413 hperh->mode = I2C_MODE_NONE;
2414 __UNLOCK(hperh);
2415
2416 if (hperh->error_code != I2C_ERROR_NONE) {
2417 if (hperh->error_callback)
2418 hperh->error_callback(hperh);
2419 }
2420 else {
2421 if (hperh->master_tx_cplt_cbk)
2422 hperh->master_tx_cplt_cbk(hperh);
2423 }
2424 }
2425
2431 static void i2c_dma_slave_send_cplt(void *argv)
2432 {
2433 i2c_handle_t* hperh = (i2c_handle_t*)argv;
2434
2435 CLEAR_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK);
2436
2437 hperh->xfer_count = 0;
2438 hperh->state = I2C_STATE_READY;
2439 hperh->mode = I2C_MODE_NONE;
2440 __UNLOCK(hperh);
2441
2442 if (hperh->error_code != I2C_ERROR_NONE) {
2443 if (hperh->error_callback)
2444 hperh->error_callback(hperh);
2445 }
2446 else {
2447 if (hperh->slave_tx_cplt_cbk)
2448 hperh->slave_tx_cplt_cbk(hperh);
2449 }
2450 }
2451
2457 static void i2c_dma_master_recv_cplt(void *argv)
2458 {
2459 i2c_handle_t* hperh = (i2c_handle_t*)argv;
2460
2461 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == ERROR)
2462 hperh->error_code |= I2C_ERROR_TIMEOUT;
2463
2464 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
2465 CLEAR_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK);
2466
2467 hperh->xfer_count = 0;
2468 hperh->state = I2C_STATE_READY;
2469 hperh->mode = I2C_MODE_NONE;
2470 __UNLOCK(hperh);
2471
2472 if (hperh->error_code != I2C_ERROR_NONE) {
2473 if (hperh->error_callback)
2474 hperh->error_callback(hperh);
2475 }
2476 else {
2477 if (hperh->master_rx_cplt_cbk)
2478 hperh->master_rx_cplt_cbk(hperh);
2479 }
2480 }
2481
2487 static void i2c_dma_slave_recv_cplt(void *argv)
2488 {
2489 i2c_handle_t* hperh = (i2c_handle_t*)argv;
2490
2491 CLEAR_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK);
2492
2493 hperh->xfer_count = 0;
2494 hperh->state = I2C_STATE_READY;
2495 hperh->mode = I2C_MODE_NONE;
2496 __UNLOCK(hperh);
2497
2498 if (hperh->error_code != I2C_ERROR_NONE) {
2499 if (hperh->error_callback)
2500 hperh->error_callback(hperh);
2501 }
2502 else {
2503 if (hperh->slave_rx_cplt_cbk)
2504 hperh->slave_rx_cplt_cbk(hperh);
2505 }
2506 }
2507
2513 static void i2c_dma_mem_send_cplt(void *argv)
2514 {
2515 i2c_handle_t* hperh = (i2c_handle_t*)argv;
2516
2517 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == ERROR)
2518 hperh->error_code |= I2C_ERROR_TIMEOUT;
2519
2520 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
2521 CLEAR_BIT(hperh->perh->CON1, I2C_CON1_TXDMAEN_MSK);
2522
2523 hperh->xfer_count = 0;
2524 hperh->state = I2C_STATE_READY;
2525 hperh->mode = I2C_MODE_NONE;
2526 __UNLOCK(hperh);
2527
2528 if (hperh->error_code != I2C_ERROR_NONE) {
2529 if (hperh->error_callback)
2530 hperh->error_callback(hperh);
2531 }
2532 else {
2533 if (hperh->mem_tx_cplt_cbk)
2534 hperh->mem_tx_cplt_cbk(hperh);
2535 }
2536 }
2537
2543 static void i2c_dma_mem_recv_cplt(void *argv)
2544 {
2545 i2c_handle_t* hperh = (i2c_handle_t*)argv;
2546
2547 if (i2c_wait_flag_change_to_timeout(hperh, I2C_STAT_TC, RESET, I2C_TIMEOUT_FLAG) == OK)
2548 hperh->error_code |= I2C_ERROR_TIMEOUT;
2549
2550 SET_BIT(hperh->perh->CON2, I2C_CON2_STOP_MSK);
2551 CLEAR_BIT(hperh->perh->CON1, I2C_CON1_RXDMAEN_MSK);
2552
2553 hperh->xfer_count = 0;
2554 hperh->state = I2C_STATE_READY;
2555 hperh->mode = I2C_MODE_NONE;
2556 __UNLOCK(hperh);
2557
2558 if (hperh->error_code != I2C_ERROR_NONE) {
2559 if (hperh->error_callback)
2560 hperh->error_callback(hperh);
2561 }
2562 else {
2563 if (hperh->mem_rx_cplt_cbk)
2564 hperh->mem_rx_cplt_cbk(hperh);
2565 }
2566 }
2567
2573 static void i2c_dma_error(void *argv)
2574 {
2575 i2c_handle_t* hperh = (i2c_handle_t*)argv;
2576
2577 hperh->xfer_count = 0;
2578 hperh->state = I2C_STATE_READY;
2579 hperh->mode = I2C_MODE_NONE;
2580 hperh->error_code |= I2C_ERROR_DMA;
2581 __UNLOCK(hperh);
2582
2583 if (hperh->error_callback)
2584 hperh->error_callback(hperh);
2585 }
2586 #endif
2587
2597 static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
2598 {
2599 uint32_t tickstart = 0;
2600
2601 tickstart = ald_get_tick();
2602 if (status == RESET) {
2603 while (I2C_GET_FLAG(hperh, flag) == RESET) {
2604 if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) {
2605 hperh->error_code |= I2C_ERROR_TIMEOUT;
2606 return TIMEOUT;
2607 }
2608 }
2609 }
2610 else {
2611 while (I2C_GET_FLAG(hperh, flag) != RESET) {
2612 if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) {
2613 hperh->error_code |= I2C_ERROR_TIMEOUT;
2614 return TIMEOUT;
2615 }
2616 }
2617 }
2618
2619 return OK;
2620 }
2621
2630 static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, uint32_t flag, uint32_t timeout)
2631 {
2632 uint32_t tickstart = ald_get_tick();
2633
2634 while (I2C_GET_IT_FLAG(hperh, flag) == RESET) {
2635 if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout)) {
2636 hperh->error_code = I2C_ERROR_TIMEOUT;
2637
2638 return ERROR;
2639 }
2640 }
2641
2642 return OK;
2643 }
2644
2652 static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout)
2653 {
2654 uint32_t tickstart = ald_get_tick();
2655
2656 while (I2C_GET_FLAG(hperh, I2C_STAT_THTH) == RESET) {
2657 if (I2C_GET_IT_FLAG(hperh, I2C_IT_ARLO)) {
2658 hperh->error_code |= I2C_ERROR_ARLO;
2659 return ERROR;
2660 }
2661
2662 if (I2C_GET_IT_FLAG(hperh, I2C_IT_NACK) == SET) {
2663 hperh->error_code |= I2C_ERROR_AF;
2664 return ERROR;
2665 }
2666
2667 if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) {
2668 hperh->error_code |= I2C_ERROR_TIMEOUT;
2669 return ERROR;
2670 }
2671 }
2672
2673 return OK;
2674 }
2675
2683 static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeout)
2684 {
2685 uint32_t tickstart = ald_get_tick();
2686
2687 while (I2C_GET_FLAG(hperh, I2C_STAT_RXTH) == RESET) {
2688 if ((timeout == 0) || ((ald_get_tick() - tickstart) > timeout)) {
2689 hperh->error_code |= I2C_ERROR_TIMEOUT;
2690 return ERROR;
2691 }
2692 }
2693
2694 return OK;
2695 }
2696
2701 #endif /* ALD_I2C */
2702
i2c_init_t::clk_speed
uint32_t clk_speed
Definition: ald_i2c.h:257
ald_i2c_master_send
ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size, uint32_t timeout)
Transmits in master mode an amount of data in blocking mode.
Definition: ald_i2c.c:480
I2C_ERROR_AF
Definition: ald_i2c.h:48
I2C_STATE_BUSY_TX
Definition: ald_i2c.h:65
i2c_handle_s::mem_rx_cplt_cbk
void(* mem_rx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:289
ENABLE
Definition: type.h:49
ald_i2c_master_recv_by_it
ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
Definition: ald_i2c.c:861
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
i2c_dma_mem_send_cplt
static void i2c_dma_mem_send_cplt(void *argv)
DMA I2C Memory Write process complete callback.
Definition: ald_i2c.c:2513
i2c_slave_send_txe
static ald_status_t i2c_slave_send_txe(i2c_handle_t *hperh)
Handle TXE flag for Slave Transmit mode.
Definition: ald_i2c.c:2212
ald_i2c_slave_recv
ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Receive in slave mode an amount of data in blocking mode.
Definition: ald_i2c.c:744
i2c_handle_s::hdmatx
dma_handle_t hdmatx
Definition: ald_i2c.h:276
ald_i2c_get_it_status
it_status_t ald_i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it)
Get the status of I2C interrupt source.
Definition: ald_i2c.c:2041
I2C_FREQ_RANGE
#define I2C_FREQ_RANGE(__PCLK__)
Definition: ald_i2c.h:332
ald_i2c_interrupt_config
void ald_i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state)
Enable/disable the specified I2C interrupts.
Definition: ald_i2c.c:2018
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
i2c_dma_slave_send_cplt
static void i2c_dma_slave_send_cplt(void *argv)
DMA I2C slave transmit process complete callback.
Definition: ald_i2c.c:2431
I2C_STAT_TXE
Definition: ald_i2c.h:205
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
I2C_ERROR_RUD
Definition: ald_i2c.h:47
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
i2c_addr_size_t
i2c_addr_size_t
I2C Memory Address Size.
Definition: ald_i2c.h:106
IS_I2C_NO_STRETCH
#define IS_I2C_NO_STRETCH(STRETCH)
Definition: ald_i2c.h:329
SET
Definition: type.h:39
ald_i2c_master_recv
ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size, uint32_t timeout)
Receives in master mode an amount of data in blocking mode.
Definition: ald_i2c.c:576
I2C_STAT_RXTH
Definition: ald_i2c.h:214
DMA_MSIGSEL_I2C_TXEMPTY
Definition: ald_dma.h:144
I2C_MODE_MEM
Definition: ald_i2c.h:118
type_func_t
type_func_t
Definition: type.h:47
i2c_wait_rxne_to_timeout
static ald_status_t i2c_wait_rxne_to_timeout(i2c_handle_t *hperh, uint32_t timeout)
This function handles I2C Communication timeout for specific usage of RXNE flag.
Definition: ald_i2c.c:2683
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
I2C_IT_TXE
Definition: ald_i2c.h:225
I2C_IT_RXF
Definition: ald_i2c.h:229
i2c_init_t::module
i2c_module_t module
Definition: ald_i2c.h:256
i2c_interrupt_t
i2c_interrupt_t
Interrupt Configuration Definition.
Definition: ald_i2c.h:224
DMA_MSIGSEL_I2C_RNR
Definition: ald_dma.h:143
i2c_wait_txe_to_timeout
static ald_status_t i2c_wait_txe_to_timeout(i2c_handle_t *hperh, uint32_t timeout)
This function handles I2C Communication timeout for specific usage of TXE flag.
Definition: ald_i2c.c:2652
I2C_DISABLE
#define I2C_DISABLE(x)
Definition: ald_i2c.h:311
IS_I2C_TYPE
#define IS_I2C_TYPE(x)
Definition: ald_i2c.h:319
i2c_dma_slave_recv_cplt
static void i2c_dma_slave_recv_cplt(void *argv)
DMA I2C slave receive process complete callback.
Definition: ald_i2c.c:2487
i2c_init_t::no_stretch
i2c_nostretch_t no_stretch
Definition: ald_i2c.h:263
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
i2c_handle_s::init
i2c_init_t init
Definition: ald_i2c.h:271
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
ald_i2c_ev_irq_handler
void ald_i2c_ev_irq_handler(i2c_handle_t *hperh)
This function handles I2C event interrupt request.
Definition: ald_i2c.c:1854
I2C_ENABLE
#define I2C_ENABLE(x)
Definition: ald_i2c.h:310
I2C_TIMEOUT_FLAG
#define I2C_TIMEOUT_FLAG
Definition: ald_i2c.c:171
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
i2c_handle_s::mem_tx_cplt_cbk
void(* mem_tx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:288
dma_config_t::src
void * src
Definition: ald_dma.h:278
I2C_STAT_BUSY
Definition: ald_i2c.h:217
ald_i2c_mem_read
ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout)
Read an amount of data in blocking mode from a specific memory address.
Definition: ald_i2c.c:1378
IS_I2C_IT
#define IS_I2C_IT(x)
Definition: ald_i2c.h:336
i2c_dma_error
static void i2c_dma_error(void *argv)
DMA I2C communication error callback.
Definition: ald_i2c.c:2573
i2c_init_t::dual_addr
i2c_dual_addr_t dual_addr
Definition: ald_i2c.h:260
I2C_MEM_ADD_LSB
#define I2C_MEM_ADD_LSB(__ADDRESS__)
Definition: ald_i2c.h:335
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
ald_i2c_mem_read_by_it
ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint32_t size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address...
Definition: ald_i2c.c:1566
I2C_TIMEOUT_BUSY_FLAG
#define I2C_TIMEOUT_BUSY_FLAG
Definition: ald_i2c.c:173
ald_i2c_master_recv_by_dma
ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint8_t size, uint8_t channel)
Receive in master mode an amount of data in non-blocking mode with DMA.
Definition: ald_i2c.c:1070
i2c_handle_s::lock
lock_state_t lock
Definition: ald_i2c.h:279
UNLOCK
Definition: type.h:59
I2C_MODULE_SLAVE
Definition: ald_i2c.h:198
DMA_DATA_SIZE_BYTE
Definition: ald_dma.h:227
ald_i2c_mem_write_by_dma
ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint8_t size, uint8_t channel)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
Definition: ald_i2c.c:1641
I2C_MEM_ADD_MSB
#define I2C_MEM_ADD_MSB(__ADDRESS__)
Definition: ald_i2c.h:333
RESET
Definition: type.h:38
ald_i2c_get_state
i2c_state_t ald_i2c_get_state(i2c_handle_t *hperh)
Return the I2C handle state.
Definition: ald_i2c.c:1825
I2C_STATE_BUSY
Definition: ald_i2c.h:64
I2C_ERROR_TUD
Definition: ald_i2c.h:51
I2C_ERROR_NONE
Definition: ald_i2c.h:44
i2c_master_send_tc
static ald_status_t i2c_master_send_tc(i2c_handle_t *hperh)
Handle transmit complete flag for Master Transmit mode.
Definition: ald_i2c.c:2124
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
ald_i2c_slave_send
ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Transmits in slave mode an amount of data in blocking mode.
Definition: ald_i2c.c:666
I2C_IT_ALERT
Definition: ald_i2c.h:242
i2c_init_t::general_call
i2c_general_addr_t general_call
Definition: ald_i2c.h:262
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
ald_i2c_reset
ald_status_t ald_i2c_reset(i2c_handle_t *hperh)
DeInitialize the I2C peripheral.
Definition: ald_i2c.c:381
I2C_ERROR_BERR
Definition: ald_i2c.h:45
i2c_slave_stopf
static ald_status_t i2c_slave_stopf(i2c_handle_t *hperh)
Handle STOPF flag for Slave mode.
Definition: ald_i2c.c:2244
i2c_wait_flag_change_to_timeout
static ald_status_t i2c_wait_flag_change_to_timeout(i2c_handle_t *hperh, uint32_t flag, flag_status_t status, uint32_t timeout)
This function handles I2C Communication timeout.
Definition: ald_i2c.c:2597
I2C_STAT_TCR
Definition: ald_i2c.h:216
I2C_ADDR_10BIT
Definition: ald_i2c.h:76
I2C_FLAG_MASK
#define I2C_FLAG_MASK
Definition: ald_i2c.h:300
I2C_IT_BERR
Definition: ald_i2c.h:238
it_status_t
enum flag_status_t it_status_t
I2C_GET_IT_FLAG
#define I2C_GET_IT_FLAG(x, y)
Definition: ald_i2c.h:305
IS_I2C_ADDRESSING_MODE
#define IS_I2C_ADDRESSING_MODE(ADDRESS)
Definition: ald_i2c.h:321
i2c_master_recv_tc
static ald_status_t i2c_master_recv_tc(i2c_handle_t *hperh)
Handle receive complete for Master Receive mode.
Definition: ald_i2c.c:2169
IS_I2C_MEMADD_size
#define IS_I2C_MEMADD_size(size)
Definition: ald_i2c.h:327
I2C_MODE_SLAVE
Definition: ald_i2c.h:117
i2c_master_recv_rxne
static ald_status_t i2c_master_recv_rxne(i2c_handle_t *hperh)
Handle receive not empty for Master Receive mode.
Definition: ald_i2c.c:2196
DMA_MSEL_I2C0
Definition: ald_dma.h:92
i2c_master_req_write
static ald_status_t i2c_master_req_write(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout)
Master sends target device address followed by internal memory address for write request.
Definition: ald_i2c.c:2275
I2C_MODE_MASTER
Definition: ald_i2c.h:116
I2C_STATE_RESET
Definition: ald_i2c.h:62
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
ald_i2c_clear_flag_status
void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag)
Clear the I2C interrupt flag.
Definition: ald_i2c.c:2101
i2c_handle_s::error_callback
void(* error_callback)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:290
IS_I2C_CLOCK_SPEED
#define IS_I2C_CLOCK_SPEED(SPEED)
Definition: ald_i2c.h:331
i2c_master_send_txe
static ald_status_t i2c_master_send_txe(i2c_handle_t *hperh)
Handle transmit empty flag for Master Transmit mode.
Definition: ald_i2c.c:2153
I2C_STAT_TC
Definition: ald_i2c.h:215
I2C_STATE_BUSY_RX
Definition: ald_i2c.h:66
I2C_DUALADDR_ENABLE
Definition: ald_i2c.h:84
i2c_req_mem_read
static ald_status_t i2c_req_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout)
Master sends target device address followed by internal memory address for read request.
Definition: ald_i2c.c:2356
ald_i2c.h
Header file of I2C driver.
I2C_IT_ADDR
Definition: ald_i2c.h:235
I2C_ERROR_TIMEOUT
Definition: ald_i2c.h:55
ald_i2c_get_error
uint32_t ald_i2c_get_error(i2c_handle_t *hperh)
Return the I2C error code.
Definition: ald_i2c.c:1836
I2C_STAT_THTH
Definition: ald_i2c.h:209
I2C_ERROR_ARLO
Definition: ald_i2c.h:46
I2C_IT_ARLO
Definition: ald_i2c.h:239
ald_i2c_get_flag_status
flag_status_t ald_i2c_get_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag)
Get the status of I2C interrupt flag.
Definition: ald_i2c.c:2063
ald_i2c_slave_send_by_it
ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint32_t size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
Definition: ald_i2c.c:914
ald_i2c_slave_recv_by_dma
ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel)
Receive in slave mode an amount of data in non-blocking mode with DMA.
Definition: ald_i2c.c:1202
I2C_ERROR_TOV
Definition: ald_i2c.h:52
I2C_IT_TOUT
Definition: ald_i2c.h:241
I2C_FAST_MODE_MAX_CLK
Definition: ald_i2c.h:126
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
IS_I2C_GENERAL_CALL
#define IS_I2C_GENERAL_CALL(CALL)
Definition: ald_i2c.h:325
I2C_STANDARD_MODE_MAX_CLK
Definition: ald_i2c.h:125
i2c_handle_s::slave_rx_cplt_cbk
void(* slave_rx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:287
i2c_speed_init
ald_status_t i2c_speed_init(i2c_handle_t *hperh, uint32_t freqrange)
I2C Configuration Speed function.
Definition: ald_i2c.c:254
I2C_GET_FLAG
#define I2C_GET_FLAG(x, y)
Definition: ald_i2c.h:307
i2c_handle_s::slave_tx_cplt_cbk
void(* slave_tx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:286
i2c_dma_master_recv_cplt
static void i2c_dma_master_recv_cplt(void *argv)
DMA I2C master receive process complete callback.
Definition: ald_i2c.c:2457
I2C_MASTER_GET_DIR
#define I2C_MASTER_GET_DIR(x)
Definition: ald_i2c.h:308
DMA_DATA_INC_BYTE
Definition: ald_dma.h:217
I2C_IT_TXTH
Definition: ald_i2c.h:228
I2C_DISABLE_IT
#define I2C_DISABLE_IT(x, y)
Definition: ald_i2c.h:303
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
i2c_handle_s
I2C handle Structure definition.
Definition: ald_i2c.h:269
TIMEOUT
Definition: utils.h:58
I2C_IT_NACK
Definition: ald_i2c.h:236
I2C_ERROR_ROV
Definition: ald_i2c.h:49
i2c_state_t
i2c_state_t
I2C state structure definition.
Definition: ald_i2c.h:61
ald_cmu_get_pclk1_clock
uint32_t ald_cmu_get_pclk1_clock(void)
Get APB1 clock.
Definition: ald_cmu.c:627
i2c_wait_master_addr_to_timeout
static ald_status_t i2c_wait_master_addr_to_timeout(i2c_handle_t *hperh, uint32_t flag, uint32_t timeout)
This function handles I2C Communication timeout for Master addressing phase.
Definition: ald_i2c.c:2630
ald_i2c_slave_send_by_dma
ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
Definition: ald_i2c.c:1135
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
I2C_IT_RXUD
Definition: ald_i2c.h:231
i2c_init_t::addr_mode
i2c_addr_t addr_mode
Definition: ald_i2c.h:259
I2C_ERROR_DMA
Definition: ald_i2c.h:54
I2C_MEMADD_SIZE_8BIT
Definition: ald_i2c.h:107
I2C_TIMEOUT_ADDR_SLAVE
#define I2C_TIMEOUT_ADDR_SLAVE
Definition: ald_i2c.c:172
i2c_init_t::own_addr2
uint32_t own_addr2
Definition: ald_i2c.h:261
ald_i2c_slave_recv_by_it
ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint32_t size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
Definition: ald_i2c.c:956
ald_i2c_master_send_by_dma
ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint8_t size, uint8_t channel)
Transmit in master mode an amount of data in non-blocking mode with DMA.
Definition: ald_i2c.c:1001
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_I2C_MODULE
#define IS_I2C_MODULE(x)
Definition: ald_i2c.h:320
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
i2c_handle_s::master_tx_cplt_cbk
void(* master_tx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:284
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
ald_i2c_er_irq_handler
void ald_i2c_er_irq_handler(i2c_handle_t *hperh)
This function handles I2C error interrupt request.
Definition: ald_i2c.c:1935
I2C_CLEAR_IT
#define I2C_CLEAR_IT(x, y)
Definition: ald_i2c.h:304
I2C_IT_TXUD
Definition: ald_i2c.h:227
i2c_slave_recv_rxne
static ald_status_t i2c_slave_recv_rxne(i2c_handle_t *hperh)
Handle RXNE flag for Slave Receive mode.
Definition: ald_i2c.c:2228
I2C_MODE_NONE
Definition: ald_i2c.h:115
ald_i2c_mem_read_by_dma
ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint8_t size, uint8_t channel)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
Definition: ald_i2c.c:1721
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
ald_i2c_init
ald_status_t ald_i2c_init(i2c_handle_t *hperh)
Initializes the I2C according to the specified parameters in the i2c_init_t and initialize the associ...
Definition: ald_i2c.c:319
I2C_MEMADD_SIZE_16BIT
Definition: ald_i2c.h:108
i2c_handle_s::master_rx_cplt_cbk
void(* master_rx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:285
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
flag_status_t
flag_status_t
Definition: type.h:37
i2c_dma_master_send_cplt
static void i2c_dma_master_send_cplt(void *argv)
DMA I2C master transmit process complete callback.
Definition: ald_i2c.c:2401
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
i2c_req_mem_write
static ald_status_t i2c_req_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, uint16_t add_size, uint32_t timeout)
Master sends target device address followed by internal memory address for write request.
Definition: ald_i2c.c:2323
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
I2C_ENABLE_IT
#define I2C_ENABLE_IT(x, y)
Definition: ald_i2c.h:302
DMA_MSEL_I2C1
Definition: ald_dma.h:93
I2C_IT_TXOV
Definition: ald_i2c.h:226
I2C_IT_STOP
Definition: ald_i2c.h:237
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
ald_i2c_mem_write_by_it
ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint32_t size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
Definition: ald_i2c.c:1488
I2C_IT_TC
Definition: ald_i2c.h:233
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
i2c_init_t::own_addr1
uint32_t own_addr1
Definition: ald_i2c.h:258
I2C_IT_TCR
Definition: ald_i2c.h:234
i2c_dma_mem_recv_cplt
static void i2c_dma_mem_recv_cplt(void *argv)
DMA I2C Memory Read process complete callback.
Definition: ald_i2c.c:2543
I2C_ADDR_7BIT
Definition: ald_i2c.h:75
I2C_IT_RXTH
Definition: ald_i2c.h:232
__LOCK
#define __LOCK(x)
Definition: utils.h:92
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
I2C_IT_PECE
Definition: ald_i2c.h:240
ERROR
Definition: utils.h:56
ald_i2c_master_send_by_it
ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
Definition: ald_i2c.c:806
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
ald_i2c_get_mask_flag_status
flag_status_t ald_i2c_get_mask_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag)
Get the status of interrupt flag and interupt source.
Definition: ald_i2c.c:2084
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
i2c_handle_s::hdmarx
dma_handle_t hdmarx
Definition: ald_i2c.h:277
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
I2C_STATE_READY
Definition: ald_i2c.h:63
ald_i2c_mem_write
ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout)
Write an amount of data in blocking mode to a specific memory address.
Definition: ald_i2c.c:1272
i2c_master_req_read
static ald_status_t i2c_master_req_read(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t timeout)
Master sends target device address followed by internal memory address for read request.
Definition: ald_i2c.c:2298
I2C_IT_RXOV
Definition: ald_i2c.h:230


ALD User Manual: D:/svn/src/ald_i2c.h Source File

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  • svn
  • src
ald_i2c.h
Go to the documentation of this file.
1
17 #ifndef __ALD_I2C_H__
18 #define __ALD_I2C_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25 #include "ald_dma.h"
26 #include "ald_cmu.h"
27 #include <string.h>
28
43 typedef enum {
44 I2C_ERROR_NONE = 0x0U,
45 I2C_ERROR_BERR = 0x1U,
46 I2C_ERROR_ARLO = 0x2U,
47 I2C_ERROR_RUD = 0x4U,
48 I2C_ERROR_AF = 0x8U,
49 I2C_ERROR_ROV = 0x10U,
50 I2C_ERROR_RF = 0x20U,
51 I2C_ERROR_TUD = 0x40U,
52 I2C_ERROR_TOV = 0x80U,
53 I2C_ERROR_TE = 0x100U,
54 I2C_ERROR_DMA = 0x200U,
55 I2C_ERROR_TIMEOUT = 0x400U,
56 } i2c_error_t;
57
61 typedef enum {
62 I2C_STATE_RESET = 0x0U,
63 I2C_STATE_READY = 0x20U,
64 I2C_STATE_BUSY = 0x24U,
65 I2C_STATE_BUSY_TX = 0x21U,
66 I2C_STATE_BUSY_RX = 0x22U,
67 I2C_STATE_TIMEOUT = 0xA0U,
68 I2C_STATE_ERROR = 0xE0U,
69 } i2c_state_t;
70
74 typedef enum {
75 I2C_ADDR_7BIT = 0x0U,
76 I2C_ADDR_10BIT = 0x1U,
77 } i2c_addr_t;
78
82 typedef enum {
83 I2C_DUALADDR_DISABLE = 0x0U,
84 I2C_DUALADDR_ENABLE = 0x1U,
85 } i2c_dual_addr_t;
86
90 typedef enum {
91 I2C_GENERALCALL_DISABLE = 0x0U,
92 I2C_GENERALCALL_ENABLE = 0x1U,
93 } i2c_general_addr_t;
94
98 typedef enum {
99 I2C_NOSTRETCH_DISABLE = 0x0U,
100 I2C_NOSTRETCH_ENABLE = 0x1U,
101 } i2c_nostretch_t;
102
106 typedef enum {
107 I2C_MEMADD_SIZE_8BIT = 0x8U,
108 I2C_MEMADD_SIZE_16BIT = 0x10U,
109 } i2c_addr_size_t;
110
114 typedef enum {
115 I2C_MODE_NONE = 0x0U,
116 I2C_MODE_MASTER = 0x10U,
117 I2C_MODE_SLAVE = 0x20U,
118 I2C_MODE_MEM = 0x40U,
119 } i2c_mode_t;
120
124 typedef enum {
125 I2C_STANDARD_MODE_MAX_CLK = 100000U,
126 I2C_FAST_MODE_MAX_CLK = 400000U,
127 I2C_EXTREME_FAST_MODE_MAX_CLK = 1000000U,
128 } i2c_clock_t;
129
133 typedef enum {
134 I2C_OAR2_ENDUAL = (1U << 0),
135 I2C_OAR2_ADD2 = (1U << 1)
136 } i2c_oar2_t;
137
141 typedef enum {
142 I2C_CON1_PE = (1U << 0),
143 I2C_CON1_TXDMA = (1U << 14),
144 I2C_CON1_RXDMA = (1U << 15),
145 I2C_CON1_SBC = (1U << 16),
146 I2C_CON1_NOSTRETCH = (1U << 17),
147 I2C_CON1_GCEN = (1U << 19),
148 I2C_CON1_SMBHEN = (1U << 20),
149 I2C_CON1_SMBDEN = (1U << 21),
150 I2C_CON1_ALERTEN = (1U << 22),
151 I2C_CON1_PECEN = (1U << 23),
152 } i2c_con1_t;
153
157 typedef enum {
158 I2C_CON2_RD_WRN = (1U << 10),
159 I2C_CON2_ADD10 = (1U << 11),
160 I2C_CON2_HEAD10R = (1U << 12),
161 I2C_CON2_START = (1U << 13),
162 I2C_CON2_STOP = (1U << 14),
163 I2C_CON2_NACK = (1U << 15),
164 I2C_CON2_RELOAD = (1U << 24),
165 I2C_CON2_AUTOEND = (1U << 25),
166 I2C_CON2_PECBYTE = (1U << 26),
167 I2C_CON2_HOLDACK = (1U << 28),
168 } i2c_con2_t;
169
173 typedef enum {
174 I2C_OA1MODE = (1U << 10),
175 I2C_OA1EN = (1U << 15),
176 } i2c_addr1_t;
177
181 typedef enum {
182 I2C_OA2EN = (1U << 15),
183 } i2c_addr2_t;
184
188 typedef enum {
189 I2C_TIMEOUTR_TIDLE = (1U << 12),
190 I2C_TIMEOUTR_TIMEOUTEN = (1U << 15),
191 } i2c_timoutr_t;
192
196 typedef enum {
197 I2C_MODULE_MASTER = (1U << 0),
198 I2C_MODULE_SLAVE = (1U << 1)
199 } i2c_module_t;
200
204 typedef enum {
205 I2C_STAT_TXE = (1U << 0),
206 I2C_STAT_TXF = (1U << 1),
207 I2C_STAT_TXOV = (1U << 2),
208 I2C_STAT_TXUD = (1U << 3),
209 I2C_STAT_THTH = (1U << 4),
210 I2C_STAT_RXE = (1U << 5),
211 I2C_STAT_RXF = (1U << 6),
212 I2C_STAT_RXOV = (1U << 7),
213 I2C_STAT_RXUD = (1U << 8),
214 I2C_STAT_RXTH = (1U << 9),
215 I2C_STAT_TC = (1U << 10),
216 I2C_STAT_TCR = (1U << 11),
217 I2C_STAT_BUSY = (1U << 15),
218 I2C_STAT_DIR = (1U << 16),
219 } i2c_stat_t;
220
224 typedef enum {
225 I2C_IT_TXE = (1U << 0),
226 I2C_IT_TXOV = (1U << 2),
227 I2C_IT_TXUD = (1U << 3),
228 I2C_IT_TXTH = (1U << 4),
229 I2C_IT_RXF = (1U << 6),
230 I2C_IT_RXOV = (1U << 7),
231 I2C_IT_RXUD = (1U << 8),
232 I2C_IT_RXTH = (1U << 9),
233 I2C_IT_TC = (1U << 10),
234 I2C_IT_TCR = (1U << 11),
235 I2C_IT_ADDR = (1U << 12),
236 I2C_IT_NACK = (1U << 13),
237 I2C_IT_STOP = (1U << 14),
238 I2C_IT_BERR = (1U << 16),
239 I2C_IT_ARLO = (1U << 17),
240 I2C_IT_PECE = (1U << 18),
241 I2C_IT_TOUT = (1U << 19),
242 I2C_IT_ALERT = (1U << 20),
243 } i2c_interrupt_t;
244
248 typedef enum {
249 I2C_TRISE_TRISE = 0x3FU,
250 } i2c_trise_t;
251
255 typedef struct {
256 i2c_module_t module;
257 uint32_t clk_speed;
258 uint32_t own_addr1;
259 i2c_addr_t addr_mode;
260 i2c_dual_addr_t dual_addr;
261 uint32_t own_addr2;
262 i2c_general_addr_t general_call;
263 i2c_nostretch_t no_stretch;
264 } i2c_init_t;
265
269 typedef struct i2c_handle_s {
270 I2C_TypeDef *perh;
271 i2c_init_t init;
272 uint8_t *p_buff;
273 uint16_t xfer_size;
274 __IO uint16_t xfer_count;
275 #ifdef ALD_DMA
276 dma_handle_t hdmatx;
277 dma_handle_t hdmarx;
278 #endif
279 lock_state_t lock;
280 __IO i2c_state_t state;
281 __IO i2c_mode_t mode;
282 __IO uint32_t error_code;
284 void (*master_tx_cplt_cbk)(struct i2c_handle_s *arg);
285 void (*master_rx_cplt_cbk)(struct i2c_handle_s *arg);
286 void (*slave_tx_cplt_cbk)(struct i2c_handle_s *arg);
287 void (*slave_rx_cplt_cbk)(struct i2c_handle_s *arg);
288 void (*mem_tx_cplt_cbk)(struct i2c_handle_s *arg);
289 void (*mem_rx_cplt_cbk)(struct i2c_handle_s *arg);
290 void (*error_callback)(struct i2c_handle_s *arg);
291 } i2c_handle_t;
292
300 #define I2C_FLAG_MASK (0xFFFFFFFFU)
301 #define I2C_RESET_HANDLE_STATE(x) ((x)->state = I2C_STATE_RESET)
302 #define I2C_ENABLE_IT(x, y) (SET_BIT((x)->perh->IER, (y)))
303 #define I2C_DISABLE_IT(x, y) (SET_BIT((x)->perh->IDR, (y)))
304 #define I2C_CLEAR_IT(x, y) (SET_BIT((x)->perh->ICR, (y)))
305 #define I2C_GET_IT_FLAG(x, y) (READ_BIT((x)->perh->RIF, (y)))
306 #define I2C_GET_IT_SOURCE(x, y) ((((x)->perh->IFM & (y)) == (y)) ? SET : RESET)
307 #define I2C_GET_FLAG(x, y) ((((x)->perh->STAT) & ((y) & I2C_FLAG_MASK)) != RESET)
308 #define I2C_MASTER_GET_DIR(x) (READ_BIT(((x)->perh->CON2), I2C_CON2_RD_WRN_MSK))
309 #define I2C_SLAVE_GET_DIR(x) (READ_BIT(hperh->perh->STAT, I2C_STAT_DIR_MSK))
310 #define I2C_ENABLE(x) (SET_BIT((x)->perh->CON1, I2C_CON1_PE_MSK))
311 #define I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PE_MSK))
312
319 #define IS_I2C_TYPE(x) (((x) == I2C0) || ((x) == I2C1))
320 #define IS_I2C_MODULE(x) (((x) == I2C_MODULE_MASTER) || ((x) == I2C_MODULE_SLAVE))
321 #define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDR_7BIT) || \
322 ((ADDRESS) == I2C_ADDR_10BIT))
323 #define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDR_DISABLE) || \
324 ((ADDRESS) == I2C_DUALADDR_ENABLE))
325 #define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
326 ((CALL) == I2C_GENERALCALL_ENABLE))
327 #define IS_I2C_MEMADD_size(size) (((size) == I2C_MEMADD_SIZE_8BIT) || \
328 ((size) == I2C_MEMADD_SIZE_16BIT))
329 #define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
330 ((STRETCH) == I2C_NOSTRETCH_ENABLE))
331 #define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= I2C_EXTREME_FAST_MODE_MAX_CLK) )
332 #define I2C_FREQ_RANGE(__PCLK__) ((__PCLK__) / 1000000)
333 #define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) &\
334 (uint16_t)(0xFF00))) >> 8)))
335 #define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
336 #define IS_I2C_IT(x) (((x) == I2C_IT_TXE) || \
337 ((x) == I2C_IT_TXOV) || \
338 ((x) == I2C_IT_TXUD) || \
339 ((x) == I2C_IT_TXTH) || \
340 ((x) == I2C_IT_RXF) || \
341 ((x) == I2C_IT_RXOV) || \
342 ((x) == I2C_IT_RXUD) || \
343 ((x) == I2C_IT_RXTH) || \
344 ((x) == I2C_IT_TC) || \
345 ((x) == I2C_IT_TCR) || \
346 ((x) == I2C_IT_ADDR) || \
347 ((x) == I2C_IT_NACK) || \
348 ((x) == I2C_IT_STOP) || \
349 ((x) == I2C_IT_BERR) || \
350 ((x) == I2C_IT_ARLO) || \
351 ((x) == I2C_IT_PECE) || \
352 ((x) == I2C_IT_TOUT) || \
353 ((x) == I2C_IT_ALERT))
354
365 ald_status_t ald_i2c_init(i2c_handle_t *hperh);
366 ald_status_t ald_i2c_reset(i2c_handle_t *hperh);
367
376 ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr,
377 uint8_t *buf, uint32_t size, uint32_t timeout);
378 ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr,
379 uint8_t *buf, uint32_t size, uint32_t timeout);
380 ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout);
381 ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout);
382 ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
383 i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout);
384 ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
385 i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout);
386
388 ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size);
389 ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size);
390 ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint32_t size);
391 ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint32_t size);
392 ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
393 i2c_addr_size_t add_size, uint8_t *buf, uint32_t size);
394 ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
395 i2c_addr_size_t add_size, uint8_t *buf, uint32_t size);
396
397 #ifdef ALD_DMA
398
399 ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr,
400 uint8_t *buf, uint8_t size, uint8_t channel);
401 ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr,
402 uint8_t *buf, uint8_t size, uint8_t channel);
403 ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel);
404 ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel);
405 ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size,
406 uint8_t *buf, uint8_t size, uint8_t channel);
407 ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
408 i2c_addr_size_t add_size, uint8_t *buf, uint8_t size, uint8_t channel);
409 #endif
410
417 i2c_state_t ald_i2c_get_state(i2c_handle_t *hperh);
418 uint32_t ald_i2c_get_error(i2c_handle_t *hperh);
419 void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag);
420 flag_status_t ald_i2c_get_mask_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag);
421 flag_status_t ald_i2c_get_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag);
422 it_status_t ald_i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it);
430 void ald_i2c_ev_irq_handler(i2c_handle_t *hperh);
431 void ald_i2c_er_irq_handler(i2c_handle_t *hperh);
432 void ald_i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state);
448 #ifdef __cplusplus
449 }
450 #endif
451
452 #endif /* __ALD_I2C_H__ */
I2C_ERROR_TE
Definition: ald_i2c.h:53
i2c_init_t::clk_speed
uint32_t clk_speed
Definition: ald_i2c.h:257
ald_i2c_get_flag_status
flag_status_t ald_i2c_get_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag)
Get the status of I2C interrupt flag.
Definition: ald_i2c.c:2063
I2C_CON1_PECEN
Definition: ald_i2c.h:151
ald_i2c_master_send
ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size, uint32_t timeout)
Transmits in master mode an amount of data in blocking mode.
Definition: ald_i2c.c:480
I2C_ERROR_AF
Definition: ald_i2c.h:48
I2C_STATE_BUSY_TX
Definition: ald_i2c.h:65
I2C_GENERALCALL_ENABLE
Definition: ald_i2c.h:92
i2c_handle_s::mem_rx_cplt_cbk
void(* mem_rx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:289
ald_i2c_master_recv_by_it
ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size)
Receive in master mode an amount of data in non-blocking mode with Interrupt.
Definition: ald_i2c.c:861
I2C_TRISE_TRISE
Definition: ald_i2c.h:249
I2C_STAT_TXF
Definition: ald_i2c.h:206
ald_i2c_slave_recv
ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Receive in slave mode an amount of data in blocking mode.
Definition: ald_i2c.c:744
I2C_ERROR_RF
Definition: ald_i2c.h:50
i2c_handle_s::hdmatx
dma_handle_t hdmatx
Definition: ald_i2c.h:276
dma_handle_t
DMA handle structure definition.
Definition: ald_dma.h:297
ald_i2c_interrupt_config
void ald_i2c_interrupt_config(i2c_handle_t *hperh, i2c_interrupt_t it, type_func_t state)
Enable/disable the specified I2C interrupts.
Definition: ald_i2c.c:2018
I2C_STAT_RXF
Definition: ald_i2c.h:211
I2C_NOSTRETCH_ENABLE
Definition: ald_i2c.h:100
I2C_STAT_TXE
Definition: ald_i2c.h:205
i2c_con2_t
i2c_con2_t
I2C CON2 Register.
Definition: ald_i2c.h:157
I2C_CON1_SMBHEN
Definition: ald_i2c.h:148
I2C_CON1_TXDMA
Definition: ald_i2c.h:143
i2c_timoutr_t
i2c_timoutr_t
I2C TIMEOUTR Register.
Definition: ald_i2c.h:188
I2C_ERROR_RUD
Definition: ald_i2c.h:47
I2C_STAT_RXE
Definition: ald_i2c.h:210
i2c_addr_size_t
i2c_addr_size_t
I2C Memory Address Size.
Definition: ald_i2c.h:106
I2C_CON1_PE
Definition: ald_i2c.h:142
ald_i2c_master_recv
ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size, uint32_t timeout)
Receives in master mode an amount of data in blocking mode.
Definition: ald_i2c.c:576
I2C_STAT_RXTH
Definition: ald_i2c.h:214
I2C_MODE_MEM
Definition: ald_i2c.h:118
type_func_t
type_func_t
Definition: type.h:47
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
i2c_stat_t
i2c_stat_t
I2C STAT Register.
Definition: ald_i2c.h:204
I2C_OA1MODE
Definition: ald_i2c.h:174
I2C_IT_TXE
Definition: ald_i2c.h:225
I2C_IT_RXF
Definition: ald_i2c.h:229
i2c_init_t::module
i2c_module_t module
Definition: ald_i2c.h:256
i2c_interrupt_t
i2c_interrupt_t
Interrupt Configuration Definition.
Definition: ald_i2c.h:224
I2C_MODULE_MASTER
Definition: ald_i2c.h:197
i2c_init_t::no_stretch
i2c_nostretch_t no_stretch
Definition: ald_i2c.h:263
I2C_CON1_RXDMA
Definition: ald_i2c.h:144
i2c_handle_s::init
i2c_init_t init
Definition: ald_i2c.h:271
ald_i2c_ev_irq_handler
void ald_i2c_ev_irq_handler(i2c_handle_t *hperh)
This function handles I2C event interrupt request.
Definition: ald_i2c.c:1854
i2c_oar2_t
i2c_oar2_t
I2C OAR2 Register.
Definition: ald_i2c.h:133
i2c_handle_s::p_buff
uint8_t * p_buff
Definition: ald_i2c.h:272
i2c_handle_s::mem_tx_cplt_cbk
void(* mem_tx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:288
i2c_trise_t
i2c_trise_t
I2C TRISE Register.
Definition: ald_i2c.h:248
I2C_STAT_BUSY
Definition: ald_i2c.h:217
ald_i2c_mem_read
ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout)
Read an amount of data in blocking mode from a specific memory address.
Definition: ald_i2c.c:1378
I2C_CON1_NOSTRETCH
Definition: ald_i2c.h:146
I2C_CON2_PECBYTE
Definition: ald_i2c.h:166
i2c_init_t::dual_addr
i2c_dual_addr_t dual_addr
Definition: ald_i2c.h:260
i2c_dual_addr_t
i2c_dual_addr_t
I2C Dual Addressing Mode.
Definition: ald_i2c.h:82
i2c_handle_s::xfer_count
__IO uint16_t xfer_count
Definition: ald_i2c.h:274
ald_i2c_mem_read_by_it
ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint32_t size)
Read an amount of data in non-blocking mode with Interrupt from a specific memory address...
Definition: ald_i2c.c:1566
ald_i2c_master_recv_by_dma
ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint8_t size, uint8_t channel)
Receive in master mode an amount of data in non-blocking mode with DMA.
Definition: ald_i2c.c:1070
i2c_handle_s::lock
lock_state_t lock
Definition: ald_i2c.h:279
i2c_module_t
i2c_module_t
I2C peripherals module.
Definition: ald_i2c.h:196
I2C_MODULE_SLAVE
Definition: ald_i2c.h:198
ald_i2c_mem_write_by_dma
ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint8_t size, uint8_t channel)
Write an amount of data in non-blocking mode with DMA to a specific memory address.
Definition: ald_i2c.c:1641
I2C_CON1_SMBDEN
Definition: ald_i2c.h:149
ald_i2c_get_state
i2c_state_t ald_i2c_get_state(i2c_handle_t *hperh)
Return the I2C handle state.
Definition: ald_i2c.c:1825
I2C_STATE_BUSY
Definition: ald_i2c.h:64
I2C_OAR2_ADD2
Definition: ald_i2c.h:135
I2C_ERROR_TUD
Definition: ald_i2c.h:51
I2C_ERROR_NONE
Definition: ald_i2c.h:44
I2C_STATE_TIMEOUT
Definition: ald_i2c.h:67
I2C_CON2_AUTOEND
Definition: ald_i2c.h:165
i2c_handle_s::mode
__IO i2c_mode_t mode
Definition: ald_i2c.h:281
I2C_GENERALCALL_DISABLE
Definition: ald_i2c.h:91
utils.h
This file contains the Utilities functions/types for the driver.
I2C_NOSTRETCH_DISABLE
Definition: ald_i2c.h:99
i2c_addr_t
i2c_addr_t
I2C Addressing Mode.
Definition: ald_i2c.h:74
ald_i2c_slave_send
ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Transmits in slave mode an amount of data in blocking mode.
Definition: ald_i2c.c:666
I2C_IT_ALERT
Definition: ald_i2c.h:242
i2c_init_t::general_call
i2c_general_addr_t general_call
Definition: ald_i2c.h:262
ald_i2c_reset
ald_status_t ald_i2c_reset(i2c_handle_t *hperh)
DeInitialize the I2C peripheral.
Definition: ald_i2c.c:381
i2c_handle_s::xfer_size
uint16_t xfer_size
Definition: ald_i2c.h:273
I2C_ERROR_BERR
Definition: ald_i2c.h:45
I2C_STAT_TCR
Definition: ald_i2c.h:216
I2C_ADDR_10BIT
Definition: ald_i2c.h:76
I2C_OAR2_ENDUAL
Definition: ald_i2c.h:134
I2C_IT_BERR
Definition: ald_i2c.h:238
it_status_t
enum flag_status_t it_status_t
I2C_STATE_ERROR
Definition: ald_i2c.h:68
I2C_DUALADDR_DISABLE
Definition: ald_i2c.h:83
ald_i2c_get_it_status
it_status_t ald_i2c_get_it_status(i2c_handle_t *hperh, i2c_interrupt_t it)
Get the status of I2C interrupt source.
Definition: ald_i2c.c:2041
I2C_MODE_SLAVE
Definition: ald_i2c.h:117
i2c_con1_t
i2c_con1_t
I2C CON1 Register.
Definition: ald_i2c.h:141
I2C_OA2EN
Definition: ald_i2c.h:182
I2C_CON2_STOP
Definition: ald_i2c.h:162
I2C_MODE_MASTER
Definition: ald_i2c.h:116
I2C_STATE_RESET
Definition: ald_i2c.h:62
ald_i2c_get_mask_flag_status
flag_status_t ald_i2c_get_mask_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag)
Get the status of interrupt flag and interupt source.
Definition: ald_i2c.c:2084
i2c_handle_s::error_callback
void(* error_callback)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:290
I2C_STAT_TC
Definition: ald_i2c.h:215
I2C_STATE_BUSY_RX
Definition: ald_i2c.h:66
I2C_DUALADDR_ENABLE
Definition: ald_i2c.h:84
lock_state_t
lock_state_t
Definition: type.h:58
I2C_IT_ADDR
Definition: ald_i2c.h:235
ald_cmu.h
Header file of CMU module driver.
I2C_ERROR_TIMEOUT
Definition: ald_i2c.h:55
ald_dma.h
DMA module Library.
I2C_TIMEOUTR_TIDLE
Definition: ald_i2c.h:189
ald_i2c_get_error
uint32_t ald_i2c_get_error(i2c_handle_t *hperh)
Return the I2C error code.
Definition: ald_i2c.c:1836
I2C_STAT_THTH
Definition: ald_i2c.h:209
I2C_ERROR_ARLO
Definition: ald_i2c.h:46
I2C_IT_ARLO
Definition: ald_i2c.h:239
ald_i2c_slave_send_by_it
ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint32_t size)
Transmit in slave mode an amount of data in non-blocking mode with Interrupt.
Definition: ald_i2c.c:914
i2c_addr2_t
i2c_addr2_t
I2C ADDR2 Register.
Definition: ald_i2c.h:181
I2C_CON1_GCEN
Definition: ald_i2c.h:147
i2c_handle_t
struct i2c_handle_s i2c_handle_t
I2C handle Structure definition.
ald_i2c_slave_recv_by_dma
ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel)
Receive in slave mode an amount of data in non-blocking mode with DMA.
Definition: ald_i2c.c:1202
I2C_ERROR_TOV
Definition: ald_i2c.h:52
I2C_IT_TOUT
Definition: ald_i2c.h:241
I2C_FAST_MODE_MAX_CLK
Definition: ald_i2c.h:126
I2C_EXTREME_FAST_MODE_MAX_CLK
Definition: ald_i2c.h:127
I2C_STANDARD_MODE_MAX_CLK
Definition: ald_i2c.h:125
i2c_handle_s::slave_rx_cplt_cbk
void(* slave_rx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:287
i2c_nostretch_t
i2c_nostretch_t
I2C Nostretch Mode.
Definition: ald_i2c.h:98
i2c_handle_s::slave_tx_cplt_cbk
void(* slave_tx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:286
I2C_CON2_NACK
Definition: ald_i2c.h:163
I2C_IT_TXTH
Definition: ald_i2c.h:228
I2C_CON2_RELOAD
Definition: ald_i2c.h:164
I2C_STAT_TXUD
Definition: ald_i2c.h:208
I2C_CON2_START
Definition: ald_i2c.h:161
i2c_handle_s
I2C handle Structure definition.
Definition: ald_i2c.h:269
I2C_IT_NACK
Definition: ald_i2c.h:236
I2C_ERROR_ROV
Definition: ald_i2c.h:49
i2c_state_t
i2c_state_t
I2C state structure definition.
Definition: ald_i2c.h:61
ald_i2c_slave_send_by_dma
ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint8_t size, uint8_t channel)
Transmit in slave mode an amount of data in non-blocking mode with DMA.
Definition: ald_i2c.c:1135
I2C_IT_RXUD
Definition: ald_i2c.h:231
i2c_init_t::addr_mode
i2c_addr_t addr_mode
Definition: ald_i2c.h:259
I2C_ERROR_DMA
Definition: ald_i2c.h:54
I2C_MEMADD_SIZE_8BIT
Definition: ald_i2c.h:107
i2c_init_t::own_addr2
uint32_t own_addr2
Definition: ald_i2c.h:261
I2C_STAT_RXOV
Definition: ald_i2c.h:212
ald_i2c_slave_recv_by_it
ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint32_t size)
Receive in slave mode an amount of data in non-blocking mode with Interrupt.
Definition: ald_i2c.c:956
ald_i2c_master_send_by_dma
ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint8_t size, uint8_t channel)
Transmit in master mode an amount of data in non-blocking mode with DMA.
Definition: ald_i2c.c:1001
I2C_STAT_TXOV
Definition: ald_i2c.h:207
i2c_mode_t
i2c_mode_t
I2C mode structure definition.
Definition: ald_i2c.h:114
i2c_handle_s::master_tx_cplt_cbk
void(* master_tx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:284
I2C_CON1_SBC
Definition: ald_i2c.h:145
ald_i2c_er_irq_handler
void ald_i2c_er_irq_handler(i2c_handle_t *hperh)
This function handles I2C error interrupt request.
Definition: ald_i2c.c:1935
I2C_TIMEOUTR_TIMEOUTEN
Definition: ald_i2c.h:190
I2C_IT_TXUD
Definition: ald_i2c.h:227
I2C_MODE_NONE
Definition: ald_i2c.h:115
I2C_CON2_HOLDACK
Definition: ald_i2c.h:167
ald_i2c_mem_read_by_dma
ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint8_t size, uint8_t channel)
Reads an amount of data in non-blocking mode with DMA from a specific memory address.
Definition: ald_i2c.c:1721
i2c_clock_t
i2c_clock_t
I2C Clock.
Definition: ald_i2c.h:124
ald_i2c_init
ald_status_t ald_i2c_init(i2c_handle_t *hperh)
Initializes the I2C according to the specified parameters in the i2c_init_t and initialize the associ...
Definition: ald_i2c.c:319
I2C_MEMADD_SIZE_16BIT
Definition: ald_i2c.h:108
i2c_handle_s::master_rx_cplt_cbk
void(* master_rx_cplt_cbk)(struct i2c_handle_s *arg)
Definition: ald_i2c.h:285
flag_status_t
flag_status_t
Definition: type.h:37
I2C_STAT_RXUD
Definition: ald_i2c.h:213
i2c_init_t
I2C Configuration Structure definition.
Definition: ald_i2c.h:255
I2C_CON2_ADD10
Definition: ald_i2c.h:159
ald_i2c_clear_flag_status
void ald_i2c_clear_flag_status(i2c_handle_t *hperh, i2c_interrupt_t flag)
Clear the I2C interrupt flag.
Definition: ald_i2c.c:2101
I2C_OA1EN
Definition: ald_i2c.h:175
I2C_CON2_RD_WRN
Definition: ald_i2c.h:158
I2C_IT_TXOV
Definition: ald_i2c.h:226
I2C_IT_STOP
Definition: ald_i2c.h:237
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
ald_i2c_mem_write_by_it
ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint32_t size)
Write an amount of data in non-blocking mode with Interrupt to a specific memory address.
Definition: ald_i2c.c:1488
I2C_IT_TC
Definition: ald_i2c.h:233
I2C_CON1_ALERTEN
Definition: ald_i2c.h:150
i2c_init_t::own_addr1
uint32_t own_addr1
Definition: ald_i2c.h:258
I2C_STAT_DIR
Definition: ald_i2c.h:218
I2C_IT_TCR
Definition: ald_i2c.h:234
i2c_addr1_t
i2c_addr1_t
I2C ADDR1 Register.
Definition: ald_i2c.h:173
I2C_ADDR_7BIT
Definition: ald_i2c.h:75
I2C_IT_RXTH
Definition: ald_i2c.h:232
I2C_IT_PECE
Definition: ald_i2c.h:240
i2c_error_t
i2c_error_t
I2C Error Code.
Definition: ald_i2c.h:43
ald_i2c_master_send_by_it
ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint32_t size)
Transmit in master mode an amount of data in non-blocking mode with Interrupt.
Definition: ald_i2c.c:806
i2c_handle_s::error_code
__IO uint32_t error_code
Definition: ald_i2c.h:282
i2c_handle_s::perh
I2C_TypeDef * perh
Definition: ald_i2c.h:270
i2c_handle_s::hdmarx
dma_handle_t hdmarx
Definition: ald_i2c.h:277
I2C_STATE_READY
Definition: ald_i2c.h:63
I2C_CON2_HEAD10R
Definition: ald_i2c.h:160
ald_i2c_mem_write
ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size, uint8_t *buf, uint32_t size, uint32_t timeout)
Write an amount of data in blocking mode to a specific memory address.
Definition: ald_i2c.c:1272
I2C_IT_RXOV
Definition: ald_i2c.h:230
i2c_general_addr_t
i2c_general_addr_t
I2C General Call Addressing mode.
Definition: ald_i2c.h:90


ALD User Manual: D:/svn/src/ald_i2s.c Source File

  • D:
  • svn
  • src
ald_i2s.c
Go to the documentation of this file.
1
56 #include "ald_i2s.h"
57 #include "ald_cmu.h"
58
59
68 #ifdef ALD_I2S
69
74 static ald_status_t i2s_wait_status(i2s_handle_t *hperh, i2s_status_t state, flag_status_t status, uint32_t timeout);
75 static void __i2s_send_by_it(i2s_handle_t *hperh);
76 static void __i2s_recv_by_it(i2s_handle_t *hperh);
77 static void __i2s_tx_recv_by_it(i2s_handle_t *hperh);
78 #ifdef ALD_DMA
79 static void i2s_dma_send_cplt(void *arg);
80 static void i2s_dma_recv_cplt(void *arg);
81 static void i2s_dma_error(void *arg);
82 #endif
83
128 void ald_i2s_reset(i2s_handle_t *hperh)
129 {
130 hperh->perh->I2SCFG = 0x0;
131 hperh->perh->I2SPR = 0x0;
132
133 I2S_RESET_HANDLE_STATE(hperh);
134 __UNLOCK(hperh);
135
136 return;
137 }
138
146 ald_status_t ald_i2s_init(i2s_handle_t *hperh)
147 {
148 uint32_t tmp = 0, clk, _div;
149
150 if (hperh == NULL)
151 return ERROR;
152
153 assert_param(IS_I2S(hperh->perh));
154 assert_param(IS_I2S_CH_LEN(hperh->init.ch_len));
155 assert_param(IS_I2S_DATE_LEN(hperh->init.data_len));
156 assert_param(IS_I2S_CPOL(hperh->init.polarity));
157 assert_param(IS_I2S_STANDARD(hperh->init.standard));
158 assert_param(IS_FUNC_STATE(hperh->init.ext_clk_en));
159 assert_param(IS_FUNC_STATE(hperh->init.mck_en));
160 assert_param(IS_I2S_PCMS(hperh->init.pcm_frame));
161
162 ald_i2s_reset(hperh);
163
164 tmp |= (hperh->init.ext_clk_en << SPI_I2SPR_EXTCKEN_POS);
165
166 /* Get I2S clock */
167 if (hperh->init.ext_clk_en)
168 clk = hperh->init.ext_clk;
169 else
170 clk = ald_cmu_get_pclk1_clock();
171
172 if (hperh->init.mck_en) {
173 _div = ((clk / hperh->init.sampling) >> 8);
174 }
175 else {
176 if (hperh->init.ch_len == I2S_WIDE_16)
177 _div = ((clk / hperh->init.sampling) >> 5);
178 else
179 _div = ((clk / hperh->init.sampling) >> 6);
180 }
181
182 if (_div & 0x1) {
183 SET_BIT(tmp, SPI_I2SPR_ODD_MSK);
184 --_div;
185 }
186 else {
187 CLEAR_BIT(tmp, SPI_I2SPR_ODD_MSK);
188 }
189
190 if (hperh->init.standard != I2S_STD_PCM)
191 MODIFY_REG(tmp, SPI_I2SPR_I2SDIV_MSK, (_div >> 1) << SPI_I2SPR_I2SDIV_POSS);
192 else
193 MODIFY_REG(tmp, SPI_I2SPR_I2SDIV_MSK, _div << SPI_I2SPR_I2SDIV_POSS);
194
195 hperh->perh->I2SPR = tmp;
196
197 tmp = hperh->perh->I2SCFG;
198 tmp |= ((hperh->init.ch_len << SPI_I2SCFG_CHLEN_POS) | (hperh->init.data_len << SPI_I2SCFG_DATLEN_POSS) |
199 (hperh->init.polarity << SPI_I2SCFG_CKPOL_POS) | (hperh->init.standard << SPI_I2SCFG_I2SSTD_POSS) |
200 (1 << SPI_I2SCFG_I2SMOD_POS));
201 hperh->perh->I2SCFG = tmp;
202
203 if (hperh->init.standard == I2S_STD_PCM)
204 hperh->perh->I2SCFG |= (hperh->init.pcm_frame << SPI_I2SCFG_PCMSYNC_POS);
205
206 hperh->err_code = I2S_ERROR_NONE;
207 hperh->state = I2S_STATE_READY;
208
209 return OK;
210 }
254 ald_status_t ald_i2s_master_send(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout)
255 {
256 assert_param(IS_I2S(hperh->perh));
257
258 if (hperh->state != I2S_STATE_READY)
259 return BUSY;
260 if (buf == NULL || size == 0)
261 return ERROR;
262
263 hperh->state = I2S_STATE_BUSY_TX;
264 hperh->err_code = I2S_ERROR_NONE;
265
266 MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS);
267
268 if (hperh->init.mck_en)
269 MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS);
270 if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0)
271 I2S_ENABLE(hperh);
272
273 while (size > 0) {
274 if (i2s_wait_status(hperh, I2S_STATUS_TXE, SET, timeout) != OK) {
275 I2S_DISABLE(hperh);
276
277 hperh->state = I2S_STATE_READY;
278 return TIMEOUT;
279 }
280
281 hperh->side = READ_BITS(hperh->perh->STAT, SPI_STAT_CHSIDE_MSK, SPI_STAT_CHSIDE_POS);
282 hperh->perh->DATA = *buf++;
283 --size;
284 }
285
286 if ((i2s_wait_status(hperh, I2S_STATUS_TXE, SET, timeout) != OK)
287 || (i2s_wait_status(hperh, I2S_STATUS_BUSY, RESET, timeout) != OK)) {
288 I2S_DISABLE(hperh);
289 hperh->state = I2S_STATE_READY;
290 return TIMEOUT;
291 }
292
293 I2S_DISABLE(hperh);
294 hperh->state = I2S_STATE_READY;
295
296 return OK;
297 }
298
307 ald_status_t ald_i2s_master_recv(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout)
308 {
309 assert_param(IS_I2S(hperh->perh));
310
311 if (hperh->state != I2S_STATE_READY)
312 return BUSY;
313 if (buf == NULL || size == 0)
314 return ERROR;
315
316 hperh->state = I2S_STATE_BUSY_RX;
317 hperh->err_code = I2S_ERROR_NONE;
318
319 MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_RECEIVE << SPI_I2SCFG_I2SCFG_POSS);
320
321 if (hperh->init.mck_en)
322 MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS);
323 if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0)
324 I2S_ENABLE(hperh);
325
326 while (size > 0) {
327 hperh->perh->DATA = 0xffff;
328 if (i2s_wait_status(hperh, I2S_STATUS_RXE, RESET, timeout) != OK) {
329 I2S_DISABLE(hperh);
330 hperh->state = I2S_STATE_READY;
331 return TIMEOUT;
332 }
333
334 *buf++ = hperh->perh->DATA;
335 --size;
336 }
337
338 hperh->state = I2S_STATE_READY;
339 return OK;
340 }
341
349 ald_status_t ald_i2s_master_send_by_it(i2s_handle_t *hperh, uint16_t *buf, uint32_t size)
350 {
351 assert_param(IS_I2S(hperh->perh));
352
353 if (hperh->state != I2S_STATE_READY)
354 return BUSY;
355 if (buf == NULL || size == 0)
356 return ERROR;
357
358 hperh->state = I2S_STATE_BUSY_TX;
359 hperh->err_code = I2S_ERROR_NONE;
360 hperh->tx_buf = buf;
361 hperh->tx_size = size;
362 hperh->tx_count = size;
363 hperh->rx_buf = NULL;
364 hperh->rx_size = 0;
365 hperh->rx_count = 0;
366
367 WRITE_REG(hperh->perh->ICR, 0xffffffff);
368
369 I2S_DISABLE(hperh);
370 MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS);
371
372 if (hperh->init.mck_en)
373 MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS);
374 if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0)
375 I2S_ENABLE(hperh);
376
377 ald_i2s_interrupt_config(hperh, I2S_IT_TXE, ENABLE);
378 return OK;
379 }
380
388 ald_status_t ald_i2s_master_recv_by_it(i2s_handle_t *hperh, uint16_t *buf, uint32_t size)
389 {
390 assert_param(IS_I2S(hperh->perh));
391
392 if (hperh->state != I2S_STATE_READY)
393 return BUSY;
394 if (buf == NULL || size == 0)
395 return ERROR;
396
397 hperh->state = I2S_STATE_BUSY_TX_RX;
398 hperh->err_code = I2S_ERROR_NONE;
399 hperh->rx_buf = buf;
400 hperh->rx_size = size;
401 hperh->rx_count = size;
402 hperh->tx_buf = 0;
403 hperh->tx_size = size;
404 hperh->tx_count = size;
405
406 WRITE_REG(hperh->perh->ICR, 0xffffffff);
407
408 I2S_DISABLE(hperh);
409 MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_RECEIVE << SPI_I2SCFG_I2SCFG_POSS);
410
411 if (hperh->init.mck_en)
412 MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS);
413
414 if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0)
415 I2S_ENABLE(hperh);
416
417 ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, ENABLE);
418 ald_i2s_interrupt_config(hperh, I2S_IT_TXE, ENABLE);
419
420 return OK;
421 }
422
423 #ifdef ALD_DMA
424
432 ald_status_t ald_i2s_master_send_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t channel)
433 {
434 assert_param(IS_I2S(hperh->perh));
435
436 if (hperh->state != I2S_STATE_READY)
437 return BUSY;
438 if (buf == NULL || size == 0)
439 return ERROR;
440
441 hperh->state = I2S_STATE_BUSY_TX;
442 hperh->err_code = I2S_ERROR_NONE;
443 hperh->tx_buf = buf;
444 hperh->tx_size = size;
445 hperh->tx_count = size;
446 hperh->rx_buf = NULL;
447 hperh->rx_size = 0;
448 hperh->rx_count = 0;
449
450 WRITE_REG(hperh->perh->ICR, 0xffffffff);
451
452 I2S_DISABLE(hperh);
453
454 MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_TRANSMIT << SPI_I2SCFG_I2SCFG_POSS);
455
456 if (hperh->init.mck_en)
457 MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS);
458
459 hperh->hdmatx.cplt_arg = (void *)hperh;
460 hperh->hdmatx.cplt_cbk = i2s_dma_send_cplt;
461 hperh->hdmatx.err_arg = (void *)hperh;
462 hperh->hdmatx.err_cbk = i2s_dma_error;
463
464 /* Configure I2S DMA transmit */
465 ald_dma_config_struct(&(hperh->hdmatx.config));
466 hperh->hdmatx.perh = DMA0;
467 hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD;
468 hperh->hdmatx.config.src = (void *)buf;
469 hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA;
470 hperh->hdmatx.config.size = size;
471 hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD;
472 hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
473 hperh->hdmatx.config.msel = hperh->perh == I2S0 ? DMA_MSEL_SPI0 : (hperh->perh == I2S1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2);
474 hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY;
475 hperh->hdmatx.config.channel = channel;
476 hperh->hdmatx.config.burst = ENABLE;
477 ald_dma_config_basic(&(hperh->hdmatx));
478 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, ENABLE);
479
480 if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0)
481 I2S_ENABLE(hperh);
482
483 return OK;
484 }
485
495 ald_status_t ald_i2s_master_recv_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t dma_ch, uint8_t _dma_ch)
496 {
497 assert_param(IS_I2S(hperh->perh));
498
499 if (hperh->state != I2S_STATE_READY)
500 return BUSY;
501 if (buf == NULL || size == 0)
502 return ERROR;
503
504 hperh->state = I2S_STATE_BUSY_RX;
505 hperh->err_code = I2S_ERROR_NONE;
506 hperh->rx_buf = buf;
507 hperh->rx_size = size;
508 hperh->rx_count = size;
509 hperh->tx_buf = NULL;
510 hperh->tx_size = 0;
511 hperh->tx_count = 0;
512 buf[size - 1] = 0xFFFF;
513
514 WRITE_REG(hperh->perh->ICR, 0xffffffff);
515
516 I2S_DISABLE(hperh);
517
518 MODIFY_REG(hperh->perh->I2SCFG, SPI_I2SCFG_I2SCFG_MSK, I2S_MASTER_RECEIVE << SPI_I2SCFG_I2SCFG_POSS);
519
520 if (hperh->init.mck_en)
521 MODIFY_REG(hperh->perh->I2SPR, SPI_I2SPR_MCKOE_MSK, hperh->init.mck_en << SPI_I2SPR_MCKOE_POS);
522
523 hperh->hdmatx.cplt_arg = (void *)hperh;
524 hperh->hdmatx.cplt_cbk = i2s_dma_send_cplt;
525 hperh->hdmatx.err_arg = (void *)hperh;
526 hperh->hdmatx.err_cbk = i2s_dma_error;
527
528 ald_dma_config_struct(&(hperh->hdmatx.config));
529 hperh->hdmatx.perh = DMA0;
530 hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD;
531 hperh->hdmatx.config.src = (void *)&buf[size - 1];
532 hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA;
533 hperh->hdmatx.config.size = size;
534 hperh->hdmatx.config.src_inc = DMA_DATA_INC_NONE;
535 hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
536 hperh->hdmatx.config.msel = hperh->perh == I2S0 ? DMA_MSEL_SPI0 : (hperh->perh == I2S1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2);
537 hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY;
538 hperh->hdmatx.config.burst = ENABLE;
539 hperh->hdmatx.config.channel = _dma_ch;
540 ald_dma_config_basic(&(hperh->hdmatx));
541 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, ENABLE);
542
543 hperh->hdmarx.cplt_arg = (void *)hperh;
544 hperh->hdmarx.cplt_cbk = i2s_dma_recv_cplt;
545 hperh->hdmarx.err_arg = (void *)hperh;
546 hperh->hdmarx.err_cbk = i2s_dma_error;
547
548 /* Configure DMA Receive */
549 ald_dma_config_struct(&(hperh->hdmarx.config));
550 hperh->hdmarx.perh = DMA0;
551 hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD;
552 hperh->hdmarx.config.src = (void *)&hperh->perh->DATA;
553 hperh->hdmarx.config.dst = (void *)buf;
554 hperh->hdmarx.config.size = size;
555 hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE;
556 hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD;
557 hperh->hdmarx.config.msel = hperh->perh == I2S0 ? DMA_MSEL_SPI0 : (hperh->perh == I2S1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2);
558 hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR;
559 hperh->hdmarx.config.channel = dma_ch;
560 hperh->hdmarx.config.burst = ENABLE;
561 ald_dma_config_basic(&(hperh->hdmarx));
562 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, ENABLE);
563
564 if (READ_BIT(hperh->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK) == 0)
565 I2S_ENABLE(hperh);
566
567 return OK;
568 }
569
575 ald_status_t ald_i2s_dma_pause(i2s_handle_t *hperh)
576 {
577 assert_param(IS_I2S(hperh->perh));
578
579 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, DISABLE);
580 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, DISABLE);
581
582 return OK;
583 }
584
590 ald_status_t ald_i2s_dma_resume(i2s_handle_t *hperh)
591 {
592 assert_param(IS_I2S(hperh->perh));
593
594 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, ENABLE);
595 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, ENABLE);
596
597 return OK;
598 }
599
605 ald_status_t ald_i2s_dma_stop(i2s_handle_t *hperh)
606 {
607 assert_param(IS_I2S(hperh->perh));
608
609 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, DISABLE);
610 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, DISABLE);
611
612 hperh->state = I2S_STATE_READY;
613 return OK;
614 }
615 #endif
616
646 void ald_i2s_irq_handler(i2s_handle_t *hperh)
647 {
648 if (ald_i2s_get_mask_flag_status(hperh, I2S_IF_RXTH) == SET) {
649 ald_i2s_clear_flag_status(hperh, I2S_IF_RXTH);
650 if ((hperh->state == I2S_STATE_BUSY_TX_RX) || (hperh->state == I2S_STATE_BUSY_RX))
651 __i2s_recv_by_it(hperh);
652 }
653
654 if (ald_i2s_get_mask_flag_status(hperh, I2S_IF_TXE) == SET) {
655 ald_i2s_clear_flag_status(hperh, I2S_IF_TXE);
656 if (hperh->state == I2S_STATE_BUSY_TX)
657 __i2s_send_by_it(hperh);
658 else if (hperh->state == I2S_STATE_BUSY_TX_RX)
659 __i2s_tx_recv_by_it(hperh);
660
661 }
662
663 if (hperh->err_code != I2S_ERROR_NONE) {
664 ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, DISABLE);
665 ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE);
666 hperh->state = I2S_STATE_READY;
667
668 if (hperh->err_cbk)
669 hperh->err_cbk(hperh);
670 }
671
672 return;
673 }
674
685 void ald_i2s_interrupt_config(i2s_handle_t *hperh, i2s_it_t it, type_func_t state)
686 {
687 assert_param(IS_I2S(hperh->perh));
688 assert_param(IS_I2S_IT(it));
689 assert_param(IS_FUNC_STATE(state));
690
691 if (state == ENABLE)
692 hperh->perh->IER = (uint32_t)it;
693 else
694 hperh->perh->IDR = (uint32_t)it;
695
696 return;
697 }
698
709 void ald_i2s_dma_req_config(i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t state)
710 {
711 assert_param(IS_I2S(hperh->perh));
712 assert_param(IS_I2S_DMA_REQ(req));
713 assert_param(IS_FUNC_STATE(state));
714
715 if (state == ENABLE) {
716 if (req == I2S_DMA_REQ_TX)
717 SET_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK);
718 else
719 SET_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK);
720 }
721 else {
722 if (req == I2S_DMA_REQ_TX)
723 CLEAR_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK);
724 else
725 CLEAR_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK);
726 }
727
728 return;
729 }
730
739 flag_status_t ald_i2s_get_status(i2s_handle_t *hperh, i2s_status_t status)
740 {
741 assert_param(IS_I2S(hperh->perh));
742 assert_param(IS_I2S_STATUS(status));
743
744 if (hperh->perh->STAT & status)
745 return SET;
746
747 return RESET;
748 }
749
759 it_status_t ald_i2s_get_it_status(i2s_handle_t *hperh, i2s_it_t it)
760 {
761 assert_param(IS_I2S(hperh->perh));
762 assert_param(IS_I2S_IT(it));
763
764 if (hperh->perh->IVS & it)
765 return SET;
766
767 return RESET;
768 }
769
778 flag_status_t ald_i2s_get_flag_status(i2s_handle_t *hperh, i2s_flag_t flag)
779 {
780 assert_param(IS_I2S(hperh->perh));
781 assert_param(IS_I2S_IF(flag));
782
783 if (hperh->perh->RIF & flag)
784 return SET;
785
786 return RESET;
787 }
788
797 flag_status_t ald_i2s_get_mask_flag_status(i2s_handle_t *hperh, i2s_flag_t flag)
798 {
799 assert_param(IS_I2S(hperh->perh));
800 assert_param(IS_I2S_IF(flag));
801
802 if (hperh->perh->IFM & flag)
803 return SET;
804
805 return RESET;
806 }
807
814 void ald_i2s_clear_flag_status(i2s_handle_t *hperh, i2s_flag_t flag)
815 {
816 assert_param(IS_I2S(hperh->perh));
817 assert_param(IS_I2S_IF(flag));
818
819 hperh->perh->ICR = flag;
820 return;
821 }
847 i2s_state_t ald_i2s_get_state(i2s_handle_t *hperh)
848 {
849 assert_param(IS_I2S(hperh->perh));
850 return hperh->state;
851 }
852
858 uint32_t ald_i2s_get_error(i2s_handle_t *hperh)
859 {
860 assert_param(IS_I2S(hperh->perh));
861 return hperh->err_code;
862 }
882 static ald_status_t i2s_wait_status(i2s_handle_t *hperh, i2s_status_t flag, flag_status_t status, uint32_t timeout)
883 {
884 uint32_t tick = ald_get_tick();
885
886 assert_param(timeout > 0);
887
888 while ((ald_i2s_get_status(hperh, flag)) != status) {
889 if (((ald_get_tick()) - tick) > timeout) {
890 ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE);
891 ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, DISABLE);
892 return TIMEOUT;
893 }
894 }
895
896 return OK;
897 }
898
904 static void __i2s_send_by_it(i2s_handle_t *hperh)
905 {
906 int cnt = 8000;
907
908 if (hperh->tx_count == 0) {
909 ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE);
910 hperh->state = I2S_STATE_READY;
911
912 while ((hperh->perh->STAT & SPI_STAT_BUSY_MSK) && (--cnt));
913 if (cnt == 0) {
914 if (hperh->err_cbk)
915 hperh->err_cbk(hperh);
916
917 ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, DISABLE);
918 return;
919 }
920
921 if (hperh->tx_cplt_cbk)
922 hperh->tx_cplt_cbk(hperh);
923
924 return;
925 }
926
927 hperh->side = READ_BITS(hperh->perh->STAT, SPI_STAT_CHSIDE_MSK, SPI_STAT_CHSIDE_POS);
928 hperh->perh->DATA = *hperh->tx_buf++;
929 --hperh->tx_count;
930
931 return;
932 }
933
939 static void __i2s_recv_by_it(i2s_handle_t *hperh)
940 {
941 *(hperh->rx_buf++) = hperh->perh->DATA;
942 --hperh->rx_count;
943
944 if (hperh->rx_count == 0) {
945 ald_i2s_interrupt_config(hperh, I2S_IT_RXTH, DISABLE);
946 hperh->state = I2S_STATE_READY;
947
948 if (hperh->rx_cplt_cbk)
949 hperh->rx_cplt_cbk(hperh);
950 }
951
952 return;
953 }
954
960 static void __i2s_tx_recv_by_it(i2s_handle_t *hperh)
961 {
962 if (hperh->tx_count != 0) {
963 ald_i2s_clear_flag_status(hperh, I2S_IF_TXE);
964 hperh->perh->DATA = 0xffff;
965 // while(ald_i2s_get_status(hperh, I2S_STATUS_RXE) == SET);
966 --hperh->tx_count;
967 if (hperh->tx_count == 0)
968 ald_i2s_interrupt_config(hperh, I2S_IT_TXE, DISABLE);
969 }
970 }
971
972 #ifdef ALD_DMA
973
978 static void i2s_dma_send_cplt(void *arg)
979 {
980 int cnt = 8000;
981 i2s_handle_t *hperh = (i2s_handle_t *)arg;
982
983 hperh->tx_count = 0;
984 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, DISABLE);
985 hperh->state = I2S_STATE_READY;
986
987 while ((hperh->perh->STAT & SPI_STAT_BUSY_MSK) && (--cnt));
988 if (cnt == 0)
989 hperh->err_code |= I2S_ERROR_FLAG;
990
991 if (hperh->err_code == I2S_ERROR_NONE) {
992 if (hperh->tx_cplt_cbk)
993 hperh->tx_cplt_cbk(hperh);
994 }
995 else {
996 if (hperh->err_cbk)
997 hperh->err_cbk(hperh);
998 }
999
1000 return;
1001 }
1002
1008 static void i2s_dma_recv_cplt(void *arg)
1009 {
1010 i2s_handle_t *hperh = (i2s_handle_t *)arg;
1011
1012 hperh->rx_count = 0;
1013 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, DISABLE);
1014 hperh->state = I2S_STATE_READY;
1015
1016 if (hperh->err_code == I2S_ERROR_NONE) {
1017 if (hperh->rx_cplt_cbk)
1018 hperh->rx_cplt_cbk(hperh);
1019 }
1020 else {
1021 if (hperh->err_cbk)
1022 hperh->err_cbk(hperh);
1023 }
1024
1025 return;
1026 }
1027
1033 static void i2s_dma_error(void *arg)
1034 {
1035 i2s_handle_t *hperh = (i2s_handle_t *)arg;
1036
1037 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_TX, DISABLE);
1038 ald_i2s_dma_req_config(hperh, I2S_DMA_REQ_RX, DISABLE);
1039 SET_BIT(hperh->err_code, I2S_ERROR_DMA);
1040
1041 hperh->tx_count = 0;
1042 hperh->rx_count = 0;
1043 hperh->state = I2S_STATE_READY;
1044
1045 if (hperh->err_cbk)
1046 hperh->err_cbk(hperh);
1047
1048 return;
1049 }
1050
1051 #endif
1052
1055 #endif
1056
I2S_MASTER_TRANSMIT
Definition: ald_i2s.h:78
DMA_MSEL_SPI1
Definition: ald_dma.h:91
i2s_init_t::data_len
i2s_datalen_t data_len
Definition: ald_i2s.h:193
I2S_RESET_HANDLE_STATE
#define I2S_RESET_HANDLE_STATE(x)
Definition: ald_i2s.h:235
I2S_ENABLE
#define I2S_ENABLE(x)
Definition: ald_i2s.h:236
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
__i2s_send_by_it
static void __i2s_send_by_it(i2s_handle_t *hperh)
handle program when an tx empty interrupt flag arrived in non block mode
Definition: ald_i2s.c:904
i2s_dma_error
static void i2s_dma_error(void *arg)
DMA I2S communication error callback.
Definition: ald_i2s.c:1033
i2s_handle_s::side
uint8_t side
Definition: ald_i2s.h:221
ald_i2s_dma_pause
ald_status_t ald_i2s_dma_pause(i2s_handle_t *hperh)
Pauses the DMA Transfer.
Definition: ald_i2s.c:575
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
ald_i2s_init
ald_status_t ald_i2s_init(i2s_handle_t *hperh)
Initializes the I2S mode according to the specified parameters in the i2s_init_t and create the assoc...
Definition: ald_i2s.c:146
BUSY
Definition: utils.h:57
i2s_init_t::ext_clk_en
type_func_t ext_clk_en
Definition: ald_i2s.h:197
ald_i2s.h
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
ald_i2s_dma_req_config
void ald_i2s_dma_req_config(i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t state)
Enables or disables the dma request.
Definition: ald_i2s.c:709
SET
Definition: type.h:39
IS_I2S_IT
#define IS_I2S_IT(x)
Definition: ald_i2s.h:261
ald_i2s_master_recv_by_it
ald_status_t ald_i2s_master_recv_by_it(i2s_handle_t *hperh, uint16_t *buf, uint32_t size)
Master mode receives an amount of data in non blocking mode.
Definition: ald_i2s.c:388
ald_i2s_get_flag_status
flag_status_t ald_i2s_get_flag_status(i2s_handle_t *hperh, i2s_flag_t flag)
Check whether the specified I2S interrupt flag is set or not.
Definition: ald_i2s.c:778
type_func_t
type_func_t
Definition: type.h:47
IS_I2S_IF
#define IS_I2S_IF(x)
Definition: ald_i2s.h:271
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
DMA_MSEL_SPI2
Definition: ald_dma.h:99
I2S_IT_RXTH
Definition: ald_i2s.h:113
DISABLE
Definition: type.h:48
ald_i2s_get_error
uint32_t ald_i2s_get_error(i2s_handle_t *hperh)
Return the I2S error code.
Definition: ald_i2s.c:858
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
I2S_IT_TXE
Definition: ald_i2s.h:107
i2s_init_t::sampling
uint32_t sampling
Definition: ald_i2s.h:200
i2s_it_t
i2s_it_t
interrupt control
Definition: ald_i2s.h:106
I2S_STATUS_BUSY
Definition: ald_i2s.h:168
dma_config_t::src
void * src
Definition: ald_dma.h:278
I2S_MASTER_RECEIVE
Definition: ald_i2s.h:79
__i2s_tx_recv_by_it
static void __i2s_tx_recv_by_it(i2s_handle_t *hperh)
handle program when an rx no empty interrupt flag arrived in non block mode
Definition: ald_i2s.c:960
i2s_handle_s::rx_buf
uint16_t * rx_buf
Definition: ald_i2s.h:212
i2s_dma_recv_cplt
static void i2s_dma_recv_cplt(void *arg)
DMA I2S receive process complete callback.
Definition: ald_i2s.c:1008
I2S_STD_PCM
Definition: ald_i2s.h:71
IS_I2S
#define IS_I2S(x)
Definition: ald_i2s.h:245
IS_I2S_CPOL
#define IS_I2S_CPOL(x)
Definition: ald_i2s.h:253
i2s_handle_s::hdmarx
dma_handle_t hdmarx
Definition: ald_i2s.h:217
I2S_STATE_BUSY_TX_RX
Definition: ald_i2s.h:150
i2s_init_t::ext_clk
uint32_t ext_clk
Definition: ald_i2s.h:198
IS_I2S_STANDARD
#define IS_I2S_STANDARD(x)
Definition: ald_i2s.h:255
ald_i2s_master_send_by_it
ald_status_t ald_i2s_master_send_by_it(i2s_handle_t *hperh, uint16_t *buf, uint32_t size)
Wraps up master mode transmission in non blocking mode.
Definition: ald_i2s.c:349
I2S_STATUS_TXE
Definition: ald_i2s.h:159
ald_i2s_dma_resume
ald_status_t ald_i2s_dma_resume(i2s_handle_t *hperh)
Resumes the DMA Transfer.
Definition: ald_i2s.c:590
i2s_handle_s::rx_cplt_cbk
void(* rx_cplt_cbk)(struct i2s_handle_s *arg)
Definition: ald_i2s.h:225
RESET
Definition: type.h:38
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
i2s_handle_s::state
i2s_state_t state
Definition: ald_i2s.h:220
ald_i2s_get_state
i2s_state_t ald_i2s_get_state(i2s_handle_t *hperh)
Returns the I2S state.
Definition: ald_i2s.c:847
i2s_handle_s::err_cbk
void(* err_cbk)(struct i2s_handle_s *arg)
Definition: ald_i2s.h:226
i2s_wait_status
static ald_status_t i2s_wait_status(i2s_handle_t *hperh, i2s_status_t state, flag_status_t status, uint32_t timeout)
This function wait I2S status until timeout.
Definition: ald_i2s.c:882
I2S_IF_RXTH
Definition: ald_i2s.h:137
i2s_init_t::ch_len
i2s_chlen_t ch_len
Definition: ald_i2s.h:192
it_status_t
enum flag_status_t it_status_t
ald_i2s_irq_handler
void ald_i2s_irq_handler(i2s_handle_t *hperh)
This function handles I2S interrupt request.
Definition: ald_i2s.c:646
i2s_handle_s::err_code
uint32_t err_code
Definition: ald_i2s.h:222
ald_i2s_interrupt_config
void ald_i2s_interrupt_config(i2s_handle_t *hperh, i2s_it_t it, type_func_t state)
Enables or disables the specified I2S interrupts.
Definition: ald_i2s.c:685
i2s_handle_s::tx_size
uint32_t tx_size
Definition: ald_i2s.h:210
__i2s_recv_by_it
static void __i2s_recv_by_it(i2s_handle_t *hperh)
handle program when an rx no empty interrupt flag arrived in non block mode
Definition: ald_i2s.c:939
IS_I2S_DATE_LEN
#define IS_I2S_DATE_LEN(x)
Definition: ald_i2s.h:250
IS_I2S_DMA_REQ
#define IS_I2S_DMA_REQ(x)
Definition: ald_i2s.h:299
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
ald_i2s_master_recv
ald_status_t ald_i2s_master_recv(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout)
Master mode receive an amount of data in blocking mode.
Definition: ald_i2s.c:307
ald_i2s_dma_stop
ald_status_t ald_i2s_dma_stop(i2s_handle_t *hperh)
Stops the DMA Transfer.
Definition: ald_i2s.c:605
i2s_init_t::standard
i2s_standard_t standard
Definition: ald_i2s.h:195
i2s_init_t::mck_en
type_func_t mck_en
Definition: ald_i2s.h:199
I2S_STATE_BUSY_TX
Definition: ald_i2s.h:148
i2s_state_t
i2s_state_t
I2S state structures definition.
Definition: ald_i2s.h:144
I2S_ERROR_DMA
Definition: ald_i2s.h:96
ald_cmu.h
Header file of CMU module driver.
IS_I2S_PCMS
#define IS_I2S_PCMS(x)
Definition: ald_i2s.h:259
IS_I2S_STATUS
#define IS_I2S_STATUS(x)
Definition: ald_i2s.h:289
i2s_handle_s::tx_cplt_cbk
void(* tx_cplt_cbk)(struct i2s_handle_s *arg)
Definition: ald_i2s.h:224
I2S_STATE_BUSY_RX
Definition: ald_i2s.h:149
I2S_ERROR_NONE
Definition: ald_i2s.h:94
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
I2S_IF_TXE
Definition: ald_i2s.h:131
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
DMA_MSIGSEL_SPI_RNR
Definition: ald_dma.h:141
I2S_ERROR_FLAG
Definition: ald_i2s.h:100
I2S_DMA_REQ_TX
Definition: ald_i2s.h:123
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
ald_i2s_get_it_status
it_status_t ald_i2s_get_it_status(i2s_handle_t *hperh, i2s_it_t it)
Checks whether the specified I2S interrupt has occurred or not.
Definition: ald_i2s.c:759
I2S_STATUS_RXE
Definition: ald_i2s.h:163
i2s_handle_s::tx_buf
uint16_t * tx_buf
Definition: ald_i2s.h:209
ald_cmu_get_pclk1_clock
uint32_t ald_cmu_get_pclk1_clock(void)
Get APB1 clock.
Definition: ald_cmu.c:627
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
ald_i2s_get_status
flag_status_t ald_i2s_get_status(i2s_handle_t *hperh, i2s_status_t status)
Check whether the specified I2S flag is set or not.
Definition: ald_i2s.c:739
i2s_handle_s::rx_count
uint32_t rx_count
Definition: ald_i2s.h:214
ald_i2s_clear_flag_status
void ald_i2s_clear_flag_status(i2s_handle_t *hperh, i2s_flag_t flag)
Clear the specified I2S interrupt flags.
Definition: ald_i2s.c:814
ald_i2s_master_recv_by_dma
ald_status_t ald_i2s_master_recv_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t dma_ch, uint8_t _dma_ch)
Master mode receive an amount of data used dma channel.
Definition: ald_i2s.c:495
I2S_WIDE_16
Definition: ald_i2s.h:43
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
i2s_init_t::polarity
i2s_cpol_t polarity
Definition: ald_i2s.h:194
ald_i2s_get_mask_flag_status
flag_status_t ald_i2s_get_mask_flag_status(i2s_handle_t *hperh, i2s_flag_t flag)
Check whether the specified I2S interrupt flag is set or not.
Definition: ald_i2s.c:797
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
i2s_handle_s::hdmatx
dma_handle_t hdmatx
Definition: ald_i2s.h:216
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
i2s_status_t
i2s_status_t
I2S status definition.
Definition: ald_i2s.h:158
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
I2S_STATE_READY
Definition: ald_i2s.h:146
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
flag_status_t
flag_status_t
Definition: type.h:37
ald_i2s_master_send
ald_status_t ald_i2s_master_send(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout)
Master mode transmit an amount of data in blocking mode.
Definition: ald_i2s.c:254
DMA_MSIGSEL_SPI_TXEMPTY
Definition: ald_dma.h:142
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
i2s_handle_s
I2S handle structure definition.
Definition: ald_i2s.h:206
IS_I2S_CH_LEN
#define IS_I2S_CH_LEN(x)
Definition: ald_i2s.h:248
i2s_flag_t
i2s_flag_t
interrupt flag
Definition: ald_i2s.h:130
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
I2S_DMA_REQ_RX
Definition: ald_i2s.h:124
i2s_dma_req_t
i2s_dma_req_t
I2S dma request definition.
Definition: ald_i2s.h:122
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
ald_i2s_reset
void ald_i2s_reset(i2s_handle_t *hperh)
Reset the I2S peripheral.
Definition: ald_i2s.c:128
DMA_MSEL_SPI0
Definition: ald_dma.h:90
i2s_handle_s::tx_count
uint32_t tx_count
Definition: ald_i2s.h:211
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
ERROR
Definition: utils.h:56
i2s_handle_s::init
i2s_init_t init
Definition: ald_i2s.h:208
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
ald_i2s_master_send_by_dma
ald_status_t ald_i2s_master_send_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t channel)
Master mode transmit an amount of data used dma channel.
Definition: ald_i2s.c:432
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
i2s_dma_send_cplt
static void i2s_dma_send_cplt(void *arg)
DMA I2S transmit process complete callback.
Definition: ald_i2s.c:978
I2S_DISABLE
#define I2S_DISABLE(x)
Definition: ald_i2s.h:237
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207
i2s_init_t::pcm_frame
i2s_pcms_t pcm_frame
Definition: ald_i2s.h:196
i2s_handle_s::rx_size
uint32_t rx_size
Definition: ald_i2s.h:213


ALD User Manual: D:/svn/src/ald_i2s.h Source File

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  • svn
  • src
ald_i2s.h
Go to the documentation of this file.
1
17 #ifndef __ALD_I2S_H__
18 #define __ALD_I2S_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25 #include "ald_dma.h"
26
42 typedef enum {
43 I2S_WIDE_16 = 0x0U,
44 I2S_WIDE_32 = 0x1U,
45 } i2s_chlen_t;
46
50 typedef enum {
51 I2S_LEN_16 = 0x0U,
52 I2S_LEN_24 = 0x1U,
53 I2S_LEN_32 = 0x2U,
54 } i2s_datalen_t;
55
59 typedef enum {
60 I2S_INACTIVE_LOW = 0x0U,
61 I2S_INACTIVE_HIGH = 0x1U,
62 } i2s_cpol_t;
63
67 typedef enum {
68 I2S_STD_PHI = 0x0U,
69 I2S_STD_MSB = 0x1U,
70 I2S_STD_LSB = 0x2U,
71 I2S_STD_PCM = 0x3U,
72 } i2s_standard_t;
73
77 typedef enum {
78 I2S_MASTER_TRANSMIT = 0x2U,
79 I2S_MASTER_RECEIVE = 0x3U,
80 } i2s_cfg_t;
81
85 typedef enum {
86 I2S_FRAME_SHORT = 0x0U,
87 I2S_FRAME_LONG = 0x1U,
88 } i2s_pcms_t;
89
93 typedef enum {
94 I2S_ERROR_NONE = 0x0U,
95 I2S_ERROR_MODF = 0x1U,
96 I2S_ERROR_DMA = 0x2U,
97 I2S_ERROR_FRE = 0x4U,
98 I2S_ERROR_RXOV = 0x8U,
99 I2S_ERROR_TXOV = 0x10U,
100 I2S_ERROR_FLAG = 0x20U,
101 } i2s_error_t;
102
106 typedef enum {
107 I2S_IT_TXE = (1U << 0),
108 I2S_IT_TXOV = (1U << 2),
109 I2S_IT_TXUD = (1U << 3),
110 I2S_IT_RXF = (1U << 9),
111 I2S_IT_RXOV = (1U << 10),
112 I2S_IT_RXUD = (1U << 11),
113 I2S_IT_RXTH = (1U << 12),
114 I2S_IT_CRCERR = (1U << 16),
115 I2S_IT_MODF = (1U << 17),
116 I2S_IT_FRE = (1U << 18),
117 } i2s_it_t;
118
122 typedef enum {
123 I2S_DMA_REQ_TX = 0U,
124 I2S_DMA_REQ_RX = 1U,
125 } i2s_dma_req_t;
126
130 typedef enum {
131 I2S_IF_TXE = (1U << 0),
132 I2S_IF_TXOV = (1U << 2),
133 I2S_IF_TXUD = (1U << 3),
134 I2S_IF_RXF = (1U << 9),
135 I2S_IF_RXOV = (1U << 10),
136 I2S_IF_RXUD = (1U << 11),
137 I2S_IF_RXTH = (1U << 12),
138 I2S_IF_FRE = (1U << 18),
139 } i2s_flag_t;
140
144 typedef enum {
145 I2S_STATE_RESET = 0x00U,
146 I2S_STATE_READY = 0x01U,
147 I2S_STATE_BUSY = 0x02U,
148 I2S_STATE_BUSY_TX = 0x11U,
149 I2S_STATE_BUSY_RX = 0x21U,
150 I2S_STATE_BUSY_TX_RX = 0x31U,
151 I2S_STATE_TIMEOUT = 0x03U,
152 I2S_STATE_ERROR = 0x04U,
153 } i2s_state_t;
154
158 typedef enum {
159 I2S_STATUS_TXE = (1U << 0),
160 I2S_STATUS_TXF = (1U << 1),
161 I2S_STATUS_TXOV = (1U << 2),
162 I2S_STATUS_TXUD = (1U << 3),
163 I2S_STATUS_RXE = (1U << 8),
164 I2S_STATUS_RXF = (1U << 9),
165 I2S_STATUS_RXOV = (1U << 10),
166 I2S_STATUS_RXUD = (1U << 11),
167 I2S_STATUS_CHSIDE = (1U << 14),
168 I2S_STATUS_BUSY = (1U << 15),
169 } i2s_status_t;
170
174 typedef enum {
175 I2S_SIDE_LEFT = 0U,
176 I2S_SIDE_RIGHT = 1U,
177 } i2s_ch_side_t;
178
182 typedef enum {
183 I2S_SR_TXE = 0U,
184 I2S_SR_RXNE = 1U,
185 I2S_SR_TXE_RXNE = 2U,
186 } i2s_sr_status_t;
187
191 typedef struct {
192 i2s_chlen_t ch_len;
193 i2s_datalen_t data_len;
194 i2s_cpol_t polarity;
195 i2s_standard_t standard;
196 i2s_pcms_t pcm_frame;
197 type_func_t ext_clk_en;
198 uint32_t ext_clk;
199 type_func_t mck_en;
200 uint32_t sampling;
201 } i2s_init_t;
202
206 typedef struct i2s_handle_s {
207 SPI_I2S_TypeDef *perh;
208 i2s_init_t init;
209 uint16_t *tx_buf;
210 uint32_t tx_size;
211 uint32_t tx_count;
212 uint16_t *rx_buf;
213 uint32_t rx_size;
214 uint32_t rx_count;
215 #ifdef ALD_DMA
216 dma_handle_t hdmatx;
217 dma_handle_t hdmarx;
218 #endif
219 lock_state_t lock;
220 i2s_state_t state;
221 uint8_t side;
222 uint32_t err_code;
224 void (*tx_cplt_cbk)(struct i2s_handle_s *arg);
225 void (*rx_cplt_cbk)(struct i2s_handle_s *arg);
226 void (*err_cbk)(struct i2s_handle_s *arg);
227 } i2s_handle_t;
235 #define I2S_RESET_HANDLE_STATE(x) ((x)->state = I2S_STATE_RESET)
236 #define I2S_ENABLE(x) (SET_BIT((x)->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK))
237 #define I2S_DISABLE(x) (CLEAR_BIT((x)->perh->I2SCFG, SPI_I2SCFG_I2SE_MSK))
238
245 #define IS_I2S(x) (((x) == I2S0) || \
246 ((x) == I2S1) || \
247 ((x) == I2S2))
248 #define IS_I2S_CH_LEN(x) (((x) == I2S_WIDE_16) || \
249 ((x) == I2S_WIDE_32))
250 #define IS_I2S_DATE_LEN(x) (((x) == I2S_LEN_16) || \
251 ((x) == I2S_LEN_24) || \
252 ((x) == I2S_LEN_32))
253 #define IS_I2S_CPOL(x) (((x) == I2S_INACTIVE_LOW) || \
254 ((x) == I2S_INACTIVE_HIGH))
255 #define IS_I2S_STANDARD(x) (((x) == I2S_STD_PHI) || \
256 ((x) == I2S_STD_MSB) || \
257 ((x) == I2S_STD_LSB) || \
258 ((x) == I2S_STD_PCM))
259 #define IS_I2S_PCMS(x) (((x) == I2S_FRAME_SHORT) || \
260 ((x) == I2S_FRAME_LONG))
261 #define IS_I2S_IT(x) (((x) == I2S_IT_TXE) || \
262 ((x) == I2S_IT_TXOV) || \
263 ((x) == I2S_IT_TXUD) || \
264 ((x) == I2S_IT_RXF) || \
265 ((x) == I2S_IT_RXOV) || \
266 ((x) == I2S_IT_RXUD) || \
267 ((x) == I2S_IT_RXTH) || \
268 ((x) == I2S_IT_CRCERR) || \
269 ((x) == I2S_IT_MODF) || \
270 ((x) == I2S_IT_FRE))
271 #define IS_I2S_IF(x) (((x) == I2S_IF_TXE) || \
272 ((x) == I2S_IF_TXOV) || \
273 ((x) == I2S_IF_TXUD) || \
274 ((x) == I2S_IF_RXF) || \
275 ((x) == I2S_IF_RXOV) || \
276 ((x) == I2S_IF_RXUD) || \
277 ((x) == I2S_IF_RXTH) || \
278 ((x) == I2S_IF_FRE))
279 #define IS_I2S_FLAG(x) (((x) == I2S_FLAG_TXE) || \
280 ((x) == I2S_FLAG_TXF) || \
281 ((x) == I2S_FLAG_TXOV) || \
282 ((x) == I2S_FLAG_TXUD) || \
283 ((x) == I2S_FLAG_RXE) || \
284 ((x) == I2S_FLAG_RXF) || \
285 ((x) == I2S_FLAG_RXOV) || \
286 ((x) == I2S_FLAG_RXUD) || \
287 ((x) == I2S_FLAG_CHSIDE) || \
288 ((x) == I2S_FLAG_BSY))
289 #define IS_I2S_STATUS(x) (((x) == I2S_STATUS_TXE) || \
290 ((x) == I2S_STATUS_TXF) || \
291 ((x) == I2S_STATUS_TXOV) || \
292 ((x) == I2S_STATUS_TXUD) || \
293 ((x) == I2S_STATUS_RXE) || \
294 ((x) == I2S_STATUS_RXF) || \
295 ((x) == I2S_STATUS_RXOV) || \
296 ((x) == I2S_STATUS_RXUD) || \
297 ((x) == I2S_STATUS_CHSIDE) || \
298 ((x) == I2S_STATUS_BUSY))
299 #define IS_I2S_DMA_REQ(x) (((x) == I2S_DMA_REQ_TX) || \
300 ((x) == I2S_DMA_REQ_RX))
301
313 ald_status_t ald_i2s_init(i2s_handle_t *hperh);
314 void ald_i2s_reset(i2s_handle_t *hperh);
322 ald_status_t ald_i2s_master_send(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout);
323 ald_status_t ald_i2s_master_recv(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout);
324 ald_status_t ald_i2s_master_send_by_it(i2s_handle_t *hperh, uint16_t *buf, uint32_t size);
325 ald_status_t ald_i2s_master_recv_by_it(i2s_handle_t *hperh, uint16_t *buf, uint32_t size);
326 #ifdef ALD_DMA
327 ald_status_t ald_i2s_master_send_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t channel);
328 ald_status_t ald_i2s_master_recv_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t dma_ch, uint8_t _dma_ch);
329 ald_status_t ald_i2s_dma_pause(i2s_handle_t *hperh);
330 ald_status_t ald_i2s_dma_resume(i2s_handle_t *hperh);
331 ald_status_t ald_i2s_dma_stop(i2s_handle_t *hperh);
332 #endif
333
340 void ald_i2s_irq_handler(i2s_handle_t *hperh);
341 void ald_i2s_interrupt_config(i2s_handle_t *hperh, i2s_it_t it, type_func_t state);
342 void ald_i2s_dma_req_config(i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t state);
343 flag_status_t ald_i2s_get_status(i2s_handle_t *hperh, i2s_status_t status);
344 it_status_t ald_i2s_get_it_status(i2s_handle_t *hperh, i2s_it_t it);
345 flag_status_t ald_i2s_get_flag_status(i2s_handle_t *hperh, i2s_flag_t flag);
346 flag_status_t ald_i2s_get_mask_flag_status(i2s_handle_t *hperh, i2s_flag_t flag);
347 void ald_i2s_clear_flag_status(i2s_handle_t *hperh, i2s_flag_t flag);
355 i2s_state_t ald_i2s_get_state(i2s_handle_t *hperh);
356 uint32_t ald_i2s_get_error(i2s_handle_t *hperh);
372 #ifdef __cplusplus
373 }
374 #endif
375 #endif
i2s_sr_status_t
i2s_sr_status_t
I2S TXE/RXNE status definition.
Definition: ald_i2s.h:182
I2S_MASTER_TRANSMIT
Definition: ald_i2s.h:78
i2s_init_t::data_len
i2s_datalen_t data_len
Definition: ald_i2s.h:193
I2S_INACTIVE_LOW
Definition: ald_i2s.h:60
i2s_cfg_t
i2s_cfg_t
I2s configuration mode.
Definition: ald_i2s.h:77
I2S_IT_CRCERR
Definition: ald_i2s.h:114
i2s_handle_s::side
uint8_t side
Definition: ald_i2s.h:221
ald_i2s_dma_pause
ald_status_t ald_i2s_dma_pause(i2s_handle_t *hperh)
Pauses the DMA Transfer.
Definition: ald_i2s.c:575
dma_handle_t
DMA handle structure definition.
Definition: ald_dma.h:297
i2s_ch_side_t
i2s_ch_side_t
Channel side.
Definition: ald_i2s.h:174
I2S_STATUS_RXOV
Definition: ald_i2s.h:165
I2S_STATE_BUSY
Definition: ald_i2s.h:147
i2s_error_t
i2s_error_t
I2S error status.
Definition: ald_i2s.h:93
ald_i2s_init
ald_status_t ald_i2s_init(i2s_handle_t *hperh)
Initializes the I2S mode according to the specified parameters in the i2s_init_t and create the assoc...
Definition: ald_i2s.c:146
I2S_IF_RXF
Definition: ald_i2s.h:134
i2s_init_t::ext_clk_en
type_func_t ext_clk_en
Definition: ald_i2s.h:197
ald_i2s_dma_req_config
void ald_i2s_dma_req_config(i2s_handle_t *hperh, i2s_dma_req_t req, type_func_t state)
Enables or disables the dma request.
Definition: ald_i2s.c:709
ald_i2s_master_recv_by_it
ald_status_t ald_i2s_master_recv_by_it(i2s_handle_t *hperh, uint16_t *buf, uint32_t size)
Master mode receives an amount of data in non blocking mode.
Definition: ald_i2s.c:388
ald_i2s_get_flag_status
flag_status_t ald_i2s_get_flag_status(i2s_handle_t *hperh, i2s_flag_t flag)
Check whether the specified I2S interrupt flag is set or not.
Definition: ald_i2s.c:778
I2S_STD_PHI
Definition: ald_i2s.h:68
type_func_t
type_func_t
Definition: type.h:47
i2c_handle_s::state
__IO i2c_state_t state
Definition: ald_i2c.h:280
I2S_IT_RXTH
Definition: ald_i2s.h:113
i2s_standard_t
i2s_standard_t
I2s standard.
Definition: ald_i2s.h:67
ald_i2s_get_error
uint32_t ald_i2s_get_error(i2s_handle_t *hperh)
Return the I2S error code.
Definition: ald_i2s.c:858
I2S_IT_RXUD
Definition: ald_i2s.h:112
I2S_IT_TXE
Definition: ald_i2s.h:107
i2s_init_t::sampling
uint32_t sampling
Definition: ald_i2s.h:200
i2s_it_t
i2s_it_t
interrupt control
Definition: ald_i2s.h:106
I2S_SR_TXE
Definition: ald_i2s.h:183
I2S_STATUS_BUSY
Definition: ald_i2s.h:168
I2S_MASTER_RECEIVE
Definition: ald_i2s.h:79
i2s_init_t
I2S init structure definition.
Definition: ald_i2s.h:191
i2s_handle_s::rx_buf
uint16_t * rx_buf
Definition: ald_i2s.h:212
I2S_STATE_ERROR
Definition: ald_i2s.h:152
I2S_FRAME_SHORT
Definition: ald_i2s.h:86
I2S_SR_RXNE
Definition: ald_i2s.h:184
I2S_STD_PCM
Definition: ald_i2s.h:71
i2s_handle_s::hdmarx
dma_handle_t hdmarx
Definition: ald_i2s.h:217
I2S_STATE_BUSY_TX_RX
Definition: ald_i2s.h:150
i2s_init_t::ext_clk
uint32_t ext_clk
Definition: ald_i2s.h:198
ald_i2s_master_send_by_it
ald_status_t ald_i2s_master_send_by_it(i2s_handle_t *hperh, uint16_t *buf, uint32_t size)
Wraps up master mode transmission in non blocking mode.
Definition: ald_i2s.c:349
I2S_STATUS_TXE
Definition: ald_i2s.h:159
ald_i2s_dma_resume
ald_status_t ald_i2s_dma_resume(i2s_handle_t *hperh)
Resumes the DMA Transfer.
Definition: ald_i2s.c:590
i2s_handle_s::rx_cplt_cbk
void(* rx_cplt_cbk)(struct i2s_handle_s *arg)
Definition: ald_i2s.h:225
I2S_ERROR_RXOV
Definition: ald_i2s.h:98
i2s_handle_s::state
i2s_state_t state
Definition: ald_i2s.h:220
ald_i2s_get_state
i2s_state_t ald_i2s_get_state(i2s_handle_t *hperh)
Returns the I2S state.
Definition: ald_i2s.c:847
utils.h
This file contains the Utilities functions/types for the driver.
I2S_IT_RXOV
Definition: ald_i2s.h:111
I2S_SR_TXE_RXNE
Definition: ald_i2s.h:185
i2s_handle_s::err_cbk
void(* err_cbk)(struct i2s_handle_s *arg)
Definition: ald_i2s.h:226
I2S_SIDE_LEFT
Definition: ald_i2s.h:175
i2s_pcms_t
i2s_pcms_t
Pcm frame synchronization.
Definition: ald_i2s.h:85
I2S_IF_RXTH
Definition: ald_i2s.h:137
I2S_ERROR_TXOV
Definition: ald_i2s.h:99
i2s_handle_s::lock
lock_state_t lock
Definition: ald_i2s.h:219
i2s_init_t::ch_len
i2s_chlen_t ch_len
Definition: ald_i2s.h:192
it_status_t
enum flag_status_t it_status_t
ald_i2s_irq_handler
void ald_i2s_irq_handler(i2s_handle_t *hperh)
This function handles I2S interrupt request.
Definition: ald_i2s.c:646
i2s_handle_s::err_code
uint32_t err_code
Definition: ald_i2s.h:222
i2s_chlen_t
i2s_chlen_t
Channel length.
Definition: ald_i2s.h:42
ald_i2s_interrupt_config
void ald_i2s_interrupt_config(i2s_handle_t *hperh, i2s_it_t it, type_func_t state)
Enables or disables the specified I2S interrupts.
Definition: ald_i2s.c:685
i2s_handle_s::tx_size
uint32_t tx_size
Definition: ald_i2s.h:210
I2S_STATUS_TXF
Definition: ald_i2s.h:160
I2S_LEN_16
Definition: ald_i2s.h:51
I2S_IT_MODF
Definition: ald_i2s.h:115
ald_i2s_master_recv
ald_status_t ald_i2s_master_recv(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout)
Master mode receive an amount of data in blocking mode.
Definition: ald_i2s.c:307
ald_i2s_dma_stop
ald_status_t ald_i2s_dma_stop(i2s_handle_t *hperh)
Stops the DMA Transfer.
Definition: ald_i2s.c:605
i2s_init_t::standard
i2s_standard_t standard
Definition: ald_i2s.h:195
i2s_handle_t
struct i2s_handle_s i2s_handle_t
I2S handle structure definition.
i2s_init_t::mck_en
type_func_t mck_en
Definition: ald_i2s.h:199
I2S_STATE_BUSY_TX
Definition: ald_i2s.h:148
i2s_state_t
i2s_state_t
I2S state structures definition.
Definition: ald_i2s.h:144
I2S_ERROR_DMA
Definition: ald_i2s.h:96
I2S_FRAME_LONG
Definition: ald_i2s.h:87
lock_state_t
lock_state_t
Definition: type.h:58
I2S_SIDE_RIGHT
Definition: ald_i2s.h:176
ald_dma.h
DMA module Library.
I2S_STATUS_RXUD
Definition: ald_i2s.h:166
I2S_IF_TXUD
Definition: ald_i2s.h:133
I2S_STATE_BUSY_RX
Definition: ald_i2s.h:149
I2S_STATE_RESET
Definition: ald_i2s.h:145
I2S_ERROR_NONE
Definition: ald_i2s.h:94
I2S_IT_TXOV
Definition: ald_i2s.h:108
I2S_IF_FRE
Definition: ald_i2s.h:138
I2S_IF_TXE
Definition: ald_i2s.h:131
I2S_ERROR_FRE
Definition: ald_i2s.h:97
I2S_ERROR_FLAG
Definition: ald_i2s.h:100
I2S_DMA_REQ_TX
Definition: ald_i2s.h:123
I2S_IF_RXUD
Definition: ald_i2s.h:136
I2S_STD_MSB
Definition: ald_i2s.h:69
I2S_STATUS_TXUD
Definition: ald_i2s.h:162
ald_i2s_get_it_status
it_status_t ald_i2s_get_it_status(i2s_handle_t *hperh, i2s_it_t it)
Checks whether the specified I2S interrupt has occurred or not.
Definition: ald_i2s.c:759
I2S_STATUS_RXE
Definition: ald_i2s.h:163
i2s_handle_s::tx_buf
uint16_t * tx_buf
Definition: ald_i2s.h:209
I2S_IF_RXOV
Definition: ald_i2s.h:135
ald_i2s_get_status
flag_status_t ald_i2s_get_status(i2s_handle_t *hperh, i2s_status_t status)
Check whether the specified I2S flag is set or not.
Definition: ald_i2s.c:739
I2S_ERROR_MODF
Definition: ald_i2s.h:95
I2S_STATUS_CHSIDE
Definition: ald_i2s.h:167
i2s_handle_s::rx_count
uint32_t rx_count
Definition: ald_i2s.h:214
ald_i2s_clear_flag_status
void ald_i2s_clear_flag_status(i2s_handle_t *hperh, i2s_flag_t flag)
Clear the specified I2S interrupt flags.
Definition: ald_i2s.c:814
ald_i2s_master_recv_by_dma
ald_status_t ald_i2s_master_recv_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t dma_ch, uint8_t _dma_ch)
Master mode receive an amount of data used dma channel.
Definition: ald_i2s.c:495
I2S_IT_RXF
Definition: ald_i2s.h:110
I2S_WIDE_16
Definition: ald_i2s.h:43
I2S_LEN_24
Definition: ald_i2s.h:52
I2S_STATUS_RXF
Definition: ald_i2s.h:164
I2S_IF_TXOV
Definition: ald_i2s.h:132
i2s_init_t::polarity
i2s_cpol_t polarity
Definition: ald_i2s.h:194
ald_i2s_get_mask_flag_status
flag_status_t ald_i2s_get_mask_flag_status(i2s_handle_t *hperh, i2s_flag_t flag)
Check whether the specified I2S interrupt flag is set or not.
Definition: ald_i2s.c:797
i2s_handle_s::hdmatx
dma_handle_t hdmatx
Definition: ald_i2s.h:216
I2S_STD_LSB
Definition: ald_i2s.h:70
I2S_STATE_TIMEOUT
Definition: ald_i2s.h:151
I2S_INACTIVE_HIGH
Definition: ald_i2s.h:61
i2s_status_t
i2s_status_t
I2S status definition.
Definition: ald_i2s.h:158
I2S_STATE_READY
Definition: ald_i2s.h:146
flag_status_t
flag_status_t
Definition: type.h:37
I2S_IT_TXUD
Definition: ald_i2s.h:109
ald_i2s_master_send
ald_status_t ald_i2s_master_send(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint32_t timeout)
Master mode transmit an amount of data in blocking mode.
Definition: ald_i2s.c:254
i2s_datalen_t
i2s_datalen_t
Data length.
Definition: ald_i2s.h:50
I2S_IT_FRE
Definition: ald_i2s.h:116
i2s_handle_s
I2S handle structure definition.
Definition: ald_i2s.h:206
i2s_flag_t
i2s_flag_t
interrupt flag
Definition: ald_i2s.h:130
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
I2S_DMA_REQ_RX
Definition: ald_i2s.h:124
i2s_dma_req_t
i2s_dma_req_t
I2S dma request definition.
Definition: ald_i2s.h:122
ald_i2s_reset
void ald_i2s_reset(i2s_handle_t *hperh)
Reset the I2S peripheral.
Definition: ald_i2s.c:128
i2s_handle_s::tx_count
uint32_t tx_count
Definition: ald_i2s.h:211
i2s_handle_s::init
i2s_init_t init
Definition: ald_i2s.h:208
I2S_LEN_32
Definition: ald_i2s.h:53
i2s_cpol_t
i2s_cpol_t
Inactive state clock polarity.
Definition: ald_i2s.h:59
ald_i2s_master_send_by_dma
ald_status_t ald_i2s_master_send_by_dma(i2s_handle_t *hperh, uint16_t *buf, uint32_t size, uint8_t channel)
Master mode transmit an amount of data used dma channel.
Definition: ald_i2s.c:432
i2s_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_i2s.h:207
i2s_init_t::pcm_frame
i2s_pcms_t pcm_frame
Definition: ald_i2s.h:196
I2S_WIDE_32
Definition: ald_i2s.h:44
I2S_STATUS_TXOV
Definition: ald_i2s.h:161
i2s_handle_s::rx_size
uint32_t rx_size
Definition: ald_i2s.h:213


ALD User Manual: D:/svn/src/ald_iap.c Source File

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  • src
ald_iap.c
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1
17 #include "ald_iap.h"
18
19
28 #ifdef ALD_IAP
29
30
52 uint32_t ald_iap_erase_page(uint32_t addr)
53 {
54 uint32_t status;
55 IAP_PE iap_pe = (IAP_PE)(*(uint32_t *)IAP_PE_ADDR);
56
57 __disable_irq();
58 status = (*iap_pe)(addr);
59 __enable_irq();
60
61 return !status;
62 }
63
73 uint32_t ald_iap_program_word(uint32_t addr, uint32_t data)
74 {
75 uint32_t status;
76 IAP_WP iap_wp = (IAP_WP)(*(uint32_t *)IAP_WP_ADDR);
77
78 if (addr & 0x3)
79 return 1;
80
81 __disable_irq();
82 status = (*iap_wp)(addr, data);
83 __enable_irq();
84
85 return !status;
86 }
87
98 uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h)
99 {
100 uint32_t status;
101 IAP_DWP iap_dwp = (IAP_DWP)(*(uint32_t *)IAP_DWP_ADDR);
102
103 if (addr & 0x3)
104 return 1;
105
106 __disable_irq();
107 status = (*iap_dwp)(addr, data_l, data_h);
108 __enable_irq();
109
110 return !status;
111 }
112
125 uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase)
126 {
127 uint32_t status;
128 IAP_WSP iap_wsp = (IAP_WSP)(*(uint32_t *)IAP_WSP_ADDR);
129
130 if ((addr & 0x3) || (len & 0x3))
131 return 1;
132
133 __disable_irq();
134 status = (*iap_wsp)(addr, data, len, erase);
135 __enable_irq();
136
137 return !status;
138 }
142 #endif /* ALD_IAP */
143
IAP_DWP_ADDR
#define IAP_DWP_ADDR
Definition: ald_iap.h:42
IAP_DWP
uint32_t(* IAP_DWP)(uint32_t addr, uint32_t data_l, uint32_t data_h)
Definition: ald_iap.h:52
IAP_WSP
uint32_t(* IAP_WSP)(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase)
Definition: ald_iap.h:53
IAP_PE
uint32_t(* IAP_PE)(uint32_t addr)
Definition: ald_iap.h:50
IAP_WP
uint32_t(* IAP_WP)(uint32_t addr, uint32_t data)
Definition: ald_iap.h:51
ald_iap_erase_page
uint32_t ald_iap_erase_page(uint32_t addr)
Erases a specified page.
Definition: ald_iap.c:52
ald_iap_program_words
uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase)
Programs datas at a specified address.
Definition: ald_iap.c:125
ald_iap_program_dword
uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h)
Programs double words at a specified address.
Definition: ald_iap.c:98
IAP_WSP_ADDR
#define IAP_WSP_ADDR
Definition: ald_iap.h:39
IAP_WP_ADDR
#define IAP_WP_ADDR
Definition: ald_iap.h:41
ald_iap_program_word
uint32_t ald_iap_program_word(uint32_t addr, uint32_t data)
Programs a word at a specified address.
Definition: ald_iap.c:73
ald_iap.h
Header file of IAP module driver.
IAP_PE_ADDR
#define IAP_PE_ADDR
Definition: ald_iap.h:40


ALD User Manual: D:/svn/src/ald_iap.h Source File

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  • src
ald_iap.h
Go to the documentation of this file.
1
17 #ifndef __ALD_IAP_H__
18 #define __ALD_IAP_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25
26
39 #define IAP_WSP_ADDR 0x10000000U
40 #define IAP_PE_ADDR 0x10000004U
41 #define IAP_WP_ADDR 0x10000008U
42 #define IAP_DWP_ADDR 0x1000000cU
43
50 typedef uint32_t (*IAP_PE)(uint32_t addr);
51 typedef uint32_t (*IAP_WP)(uint32_t addr, uint32_t data);
52 typedef uint32_t (*IAP_DWP)(uint32_t addr, uint32_t data_l, uint32_t data_h);
53 typedef uint32_t (*IAP_WSP)(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase);
61 uint32_t ald_iap_erase_page(uint32_t addr);
62 uint32_t ald_iap_program_word(uint32_t addr, uint32_t data);
63 uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h);
64 uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase);
76 #ifdef __cplusplus
77 }
78 #endif
79
80 #endif /* __ALD_IAP_H__ */
IAP_DWP
uint32_t(* IAP_DWP)(uint32_t addr, uint32_t data_l, uint32_t data_h)
Definition: ald_iap.h:52
IAP_WSP
uint32_t(* IAP_WSP)(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase)
Definition: ald_iap.h:53
IAP_PE
uint32_t(* IAP_PE)(uint32_t addr)
Definition: ald_iap.h:50
utils.h
This file contains the Utilities functions/types for the driver.
IAP_WP
uint32_t(* IAP_WP)(uint32_t addr, uint32_t data)
Definition: ald_iap.h:51
ald_iap_erase_page
uint32_t ald_iap_erase_page(uint32_t addr)
Erases a specified page.
Definition: ald_iap.c:52
ald_iap_program_words
uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase)
Programs datas at a specified address.
Definition: ald_iap.c:125
ald_iap_program_dword
uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h)
Programs double words at a specified address.
Definition: ald_iap.c:98
ald_iap_program_word
uint32_t ald_iap_program_word(uint32_t addr, uint32_t data)
Programs a word at a specified address.
Definition: ald_iap.c:73


ALD User Manual: D:/svn/src/ald_nand.c Source File

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ald_nand.c
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1
43 #include "ald_nand.h"
44
45
54 #ifdef ALD_NAND
55
71 ald_status_t ald_nand_init(nand_handle_t *hperh, ald_ebi_nand_timing_t *ctiming, ald_ebi_nand_timing_t *atiming)
72 {
73 if (hperh == NULL)
74 return ERROR;
75 if (hperh->state == ALD_NAND_STATE_RESET)
76 hperh->lock = UNLOCK;
77
78 ald_ebi_nand_init(hperh->instance, &(hperh->init));
79 ald_ebi_nand_comm_timing_init(hperh->instance, ctiming, hperh->init.bank);
80 ald_ebi_nand_attr_timing_init(hperh->instance, atiming, hperh->init.bank);
81 ald_ebi_nand_enable(hperh->instance, hperh->init.bank);
82 hperh->state = ALD_NAND_STATE_READY;
83
84 return OK;
85 }
86
92 ald_status_t ald_nand_deinit(nand_handle_t *hperh)
93 {
94 ald_ebi_nand_deinit(hperh->instance, hperh->init.bank);
95 hperh->state = ALD_NAND_STATE_RESET;
96 __UNLOCK(hperh);
97
98 return OK;
99 }
100
106 ald_status_t ald_nand_reset(nand_handle_t *hperh)
107 {
108 uint32_t deviceaddr = 0;
109
110 __LOCK(hperh);
111
112 if (hperh->state == ALD_NAND_STATE_BUSY)
113 return BUSY;
114
115 /* Identify the device address */
116 if (hperh->init.bank == EBI_NAND_BANK2)
117 deviceaddr = NAND_DEVICE1;
118 else
119 deviceaddr = NAND_DEVICE2;
120
121 hperh->state = ALD_NAND_STATE_BUSY;
122
123 /* Send NAND reset command */
124 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = 0xFF;
125
126 hperh->state = ALD_NAND_STATE_READY;
127 __UNLOCK(hperh);
128
129 return OK;
130 }
131
138 void nand_config_device(nand_handle_t *hperh, nand_device_cfg_t *pdcfg)
139 {
140 hperh->config.page_size = pdcfg->page_size;
141 hperh->config.spare_size = pdcfg->spare_size;
142 hperh->config.block_size = pdcfg->block_size;
143 hperh->config.block_nbr = pdcfg->block_nbr;
144 hperh->config.plane_size = pdcfg->plane_size;
145 hperh->config.plane_nbr = pdcfg->plane_nbr;
146 hperh->config.extra_cmd = pdcfg->extra_cmd;
147 }
161 ald_status_t ald_nand_read_id(nand_handle_t *hperh, nand_id_t *id)
162 {
163 __IO uint32_t data = 0;
164 __IO uint32_t data1 = 0;
165 uint32_t deviceaddr = 0;
166
167 __LOCK(hperh);
168
169 if (hperh->state == ALD_NAND_STATE_BUSY)
170 return BUSY;
171
172 /* Identify the device address */
173 if (hperh->init.bank == EBI_NAND_BANK2)
174 deviceaddr = NAND_DEVICE1;
175 else
176 deviceaddr = NAND_DEVICE2;
177
178 hperh->state = ALD_NAND_STATE_BUSY;
179
180 /* Send Read ID command sequence */
181 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_READID;
182 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
183
184 if (hperh->init.width == EBI_NAND_MEM_BUS_WIDTH_8) {
185 data = *(__IO uint32_t *)deviceaddr;
186
187 id->maker_id = ADDR_1ST_CYCLE(data);
188 id->device_id = ADDR_2ND_CYCLE(data);
189 id->third_id = ADDR_3RD_CYCLE(data);
190 id->fourth_id = ADDR_4TH_CYCLE(data);
191 }
192 else {
193 data = *(__IO uint32_t *)deviceaddr;
194 data1 = *((__IO uint32_t *)deviceaddr + 4);
195
196 /* Return the data read */
197 id->maker_id = ADDR_1ST_CYCLE(data);
198 id->device_id = ADDR_3RD_CYCLE(data);
199 id->third_id = ADDR_1ST_CYCLE(data1);
200 id->fourth_id = ADDR_3RD_CYCLE(data1);
201 }
202
203 hperh->state = ALD_NAND_STATE_READY;
204 __UNLOCK(hperh);
205
206 return OK;
207 }
208
217 ald_status_t ald_nand_read_page_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
218 {
219 __IO uint32_t index = 0;
220 uint32_t tickstart = 0;
221 uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0;
222
223 __LOCK(hperh);
224
225 if (hperh->state == ALD_NAND_STATE_BUSY)
226 return BUSY;
227
228 /* Identify the device address */
229 if (hperh->init.bank == EBI_NAND_BANK2)
230 deviceaddr = NAND_DEVICE1;
231 else
232 deviceaddr = NAND_DEVICE2;
233
234 hperh->state = ALD_NAND_STATE_BUSY;
235
236 /* NAND raw address calculation */
237 nandaddr = ARRAY_ADDRESS(addr, hperh);
238
239 /* Page(s) read loop */
240 while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) {
241 /* update the buffer size */
242 size = (hperh->config.page_size) + ((hperh->config.page_size) * num);
243
244 /* Send read page command sequence */
245 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A;
246
247 /* Cards with page size <= 512 bytes */
248 if ((hperh->config.page_size) <= 512U) {
249 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
250 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
251 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
252 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
253 }
254 else { /* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
255 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
256 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
257 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
258 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
259 }
260 }
261 else { /* (hperh->config.page_size) > 512 */
262 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
263 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
264 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
265 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
266 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
267 }
268 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
269 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
270 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
271 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
272 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
273 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
274 }
275 }
276
277 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
278
279 /* Check if an extra command is needed for reading pages */
280 if (hperh->config.extra_cmd == ENABLE) {
281 /* Get tick */
282 tickstart = ald_get_tick();
283
284 /* Read status until NAND is ready */
285 while (ald_nand_read_status(hperh) != NAND_READY) {
286 if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT)
287 return TIMEOUT;
288 }
289
290 /* Go back to read mode */
291 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = ((uint8_t)0x00);
292 }
293
294 /* Get Data into Buffer */
295 for (; index < size; index++) {
296 *(uint8_t *)buf++ = *(uint8_t *)deviceaddr;
297 }
298
299 num++;
300 nr--;
301 nandaddr = (uint32_t)(nandaddr + 1U);
302 }
303
304 hperh->state = ALD_NAND_STATE_READY;
305 __UNLOCK(hperh);
306
307 return OK;
308 }
309
318 ald_status_t ald_nand_write_page_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
319 {
320 __IO uint32_t index = 0;
321 uint32_t tickstart = 0;
322 uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0;
323
324 __LOCK(hperh);
325
326 if (hperh->state == ALD_NAND_STATE_BUSY)
327 return BUSY;
328
329 /* Identify the device address */
330 if (hperh->init.bank == EBI_NAND_BANK2)
331 deviceaddr = NAND_DEVICE1;
332 else
333 deviceaddr = NAND_DEVICE2;
334
335 /* Update the NAND controller state */
336 hperh->state = ALD_NAND_STATE_BUSY;
337
338 /* NAND raw address calculation */
339 nandaddr = ARRAY_ADDRESS(addr, hperh);
340
341 /* Page(s) write loop */
342 while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) {
343 /* update the buffer size */
344 size = hperh->config.page_size + ((hperh->config.page_size) * num);
345
346 /* Send write page command sequence */
347 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A;
348 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0;
349
350 /* Cards with page size <= 512 bytes */
351 if ((hperh->config.page_size) <= 512U) {
352 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
353 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
354 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
355 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
356 }
357 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
358 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
359 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
360 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
361 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
362 }
363 }
364 else {/* (hperh->config.page_size) > 512 */
365 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
366 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
367 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
368 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
369 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
370 }
371 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
372 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
373 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
374 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
375 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
376 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
377 }
378 }
379
380 /* Write data to memory */
381 for (; index < size; index++)
382 *(__IO uint8_t *)deviceaddr = *(uint8_t *)buf++;
383
384 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
385
386 /* Read status until NAND is ready */
387 while (ald_nand_read_status(hperh) != NAND_READY) {
388 /* Get tick */
389 tickstart = ald_get_tick();
390
391 if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT)
392 return TIMEOUT;
393 }
394
395 num++;
396 nr--;
397 nandaddr = (uint32_t)(nandaddr + 1U);
398 }
399
400 hperh->state = ALD_NAND_STATE_READY;
401 __UNLOCK(hperh);
402
403 return OK;
404 }
405
414 ald_status_t ald_nand_read_sparearea_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
415 {
416 __IO uint32_t index = 0;
417 uint32_t tickstart = 0;
418 uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0, columnaddr = 0;
419
420 /* Process Locked */
421 __LOCK(hperh);
422
423 if (hperh->state == ALD_NAND_STATE_BUSY)
424 return BUSY;
425
426 /* Identify the device address */
427 if (hperh->init.bank == EBI_NAND_BANK2)
428 deviceaddr = NAND_DEVICE1;
429 else
430 deviceaddr = NAND_DEVICE2;
431
432 /* Update the NAND controller state */
433 hperh->state = ALD_NAND_STATE_BUSY;
434 /* NAND raw address calculation */
435 nandaddr = ARRAY_ADDRESS(addr, hperh);
436 /* Column in page address */
437 columnaddr = COLUMN_ADDRESS(hperh);
438
439 /* Spare area(s) read loop */
440 while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) {
441 /* update the buffer size */
442 size = (hperh->config.spare_size) + ((hperh->config.spare_size) * num);
443
444 /* Cards with page size <= 512 bytes */
445 if ((hperh->config.page_size) <= 512U) {
446 /* Send read spare area command sequence */
447 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_C;
448
449 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
450 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
451 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
452 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
453 }
454 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
455 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
456 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
457 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
458 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
459 }
460 }
461 else {/* (hperh->config.page_size) > 512 */
462 /* Send read spare area command sequence */
463 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A;
464
465 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
466 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr);
467 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr);
468 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
469 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
470 }
471 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
472 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr);
473 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr);
474 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
475 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
476 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
477 }
478 }
479
480 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
481
482 if (hperh->config.extra_cmd == ENABLE) {
483 /* Get tick */
484 tickstart = ald_get_tick();
485
486 /* Read status until NAND is ready */
487 while (ald_nand_read_status(hperh) != NAND_READY) {
488 if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT)
489 return TIMEOUT;
490 }
491
492 /* Go back to read mode */
493 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = ((uint8_t)0x00);
494 }
495
496 /* Get Data into Buffer */
497 for (; index < size; index++)
498 *(uint8_t *)buf++ = *(uint8_t *)deviceaddr;
499
500 num++;
501 nr--;
502 nandaddr = (uint32_t)(nandaddr + 1U);
503 }
504
505 hperh->state = ALD_NAND_STATE_READY;
506 __UNLOCK(hperh);
507
508 return OK;
509 }
510
519 ald_status_t ald_nand_write_sparearea_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
520 {
521 __IO uint32_t index = 0;
522 uint32_t tickstart = 0;
523 uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0, columnaddr = 0;
524
525 __LOCK(hperh);
526
527 if (hperh->state == ALD_NAND_STATE_BUSY)
528 return BUSY;
529
530 /* Identify the device address */
531 if (hperh->init.bank == EBI_NAND_BANK2)
532 deviceaddr = NAND_DEVICE1;
533 else
534 deviceaddr = NAND_DEVICE2;
535
536 /* Update the FSMC_NAND controller state */
537 hperh->state = ALD_NAND_STATE_BUSY;
538 /* Page address calculation */
539 nandaddr = ARRAY_ADDRESS(addr, hperh);
540 /* Column in page address */
541 columnaddr = COLUMN_ADDRESS(hperh);
542
543 /* Spare area(s) write loop */
544 while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) {
545 /* update the buffer size */
546 size = (hperh->config.spare_size) + ((hperh->config.spare_size) * num);
547
548 /* Cards with page size <= 512 bytes */
549 if ((hperh->config.page_size) <= 512U) {
550 /* Send write Spare area command sequence */
551 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_C;
552 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0;
553
554 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
555 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
556 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
557 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
558 }
559 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
560 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
561 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
562 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
563 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
564 }
565 }
566 else {/* (hperh->config.page_size) > 512 */
567 /* Send write Spare area command sequence */
568 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A;
569 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0;
570
571 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
572 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr);
573 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr);
574 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
575 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
576 }
577 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
578 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr);
579 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr);
580 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
581 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
582 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
583 }
584 }
585
586 /* Write data to memory */
587 for (; index < size; index++)
588 *(__IO uint8_t *)deviceaddr = *(uint8_t *)buf++;
589
590 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
591 tickstart = ald_get_tick();
592
593 /* Read status until NAND is ready */
594 while (ald_nand_read_status(hperh) != NAND_READY) {
595 if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT)
596 return TIMEOUT;
597 }
598
599 num++;
600 nr--;
601 nandaddr = (uint32_t)(nandaddr + 1U);
602 }
603
604 hperh->state = ALD_NAND_STATE_READY;
605 __UNLOCK(hperh);
606
607 return OK;
608 }
609
618 ald_status_t ald_nand_read_page_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
619 {
620 __IO uint32_t index = 0;
621 uint32_t tickstart = 0;
622 uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0;
623
624 __LOCK(hperh);
625
626 if (hperh->state == ALD_NAND_STATE_BUSY)
627 return BUSY;
628
629 /* Identify the device address */
630 if (hperh->init.bank == EBI_NAND_BANK2)
631 deviceaddr = NAND_DEVICE1;
632 else
633 deviceaddr = NAND_DEVICE2;
634
635 hperh->state = ALD_NAND_STATE_BUSY;
636 nandaddr = ARRAY_ADDRESS(addr, hperh);
637
638 /* Page(s) read loop */
639 while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) {
640 /* update the buffer size */
641 size = (hperh->config.page_size) + ((hperh->config.page_size) * num);
642
643 /* Send read page command sequence */
644 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A;
645
646 /* Cards with page size <= 512 bytes */
647 if ((hperh->config.page_size) <= 512U) {
648 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
649 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
650 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
651 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
652 }
653 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
654 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
655 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
656 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
657 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
658 }
659 }
660 else {/* (hperh->config.page_size) > 512 */
661 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
662 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
663 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
664 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
665 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
666 }
667 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
668 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
669 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
670 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
671 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
672 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
673 }
674 }
675
676 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
677
678 if (hperh->config.extra_cmd == ENABLE) {
679 /* Get tick */
680 tickstart = ald_get_tick();
681
682 /* Read status until NAND is ready */
683 while (ald_nand_read_status(hperh) != NAND_READY) {
684 if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT)
685 return TIMEOUT;
686 }
687
688 /* Go back to read mode */
689 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = ((uint8_t)0x00);
690 }
691
692 /* Get Data into Buffer */
693 for (; index < size; index++)
694 *(uint16_t *)buf++ = *(uint16_t *)deviceaddr;
695
696 num++;
697 nr--;
698 nandaddr = (uint32_t)(nandaddr + 1U);
699 }
700
701 hperh->state = ALD_NAND_STATE_READY;
702 __UNLOCK(hperh);
703
704 return OK;
705 }
706
715 ald_status_t ald_nand_write_page_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
716 {
717 __IO uint32_t index = 0;
718 uint32_t tickstart = 0;
719 uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0;
720
721 __LOCK(hperh);
722
723 if (hperh->state == ALD_NAND_STATE_BUSY)
724 return BUSY;
725
726 /* Identify the device address */
727 if (hperh->init.bank == EBI_NAND_BANK2)
728 deviceaddr = NAND_DEVICE1;
729 else
730 deviceaddr = NAND_DEVICE2;
731
732 hperh->state = ALD_NAND_STATE_BUSY;
733 /* NAND raw address calculation */
734 nandaddr = ARRAY_ADDRESS(addr, hperh);
735
736 /* Page(s) write loop */
737 while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) {
738 /* update the buffer size */
739 size = (hperh->config.page_size) + ((hperh->config.page_size) * num);
740
741 /* Send write page command sequence */
742 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A;
743 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0;
744
745 /* Cards with page size <= 512 bytes */
746 if ((hperh->config.page_size) <= 512U) {
747 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
748 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
749 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
750 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
751 }
752 else { /* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
753 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
754 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
755 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
756 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
757 }
758 }
759 else { /* (hperh->config.page_size) > 512 */
760 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
761 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
762 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
763 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
764 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
765 }
766 else { /* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
767 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
768 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
769 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
770 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
771 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
772 }
773 }
774
775 /* Write data to memory */
776 for (; index < size; index++)
777 *(__IO uint16_t *)deviceaddr = *(uint16_t *)buf++;
778
779 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
780
781 /* Read status until NAND is ready */
782 while (ald_nand_read_status(hperh) != NAND_READY) {
783 /* Get tick */
784 tickstart = ald_get_tick();
785
786 if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT)
787 return TIMEOUT;
788 }
789
790 num++;
791 nr--;
792 nandaddr = (uint32_t)(nandaddr + 1U);
793 }
794
795 hperh->state = ALD_NAND_STATE_READY;
796 __UNLOCK(hperh);
797
798 return OK;
799 }
800
801
802
811 ald_status_t ald_nand_read_sparearea_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
812 {
813 __IO uint32_t index = 0;
814 uint32_t tickstart = 0;
815 uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0, columnaddr = 0;
816
817 __LOCK(hperh);
818
819 /* Check the NAND controller state */
820 if (hperh->state == ALD_NAND_STATE_BUSY)
821 return BUSY;
822
823 /* Identify the device address */
824 if (hperh->init.bank == EBI_NAND_BANK2)
825 deviceaddr = NAND_DEVICE1;
826 else
827 deviceaddr = NAND_DEVICE2;
828
829 /* Update the NAND controller state */
830 hperh->state = ALD_NAND_STATE_BUSY;
831 /* NAND raw address calculation */
832 nandaddr = ARRAY_ADDRESS(addr, hperh);
833 /* Column in page address */
834 columnaddr = (uint32_t)(COLUMN_ADDRESS(hperh) * 2U);
835
836 /* Spare area(s) read loop */
837 while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) {
838 /* update the buffer size */
839 size = (hperh->config.spare_size) + ((hperh->config.spare_size) * num);
840
841 /* Cards with page size <= 512 bytes */
842 if ((hperh->config.page_size) <= 512U) {
843 /* Send read spare area command sequence */
844 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_C;
845
846 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
847 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
848 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
849 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
850 }
851 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
852 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
853 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
854 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
855 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
856 }
857 }
858 else {/* (hperh->config.page_size) > 512 */
859 /* Send read spare area command sequence */
860 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A;
861
862 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
863 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr);
864 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr);
865 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
866 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
867 }
868 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
869 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr);
870 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr);
871 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
872 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
873 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
874 }
875 }
876
877 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
878
879 if (hperh->config.extra_cmd == ENABLE) {
880 /* Get tick */
881 tickstart = ald_get_tick();
882
883 /* Read status until NAND is ready */
884 while (ald_nand_read_status(hperh) != NAND_READY) {
885 if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT)
886 return TIMEOUT;
887 }
888
889 /* Go back to read mode */
890 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = ((uint8_t)0x00);
891 }
892
893 /* Get Data into Buffer */
894 for (; index < size; index++)
895 *(uint16_t *)buf++ = *(uint16_t *)deviceaddr;
896
897 num++;
898 nr--;
899 nandaddr = (uint32_t)(nandaddr + 1U);
900 }
901
902 hperh->state = ALD_NAND_STATE_READY;
903 __UNLOCK(hperh);
904
905 return OK;
906 }
907
908
917 ald_status_t ald_nand_write_sparearea_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
918 {
919 __IO uint32_t index = 0;
920 uint32_t tickstart = 0;
921 uint32_t deviceaddr = 0, size = 0, num = 0, nandaddr = 0, columnaddr = 0;
922
923 __LOCK(hperh);
924
925 if (hperh->state == ALD_NAND_STATE_BUSY)
926 return BUSY;
927
928 /* Identify the device address */
929 if (hperh->init.bank == EBI_NAND_BANK2)
930 deviceaddr = NAND_DEVICE1;
931 else
932 deviceaddr = NAND_DEVICE2;
933
934 /* Update the FSMC_NAND controller state */
935 hperh->state = ALD_NAND_STATE_BUSY;
936 /* NAND raw address calculation */
937 nandaddr = ARRAY_ADDRESS(addr, hperh);
938 /* Column in page address */
939 columnaddr = (uint32_t)(COLUMN_ADDRESS(hperh) * 2);
940
941 /* Spare area(s) write loop */
942 while ((nr != 0) && (nandaddr < ((hperh->config.block_size) * (hperh->config.block_nbr)))) {
943 /* update the buffer size */
944 size = (hperh->config.spare_size) + ((hperh->config.spare_size) * num);
945
946 /* Cards with page size <= 512 bytes */
947 if ((hperh->config.page_size) <= 512U) {
948 /* Send write Spare area command sequence */
949 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_C;
950 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0;
951
952 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
953 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
954 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
955 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
956 }
957 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
958 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = 0x00;
959 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
960 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
961 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
962 }
963 }
964 else {/* (hperh->config.page_size) > 512 */
965 /* Send write Spare area command sequence */
966 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_AREA_A;
967 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE0;
968
969 if (((hperh->config.block_size)* (hperh->config.block_nbr)) <= 65535U) {
970 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr);
971 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr);
972 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
973 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
974 }
975 else {/* ((hperh->config.block_size)*(hperh->config.block_nbr)) > 65535 */
976 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddr);
977 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddr);
978 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddr);
979 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddr);
980 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddr);
981 }
982 }
983
984 /* Write data to memory */
985 for (; index < size; index++)
986 *(__IO uint16_t *)deviceaddr = *(uint16_t *)buf++;
987
988 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
989
990 /* Read status until NAND is ready */
991 while (ald_nand_read_status(hperh) != NAND_READY) {
992 /* Get tick */
993 tickstart = ald_get_tick();
994
995 if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT)
996 return TIMEOUT;
997 }
998
999 num++;
1000 nr--;
1001 nandaddr = (uint32_t)(nandaddr + 1U);
1002 }
1003
1004 hperh->state = ALD_NAND_STATE_READY;
1005 __UNLOCK(hperh);
1006
1007 return OK;
1008 }
1009
1016 ald_status_t ald_nand_erase_block(nand_handle_t *hperh, nand_address_t *addr)
1017 {
1018 uint32_t deviceaddr = 0;
1019 uint32_t tickstart = 0;
1020
1021 __LOCK(hperh);
1022
1023 if (hperh->state == ALD_NAND_STATE_BUSY)
1024 return BUSY;
1025
1026 /* Identify the device address */
1027 if (hperh->init.bank == EBI_NAND_BANK2)
1028 deviceaddr = NAND_DEVICE1;
1029 else
1030 deviceaddr = NAND_DEVICE2;
1031
1032 /* Update the NAND controller state */
1033 hperh->state = ALD_NAND_STATE_BUSY;
1034
1035 /* Send Erase block command sequence */
1036 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_ERASE0;
1037 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(addr, hperh));
1038 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(addr, hperh));
1039 *(__IO uint8_t *)((uint32_t)(deviceaddr | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(addr, hperh));
1040 *(__IO uint8_t *)((uint32_t)(deviceaddr | CMD_AREA)) = NAND_CMD_ERASE1;
1041
1042 /* Update the NAND controller state */
1043 hperh->state = ALD_NAND_STATE_READY;
1044 /* Get tick */
1045 tickstart = ald_get_tick();
1046
1047 /* Read status until NAND is ready */
1048 while (ald_nand_read_status(hperh) != NAND_READY) {
1049 if ((ald_get_tick() - tickstart ) > NAND_WRITE_TIMEOUT) {
1050 __UNLOCK(hperh);
1051
1052 return TIMEOUT;
1053 }
1054 }
1055
1056 __UNLOCK(hperh);
1057
1058 return OK;
1059 }
1073 void ald_nand_irq_handler(nand_handle_t *hperh)
1074 {
1075 /* Check NAND interrupt Rising edge flag */
1076 if (ald_ebi_nand_get_flag(hperh->instance, hperh->init.bank, EBI_FLAG_RISING_EDGE)) {
1077 ald_nand_irq_cbk(hperh);
1078 ald_ebi_nand_clear_flag(hperh->instance, hperh->init.bank, EBI_FLAG_RISING_EDGE);
1079 }
1080
1081 /* Check NAND interrupt Level flag */
1082 if (ald_ebi_nand_get_flag(hperh->instance, hperh->init.bank, EBI_FLAG_LEVEL)) {
1083 ald_nand_irq_cbk(hperh);
1084 ald_ebi_nand_clear_flag(hperh->instance, hperh->init.bank, EBI_FLAG_LEVEL);
1085 }
1086
1087 if (ald_ebi_nand_get_flag(hperh->instance, hperh->init.bank, EBI_FLAG_FALLING_EDGE)) {
1088 /* NAND interrupt callback*/
1089 ald_nand_irq_cbk(hperh);
1090 ald_ebi_nand_clear_flag(hperh->instance, hperh->init.bank, EBI_FLAG_FALLING_EDGE);
1091 }
1092
1093 /* Check NAND interrupt FIFO empty flag */
1094 if (ald_ebi_nand_get_flag(hperh->instance, hperh->init.bank, EBI_FLAG_FEMPT)) {
1095 ald_nand_irq_cbk(hperh);
1096 ald_ebi_nand_clear_flag(hperh->instance, hperh->init.bank, EBI_FLAG_FEMPT);
1097 }
1098 }
1099
1105 __weak void ald_nand_irq_cbk(nand_handle_t *hperh)
1106 {
1107 /* Prevent unused argument(s) compilation warning */
1108 UNUSED(hperh);
1109 }
1110
1119 uint32_t ald_nand_address_inc(nand_handle_t *hperh, nand_address_t *addr)
1120 {
1121 uint32_t status = NAND_VALID_ADDRESS;
1122
1123 addr->page++;
1124
1125 /* Check NAND address is valid */
1126 if (addr->page == hperh->config.block_size) {
1127 addr->page = 0;
1128 addr->block++;
1129
1130 if (addr->block == hperh->config.plane_size) {
1131 addr->block = 0;
1132 addr->plane++;
1133
1134 if (addr->plane == (hperh->config.plane_nbr))
1135 status = NAND_INVALID_ADDRESS;
1136 }
1137 }
1138
1139 return status;
1140 }
1141
1147 uint32_t ald_nand_read_status(nand_handle_t *hperh)
1148 {
1149 uint32_t data = 0;
1150 uint32_t addr = 0;
1151
1152 /* Identify the device address */
1153 if (hperh->init.bank == EBI_NAND_BANK2)
1154 addr = NAND_DEVICE1;
1155 else
1156 addr = NAND_DEVICE2;
1157
1158 /* Send Read status operation command */
1159 *(__IO uint8_t *)((uint32_t)(addr | CMD_AREA)) = NAND_CMD_STATUS;
1160 /* Read status register data */
1161 data = *(__IO uint8_t *)addr;
1162
1163 /* Return the status */
1164 if ((data & NAND_ERROR) == NAND_ERROR)
1165 return NAND_ERROR;
1166 else if ((data & NAND_READY) == NAND_READY)
1167 return NAND_READY;
1168
1169 return NAND_BUSY;
1170 }
1171
1177 ald_nand_state_t ald_nand_get_state(nand_handle_t *hperh)
1178 {
1179 return hperh->state;
1180 }
1181
1187 ald_status_t ald_nand_ecc_enable(nand_handle_t *hperh)
1188 {
1189 if (hperh->state == ALD_NAND_STATE_BUSY)
1190 return BUSY;
1191
1192 /* Update the NAND state */
1193 hperh->state = ALD_NAND_STATE_BUSY;
1194 /* Enable ECC feature */
1195 ald_ebi_nand_ecc_enable(hperh->instance, hperh->init.bank);
1196 /* Update the NAND state */
1197 hperh->state = ALD_NAND_STATE_READY;
1198
1199 return OK;
1200 }
1201
1207 ald_status_t ald_nand_ecc_disable(nand_handle_t *hperh)
1208 {
1209 if (hperh->state == ALD_NAND_STATE_BUSY)
1210 return BUSY;
1211
1212 /* Update the NAND state */
1213 hperh->state = ALD_NAND_STATE_BUSY;
1214 /* Disable ECC feature */
1215 ald_ebi_nand_ecc_disable(hperh->instance, hperh->init.bank);
1216 hperh->state = ALD_NAND_STATE_READY;
1217
1218 return OK;
1219 }
1220
1228 ald_status_t ald_nand_get_ecc(nand_handle_t *hperh, uint32_t *val, uint32_t timeout)
1229 {
1230 ald_status_t status = OK;
1231
1232 if (hperh->state == ALD_NAND_STATE_BUSY)
1233 return BUSY;
1234
1235 hperh->state = ALD_NAND_STATE_BUSY;
1236 status = ald_ebi_nand_get_ecc(hperh->instance, val, hperh->init.bank, timeout);
1237 hperh->state = ALD_NAND_STATE_READY;
1238
1239 return status;
1240 }
1247 #endif
1248
EBI_FLAG_FEMPT
Definition: ald_ebi.h:318
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
NAND_CMD_WRITE_TRUE1
#define NAND_CMD_WRITE_TRUE1
Definition: ald_nand.h:113
nand_id_t
NAND Memory electronic signature Structure definition.
Definition: ald_nand.h:51
NAND_WRITE_TIMEOUT
#define NAND_WRITE_TIMEOUT
Definition: ald_nand.h:105
NAND_BUSY
#define NAND_BUSY
Definition: ald_nand.h:124
ald_ebi_nand_ecc_disable
void ald_ebi_nand_ecc_disable(EBI_NAND_TypeDef *dev, uint32_t bank)
Disables dynamically EBI_NAND ECC feature.
Definition: ald_ebi.c:509
BUSY
Definition: utils.h:57
ald_nand_ecc_disable
ald_status_t ald_nand_ecc_disable(nand_handle_t *hperh)
Disables dynamically FSMC_NAND ECC feature.
Definition: ald_nand.c:1207
nand_device_cfg_t::plane_size
uint32_t plane_size
Definition: ald_nand.h:78
ald_nand_reset
ald_status_t ald_nand_reset(nand_handle_t *hperh)
NAND memory reset.
Definition: ald_nand.c:106
nand_device_cfg_t
NAND Memory info Structure definition.
Definition: ald_nand.h:71
NAND_CMD_ERASE0
#define NAND_CMD_ERASE0
Definition: ald_nand.h:114
NAND_ERROR
#define NAND_ERROR
Definition: ald_nand.h:125
nand_address_t::block
uint16_t block
Definition: ald_nand.h:65
nand_handle_t::init
ald_ebi_nand_init_t init
Definition: ald_nand.h:88
ADDR_AREA
#define ADDR_AREA
Definition: ald_nand.h:107
nand_handle_t
NAND handle Structure definition.
Definition: ald_nand.h:85
EBI_NAND_BANK2
#define EBI_NAND_BANK2
Definition: ald_ebi.h:48
nand_handle_t::state
__IO ald_nand_state_t state
Definition: ald_nand.h:90
nand_address_t::page
uint16_t page
Definition: ald_nand.h:63
nand_handle_t::instance
EBI_NAND_TypeDef * instance
Definition: ald_nand.h:87
nand_address_t::plane
uint16_t plane
Definition: ald_nand.h:64
ALD_NAND_STATE_READY
Definition: ald_nand.h:43
NAND_READY
#define NAND_READY
Definition: ald_nand.h:126
NAND_CMD_READID
#define NAND_CMD_READID
Definition: ald_nand.h:116
ald_ebi_nand_enable
void ald_ebi_nand_enable(EBI_NAND_TypeDef *dev, uint32_t bank)
Enable the NAND device access.
Definition: ald_ebi.c:413
UNLOCK
Definition: type.h:59
NAND_DEVICE2
#define NAND_DEVICE2
Definition: ald_nand.h:104
ALD_NAND_STATE_BUSY
Definition: ald_nand.h:44
nand_device_cfg_t::extra_cmd
type_func_t extra_cmd
Definition: ald_nand.h:79
ARRAY_ADDRESS
#define ARRAY_ADDRESS(x, y)
Definition: ald_nand.h:134
NAND_CMD_AREA_A
#define NAND_CMD_AREA_A
Definition: ald_nand.h:108
UNUSED
#define UNUSED(x)
Definition: type.h:76
ald_nand_write_page_8b
ald_status_t ald_nand_write_page_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
Write page(s) to NAND memory block (8-bits addressing)
Definition: ald_nand.c:318
ald_ebi_nand_init_t::width
ebi_nand_mem_bus_width_t width
Definition: ald_ebi.h:161
nand_device_cfg_t::block_size
uint32_t block_size
Definition: ald_nand.h:75
ald_nand_read_page_16b
ald_status_t ald_nand_read_page_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
Read page(s) from NAND memory block (16-bits addressing)
Definition: ald_nand.c:618
ald_nand_state_t
ald_nand_state_t
NAND State structures definition.
Definition: ald_nand.h:41
nand_handle_t::config
nand_device_cfg_t config
Definition: ald_nand.h:91
NAND_INVALID_ADDRESS
#define NAND_INVALID_ADDRESS
Definition: ald_nand.h:122
ald_nand_write_sparearea_16b
ald_status_t ald_nand_write_sparearea_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
Write spare area(s) to NAND memory (16-bits addressing)
Definition: ald_nand.c:917
ald_nand_deinit
ald_status_t ald_nand_deinit(nand_handle_t *hperh)
Perform NAND memory De-Initialization sequence.
Definition: ald_nand.c:92
COLUMN_2ND_CYCLE
#define COLUMN_2ND_CYCLE(x)
Definition: ald_nand.h:143
ald_nand_read_sparearea_8b
ald_status_t ald_nand_read_sparearea_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
Read spare area(s) from NAND memory (8-bits addressing)
Definition: ald_nand.c:414
ald_ebi_nand_comm_timing_init
void ald_ebi_nand_comm_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
Initializes the EBI_NAND Common space Timing according to the specified parameters in the EBI_NAND_Ti...
Definition: ald_ebi.c:312
ald_nand_init
ald_status_t ald_nand_init(nand_handle_t *hperh, ald_ebi_nand_timing_t *ctiming, ald_ebi_nand_timing_t *atiming)
Perform NAND memory initialization sequence.
Definition: ald_nand.c:71
ald_ebi_nand_init_t::bank
uint32_t bank
Definition: ald_ebi.h:159
ald_ebi_nand_ecc_enable
void ald_ebi_nand_ecc_enable(EBI_NAND_TypeDef *dev, uint32_t bank)
Enables dynamically EBI_NAND ECC feature.
Definition: ald_ebi.c:491
ADDR_3RD_CYCLE
#define ADDR_3RD_CYCLE(x)
Definition: ald_nand.h:140
nand_config_device
void nand_config_device(nand_handle_t *hperh, nand_device_cfg_t *pdcfg)
configure the device: Enter the physical parameters of the device
Definition: ald_nand.c:138
NAND_DEVICE1
#define NAND_DEVICE1
Definition: ald_nand.h:103
COLUMN_ADDRESS
#define COLUMN_ADDRESS(x)
Definition: ald_nand.h:137
ald_nand_get_state
ald_nand_state_t ald_nand_get_state(nand_handle_t *hperh)
return the NAND state
Definition: ald_nand.c:1177
ald_ebi_nand_init
void ald_ebi_nand_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_init_t *init)
Initializes the EBI_NAND device according to the specified control parameters in the EBI_NAND_HandleT...
Definition: ald_ebi.c:272
nand_address_t
NAND Memory address Structure definition.
Definition: ald_nand.h:61
ald_nand_erase_block
ald_status_t ald_nand_erase_block(nand_handle_t *hperh, nand_address_t *addr)
NAND memory Block erase.
Definition: ald_nand.c:1016
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
NAND_CMD_AREA_C
#define NAND_CMD_AREA_C
Definition: ald_nand.h:110
nand_device_cfg_t::spare_size
uint32_t spare_size
Definition: ald_nand.h:74
ALD_NAND_STATE_RESET
Definition: ald_nand.h:42
EBI_FLAG_FALLING_EDGE
Definition: ald_ebi.h:317
NAND_CMD_STATUS
#define NAND_CMD_STATUS
Definition: ald_nand.h:117
ADDR_2ND_CYCLE
#define ADDR_2ND_CYCLE(x)
Definition: ald_nand.h:139
EBI_NAND_MEM_BUS_WIDTH_8
Definition: ald_ebi.h:131
nand_device_cfg_t::page_size
uint32_t page_size
Definition: ald_nand.h:73
ald_ebi_nand_get_flag
flag_status_t ald_ebi_nand_get_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
Get flag status of the NAND device.
Definition: ald_ebi.c:568
ald_ebi_nand_attr_timing_init
void ald_ebi_nand_attr_timing_init(EBI_NAND_TypeDef *dev, ald_ebi_nand_timing_t *timing, uint32_t bank)
Initializes the EBI_NAND Attribute space Timing according to the specified parameters in the EBI_NAND...
Definition: ald_ebi.c:344
nand_device_cfg_t::plane_nbr
uint32_t plane_nbr
Definition: ald_nand.h:77
ald_ebi_nand_clear_flag
void ald_ebi_nand_clear_flag(EBI_NAND_TypeDef *dev, uint32_t bank, ebi_flag_t flag)
Clear flag status of the NAND device.
Definition: ald_ebi.c:596
ald_ebi_nand_get_ecc
ald_status_t ald_ebi_nand_get_ecc(EBI_NAND_TypeDef *dev, uint32_t *val, uint32_t bank, uint32_t timeout)
Disables dynamically EBI_NAND ECC feature.
Definition: ald_ebi.c:529
ald_ebi_nand_deinit
void ald_ebi_nand_deinit(EBI_NAND_TypeDef *dev, uint32_t bank)
DeInitializes the EBI_NAND device.
Definition: ald_ebi.c:374
ald_nand_read_sparearea_16b
ald_status_t ald_nand_read_sparearea_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
Read spare area(s) from NAND memory (16-bits addressing)
Definition: ald_nand.c:811
NAND_CMD_WRITE0
#define NAND_CMD_WRITE0
Definition: ald_nand.h:112
ald_nand_irq_cbk
__weak void ald_nand_irq_cbk(nand_handle_t *hperh)
NAND interrupt feature callback.
Definition: ald_nand.c:1105
nand_handle_t::lock
lock_state_t lock
Definition: ald_nand.h:89
ald_ebi_nand_timing_t
EBI NAND Timing parameters structure definition.
Definition: ald_ebi.h:171
ald_nand_read_id
ald_status_t ald_nand_read_id(nand_handle_t *hperh, nand_id_t *id)
Read the NAND memory electronic signature.
Definition: ald_nand.c:161
ald_nand_irq_handler
void ald_nand_irq_handler(nand_handle_t *hperh)
This function handles NAND device interrupt request.
Definition: ald_nand.c:1073
EBI_FLAG_LEVEL
Definition: ald_ebi.h:316
ald_nand_read_status
uint32_t ald_nand_read_status(nand_handle_t *hperh)
NAND memory read status.
Definition: ald_nand.c:1147
COLUMN_1ST_CYCLE
#define COLUMN_1ST_CYCLE(x)
Definition: ald_nand.h:142
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
CMD_AREA
#define CMD_AREA
Definition: ald_nand.h:106
NAND_CMD_ERASE1
#define NAND_CMD_ERASE1
Definition: ald_nand.h:115
EBI_FLAG_RISING_EDGE
Definition: ald_ebi.h:315
ald_nand_ecc_enable
ald_status_t ald_nand_ecc_enable(nand_handle_t *hperh)
Enables dynamically NAND ECC feature.
Definition: ald_nand.c:1187
ADDR_1ST_CYCLE
#define ADDR_1ST_CYCLE(x)
Definition: ald_nand.h:138
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ald_nand_address_inc
uint32_t ald_nand_address_inc(nand_handle_t *hperh, nand_address_t *addr)
Increment the NAND memory address.
Definition: ald_nand.c:1119
ERROR
Definition: utils.h:56
ADDR_4TH_CYCLE
#define ADDR_4TH_CYCLE(x)
Definition: ald_nand.h:141
ald_nand_read_page_8b
ald_status_t ald_nand_read_page_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
Read page(s) from NAND memory block (8-bits addressing)
Definition: ald_nand.c:217
ald_nand_write_sparearea_8b
ald_status_t ald_nand_write_sparearea_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
Write spare area(s) to NAND memory (8-bits addressing)
Definition: ald_nand.c:519
ald_nand_get_ecc
ald_status_t ald_nand_get_ecc(nand_handle_t *hperh, uint32_t *val, uint32_t timeout)
Disables dynamically NAND ECC feature.
Definition: ald_nand.c:1228
NAND_VALID_ADDRESS
#define NAND_VALID_ADDRESS
Definition: ald_nand.h:121
ald_nand.h
Header file of EBI_NAND module driver.
ald_nand_write_page_16b
ald_status_t ald_nand_write_page_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
Write page(s) to NAND memory block (16-bits addressing)
Definition: ald_nand.c:715
nand_device_cfg_t::block_nbr
uint32_t block_nbr
Definition: ald_nand.h:76
NAND_CMD_AREA_TRUE1
#define NAND_CMD_AREA_TRUE1
Definition: ald_nand.h:111


ALD User Manual: D:/svn/src/ald_nand.h Source File

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  • svn
  • src
ald_nand.h
Go to the documentation of this file.
1
17 #ifndef __ALD_NAND_H_
18 #define __ALD_NAND_H_
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "ald_ebi.h"
25
41 typedef enum {
42 ALD_NAND_STATE_RESET = 0x00U,
43 ALD_NAND_STATE_READY = 0x01U,
44 ALD_NAND_STATE_BUSY = 0x02U,
45 ALD_NAND_STATE_ERROR = 0x03U
46 } ald_nand_state_t;
47
51 typedef struct {
52 uint8_t maker_id;
53 uint8_t device_id;
54 uint8_t third_id;
55 uint8_t fourth_id;
56 } nand_id_t;
57
61 typedef struct
62 {
63 uint16_t page;
64 uint16_t plane;
65 uint16_t block;
66 } nand_address_t;
67
71 typedef struct
72 {
73 uint32_t page_size;
74 uint32_t spare_size;
75 uint32_t block_size;
76 uint32_t block_nbr;
77 uint32_t plane_nbr;
78 uint32_t plane_size;
79 type_func_t extra_cmd;
80 } nand_device_cfg_t;
81
85 typedef struct
86 {
87 EBI_NAND_TypeDef *instance;
88 ald_ebi_nand_init_t init;
89 lock_state_t lock;
90 __IO ald_nand_state_t state;
91 nand_device_cfg_t config;
92 } nand_handle_t;
93
103 #define NAND_DEVICE1 EBI_BANK2
104 #define NAND_DEVICE2 EBI_BANK3
105 #define NAND_WRITE_TIMEOUT 1000U
106 #define CMD_AREA (1U<<16U) /* A16 = CLE high */
107 #define ADDR_AREA (1U<<17U) /* A17 = ALE high */
108 #define NAND_CMD_AREA_A ((uint8_t)0x00U)
109 #define NAND_CMD_AREA_B ((uint8_t)0x01U)
110 #define NAND_CMD_AREA_C ((uint8_t)0x50U)
111 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
112 #define NAND_CMD_WRITE0 ((uint8_t)0x80U)
113 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
114 #define NAND_CMD_ERASE0 ((uint8_t)0x60U)
115 #define NAND_CMD_ERASE1 ((uint8_t)0xD0U)
116 #define NAND_CMD_READID ((uint8_t)0x90U)
117 #define NAND_CMD_STATUS ((uint8_t)0x70U)
118 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
119 #define NAND_CMD_RESET ((uint8_t)0xFFU)
120 /* NAND memory status */
121 #define NAND_VALID_ADDRESS 0x00000100U
122 #define NAND_INVALID_ADDRESS 0x00000200U
123 #define NAND_TIMEOUT_ERROR 0x00000400U
124 #define NAND_BUSY 0x00000000U
125 #define NAND_ERROR 0x00000001U
126 #define NAND_READY 0x00000040U
127
134 #define ARRAY_ADDRESS(x , y) ((x)->page + \
135 (((x)->block + (((x)->plane) * \
136 ((y)->config.plane_size))) * ((y)->config.block_size)))
137 #define COLUMN_ADDRESS( x) ((x)->config.page_size)
138 #define ADDR_1ST_CYCLE(x) (uint8_t)(x) /* 1st addressing cycle */
139 #define ADDR_2ND_CYCLE(x) (uint8_t)((x) >> 8U) /* 2nd addressing cycle */
140 #define ADDR_3RD_CYCLE(x) (uint8_t)((x) >> 16U) /* 3rd addressing cycle */
141 #define ADDR_4TH_CYCLE(x) (uint8_t)((x) >> 24U) /* 4th addressing cycle */
142 #define COLUMN_1ST_CYCLE(x) (uint8_t)(x) /* 1st Column addressing cycle */
143 #define COLUMN_2ND_CYCLE(x) (uint8_t)((x) >> 8U) /* 2nd Column addressing cycle */
144
154 /* Initialization/de-initialization functions */
155 ald_status_t ald_nand_init(nand_handle_t *hperh, ald_ebi_nand_timing_t *ctiming, ald_ebi_nand_timing_t *atiming);
156 ald_status_t ald_nand_deinit(nand_handle_t *hperh);
157 ald_status_t ald_nand_reset(nand_handle_t *hperh);
158 void nand_config_device(nand_handle_t *hperh, nand_device_cfg_t *pdcfg);
165 /* IO operation functions */
166 ald_status_t ald_nand_read_id(nand_handle_t *hperh, nand_id_t *id);
167 ald_status_t ald_nand_read_page_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr);
168 ald_status_t ald_nand_write_page_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr);
169 ald_status_t ald_nand_read_sparearea_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr);
170 ald_status_t ald_nand_write_sparearea_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr);
171 ald_status_t ald_nand_read_page_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr);
172 ald_status_t ald_nand_write_page_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr);
173 ald_status_t ald_nand_read_sparearea_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr);
174 ald_status_t ald_nand_write_sparearea_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr);
175 ald_status_t ald_nand_erase_block(nand_handle_t *hperh, nand_address_t *addr);
182 /* NAND Control functions */
183 void ald_nand_irq_handler(nand_handle_t *hperh);
184 void ald_nand_irq_cbk(nand_handle_t *hperh);
185 uint32_t ald_nand_address_inc(nand_handle_t *hperh, nand_address_t *addr);
186 uint32_t ald_nand_read_status(nand_handle_t *hperh);
187 ald_nand_state_t ald_nand_get_state(nand_handle_t *hperh);
188 ald_status_t ald_nand_ecc_enable(nand_handle_t *hperh);
189 ald_status_t ald_nand_ecc_disable(nand_handle_t *hperh);
190 ald_status_t ald_nand_get_ecc(nand_handle_t *hperh, uint32_t *val, uint32_t timeout);
203 #ifdef __cplusplus
204 }
205 #endif
206 #endif
nand_id_t
NAND Memory electronic signature Structure definition.
Definition: ald_nand.h:51
nand_id_t::third_id
uint8_t third_id
Definition: ald_nand.h:54
ald_nand_ecc_disable
ald_status_t ald_nand_ecc_disable(nand_handle_t *hperh)
Disables dynamically FSMC_NAND ECC feature.
Definition: ald_nand.c:1207
nand_device_cfg_t::plane_size
uint32_t plane_size
Definition: ald_nand.h:78
nand_id_t::fourth_id
uint8_t fourth_id
Definition: ald_nand.h:55
ald_nand_reset
ald_status_t ald_nand_reset(nand_handle_t *hperh)
NAND memory reset.
Definition: ald_nand.c:106
nand_device_cfg_t
NAND Memory info Structure definition.
Definition: ald_nand.h:71
type_func_t
type_func_t
Definition: type.h:47
nand_address_t::block
uint16_t block
Definition: ald_nand.h:65
nand_handle_t::init
ald_ebi_nand_init_t init
Definition: ald_nand.h:88
nand_handle_t
NAND handle Structure definition.
Definition: ald_nand.h:85
nand_handle_t::state
__IO ald_nand_state_t state
Definition: ald_nand.h:90
nand_address_t::page
uint16_t page
Definition: ald_nand.h:63
nand_handle_t::instance
EBI_NAND_TypeDef * instance
Definition: ald_nand.h:87
nand_address_t::plane
uint16_t plane
Definition: ald_nand.h:64
ALD_NAND_STATE_READY
Definition: ald_nand.h:43
nand_id_t::device_id
uint8_t device_id
Definition: ald_nand.h:53
ALD_NAND_STATE_BUSY
Definition: ald_nand.h:44
nand_device_cfg_t::extra_cmd
type_func_t extra_cmd
Definition: ald_nand.h:79
ald_nand_write_page_8b
ald_status_t ald_nand_write_page_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
Write page(s) to NAND memory block (8-bits addressing)
Definition: ald_nand.c:318
nand_device_cfg_t::block_size
uint32_t block_size
Definition: ald_nand.h:75
ald_nand_read_page_16b
ald_status_t ald_nand_read_page_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
Read page(s) from NAND memory block (16-bits addressing)
Definition: ald_nand.c:618
ald_nand_state_t
ald_nand_state_t
NAND State structures definition.
Definition: ald_nand.h:41
nand_handle_t::config
nand_device_cfg_t config
Definition: ald_nand.h:91
ald_nand_write_sparearea_16b
ald_status_t ald_nand_write_sparearea_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
Write spare area(s) to NAND memory (16-bits addressing)
Definition: ald_nand.c:917
nand_id_t::maker_id
uint8_t maker_id
Definition: ald_nand.h:52
ald_nand_deinit
ald_status_t ald_nand_deinit(nand_handle_t *hperh)
Perform NAND memory De-Initialization sequence.
Definition: ald_nand.c:92
ald_nand_read_sparearea_8b
ald_status_t ald_nand_read_sparearea_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
Read spare area(s) from NAND memory (8-bits addressing)
Definition: ald_nand.c:414
ald_nand_init
ald_status_t ald_nand_init(nand_handle_t *hperh, ald_ebi_nand_timing_t *ctiming, ald_ebi_nand_timing_t *atiming)
Perform NAND memory initialization sequence.
Definition: ald_nand.c:71
lock_state_t
lock_state_t
Definition: type.h:58
ald_ebi_nand_init_t
EBI NAND Configuration Structure definition.
Definition: ald_ebi.h:158
EBI_NAND_TypeDef
#define EBI_NAND_TypeDef
Definition: ald_ebi.h:42
nand_config_device
void nand_config_device(nand_handle_t *hperh, nand_device_cfg_t *pdcfg)
configure the device: Enter the physical parameters of the device
Definition: ald_nand.c:138
ALD_NAND_STATE_ERROR
Definition: ald_nand.h:45
ald_nand_get_state
ald_nand_state_t ald_nand_get_state(nand_handle_t *hperh)
return the NAND state
Definition: ald_nand.c:1177
nand_address_t
NAND Memory address Structure definition.
Definition: ald_nand.h:61
ald_nand_erase_block
ald_status_t ald_nand_erase_block(nand_handle_t *hperh, nand_address_t *addr)
NAND memory Block erase.
Definition: ald_nand.c:1016
nand_device_cfg_t::spare_size
uint32_t spare_size
Definition: ald_nand.h:74
ALD_NAND_STATE_RESET
Definition: ald_nand.h:42
nand_device_cfg_t::page_size
uint32_t page_size
Definition: ald_nand.h:73
nand_device_cfg_t::plane_nbr
uint32_t plane_nbr
Definition: ald_nand.h:77
ald_nand_read_sparearea_16b
ald_status_t ald_nand_read_sparearea_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
Read spare area(s) from NAND memory (16-bits addressing)
Definition: ald_nand.c:811
ald_nand_irq_cbk
__weak void ald_nand_irq_cbk(nand_handle_t *hperh)
NAND interrupt feature callback.
Definition: ald_nand.c:1105
nand_handle_t::lock
lock_state_t lock
Definition: ald_nand.h:89
ald_ebi_nand_timing_t
EBI NAND Timing parameters structure definition.
Definition: ald_ebi.h:171
ald_ebi.h
Header file of EBI module driver.
ald_nand_read_id
ald_status_t ald_nand_read_id(nand_handle_t *hperh, nand_id_t *id)
Read the NAND memory electronic signature.
Definition: ald_nand.c:161
ald_nand_irq_handler
void ald_nand_irq_handler(nand_handle_t *hperh)
This function handles NAND device interrupt request.
Definition: ald_nand.c:1073
ald_nand_read_status
uint32_t ald_nand_read_status(nand_handle_t *hperh)
NAND memory read status.
Definition: ald_nand.c:1147
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
ald_nand_ecc_enable
ald_status_t ald_nand_ecc_enable(nand_handle_t *hperh)
Enables dynamically NAND ECC feature.
Definition: ald_nand.c:1187
ald_nand_address_inc
uint32_t ald_nand_address_inc(nand_handle_t *hperh, nand_address_t *addr)
Increment the NAND memory address.
Definition: ald_nand.c:1119
ald_nand_read_page_8b
ald_status_t ald_nand_read_page_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
Read page(s) from NAND memory block (8-bits addressing)
Definition: ald_nand.c:217
ald_nand_write_sparearea_8b
ald_status_t ald_nand_write_sparearea_8b(nand_handle_t *hperh, nand_address_t *addr, uint8_t *buf, uint32_t nr)
Write spare area(s) to NAND memory (8-bits addressing)
Definition: ald_nand.c:519
ald_nand_get_ecc
ald_status_t ald_nand_get_ecc(nand_handle_t *hperh, uint32_t *val, uint32_t timeout)
Disables dynamically NAND ECC feature.
Definition: ald_nand.c:1228
ald_nand_write_page_16b
ald_status_t ald_nand_write_page_16b(nand_handle_t *hperh, nand_address_t *addr, uint16_t *buf, uint32_t nr)
Write page(s) to NAND memory block (16-bits addressing)
Definition: ald_nand.c:715
nand_device_cfg_t::block_nbr
uint32_t block_nbr
Definition: ald_nand.h:76


ALD User Manual: D:/svn/src/ald_nor_lcd.c Source File

  • D:
  • svn
  • src
ald_nor_lcd.c
Go to the documentation of this file.
1
17 #include "ald_nor_lcd.h"
18
19
28 #ifdef ALD_NOR
29
33 static uint32_t NORMEMDATWIDTH = NOR_MEMORY_8B;
53 ald_status_t ald_nor_init(nor_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing)
54 {
55 if (hperh == NULL)
56 return ERROR;
57 if (hperh->state == ALD_NOR_STATE_RESET)
58 hperh->lock = UNLOCK;
59
60 /* Initialize NOR control Interface */
61 ald_ebi_nor_sram_init(hperh->instance, &(hperh->init));
62 /* Initialize NOR timing Interface */
63 ald_ebi_nor_sram_timing_init(hperh->instance, timing, hperh->init.bank);
64 /* Initialize NOR extended mode timing Interface */
65 ald_ebi_nor_sram_ext_timing_init(hperh->ext, ext_timing, hperh->init.bank, hperh->init.ext_mode);
66 /* Enable the NORSRAM device */
67 ald_ebi_nor_sram_enable(hperh->instance, hperh->init.bank);
68
69 /* Initialize NOR Memory Data Width*/
70 if (hperh->init.width == EBI_NORSRAM_MEM_BUS_WIDTH_8)
71 NORMEMDATWIDTH = NOR_MEMORY_8B;
72 else
73 NORMEMDATWIDTH = NOR_MEMORY_16B;
74
75 hperh->state = ALD_NOR_STATE_READY;
76 return OK;
77 }
78
84 ald_status_t ald_nor_deinit(nor_handle_t *hperh)
85 {
86 ald_ebi_nor_sram_deinit(hperh->instance, hperh->ext, hperh->init.bank);
87 hperh->state = ALD_NOR_STATE_RESET;
88 __UNLOCK(hperh);
89
90 return OK;
91 }
106 ald_status_t ald_nor_read_id(nor_handle_t *hperh, nor_id_t *id)
107 {
108 uint32_t devaddr = 0;
109
110 __LOCK(hperh);
111
112 if (hperh->state == ALD_NOR_STATE_BUSY)
113 return BUSY;
114
115 /* Select the NOR device address */
116 if (hperh->init.bank == EBI_NORSRAM_BANK1)
117 devaddr = NOR_MEMORY_ADRESS1;
118 else if (hperh->init.bank == EBI_NORSRAM_BANK2)
119 devaddr = NOR_MEMORY_ADRESS2;
120 else if (hperh->init.bank == EBI_NORSRAM_BANK3)
121 devaddr = NOR_MEMORY_ADRESS3;
122 else
123 devaddr = NOR_MEMORY_ADRESS4;
124
125 hperh->state = ALD_NOR_STATE_BUSY;
126
127 /* Send read ID command */
128 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
129 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
130 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
131
132 /* Read the NOR IDs */
133 id->m_code = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, MC_ADDRESS);
134 id->device_code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, DEVICE_CODE1_ADDR);
135 id->device_code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, DEVICE_CODE2_ADDR);
136 id->device_code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, DEVICE_CODE3_ADDR);
137
138 hperh->state = ALD_NOR_STATE_READY;
139 __UNLOCK(hperh);
140
141 return OK;
142 }
143
149 ald_status_t ald_nor_return_readmode(nor_handle_t *hperh)
150 {
151 uint32_t devaddr = 0;
152
153 __LOCK(hperh);
154
155 if (hperh->state == ALD_NOR_STATE_BUSY)
156 return BUSY;
157
158 /* Select the NOR device address */
159 if (hperh->init.bank == EBI_NORSRAM_BANK1)
160 devaddr = NOR_MEMORY_ADRESS1;
161 else if (hperh->init.bank == EBI_NORSRAM_BANK2)
162 devaddr = NOR_MEMORY_ADRESS2;
163 else if (hperh->init.bank == EBI_NORSRAM_BANK3)
164 devaddr = NOR_MEMORY_ADRESS3;
165 else
166 devaddr = NOR_MEMORY_ADRESS4;
167
168 NOR_WRITE(devaddr, NOR_CMD_DATA_READ_RESET);
169 hperh->state = ALD_NOR_STATE_READY;
170 __UNLOCK(hperh);
171
172 return OK;
173 }
174
182 ald_status_t ald_nor_read(nor_handle_t *hperh, uint32_t *addr, uint16_t *data)
183 {
184 uint32_t devaddr = 0;
185
186 __LOCK(hperh);
187
188 if (hperh->state == ALD_NOR_STATE_BUSY)
189 return BUSY;
190
191 if (hperh->init.bank == EBI_NORSRAM_BANK1)
192 devaddr = NOR_MEMORY_ADRESS1;
193 else if (hperh->init.bank == EBI_NORSRAM_BANK2)
194 devaddr = NOR_MEMORY_ADRESS2;
195 else if (hperh->init.bank == EBI_NORSRAM_BANK3)
196 devaddr = NOR_MEMORY_ADRESS3;
197 else
198 devaddr = NOR_MEMORY_ADRESS4;
199
200 hperh->state = ALD_NOR_STATE_BUSY;
201
202 /* Send read data command */
203 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
204 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
205 NOR_WRITE((uint32_t)addr, NOR_CMD_DATA_READ_RESET);
206
207 *data = *(__IO uint32_t *)(uint32_t)addr;
208 hperh->state = ALD_NOR_STATE_READY;
209 __UNLOCK(hperh);
210
211 return OK;
212 }
213
221 ald_status_t ald_nor_program(nor_handle_t *hperh, uint32_t *addr, uint16_t *data)
222 {
223 uint32_t devaddr = 0;
224
225 __LOCK(hperh);
226
227 if (hperh->state == ALD_NOR_STATE_BUSY)
228 return BUSY;
229
230 /* Select the NOR device address */
231 if (hperh->init.bank == EBI_NORSRAM_BANK1)
232 devaddr = NOR_MEMORY_ADRESS1;
233 else if (hperh->init.bank == EBI_NORSRAM_BANK2)
234 devaddr = NOR_MEMORY_ADRESS2;
235 else if (hperh->init.bank == EBI_NORSRAM_BANK3)
236 devaddr = NOR_MEMORY_ADRESS3;
237 else /* EBI_NORSRAM_BANK4 */
238 devaddr = NOR_MEMORY_ADRESS4;
239
240 hperh->state = ALD_NOR_STATE_BUSY;
241
242 /* Send program data command */
243 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
244 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
245 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
246
247 /* Write the data */
248 NOR_WRITE(addr, *data);
249 hperh->state = ALD_NOR_STATE_READY;
250 __UNLOCK(hperh);
251
252 return OK;
253 }
254
264 ald_status_t ald_nor_read_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size)
265 {
266 uint32_t devaddr = 0;
267
268 /* Process Locked */
269 __LOCK(hperh);
270
271 if (hperh->state == ALD_NOR_STATE_BUSY)
272 return BUSY;
273
274 if (hperh->init.bank == EBI_NORSRAM_BANK1)
275 devaddr = NOR_MEMORY_ADRESS1;
276 else if (hperh->init.bank == EBI_NORSRAM_BANK2)
277 devaddr = NOR_MEMORY_ADRESS2;
278 else if (hperh->init.bank == EBI_NORSRAM_BANK3)
279 devaddr = NOR_MEMORY_ADRESS3;
280 else
281 devaddr = NOR_MEMORY_ADRESS4;
282
283 hperh->state = ALD_NOR_STATE_BUSY;
284
285 /* Send read data command */
286 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
287 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
288 NOR_WRITE(addr, NOR_CMD_DATA_READ_RESET);
289
290 /* Read buffer */
291 while (size > 0) {
292 *data++ = *(__IO uint16_t *)addr;
293 addr += 2U;
294 size--;
295 }
296
297 hperh->state = ALD_NOR_STATE_READY;
298 __UNLOCK(hperh);
299
300 return OK;
301 }
302
311 ald_status_t ald_nor_program_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size)
312 {
313 uint16_t * p_currentaddr = (uint16_t *)NULL;
314 uint16_t * p_endaddr = (uint16_t *)NULL;
315 uint32_t lastloadedaddr = 0, devaddr = 0;
316
317 __LOCK(hperh);
318
319 if (hperh->state == ALD_NOR_STATE_BUSY)
320 return BUSY;
321
322 if (hperh->init.bank == EBI_NORSRAM_BANK1)
323 devaddr = NOR_MEMORY_ADRESS1;
324 else if (hperh->init.bank == EBI_NORSRAM_BANK2)
325 devaddr = NOR_MEMORY_ADRESS2;
326 else if (hperh->init.bank == EBI_NORSRAM_BANK3)
327 devaddr = NOR_MEMORY_ADRESS3;
328 else
329 devaddr = NOR_MEMORY_ADRESS4;
330
331 hperh->state = ALD_NOR_STATE_BUSY;
332
333 /* Initialize variables */
334 p_currentaddr = (uint16_t*)((uint32_t)(addr));
335 p_endaddr = p_currentaddr + (size - 1U);
336 lastloadedaddr = (uint32_t)(addr);
337
338 /* Issue unlock command sequence */
339 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
340 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
341 /* Write Buffer Load Command */
342 NOR_WRITE((uint32_t)(p_currentaddr), NOR_CMD_DATA_BUFFER_AND_PROG);
343 NOR_WRITE((uint32_t)(p_currentaddr), (size - 1U));
344
345 /* Load Data into NOR Buffer */
346 while (p_currentaddr <= p_endaddr) {
347 lastloadedaddr = (uint32_t)p_currentaddr;
348 NOR_WRITE(p_currentaddr, *data++);
349 p_currentaddr++;
350 }
351
352 NOR_WRITE((uint32_t)(lastloadedaddr), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
353 hperh->state = ALD_NOR_STATE_READY;
354 __UNLOCK(hperh);
355
356 return OK;
357 }
358
366 ald_status_t ald_nor_erase_block(nor_handle_t *hperh, uint32_t blkaddr, uint32_t addr)
367 {
368 uint32_t devaddr = 0;
369
370 __LOCK(hperh);
371
372 if (hperh->state == ALD_NOR_STATE_BUSY)
373 return BUSY;
374
375 if (hperh->init.bank == EBI_NORSRAM_BANK1)
376 devaddr = NOR_MEMORY_ADRESS1;
377 else if (hperh->init.bank == EBI_NORSRAM_BANK2)
378 devaddr = NOR_MEMORY_ADRESS2;
379 else if (hperh->init.bank == EBI_NORSRAM_BANK3)
380 devaddr = NOR_MEMORY_ADRESS3;
381 else
382 devaddr = NOR_MEMORY_ADRESS4;
383
384 hperh->state = ALD_NOR_STATE_BUSY;
385
386 /* Send block erase command sequence */
387 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
388 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
389 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
390 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
391 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
392 NOR_WRITE((uint32_t)(blkaddr + addr), NOR_CMD_DATA_BLOCK_ERASE);
393
394 hperh->state = ALD_NOR_STATE_READY;
395 __UNLOCK(hperh);
396
397 return OK;
398
399 }
400
406 ald_status_t ald_nor_erase_chip(nor_handle_t *hperh)
407 {
408 uint32_t devaddr = 0;
409
410 __LOCK(hperh);
411
412 if (hperh->state == ALD_NOR_STATE_BUSY)
413 return BUSY;
414
415 /* Select the NOR device address */
416 if (hperh->init.bank == EBI_NORSRAM_BANK1)
417 devaddr = NOR_MEMORY_ADRESS1;
418 else if (hperh->init.bank == EBI_NORSRAM_BANK2)
419 devaddr = NOR_MEMORY_ADRESS2;
420 else if (hperh->init.bank == EBI_NORSRAM_BANK3)
421 devaddr = NOR_MEMORY_ADRESS3;
422 else
423 devaddr = NOR_MEMORY_ADRESS4;
424
425 hperh->state = ALD_NOR_STATE_BUSY;
426
427 /* Send NOR chip erase command sequence */
428 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
429 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
430 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
431 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
432 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
433 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
434
435 hperh->state = ALD_NOR_STATE_READY;
436 __UNLOCK(hperh);
437
438 return OK;
439 }
440
447 ald_status_t ald_nor_read_cfi(nor_handle_t *hperh, nor_cfi_t *cfi)
448 {
449 uint32_t devaddr = 0;
450
451 __LOCK(hperh);
452
453 if (hperh->state == ALD_NOR_STATE_BUSY)
454 return BUSY;
455
456 /* Select the NOR device address */
457 if (hperh->init.bank == EBI_NORSRAM_BANK1)
458 devaddr = NOR_MEMORY_ADRESS1;
459 else if (hperh->init.bank == EBI_NORSRAM_BANK2)
460 devaddr = NOR_MEMORY_ADRESS2;
461 else if (hperh->init.bank == EBI_NORSRAM_BANK3)
462 devaddr = NOR_MEMORY_ADRESS3;
463 else
464 devaddr = NOR_MEMORY_ADRESS4;
465
466 hperh->state = ALD_NOR_STATE_BUSY;
467 NOR_WRITE(NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
468
469 cfi->cfi_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI1_ADDRESS);
470 cfi->cfi_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI2_ADDRESS);
471 cfi->cfi_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI3_ADDRESS);
472 cfi->cfi_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(devaddr, NORMEMDATWIDTH, CFI4_ADDRESS);
473
474 hperh->state = ALD_NOR_STATE_READY;
475 __UNLOCK(hperh);
476
477 return OK;
478 }
492 ald_status_t ald_nor_write_enable(nor_handle_t *hperh)
493 {
494 __LOCK(hperh);
495 /* Enable write operation */
496 ald_ebi_nor_sram_write_enable(hperh->instance, hperh->init.bank);
497 hperh->state = ALD_NOR_STATE_READY;
498 __UNLOCK(hperh);
499
500 return OK;
501 }
502
508 ald_status_t ald_nor_write_disable(nor_handle_t *hperh)
509 {
510 __LOCK(hperh);
511 hperh->state = ALD_NOR_STATE_BUSY;
512 /* Disable write operation */
513 ald_ebi_nor_sram_write_disable(hperh->instance, hperh->init.bank);
514 hperh->state = ALD_NOR_STATE_PROTECTED;
515 __UNLOCK(hperh);
516
517 return OK;
518 }
532 ald_nor_state_t ald_nor_get_state(nor_handle_t *hperh)
533 {
534 return hperh->state;
535 }
536
544 nor_status_t ald_nor_get_status(nor_handle_t *hperh, uint32_t addr, uint32_t timeout)
545 {
546 nor_status_t status = ALD_NOR_STATUS_ONGOING;
547 uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
548 uint32_t tickstart = 0;
549
550 /* Get tick */
551 tickstart = ald_get_tick();
552 while ((status != ALD_NOR_STATUS_SUCCESS) && (status != ALD_NOR_STATUS_TIMEOUT)) {
553 /* Check for the Timeout */
554 if (timeout != ALD_MAX_DELAY) {
555 if ((timeout == 0) || ((ald_get_tick() - tickstart ) > timeout))
556 status = ALD_NOR_STATUS_TIMEOUT;
557 }
558
559 /* Read NOR status register (DQ6 and DQ5) */
560 tmp_sr1 = *(__IO uint16_t *)addr;
561 tmp_sr2 = *(__IO uint16_t *)addr;
562
563 /* If DQ6 did not toggle between the two reads then return NOR_Success */
564 if ((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
565 return ALD_NOR_STATUS_SUCCESS;
566
567 if ((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
568 status = ALD_NOR_STATUS_ONGOING;
569
570 tmp_sr1 = *(__IO uint16_t *)addr;
571 tmp_sr2 = *(__IO uint16_t *)addr;
572
573 /* If DQ6 did not toggle between the two reads then return NOR_Success */
574 if ((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
575 return ALD_NOR_STATUS_SUCCESS;
576 else if ((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
577 return ALD_NOR_STATUS_ERROR;
578 }
579
580 return status;
581 }
588 #endif
589
ALD_NOR_STATE_PROTECTED
Definition: ald_nor_lcd.h:114
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH
#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH
Definition: ald_nor_lcd.h:79
NOR_CMD_DATA_AUTO_SELECT
#define NOR_CMD_DATA_AUTO_SELECT
Definition: ald_nor_lcd.h:75
NOR_CMD_ADDRESS_SIXTH
#define NOR_CMD_ADDRESS_SIXTH
Definition: ald_nor_lcd.h:70
ALD_NOR_STATE_READY
Definition: ald_nor_lcd.h:111
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
nor_cfi_t::cfi_2
uint16_t cfi_2
Definition: ald_nor_lcd.h:142
nor_cfi_t
EBI NOR CFI typedef.
Definition: ald_nor_lcd.h:140
NOR_MEMORY_ADRESS1
#define NOR_MEMORY_ADRESS1
Definition: ald_nor_lcd.h:59
BUSY
Definition: utils.h:57
DEVICE_CODE3_ADDR
#define DEVICE_CODE3_ADDR
Definition: ald_nor_lcd.h:43
ald_nor_read_cfi
ald_status_t ald_nor_read_cfi(nor_handle_t *hperh, nor_cfi_t *cfi)
Read NOR flash CFI IDs.
Definition: ald_nor_lcd.c:447
ALD_NOR_STATE_BUSY
Definition: ald_nor_lcd.h:112
ALD_MAX_DELAY
#define ALD_MAX_DELAY
Definition: utils.h:88
ald_nor_program_buffer
ald_status_t ald_nor_program_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size)
Writes a half-word buffer to the EBI NOR memory.
Definition: ald_nor_lcd.c:311
ald_nor_read_id
ald_status_t ald_nor_read_id(nor_handle_t *hperh, nor_id_t *id)
Read NOR flash IDs.
Definition: ald_nor_lcd.c:106
EBI_NORSRAM_BANK2
Definition: ald_ebi.h:191
ald_ebi_nor_sram_deinit
ald_status_t ald_ebi_nor_sram_deinit(EBI_NOR_SRAM_TypeDef *dev, EBI_NOR_SRAM_EXTENDED_TypeDef *e_dev, uint32_t bank)
DeInitialize the EBI_NOR_SRAM peripheral.
Definition: ald_ebi.c:172
NOR_CMD_DATA_CFI
#define NOR_CMD_DATA_CFI
Definition: ald_nor_lcd.h:81
NOR_CMD_ADDRESS_FIFTH
#define NOR_CMD_ADDRESS_FIFTH
Definition: ald_nor_lcd.h:69
ald_nor_get_state
ald_nor_state_t ald_nor_get_state(nor_handle_t *hperh)
return the NOR controller state
Definition: ald_nor_lcd.c:532
NOR_MEMORY_ADRESS3
#define NOR_MEMORY_ADRESS3
Definition: ald_nor_lcd.h:61
ald_nor_state_t
ald_nor_state_t
ALD SRAM State structures definition.
Definition: ald_nor_lcd.h:109
NOR_CMD_DATA_READ_RESET
#define NOR_CMD_DATA_READ_RESET
Definition: ald_nor_lcd.h:72
NOR_CMD_ADDRESS_SECOND
#define NOR_CMD_ADDRESS_SECOND
Definition: ald_nor_lcd.h:66
UNLOCK
Definition: type.h:59
ALD_NOR_STATUS_TIMEOUT
Definition: ald_nor_lcd.h:124
EBI_NORSRAM_BANK3
Definition: ald_ebi.h:192
ald_nor_program
ald_status_t ald_nor_program(nor_handle_t *hperh, uint32_t *addr, uint16_t *data)
Program data to NOR memory.
Definition: ald_nor_lcd.c:221
ald_ebi_nor_sram_init_t::ext_mode
ebi_extended_mode_t ext_mode
Definition: ald_ebi.h:409
ALD_NOR_STATUS_ONGOING
Definition: ald_nor_lcd.h:122
ald_nor_get_status
nor_status_t ald_nor_get_status(nor_handle_t *hperh, uint32_t addr, uint32_t timeout)
Returns the NOR operation status.
Definition: ald_nor_lcd.c:544
NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM
#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM
Definition: ald_nor_lcd.h:83
ald_ebi_nor_sram_write_enable
void ald_ebi_nor_sram_write_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Enables dynamically NOR-FLASH/SRAM write operation.
Definition: ald_ebi.c:234
NOR_CMD_ADDRESS_FIRST
#define NOR_CMD_ADDRESS_FIRST
Definition: ald_nor_lcd.h:64
ald_nor_deinit
ald_status_t ald_nor_deinit(nor_handle_t *hperh)
Perform NOR memory De-Initialization sequence.
Definition: ald_nor_lcd.c:84
DEVICE_CODE2_ADDR
#define DEVICE_CODE2_ADDR
Definition: ald_nor_lcd.h:42
ald_ebi_nor_sram_timing_init
void ald_ebi_nor_sram_timing_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank)
Initialize the EBI_NOR_SRAM Timing according to the specified parameters in the EBI_NOR_SRAM_TimingTy...
Definition: ald_ebi.c:104
NORMEMDATWIDTH
static uint32_t NORMEMDATWIDTH
Definition: ald_nor_lcd.c:33
ald_nor_erase_chip
ald_status_t ald_nor_erase_chip(nor_handle_t *hperh)
Erase the entire NOR chip.
Definition: ald_nor_lcd.c:406
ald_nor_read
ald_status_t ald_nor_read(nor_handle_t *hperh, uint32_t *addr, uint16_t *data)
Read data from NOR memory.
Definition: ald_nor_lcd.c:182
ald_nor_lcd.h
Header file of EBI_NOR_LCD module driver.
NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD
#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD
Definition: ald_nor_lcd.h:77
CFI2_ADDRESS
#define CFI2_ADDRESS
Definition: ald_nor_lcd.h:47
NOR_CMD_DATA_FIRST
#define NOR_CMD_DATA_FIRST
Definition: ald_nor_lcd.h:73
NOR_MEMORY_ADRESS2
#define NOR_MEMORY_ADRESS2
Definition: ald_nor_lcd.h:60
NOR_CMD_DATA_BUFFER_AND_PROG
#define NOR_CMD_DATA_BUFFER_AND_PROG
Definition: ald_nor_lcd.h:82
NOR_CMD_DATA_CHIP_ERASE
#define NOR_CMD_DATA_CHIP_ERASE
Definition: ald_nor_lcd.h:80
NOR_CMD_DATA_PROGRAM
#define NOR_CMD_DATA_PROGRAM
Definition: ald_nor_lcd.h:76
NOR_WRITE
#define NOR_WRITE(ADDR, DATA)
Definition: ald_nor_lcd.h:98
NOR_MASK_STATUS_DQ6
#define NOR_MASK_STATUS_DQ6
Definition: ald_nor_lcd.h:86
NOR_MASK_STATUS_DQ5
#define NOR_MASK_STATUS_DQ5
Definition: ald_nor_lcd.h:85
ALD_NOR_STATUS_ERROR
Definition: ald_nor_lcd.h:123
NOR_CMD_ADDRESS_FIRST_CFI
#define NOR_CMD_ADDRESS_FIRST_CFI
Definition: ald_nor_lcd.h:65
ald_ebi_nor_sram_write_disable
void ald_ebi_nor_sram_write_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Disables dynamically EBI_NORSRAM write operation.
Definition: ald_ebi.c:249
nor_handle_t::lock
lock_state_t lock
Definition: ald_nor_lcd.h:154
ALD_NOR_STATUS_SUCCESS
Definition: ald_nor_lcd.h:121
nor_cfi_t::cfi_1
uint16_t cfi_1
Definition: ald_nor_lcd.h:141
NOR_ADDR_SHIFT
#define NOR_ADDR_SHIFT(NOR_ADDR, NOR_MEMORY_WIDTH_, ADDRESS)
Definition: ald_nor_lcd.h:94
nor_handle_t::instance
EBI_NOR_SRAM_TypeDef * instance
Definition: ald_nor_lcd.h:151
EBI_NORSRAM_MEM_BUS_WIDTH_8
Definition: ald_ebi.h:209
NOR_MEMORY_ADRESS4
#define NOR_MEMORY_ADRESS4
Definition: ald_nor_lcd.h:62
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
ald_nor_erase_block
ald_status_t ald_nor_erase_block(nor_handle_t *hperh, uint32_t blkaddr, uint32_t addr)
Erase the specified block of the NOR memory.
Definition: ald_nor_lcd.c:366
NOR_CMD_ADDRESS_THIRD
#define NOR_CMD_ADDRESS_THIRD
Definition: ald_nor_lcd.h:67
nor_cfi_t::cfi_3
uint16_t cfi_3
Definition: ald_nor_lcd.h:143
CFI4_ADDRESS
#define CFI4_ADDRESS
Definition: ald_nor_lcd.h:49
nor_handle_t
NOR handle Structure definition.
Definition: ald_nor_lcd.h:150
nor_id_t
EBI NOR ID typedef.
Definition: ald_nor_lcd.h:130
nor_status_t
nor_status_t
EBI NOR Status typedef.
Definition: ald_nor_lcd.h:120
nor_handle_t::state
__IO ald_nor_state_t state
Definition: ald_nor_lcd.h:155
NOR_CMD_ADDRESS_FOURTH
#define NOR_CMD_ADDRESS_FOURTH
Definition: ald_nor_lcd.h:68
CFI1_ADDRESS
#define CFI1_ADDRESS
Definition: ald_nor_lcd.h:46
DEVICE_CODE1_ADDR
#define DEVICE_CODE1_ADDR
Definition: ald_nor_lcd.h:41
MC_ADDRESS
#define MC_ADDRESS
Definition: ald_nor_lcd.h:40
nor_handle_t::ext
EBI_NOR_SRAM_EXTENDED_TypeDef * ext
Definition: ald_nor_lcd.h:152
ALD_NOR_STATE_RESET
Definition: ald_nor_lcd.h:110
ald_nor_init
ald_status_t ald_nor_init(nor_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing)
Perform the NOR memory Initialization sequence.
Definition: ald_nor_lcd.c:53
NOR_MEMORY_16B
#define NOR_MEMORY_16B
Definition: ald_nor_lcd.h:56
NOR_CMD_DATA_SECOND
#define NOR_CMD_DATA_SECOND
Definition: ald_nor_lcd.h:74
ald_nor_read_buffer
ald_status_t ald_nor_read_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size)
Reads a block of data from the EBI NOR memory.
Definition: ald_nor_lcd.c:264
ald_nor_write_enable
ald_status_t ald_nor_write_enable(nor_handle_t *hperh)
Enables dynamically NOR write operation.
Definition: ald_nor_lcd.c:492
ald_ebi_nor_sram_init
void ald_ebi_nor_sram_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_init_t *init)
Initialize the EBI_NOR_SRAM device according to the specified control parameters in the EBI_NOR_SRAM_...
Definition: ald_ebi.c:43
CFI3_ADDRESS
#define CFI3_ADDRESS
Definition: ald_nor_lcd.h:48
ald_ebi_nor_sram_init_t::width
ebi_norsram_mem_bus_width_t width
Definition: ald_ebi.h:402
NOR_CMD_DATA_BLOCK_ERASE
#define NOR_CMD_DATA_BLOCK_ERASE
Definition: ald_nor_lcd.h:84
NOR_MEMORY_8B
#define NOR_MEMORY_8B
Definition: ald_nor_lcd.h:55
nor_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_nor_lcd.h:153
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH
#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH
Definition: ald_nor_lcd.h:78
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ald_ebi_nor_sram_timing_t
EBI NORSRAM Timing parameters structure definition.
Definition: ald_ebi.h:109
nor_cfi_t::cfi_4
uint16_t cfi_4
Definition: ald_nor_lcd.h:144
ERROR
Definition: utils.h:56
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399
ald_ebi_nor_sram_enable
void ald_ebi_nor_sram_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Enable the NOR/SRAM device access.
Definition: ald_ebi.c:206
EBI_NORSRAM_BANK1
Definition: ald_ebi.h:190
ald_ebi_nor_sram_ext_timing_init
void ald_ebi_nor_sram_ext_timing_init(EBI_NOR_SRAM_EXTENDED_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank, uint32_t mode)
Initialize the EBI_NOR_SRAM Extended mode Timing according to the specified parameters in the EBI_NOR...
Definition: ald_ebi.c:138
ald_nor_write_disable
ald_status_t ald_nor_write_disable(nor_handle_t *hperh)
Disables dynamically NOR write operation.
Definition: ald_nor_lcd.c:508
ald_nor_return_readmode
ald_status_t ald_nor_return_readmode(nor_handle_t *hperh)
Returns the NOR memory to Read mode.
Definition: ald_nor_lcd.c:149


ALD User Manual: D:/svn/src/ald_nor_lcd.h Source File

  • D:
  • svn
  • src
ald_nor_lcd.h
Go to the documentation of this file.
1
17 #ifndef __ALD_NOR_LCD_H_
18 #define __ALD_NOR_LCD_H_
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "ald_ebi.h"
25
39 /* NOR device IDs addresses */
40 #define MC_ADDRESS ((uint16_t)0x0000U)
41 #define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
42 #define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
43 #define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
44
45 /* NOR CFI IDs addresses */
46 #define CFI1_ADDRESS ((uint16_t)0x10U)
47 #define CFI2_ADDRESS ((uint16_t)0x11U)
48 #define CFI3_ADDRESS ((uint16_t)0x12U)
49 #define CFI4_ADDRESS ((uint16_t)0x13U)
50
51 /* NOR operation wait timeout */
52 #define NOR_TMEOUT ((uint16_t)0xFFFFU)
53
54 /* NOR memory data width */
55 #define NOR_MEMORY_8B ((uint8_t)0x0U)
56 #define NOR_MEMORY_16B ((uint8_t)0x1U)
57
58 /* NOR memory device read/write start address */
59 #define NOR_MEMORY_ADRESS1 EBI_BANK1_1
60 #define NOR_MEMORY_ADRESS2 EBI_BANK1_2
61 #define NOR_MEMORY_ADRESS3 EBI_BANK1_3
62 #define NOR_MEMORY_ADRESS4 EBI_BANK1_4
63
64 #define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555U
65 #define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055U
66 #define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AAU
67 #define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555U
68 #define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555U
69 #define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AAU
70 #define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555U
71
72 #define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0U
73 #define NOR_CMD_DATA_FIRST (uint16_t)0x00AAU
74 #define NOR_CMD_DATA_SECOND (uint16_t)0x0055U
75 #define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090U
76 #define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0U
77 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080U
78 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AAU
79 #define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055U
80 #define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010U
81 #define NOR_CMD_DATA_CFI (uint16_t)0x0098U
82 #define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25U
83 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29U
84 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30U
85 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020U
86 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040U
87
94 #define NOR_ADDR_SHIFT(NOR_ADDR, NOR_MEMORY_WIDTH_, ADDRESS) \
95 ((uint32_t)(((NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B) ? \
96 ((uint32_t)((NOR_ADDR) + (2U * (ADDRESS)))): \
97 ((uint32_t)((NOR_ADDR) + (ADDRESS)))))
98 #define NOR_WRITE(ADDR, DATA) (*(__IO uint16_t *)((uint32_t)(ADDR)) = (DATA))
99
109 typedef enum {
110 ALD_NOR_STATE_RESET = 0x00U,
111 ALD_NOR_STATE_READY = 0x01U,
112 ALD_NOR_STATE_BUSY = 0x02U,
113 ALD_NOR_STATE_ERROR = 0x03U,
114 ALD_NOR_STATE_PROTECTED = 0x04U
115 } ald_nor_state_t;
116
120 typedef enum {
121 ALD_NOR_STATUS_SUCCESS = 0U,
122 ALD_NOR_STATUS_ONGOING,
123 ALD_NOR_STATUS_ERROR,
124 ALD_NOR_STATUS_TIMEOUT,
125 } nor_status_t;
126
130 typedef struct {
131 uint16_t m_code;
132 uint16_t device_code1;
133 uint16_t device_code2;
134 uint16_t device_code3;
135 } nor_id_t;
136
140 typedef struct {
141 uint16_t cfi_1;
142 uint16_t cfi_2;
143 uint16_t cfi_3;
144 uint16_t cfi_4;
145 } nor_cfi_t;
146
150 typedef struct {
151 EBI_NOR_SRAM_TypeDef *instance;
152 EBI_NOR_SRAM_EXTENDED_TypeDef *ext;
153 ald_ebi_nor_sram_init_t init;
154 lock_state_t lock;
155 __IO ald_nor_state_t state;
156 } nor_handle_t;
167 /* Initialization/de-initialization functions */
168 ald_status_t ald_nor_init(nor_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing);
169 ald_status_t ald_nor_deinit(nor_handle_t *hperh);
176 /* I/O operation functions */
177 ald_status_t ald_nor_read_id(nor_handle_t *hperh, nor_id_t *id);
178 ald_status_t ald_nor_return_readmode(nor_handle_t *hperh);
179 ald_status_t ald_nor_read(nor_handle_t *hperh, uint32_t *addr, uint16_t *data);
180 ald_status_t ald_nor_program(nor_handle_t *hperh, uint32_t *addr, uint16_t *data);
181 ald_status_t ald_nor_read_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size);
182 ald_status_t ald_nor_program_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size);
183 ald_status_t ald_nor_erase_block(nor_handle_t *hperh, uint32_t blkaddr, uint32_t addr);
184 ald_status_t ald_nor_erase_chip(nor_handle_t *hperh);
185 ald_status_t ald_nor_read_cfi(nor_handle_t *hperh, nor_cfi_t *cfi);
192 /* Control functions */
193 ald_status_t ald_nor_write_enable(nor_handle_t *hperh);
194 ald_status_t ald_nor_write_disable(nor_handle_t *hperh);
201 /* State functions */
202 ald_nor_state_t ald_nor_get_state(nor_handle_t *hperh);
203 nor_status_t ald_nor_get_status(nor_handle_t *hperh, uint32_t addr, uint32_t timeout);
216 #ifdef __cplusplus
217 }
218 #endif
219
220 #endif /* __ALD_NOR_LCD_H__ */
ALD_NOR_STATE_PROTECTED
Definition: ald_nor_lcd.h:114
ALD_NOR_STATE_READY
Definition: ald_nor_lcd.h:111
EBI_NOR_SRAM_TypeDef
#define EBI_NOR_SRAM_TypeDef
Definition: ald_ebi.h:40
nor_cfi_t::cfi_2
uint16_t cfi_2
Definition: ald_nor_lcd.h:142
EBI_NOR_SRAM_EXTENDED_TypeDef
#define EBI_NOR_SRAM_EXTENDED_TypeDef
Definition: ald_ebi.h:41
nor_cfi_t
EBI NOR CFI typedef.
Definition: ald_nor_lcd.h:140
ald_nor_read_cfi
ald_status_t ald_nor_read_cfi(nor_handle_t *hperh, nor_cfi_t *cfi)
Read NOR flash CFI IDs.
Definition: ald_nor_lcd.c:447
ALD_NOR_STATE_BUSY
Definition: ald_nor_lcd.h:112
ald_nor_program_buffer
ald_status_t ald_nor_program_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size)
Writes a half-word buffer to the EBI NOR memory.
Definition: ald_nor_lcd.c:311
ald_nor_read_id
ald_status_t ald_nor_read_id(nor_handle_t *hperh, nor_id_t *id)
Read NOR flash IDs.
Definition: ald_nor_lcd.c:106
nor_id_t::device_code1
uint16_t device_code1
Definition: ald_nor_lcd.h:132
ald_nor_get_state
ald_nor_state_t ald_nor_get_state(nor_handle_t *hperh)
return the NOR controller state
Definition: ald_nor_lcd.c:532
ald_nor_state_t
ald_nor_state_t
ALD SRAM State structures definition.
Definition: ald_nor_lcd.h:109
ald_ebi_nor_sram_init_t
EBI NORSRAM Configuration Structure definition.
Definition: ald_ebi.h:398
ald_nor_init
ald_status_t ald_nor_init(nor_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing)
Perform the NOR memory Initialization sequence.
Definition: ald_nor_lcd.c:53
ALD_NOR_STATUS_TIMEOUT
Definition: ald_nor_lcd.h:124
ald_nor_program
ald_status_t ald_nor_program(nor_handle_t *hperh, uint32_t *addr, uint16_t *data)
Program data to NOR memory.
Definition: ald_nor_lcd.c:221
ALD_NOR_STATUS_ONGOING
Definition: ald_nor_lcd.h:122
ald_nor_get_status
nor_status_t ald_nor_get_status(nor_handle_t *hperh, uint32_t addr, uint32_t timeout)
Returns the NOR operation status.
Definition: ald_nor_lcd.c:544
ALD_NOR_STATE_ERROR
Definition: ald_nor_lcd.h:113
ald_nor_deinit
ald_status_t ald_nor_deinit(nor_handle_t *hperh)
Perform NOR memory De-Initialization sequence.
Definition: ald_nor_lcd.c:84
ald_nor_erase_chip
ald_status_t ald_nor_erase_chip(nor_handle_t *hperh)
Erase the entire NOR chip.
Definition: ald_nor_lcd.c:406
ald_nor_read
ald_status_t ald_nor_read(nor_handle_t *hperh, uint32_t *addr, uint16_t *data)
Read data from NOR memory.
Definition: ald_nor_lcd.c:182
nor_id_t::device_code3
uint16_t device_code3
Definition: ald_nor_lcd.h:134
nor_id_t::m_code
uint16_t m_code
Definition: ald_nor_lcd.h:131
lock_state_t
lock_state_t
Definition: type.h:58
ALD_NOR_STATUS_ERROR
Definition: ald_nor_lcd.h:123
nor_handle_t::lock
lock_state_t lock
Definition: ald_nor_lcd.h:154
ALD_NOR_STATUS_SUCCESS
Definition: ald_nor_lcd.h:121
nor_cfi_t::cfi_1
uint16_t cfi_1
Definition: ald_nor_lcd.h:141
nor_id_t::device_code2
uint16_t device_code2
Definition: ald_nor_lcd.h:133
nor_handle_t::instance
EBI_NOR_SRAM_TypeDef * instance
Definition: ald_nor_lcd.h:151
ald_nor_erase_block
ald_status_t ald_nor_erase_block(nor_handle_t *hperh, uint32_t blkaddr, uint32_t addr)
Erase the specified block of the NOR memory.
Definition: ald_nor_lcd.c:366
nor_cfi_t::cfi_3
uint16_t cfi_3
Definition: ald_nor_lcd.h:143
nor_handle_t
NOR handle Structure definition.
Definition: ald_nor_lcd.h:150
nor_id_t
EBI NOR ID typedef.
Definition: ald_nor_lcd.h:130
nor_status_t
nor_status_t
EBI NOR Status typedef.
Definition: ald_nor_lcd.h:120
nor_handle_t::state
__IO ald_nor_state_t state
Definition: ald_nor_lcd.h:155
nor_handle_t::ext
EBI_NOR_SRAM_EXTENDED_TypeDef * ext
Definition: ald_nor_lcd.h:152
ALD_NOR_STATE_RESET
Definition: ald_nor_lcd.h:110
ald_nor_read_buffer
ald_status_t ald_nor_read_buffer(nor_handle_t *hperh, uint32_t addr, uint16_t *data, uint32_t size)
Reads a block of data from the EBI NOR memory.
Definition: ald_nor_lcd.c:264
ald_nor_write_enable
ald_status_t ald_nor_write_enable(nor_handle_t *hperh)
Enables dynamically NOR write operation.
Definition: ald_nor_lcd.c:492
ald_ebi.h
Header file of EBI module driver.
nor_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_nor_lcd.h:153
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
ald_ebi_nor_sram_timing_t
EBI NORSRAM Timing parameters structure definition.
Definition: ald_ebi.h:109
nor_cfi_t::cfi_4
uint16_t cfi_4
Definition: ald_nor_lcd.h:144
ald_nor_write_disable
ald_status_t ald_nor_write_disable(nor_handle_t *hperh)
Disables dynamically NOR write operation.
Definition: ald_nor_lcd.c:508
ald_nor_return_readmode
ald_status_t ald_nor_return_readmode(nor_handle_t *hperh)
Returns the NOR memory to Read mode.
Definition: ald_nor_lcd.c:149


ALD User Manual: D:/svn/src/ald_pis.c Source File

  • D:
  • svn
  • src
ald_pis.c
Go to the documentation of this file.
1
17 #include "ald_pis.h"
18
27 #ifdef ALD_PIS
28
45 ald_status_t ald_pis_create(pis_handle_t *hperh)
46 {
47 if (hperh == NULL)
48 return ERROR;
49
50 assert_param(IS_PIS_SRC(hperh->init.producer_src));
51 assert_param(IS_PIS_TRIG(hperh->init.consumer_trig));
52 assert_param(IS_PIS_CLOCK(hperh->init.producer_clk));
53 assert_param(IS_PIS_CLOCK(hperh->init.consumer_clk));
54 assert_param(IS_PIS_EDGE(hperh->init.producer_edge));
55 assert_param(IS_PIS_SIGNAL_MODE(hperh->init.producer_signal));
56
57 __LOCK(hperh);
58 hperh->perh = PIS;
59
60 /* get location of consumer in channel and position of con0/con1
61 * accord to comsumer_trig information */
62 hperh->consumer_ch = (pis_ch_t)(hperh->init.consumer_trig & 0x0F);
63 hperh->consumer_con = (pis_con_t)((hperh->init.consumer_trig >> 4) & 0x0F);
64 hperh->consumer_pos = (1U << (uint32_t)((hperh->init.consumer_trig >> 8) & 0xFF));
65
66 if (hperh->perh->CH_CON[hperh->consumer_ch] != 0) {
67 __UNLOCK(hperh);
68 return BUSY;
69 }
70
71 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SRCS_MSK, ((hperh->init.producer_src) >> 4) << PIS_CH0_CON_SRCS_POSS);
72 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_MSIGS_MSK, ((hperh->init.producer_src) & 0xf) << PIS_CH0_CON_MSIGS_POSS);
73
74 if (hperh->init.producer_clk == hperh->init.consumer_clk) {
75 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_DIRECT << PIS_CH0_CON_SYNCSEL_POSS);
76 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, (hperh->init.consumer_clk) << PIS_CH0_CON_PULCK_POSS);
77 }
78 else {
79 if (hperh->init.producer_signal == PIS_OUT_LEVEL) {
80 if (hperh->init.consumer_clk == PIS_CLK_PCLK1)
81 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_LEVEL_ASY_APB1 << PIS_CH0_CON_SYNCSEL_POSS);
82 if (hperh->init.consumer_clk == PIS_CLK_PCLK2)
83 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_LEVEL_ASY_APB2 << PIS_CH0_CON_SYNCSEL_POSS);
84 if (hperh->init.consumer_clk == PIS_CLK_SYS)
85 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_LEVEL_ASY_AHB << PIS_CH0_CON_SYNCSEL_POSS);
86 }
87
88 if (hperh->init.producer_signal == PIS_OUT_PULSE) {
89 if (hperh->init.consumer_clk == PIS_CLK_PCLK1)
90 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_PULSE_ASY_APB1 << PIS_CH0_CON_SYNCSEL_POSS);
91 if (hperh->init.consumer_clk == PIS_CLK_PCLK2)
92 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_PULSE_ASY_APB2 << PIS_CH0_CON_SYNCSEL_POSS);
93 if (hperh->init.consumer_clk == PIS_CLK_SYS)
94 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, PIS_SYN_PULSE_ASY_AHB << PIS_CH0_CON_SYNCSEL_POSS);
95 }
96 }
97
98 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, hperh->init.consumer_clk << PIS_CH0_CON_PULCK_POSS);
99 MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_EDGS_MSK, hperh->init.producer_edge << PIS_CH0_CON_EDGS_POSS);
100 hperh->check_info = hperh->perh->CH_CON[hperh->consumer_ch];
101
102 /* enable consumer bit, switch pin of consumer */
103 if (hperh->init.input_chan == PIS_CHAN_INPUT) {
104 switch (hperh->consumer_con) {
105 case PIS_CON_0:
106 PIS->TAR_CON0 |= hperh->consumer_pos;
107 break;
108 case PIS_CON_1:
109 PIS->TAR_CON1 |= hperh->consumer_pos;
110 break;
111 default:
112 break;
113 }
114 }
115
116 __UNLOCK(hperh);
117 return OK;
118 }
119
127 ald_status_t ald_pis_destroy(pis_handle_t *hperh)
128 {
129 assert_param(IS_PIS(hperh->perh));
130
131 if (hperh->check_info != hperh->perh->CH_CON[hperh->consumer_ch])
132 return ERROR;
133
134 __LOCK(hperh);
135
136 CLEAR_BIT(PIS->CH_OER, (1U << (uint32_t)hperh->consumer_ch));
137 WRITE_REG(hperh->perh->CH_CON[hperh->consumer_ch], 0x0);
138
139 switch (hperh->consumer_con) {
140 case PIS_CON_0:
141 PIS->TAR_CON0 &= ~(hperh->consumer_pos);
142 break;
143 case PIS_CON_1:
144 PIS->TAR_CON1 &= ~(hperh->consumer_pos);
145 break;
146 default:
147 break;
148 }
149
150 hperh->state = PIS_STATE_RESET;
151 __UNLOCK(hperh);
152
153 return OK;
154 }
176 ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch)
177 {
178 assert_param(IS_PIS(hperh->perh));
179 assert_param(IS_PIS_OUPUT_CH(ch));
180 __LOCK(hperh);
181 SET_BIT(PIS->CH_OER, (1 << ch));
182 __UNLOCK(hperh);
183
184 return OK;
185 }
186
199 ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch)
200 {
201 assert_param(IS_PIS(hperh->perh));
202 assert_param(IS_PIS_OUPUT_CH(ch));
203 __LOCK(hperh);
204 CLEAR_BIT(PIS->CH_OER, (1 << ch));
205 __UNLOCK(hperh);
206
207 return OK;
208 }
224 pis_state_t ald_pis_get_state(pis_handle_t *hperh)
225 {
226 assert_param(IS_PIS(hperh->perh));
227 return hperh->state;
228 }
229
248 ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config)
249 {
250 assert_param(IS_PIS(hperh->perh));
251 assert_param(IS_PIS_MODU_TARGET(config->target));
252 assert_param(IS_PIS_MODU_LEVEL(config->level));
253 assert_param(IS_PIS_MODU_SRC(config->src));
254 assert_param(IS_PIS_MODU_CHANNEL(config->channel));
255 __LOCK(hperh);
256
257 switch (config->target) {
258 case PIS_UART0_TX:
259 MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXMLVLS_MSK, config->level << PIS_UART0_TXMCR_TXMLVLS_POS);
260 MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXMSS_MSK, config->src << PIS_UART0_TXMCR_TXMSS_POSS);
261 MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_UART0_TXMCR_TXSIGS_MSK, config->channel << PIS_UART0_TXMCR_TXSIGS_POSS);
262 break;
263
264 case PIS_UART1_TX:
265 MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXMLVLS_MSK, config->level << PIS_UART1_TXMCR_TXMLVLS_POS);
266 MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXMSS_MSK, config->src << PIS_UART1_TXMCR_TXMSS_POSS);
267 MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_UART1_TXMCR_TXSIGS_MSK, config->channel << PIS_UART1_TXMCR_TXSIGS_POSS);
268 break;
269
270 case PIS_UART2_TX:
271 MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXMLVLS_MSK, config->level << PIS_UART2_TXMCR_TXMLVLS_POS);
272 MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXMSS_MSK, config->src << PIS_UART2_TXMCR_TXMSS_POSS);
273 MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_UART2_TXMCR_TXSIGS_MSK, config->channel << PIS_UART2_TXMCR_TXSIGS_POSS);
274 break;
275
276 case PIS_UART3_TX:
277 MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXMLVLS_MSK, config->level << PIS_UART3_TXMCR_TXMLVLS_POS);
278 MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXMSS_MSK, config->src << PIS_UART3_TXMCR_TXMSS_POSS);
279 MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_UART3_TXMCR_TXSIGS_MSK, config->channel << PIS_UART3_TXMCR_TXSIGS_POSS);
280 break;
281
282 case PIS_LPUART0_TX:
283 MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_LPUART0_TXMCR_TXMLVLS_MSK, config->level << PIS_LPUART0_TXMCR_TXMLVLS_POS);
284 MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_LPUART0_TXMCR_TXMSS_MSK, config->src << PIS_LPUART0_TXMCR_TXMSS_POSS);
285 MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_LPUART0_TXMCR_TXSIGS_MSK, config->channel << PIS_LPUART0_TXMCR_TXSIGS_POSS);
286 break;
287
288 default:
289 break;
290 }
291
292 __UNLOCK(hperh);
293 return OK;
294 }
301 #endif /* ALD_PIS */
302
pis_modulate_config_t::level
pis_modu_level_t level
Definition: ald_pis.h:410
IS_PIS_MODU_CHANNEL
#define IS_PIS_MODU_CHANNEL(x)
Definition: ald_pis.h:649
pis_modulate_config_t::target
pis_modu_targ_t target
Definition: ald_pis.h:409
OK
Definition: utils.h:55
IS_PIS_EDGE
#define IS_PIS_EDGE(x)
Definition: ald_pis.h:623
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
PIS_STATE_RESET
Definition: ald_pis.h:332
pis_modulate_config_t
PIS modulate config structure definition.
Definition: ald_pis.h:408
IS_PIS_OUPUT_CH
#define IS_PIS_OUPUT_CH(x)
Definition: ald_pis.h:629
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
BUSY
Definition: utils.h:57
IS_PIS_MODU_TARGET
#define IS_PIS_MODU_TARGET(x)
Definition: ald_pis.h:633
ald_pis_destroy
ald_status_t ald_pis_destroy(pis_handle_t *hperh)
Destroy the PIS mode according to the specified parameters in the pis_init_t and create the associate...
Definition: ald_pis.c:127
pis_con_t
pis_con_t
Indirect value,no care of it.
Definition: ald_pis.h:322
PIS_CLK_PCLK1
Definition: ald_pis.h:251
PIS_OUT_LEVEL
Definition: ald_pis.h:271
pis_init_t::producer_src
pis_src_t producer_src
Definition: ald_pis.h:396
PIS_CON_1
Definition: ald_pis.h:324
PIS_SYN_PULSE_ASY_APB2
Definition: ald_pis.h:283
IS_PIS_TRIG
#define IS_PIS_TRIG(x)
Definition: ald_pis.h:558
pis_handle_s::consumer_ch
pis_ch_t consumer_ch
Definition: ald_pis.h:421
IS_PIS_CLOCK
#define IS_PIS_CLOCK(x)
Definition: ald_pis.h:618
pis_state_t
pis_state_t
PIS state structures definition.
Definition: ald_pis.h:331
pis_handle_s
PIS Handle Structure definition.
Definition: ald_pis.h:418
PIS_SYN_PULSE_ASY_AHB
Definition: ald_pis.h:284
pis_ch_t
pis_ch_t
Pis channel.
Definition: ald_pis.h:290
PIS_UART2_TX
Definition: ald_pis.h:345
pis_modulate_config_t::src
pis_modu_src_t src
Definition: ald_pis.h:411
IS_PIS_SIGNAL_MODE
#define IS_PIS_SIGNAL_MODE(x)
Definition: ald_pis.h:621
ald_pis_get_state
pis_state_t ald_pis_get_state(pis_handle_t *hperh)
Returns the PIS state.
Definition: ald_pis.c:224
IS_PIS_SRC
#define IS_PIS_SRC(x)
Definition: ald_pis.h:437
PIS_CHAN_INPUT
Definition: ald_pis.h:389
PIS_UART1_TX
Definition: ald_pis.h:344
PIS_CLK_SYS
Definition: ald_pis.h:253
pis_init_t::input_chan
pis_input_sel_t input_chan
Definition: ald_pis.h:402
pis_modulate_config_t::channel
pis_modu_channel_t channel
Definition: ald_pis.h:412
IS_PIS_MODU_SRC
#define IS_PIS_MODU_SRC(x)
Definition: ald_pis.h:640
PIS_SYN_LEVEL_ASY_AHB
Definition: ald_pis.h:281
ald_pis.h
Header file of PIS driver.
pis_init_t::producer_signal
pis_output_t producer_signal
Definition: ald_pis.h:397
pis_init_t::producer_edge
pis_edge_t producer_edge
Definition: ald_pis.h:399
PIS_CON_0
Definition: ald_pis.h:323
IS_PIS_MODU_LEVEL
#define IS_PIS_MODU_LEVEL(x)
Definition: ald_pis.h:638
PIS_SYN_LEVEL_ASY_APB1
Definition: ald_pis.h:279
pis_handle_s::consumer_pos
uint8_t consumer_pos
Definition: ald_pis.h:423
ald_pis_create
ald_status_t ald_pis_create(pis_handle_t *hperh)
Create the PIS mode according to the specified parameters in the pis_handle_t and create the associat...
Definition: ald_pis.c:45
pis_handle_s::state
pis_state_t state
Definition: ald_pis.h:426
PIS_SYN_DIRECT
Definition: ald_pis.h:278
ald_pis_modu_config
ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config)
Config the PIS modulate signal function.
Definition: ald_pis.c:248
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
PIS_OUT_PULSE
Definition: ald_pis.h:272
PIS_CLK_PCLK2
Definition: ald_pis.h:252
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
pis_handle_s::perh
PIS_TypeDef * perh
Definition: ald_pis.h:419
pis_handle_s::consumer_con
pis_con_t consumer_con
Definition: ald_pis.h:422
PIS_LPUART0_TX
Definition: ald_pis.h:347
PIS_UART3_TX
Definition: ald_pis.h:346
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
pis_init_t::producer_clk
pis_clock_t producer_clk
Definition: ald_pis.h:398
pis_handle_s::init
pis_init_t init
Definition: ald_pis.h:420
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
IS_PIS
#define IS_PIS(x)
Definition: ald_pis.h:436
pis_init_t::consumer_trig
pis_trig_t consumer_trig
Definition: ald_pis.h:400
pis_handle_s::check_info
uint32_t check_info
Definition: ald_pis.h:424
PIS_SYN_PULSE_ASY_APB1
Definition: ald_pis.h:282
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ERROR
Definition: utils.h:56
PIS_UART0_TX
Definition: ald_pis.h:343
ald_pis_output_start
ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch)
Start the PIS output function.
Definition: ald_pis.c:176
ald_pis_output_stop
ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch)
Stop the PIS output function.
Definition: ald_pis.c:199
pis_out_ch_t
pis_out_ch_t
Pis output channel.
Definition: ald_pis.h:312
pis_init_t::consumer_clk
pis_clock_t consumer_clk
Definition: ald_pis.h:401
PIS_SYN_LEVEL_ASY_APB2
Definition: ald_pis.h:280


ALD User Manual: D:/svn/src/ald_pis.h Source File

  • D:
  • svn
  • src
ald_pis.h
Go to the documentation of this file.
1
17 #ifndef __ALD_PIS_H__
18 #define __ALD_PIS_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25
26
58 typedef enum {
59 PIS_NON = 0x0U,
60 PIS_GPIO_PIN0 = 0x10U,
61 PIS_GPIO_PIN1 = 0x11U,
62 PIS_GPIO_PIN2 = 0x12U,
63 PIS_GPIO_PIN3 = 0x13U,
64 PIS_GPIO_PIN4 = 0x14U,
65 PIS_GPIO_PIN5 = 0x15U,
66 PIS_GPIO_PIN6 = 0x16U,
67 PIS_GPIO_PIN7 = 0x17U,
68 PIS_GPIO_PIN8 = 0x18U,
69 PIS_GPIO_PIN9 = 0x19U,
70 PIS_GPIO_PIN10 = 0x1aU,
71 PIS_GPIO_PIN11 = 0x1bU,
72 PIS_GPIO_PIN12 = 0x1cU,
73 PIS_GPIO_PIN13 = 0x1dU,
74 PIS_GPIO_PIN14 = 0x1eU,
75 PIS_GPIO_PIN15 = 0x1fU,
76 PIS_ACMP_OUT0 = 0x30U,
77 PIS_ACMP_OUT1 = 0x31U,
78 PIS_DAC0_CH0 = 0x40U,
79 PIS_DAC0_CH1 = 0x41U,
80 PIS_ADC0_INSERT = 0x60U,
81 PIS_ADC0_NORMAL = 0x61U,
82 PIS_ADC0_RESERVE = 0x62U,
83 PIS_LVD = 0x70U,
84 PIS_UART0_RESERVE0 = 0x80U,
85 PIS_UART0_RESERVE1 = 0x81U,
86 PIS_UART0_IRDAOUT = 0x82U,
87 PIS_UART0_RTSOUT = 0x83U,
88 PIS_UART0_TXOUT = 0x84U,
89 PIS_UART0_SYN_SEND = 0x85U,
90 PIS_UART0_SYN_RECV = 0x86U,
91 PIS_UART1_RESERVE0 = 0x90U,
92 PIS_UART1_RESERVE1 = 0x91U,
93 PIS_UART1_IRDA = 0x92U,
94 PIS_UART1_RTS = 0x93U,
95 PIS_UART1_TXOUT = 0x94U,
96 PIS_UART1_SYN_SEND = 0x95U,
97 PIS_UART1_SYN_RECV = 0x96U,
98 PIS_UART2_RESERVE0 = 0xa0U,
99 PIS_UART2_RESERVE1 = 0xa1U,
100 PIS_UART2_IRDA = 0xa2U,
101 PIS_UART2_RTS = 0xa3U,
102 PIS_UART2_TXOUT = 0xa4U,
103 PIS_UART2_SYN_SEND = 0xa5U,
104 PIS_UART2_SYN_RECV = 0xa6U,
105 PIS_UART3_RESERVE0 = 0xb1U,
106 PIS_UART3_RESERVE1 = 0xb2U,
107 PIS_UART3_IRDA = 0xb3U,
108 PIS_UART3_RTS = 0xb4U,
109 PIS_UART3_TXOUT = 0xb5U,
110 PIS_UART3_SYN_SEND = 0xb6U,
111 PIS_UART3_SYN_RECV = 0xb7U,
112 PIS_UART4_RECV = 0xc0U,
113 PIS_UART4_SEND = 0xc1U,
114 PIS_UART4_TXOUT = 0xc2U,
115 PIS_UART5_RECV = 0xd0U,
116 PIS_UART5_SEND = 0xd1U,
117 PIS_UART5_TXOUT = 0xd2U,
118 PIS_SPI0_RECV = 0xe0U,
119 PIS_SPI0_SEND = 0xe1U,
120 PIS_SPI0_NE = 0xe2U,
121 PIS_SPI1_RECV = 0xf0U,
122 PIS_SPI1_SEND = 0xf1U,
123 PIS_SPI1_NE = 0xf2U,
124 PIS_I2C0_RECV = 0x100U,
125 PIS_I2C0_SEND = 0x101U,
126 PIS_I2C1_RECV = 0x110U,
127 PIS_I2C1_SEND = 0x111U,
128 PIS_TIMER0_UPDATA = 0x120U,
129 PIS_TIMER0_TRIG = 0x121U,
130 PIS_TIMER0_INPUT_1 = 0x122U,
131 PIS_TIMER0_OUTPUT_1 = 0x123U,
132 PIS_TIMER0_INPUT_2 = 0x124U,
133 PIS_TIMER0_OUTPUT_2 = 0x125U,
134 PIS_TIMER0_INPUT_3 = 0x126U,
135 PIS_TIMER0_OUTPUT_3 = 0x127U,
136 PIS_TIMER0_INPUT_4 = 0x128U,
137 PIS_TIMER0_OUTPUT_4 = 0x129U,
138 PIS_TIMER1_UPDATA = 0x130U,
139 PIS_TIMER1_TRIG = 0x131U,
140 PIS_TIMER1_INPUT_1 = 0x132U,
141 PIS_TIMER1_OUTPUT_1 = 0x133U,
142 PIS_TIMER1_INPUT_2 = 0x134U,
143 PIS_TIMER1_OUTPUT_2 = 0x135U,
144 PIS_TIMER1_INPUT_3 = 0x136U,
145 PIS_TIMER1_OUTPUT_3 = 0x137U,
146 PIS_TIMER1_INPUT_4 = 0x138U,
147 PIS_TIMER1_OUTPUT_4 = 0x139U,
148 PIS_TIMER2_UPDATA = 0x140U,
149 PIS_TIMER2_TRIG = 0x141U,
150 PIS_TIMER2_INPUT_1 = 0x142U,
151 PIS_TIMER2_OUTPUT_1 = 0x143U,
152 PIS_TIMER2_INPUT_2 = 0x144U,
153 PIS_TIMER2_OUTPUT_2 = 0x145U,
154 PIS_TIMER2_INPUT_3 = 0x146U,
155 PIS_TIMER2_OUTPUT_3 = 0x147U,
156 PIS_TIMER2_INPUT_4 = 0x148U,
157 PIS_TIMER2_OUTPUT_4 = 0x149U,
158 PIS_TIMER3_UPDATA = 0x150U,
159 PIS_TIMER3_TRIG = 0x151U,
160 PIS_TIMER3_INPUT_1 = 0x152U,
161 PIS_TIMER3_OUTPUT_1 = 0x153U,
162 PIS_TIMER3_INPUT_2 = 0x154U,
163 PIS_TIMER3_OUTPUT_2 = 0x155U,
164 PIS_TIMER3_INPUT_3 = 0x156U,
165 PIS_TIMER3_OUTPUT_3 = 0x157U,
166 PIS_TIMER3_INPUT_4 = 0x158U,
167 PIS_TIMER3_OUTPUT_4 = 0x159U,
168 PIS_RTC_CLOCK = 0x160U,
169 PIS_RTC_ALARM = 0x161U,
170 PIS_LPTIMER0_SYN_UPDATA = 0x170U,
171 PIS_LPTIMER0_ASY_UPDATA = 0x171U,
172 PIS_LPUART0_ASY_RECV = 0x180U,
173 PIS_LPUART0_ASY_SEND = 0x181U,
174 PIS_LPUART0_SYN_RECV = 0x182U,
175 PIS_LPUART0_SYN_SEND = 0x183U,
176 PIS_DMA = 0x190U,
177 PIS_ADC1_INSERT = 0x1a0U,
178 PIS_ADC1_NORMAL = 0x1a1U,
179 PIS_ADC1_RESERVE = 0x1a2U,
180 } pis_src_t;
181
185 typedef enum {
186 PIS_CH12_TIMER0_ITR0 = 0x003CU,
187 PIS_CH13_TIMER0_ITR1 = 0x003DU,
188 PIS_CH14_TIMER0_ITR2 = 0x003EU,
189 PIS_CH15_TIMER0_ITR3 = 0x003FU,
190 PIS_CH12_TIMER1_ITR0 = 0x003CU,
191 PIS_CH13_TIMER1_ITR1 = 0x003DU,
192 PIS_CH14_TIMER1_ITR2 = 0x003EU,
193 PIS_CH15_TIMER1_ITR3 = 0x003FU,
194 PIS_CH12_TIMER2_ITR0 = 0x003CU,
195 PIS_CH13_TIMER2_ITR1 = 0x003DU,
196 PIS_CH14_TIMER2_ITR2 = 0x003EU,
197 PIS_CH15_TIMER2_ITR3 = 0x003FU,
198 PIS_CH12_TIMER3_ITR0 = 0x003CU,
199 PIS_CH13_TIMER3_ITR1 = 0x003DU,
200 PIS_CH14_TIMER3_ITR2 = 0x003EU,
201 PIS_CH15_TIMER3_ITR3 = 0x003FU,
202 PIS_CH6_ADC0_NORMAL = 0x0036U,
203 PIS_CH7_ADC0_INSERT = 0x0037U,
204 PIS_CH0_ADC1_NORMAL = 0x0030U,
205 PIS_CH1_ADC1_INSERT = 0x0031U,
206 PIS_CH0_LPTIM0_EXT0 = 0x0030U,
207 PIS_CH1_LPTIM0_EXT1 = 0x0031U,
208 PIS_CH2_LPTIM0_EXT2 = 0x0032U,
209 PIS_CH3_LPTIM0_EXT3 = 0x0033U,
210 PIS_CH4_LPTIM0_EXT4 = 0x0034U,
211 PIS_CH5_LPTIM0_EXT5 = 0x0035U,
212 PIS_CH6_LPTIM0_EXT6 = 0x0036U,
213 PIS_CH7_LPTIM0_EXT7 = 0x0037U,
214 PIS_CH7_DMA_REQUEST = 0x0037U,
215 PIS_CH15_LPUART0_RXD = 0x081FU,
216 PIS_CH14_UART5_RXD = 0x071EU,
217 PIS_CH13_UART4_RXD = 0x061DU,
218 PIS_CH12_UART3_RXD = 0x031CU,
219 PIS_CH11_UART2_RXD = 0x021BU,
220 PIS_CH10_UART1_RXD = 0x011AU,
221 PIS_CH9_UART0_RXD = 0x0019U,
222 PIS_CH8_TIMER3_CH4IN = 0x1B08U,
223 PIS_CH8_TIMER2_CH4IN = 0x1308U,
224 PIS_CH8_SPI1_CLK = 0x0F18U,
225 PIS_CH7_TIMER3_CH3IN = 0x1A07U,
226 PIS_CH7_TIMER2_CH3IN = 0x1207U,
227 PIS_CH7_SPI1_RX = 0x0E17U,
228 PIS_CH6_TIMER3_CH2IN = 0x1906U,
229 PIS_CH6_TIMER2_CH2IN = 0x1106U,
230 PIS_CH6_SPI0_CLK = 0x0D16U,
231 PIS_CH5_TIMER3_CH1IN = 0x1805U,
232 PIS_CH5_TIMER2_CH1IN = 0x1005U,
233 PIS_CH5_SPI0_RX = 0x0C15U,
234 PIS_CH4_TIMER1_CH4IN = 0x0B04U,
235 PIS_CH4_TIMER0_CH4IN = 0x0304U,
236 PIS_CH3_TIMER1_CH3IN = 0x0A03U,
237 PIS_CH3_TIMER0_CH3IN = 0x0203U,
238 PIS_CH2_TIMER1_CH2IN = 0x0902U,
239 PIS_CH2_TIMER0_CH2IN = 0x0102U,
240 PIS_CH1_TIMER1_CH1IN = 0x0801U,
241 PIS_CH0_TIMER0_CH1IN = 0x0000U,
242 PIS_CH0_TIMER0_BRKIN = 0x0400U,
243 PIS_CH0_TIMER1_BRKIN = 0x0C00U,
244 PIS_TRIG_RESERVE = 0xFFFFU,
245 } pis_trig_t;
246
250 typedef enum {
251 PIS_CLK_PCLK1 = 0U,
252 PIS_CLK_PCLK2 = 1U,
253 PIS_CLK_SYS = 2U,
254 PIS_CLK_RESERVE = 3U,
255 } pis_clock_t;
256
260 typedef enum {
261 PIS_EDGE_NONE = 0U,
262 PIS_EDGE_UP = 1U,
263 PIS_EDGE_DOWN = 2U,
264 PIS_EDGE_UP_DOWN = 3U,
265 } pis_edge_t;
266
270 typedef enum {
271 PIS_OUT_LEVEL = 0U,
272 PIS_OUT_PULSE = 1U,
273 } pis_output_t;
277 typedef enum {
278 PIS_SYN_DIRECT = 0U,
279 PIS_SYN_LEVEL_ASY_APB1 = 1U,
280 PIS_SYN_LEVEL_ASY_APB2 = 2U,
281 PIS_SYN_LEVEL_ASY_AHB = 3U,
282 PIS_SYN_PULSE_ASY_APB1 = 4U,
283 PIS_SYN_PULSE_ASY_APB2 = 5U,
284 PIS_SYN_PULSE_ASY_AHB = 6U,
285 } pis_syncsel_t;
286
290 typedef enum {
291 PIS_CH_0 = 0U,
292 PIS_CH_1 = 1U,
293 PIS_CH_2 = 2U,
294 PIS_CH_3 = 3U,
295 PIS_CH_4 = 4U,
296 PIS_CH_5 = 5U,
297 PIS_CH_6 = 6U,
298 PIS_CH_7 = 7U,
299 PIS_CH_8 = 8U,
300 PIS_CH_9 = 9U,
301 PIS_CH_10 = 10U,
302 PIS_CH_11 = 11U,
303 PIS_CH_12 = 12U,
304 PIS_CH_13 = 13U,
305 PIS_CH_14 = 14U,
306 PIS_CH_15 = 15U,
307 } pis_ch_t;
308
312 typedef enum {
313 PIS_OUT_CH_0 = 0U,
314 PIS_OUT_CH_1 = 1U,
315 PIS_OUT_CH_2 = 2U,
316 PIS_OUT_CH_3 = 3U,
317 } pis_out_ch_t;
318
322 typedef enum {
323 PIS_CON_0 = 0U,
324 PIS_CON_1 = 1U,
325 PIS_CON_NONE = 2U,
326 } pis_con_t;
327
331 typedef enum {
332 PIS_STATE_RESET = 0x00U,
333 PIS_STATE_READY = 0x01U,
334 PIS_STATE_BUSY = 0x02U,
335 PIS_STATE_TIMEOUT = 0x03U,
336 PIS_STATE_ERROR = 0x04U,
337 } pis_state_t;
338
342 typedef enum {
343 PIS_UART0_TX = 0U,
344 PIS_UART1_TX = 1U,
345 PIS_UART2_TX = 2U,
346 PIS_UART3_TX = 3U,
347 PIS_LPUART0_TX = 4U,
348 } pis_modu_targ_t;
349
353 typedef enum {
354 PIS_LOW_LEVEL = 0U,
355 PIS_HIGH_LEVEL = 1U,
356 } pis_modu_level_t;
357
361 typedef enum {
362 PIS_SRC_NONE = 0U,
363 PIS_SRC_TIMER0 = 1U,
364 PIS_SRC_TIMER1 = 2U,
365 PIS_SRC_TIMER2 = 3U,
366 PIS_SRC_TIMER3 = 4U,
367 PIS_SRC_TIMER6 = 5U,
368 PIS_SRC_TIMER7 = 6U,
369 PIS_SRC_LPTIM0 = 7U,
370 PIS_SRC_BUZ = 8U,
371 } pis_modu_src_t;
372
376 typedef enum {
377 PIS_TIMER_CH1 = 0U,
378 PIS_TIMER_CH2 = 1U,
379 PIS_TIMER_CH3 = 2U,
380 PIS_TIMER_CH4 = 3U,
381 } pis_modu_channel_t;
382
386 typedef enum {
387 PIS_NONE_INPUT = 0U,
388 PIS_PORT_INPUT = 1U,
389 PIS_CHAN_INPUT = 2U,
390 } pis_input_sel_t;
391
395 typedef struct {
396 pis_src_t producer_src;
397 pis_output_t producer_signal;
398 pis_clock_t producer_clk;
399 pis_edge_t producer_edge;
400 pis_trig_t consumer_trig;
401 pis_clock_t consumer_clk;
402 pis_input_sel_t input_chan;
403 } pis_init_t;
404
408 typedef struct {
409 pis_modu_targ_t target;
410 pis_modu_level_t level;
411 pis_modu_src_t src;
412 pis_modu_channel_t channel;
413 } pis_modulate_config_t;
414
418 typedef struct pis_handle_s {
419 PIS_TypeDef *perh;
420 pis_init_t init;
421 pis_ch_t consumer_ch;
422 pis_con_t consumer_con;
423 uint8_t consumer_pos;
424 uint32_t check_info;
425 lock_state_t lock;
426 pis_state_t state;
427 } pis_handle_t;
436 #define IS_PIS(x) (((x) == PIS))
437 #define IS_PIS_SRC(x) (((x) == PIS_NON) || \
438 ((x) == PIS_GPIO_PIN0) || \
439 ((x) == PIS_GPIO_PIN1) || \
440 ((x) == PIS_GPIO_PIN2) || \
441 ((x) == PIS_GPIO_PIN3) || \
442 ((x) == PIS_GPIO_PIN4) || \
443 ((x) == PIS_GPIO_PIN5) || \
444 ((x) == PIS_GPIO_PIN6) || \
445 ((x) == PIS_GPIO_PIN7) || \
446 ((x) == PIS_GPIO_PIN8) || \
447 ((x) == PIS_GPIO_PIN9) || \
448 ((x) == PIS_GPIO_PIN10) || \
449 ((x) == PIS_GPIO_PIN11) || \
450 ((x) == PIS_GPIO_PIN12) || \
451 ((x) == PIS_GPIO_PIN13) || \
452 ((x) == PIS_GPIO_PIN14) || \
453 ((x) == PIS_GPIO_PIN15) || \
454 ((x) == PIS_ACMP_OUT0) || \
455 ((x) == PIS_ACMP_OUT1) || \
456 ((x) == PIS_DAC0_CH0) || \
457 ((x) == PIS_DAC0_CH1) || \
458 ((x) == PIS_ADC0_INSERT) || \
459 ((x) == PIS_ADC0_NORMAL) || \
460 ((x) == PIS_ADC0_RESERVE) || \
461 ((x) == PIS_LVD) || \
462 ((x) == PIS_UART0_RESERVE0) || \
463 ((x) == PIS_UART0_RESERVE1) || \
464 ((x) == PIS_UART0_IRDAOUT) || \
465 ((x) == PIS_UART0_RTSOUT) || \
466 ((x) == PIS_UART0_TXOUT) || \
467 ((x) == PIS_UART0_SYN_SEND) || \
468 ((x) == PIS_UART0_SYN_RECV) || \
469 ((x) == PIS_UART1_RESERVE0) || \
470 ((x) == PIS_UART1_RESERVE1) || \
471 ((x) == PIS_UART1_IRDA) || \
472 ((x) == PIS_UART1_RTS) || \
473 ((x) == PIS_UART1_TXOUT) || \
474 ((x) == PIS_UART1_SYN_SEND) || \
475 ((x) == PIS_UART1_SYN_RECV) || \
476 ((x) == PIS_UART2_RESERVE0) || \
477 ((x) == PIS_UART2_RESERVE1) || \
478 ((x) == PIS_UART2_IRDA) || \
479 ((x) == PIS_UART2_RTS) || \
480 ((x) == PIS_UART2_TXOUT) || \
481 ((x) == PIS_UART2_SYN_SEND) || \
482 ((x) == PIS_UART2_SYN_RECV) || \
483 ((x) == PIS_UART3_RESERVE0) || \
484 ((x) == PIS_UART3_RESERVE1) || \
485 ((x) == PIS_UART3_IRDA) || \
486 ((x) == PIS_UART3_RTS) || \
487 ((x) == PIS_UART3_TXOUT) || \
488 ((x) == PIS_UART3_SYN_SEND) || \
489 ((x) == PIS_UART3_SYN_RECV) || \
490 ((x) == PIS_UART4_RECV) || \
491 ((x) == PIS_UART4_SEND) || \
492 ((x) == PIS_UART4_TXOUT) || \
493 ((x) == PIS_UART5_RECV) || \
494 ((x) == PIS_UART5_SEND) || \
495 ((x) == PIS_UART5_TXOUT) || \
496 ((x) == PIS_SPI0_RECV) || \
497 ((x) == PIS_SPI0_SEND) || \
498 ((x) == PIS_SPI0_NE) || \
499 ((x) == PIS_SPI1_RECV) || \
500 ((x) == PIS_SPI1_SEND) || \
501 ((x) == PIS_SPI1_NE) || \
502 ((x) == PIS_I2C0_RECV) || \
503 ((x) == PIS_I2C0_SEND) || \
504 ((x) == PIS_I2C1_RECV) || \
505 ((x) == PIS_I2C1_SEND) || \
506 ((x) == PIS_TIMER0_UPDATA) || \
507 ((x) == PIS_TIMER0_TRIG) || \
508 ((x) == PIS_TIMER0_INPUT_1) || \
509 ((x) == PIS_TIMER0_OUTPUT_1) || \
510 ((x) == PIS_TIMER0_INPUT_2) || \
511 ((x) == PIS_TIMER0_OUTPUT_2) || \
512 ((x) == PIS_TIMER0_INPUT_3) || \
513 ((x) == PIS_TIMER0_OUTPUT_3) || \
514 ((x) == PIS_TIMER0_INPUT_4) || \
515 ((x) == PIS_TIMER0_OUTPUT_4) || \
516 ((x) == PIS_TIMER1_UPDATA) || \
517 ((x) == PIS_TIMER1_TRIG) || \
518 ((x) == PIS_TIMER1_INPUT_1) || \
519 ((x) == PIS_TIMER1_OUTPUT_1) || \
520 ((x) == PIS_TIMER1_INPUT_2) || \
521 ((x) == PIS_TIMER1_OUTPUT_2) || \
522 ((x) == PIS_TIMER1_INPUT_3) || \
523 ((x) == PIS_TIMER1_OUTPUT_3) || \
524 ((x) == PIS_TIMER1_INPUT_4) || \
525 ((x) == PIS_TIMER1_OUTPUT_4) || \
526 ((x) == PIS_TIMER2_UPDATA) || \
527 ((x) == PIS_TIMER2_TRIG) || \
528 ((x) == PIS_TIMER2_INPUT_1) || \
529 ((x) == PIS_TIMER2_OUTPUT_1) || \
530 ((x) == PIS_TIMER2_INPUT_2) || \
531 ((x) == PIS_TIMER2_OUTPUT_2) || \
532 ((x) == PIS_TIMER2_INPUT_3) || \
533 ((x) == PIS_TIMER2_OUTPUT_3) || \
534 ((x) == PIS_TIMER2_INPUT_4) || \
535 ((x) == PIS_TIMER2_OUTPUT_4) || \
536 ((x) == PIS_TIMER3_UPDATA) || \
537 ((x) == PIS_TIMER3_TRIG) || \
538 ((x) == PIS_TIMER3_INPUT_1) || \
539 ((x) == PIS_TIMER3_OUTPUT_1) || \
540 ((x) == PIS_TIMER3_INPUT_2) || \
541 ((x) == PIS_TIMER3_OUTPUT_2) || \
542 ((x) == PIS_TIMER3_INPUT_3) || \
543 ((x) == PIS_TIMER3_OUTPUT_3) || \
544 ((x) == PIS_TIMER3_INPUT_4) || \
545 ((x) == PIS_TIMER3_OUTPUT_4) || \
546 ((x) == PIS_RTC_CLOCK) || \
547 ((x) == PIS_RTC_ALARM) || \
548 ((x) == PIS_LPTIMER0_SYN_UPDATA) || \
549 ((x) == PIS_LPTIMER0_ASY_UPDATA) || \
550 ((x) == PIS_LPUART0_ASY_RECV) || \
551 ((x) == PIS_LPUART0_ASY_SEND) || \
552 ((x) == PIS_LPUART0_SYN_RECV) || \
553 ((x) == PIS_LPUART0_SYN_SEND) || \
554 ((x) == PIS_DMA) || \
555 ((x) == PIS_ADC1_INSERT) || \
556 ((x) == PIS_ADC1_NORMAL) || \
557 ((x) == PIS_ADC1_RESERVE))
558 #define IS_PIS_TRIG(x) (((x) == PIS_CH12_TIMER0_ITR0) || \
559 ((x) == PIS_CH13_TIMER0_ITR1) || \
560 ((x) == PIS_CH14_TIMER0_ITR2) || \
561 ((x) == PIS_CH15_TIMER0_ITR3) || \
562 ((x) == PIS_CH12_TIMER1_ITR0) || \
563 ((x) == PIS_CH13_TIMER1_ITR1) || \
564 ((x) == PIS_CH14_TIMER1_ITR2) || \
565 ((x) == PIS_CH15_TIMER1_ITR3) || \
566 ((x) == PIS_CH12_TIMER2_ITR0) || \
567 ((x) == PIS_CH13_TIMER2_ITR1) || \
568 ((x) == PIS_CH14_TIMER2_ITR2) || \
569 ((x) == PIS_CH15_TIMER2_ITR3) || \
570 ((x) == PIS_CH12_TIMER3_ITR0) || \
571 ((x) == PIS_CH13_TIMER3_ITR1) || \
572 ((x) == PIS_CH14_TIMER3_ITR2) || \
573 ((x) == PIS_CH15_TIMER3_ITR3) || \
574 ((x) == PIS_CH6_ADC0_NORMAL ) || \
575 ((x) == PIS_CH7_ADC0_INSERT) || \
576 ((x) == PIS_CH0_ADC1_NORMAL) || \
577 ((x) == PIS_CH1_ADC1_INSERT) || \
578 ((x) == PIS_CH0_LPTIM0_EXT0) || \
579 ((x) == PIS_CH1_LPTIM0_EXT1) || \
580 ((x) == PIS_CH2_LPTIM0_EXT2) || \
581 ((x) == PIS_CH3_LPTIM0_EXT3) || \
582 ((x) == PIS_CH4_LPTIM0_EXT4) || \
583 ((x) == PIS_CH5_LPTIM0_EXT5) || \
584 ((x) == PIS_CH6_LPTIM0_EXT6) || \
585 ((x) == PIS_CH7_LPTIM0_EXT7) || \
586 ((x) == PIS_CH7_DMA_REQUEST) || \
587 ((x) == PIS_CH15_LPUART0_RXD) || \
588 ((x) == PIS_CH14_UART5_RXD) || \
589 ((x) == PIS_CH13_UART4_RXD) || \
590 ((x) == PIS_CH12_UART3_RXD) || \
591 ((x) == PIS_CH11_UART2_RXD) || \
592 ((x) == PIS_CH10_UART1_RXD) || \
593 ((x) == PIS_CH9_UART0_RXD) || \
594 ((x) == PIS_CH8_TIMER3_CH4IN) || \
595 ((x) == PIS_CH8_TIMER2_CH4IN) || \
596 ((x) == PIS_CH8_SPI1_CLK) || \
597 ((x) == PIS_CH7_TIMER3_CH3IN) || \
598 ((x) == PIS_CH7_TIMER2_CH3IN) || \
599 ((x) == PIS_CH7_SPI1_RX) || \
600 ((x) == PIS_CH6_TIMER3_CH2IN) || \
601 ((x) == PIS_CH6_TIMER2_CH2IN) || \
602 ((x) == PIS_CH6_SPI0_CLK) || \
603 ((x) == PIS_CH5_TIMER3_CH1IN) || \
604 ((x) == PIS_CH5_TIMER2_CH1IN) || \
605 ((x) == PIS_CH5_SPI0_RX) || \
606 ((x) == PIS_CH4_TIMER1_CH4IN) || \
607 ((x) == PIS_CH4_TIMER0_CH4IN) || \
608 ((x) == PIS_CH3_TIMER1_CH3IN) || \
609 ((x) == PIS_CH3_TIMER0_CH3IN) || \
610 ((x) == PIS_CH2_TIMER1_CH2IN) || \
611 ((x) == PIS_CH2_TIMER0_CH2IN) || \
612 ((x) == PIS_CH1_TIMER1_CH1IN) || \
613 ((x) == PIS_CH0_TIMER0_CH1IN) || \
614 ((x) == PIS_CH0_TIMER0_BRKIN) || \
615 ((x) == PIS_CH0_TIMER1_BRKIN) || \
616 ((x) == PIS_TRIG_RESERVE) || \
617 ((x) == PIS_CH8_SPI1_CLK))
618 #define IS_PIS_CLOCK(x) (((x) == PIS_CLK_PCLK1) || \
619 ((x) == PIS_CLK_PCLK2) || \
620 ((x) == PIS_CLK_SYS))
621 #define IS_PIS_SIGNAL_MODE(x) (((x) == PIS_OUT_LEVEL) || \
622 ((x) == PIS_OUT_PULSE))
623 #define IS_PIS_EDGE(x) (((x) == PIS_EDGE_NONE) || \
624 ((x) == PIS_EDGE_UP) || \
625 ((x) == PIS_EDGE_DOWN) || \
626 ((x) == PIS_EDGE_UP_DOWN))
627 #define IS_PIS_OUTPUT(x) (((x) == PIS_OUT_LEVEL) || \
628 ((x) == PIS_OUT_PULSE))
629 #define IS_PIS_OUPUT_CH(x) (((x) == PIS_OUT_CH_0) || \
630 ((x) == PIS_OUT_CH_1) || \
631 ((x) == PIS_OUT_CH_2) || \
632 ((x) == PIS_OUT_CH_3))
633 #define IS_PIS_MODU_TARGET(x) (((x) == PIS_UART0_TX) || \
634 ((x) == PIS_UART1_TX) || \
635 ((x) == PIS_UART2_TX) || \
636 ((x) == PIS_UART3_TX) || \
637 ((x) == PIS_LPUART0_TX))
638 #define IS_PIS_MODU_LEVEL(x) (((x) == PIS_LOW_LEVEL) || \
639 ((x) == PIS_HIGH_LEVEL))
640 #define IS_PIS_MODU_SRC(x) (((x) == PIS_SRC_NONE) || \
641 ((x) == PIS_SRC_TIMER0) || \
642 ((x) == PIS_SRC_TIMER1) || \
643 ((x) == PIS_SRC_TIMER2) || \
644 ((x) == PIS_SRC_TIMER3) || \
645 ((x) == PIS_SRC_TIMER6) || \
646 ((x) == PIS_SRC_TIMER7) || \
647 ((x) == PIS_SRC_LPTIM0) || \
648 ((x) == PIS_SRC_BUZ))
649 #define IS_PIS_MODU_CHANNEL(x) (((x) == PIS_TIMER_CH1) || \
650 ((x) == PIS_TIMER_CH2) || \
651 ((x) == PIS_TIMER_CH3) || \
652 ((x) == PIS_TIMER_CH4))
653
664 ald_status_t ald_pis_create(pis_handle_t *hperh);
665 ald_status_t ald_pis_destroy(pis_handle_t *hperh);
673 ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch);
674 ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch);
682 pis_state_t ald_pis_get_state(pis_handle_t *hperh);
690 ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config);
707 #ifdef __cplusplus
708 }
709 #endif
710
711 #endif /* __ALD_PIS_H__ */
pis_modulate_config_t::level
pis_modu_level_t level
Definition: ald_pis.h:410
PIS_SRC_BUZ
Definition: ald_pis.h:370
PIS_UART0_IRDAOUT
Definition: ald_pis.h:86
PIS_ADC0_INSERT
Definition: ald_pis.h:80
PIS_TIMER0_TRIG
Definition: ald_pis.h:129
PIS_CH5_TIMER2_CH1IN
Definition: ald_pis.h:232
PIS_LVD
Definition: ald_pis.h:83
PIS_CH13_UART4_RXD
Definition: ald_pis.h:217
PIS_PORT_INPUT
Definition: ald_pis.h:388
pis_modulate_config_t::target
pis_modu_targ_t target
Definition: ald_pis.h:409
PIS_STATE_BUSY
Definition: ald_pis.h:334
PIS_TIMER0_INPUT_4
Definition: ald_pis.h:136
PIS_TIMER0_UPDATA
Definition: ald_pis.h:128
PIS_SRC_TIMER0
Definition: ald_pis.h:363
PIS_TIMER1_UPDATA
Definition: ald_pis.h:138
PIS_STATE_RESET
Definition: ald_pis.h:332
PIS_CH_13
Definition: ald_pis.h:304
PIS_TIMER2_UPDATA
Definition: ald_pis.h:148
PIS_UART0_RESERVE0
Definition: ald_pis.h:84
PIS_SPI0_RECV
Definition: ald_pis.h:118
pis_modulate_config_t
PIS modulate config structure definition.
Definition: ald_pis.h:408
PIS_CH_4
Definition: ald_pis.h:295
PIS_LOW_LEVEL
Definition: ald_pis.h:354
PIS_STATE_ERROR
Definition: ald_pis.h:336
PIS_UART2_RESERVE1
Definition: ald_pis.h:99
PIS_UART4_TXOUT
Definition: ald_pis.h:114
PIS_GPIO_PIN14
Definition: ald_pis.h:74
PIS_NONE_INPUT
Definition: ald_pis.h:387
PIS_GPIO_PIN3
Definition: ald_pis.h:63
PIS_CH13_TIMER3_ITR1
Definition: ald_pis.h:199
PIS_CH5_SPI0_RX
Definition: ald_pis.h:233
PIS_OUT_CH_0
Definition: ald_pis.h:313
PIS_I2C1_RECV
Definition: ald_pis.h:126
PIS_LPTIMER0_SYN_UPDATA
Definition: ald_pis.h:170
PIS_CH4_TIMER1_CH4IN
Definition: ald_pis.h:234
PIS_ADC1_RESERVE
Definition: ald_pis.h:179
PIS_UART3_IRDA
Definition: ald_pis.h:107
PIS_UART2_RTS
Definition: ald_pis.h:101
PIS_UART2_TXOUT
Definition: ald_pis.h:102
PIS_CH3_TIMER0_CH3IN
Definition: ald_pis.h:237
PIS_ADC1_NORMAL
Definition: ald_pis.h:178
PIS_UART5_SEND
Definition: ald_pis.h:116
PIS_GPIO_PIN1
Definition: ald_pis.h:61
PIS_CH12_TIMER0_ITR0
Definition: ald_pis.h:186
PIS_UART3_SYN_SEND
Definition: ald_pis.h:110
PIS_SPI0_NE
Definition: ald_pis.h:120
PIS_CH7_LPTIM0_EXT7
Definition: ald_pis.h:213
ald_pis_destroy
ald_status_t ald_pis_destroy(pis_handle_t *hperh)
Destroy the PIS mode according to the specified parameters in the pis_init_t and create the associate...
Definition: ald_pis.c:127
PIS_TIMER3_INPUT_4
Definition: ald_pis.h:166
pis_con_t
pis_con_t
Indirect value,no care of it.
Definition: ald_pis.h:322
PIS_CH7_TIMER3_CH3IN
Definition: ald_pis.h:225
PIS_CH13_TIMER0_ITR1
Definition: ald_pis.h:187
PIS_CLK_PCLK1
Definition: ald_pis.h:251
PIS_DAC0_CH1
Definition: ald_pis.h:79
PIS_OUT_LEVEL
Definition: ald_pis.h:271
PIS_UART1_SYN_SEND
Definition: ald_pis.h:96
PIS_CH_0
Definition: ald_pis.h:291
PIS_LPTIMER0_ASY_UPDATA
Definition: ald_pis.h:171
PIS_UART4_RECV
Definition: ald_pis.h:112
PIS_TIMER1_OUTPUT_4
Definition: ald_pis.h:147
PIS_CH13_TIMER2_ITR1
Definition: ald_pis.h:195
PIS_GPIO_PIN7
Definition: ald_pis.h:67
PIS_CH6_LPTIM0_EXT6
Definition: ald_pis.h:212
pis_init_t::producer_src
pis_src_t producer_src
Definition: ald_pis.h:396
PIS_EDGE_UP_DOWN
Definition: ald_pis.h:264
PIS_CH7_SPI1_RX
Definition: ald_pis.h:227
PIS_CON_1
Definition: ald_pis.h:324
PIS_SYN_PULSE_ASY_APB2
Definition: ald_pis.h:283
PIS_CH7_DMA_REQUEST
Definition: ald_pis.h:214
PIS_UART1_IRDA
Definition: ald_pis.h:93
PIS_EDGE_DOWN
Definition: ald_pis.h:263
PIS_SPI1_NE
Definition: ald_pis.h:123
PIS_CH_7
Definition: ald_pis.h:298
PIS_CH_6
Definition: ald_pis.h:297
PIS_UART2_SYN_SEND
Definition: ald_pis.h:103
PIS_TIMER2_OUTPUT_3
Definition: ald_pis.h:155
PIS_ADC1_INSERT
Definition: ald_pis.h:177
PIS_GPIO_PIN6
Definition: ald_pis.h:66
PIS_UART0_SYN_RECV
Definition: ald_pis.h:90
PIS_TIMER0_INPUT_2
Definition: ald_pis.h:132
pis_handle_s::consumer_ch
pis_ch_t consumer_ch
Definition: ald_pis.h:421
pis_modu_src_t
pis_modu_src_t
PIS modulate source.
Definition: ald_pis.h:361
PIS_EDGE_UP
Definition: ald_pis.h:262
PIS_LPUART0_ASY_RECV
Definition: ald_pis.h:172
PIS_TIMER0_OUTPUT_4
Definition: ald_pis.h:137
PIS_UART5_TXOUT
Definition: ald_pis.h:117
PIS_CH0_LPTIM0_EXT0
Definition: ald_pis.h:206
pis_input_sel_t
pis_input_sel_t
PIS input channel chose.
Definition: ald_pis.h:386
PIS_CH_15
Definition: ald_pis.h:306
pis_state_t
pis_state_t
PIS state structures definition.
Definition: ald_pis.h:331
pis_handle_s
PIS Handle Structure definition.
Definition: ald_pis.h:418
PIS_SYN_PULSE_ASY_AHB
Definition: ald_pis.h:284
pis_ch_t
pis_ch_t
Pis channel.
Definition: ald_pis.h:290
PIS_CH5_TIMER3_CH1IN
Definition: ald_pis.h:231
PIS_UART2_TX
Definition: ald_pis.h:345
pis_modulate_config_t::src
pis_modu_src_t src
Definition: ald_pis.h:411
PIS_TIMER3_INPUT_2
Definition: ald_pis.h:162
PIS_TRIG_RESERVE
Definition: ald_pis.h:244
PIS_CH0_TIMER0_BRKIN
Definition: ald_pis.h:242
PIS_UART1_RTS
Definition: ald_pis.h:94
pis_modu_channel_t
pis_modu_channel_t
PIS modulate channel.
Definition: ald_pis.h:376
PIS_UART1_TXOUT
Definition: ald_pis.h:95
PIS_CH6_SPI0_CLK
Definition: ald_pis.h:230
PIS_UART2_SYN_RECV
Definition: ald_pis.h:104
PIS_SRC_TIMER6
Definition: ald_pis.h:367
pis_handle_s::lock
lock_state_t lock
Definition: ald_pis.h:425
PIS_SPI0_SEND
Definition: ald_pis.h:119
PIS_UART5_RECV
Definition: ald_pis.h:115
utils.h
This file contains the Utilities functions/types for the driver.
PIS_CH8_TIMER2_CH4IN
Definition: ald_pis.h:223
PIS_TIMER1_INPUT_1
Definition: ald_pis.h:140
PIS_UART0_RESERVE1
Definition: ald_pis.h:85
pis_handle_t
struct pis_handle_s pis_handle_t
PIS Handle Structure definition.
pis_syncsel_t
pis_syncsel_t
Sync select.
Definition: ald_pis.h:277
PIS_CH5_LPTIM0_EXT5
Definition: ald_pis.h:211
PIS_CH8_TIMER3_CH4IN
Definition: ald_pis.h:222
PIS_SRC_TIMER2
Definition: ald_pis.h:365
PIS_GPIO_PIN4
Definition: ald_pis.h:64
PIS_CH2_TIMER0_CH2IN
Definition: ald_pis.h:239
pis_clock_t
pis_clock_t
Clock select.
Definition: ald_pis.h:250
PIS_HIGH_LEVEL
Definition: ald_pis.h:355
PIS_CH_8
Definition: ald_pis.h:299
ald_pis_get_state
pis_state_t ald_pis_get_state(pis_handle_t *hperh)
Returns the PIS state.
Definition: ald_pis.c:224
PIS_CON_NONE
Definition: ald_pis.h:325
PIS_TIMER3_OUTPUT_3
Definition: ald_pis.h:165
PIS_SRC_TIMER7
Definition: ald_pis.h:368
PIS_TIMER0_OUTPUT_2
Definition: ald_pis.h:133
PIS_UART3_SYN_RECV
Definition: ald_pis.h:111
PIS_TIMER2_OUTPUT_1
Definition: ald_pis.h:151
PIS_CHAN_INPUT
Definition: ald_pis.h:389
PIS_TIMER2_OUTPUT_4
Definition: ald_pis.h:157
PIS_UART1_TX
Definition: ald_pis.h:344
PIS_LPUART0_SYN_SEND
Definition: ald_pis.h:175
PIS_GPIO_PIN5
Definition: ald_pis.h:65
PIS_UART0_RTSOUT
Definition: ald_pis.h:87
PIS_ACMP_OUT1
Definition: ald_pis.h:77
PIS_TIMER2_INPUT_4
Definition: ald_pis.h:156
PIS_CLK_SYS
Definition: ald_pis.h:253
PIS_OUT_CH_1
Definition: ald_pis.h:314
pis_init_t::input_chan
pis_input_sel_t input_chan
Definition: ald_pis.h:402
PIS_TIMER1_OUTPUT_2
Definition: ald_pis.h:143
PIS_CH4_LPTIM0_EXT4
Definition: ald_pis.h:210
PIS_GPIO_PIN11
Definition: ald_pis.h:71
PIS_SRC_TIMER1
Definition: ald_pis.h:364
PIS_SRC_LPTIM0
Definition: ald_pis.h:369
PIS_CH9_UART0_RXD
Definition: ald_pis.h:221
pis_modulate_config_t::channel
pis_modu_channel_t channel
Definition: ald_pis.h:412
PIS_TIMER_CH2
Definition: ald_pis.h:378
PIS_CH_10
Definition: ald_pis.h:301
lock_state_t
lock_state_t
Definition: type.h:58
PIS_TIMER3_INPUT_1
Definition: ald_pis.h:160
PIS_UART3_TXOUT
Definition: ald_pis.h:109
PIS_CH6_TIMER2_CH2IN
Definition: ald_pis.h:229
PIS_UART1_RESERVE1
Definition: ald_pis.h:92
PIS_DMA
Definition: ald_pis.h:176
PIS_EDGE_NONE
Definition: ald_pis.h:261
PIS_GPIO_PIN15
Definition: ald_pis.h:75
pis_output_t
pis_output_t
Output style.
Definition: ald_pis.h:270
PIS_TIMER_CH3
Definition: ald_pis.h:379
PIS_CH6_TIMER3_CH2IN
Definition: ald_pis.h:228
PIS_CH2_TIMER1_CH2IN
Definition: ald_pis.h:238
PIS_TIMER2_INPUT_2
Definition: ald_pis.h:152
PIS_TIMER3_OUTPUT_4
Definition: ald_pis.h:167
PIS_SYN_LEVEL_ASY_AHB
Definition: ald_pis.h:281
PIS_CH6_ADC0_NORMAL
Definition: ald_pis.h:202
PIS_CH_5
Definition: ald_pis.h:296
PIS_CH7_ADC0_INSERT
Definition: ald_pis.h:203
pis_edge_t
pis_edge_t
Level select.
Definition: ald_pis.h:260
pis_init_t::producer_signal
pis_output_t producer_signal
Definition: ald_pis.h:397
pis_modu_targ_t
pis_modu_targ_t
PIS modulate target.
Definition: ald_pis.h:342
pis_init_t::producer_edge
pis_edge_t producer_edge
Definition: ald_pis.h:399
PIS_CON_0
Definition: ald_pis.h:323
PIS_CH12_UART3_RXD
Definition: ald_pis.h:218
PIS_CH_14
Definition: ald_pis.h:305
PIS_CH14_UART5_RXD
Definition: ald_pis.h:216
PIS_TIMER0_OUTPUT_3
Definition: ald_pis.h:135
PIS_SYN_LEVEL_ASY_APB1
Definition: ald_pis.h:279
PIS_OUT_CH_2
Definition: ald_pis.h:315
PIS_TIMER2_OUTPUT_2
Definition: ald_pis.h:153
PIS_TIMER0_OUTPUT_1
Definition: ald_pis.h:131
PIS_TIMER2_INPUT_1
Definition: ald_pis.h:150
PIS_CH12_TIMER2_ITR0
Definition: ald_pis.h:194
PIS_TIMER2_INPUT_3
Definition: ald_pis.h:154
PIS_CH11_UART2_RXD
Definition: ald_pis.h:219
pis_handle_s::consumer_pos
uint8_t consumer_pos
Definition: ald_pis.h:423
PIS_CH14_TIMER3_ITR2
Definition: ald_pis.h:200
PIS_GPIO_PIN2
Definition: ald_pis.h:62
PIS_UART0_TXOUT
Definition: ald_pis.h:88
PIS_CH15_TIMER0_ITR3
Definition: ald_pis.h:189
PIS_UART2_IRDA
Definition: ald_pis.h:100
PIS_ACMP_OUT0
Definition: ald_pis.h:76
PIS_CH12_TIMER3_ITR0
Definition: ald_pis.h:198
PIS_TIMER1_OUTPUT_3
Definition: ald_pis.h:145
PIS_CH14_TIMER0_ITR2
Definition: ald_pis.h:188
PIS_GPIO_PIN13
Definition: ald_pis.h:73
ald_pis_create
ald_status_t ald_pis_create(pis_handle_t *hperh)
Create the PIS mode according to the specified parameters in the pis_handle_t and create the associat...
Definition: ald_pis.c:45
pis_handle_s::state
pis_state_t state
Definition: ald_pis.h:426
PIS_UART1_SYN_RECV
Definition: ald_pis.h:97
PIS_GPIO_PIN10
Definition: ald_pis.h:70
PIS_SYN_DIRECT
Definition: ald_pis.h:278
ald_pis_modu_config
ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config)
Config the PIS modulate signal function.
Definition: ald_pis.c:248
PIS_UART0_SYN_SEND
Definition: ald_pis.h:89
PIS_CH_2
Definition: ald_pis.h:293
PIS_UART3_RESERVE1
Definition: ald_pis.h:106
PIS_TIMER_CH4
Definition: ald_pis.h:380
PIS_SRC_NONE
Definition: ald_pis.h:362
PIS_CH14_TIMER2_ITR2
Definition: ald_pis.h:196
pis_modu_level_t
pis_modu_level_t
PIS modulate level.
Definition: ald_pis.h:353
PIS_UART1_RESERVE0
Definition: ald_pis.h:91
PIS_RTC_CLOCK
Definition: ald_pis.h:168
PIS_CH1_TIMER1_CH1IN
Definition: ald_pis.h:240
PIS_TIMER3_OUTPUT_1
Definition: ald_pis.h:161
PIS_I2C0_RECV
Definition: ald_pis.h:124
PIS_CH3_TIMER1_CH3IN
Definition: ald_pis.h:236
PIS_GPIO_PIN8
Definition: ald_pis.h:68
PIS_CH1_ADC1_INSERT
Definition: ald_pis.h:205
PIS_OUT_PULSE
Definition: ald_pis.h:272
PIS_UART3_RTS
Definition: ald_pis.h:108
PIS_CH15_TIMER2_ITR3
Definition: ald_pis.h:197
PIS_CH15_LPUART0_RXD
Definition: ald_pis.h:215
PIS_GPIO_PIN12
Definition: ald_pis.h:72
PIS_TIMER0_INPUT_1
Definition: ald_pis.h:130
PIS_I2C1_SEND
Definition: ald_pis.h:127
PIS_CLK_PCLK2
Definition: ald_pis.h:252
PIS_CH0_TIMER1_BRKIN
Definition: ald_pis.h:243
PIS_RTC_ALARM
Definition: ald_pis.h:169
PIS_CH8_SPI1_CLK
Definition: ald_pis.h:224
PIS_CH12_TIMER1_ITR0
Definition: ald_pis.h:190
pis_handle_s::perh
PIS_TypeDef * perh
Definition: ald_pis.h:419
PIS_TIMER1_INPUT_4
Definition: ald_pis.h:146
PIS_CH1_LPTIM0_EXT1
Definition: ald_pis.h:207
PIS_NON
Definition: ald_pis.h:59
PIS_STATE_TIMEOUT
Definition: ald_pis.h:335
PIS_TIMER1_OUTPUT_1
Definition: ald_pis.h:141
PIS_CH2_LPTIM0_EXT2
Definition: ald_pis.h:208
pis_handle_s::consumer_con
pis_con_t consumer_con
Definition: ald_pis.h:422
PIS_GPIO_PIN0
Definition: ald_pis.h:60
PIS_UART2_RESERVE0
Definition: ald_pis.h:98
PIS_UART3_RESERVE0
Definition: ald_pis.h:105
PIS_CH_12
Definition: ald_pis.h:303
PIS_TIMER3_OUTPUT_2
Definition: ald_pis.h:163
PIS_LPUART0_TX
Definition: ald_pis.h:347
PIS_TIMER1_INPUT_3
Definition: ald_pis.h:144
PIS_UART3_TX
Definition: ald_pis.h:346
PIS_CH7_TIMER2_CH3IN
Definition: ald_pis.h:226
PIS_TIMER3_TRIG
Definition: ald_pis.h:159
pis_init_t::producer_clk
pis_clock_t producer_clk
Definition: ald_pis.h:398
PIS_TIMER2_TRIG
Definition: ald_pis.h:149
PIS_I2C0_SEND
Definition: ald_pis.h:125
pis_init_t
PIS init structure definition.
Definition: ald_pis.h:395
PIS_GPIO_PIN9
Definition: ald_pis.h:69
pis_handle_s::init
pis_init_t init
Definition: ald_pis.h:420
PIS_CH15_TIMER1_ITR3
Definition: ald_pis.h:193
PIS_CH_9
Definition: ald_pis.h:300
PIS_CH14_TIMER1_ITR2
Definition: ald_pis.h:192
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
PIS_LPUART0_SYN_RECV
Definition: ald_pis.h:174
PIS_ADC0_NORMAL
Definition: ald_pis.h:81
PIS_CH3_LPTIM0_EXT3
Definition: ald_pis.h:209
pis_init_t::consumer_trig
pis_trig_t consumer_trig
Definition: ald_pis.h:400
PIS_DAC0_CH0
Definition: ald_pis.h:78
PIS_CH0_ADC1_NORMAL
Definition: ald_pis.h:204
PIS_CH4_TIMER0_CH4IN
Definition: ald_pis.h:235
pis_handle_s::check_info
uint32_t check_info
Definition: ald_pis.h:424
PIS_CH0_TIMER0_CH1IN
Definition: ald_pis.h:241
PIS_SYN_PULSE_ASY_APB1
Definition: ald_pis.h:282
PIS_CH_3
Definition: ald_pis.h:294
PIS_CH10_UART1_RXD
Definition: ald_pis.h:220
PIS_SRC_TIMER3
Definition: ald_pis.h:366
PIS_STATE_READY
Definition: ald_pis.h:333
PIS_OUT_CH_3
Definition: ald_pis.h:316
pis_trig_t
pis_trig_t
Consumer entry.
Definition: ald_pis.h:185
PIS_TIMER_CH1
Definition: ald_pis.h:377
PIS_ADC0_RESERVE
Definition: ald_pis.h:82
PIS_CH13_TIMER1_ITR1
Definition: ald_pis.h:191
PIS_UART4_SEND
Definition: ald_pis.h:113
PIS_UART0_TX
Definition: ald_pis.h:343
PIS_SPI1_RECV
Definition: ald_pis.h:121
pis_src_t
pis_src_t
Producer entry.
Definition: ald_pis.h:58
PIS_TIMER1_INPUT_2
Definition: ald_pis.h:142
PIS_CH15_TIMER3_ITR3
Definition: ald_pis.h:201
PIS_TIMER1_TRIG
Definition: ald_pis.h:139
ald_pis_output_start
ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch)
Start the PIS output function.
Definition: ald_pis.c:176
PIS_TIMER3_UPDATA
Definition: ald_pis.h:158
PIS_CLK_RESERVE
Definition: ald_pis.h:254
PIS_CH_11
Definition: ald_pis.h:302
PIS_CH_1
Definition: ald_pis.h:292
PIS_TIMER3_INPUT_3
Definition: ald_pis.h:164
PIS_LPUART0_ASY_SEND
Definition: ald_pis.h:173
PIS_TIMER0_INPUT_3
Definition: ald_pis.h:134
ald_pis_output_stop
ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch)
Stop the PIS output function.
Definition: ald_pis.c:199
PIS_SPI1_SEND
Definition: ald_pis.h:122
pis_out_ch_t
pis_out_ch_t
Pis output channel.
Definition: ald_pis.h:312
pis_init_t::consumer_clk
pis_clock_t consumer_clk
Definition: ald_pis.h:401
PIS_SYN_LEVEL_ASY_APB2
Definition: ald_pis.h:280


ALD User Manual: D:/svn/src/ald_pmu.c Source File

  • D:
  • svn
  • src
ald_pmu.c
Go to the documentation of this file.
1
17 #include "ald_pmu.h"
18 #include "ald_bkpc.h"
19
20
29 #ifdef ALD_PMU
30
31
40 void ald_lvd_irq_handler(void)
41 {
42 SYSCFG_UNLOCK();
43 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
44 SYSCFG_LOCK();
45
46 return;
47 }
78 void ald_pmu_stop1_enter(void)
79 {
80 int cnt = 4000;
81
82 SYSCFG_UNLOCK();
83
84 CLEAR_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK);
85 #ifdef ES32F336x /* MCU Series: ES32F336x */
86 SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK);
87 #endif
88 MODIFY_REG(PMU->CR1, PMU_CR1_LDO18MOD_MSK, PMU_LDO_18_HOLD << PMU_CR1_LDO18MOD_POSS);
89 MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STOP1 << PMU_CR0_LPM_POSS);
90 SYSCFG_LOCK();
91
92 while ((!(PMU->CR1 & PMU_CR1_LDO18RDY_MSK)) && (cnt--));
93
94 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
95 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
96 __WFI();
97 SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
98
99 return;
100 }
101
106 void ald_pmu_stop2_enter(void)
107 {
108 int cnt = 4000;
109
110 SYSCFG_UNLOCK();
111
112 SET_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK);
113 #ifdef ES32F336x /* MCU Series: ES32F336x */
114 SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK);
115 #endif
116 MODIFY_REG(PMU->CR1, PMU_CR1_LDO18MOD_MSK, PMU_LDO_18_HOLD << PMU_CR1_LDO18MOD_POSS);
117 MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STOP2 << PMU_CR0_LPM_POSS);
118 SYSCFG_LOCK();
119
120 while ((!(PMU->CR1 & PMU_CR1_LDO18RDY_MSK)) && (cnt--));
121
122 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
123 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
124 __WFI();
125 SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
126
127 return;
128 }
129
136 void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
137 {
138 ald_bkpc_standby_wakeup_config(port, level);
139
140 SYSCFG_UNLOCK();
141 MODIFY_REG(PMU->CR0, PMU_CR0_LPM_MSK, PMU_LP_STANDBY << PMU_CR0_LPM_POSS);
142 SYSCFG_LOCK();
143
144 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
145 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
146 __WFI();
147 SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
148
149 return;
150 }
151
157 void ald_pmu_ldo_12_config(type_func_t state)
158 {
159 assert_param(IS_FUNC_STATE(state));
160 SYSCFG_UNLOCK();
161
162 if (state)
163 SET_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK);
164 else
165 CLEAR_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK);
166
167 SYSCFG_LOCK();
168 return;
169 }
170
176 void ald_pmu_ldo_18_config(pmu_ldo_18_mode_t mode)
177 {
178 uint32_t cnt = 4000;
179
180 assert_param(IS_PMU_LDO18_MODE(mode));
181
182 SYSCFG_UNLOCK();
183 MODIFY_REG(PMU->CR1, PMU_CR1_LDO18MOD_MSK, mode << PMU_CR1_LDO18MOD_POSS);
184 SYSCFG_LOCK();
185
186 while ((!(PMU->CR1 & PMU_CR1_LDO18RDY_MSK)) && (cnt--));
187 return;
188 }
189
190 #ifdef ES32F336x /* MCU Series: ES32F336x */
191
199 void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state)
200 {
201 assert_param(IS_FUNC_STATE(state));
202 SYSCFG_UNLOCK();
203
204 if (state) {
205 assert_param(IS_PMU_LDO_LPMODE_OUTPUT(vol));
206
207 MODIFY_REG(PMU->CR0, PMU_CR0_LPVS_MSK, vol << PMU_CR0_LPVS_POSS);
208 SET_BIT(PMU->CR0, PMU_CR0_LPRUN_MSK);
209 }
210 else {
211 CLEAR_BIT(PMU->CR0, PMU_CR0_LPRUN_MSK);
212 }
213
214 SYSCFG_LOCK();
215 return;
216 }
217 #endif
218
224 flag_status_t ald_pmu_get_status(pmu_status_t sr)
225 {
226 assert_param(IS_PMU_STATUS(sr));
227
228 if (READ_BIT(PMU->SR, sr))
229 return SET;
230
231 return RESET;
232 }
233
239 void ald_pmu_clear_status(pmu_status_t sr)
240 {
241 assert_param(IS_PMU_STATUS(sr));
242 SYSCFG_UNLOCK();
243
244 if (sr == PMU_SR_WUF)
245 SET_BIT(PMU->CR0, PMU_CR0_CWUF_MSK);
246 else if (sr == PMU_SR_STANDBYF)
247 SET_BIT(PMU->CR0, PMU_CR0_CSTANDBYF_MSK);
248 else
249 ;/* do nothing */
250
251 SYSCFG_LOCK();
252 return;
253 }
254
261 void ald_pmu_perh_power_config(pmu_perh_power_t perh, type_func_t state)
262 {
263 assert_param(IS_PMU_PERH_POWER(perh));
264 assert_param(IS_FUNC_STATE(state));
265
266 SYSCFG_UNLOCK();
267
268 if (state)
269 SET_BIT(PMU->PWRCR, perh);
270 else
271 CLEAR_BIT(PMU->PWRCR, perh);
272
273 SYSCFG_LOCK();
274 return;
275 }
301 void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state)
302 {
303 assert_param(IS_FUNC_STATE(state));
304 SYSCFG_UNLOCK();
305
306 if (state) {
307 assert_param(IS_PMU_LVD_VOL_SEL(sel));
308 assert_param(IS_PMU_LVD_TRIGGER_MODE(mode));
309
310 MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, sel << PMU_LVDCR_LVDS_POSS);
311 MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVIFS_MSK, mode << PMU_LVDCR_LVIFS_POSS);
312 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK);
313 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
314 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK);
315 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK);
316 }
317 else {
318 SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
319 CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK);
320 CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK);
321 }
322
323 SYSCFG_LOCK();
324 return;
325 }
334 #endif /* ALD_PMU */
335
PMU_SR_STANDBYF
Definition: ald_pmu.h:119
ald_pmu_lvd_config
void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state)
Configure lvd using specified parameters.
Definition: ald_pmu.c:301
ald_pmu_ldo_12_config
void ald_pmu_ldo_12_config(type_func_t state)
Enable/Disable LDO(1.2V) hold mode. It must be disabled in STOP1.
Definition: ald_pmu.c:157
PMU_SR_WUF
Definition: ald_pmu.h:118
bkpc_wakeup_port_t
bkpc_wakeup_port_t
Standby wakeup port select.
Definition: ald_bkpc.h:111
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
type_func_t
type_func_t
Definition: type.h:47
ald_pmu_perh_power_config
void ald_pmu_perh_power_config(pmu_perh_power_t perh, type_func_t state)
Configure peripheral power.
Definition: ald_pmu.c:261
IS_PMU_STATUS
#define IS_PMU_STATUS(x)
Definition: ald_pmu.h:194
ald_bkpc_standby_wakeup_config
void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
Configure standby wakeup in backup field.
Definition: ald_bkpc.c:57
RESET
Definition: type.h:38
pmu_lvd_trigger_mode_t
pmu_lvd_trigger_mode_t
LVD trigger mode.
Definition: ald_pmu.h:148
ald_lvd_irq_handler
void ald_lvd_irq_handler(void)
PMU module interrupt handler.
Definition: ald_pmu.c:40
ald_bkpc.h
Header file of BKPC module driver.
PMU_LDO_18_HOLD
Definition: ald_pmu.h:113
ald_pmu_ldo_18_config
void ald_pmu_ldo_18_config(pmu_ldo_18_mode_t mode)
Configure LDO(1.8V) mode.
Definition: ald_pmu.c:176
IS_PMU_LVD_VOL_SEL
#define IS_PMU_LVD_VOL_SEL(x)
Definition: ald_pmu.h:198
pmu_perh_power_t
pmu_perh_power_t
Definition: ald_pmu.h:166
IS_PMU_LDO_LPMODE_OUTPUT
#define IS_PMU_LDO_LPMODE_OUTPUT(x)
Definition: ald_pmu.h:218
pmu_status_t
pmu_status_t
Definition: ald_pmu.h:117
IS_PMU_LVD_TRIGGER_MODE
#define IS_PMU_LVD_TRIGGER_MODE(x)
Definition: ald_pmu.h:213
ald_pmu_stop1_enter
void ald_pmu_stop1_enter(void)
Enter stop1 mode.
Definition: ald_pmu.c:78
pmu_ldo_lpmode_output_t
pmu_ldo_lpmode_output_t
LDO output voltage selest in low power mode.
Definition: ald_pmu.h:159
ald_pmu_get_status
flag_status_t ald_pmu_get_status(pmu_status_t sr)
Get wakup status.
Definition: ald_pmu.c:224
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
pmu_ldo_18_mode_t
pmu_ldo_18_mode_t
LDO_18 mode.
Definition: ald_pmu.h:110
ald_pmu_standby_enter
void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
Enter standby mode.
Definition: ald_pmu.c:136
pmu_lvd_voltage_sel_t
pmu_lvd_voltage_sel_t
LVD voltage select.
Definition: ald_pmu.h:127
PMU_LP_STOP2
Definition: ald_pmu.h:103
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_PMU_LDO18_MODE
#define IS_PMU_LDO18_MODE(x)
Definition: ald_pmu.h:190
flag_status_t
flag_status_t
Definition: type.h:37
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
bkpc_wakeup_level_t
bkpc_wakeup_level_t
Standby wakeup level.
Definition: ald_bkpc.h:126
PMU_LP_STANDBY
Definition: ald_pmu.h:104
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
ald_pmu_clear_status
void ald_pmu_clear_status(pmu_status_t sr)
Clear wakup status.
Definition: ald_pmu.c:239
ald_pmu_stop2_enter
void ald_pmu_stop2_enter(void)
Enter stop2 mode.
Definition: ald_pmu.c:106
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
PMU_LP_STOP1
Definition: ald_pmu.h:102
IS_PMU_PERH_POWER
#define IS_PMU_PERH_POWER(x)
Definition: ald_pmu.h:222
ald_pmu.h
Header file of PMU module driver.


ALD User Manual: D:/svn/src/ald_pmu.h Source File

  • D:
  • svn
  • src
ald_pmu.h
Go to the documentation of this file.
1
17 #ifndef __ALD_PMU_H__
18 #define __ALD_PMU_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25 #include "ald_syscfg.h"
26 #include "ald_bkpc.h"
27
28
40 #define PMU_LPSTOP_ENABLE() \
41 do { \
42 SYSCFG_UNLOCK(); \
43 SET_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); \
44 SYSCFG_LOCK(); \
45 } while (0)
46 #define PMU_LPSTOP_DISABLE() \
47 do { \
48 SYSCFG_UNLOCK(); \
49 CLEAR_BIT(PMU->CR0, PMU_CR0_LPSTOP_MSK); \
50 SYSCFG_LOCK(); \
51 } while (0)
52 #define PMU_FLASH_MODE_IDLE() \
53 do { \
54 SYSCFG_UNLOCK(); \
55 CLEAR_BIT(PMU->CR0, PMU_CR0_SFPD_MSK); \
56 SYSCFG_LOCK(); \
57 } while (0)
58 #define PMU_FLASH_MODE_WAIT() \
59 do { \
60 SYSCFG_UNLOCK(); \
61 SET_BIT(PMU->CR0, PMU_CR0_SFPD_MSK); \
62 SYSCFG_LOCK(); \
63 } while (0)
64 #define PMU_MTSTOP_ENABLE() \
65 do { \
66 SYSCFG_UNLOCK(); \
67 SET_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); \
68 SYSCFG_LOCK(); \
69 } while (0)
70 #define PMU_MTSTOP_DISABLE() \
71 do { \
72 SYSCFG_UNLOCK(); \
73 CLEAR_BIT(PMU->CR0, PMU_CR0_MTSTOP_MSK); \
74 SYSCFG_LOCK(); \
75 } while (0)
76 #define PMU_VREF_ENABLE() \
77 do { \
78 SYSCFG_UNLOCK(); \
79 SET_BIT(PMU->VREFCR, PMU_VREFCR_VREFEN_MSK); \
80 SYSCFG_LOCK(); \
81 } while (0)
82 #define PMU_VREF_DISABLE() \
83 do { \
84 SYSCFG_UNLOCK(); \
85 CLEAR_BIT(PMU->VREFCR, PMU_VREFCR_VREFEN_MSK); \
86 SYSCFG_LOCK(); \
87 } while (0)
88
89 #define PMU_GET_LVD_STATUS() (READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS))
90
101 typedef enum {
102 PMU_LP_STOP1 = 0x0U,
103 PMU_LP_STOP2 = 0x1U,
104 PMU_LP_STANDBY = 0x2U,
105 } pmu_lp_mode_t;
106
110 typedef enum {
111 PMU_LDO_18_DRV_HIGH = 0x0U,
112 PMU_LDO_18_DRV_LOW = 0x1U,
113 PMU_LDO_18_HOLD = 0x2U,
114 PMU_LDO_18_OFF = 0x3U,
115 } pmu_ldo_18_mode_t;
116
117 typedef enum {
118 PMU_SR_WUF = (1U << 0),
119 PMU_SR_STANDBYF = (1U << 1),
120 PMU_SR_USBRDY = (1U << 2),
121 PMU_SR_RSTAT = (1U << 3),
122 } pmu_status_t;
123
127 typedef enum {
128 PMU_LVD_VOL_SEL_2_2 = 0x0U,
129 PMU_LVD_VOL_SEL_2_4 = 0x1U,
130 PMU_LVD_VOL_SEL_2_6 = 0x2U,
131 PMU_LVD_VOL_SEL_2_8 = 0x3U,
132 PMU_LVD_VOL_SEL_3_0 = 0x4U,
133 PMU_LVD_VOL_SEL_3_2 = 0x5U,
134 PMU_LVD_VOL_SEL_3_4 = 0x6U,
135 PMU_LVD_VOL_SEL_3_6 = 0x7U,
136 PMU_LVD_VOL_SEL_3_8 = 0x8U,
137 PMU_LVD_VOL_SEL_4_0 = 0x9U,
138 PMU_LVD_VOL_SEL_4_2 = 0xAU,
139 PMU_LVD_VOL_SEL_4_4 = 0xBU,
140 PMU_LVD_VOL_SEL_4_6 = 0xCU,
141 PMU_LVD_VOL_SEL_4_8 = 0xDU,
142 PMU_LVD_VOL_SEL_EXT = 0xFU,
143 } pmu_lvd_voltage_sel_t;
144
148 typedef enum {
149 PMU_LVD_TRIGGER_RISING_EDGE = 0x0U,
150 PMU_LVD_TRIGGER_FALLING_EDGE = 0x1U,
151 PMU_LVD_TRIGGER_HIGH_LEVEL = 0x2U,
152 PMU_LVD_TRIGGER_LOW_LEVEL = 0x3U,
153 PMU_LVD_TRIGGER_RISING_FALLING = 0x4U,
154 } pmu_lvd_trigger_mode_t;
155
159 typedef enum {
160 PMU_LDO_LPMODE_OUTPUT_0_9 = 0x0U,
161 PMU_LDO_LPMODE_OUTPUT_1_0 = 0x1U,
162 PMU_LDO_LPMODE_OUTPUT_1_1 = 0x2U,
163 PMU_LDO_LPMODE_OUTPUT_1_2 = 0x3U,
164 } pmu_ldo_lpmode_output_t;
165
166 typedef enum {
167 PMU_POWER_SRAM0 = 0x1U,
168 PMU_POWER_SRAM1 = 0x2U,
169 PMU_POWER_SRAM2 = 0x4U,
170 PMU_POWER_SRAM3 = 0x8U,
171 PMU_POWER_SRAM4 = 0x10U,
172 PMU_POWER_SRAM5 = 0x20U,
173 PMU_POWER_CAN = 0x100U,
174 PMU_POWER_QSPI = 0x400U,
175 PMU_POWER_USB = 0x800U,
176 PMU_POWER_ROM = 0x1000U,
177 } pmu_perh_power_t;
178
187 #define IS_PMU_LP_MODE(x) (((x) == PMU_LP_STOP1) || \
188 ((x) == PMU_LP_STOP2) || \
189 ((x) == PMU_LP_STANDBY))
190 #define IS_PMU_LDO18_MODE(x) (((x) == PMU_LDO_18_DRV_HIGH) || \
191 ((x) == PMU_LDO_18_DRV_LOW) || \
192 ((x) == PMU_LDO_18_HOLD) || \
193 ((x) == PMU_LDO_18_OFF))
194 #define IS_PMU_STATUS(x) (((x) == PMU_SR_WUF) || \
195 ((x) == PMU_SR_STANDBYF) || \
196 ((x) == PMU_SR_USBRDY) || \
197 ((x) == PMU_SR_RSTAT))
198 #define IS_PMU_LVD_VOL_SEL(x) (((x) == PMU_LVD_VOL_SEL_2_2) || \
199 ((x) == PMU_LVD_VOL_SEL_2_4) || \
200 ((x) == PMU_LVD_VOL_SEL_2_6) || \
201 ((x) == PMU_LVD_VOL_SEL_2_8) || \
202 ((x) == PMU_LVD_VOL_SEL_3_0) || \
203 ((x) == PMU_LVD_VOL_SEL_3_2) || \
204 ((x) == PMU_LVD_VOL_SEL_3_4) || \
205 ((x) == PMU_LVD_VOL_SEL_3_6) || \
206 ((x) == PMU_LVD_VOL_SEL_3_8) || \
207 ((x) == PMU_LVD_VOL_SEL_4_0) || \
208 ((x) == PMU_LVD_VOL_SEL_4_2) || \
209 ((x) == PMU_LVD_VOL_SEL_4_4) || \
210 ((x) == PMU_LVD_VOL_SEL_4_6) || \
211 ((x) == PMU_LVD_VOL_SEL_4_8) || \
212 ((x) == PMU_LVD_VOL_SEL_EXT))
213 #define IS_PMU_LVD_TRIGGER_MODE(x) (((x) == PMU_LVD_TRIGGER_RISING_EDGE) || \
214 ((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \
215 ((x) == PMU_LVD_TRIGGER_HIGH_LEVEL) || \
216 ((x) == PMU_LVD_TRIGGER_LOW_LEVEL) || \
217 ((x) == PMU_LVD_TRIGGER_RISING_FALLING))
218 #define IS_PMU_LDO_LPMODE_OUTPUT(x) (((x) == PMU_LDO_LPMODE_OUTPUT_0_9) || \
219 ((x) == PMU_LDO_LPMODE_OUTPUT_1_0) || \
220 ((x) == PMU_LDO_LPMODE_OUTPUT_1_1) || \
221 ((x) == PMU_LDO_LPMODE_OUTPUT_1_2))
222 #define IS_PMU_PERH_POWER(x) (((x) == PMU_POWER_SRAM0) || \
223 ((x) == PMU_POWER_SRAM1) || \
224 ((x) == PMU_POWER_SRAM2) || \
225 ((x) == PMU_POWER_SRAM3) || \
226 ((x) == PMU_POWER_SRAM4) || \
227 ((x) == PMU_POWER_SRAM5) || \
228 ((x) == PMU_POWER_CAN) || \
229 ((x) == PMU_POWER_QSPI) || \
230 ((x) == PMU_POWER_USB) || \
231 ((x) == PMU_POWER_ROM))
232
243 /* Low power mode select */
244 __STATIC_INLINE__ void ald_pmu_sleep()
245 {
246 __WFI();
247 }
248
249 __STATIC_INLINE__ void ald_pmu_sleep_deep()
250 {
251 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
252 __WFI();
253 }
254
255 void ald_pmu_stop1_enter(void);
256 void ald_pmu_stop2_enter(void);
257 void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level);
258 void ald_pmu_ldo_12_config(type_func_t state);
259 void ald_pmu_ldo_18_config(pmu_ldo_18_mode_t mode);
260 #ifdef ES32F336x /* MCU Series: ES32F336x */
261 void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state);
262 #endif
263 flag_status_t ald_pmu_get_status(pmu_status_t sr);
264 void ald_pmu_clear_status(pmu_status_t sr);
265 void ald_pmu_perh_power_config(pmu_perh_power_t perh, type_func_t state);
272 /* LVD configure */
273 void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state);
274 void ald_lvd_irq_handler(void);
289 #ifdef __cplusplus
290 }
291 #endif
292
293 #endif /* __ALD_PMU_H__ */
PMU_SR_STANDBYF
Definition: ald_pmu.h:119
PMU_LDO_18_OFF
Definition: ald_pmu.h:114
ald_pmu_lvd_config
void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state)
Configure lvd using specified parameters.
Definition: ald_pmu.c:301
ald_pmu_ldo_12_config
void ald_pmu_ldo_12_config(type_func_t state)
Enable/Disable LDO(1.2V) hold mode. It must be disabled in STOP1.
Definition: ald_pmu.c:157
PMU_SR_WUF
Definition: ald_pmu.h:118
PMU_POWER_SRAM3
Definition: ald_pmu.h:170
bkpc_wakeup_port_t
bkpc_wakeup_port_t
Standby wakeup port select.
Definition: ald_bkpc.h:111
PMU_POWER_SRAM5
Definition: ald_pmu.h:172
PMU_LVD_VOL_SEL_4_0
Definition: ald_pmu.h:137
PMU_POWER_ROM
Definition: ald_pmu.h:176
type_func_t
type_func_t
Definition: type.h:47
PMU_LDO_LPMODE_OUTPUT_1_0
Definition: ald_pmu.h:161
PMU_POWER_SRAM4
Definition: ald_pmu.h:171
PMU_LVD_TRIGGER_HIGH_LEVEL
Definition: ald_pmu.h:151
ald_lvd_irq_handler
void ald_lvd_irq_handler(void)
PMU module interrupt handler.
Definition: ald_pmu.c:40
PMU_LVD_VOL_SEL_3_8
Definition: ald_pmu.h:136
PMU_LVD_VOL_SEL_3_2
Definition: ald_pmu.h:133
ald_pmu_perh_power_config
void ald_pmu_perh_power_config(pmu_perh_power_t perh, type_func_t state)
Configure peripheral power.
Definition: ald_pmu.c:261
PMU_LVD_VOL_SEL_2_2
Definition: ald_pmu.h:128
PMU_LVD_TRIGGER_RISING_EDGE
Definition: ald_pmu.h:149
pmu_lvd_trigger_mode_t
pmu_lvd_trigger_mode_t
LVD trigger mode.
Definition: ald_pmu.h:148
utils.h
This file contains the Utilities functions/types for the driver.
PMU_POWER_SRAM1
Definition: ald_pmu.h:168
ald_bkpc.h
Header file of BKPC module driver.
PMU_LVD_VOL_SEL_4_4
Definition: ald_pmu.h:139
PMU_LDO_18_HOLD
Definition: ald_pmu.h:113
ald_pmu_ldo_18_config
void ald_pmu_ldo_18_config(pmu_ldo_18_mode_t mode)
Configure LDO(1.8V) mode.
Definition: ald_pmu.c:176
pmu_perh_power_t
pmu_perh_power_t
Definition: ald_pmu.h:166
PMU_LVD_VOL_SEL_2_8
Definition: ald_pmu.h:131
PMU_LVD_VOL_SEL_4_2
Definition: ald_pmu.h:138
PMU_LVD_VOL_SEL_3_0
Definition: ald_pmu.h:132
__STATIC_INLINE__
#define __STATIC_INLINE__
Definition: type.h:32
PMU_LDO_18_DRV_LOW
Definition: ald_pmu.h:112
PMU_LDO_LPMODE_OUTPUT_1_2
Definition: ald_pmu.h:163
PMU_SR_RSTAT
Definition: ald_pmu.h:121
PMU_LVD_VOL_SEL_4_6
Definition: ald_pmu.h:140
pmu_status_t
pmu_status_t
Definition: ald_pmu.h:117
ald_pmu_stop1_enter
void ald_pmu_stop1_enter(void)
Enter stop1 mode.
Definition: ald_pmu.c:78
PMU_POWER_SRAM2
Definition: ald_pmu.h:169
pmu_ldo_lpmode_output_t
pmu_ldo_lpmode_output_t
LDO output voltage selest in low power mode.
Definition: ald_pmu.h:159
ald_pmu_get_status
flag_status_t ald_pmu_get_status(pmu_status_t sr)
Get wakup status.
Definition: ald_pmu.c:224
pmu_ldo_18_mode_t
pmu_ldo_18_mode_t
LDO_18 mode.
Definition: ald_pmu.h:110
ald_syscfg.h
SYSCFG module driver.
ald_pmu_standby_enter
void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
Enter standby mode.
Definition: ald_pmu.c:136
pmu_lvd_voltage_sel_t
pmu_lvd_voltage_sel_t
LVD voltage select.
Definition: ald_pmu.h:127
PMU_LP_STOP2
Definition: ald_pmu.h:103
PMU_LVD_VOL_SEL_2_6
Definition: ald_pmu.h:130
PMU_LVD_VOL_SEL_3_4
Definition: ald_pmu.h:134
PMU_POWER_CAN
Definition: ald_pmu.h:173
pmu_lp_mode_t
pmu_lp_mode_t
Low power mode.
Definition: ald_pmu.h:101
PMU_POWER_SRAM0
Definition: ald_pmu.h:167
PMU_LDO_18_DRV_HIGH
Definition: ald_pmu.h:111
PMU_SR_USBRDY
Definition: ald_pmu.h:120
PMU_LVD_TRIGGER_FALLING_EDGE
Definition: ald_pmu.h:150
PMU_LVD_TRIGGER_LOW_LEVEL
Definition: ald_pmu.h:152
PMU_LVD_VOL_SEL_EXT
Definition: ald_pmu.h:142
PMU_POWER_QSPI
Definition: ald_pmu.h:174
flag_status_t
flag_status_t
Definition: type.h:37
PMU_LVD_VOL_SEL_4_8
Definition: ald_pmu.h:141
ald_pmu_sleep
__STATIC_INLINE__ void ald_pmu_sleep()
Definition: ald_pmu.h:244
PMU_LDO_LPMODE_OUTPUT_1_1
Definition: ald_pmu.h:162
ald_pmu_sleep_deep
__STATIC_INLINE__ void ald_pmu_sleep_deep()
Definition: ald_pmu.h:249
bkpc_wakeup_level_t
bkpc_wakeup_level_t
Standby wakeup level.
Definition: ald_bkpc.h:126
PMU_LP_STANDBY
Definition: ald_pmu.h:104
ald_pmu_clear_status
void ald_pmu_clear_status(pmu_status_t sr)
Clear wakup status.
Definition: ald_pmu.c:239
ald_pmu_stop2_enter
void ald_pmu_stop2_enter(void)
Enter stop2 mode.
Definition: ald_pmu.c:106
PMU_LVD_VOL_SEL_3_6
Definition: ald_pmu.h:135
PMU_LVD_TRIGGER_RISING_FALLING
Definition: ald_pmu.h:153
PMU_LP_STOP1
Definition: ald_pmu.h:102
PMU_LVD_VOL_SEL_2_4
Definition: ald_pmu.h:129
PMU_POWER_USB
Definition: ald_pmu.h:175
PMU_LDO_LPMODE_OUTPUT_0_9
Definition: ald_pmu.h:160


ALD User Manual: D:/svn/src/ald_qspi.c Source File

  • D:
  • svn
  • src
ald_qspi.c
Go to the documentation of this file.
1
16 #include "ald_qspi.h"
17
18
28 #ifdef ALD_QSPI
29
42 static ald_status_t qspi_wait_for_idle(qspi_handle_t *hperh, uint32_t tickstart, uint32_t timeout)
43 {
44 /* Wait until flag is in expected state */
45 while (READ_BIT(hperh->perh->CR, QSPI_CR_IDLES_MSK) != QSPI_CR_IDLES) {
46 /* Check for the Timeout */
47 if (timeout != ALD_MAX_DELAY) {
48 if ((timeout == 0U) || ((ald_get_tick() - tickstart) > timeout)) {
49 return ERROR;
50 }
51 }
52 }
53 return OK;
54 }
55
62 static flag_status_t qspi_indrd_get_status(qspi_handle_t *hperh, qspi_indrd_flag_t status)
63 {
64 assert_param(IS_QSPI_ALL(hperh->perh));
65 assert_param(IS_QSPI_INDIRECT_READ_STATUS(status));
66
67 if (hperh->perh->IRTR & status)
68 return SET;
69
70 return RESET;
71 }
72
90 void ald_qspi_init(qspi_handle_t *hperh)
91 {
92 assert_param(IS_QSPI_CLOCK_PRESCALER(hperh->init.clkdiv));
93 assert_param(IS_QSPI_CLOCK_PHASE(hperh->init.chpa));
94 assert_param(IS_QSPI_CLOCK_POLARITY(hperh->init.cpol));
95
96 MODIFY_REG(hperh->perh->CR, QSPI_CR_BAUD_MSK | QSPI_CR_CPOL_MSK | QSPI_CR_CPHA_MSK | \
97 QSPI_CR_PSL_MSK | QSPI_CR_SWPP_MSK , (hperh->init.clkdiv << QSPI_CR_BAUD_POSS) | \
98 (hperh->init.cpol << QSPI_CR_CPOL_POS) | \
99 (hperh->init.chpa << QSPI_CR_CPHA_POS) | \
100 (hperh->init.chipsel << QSPI_CR_PSL_POSS) | \
101 (hperh->init.wrppin << QSPI_CR_SWPP_POS));
102
103 return;
104 }
105
111 uint32_t ald_qspi_dac_rd(uint32_t addr)
112 {
113 return ((*(volatile uint32_t *)(addr)));
114 }
115
122 void ald_qspi_dac_wr(uint32_t addr, uint32_t dat)
123 {
124 (*(volatile uint32_t *)(addr)) = dat;
125 }
126
133 ald_status_t ald_qspi_read_config(qspi_handle_t * hperh, const qspi_read_cfg_t * rdcfg)
134 {
135 ald_status_t status = ERROR;
136 uint32_t tickstart = ald_get_tick();
137
138 assert_param(IS_QSPI_RD_OPCODE(rdcfg->rdcde));
139 assert_param(IS_QSPI_DCYLES(rdcfg->dcyles));
140 assert_param(IS_QSPI_XFER_TYPE(rdcfg->datxfer));
141 assert_param(IS_QSPI_XFER_TYPE(rdcfg->addxfer));
142 assert_param(IS_QSPI_XFER_TYPE(rdcfg->instxfer));
143
144 status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE);
145
146 if (status != OK)
147 return status;
148
149 MODIFY_REG(hperh->perh->DRIR, QSPI_DRIR_RINST_MSK | QSPI_DRIR_MBEN_MSK | \
150 QSPI_DRIR_DCYC_MSK | QSPI_DRIR_ADMODE_MSK | \
151 QSPI_DRIR_DMODE_MSK | QSPI_DRIR_IMODE_MSK | \
152 QSPI_DRIR_DDRM_MSK, \
153 (rdcfg->rdcde | (rdcfg->dcyles << 24) | \
154 (rdcfg->addxfer << 12) | (rdcfg->instxfer << 8) | \
155 (rdcfg->ddrbit << QSPI_DRIR_DDRM_POS) | (rdcfg->modebit << QSPI_DRIR_MBEN_POS)) | \
156 (rdcfg->datxfer << QSPI_DRIR_DMODE_POSS));
157
158 if (rdcfg->modebit)
159 MODIFY_REG(hperh->perh->MBR, QSPI_MBR_MODEB_MSK, rdcfg->mbitval);
160
161 return status;
162 }
163
170 ald_status_t ald_qspi_write_config(qspi_handle_t * hperh, const qspi_write_cfg_t * wrcfg)
171 {
172 ald_status_t status = ERROR;
173 uint32_t tickstart = ald_get_tick();
174
175 assert_param(IS_QSPI_WR_OPCODE(wrcfg->wrcde));
176 assert_param(IS_QSPI_DCYLES(wrcfg->dcyles));
177 assert_param(IS_QSPI_XFER_TYPE(wrcfg->datxfer));
178 assert_param(IS_QSPI_XFER_TYPE(wrcfg->addxfer));
179
180 status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE);
181
182 if (status != OK)
183 return status;
184
185 MODIFY_REG(hperh->perh->DWIR, QSPI_DWIR_WINST_MSK | QSPI_DWIR_DCYC_MSK | \
186 QSPI_DWIR_ADMODE_MSK | QSPI_DWIR_DMODE_MSK,
187 wrcfg->wrcde | \
188 (wrcfg->addxfer << 12) | \
189 (wrcfg->datxfer << 16) | \
190 (wrcfg->dcyles << 24));
191 if (wrcfg->autowel)
192 CLEAR_BIT(hperh->perh->DWIR, QSPI_DWIR_WELD_MSK);
193 else
194 SET_BIT(hperh->perh->DWIR, QSPI_DWIR_WELD_MSK);
195
196 return status;
197 }
198
205 ald_status_t ald_qspi_device_delay_config(qspi_handle_t * hperh, qspi_dly_cfg_t *dlycfg)
206 {
207 ald_status_t status = ERROR;
208 uint32_t tickstart = ald_get_tick();
209
210 assert_param(IS_QSPI_ALL(hperh->perh));
211 assert_param(IS_QSPI_DEVICE_DELAY_CCSOT(dlycfg->ccsot));
212 assert_param(IS_QSPI_DEVICE_DELAY_CSEOT(dlycfg->cseot));
213 assert_param(IS_QSPI_DEVICE_DELAY_CSDADS(dlycfg->csdads));
214 assert_param(IS_QSPI_DEVICE_DELAY_CSDA(dlycfg->csda));
215
216 status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE);
217
218 if (status != OK)
219 return status;
220
221 MODIFY_REG(hperh->perh->DDLR, QSPI_DDLR_CSSOT_MSK | QSPI_DDLR_CSEOT_MSK | QSPI_DDLR_CSDADS_MSK | QSPI_DDLR_CSDA_MSK, \
222 dlycfg->ccsot | (dlycfg->cseot << 8) | (dlycfg->csdads << 16) | (dlycfg->csda << 24));
223 return status;
224 }
225
232 ald_status_t ald_qspi_read_data_capture_config(qspi_handle_t * hperh, qspi_data_capture_cfg_t *dtcptcfg)
233 {
234 ald_status_t status = ERROR;
235 uint32_t tickstart = ald_get_tick();
236
237 assert_param(IS_QSPI_ALL(hperh->perh));
238 assert_param(IS_QSPI_READ_DATA_CAPTURE_DELAY_READ(dtcptcfg->dlydcl));
239 assert_param(IS_QSPI_READ_DATA_SAMPLE_EDGE(dtcptcfg->smpledge));
240 assert_param(IS_QSPI_READ_DATA_DELAY_TRANSMIT(dtcptcfg->dlytd));
241
242 status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE);
243
244 if (status != OK)
245 return status;
246
247 MODIFY_REG(hperh->perh->RDCR, QSPI_RDCR_BYLPC_MSK | QSPI_RDCR_DLYR_MSK | QSPI_RDCR_SMES_MSK | QSPI_RDCR_DLYT_MSK, \
248 dtcptcfg->bypsalcc | (dtcptcfg->dlydcl << 1) | (dtcptcfg->smpledge << 5) | (dtcptcfg->dlytd << 16));
249 return status;
250 }
251
258 ald_status_t ald_qspi_device_size_config(qspi_handle_t *hperh, qspi_device_size_t * devcfg)
259 {
260 ald_status_t status = ERROR;
261 uint32_t tickstart = ald_get_tick();
262
263 assert_param(IS_QSPI_ADDR_SIZE(devcfg->addr));
264 assert_param(IS_QSPI_PAGE_SIZE(devcfg->page));
265 assert_param(IS_QSPI_BLOCK_SIZE(devcfg->blk));
266 assert_param(IS_QSPI_NSS_SIZE(devcfg->cs0));
267 assert_param(IS_QSPI_NSS_SIZE(devcfg->cs1));
268 assert_param(IS_QSPI_NSS_SIZE(devcfg->cs2));
269 assert_param(IS_QSPI_NSS_SIZE(devcfg->cs3));
270
271 status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE);
272
273 if (status != OK)
274 return status;
275
276 MODIFY_REG(hperh->perh->DSCR, QSPI_DSCR_ADSIZE_MSK | QSPI_DSCR_PASIZE_MSK | QSPI_DSCR_BKSIZE_MSK | QSPI_DSCR_CS0SIZE_MSK | \
277 QSPI_DSCR_CS1SIZE_MSK | QSPI_DSCR_CS2SIZE_MSK | QSPI_DSCR_CS3SIZE_MSK, \
278 (devcfg->addr << QSPI_DSCR_ADSIZE_POSS) | \
279 (devcfg->page << QSPI_DSCR_PASIZE_POSS) | \
280 (devcfg->blk << QSPI_DSCR_BKSIZE_POSS) | \
281 (devcfg->cs0 << QSPI_DSCR_CS0SIZE_POSS) | \
282 (devcfg->cs1 << QSPI_DSCR_CS1SIZE_POSS) | \
283 (devcfg->cs2 << QSPI_DSCR_CS2SIZE_POSS) | \
284 (devcfg->cs3 << QSPI_DSCR_CS3SIZE_POSS));
285 return OK;
286 }
287
295 ald_status_t qspi_dac_config(qspi_handle_t * hperh, qspi_dac_cfg_t * dcfg)
296 {
297 ald_status_t status = ERROR;
298 uint32_t tickstart = ald_get_tick();
299
300 assert_param(IS_QSPI_WR_OPCODE(dcfg->wrinit.wrcde));
301 assert_param(IS_QSPI_DCYLES(dcfg->wrinit.dcyles));
302 assert_param(IS_QSPI_XFER_TYPE(dcfg->wrinit.datxfer));
303 assert_param(IS_QSPI_XFER_TYPE(dcfg->wrinit.addxfer));
304 assert_param(IS_QSPI_XFER_TYPE(dcfg->wrinit.instxfer));
305
306 status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE);
307
308 if (status != OK)
309 return status;
310
311 QSPI_DISABLE(hperh);
312 ald_qspi_init(hperh);
313
314 if (ald_qspi_write_config(hperh, &dcfg->wrinit) != OK)
315 return ERROR;
316 if (ald_qspi_read_config(hperh, &dcfg->rdinit) != OK)
317 return ERROR;
318
319 MODIFY_REG(hperh->perh->DWIR, QSPI_DWIR_WINST_MSK | QSPI_DWIR_DCYC_MSK | \
320 QSPI_DWIR_ADMODE_MSK | QSPI_DWIR_DMODE_MSK | \
321 QSPI_DWIR_WELD_MSK, dcfg->wrinit.wrcde | dcfg->wrinit.autowel | \
322 (dcfg->wrinit.addxfer << 12) | \
323 (dcfg->wrinit.datxfer << 16) | \
324 (dcfg->wrinit.dcyles << 24));
325 MODIFY_REG(hperh->perh->DRIR, QSPI_DRIR_RINST_MSK, dcfg->wrinit.instxfer);
326
327 if (dcfg->addrremap)
328 MODIFY_REG(hperh->perh->RAR, QSPI_RAR_READDR_MSK, dcfg->remapaddr);
329
330 MODIFY_REG(hperh->perh->CR, QSPI_CR_DTRM_MSK | QSPI_CR_ADEN_MSK | QSPI_CR_XIPIM_MSK | \
331 QSPI_CR_XIPNX_MSK | QSPI_CR_AREN_MSK | QSPI_CR_DMAEN_MSK, \
332 dcfg->dtrprtcol | dcfg->ahbdecoder);
333 QSPI_ENABLE(hperh);
334 return OK;
335 }
336
352 ald_status_t ald_qspi_indac_config(qspi_handle_t * hperh, qspi_indac_cfg_t *indcfg)
353 {
354 ald_status_t status = ERROR;
355 uint32_t tickstart = ald_get_tick();
356
357 assert_param(IS_QSPI_ALL(hperh->perh));
358 assert_param(IS_QSPI_SRAM_PARTITION(indcfg->srampt));
359 assert_param(IS_QSPI_INDIRECT_TRIGGER_RANGE(indcfg->trgrng));
360 assert_param(IS_QSPI_INDIRECT_READ_WATERMARK(indcfg->rdwmark));
361
362 status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE);
363
364 if (status != OK)
365 return status;
366
367 QSPI_DISABLE(hperh);
368
369 MODIFY_REG(hperh->perh->SPR, QSPI_SPR_SRAMPS_MSK, indcfg->srampt);
370 MODIFY_REG(hperh->perh->IATR, QSPI_IATR_INDTAD_MSK, indcfg->trgaddr);
371 MODIFY_REG(hperh->perh->ITARR, QSPI_ITARR_RNGW_MSK, indcfg->trgrng);
372 MODIFY_REG(hperh->perh->IWTWR, QSPI_IWTWR_VAULE_MSK, indcfg->wrwmark);
373 MODIFY_REG(hperh->perh->IRTWR, QSPI_IRTWR_VAULE_MSK, indcfg->rdwmark);
374
375 QSPI_ENABLE(hperh);
376
377 return OK;
378 }
379
388 ald_status_t ald_qspi_indac_transmit_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size)
389 {
390 uint32_t i = 0;
391 uint32_t tmp = 0, pgsize = 0;
392 assert_param(IS_QSPI_ALL(hperh->perh));
393
394 if ((psrc == NULL) || (size == 0))
395 return ERROR;
396
397 hperh->state = QSPI_STATE_BUSY_TX;
398 hperh->rx_buf = NULL;
399 hperh->rx_cnt = 0;
400 hperh->rx_size = 0;
401 hperh->tx_buf = psrc;
402 hperh->tx_cnt = 0;
403 hperh->tx_size = size;
404
405 tmp = READ_REG(hperh->perh->DSCR);
406 pgsize = (tmp & 0xfff0) >> 4;
407
408 if (size >= pgsize)
409 tmp = pgsize;
410 else
411 tmp = size;
412
413 hperh->tx_cnt += tmp;
414
415 ald_qspi_clear_it_flag(hperh, QSPI_IF_INDCF);
416 MODIFY_REG(hperh->perh->IWTSAR, QSPI_IWTSAR_ADDR_MSK, saddr);
417 MODIFY_REG(hperh->perh->IWTNR, QSPI_IWTNR_NUM_MSK, size);
418 ald_qspi_interrupt_config(hperh, QSPI_IT_INDTWF, ENABLE);
419 ald_qspi_interrupt_config(hperh, QSPI_IT_INDCF, ENABLE);
420
421 /* Trigger indirect write */
422 SET_BIT(hperh->perh->IWTR, QSPI_IWTR_WRST_MSK);
423
424 for (i = 0; i < (tmp / 4); ++i)
425 *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(psrc + 4 * i));
426
427 return OK;
428 }
429
438 ald_status_t ald_qspi_indac_transmit_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size)
439 {
440 uint32_t i, j = 0, cnt = 0;
441 uint32_t tmp = 0;
442 uint32_t idx = 0, txsm = 0;
443 assert_param(IS_QSPI_ALL(hperh->perh));
444
445 if ((psrc == NULL) || (size == 0))
446 return ERROR;
447
448 MODIFY_REG(hperh->perh->IWTSAR, QSPI_IWTSAR_ADDR_MSK, saddr);
449 MODIFY_REG(hperh->perh->IWTNR, QSPI_IWTNR_NUM_MSK, size);
450
451 /* Counter write times totally */
452 if (size % 4)
453 cnt = (size / 4) + 1;
454 else
455 cnt = size / 4;
456 /* Get transmit SRAM partition (unit:4bytes)*/
457 tmp = READ_REG(hperh->perh->SPR);
458 txsm = QSPI_SRAM_SIZE - tmp;
459 if (cnt <= txsm) {
460 /* Trigger indirect write */
461 SET_BIT(hperh->perh->IWTR, QSPI_IWTR_WRST_MSK);
462 for (i = 0; i < cnt; ++i)
463 *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(psrc + 4 *i));
464 } else {
465 SET_BIT(hperh->perh->IWTR, QSPI_IWTR_WRST_MSK);
466 for (j = 0; j < (cnt / txsm); ++j) {
467 for (i = 0; i < txsm; ++i) {
468 *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(psrc + idx + 4 *i));
469 }
470 idx += txsm * 4;
471 do {
472 tmp = READ_REG(hperh->perh->SFLR);
473 tmp = (tmp >> 16) & 0xffff;
474 } while (tmp != 0);
475 }
476
477 for (j = 0; j < (cnt % txsm); ++j)
478 *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(psrc + idx + 4 *j));
479 }
480 /* Wait for indirect read operation completely */
481 do {
482 tmp = READ_REG(hperh->perh->IWTR);
483 } while ( tmp & 0x4);
484
485 return OK;
486 }
487
496 ald_status_t ald_qspi_indac_read_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size)
497 {
498
499 uint32_t i = 0, j = 0, cnt = 0;
500 uint32_t tmp = 0;
501 uint32_t idx = 0, rxsm = 1;
502
503 assert_param(IS_QSPI_ALL(hperh->perh));
504
505 if ((desbuf == NULL) || (size == 0))
506 return ERROR;
507
508 MODIFY_REG(hperh->perh->IRTSAR, QSPI_IRTSAR_ADDR_MSK, saddr);
509 MODIFY_REG(hperh->perh->IRTNR, QSPI_IRTNR_NUM_MSK, size);
510 /* Counter read times totally */
511 if (size % 4)
512 cnt = (size / 4) + 1;
513 else
514 cnt = size / 4;
515 /* Get read SRAM partition (unit: 4bytes)*/
516 rxsm = READ_REG(hperh->perh->SPR) + 1;
517 if (cnt <= rxsm) {
518 SET_BIT(hperh->perh->IRTR, QSPI_IRTR_RDST_MSK);
519 do {
520 tmp = READ_REG(hperh->perh->SFLR);
521 tmp = tmp & 0x0000ffffU;
522 } while (tmp != cnt);
523 for (i = 0; i < cnt; ++i)
524 *(uint32_t *)(desbuf + 4 * i) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS;
525 } else {
526 SET_BIT(hperh->perh->IRTR, QSPI_IRTR_RDST_MSK);
527 for (j = 0; j < (cnt / rxsm); ++j) {
528 do {
529 tmp = READ_REG(hperh->perh->SFLR);
530 tmp = tmp & 0x0000ffffU;
531 } while (tmp != rxsm);
532 for (i = 0; i < rxsm; ++i) {
533 *(uint32_t *)(desbuf + idx + 4 * i) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS;
534 }
535 idx += rxsm * 4;
536 }
537 do {
538 tmp = READ_REG(hperh->perh->SFLR);
539 tmp = tmp & 0x0000ffffU;
540 } while ( tmp != (cnt % rxsm));
541
542 for (j = 0; j < (cnt % rxsm); ++j) {
543 *(uint32_t *)(desbuf + idx + 4 * i) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS;
544 }
545 }
546 /* Wait for indirect read operation completely */
547 do {
548 tmp = READ_REG(hperh->perh->IRTR);
549 } while (tmp & 0x04);
550
551 return OK;
552 }
553
563 ald_status_t ald_qspi_indac_read_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size)
564 {
565 assert_param(IS_QSPI_ALL(hperh->perh));
566
567 if ((desbuf == NULL) || (size == 0))
568 return ERROR;
569
570 hperh->state = QSPI_STATE_BUSY_RX;
571 hperh->rx_buf = desbuf;
572 hperh->rx_cnt = 0;
573 hperh->rx_size = size;
574 hperh->tx_buf = NULL;
575 hperh->tx_cnt = 0;
576 hperh->tx_size = 0;
577
578 ald_qspi_clear_it_flag(hperh, QSPI_IF_INDCF);
579 MODIFY_REG(hperh->perh->IRTSAR, QSPI_IRTSAR_ADDR_MSK, saddr);
580 MODIFY_REG(hperh->perh->IRTNR, QSPI_IRTNR_NUM_MSK, size);
581 ald_qspi_interrupt_config(hperh, QSPI_IT_INDTWF, ENABLE);
582 ald_qspi_interrupt_config(hperh, QSPI_IT_INDCF, ENABLE);
583 SET_BIT(hperh->perh->IRTR, QSPI_IRTR_RDST_MSK);
584
585 return OK;
586 }
587
594 ald_status_t ald_qspi_execute_stig_cmd(qspi_handle_t * hperh, const qspi_stig_cmd_t * stigcmd)
595 {
596 uint32_t i;
597 ald_status_t status = ERROR;
598 uint32_t tickstart = ald_get_tick();
599
600 assert_param(IS_QSPI_ALL(hperh->perh));
601 assert_param(stigcmd->addr_len <= 4);
602 assert_param(stigcmd->wr_len <= 8);
603 assert_param(stigcmd->rd_len <= 8);
604 assert_param(stigcmd->d_sycle < 32);
605
606 if (stigcmd->wr_len)
607 assert_param(stigcmd->wr_buf);
608 if (stigcmd->rd_len)
609 assert_param(stigcmd->rd_buf);
610
611 /* wait for Flash idle */
612 status = qspi_wait_for_idle(hperh, tickstart, QSPI_TIMEOUT_DEFAULT_VALUE);
613
614 if (status != OK)
615 return ERROR;
616
617 MODIFY_REG(hperh->perh->FCR, QSPI_FCR_OPCODE_MSK | QSPI_FCR_DUMNUM_MSK , ((stigcmd->code << 24) | (stigcmd->d_sycle << 7)));
618
619 if (stigcmd->wr_len) {
620 uint32_t buffer[2] = {0, 0};
621 uint8_t * dst = (uint8_t *) buffer;
622 uint8_t * src = stigcmd->wr_buf;
623
624 MODIFY_REG(hperh->perh->FCR, QSPI_FCR_WDNUM_MSK, (stigcmd->wr_len - 1) << QSPI_FCR_WDNUM_POSS);
625 SET_BIT(hperh->perh->FCR, QSPI_FCR_WREN_MSK);
626
627 for (i = 0; i < stigcmd->wr_len; i++)
628 dst[i] = src[i];
629
630 hperh->perh->FCWLR = buffer[0];
631 hperh->perh->FCWHR = buffer[1];
632 } else {
633 CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_WDNUM_MSK);
634 CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_WREN_MSK);
635 }
636
637 if (stigcmd->addr_len) {
638 SET_BIT(hperh->perh->FCR, QSPI_FCR_ADDREN_MSK);
639
640 MODIFY_REG(hperh->perh->FCR, QSPI_FCR_ADNUM_MSK, (stigcmd->addr_len - 1) << QSPI_FCR_ADNUM_POSS);
641 MODIFY_REG(hperh->perh->FCAR, QSPI_FCAR_CMDADR_MSK, stigcmd->addr);
642 } else {
643 CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_ADDREN_MSK);
644 CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_ADNUM_MSK);
645 CLEAR_BIT(hperh->perh->FCAR, QSPI_FCAR_CMDADR_MSK);
646 }
647
648 if (stigcmd->mode_bit) {
649 SET_BIT(hperh->perh->FCR, QSPI_FCR_MODBEN_MSK);
650 MODIFY_REG(hperh->perh->MBR, QSPI_MBR_MODEB_MSK, stigcmd->val);
651 } else {
652 CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_MODBEN_MSK);
653 CLEAR_BIT(hperh->perh->MBR, QSPI_MBR_MODEB_MSK);
654 }
655
656 if (stigcmd->rd_len) {
657 SET_BIT(hperh->perh->FCR, QSPI_FCR_RDEN_MSK);
658 MODIFY_REG(hperh->perh->FCR, QSPI_FCR_RDNUM_MSK, (stigcmd->rd_len - 1) << QSPI_FCR_RDNUM_POSS);
659 } else {
660 CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_RDEN_MSK);
661 CLEAR_BIT(hperh->perh->FCR, QSPI_FCR_RDNUM_MSK);
662 }
663
664 /* Start command execution */
665 SET_BIT(hperh->perh->FCR, QSPI_FCR_CMDT_MSK);
666
667 while (hperh->perh->FCR & QSPI_FCR_CMDS_MSK);
668
669 /* Read data if any */
670 if (stigcmd->rd_len) {
671 uint32_t buffer[2] = { 0, 0 };
672 const uint8_t * src = (const uint8_t *)buffer;
673 uint8_t * dst = stigcmd->rd_buf;
674
675 buffer[0] = hperh->perh->FCRLR;
676 buffer[1] = hperh->perh->FCRHR;
677
678 for (i = 0; i < stigcmd->rd_len; i++) {
679 dst[i] = src[i];
680 }
681 }
682
683 return OK;
684 }
685
686 #ifdef ALD_DMA
687
695 ald_status_t ald_qspi_indac_transmit_by_dma(qspi_handle_t *hperh, uint32_t addr, uint8_t *psrc, uint16_t size)
696 {
697 uint16_t cnt = 0;
698 uint32_t *tmp = (uint32_t*)psrc;
699 /* Get Indirect Read Trigger Address */
700 __IO uint32_t *data_reg = (uint32_t *)hperh->perh->IATR;
701
702 assert_param(IS_QSPI_ALL(hperh->perh));
703
704 if ((psrc == NULL) || (size == 0))
705 return ERROR;
706
707 MODIFY_REG(hperh->perh->IWTSAR, QSPI_IWTSAR_ADDR_MSK, addr);
708 MODIFY_REG(hperh->perh->IWTNR, QSPI_IWTNR_NUM_MSK, size);
709 QSPI_DMA_ENABLE(hperh);
710 if (size % 4)
711 cnt = (size / 4) + 1;
712 else
713 cnt = size / 4;
714
715 __LOCK(hperh);
716
717 hperh->hdma.perh = DMA0;
718 hperh->hdma.cplt_cbk = NULL;
719 ald_dma_config_struct(&hperh->hdma.config);
720
721 hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD;
722 hperh->hdma.config.src = (void *)tmp;
723 hperh->hdma.config.dst = (void *)data_reg;
724 hperh->hdma.config.size = cnt;
725 hperh->hdma.config.src_inc = DMA_DATA_INC_WORD;
726 hperh->hdma.config.dst_inc = DMA_DATA_INC_NONE;
727 hperh->hdma.config.msel = DMA_MSEL_QSPI;
728 hperh->hdma.config.msigsel = DMA_MSIGSEL_QSPI_WRITE;
729 hperh->hdma.config.channel = 0;
730 hperh->hdma.config.R_power = DMA_R_POWER_4;
731 hperh->hdma.config.burst = ENABLE;
732 ald_dma_config_basic(&hperh->hdma);
733
734 /* Trigger indirect write */
735 SET_BIT(hperh->perh->IWTR, QSPI_IWTR_WRST_MSK);
736 __UNLOCK(hperh);
737
738 return OK;
739 }
740
749 ald_status_t ald_qspi_indac_read_by_dma(qspi_handle_t *hperh, uint32_t addr, uint8_t *pdbuf, uint16_t size)
750 {
751 uint16_t cnt = 0;
752 ald_status_t status = OK;
753 uint32_t *tmp = (uint32_t *)pdbuf;
754 /* Get Indirect Read Trigger Address */
755 __IO uint32_t *data_reg = (uint32_t *)hperh->perh->IATR;
756
757 assert_param(IS_QSPI_ALL(hperh->perh));
758
759 if ((pdbuf == NULL) || (size == 0))
760 return ERROR;
761
762 MODIFY_REG(hperh->perh->IRTSAR, QSPI_IRTSAR_ADDR_MSK, addr);
763 MODIFY_REG(hperh->perh->IRTNR, QSPI_IRTNR_NUM_MSK, size);
764
765 QSPI_DMA_ENABLE(hperh);
766
767 if (size % 4)
768 cnt = (size / 4) + 1;
769 else
770 cnt = size / 4;
771
772 __LOCK(hperh);
773
774 hperh->hdma.perh = DMA0;
775 hperh->hdma.cplt_cbk = NULL;
776 ald_dma_config_struct(&hperh->hdma.config);
777
778 hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD;
779 hperh->hdma.config.src = (void *)data_reg;
780 hperh->hdma.config.dst = (void *)tmp;
781 hperh->hdma.config.size = cnt;
782 hperh->hdma.config.src_inc = DMA_DATA_INC_NONE;
783 hperh->hdma.config.dst_inc = DMA_DATA_INC_WORD;
784 hperh->hdma.config.msel = DMA_MSEL_QSPI;
785 hperh->hdma.config.msigsel = DMA_MSIGSEL_QSPI_READ;
786 hperh->hdma.config.channel = 0;
787 hperh->hdma.config.R_power = DMA_R_POWER_4;
788 hperh->hdma.config.burst = ENABLE;
789 ald_dma_config_basic(&hperh->hdma);
790
791 /* Trigger indirect write */
792 SET_BIT(hperh->perh->IRTR, QSPI_IRTR_RDST_MSK);
793 __UNLOCK(hperh);
794
795 return status;
796 }
797 #endif
798
814 flag_status_t qspi_get_flag_status(qspi_handle_t *hperh, qspi_flag_t flag)
815 {
816 assert_param(IS_QSPI_ALL(hperh->perh));
817 assert_param(IS_QSPI_IF(flag));
818
819 if (hperh->perh->IFR & flag)
820 return SET;
821
822 return RESET;
823 }
824
832 void ald_qspi_clear_it_flag(qspi_handle_t *hperh, qspi_flag_t flag)
833 {
834 assert_param(IS_QSPI_ALL(hperh->perh));
835 assert_param(IS_QSPI_IF(flag));
836
837 hperh->perh->IFR = flag;
838
839 return;
840 }
841
848 uint16_t qspi_read_sram_fill_level(qspi_handle_t * hperh, qspi_sram_t srt)
849 {
850 assert_param(IS_QSPI_ALL(hperh->perh));
851 assert_param(IS_QSPI_INDIRECT_SRAM_FILL_TYPE(srt));
852
853 if (srt == QSPI_SRAM_RD)
854 return READ_BITS(hperh->perh->SFLR, QSPI_SFLR_INDRSFL_MSK, QSPI_SFLR_INDRSFL_POSS);
855
856 return READ_BITS(hperh->perh->SFLR, QSPI_SFLR_INDWSFL_MSK, QSPI_SFLR_INDWSFL_POSS);
857 }
858
865 void ald_qspi_write_proect_config(qspi_handle_t * hperh, qspi_wr_protect_t * wpcfg)
866 {
867 assert_param(IS_QSPI_ALL(hperh->perh));
868
869 MODIFY_REG(hperh->perh->WPLR, QSPI_WPLR_LBLKNUM_MSK, wpcfg->lowblk);
870 MODIFY_REG(hperh->perh->WPHR, QSPI_WPHR_HBLKNUM_MSK, wpcfg->upblk);
871 QSPI_WRITE_PROTECT_ENABLE(hperh);
872
873 return;
874 }
875
885 void ald_qspi_write_proect_inverse(qspi_handle_t * hperh, type_func_t state)
886 {
887 assert_param(IS_FUNC_STATE(state));
888 assert_param(IS_QSPI_ALL(hperh->perh));
889
890 if (state) {
891 QSPI_WRITE_PROTECT_DISABLE(hperh);
892 SET_BIT(hperh->perh->WPCR, QSPI_WPCR_WPINV_MSK);
893 QSPI_WRITE_PROTECT_ENABLE(hperh);
894 }
895 else {
896 QSPI_WRITE_PROTECT_DISABLE(hperh);
897 SET_BIT(hperh->perh->WPCR, QSPI_WPCR_WPINV_MSK);
898 QSPI_WRITE_PROTECT_ENABLE(hperh);
899 }
900
901 return;
902 }
903
908 void ald_qspi_irq_handler(qspi_handle_t *hperh)
909 {
910 uint32_t regs = 0;
911 uint32_t tmp = 0, i = 0;
912
913 regs = READ_REG(hperh->perh->DSCR);
914 regs = (regs & 0x0000fff0) >> 4;
915
916 // indirect transmit
917 if (hperh->state == QSPI_STATE_BUSY_TX) {
918
919 //QSPI indirect transmit(xfer length longer than watermark value)
920 if (qspi_get_flag_status(hperh, QSPI_IF_INDTWF) == SET) {
921 ald_qspi_clear_it_flag(hperh, QSPI_IF_INDTWF);
922 tmp = hperh->tx_size - hperh->tx_cnt;
923 if (tmp > regs) {
924 for (i = 0; i < (regs / 4); ++i) {
925 *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(hperh->tx_buf + hperh->tx_cnt + 4 * i));
926 }
927 hperh->tx_cnt += regs;
928 } else {
929 for (i = 0; i < (tmp / 4); ++i) {
930 *(__IO uint32_t *)QSPI_MEMORY_ADDRESS = (*(uint32_t *)(hperh->tx_buf + hperh->tx_cnt + 4 * i));
931 }
932 hperh->tx_cnt += tmp;
933 }
934 }
935 //QSPI indirect transmit completely
936 if (qspi_get_flag_status(hperh, QSPI_IF_INDCF) == SET) {
937 ald_qspi_clear_it_flag(hperh, QSPI_IF_INDCF);
938 ald_qspi_interrupt_config(hperh, QSPI_IT_INDTWF, DISABLE);
939 //transmit completely callback
940 }
941
942 }
943
944 // indirect receive
945 if (hperh->state == QSPI_STATE_BUSY_RX) {
946 if (qspi_get_flag_status(hperh, QSPI_IF_INDTWF) == SET) {
947 ald_qspi_clear_it_flag(hperh, QSPI_IF_INDTWF);
948 tmp = READ_REG(hperh->perh->SFLR);
949 tmp = tmp & 0xffff;
950
951 for (i = 0; i < tmp; ++i) {
952 *(uint32_t *)(hperh->rx_buf + hperh->rx_cnt + i*4) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS;
953 }
954 hperh->rx_cnt += tmp*4;
955 }
956
957 if (qspi_get_flag_status(hperh, QSPI_IF_INDCF) == SET) {
958 ald_qspi_clear_it_flag(hperh, QSPI_IF_INDCF);
959 ald_qspi_interrupt_config(hperh, QSPI_IT_INDTWF, DISABLE);
960
961 tmp = READ_REG(hperh->perh->SFLR);
962 tmp = tmp & 0xffff;
963
964 for (i = 0; i < tmp; ++i) {
965 *(uint32_t *)(hperh->rx_buf + hperh->rx_cnt + i*4) = *(__IO uint32_t *)QSPI_MEMORY_ADDRESS;
966 }
967 }
968 }
969 }
970
982 void ald_qspi_interrupt_config(qspi_handle_t *hperh, qspi_it_t it, type_func_t state)
983 {
984 assert_param(IS_QSPI_ALL(hperh->perh));
985 assert_param(IS_QSPI_IT(it));
986 assert_param(IS_FUNC_STATE(state));
987
988 if (state == ENABLE)
989 hperh->perh->IMR |= (uint32_t)it;
990 else
991 hperh->perh->IMR &= (uint32_t)(~it);
992
993 return;
994 }
995
1002 void ald_qspi_legacy_config(qspi_handle_t* hperh, const qspi_legacy_cfg_t *config)
1003 {
1004 assert_param(IS_QSPI_ALL(hperh->perh));
1005
1006 MODIFY_REG(hperh->perh->TXHR, QSPI_TXHR_TXTH_MSK, config->tx_thrd);
1007 MODIFY_REG(hperh->perh->RXHR, QSPI_RXHR_RXTH_MSK, config->rx_thrd);
1008 QSPI_LEGACY_SPI_ENABLE(hperh);
1009
1010 return;
1011 }
1012
1019 flag_status_t qspi_indwr_get_status(qspi_handle_t *hperh, qspi_indwr_status_t status)
1020 {
1021 assert_param(IS_QSPI_ALL(hperh->perh));
1022 assert_param(IS_QSPI_INDIRECT_WRITE_STATUS(status));
1023
1024 if (hperh->perh->IWTR & status)
1025 return SET;
1026
1027 return RESET;
1028 }
1029
1038 ald_status_t qspi_indwr_wait_flag(qspi_handle_t *hperh, qspi_indwr_status_t flag, flag_status_t status, uint32_t timeout)
1039 {
1040 uint32_t tick;
1041
1042 if (timeout == 0)
1043 return ERROR;
1044
1045 tick = ald_get_tick();
1046
1047 /* Waiting for flag */
1048 while ((qspi_indwr_get_status(hperh, flag)) != status) {
1049 if (((ald_get_tick()) - tick) > timeout)
1050 return TIMEOUT;
1051 }
1052
1053 return OK;
1054 }
1055
1064 ald_status_t qspi_indrd_wait_flag(qspi_handle_t *hperh, qspi_indrd_flag_t flag, flag_status_t status, uint32_t timeout)
1065 {
1066 uint32_t tick;
1067
1068 if (timeout == 0)
1069 return ERROR;
1070
1071 tick = ald_get_tick();
1072
1073 /* Waiting for flag */
1074 while ((qspi_indrd_get_status(hperh, flag)) != status) {
1075 if (((ald_get_tick()) - tick) > timeout)
1076 return TIMEOUT;
1077 }
1078 return OK;
1079 }
1080
1088 void qspi_clear_flag_status(qspi_handle_t *hperh, qspi_flag_t flag)
1089 {
1090 assert_param(IS_QSPI_ALL(hperh->perh));
1091 assert_param(IS_QSPI_IF(flag));
1092
1093 hperh->perh->IFR = flag;
1094 return;
1095 }
1096
1103 #endif /* ALD_QSPI */
1104
IS_QSPI_ALL
#define IS_QSPI_ALL(x)
Definition: ald_qspi.h:380
IS_QSPI_CLOCK_POLARITY
#define IS_QSPI_CLOCK_POLARITY(x)
Definition: ald_qspi.h:415
qspi_read_cfg_t::datxfer
qspi_xfer_t datxfer
Definition: ald_qspi.h:201
qspi_clear_flag_status
void qspi_clear_flag_status(qspi_handle_t *hperh, qspi_flag_t flag)
Clear the QSPI interrupt flag.
Definition: ald_qspi.c:1088
DMA_R_POWER_4
Definition: ald_dma.h:253
ald_qspi_indac_read_by_dma
ald_status_t ald_qspi_indac_read_by_dma(qspi_handle_t *hperh, uint32_t addr, uint8_t *pdbuf, uint16_t size)
Receive an amount of data with DMA.
Definition: ald_qspi.c:749
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
ald_qspi_write_proect_config
void ald_qspi_write_proect_config(qspi_handle_t *hperh, qspi_wr_protect_t *wpcfg)
QSPI Write Protect Configuration.
Definition: ald_qspi.c:865
IS_QSPI_CLOCK_PHASE
#define IS_QSPI_CLOCK_PHASE(x)
Definition: ald_qspi.h:413
qspi_flag_t
qspi_flag_t
QSPI_Flag_definition QSPI Flag Definition.
Definition: ald_qspi.h:342
qspi_device_size_t::cs2
qspi_nss_size_t cs2
Definition: ald_qspi.h:134
qspi_init_t::chpa
qspi_cpha_t chpa
Definition: ald_qspi.h:180
qspi_indac_cfg_t::wrwmark
uint32_t wrwmark
Definition: ald_qspi.h:234
qspi_read_cfg_t::mbitval
uint8_t mbitval
Definition: ald_qspi.h:197
qspi_write_cfg_t::datxfer
qspi_xfer_t datxfer
Definition: ald_qspi.h:212
dma_config_t::R_power
dma_arbiter_config_t R_power
Definition: ald_dma.h:284
QSPI_STATE_BUSY_TX
Definition: ald_qspi.h:38
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
qspi_write_cfg_t::addxfer
qspi_xfer_t addxfer
Definition: ald_qspi.h:211
qspi_dac_cfg_t::remapaddr
uint32_t remapaddr
Definition: ald_qspi.h:247
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
qspi_dly_cfg_t::ccsot
uint32_t ccsot
Definition: ald_qspi.h:276
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
READ_REG
#define READ_REG(reg)
Definition: type.h:73
SET
Definition: type.h:39
qspi_device_size_t::cs1
qspi_nss_size_t cs1
Definition: ald_qspi.h:133
qspi_data_capture_cfg_t::bypsalcc
type_func_t bypsalcc
Definition: ald_qspi.h:288
ALD_MAX_DELAY
#define ALD_MAX_DELAY
Definition: utils.h:88
qspi_device_size_t::cs0
qspi_nss_size_t cs0
Definition: ald_qspi.h:132
qspi_stig_cmd_t::val
uint32_t val
Definition: ald_qspi.h:165
type_func_t
type_func_t
Definition: type.h:47
ald_qspi_device_delay_config
ald_status_t ald_qspi_device_delay_config(qspi_handle_t *hperh, qspi_dly_cfg_t *dlycfg)
QSPI Device Delay Configuration.
Definition: ald_qspi.c:205
qspi_legacy_cfg_t::rx_thrd
uint8_t rx_thrd
Definition: ald_qspi.h:188
qspi_it_t
qspi_it_t
QSPI_Interrupt_definition QSPI Interrupt Definition.
Definition: ald_qspi.h:323
DISABLE
Definition: type.h:48
ald_qspi_device_size_config
ald_status_t ald_qspi_device_size_config(qspi_handle_t *hperh, qspi_device_size_t *devcfg)
QSPI Flash memory Configuration.
Definition: ald_qspi.c:258
IS_QSPI_CLOCK_PRESCALER
#define IS_QSPI_CLOCK_PRESCALER(x)
Definition: ald_qspi.h:397
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
qspi_dac_cfg_t
QSPI DAC configuration.
Definition: ald_qspi.h:241
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
IS_QSPI_INDIRECT_READ_WATERMARK
#define IS_QSPI_INDIRECT_READ_WATERMARK(x)
Definition: ald_qspi.h:367
IS_QSPI_INDIRECT_READ_STATUS
#define IS_QSPI_INDIRECT_READ_STATUS(x)
Definition: ald_qspi.h:369
dma_config_t::src
void * src
Definition: ald_dma.h:278
qspi_device_size_t::cs3
qspi_nss_size_t cs3
Definition: ald_qspi.h:135
qspi_write_cfg_t
QSPI Device Write Instruction Configuration structure.
Definition: ald_qspi.h:208
qspi_device_size_t::page
uint16_t page
Definition: ald_qspi.h:130
IS_QSPI_WR_OPCODE
#define IS_QSPI_WR_OPCODE(x)
Definition: ald_qspi.h:396
qspi_read_cfg_t::dcyles
uint8_t dcyles
Definition: ald_qspi.h:196
DMA_DATA_INC_WORD
Definition: ald_dma.h:219
qspi_handle_t::rx_size
uint16_t rx_size
Definition: ald_qspi.h:263
DMA_DATA_SIZE_WORD
Definition: ald_dma.h:229
IS_QSPI_IT
#define IS_QSPI_IT(x)
Definition: ald_qspi.h:431
ald_qspi.h
Header file of QSPI module driver.
qspi_indac_cfg_t
Definition: ald_qspi.h:230
QSPI_DMA_ENABLE
#define QSPI_DMA_ENABLE(hperh)
Definition: ald_qspi.h:468
qspi_read_cfg_t
QSPI Device Read Instruction Configuration structure.
Definition: ald_qspi.h:194
qspi_read_sram_fill_level
uint16_t qspi_read_sram_fill_level(qspi_handle_t *hperh, qspi_sram_t srt)
Read QSPI SRAM fill level.
Definition: ald_qspi.c:848
qspi_indwr_get_status
flag_status_t qspi_indwr_get_status(qspi_handle_t *hperh, qspi_indwr_status_t status)
Get QSPI indirect write access status.
Definition: ald_qspi.c:1019
qspi_dly_cfg_t::cseot
uint32_t cseot
Definition: ald_qspi.h:277
DMA_MSEL_QSPI
Definition: ald_dma.h:107
qspi_device_size_t::blk
uint16_t blk
Definition: ald_qspi.h:131
qspi_handle_t::init
qspi_init_t init
Definition: ald_qspi.h:258
qspi_read_cfg_t::addxfer
qspi_xfer_t addxfer
Definition: ald_qspi.h:200
qspi_indwr_wait_flag
ald_status_t qspi_indwr_wait_flag(qspi_handle_t *hperh, qspi_indwr_status_t flag, flag_status_t status, uint32_t timeout)
Wait indirect wriet a flag state until time out.
Definition: ald_qspi.c:1038
qspi_write_cfg_t::dcyles
uint8_t dcyles
Definition: ald_qspi.h:210
qspi_dac_cfg_t::ahbdecoder
type_func_t ahbdecoder
Definition: ald_qspi.h:243
IS_QSPI_INDIRECT_TRIGGER_RANGE
#define IS_QSPI_INDIRECT_TRIGGER_RANGE(x)
Definition: ald_qspi.h:366
ald_qspi_write_config
ald_status_t ald_qspi_write_config(qspi_handle_t *hperh, const qspi_write_cfg_t *wrcfg)
Configure Write Operations.
Definition: ald_qspi.c:170
RESET
Definition: type.h:38
ald_qspi_indac_transmit_by_dma
ald_status_t ald_qspi_indac_transmit_by_dma(qspi_handle_t *hperh, uint32_t addr, uint8_t *psrc, uint16_t size)
Sends an amount of data with DMA.
Definition: ald_qspi.c:695
ald_qspi_dac_rd
uint32_t ald_qspi_dac_rd(uint32_t addr)
DAC read.
Definition: ald_qspi.c:111
IS_QSPI_DEVICE_DELAY_CSDADS
#define IS_QSPI_DEVICE_DELAY_CSDADS(x)
Definition: ald_qspi.h:373
qspi_indac_cfg_t::trgaddr
uint32_t trgaddr
Definition: ald_qspi.h:232
qspi_wr_protect_t::upblk
uint32_t upblk
Definition: ald_qspi.h:151
qspi_stig_cmd_t::wr_len
uint32_t wr_len
Definition: ald_qspi.h:161
ald_qspi_indac_transmit_by_poll
ald_status_t ald_qspi_indac_transmit_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size)
Transmit data to flash by poll.
Definition: ald_qspi.c:438
IS_QSPI_NSS_SIZE
#define IS_QSPI_NSS_SIZE(x)
Definition: ald_qspi.h:386
qspi_data_capture_cfg_t
QSPI Read Data Capture Configuration.
Definition: ald_qspi.h:285
qspi_handle_t::tx_buf
uint8_t * tx_buf
Definition: ald_qspi.h:259
qspi_init_t::wrppin
type_func_t wrppin
Definition: ald_qspi.h:176
qspi_indac_cfg_t::srampt
uint32_t srampt
Definition: ald_qspi.h:231
QSPI_WRITE_PROTECT_ENABLE
#define QSPI_WRITE_PROTECT_ENABLE(hperh)
Definition: ald_qspi.h:462
IS_QSPI_READ_DATA_DELAY_TRANSMIT
#define IS_QSPI_READ_DATA_DELAY_TRANSMIT(x)
Definition: ald_qspi.h:379
QSPI_DISABLE
#define QSPI_DISABLE(hperh)
Definition: ald_qspi.h:465
qspi_indac_cfg_t::trgrng
uint32_t trgrng
Definition: ald_qspi.h:233
ald_qspi_dac_wr
void ald_qspi_dac_wr(uint32_t addr, uint32_t dat)
DAC write .
Definition: ald_qspi.c:122
qspi_handle_t::rx_buf
uint8_t * rx_buf
Definition: ald_qspi.h:262
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
qspi_write_cfg_t::autowel
type_func_t autowel
Definition: ald_qspi.h:214
qspi_handle_t::tx_size
uint16_t tx_size
Definition: ald_qspi.h:260
QSPI_MEMORY_ADDRESS
#define QSPI_MEMORY_ADDRESS
Definition: ald_qspi.h:454
ald_qspi_indac_read_by_it
ald_status_t ald_qspi_indac_read_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size)
QSPI read data by interrupt.
Definition: ald_qspi.c:563
QSPI_ENABLE
#define QSPI_ENABLE(hperh)
Definition: ald_qspi.h:464
qspi_data_capture_cfg_t::smpledge
qspi_data_sampled_t smpledge
Definition: ald_qspi.h:289
qspi_handle_t
QSPI Handle Structure definition.
Definition: ald_qspi.h:256
IS_QSPI_RD_OPCODE
#define IS_QSPI_RD_OPCODE(x)
Definition: ald_qspi.h:395
qspi_init_t::chipsel
qspi_nss_t chipsel
Definition: ald_qspi.h:178
QSPI_STATE_BUSY_RX
Definition: ald_qspi.h:39
qspi_stig_cmd_t::rd_len
uint32_t rd_len
Definition: ald_qspi.h:159
qspi_read_cfg_t::instxfer
qspi_xfer_t instxfer
Definition: ald_qspi.h:202
ald_qspi_indac_transmit_by_it
ald_status_t ald_qspi_indac_transmit_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size)
QSPI write data by interrupt.
Definition: ald_qspi.c:388
qspi_stig_cmd_t::addr_len
uint32_t addr_len
Definition: ald_qspi.h:160
qspi_wait_for_idle
static ald_status_t qspi_wait_for_idle(qspi_handle_t *hperh, uint32_t tickstart, uint32_t timeout)
Wait for a flag state until timeout.
Definition: ald_qspi.c:42
IS_QSPI_IF
#define IS_QSPI_IF(x)
Definition: ald_qspi.h:417
IS_QSPI_INDIRECT_WRITE_STATUS
#define IS_QSPI_INDIRECT_WRITE_STATUS(x)
Definition: ald_qspi.h:370
qspi_device_size_t
Qspi external flash device configuration.
Definition: ald_qspi.h:128
ald_qspi_legacy_config
void ald_qspi_legacy_config(qspi_handle_t *hperh, const qspi_legacy_cfg_t *config)
Configure the QSPI legacy .
Definition: ald_qspi.c:1002
qspi_stig_cmd_t::rd_buf
void * rd_buf
Definition: ald_qspi.h:167
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
qspi_handle_t::rx_cnt
uint16_t rx_cnt
Definition: ald_qspi.h:264
qspi_wr_protect_t::lowblk
uint32_t lowblk
Definition: ald_qspi.h:150
qspi_stig_cmd_t::addr
uint32_t addr
Definition: ald_qspi.h:166
IS_QSPI_ADDR_SIZE
#define IS_QSPI_ADDR_SIZE(x)
Definition: ald_qspi.h:383
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
qspi_dac_cfg_t::wrinit
qspi_write_cfg_t wrinit
Definition: ald_qspi.h:250
ald_qspi_clear_it_flag
void ald_qspi_clear_it_flag(qspi_handle_t *hperh, qspi_flag_t flag)
Clear the QSPI interrupt flag.
Definition: ald_qspi.c:832
qspi_stig_cmd_t::wr_buf
void * wr_buf
Definition: ald_qspi.h:168
IS_QSPI_DEVICE_DELAY_CSDA
#define IS_QSPI_DEVICE_DELAY_CSDA(x)
Definition: ald_qspi.h:374
IS_QSPI_READ_DATA_CAPTURE_DELAY_READ
#define IS_QSPI_READ_DATA_CAPTURE_DELAY_READ(x)
Definition: ald_qspi.h:376
DMA_MSIGSEL_QSPI_READ
Definition: ald_dma.h:171
qspi_legacy_cfg_t
QSPI legacy initialization structure.
Definition: ald_qspi.h:186
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
QSPI_SRAM_SIZE
#define QSPI_SRAM_SIZE
Definition: ald_qspi.h:455
qspi_indrd_flag_t
qspi_indrd_flag_t
QSPI Indirect Read Progress Status.
Definition: ald_qspi.h:303
qspi_legacy_cfg_t::tx_thrd
uint8_t tx_thrd
Definition: ald_qspi.h:187
qspi_dac_config
ald_status_t qspi_dac_config(qspi_handle_t *hperh, qspi_dac_cfg_t *dcfg)
Initializes the QSPI direct access according to the specified parameters in the associated handle...
Definition: ald_qspi.c:295
qspi_dac_cfg_t::dtrprtcol
type_func_t dtrprtcol
Definition: ald_qspi.h:242
qspi_read_cfg_t::rdcde
uint8_t rdcde
Definition: ald_qspi.h:195
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
qspi_handle_t::tx_cnt
uint16_t tx_cnt
Definition: ald_qspi.h:261
qspi_handle_t::state
qspi_state_t state
Definition: ald_qspi.h:268
qspi_indac_cfg_t::rdwmark
uint32_t rdwmark
Definition: ald_qspi.h:235
QSPI_TIMEOUT_DEFAULT_VALUE
#define QSPI_TIMEOUT_DEFAULT_VALUE
Definition: ald_qspi.h:456
ald_qspi_indac_read_by_poll
ald_status_t ald_qspi_indac_read_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size)
Read data from flash by poll.
Definition: ald_qspi.c:496
qspi_stig_cmd_t
QSPI STIG Command Structure.
Definition: ald_qspi.h:157
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
QSPI_IT_INDTWF
Definition: ald_qspi.h:331
IS_QSPI_DEVICE_DELAY_CCSOT
#define IS_QSPI_DEVICE_DELAY_CCSOT(x)
Definition: ald_qspi.h:371
qspi_stig_cmd_t::code
uint32_t code
Definition: ald_qspi.h:158
qspi_dac_cfg_t::addrremap
type_func_t addrremap
Definition: ald_qspi.h:246
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
qspi_data_capture_cfg_t::dlytd
uint32_t dlytd
Definition: ald_qspi.h:286
QSPI_IF_INDTWF
Definition: ald_qspi.h:350
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
QSPI_IF_INDCF
Definition: ald_qspi.h:354
QSPI_IT_INDCF
Definition: ald_qspi.h:335
qspi_sram_t
qspi_sram_t
QSPI Indirect Access SRAM fill level.
Definition: ald_qspi.h:54
qspi_indrd_get_status
static flag_status_t qspi_indrd_get_status(qspi_handle_t *hperh, qspi_indrd_flag_t status)
Get indirect read status.
Definition: ald_qspi.c:62
qspi_get_flag_status
flag_status_t qspi_get_flag_status(qspi_handle_t *hperh, qspi_flag_t flag)
Get the status of QSPI interrupt flag.
Definition: ald_qspi.c:814
qspi_write_cfg_t::wrcde
uint8_t wrcde
Definition: ald_qspi.h:209
qspi_data_capture_cfg_t::dlydcl
uint32_t dlydcl
Definition: ald_qspi.h:287
ald_qspi_irq_handler
void ald_qspi_irq_handler(qspi_handle_t *hperh)
QSPI interrupt handler.
Definition: ald_qspi.c:908
qspi_init_t::clkdiv
qspi_clk_div_t clkdiv
Definition: ald_qspi.h:175
ald_qspi_init
void ald_qspi_init(qspi_handle_t *hperh)
Initializes the QSPI basic parameters.
Definition: ald_qspi.c:90
qspi_dac_cfg_t::rdinit
qspi_read_cfg_t rdinit
Definition: ald_qspi.h:249
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
flag_status_t
flag_status_t
Definition: type.h:37
ald_qspi_interrupt_config
void ald_qspi_interrupt_config(qspi_handle_t *hperh, qspi_it_t it, type_func_t state)
Enable/disable the specified QSPI interrupts.
Definition: ald_qspi.c:982
ald_qspi_write_proect_inverse
void ald_qspi_write_proect_inverse(qspi_handle_t *hperh, type_func_t state)
QSPI Write Protect Inversion.
Definition: ald_qspi.c:885
QSPI_LEGACY_SPI_ENABLE
#define QSPI_LEGACY_SPI_ENABLE(hperh)
Definition: ald_qspi.h:460
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
qspi_stig_cmd_t::d_sycle
uint32_t d_sycle
Definition: ald_qspi.h:162
QSPI_WRITE_PROTECT_DISABLE
#define QSPI_WRITE_PROTECT_DISABLE(hperh)
Definition: ald_qspi.h:463
qspi_dly_cfg_t::csdads
uint32_t csdads
Definition: ald_qspi.h:278
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
QSPI_SRAM_RD
Definition: ald_qspi.h:55
qspi_dly_cfg_t
Defines command to be executed using STIG mechanism.
Definition: ald_qspi.h:275
IS_QSPI_DEVICE_DELAY_CSEOT
#define IS_QSPI_DEVICE_DELAY_CSEOT(x)
Definition: ald_qspi.h:372
qspi_stig_cmd_t::mode_bit
type_func_t mode_bit
Definition: ald_qspi.h:163
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257
qspi_write_cfg_t::instxfer
qspi_xfer_t instxfer
Definition: ald_qspi.h:213
IS_QSPI_PAGE_SIZE
#define IS_QSPI_PAGE_SIZE(x)
Definition: ald_qspi.h:384
ald_qspi_read_config
ald_status_t ald_qspi_read_config(qspi_handle_t *hperh, const qspi_read_cfg_t *rdcfg)
Configure Read Operations.
Definition: ald_qspi.c:133
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
IS_QSPI_READ_DATA_SAMPLE_EDGE
#define IS_QSPI_READ_DATA_SAMPLE_EDGE(x)
Definition: ald_qspi.h:377
qspi_wr_protect_t
Flash write-protected blocks configuration.
Definition: ald_qspi.h:149
IS_QSPI_XFER_TYPE
#define IS_QSPI_XFER_TYPE(x)
Definition: ald_qspi.h:388
IS_QSPI_SRAM_PARTITION
#define IS_QSPI_SRAM_PARTITION(x)
Definition: ald_qspi.h:365
IS_QSPI_INDIRECT_SRAM_FILL_TYPE
#define IS_QSPI_INDIRECT_SRAM_FILL_TYPE(x)
Definition: ald_qspi.h:368
qspi_handle_t::hdma
dma_handle_t hdma
Definition: ald_qspi.h:266
__LOCK
#define __LOCK(x)
Definition: utils.h:92
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
ERROR
Definition: utils.h:56
qspi_device_size_t::addr
uint8_t addr
Definition: ald_qspi.h:129
qspi_dly_cfg_t::csda
uint32_t csda
Definition: ald_qspi.h:279
ald_qspi_execute_stig_cmd
ald_status_t ald_qspi_execute_stig_cmd(qspi_handle_t *hperh, const qspi_stig_cmd_t *stigcmd)
Execute a STIG command.
Definition: ald_qspi.c:594
IS_QSPI_BLOCK_SIZE
#define IS_QSPI_BLOCK_SIZE(x)
Definition: ald_qspi.h:385
ald_qspi_indac_config
ald_status_t ald_qspi_indac_config(qspi_handle_t *hperh, qspi_indac_cfg_t *indcfg)
Initializes the QSPI indirect access according to the specified parameters in the associated handle...
Definition: ald_qspi.c:352
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
DMA_MSIGSEL_QSPI_WRITE
Definition: ald_dma.h:170
ald_qspi_read_data_capture_config
ald_status_t ald_qspi_read_data_capture_config(qspi_handle_t *hperh, qspi_data_capture_cfg_t *dtcptcfg)
QSPI Read Data Capture Configuration.
Definition: ald_qspi.c:232
qspi_read_cfg_t::ddrbit
type_func_t ddrbit
Definition: ald_qspi.h:198
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
qspi_indwr_status_t
qspi_indwr_status_t
QSPI Indirect Write Progress Status.
Definition: ald_qspi.h:295
qspi_indrd_wait_flag
ald_status_t qspi_indrd_wait_flag(qspi_handle_t *hperh, qspi_indrd_flag_t flag, flag_status_t status, uint32_t timeout)
QSPI Indirect read operation wait for specified status.
Definition: ald_qspi.c:1064
qspi_init_t::cpol
qspi_cpol_t cpol
Definition: ald_qspi.h:179
qspi_read_cfg_t::modebit
type_func_t modebit
Definition: ald_qspi.h:199
IS_QSPI_DCYLES
#define IS_QSPI_DCYLES(x)
Definition: ald_qspi.h:381


ALD User Manual: D:/svn/src/ald_qspi.h Source File

  • D:
  • svn
  • src
ald_qspi.h
Go to the documentation of this file.
1 /***************************************************************************/
14 #ifndef __ALD_QSPI_H_
15 #define __ALD_QSPI_H_
16
17 #ifdef __cplusplus
18 extern "C" {
19 #endif
20
21 #include "utils.h"
22 #include "ald_dma.h"
23
37 typedef enum {
38 QSPI_STATE_BUSY_TX = 0x11U,
39 QSPI_STATE_BUSY_RX = 0x21U,
40 } qspi_state_t;
41
45 typedef enum {
46 QSPI_XFER_SINGLE = 0x00U,
47 QSPI_XFER_DUAL = 0x01U,
48 QSPI_XFER_QUAD = 0x02U,
49 } qspi_xfer_t;
50
54 typedef enum {
55 QSPI_SRAM_RD = 0U,
56 QSPI_SRAM_WR = 1U,
57 } qspi_sram_t;
58
62 typedef enum {
63 QSPI_CPHA_1E = 0U,
64 QSPI_CPHA_2E = 1U,
65 } qspi_cpha_t;
66
70 typedef enum {
71 QSPI_CPOL_L = 0U,
72 QSPI_CPOL_H = 1U,
73 } qspi_cpol_t;
74
78 typedef enum {
79 QSPI_SINGLE_CHIP = 0x0U,
80 QSPI_MULTI_CHIP = 0x1U,
81 } qspi_nss_decode_t;
82
86 typedef enum {
87 QSPI_DIV_2 = 0x0U,
88 QSPI_DIV_4 = 0x1U,
89 QSPI_DIV_6 = 0x2U,
90 QSPI_DIV_8 = 0x3U,
91 QSPI_DIV_10 = 0x4U,
92 QSPI_DIV_12 = 0x5U,
93 QSPI_DIV_14 = 0x6U,
94 QSPI_DIV_16 = 0x7U,
95 QSPI_DIV_18 = 0x8U,
96 QSPI_DIV_20 = 0x9U,
97 QSPI_DIV_22 = 0xAU,
98 QSPI_DIV_24 = 0xBU,
99 QSPI_DIV_26 = 0xCU,
100 QSPI_DIV_28 = 0xDU,
101 QSPI_DIV_30 = 0xEU,
102 QSPI_DIV_32 = 0xFU,
103 } qspi_clk_div_t;
104
108 typedef enum {
109 QSPI_CS_NSS0 = 0x0U,
110 QSPI_CS_NSS1 = 0x1U,
111 QSPI_CS_NSS2 = 0x3U,
112 QSPI_CS_NSS3 = 0x7U,
113 } qspi_nss_t;
114
118 typedef enum {
119 QSPI_NSS_512M = 0x0U,
120 QSPI_NSS_1G = 0x1U,
121 QSPI_NSS_2G = 0x2U,
122 QSPI_NSS_4G = 0x3U,
123 } qspi_nss_size_t;
124
128 typedef struct {
129 uint8_t addr;
130 uint16_t page;
131 uint16_t blk;
132 qspi_nss_size_t cs0;
133 qspi_nss_size_t cs1;
134 qspi_nss_size_t cs2;
135 qspi_nss_size_t cs3;
136 } qspi_device_size_t;
137
141 typedef enum {
142 QSPI_FALLING_E = 0x0U,
143 QSPI_RISING_E = 0x1U,
144 } qspi_data_sampled_t;
145
149 typedef struct {
150 uint32_t lowblk;
151 uint32_t upblk;
152 } qspi_wr_protect_t;
153
157 typedef struct {
158 uint32_t code;
159 uint32_t rd_len;
160 uint32_t addr_len;
161 uint32_t wr_len;
162 uint32_t d_sycle;
163 type_func_t mode_bit;
164 type_func_t op_addr;
165 uint32_t val;
166 uint32_t addr;
167 void *rd_buf;
168 void *wr_buf;
169 } qspi_stig_cmd_t;
170
174 typedef struct {
175 qspi_clk_div_t clkdiv;
176 type_func_t wrppin;
177 qspi_nss_decode_t nssdcode;
178 qspi_nss_t chipsel;
179 qspi_cpol_t cpol;
180 qspi_cpha_t chpa;
181 } qspi_init_t;
182
186 typedef struct {
187 uint8_t tx_thrd;
188 uint8_t rx_thrd;
189 } qspi_legacy_cfg_t;
190
194 typedef struct {
195 uint8_t rdcde;
196 uint8_t dcyles;
197 uint8_t mbitval;
198 type_func_t ddrbit;
199 type_func_t modebit;
200 qspi_xfer_t addxfer;
201 qspi_xfer_t datxfer;
202 qspi_xfer_t instxfer;
203 } qspi_read_cfg_t;
204
208 typedef struct {
209 uint8_t wrcde;
210 uint8_t dcyles;
211 qspi_xfer_t addxfer;
212 qspi_xfer_t datxfer;
213 qspi_xfer_t instxfer;
214 type_func_t autowel;
215 } qspi_write_cfg_t;
216
220 typedef struct {
221 uint32_t saddr;
222 uint32_t wrlen;
223 } qspi_indac_wr_cfg_t;
224
225 typedef struct {
226 uint32_t saddr;
227 uint32_t rdlen;
228 } qspi_indac_rd_cfg_t;
229
230 typedef struct {
231 uint32_t srampt;
232 uint32_t trgaddr;
233 uint32_t trgrng;
234 uint32_t wrwmark;
235 uint32_t rdwmark;
236 } qspi_indac_cfg_t;
237
241 typedef struct {
242 type_func_t dtrprtcol;
243 type_func_t ahbdecoder;
244 type_func_t xipimmed;
245 type_func_t xipnextrd;
246 type_func_t addrremap;
247 uint32_t remapaddr;
248 type_func_t dmaperh;
249 qspi_read_cfg_t rdinit;
250 qspi_write_cfg_t wrinit;
251 } qspi_dac_cfg_t;
252
256 typedef struct {
257 QSPI_TypeDef *perh;
258 qspi_init_t init;
259 uint8_t *tx_buf;
260 uint16_t tx_size;
261 uint16_t tx_cnt;
262 uint8_t *rx_buf;
263 uint16_t rx_size;
264 uint16_t rx_cnt;
265 #ifdef ALD_DMA
266 dma_handle_t hdma;
267 #endif
268 qspi_state_t state;
269 __IO lock_state_t lock;
270 } qspi_handle_t;
271
275 typedef struct {
276 uint32_t ccsot;
277 uint32_t cseot;
278 uint32_t csdads;
279 uint32_t csda;
280 } qspi_dly_cfg_t;
281
285 typedef struct {
286 uint32_t dlytd;
287 uint32_t dlydcl;
288 type_func_t bypsalcc;
289 qspi_data_sampled_t smpledge;
290 } qspi_data_capture_cfg_t;
291
295 typedef enum {
296 QSPI_INDWR_PROGRESS = (1U << 2),
297 QSPI_INDWR_CPLT = (1U << 5),
298 } qspi_indwr_status_t;
299
303 typedef enum {
304 QSPI_INDRD_PROGRESS = (1U << 2),
305 QSPI_RD_CPLT = (1U << 5),
306 } qspi_indrd_flag_t;
307
311 typedef struct {
312 uint32_t opcode;
313 uint32_t indx;
314 uint32_t polarity;
315 uint32_t validcnt;
316 uint32_t repdly;
317 uint32_t polexpcnt;
318 } qspi_auto_poll_t;
319
323 typedef enum {
324 QSPI_IT_POLLF = (1U << 13),
325 QSPI_IT_INDRSFF = (1U << 12),
326 QSPI_IT_SRFFF = (1U << 11),
327 QSPI_IT_SRFNEF = (1U << 10),
328 QSPI_IT_STFFF = (1U << 9),
329 QSPI_IT_STFNFF = (1U << 8),
330 QSPI_IT_ROVF = (1U << 7),
331 QSPI_IT_INDTWF = (1U << 6),
332 QSPI_IT_AHBAEF = (1U << 5),
333 QSPI_IT_WPAF = (1U << 4),
334 QSPI_IT_INDRRF = (1U << 3),
335 QSPI_IT_INDCF = (1U << 2),
336 QSPI_IT_UDFF = (1U << 1),
337 QSPI_IT_MODFF = (1U << 0),
338 } qspi_it_t;
342 typedef enum {
343 QSPI_IF_POLLF = (1U << 13),
344 QSPI_IF_INDRSFF = (1U << 12),
345 QSPI_IF_SRFFF = (1U << 11),
346 QSPI_IF_SRFNEF = (1U << 10),
347 QSPI_IF_STFFF = (1U << 9),
348 QSPI_IF_STFNFF = (1U << 8),
349 QSPI_IF_ROVF = (1U << 7),
350 QSPI_IF_INDTWF = (1U << 6),
351 QSPI_IF_AHBAEF = (1U << 5),
352 QSPI_IF_WPAF = (1U << 4),
353 QSPI_IF_INDRRF = (1U << 3),
354 QSPI_IF_INDCF = (1U << 2),
355 QSPI_IF_UDFF = (1U << 1),
356 QSPI_IF_MODFF = (1U << 0),
357 } qspi_flag_t;
365 #define IS_QSPI_SRAM_PARTITION(x) ((x) < 255)
366 #define IS_QSPI_INDIRECT_TRIGGER_RANGE(x) (((x) < 16))
367 #define IS_QSPI_INDIRECT_READ_WATERMARK(x) ((x) < 512)
368 #define IS_QSPI_INDIRECT_SRAM_FILL_TYPE(x) (((x) == QSPI_SRAM_RD) || ((x) == QSPI_SRAM_WR))
369 #define IS_QSPI_INDIRECT_READ_STATUS(x) (((x) == QSPI_INDRD_PROGRESS) || ((x) == QSPI_RD_CPLT))
370 #define IS_QSPI_INDIRECT_WRITE_STATUS(x) (((x) == QSPI_INDWR_PROGRESS) || ((x) == QSPI_INDWR_CPLT))
371 #define IS_QSPI_DEVICE_DELAY_CCSOT(x) ((x) < 256)
372 #define IS_QSPI_DEVICE_DELAY_CSEOT(x) ((x) < 256)
373 #define IS_QSPI_DEVICE_DELAY_CSDADS(x) ((x) < 256)
374 #define IS_QSPI_DEVICE_DELAY_CSDA(x) ((x) < 256)
375
376 #define IS_QSPI_READ_DATA_CAPTURE_DELAY_READ(x) ((x) < 16)
377 #define IS_QSPI_READ_DATA_SAMPLE_EDGE(x) (((x) == QSPI_FALLING_E) || \
378 ((x) == QSPI_RISING_E))
379 #define IS_QSPI_READ_DATA_DELAY_TRANSMIT(x) ((x) < 16)
380 #define IS_QSPI_ALL(x) ((x) == QSPI)
381 #define IS_QSPI_DCYLES(x) ((x) <= 31)
382
383 #define IS_QSPI_ADDR_SIZE(x) ((x) <= 15)
384 #define IS_QSPI_PAGE_SIZE(x) ((x) <= 0xfff)
385 #define IS_QSPI_BLOCK_SIZE(x) ((x) <= 0x1f)
386 #define IS_QSPI_NSS_SIZE(x) ((x) <= 3)
387
388 #define IS_QSPI_XFER_TYPE(x) (((x) == QSPI_XFER_SINGLE) || \
389 ((x) == QSPI_XFER_DUAL) || \
390 ((x) == QSPI_XFER_QUAD))
391 #define IS_QSPI_DDR_BIT_ENABLE(x) (((x) == QSPI_READ_DDR_BIT_DISABLE) || \
392 ((x) == QSPI_READ_DDR_BIT_ENABLE))
393 #define IS_QSPI_MODE_BIT_ENABLE(x) (((x) == QSPI_READ_INST_MODE_BIT_DISABLE) || \
394 ((x) == QSPI_READ_INST_MODE_BIT_ENABLE))
395 #define IS_QSPI_RD_OPCODE(x) (((x) < 0xFF))
396 #define IS_QSPI_WR_OPCODE(x) (((x) < 0xFF))
397 #define IS_QSPI_CLOCK_PRESCALER(x) (((x) == QSPI_DIV_2) || \
398 ((x) == QSPI_DIV_4) || \
399 ((x) == QSPI_DIV_6) || \
400 ((x) == QSPI_DIV_8) || \
401 ((x) == QSPI_DIV_10) || \
402 ((x) == QSPI_DIV_12) || \
403 ((x) == QSPI_DIV_14) || \
404 ((x) == QSPI_DIV_16) || \
405 ((x) == QSPI_DIV_18) || \
406 ((x) == QSPI_DIV_20) || \
407 ((x) == QSPI_DIV_22) || \
408 ((x) == QSPI_DIV_24) || \
409 ((x) == QSPI_DIV_26) || \
410 ((x) == QSPI_DIV_28) || \
411 ((x) == QSPI_DIV_30) || \
412 ((x) == QSPI_DIV_32))
413 #define IS_QSPI_CLOCK_PHASE(x) (((x) == QSPI_CPHA_1E) || \
414 ((x) == QSPI_CPHA_2E))
415 #define IS_QSPI_CLOCK_POLARITY(x) (((x) == QSPI_CPOL_L) || \
416 ((x) == QSPI_CPOL_H))
417 #define IS_QSPI_IF(x) (((x) == QSPI_IF_POLLF) || \
418 ((x) == QSPI_IF_INDRSFF) || \
419 ((x) == QSPI_IF_SRFFF) || \
420 ((x) == QSPI_IF_SRFNEF) || \
421 ((x) == QSPI_IF_STFFF) || \
422 ((x) == QSPI_IF_STFNFF) || \
423 ((x) == QSPI_IF_ROVF) || \
424 ((x) == QSPI_IF_INDTWF) || \
425 ((x) == QSPI_IF_AHBAEF) || \
426 ((x) == QSPI_IF_WPAF) || \
427 ((x) == QSPI_IF_INDRRF) || \
428 ((x) == QSPI_IF_INDCF) || \
429 ((x) == QSPI_IF_UDFF) || \
430 ((x) == QSPI_IF_MODFF))
431 #define IS_QSPI_IT(x) (((x) == QSPI_IT_POLLF) || \
432 ((x) == QSPI_IT_INDRSFF) || \
433 ((x) == QSPI_IT_SRFFF) || \
434 ((x) == QSPI_IT_SRFNEF) || \
435 ((x) == QSPI_IT_STFFF) || \
436 ((x) == QSPI_IT_STFNFF) || \
437 ((x) == QSPI_IT_ROVF) || \
438 ((x) == QSPI_IT_INDTWF) || \
439 ((x) == QSPI_IT_AHBAEF) || \
440 ((x) == QSPI_IT_WPAF) || \
441 ((x) == QSPI_IT_INDRRF) || \
442 ((x) == QSPI_IT_INDCF) || \
443 ((x) == QSPI_IT_UDFF) || \
444 ((x) == QSPI_IT_MODFF))
445
454 #define QSPI_MEMORY_ADDRESS 0x90000000U
455 #define QSPI_SRAM_SIZE 255U
456 #define QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5s */
457 #define QSPI_SRAM_DEPTH 0xFFU
458 #define QSPI_DAC_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_DACEN_MSK)
459 #define QSPI_DAC_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_DACEN_MSK)
460 #define QSPI_LEGACY_SPI_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_LIMEN_MSK)
461 #define QSPI_LEGACY_SPI_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_LIMEN_MSK)
462 #define QSPI_WRITE_PROTECT_ENABLE(hperh) SET_BIT((hperh)->perh->WPCR, QSPI_WPCR_WPEN_MSK);
463 #define QSPI_WRITE_PROTECT_DISABLE(hperh) CLEAR_BIT((hperh)->perh->WPCR, QSPI_WPCR_WPEN_MSK);
464 #define QSPI_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_EN_MSK)
465 #define QSPI_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_EN_MSK)
466 #define QSPI_AUTO_POLL_ENABLE(hperh) CLEAR_BIT((hperh)->perh->WCR, QSPI_WCR_PDIS_MSK)
467 #define QSPI_AUTO_POLL_DISABLE(hperh) SET_BIT((hperh)->perh->WCR, QSPI_WCR_PDIS_MSK)
468 #define QSPI_DMA_ENABLE(hperh) SET_BIT((hperh)->perh->CR, QSPI_CR_DMAEN_MSK)
469 #define QSPI_DMA_DISABLE(hperh) CLEAR_BIT((hperh)->perh->CR, QSPI_CR_DMAEN_MSK)
470 #define QSPI_CANCEL_INDIRECT_READ(hperh) SET_BIT((hperh)->perh->IRTR, QSPI_IRTR_RDDIS_MSK)
471
482 /* QSPI basic execution functions */
483 void ald_qspi_init(qspi_handle_t *hperh);
484 uint32_t ald_qspi_dac_rd(uint32_t addr);
485 void ald_qspi_dac_wr(uint32_t addr, uint32_t dat);
486 ald_status_t ald_qspi_read_config(qspi_handle_t* hperh, const qspi_read_cfg_t * rdcfg);
487 ald_status_t ald_qspi_write_config(qspi_handle_t* hperh, const qspi_write_cfg_t * wrcfg);
488 ald_status_t ald_qspi_device_delay_config(qspi_handle_t * hperh, qspi_dly_cfg_t *dlycfg);
489 ald_status_t ald_qspi_read_data_capture_config(qspi_handle_t * hperh, qspi_data_capture_cfg_t *dtcptcfg);
490 ald_status_t ald_qspi_device_size_config(qspi_handle_t *hperh, qspi_device_size_t * devcfg);
491 ald_status_t qspi_dac_config(qspi_handle_t * hperh, qspi_dac_cfg_t * dcfg);
498 /* QSPI indirect and stig access execution functions */
499 ald_status_t ald_qspi_indac_config(qspi_handle_t * hperh, qspi_indac_cfg_t *indcfg);
500 ald_status_t ald_qspi_indac_transmit_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size);
501 ald_status_t ald_qspi_indac_transmit_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size);
502 ald_status_t ald_qspi_indac_read_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size);
503 ald_status_t ald_qspi_indac_read_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size);
504 ald_status_t ald_qspi_execute_stig_cmd(qspi_handle_t* hperh, const qspi_stig_cmd_t * scmd);
505 #ifdef ALD_DMA
506 ald_status_t ald_qspi_indac_transmit_by_dma(qspi_handle_t *hperh, uint32_t addr, uint8_t *psrc, uint16_t size);
507 ald_status_t ald_qspi_indac_read_by_dma(qspi_handle_t *hperh, uint32_t addr, uint8_t *pdbuf, uint16_t size);
508 #endif
509
515 /* QSPI status functions */
516 flag_status_t qspi_get_flag_status(qspi_handle_t *hperh, qspi_flag_t flag);
517 void ald_qspi_clear_it_flag(qspi_handle_t *hperh, qspi_flag_t flag);
518 uint16_t qspi_read_sram_fill_level(qspi_handle_t * hperh, qspi_sram_t srt);
519 void ald_qspi_write_proect_config(qspi_handle_t * hperh, qspi_wr_protect_t* wpcfg);
520 void ald_qspi_write_proect_inverse(qspi_handle_t * hperh, type_func_t state);
521 ald_status_t ald_qspi_auto_poll(qspi_handle_t *hperh, qspi_auto_poll_t* apcfg);
522 void ald_qspi_irq_handler(qspi_handle_t *hperh);
523 void ald_qspi_interrupt_config(qspi_handle_t *hperh, qspi_it_t it, type_func_t state);
524 void ald_qspi_legacy_config(qspi_handle_t* hperh, const qspi_legacy_cfg_t *config);
525 flag_status_t qspi_indwr_get_status(qspi_handle_t *hperh, qspi_indwr_status_t status);
526 ald_status_t qspi_indwr_wait_flag(qspi_handle_t *hperh, qspi_indwr_status_t flag, flag_status_t status, uint32_t timeout);
539 #ifdef __cplusplus
540 }
541 #endif
542 #endif /* __ALD_QSPI_H__ */
QSPI_DIV_4
Definition: ald_qspi.h:88
qspi_read_cfg_t::datxfer
qspi_xfer_t datxfer
Definition: ald_qspi.h:201
QSPI_IT_AHBAEF
Definition: ald_qspi.h:332
qspi_auto_poll_t::opcode
uint32_t opcode
Definition: ald_qspi.h:312
qspi_auto_poll_t::repdly
uint32_t repdly
Definition: ald_qspi.h:316
qspi_init_t
QSPI base initialization structure.
Definition: ald_qspi.h:174
QSPI_XFER_SINGLE
Definition: ald_qspi.h:46
qspi_nss_size_t
qspi_nss_size_t
Size of flash connected to CS[x](x = 0 ~ 3)pin.
Definition: ald_qspi.h:118
qspi_indac_wr_cfg_t::wrlen
uint32_t wrlen
Definition: ald_qspi.h:222
ald_qspi_indac_read_by_dma
ald_status_t ald_qspi_indac_read_by_dma(qspi_handle_t *hperh, uint32_t addr, uint8_t *pdbuf, uint16_t size)
Receive an amount of data with DMA.
Definition: ald_qspi.c:749
QSPI_IT_WPAF
Definition: ald_qspi.h:333
ald_qspi_write_proect_config
void ald_qspi_write_proect_config(qspi_handle_t *hperh, qspi_wr_protect_t *wpcfg)
QSPI Write Protect Configuration.
Definition: ald_qspi.c:865
qspi_indac_rd_cfg_t::saddr
uint32_t saddr
Definition: ald_qspi.h:226
qspi_flag_t
qspi_flag_t
QSPI_Flag_definition QSPI Flag Definition.
Definition: ald_qspi.h:342
qspi_device_size_t::cs2
qspi_nss_size_t cs2
Definition: ald_qspi.h:134
qspi_init_t::chpa
qspi_cpha_t chpa
Definition: ald_qspi.h:180
qspi_indac_cfg_t::wrwmark
uint32_t wrwmark
Definition: ald_qspi.h:234
qspi_read_cfg_t::mbitval
uint8_t mbitval
Definition: ald_qspi.h:197
QSPI_CPOL_H
Definition: ald_qspi.h:72
QSPI_MULTI_CHIP
Definition: ald_qspi.h:80
QSPI_RD_CPLT
Definition: ald_qspi.h:305
qspi_write_cfg_t::datxfer
qspi_xfer_t datxfer
Definition: ald_qspi.h:212
QSPI_IF_UDFF
Definition: ald_qspi.h:355
dma_handle_t
DMA handle structure definition.
Definition: ald_dma.h:297
QSPI_STATE_BUSY_TX
Definition: ald_qspi.h:38
QSPI_DIV_10
Definition: ald_qspi.h:91
qspi_init_t::nssdcode
qspi_nss_decode_t nssdcode
Definition: ald_qspi.h:177
qspi_write_cfg_t::addxfer
qspi_xfer_t addxfer
Definition: ald_qspi.h:211
qspi_dac_cfg_t::remapaddr
uint32_t remapaddr
Definition: ald_qspi.h:247
qspi_dly_cfg_t::ccsot
uint32_t ccsot
Definition: ald_qspi.h:276
qspi_device_size_t::cs1
qspi_nss_size_t cs1
Definition: ald_qspi.h:133
qspi_data_capture_cfg_t::bypsalcc
type_func_t bypsalcc
Definition: ald_qspi.h:288
qspi_device_size_t::cs0
qspi_nss_size_t cs0
Definition: ald_qspi.h:132
qspi_stig_cmd_t::val
uint32_t val
Definition: ald_qspi.h:165
type_func_t
type_func_t
Definition: type.h:47
QSPI_DIV_32
Definition: ald_qspi.h:102
ald_qspi_device_delay_config
ald_status_t ald_qspi_device_delay_config(qspi_handle_t *hperh, qspi_dly_cfg_t *dlycfg)
QSPI Device Delay Configuration.
Definition: ald_qspi.c:205
qspi_legacy_cfg_t::rx_thrd
uint8_t rx_thrd
Definition: ald_qspi.h:188
qspi_it_t
qspi_it_t
QSPI_Interrupt_definition QSPI Interrupt Definition.
Definition: ald_qspi.h:323
ald_qspi_device_size_config
ald_status_t ald_qspi_device_size_config(qspi_handle_t *hperh, qspi_device_size_t *devcfg)
QSPI Flash memory Configuration.
Definition: ald_qspi.c:258
ald_qspi_auto_poll
ald_status_t ald_qspi_auto_poll(qspi_handle_t *hperh, qspi_auto_poll_t *apcfg)
qspi_dac_cfg_t
QSPI DAC configuration.
Definition: ald_qspi.h:241
QSPI_CS_NSS3
Definition: ald_qspi.h:112
QSPI_IF_STFFF
Definition: ald_qspi.h:347
QSPI_INDWR_CPLT
Definition: ald_qspi.h:297
qspi_device_size_t::cs3
qspi_nss_size_t cs3
Definition: ald_qspi.h:135
qspi_write_cfg_t
QSPI Device Write Instruction Configuration structure.
Definition: ald_qspi.h:208
QSPI_DIV_26
Definition: ald_qspi.h:99
QSPI_INDWR_PROGRESS
Definition: ald_qspi.h:296
qspi_device_size_t::page
uint16_t page
Definition: ald_qspi.h:130
qspi_read_cfg_t::dcyles
uint8_t dcyles
Definition: ald_qspi.h:196
QSPI_IF_POLLF
Definition: ald_qspi.h:343
qspi_handle_t::rx_size
uint16_t rx_size
Definition: ald_qspi.h:263
qspi_indac_cfg_t
Definition: ald_qspi.h:230
qspi_read_cfg_t
QSPI Device Read Instruction Configuration structure.
Definition: ald_qspi.h:194
qspi_clk_div_t
qspi_clk_div_t
QSPI_Baud_Rate_Clock_Prescaler QSPI Baud Rate Clock Prescaler.
Definition: ald_qspi.h:86
qspi_read_sram_fill_level
uint16_t qspi_read_sram_fill_level(qspi_handle_t *hperh, qspi_sram_t srt)
Read QSPI SRAM fill level.
Definition: ald_qspi.c:848
qspi_indwr_get_status
flag_status_t qspi_indwr_get_status(qspi_handle_t *hperh, qspi_indwr_status_t status)
Get QSPI indirect write access status.
Definition: ald_qspi.c:1019
qspi_dly_cfg_t::cseot
uint32_t cseot
Definition: ald_qspi.h:277
QSPI_IF_SRFFF
Definition: ald_qspi.h:345
qspi_device_size_t::blk
uint16_t blk
Definition: ald_qspi.h:131
qspi_handle_t::init
qspi_init_t init
Definition: ald_qspi.h:258
qspi_read_cfg_t::addxfer
qspi_xfer_t addxfer
Definition: ald_qspi.h:200
qspi_nss_decode_t
qspi_nss_decode_t
QSPI peripheral select decode.
Definition: ald_qspi.h:78
qspi_indwr_wait_flag
ald_status_t qspi_indwr_wait_flag(qspi_handle_t *hperh, qspi_indwr_status_t flag, flag_status_t status, uint32_t timeout)
Wait indirect wriet a flag state until time out.
Definition: ald_qspi.c:1038
QSPI_IF_INDRRF
Definition: ald_qspi.h:353
qspi_write_cfg_t::dcyles
uint8_t dcyles
Definition: ald_qspi.h:210
qspi_dac_cfg_t::ahbdecoder
type_func_t ahbdecoder
Definition: ald_qspi.h:243
QSPI_INDRD_PROGRESS
Definition: ald_qspi.h:304
QSPI_DIV_30
Definition: ald_qspi.h:101
ald_qspi_write_config
ald_status_t ald_qspi_write_config(qspi_handle_t *hperh, const qspi_write_cfg_t *wrcfg)
Configure Write Operations.
Definition: ald_qspi.c:170
ald_qspi_indac_transmit_by_dma
ald_status_t ald_qspi_indac_transmit_by_dma(qspi_handle_t *hperh, uint32_t addr, uint8_t *psrc, uint16_t size)
Sends an amount of data with DMA.
Definition: ald_qspi.c:695
QSPI_DIV_16
Definition: ald_qspi.h:94
ald_qspi_dac_rd
uint32_t ald_qspi_dac_rd(uint32_t addr)
DAC read.
Definition: ald_qspi.c:111
utils.h
This file contains the Utilities functions/types for the driver.
qspi_indac_cfg_t::trgaddr
uint32_t trgaddr
Definition: ald_qspi.h:232
qspi_wr_protect_t::upblk
uint32_t upblk
Definition: ald_qspi.h:151
qspi_stig_cmd_t::wr_len
uint32_t wr_len
Definition: ald_qspi.h:161
ald_qspi_indac_transmit_by_poll
ald_status_t ald_qspi_indac_transmit_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size)
Transmit data to flash by poll.
Definition: ald_qspi.c:438
QSPI_CS_NSS2
Definition: ald_qspi.h:111
qspi_handle_t::lock
__IO lock_state_t lock
Definition: ald_qspi.h:269
qspi_data_capture_cfg_t
QSPI Read Data Capture Configuration.
Definition: ald_qspi.h:285
QSPI_IF_INDRSFF
Definition: ald_qspi.h:344
qspi_handle_t::tx_buf
uint8_t * tx_buf
Definition: ald_qspi.h:259
qspi_init_t::wrppin
type_func_t wrppin
Definition: ald_qspi.h:176
QSPI_IF_SRFNEF
Definition: ald_qspi.h:346
QSPI_NSS_512M
Definition: ald_qspi.h:119
qspi_indac_cfg_t::srampt
uint32_t srampt
Definition: ald_qspi.h:231
QSPI_CS_NSS0
Definition: ald_qspi.h:109
qspi_indac_cfg_t::trgrng
uint32_t trgrng
Definition: ald_qspi.h:233
QSPI_IT_SRFNEF
Definition: ald_qspi.h:327
ald_qspi_dac_wr
void ald_qspi_dac_wr(uint32_t addr, uint32_t dat)
DAC write .
Definition: ald_qspi.c:122
QSPI_DIV_24
Definition: ald_qspi.h:98
qspi_handle_t::rx_buf
uint8_t * rx_buf
Definition: ald_qspi.h:262
QSPI_IT_INDRSFF
Definition: ald_qspi.h:325
QSPI_IT_MODFF
Definition: ald_qspi.h:337
qspi_write_cfg_t::autowel
type_func_t autowel
Definition: ald_qspi.h:214
qspi_handle_t::tx_size
uint16_t tx_size
Definition: ald_qspi.h:260
ald_qspi_indac_read_by_it
ald_status_t ald_qspi_indac_read_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size)
QSPI read data by interrupt.
Definition: ald_qspi.c:563
QSPI_IT_STFNFF
Definition: ald_qspi.h:329
qspi_data_capture_cfg_t::smpledge
qspi_data_sampled_t smpledge
Definition: ald_qspi.h:289
qspi_handle_t
QSPI Handle Structure definition.
Definition: ald_qspi.h:256
QSPI_IF_AHBAEF
Definition: ald_qspi.h:351
qspi_nss_t
qspi_nss_t
QSPI Peripheral chip select decode.
Definition: ald_qspi.h:108
QSPI_IT_SRFFF
Definition: ald_qspi.h:326
lock_state_t
lock_state_t
Definition: type.h:58
qspi_auto_poll_t::indx
uint32_t indx
Definition: ald_qspi.h:313
QSPI_DIV_12
Definition: ald_qspi.h:92
qspi_init_t::chipsel
qspi_nss_t chipsel
Definition: ald_qspi.h:178
QSPI_STATE_BUSY_RX
Definition: ald_qspi.h:39
QSPI_IT_INDRRF
Definition: ald_qspi.h:334
qspi_stig_cmd_t::rd_len
uint32_t rd_len
Definition: ald_qspi.h:159
qspi_auto_poll_t::polexpcnt
uint32_t polexpcnt
Definition: ald_qspi.h:317
qspi_read_cfg_t::instxfer
qspi_xfer_t instxfer
Definition: ald_qspi.h:202
ald_qspi_indac_transmit_by_it
ald_status_t ald_qspi_indac_transmit_by_it(qspi_handle_t *hperh, uint32_t saddr, uint8_t *psrc, uint32_t size)
QSPI write data by interrupt.
Definition: ald_qspi.c:388
ald_dma.h
DMA module Library.
QSPI_DIV_22
Definition: ald_qspi.h:97
qspi_stig_cmd_t::addr_len
uint32_t addr_len
Definition: ald_qspi.h:160
QSPI_XFER_QUAD
Definition: ald_qspi.h:48
qspi_device_size_t
Qspi external flash device configuration.
Definition: ald_qspi.h:128
qspi_dac_cfg_t::xipimmed
type_func_t xipimmed
Definition: ald_qspi.h:244
QSPI_DIV_28
Definition: ald_qspi.h:100
ald_qspi_legacy_config
void ald_qspi_legacy_config(qspi_handle_t *hperh, const qspi_legacy_cfg_t *config)
Configure the QSPI legacy .
Definition: ald_qspi.c:1002
QSPI_DIV_14
Definition: ald_qspi.h:93
QSPI_DIV_2
Definition: ald_qspi.h:87
qspi_stig_cmd_t::rd_buf
void * rd_buf
Definition: ald_qspi.h:167
qspi_xfer_t
qspi_xfer_t
QSPI Instruction Transfer Type.
Definition: ald_qspi.h:45
qspi_stig_cmd_t::op_addr
type_func_t op_addr
Definition: ald_qspi.h:164
QSPI_DIV_6
Definition: ald_qspi.h:89
qspi_handle_t::rx_cnt
uint16_t rx_cnt
Definition: ald_qspi.h:264
qspi_wr_protect_t::lowblk
uint32_t lowblk
Definition: ald_qspi.h:150
qspi_indac_wr_cfg_t
QSPI Indirect Configuration structure.involatile parameters.
Definition: ald_qspi.h:220
QSPI_RISING_E
Definition: ald_qspi.h:143
QSPI_DIV_8
Definition: ald_qspi.h:90
QSPI_XFER_DUAL
Definition: ald_qspi.h:47
qspi_stig_cmd_t::addr
uint32_t addr
Definition: ald_qspi.h:166
qspi_auto_poll_t::validcnt
uint32_t validcnt
Definition: ald_qspi.h:315
QSPI_IT_STFFF
Definition: ald_qspi.h:328
qspi_dac_cfg_t::wrinit
qspi_write_cfg_t wrinit
Definition: ald_qspi.h:250
ald_qspi_clear_it_flag
void ald_qspi_clear_it_flag(qspi_handle_t *hperh, qspi_flag_t flag)
Clear the QSPI interrupt flag.
Definition: ald_qspi.c:832
qspi_stig_cmd_t::wr_buf
void * wr_buf
Definition: ald_qspi.h:168
qspi_legacy_cfg_t
QSPI legacy initialization structure.
Definition: ald_qspi.h:186
QSPI_IF_STFNFF
Definition: ald_qspi.h:348
qspi_dac_cfg_t::dmaperh
type_func_t dmaperh
Definition: ald_qspi.h:248
qspi_indrd_flag_t
qspi_indrd_flag_t
QSPI Indirect Read Progress Status.
Definition: ald_qspi.h:303
QSPI_SRAM_WR
Definition: ald_qspi.h:56
qspi_legacy_cfg_t::tx_thrd
uint8_t tx_thrd
Definition: ald_qspi.h:187
QSPI_IF_WPAF
Definition: ald_qspi.h:352
qspi_dac_config
ald_status_t qspi_dac_config(qspi_handle_t *hperh, qspi_dac_cfg_t *dcfg)
Initializes the QSPI direct access according to the specified parameters in the associated handle...
Definition: ald_qspi.c:295
QSPI_NSS_4G
Definition: ald_qspi.h:122
qspi_dac_cfg_t::dtrprtcol
type_func_t dtrprtcol
Definition: ald_qspi.h:242
qspi_read_cfg_t::rdcde
uint8_t rdcde
Definition: ald_qspi.h:195
QSPI_NSS_2G
Definition: ald_qspi.h:121
qspi_handle_t::tx_cnt
uint16_t tx_cnt
Definition: ald_qspi.h:261
qspi_handle_t::state
qspi_state_t state
Definition: ald_qspi.h:268
qspi_indac_cfg_t::rdwmark
uint32_t rdwmark
Definition: ald_qspi.h:235
ald_qspi_indac_read_by_poll
ald_status_t ald_qspi_indac_read_by_poll(qspi_handle_t *hperh, uint32_t saddr, uint8_t *desbuf, uint16_t size)
Read data from flash by poll.
Definition: ald_qspi.c:496
qspi_stig_cmd_t
QSPI STIG Command Structure.
Definition: ald_qspi.h:157
QSPI_CPHA_1E
Definition: ald_qspi.h:63
QSPI_IT_INDTWF
Definition: ald_qspi.h:331
QSPI_IT_ROVF
Definition: ald_qspi.h:330
qspi_stig_cmd_t::code
uint32_t code
Definition: ald_qspi.h:158
qspi_dac_cfg_t::addrremap
type_func_t addrremap
Definition: ald_qspi.h:246
qspi_data_capture_cfg_t::dlytd
uint32_t dlytd
Definition: ald_qspi.h:286
QSPI_IF_INDTWF
Definition: ald_qspi.h:350
qspi_data_sampled_t
qspi_data_sampled_t
QSPI Sample Edge Selection.
Definition: ald_qspi.h:141
QSPI_IF_INDCF
Definition: ald_qspi.h:354
QSPI_IT_INDCF
Definition: ald_qspi.h:335
qspi_sram_t
qspi_sram_t
QSPI Indirect Access SRAM fill level.
Definition: ald_qspi.h:54
qspi_indac_rd_cfg_t
Definition: ald_qspi.h:225
qspi_dac_cfg_t::xipnextrd
type_func_t xipnextrd
Definition: ald_qspi.h:245
qspi_get_flag_status
flag_status_t qspi_get_flag_status(qspi_handle_t *hperh, qspi_flag_t flag)
Get the status of QSPI interrupt flag.
Definition: ald_qspi.c:814
QSPI_DIV_20
Definition: ald_qspi.h:96
qspi_write_cfg_t::wrcde
uint8_t wrcde
Definition: ald_qspi.h:209
qspi_data_capture_cfg_t::dlydcl
uint32_t dlydcl
Definition: ald_qspi.h:287
ald_qspi_irq_handler
void ald_qspi_irq_handler(qspi_handle_t *hperh)
QSPI interrupt handler.
Definition: ald_qspi.c:908
qspi_init_t::clkdiv
qspi_clk_div_t clkdiv
Definition: ald_qspi.h:175
QSPI_CPHA_2E
Definition: ald_qspi.h:64
QSPI_NSS_1G
Definition: ald_qspi.h:120
ald_qspi_init
void ald_qspi_init(qspi_handle_t *hperh)
Initializes the QSPI basic parameters.
Definition: ald_qspi.c:90
qspi_auto_poll_t
QSPI Auto Poll Configuration Struction.
Definition: ald_qspi.h:311
qspi_dac_cfg_t::rdinit
qspi_read_cfg_t rdinit
Definition: ald_qspi.h:249
flag_status_t
flag_status_t
Definition: type.h:37
qspi_state_t
qspi_state_t
ALD QSPI state.
Definition: ald_qspi.h:37
QSPI_FALLING_E
Definition: ald_qspi.h:142
ald_qspi_interrupt_config
void ald_qspi_interrupt_config(qspi_handle_t *hperh, qspi_it_t it, type_func_t state)
Enable/disable the specified QSPI interrupts.
Definition: ald_qspi.c:982
ald_qspi_write_proect_inverse
void ald_qspi_write_proect_inverse(qspi_handle_t *hperh, type_func_t state)
QSPI Write Protect Inversion.
Definition: ald_qspi.c:885
qspi_stig_cmd_t::d_sycle
uint32_t d_sycle
Definition: ald_qspi.h:162
qspi_auto_poll_t::polarity
uint32_t polarity
Definition: ald_qspi.h:314
qspi_dly_cfg_t::csdads
uint32_t csdads
Definition: ald_qspi.h:278
QSPI_CS_NSS1
Definition: ald_qspi.h:110
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
QSPI_CPOL_L
Definition: ald_qspi.h:71
QSPI_SRAM_RD
Definition: ald_qspi.h:55
qspi_dly_cfg_t
Defines command to be executed using STIG mechanism.
Definition: ald_qspi.h:275
qspi_stig_cmd_t::mode_bit
type_func_t mode_bit
Definition: ald_qspi.h:163
qspi_handle_t::perh
QSPI_TypeDef * perh
Definition: ald_qspi.h:257
qspi_write_cfg_t::instxfer
qspi_xfer_t instxfer
Definition: ald_qspi.h:213
ald_qspi_read_config
ald_status_t ald_qspi_read_config(qspi_handle_t *hperh, const qspi_read_cfg_t *rdcfg)
Configure Read Operations.
Definition: ald_qspi.c:133
qspi_wr_protect_t
Flash write-protected blocks configuration.
Definition: ald_qspi.h:149
QSPI_IT_POLLF
Definition: ald_qspi.h:324
qspi_handle_t::hdma
dma_handle_t hdma
Definition: ald_qspi.h:266
qspi_indac_rd_cfg_t::rdlen
uint32_t rdlen
Definition: ald_qspi.h:227
QSPI_IF_MODFF
Definition: ald_qspi.h:356
qspi_device_size_t::addr
uint8_t addr
Definition: ald_qspi.h:129
qspi_indac_wr_cfg_t::saddr
uint32_t saddr
Definition: ald_qspi.h:221
QSPI_SINGLE_CHIP
Definition: ald_qspi.h:79
qspi_dly_cfg_t::csda
uint32_t csda
Definition: ald_qspi.h:279
ald_qspi_execute_stig_cmd
ald_status_t ald_qspi_execute_stig_cmd(qspi_handle_t *hperh, const qspi_stig_cmd_t *stigcmd)
Execute a STIG command.
Definition: ald_qspi.c:594
ald_qspi_indac_config
ald_status_t ald_qspi_indac_config(qspi_handle_t *hperh, qspi_indac_cfg_t *indcfg)
Initializes the QSPI indirect access according to the specified parameters in the associated handle...
Definition: ald_qspi.c:352
qspi_cpol_t
qspi_cpol_t
QSPI_Clock_Polarity QSPI Clock Polarity.
Definition: ald_qspi.h:70
QSPI_DIV_18
Definition: ald_qspi.h:95
ald_qspi_read_data_capture_config
ald_status_t ald_qspi_read_data_capture_config(qspi_handle_t *hperh, qspi_data_capture_cfg_t *dtcptcfg)
QSPI Read Data Capture Configuration.
Definition: ald_qspi.c:232
qspi_read_cfg_t::ddrbit
type_func_t ddrbit
Definition: ald_qspi.h:198
QSPI_IF_ROVF
Definition: ald_qspi.h:349
QSPI_IT_UDFF
Definition: ald_qspi.h:336
qspi_indwr_status_t
qspi_indwr_status_t
QSPI Indirect Write Progress Status.
Definition: ald_qspi.h:295
qspi_init_t::cpol
qspi_cpol_t cpol
Definition: ald_qspi.h:179
qspi_read_cfg_t::modebit
type_func_t modebit
Definition: ald_qspi.h:199
qspi_cpha_t
qspi_cpha_t
QSPI Clock Phase.
Definition: ald_qspi.h:62


ALD User Manual: D:/svn/src/ald_rmu.c Source File

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  • svn
  • src
ald_rmu.c
Go to the documentation of this file.
1
17 #include "ald_rmu.h"
18 #include "ald_syscfg.h"
19
28 #ifdef ALD_RMU
29
41 void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state)
42 {
43 assert_param(IS_FUNC_STATE(state));
44
45 SYSCFG_UNLOCK();
46
47 if (state) {
48 assert_param(IS_RMU_BORFLT(flt));
49 assert_param(IS_RMU_BORVOL(vol));
50
51 MODIFY_REG(RMU->CR, RMU_CR_BORFLT_MSK, flt << RMU_CR_BORFLT_POSS);
52 MODIFY_REG(RMU->CR, RMU_CR_BORVS_MSK, vol << RMU_CR_BORVS_POSS);
53 SET_BIT(RMU->CR, RMU_CR_BOREN_MSK);
54 }
55 else {
56 CLEAR_BIT(RMU->CR, RMU_CR_BOREN_MSK);
57 }
58
59 SYSCFG_LOCK();
60 return;
61 }
62
68 uint32_t ald_rmu_get_reset_status(rmu_state_t state)
69 {
70 assert_param(IS_RMU_STATE(state));
71
72 if (state == RMU_RST_ALL)
73 return RMU->RSTSR;
74
75 if (READ_BIT(RMU->RSTSR, state))
76 return SET;
77
78 return RESET;
79 }
80
86 void ald_rmu_clear_reset_status(rmu_state_t state)
87 {
88 assert_param(IS_RMU_STATE_CLEAR(state));
89
90 SYSCFG_UNLOCK();
91 WRITE_REG(RMU->CRSTSR, state);
92 SYSCFG_LOCK();
93
94 return;
95 }
101 void ald_rmu_reset_periperal(rmu_peripheral_t perh)
102 {
103 uint32_t idx, pos;
104
105 assert_param(IS_RMU_PERH(perh));
106
107 idx = ((uint32_t)perh >> 27) & 0x7;
108 pos = perh & ~(0x7 << 27);
109 SYSCFG_UNLOCK();
110
111 switch (idx) {
112 case 0:
113 WRITE_REG(RMU->AHB1RSTR, pos);
114 break;
115
116 case 1:
117 WRITE_REG(RMU->AHB2RSTR, pos);
118 break;
119
120 case 2:
121 WRITE_REG(RMU->APB1RSTR, pos);
122 break;
123
124 case 4:
125 WRITE_REG(RMU->APB2RSTR, pos);
126 break;
127
128 default:
129 break;
130 }
131
132 SYSCFG_LOCK();
133 return;
134 }
135
139 #endif /* ALD_RMU */
140
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
ald_rmu_bor_config
void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state)
Configure BOR parameters.
Definition: ald_rmu.c:41
rmu_bor_vol_t
rmu_bor_vol_t
RMU BOR voltage.
Definition: ald_rmu.h:53
type_func_t
type_func_t
Definition: type.h:47
ald_rmu.h
Header file of RMU module driver.
RESET
Definition: type.h:38
rmu_peripheral_t
rmu_peripheral_t
RMU periperal select bit.
Definition: ald_rmu.h:118
IS_RMU_BORFLT
#define IS_RMU_BORFLT(x)
Definition: ald_rmu.h:176
IS_RMU_STATE_CLEAR
#define IS_RMU_STATE_CLEAR(x)
Definition: ald_rmu.h:212
IS_RMU_STATE
#define IS_RMU_STATE(x)
Definition: ald_rmu.h:199
rmu_state_t
rmu_state_t
RMU reset status.
Definition: ald_rmu.h:75
ald_rmu_reset_periperal
void ald_rmu_reset_periperal(rmu_peripheral_t perh)
Reset peripheral device.
Definition: ald_rmu.c:101
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
ald_syscfg.h
SYSCFG module driver.
ald_rmu_clear_reset_status
void ald_rmu_clear_reset_status(rmu_state_t state)
Clear the specified reset status.
Definition: ald_rmu.c:86
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
ald_rmu_get_reset_status
uint32_t ald_rmu_get_reset_status(rmu_state_t state)
Get specified reset status.
Definition: ald_rmu.c:68
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
rmu_bor_filter_t
rmu_bor_filter_t
RMU BOR fliter.
Definition: ald_rmu.h:40
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
IS_RMU_BORVOL
#define IS_RMU_BORVOL(x)
Definition: ald_rmu.h:183
IS_RMU_PERH
#define IS_RMU_PERH(x)
Definition: ald_rmu.h:224
RMU_RST_ALL
Definition: ald_rmu.h:88


ALD User Manual: D:/svn/src/ald_rmu.h Source File

  • D:
  • svn
  • src
ald_rmu.h
Go to the documentation of this file.
1
17 #ifndef __ALD_RMU_H__
18 #define __ALD_RMU_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25
40 typedef enum {
41 RMU_BORFLT_1 = 0x1U,
42 RMU_BORFLT_2 = 0x2U,
43 RMU_BORFLT_3 = 0x3U,
44 RMU_BORFLT_4 = 0x4U,
45 RMU_BORFLT_5 = 0x5U,
46 RMU_BORFLT_6 = 0x6U,
47 RMU_BORFLT_7 = 0x7U,
48 } rmu_bor_filter_t;
49
53 typedef enum {
54 RMU_VOL_NONE = 0x0U,
55 RMU_VOL_2_0 = 0x1U,
56 RMU_VOL_2_2 = 0x2U,
57 RMU_VOL_2_4 = 0x3U,
58 RMU_VOL_2_6 = 0x4U,
59 RMU_VOL_2_8 = 0x5U,
60 RMU_VOL_3_0 = 0x6U,
61 RMU_VOL_3_2 = 0x7U,
62 RMU_VOL_3_4 = 0x8U,
63 RMU_VOL_3_6 = 0x9U,
64 RMU_VOL_3_8 = 0xAU,
65 RMU_VOL_4_0 = 0xBU,
66 RMU_VOL_4_2 = 0xCU,
67 RMU_VOL_4_4 = 0xDU,
68 RMU_VOL_4_6 = 0xEU,
69 RMU_VOL_4_8 = 0xFU,
70 } rmu_bor_vol_t;
71
75 typedef enum {
76 RMU_RST_POR = (1U << 0),
77 RMU_RST_WAKEUP = (1U << 1),
78 RMU_RST_BOR = (1U << 2),
79 RMU_RST_NMRST = (1U << 3),
80 RMU_RST_IWDT = (1U << 4),
81 RMU_RST_WWDT = (1U << 5),
82 RMU_RST_LOCKUP = (1U << 6),
83 RMU_RST_CHIP = (1U << 7),
84 RMU_RST_MCU = (1U << 8),
85 RMU_RST_CPU = (1U << 9),
86 RMU_RST_CFG = (1U << 10),
87 RMU_RST_CFGERR = (1U << 16),
88 RMU_RST_ALL = (0xFFFFFU),
89 } rmu_state_t;
90
118 typedef enum {
119 RMU_PERH_GPIO = (1U << 0),
120 RMU_PERH_CRC = (1U << 1),
121 RMU_PERH_CALC = (1U << 2),
122 RMU_PERH_CRYPT = (1U << 3),
123 RMU_PERH_TRNG = (1U << 4),
124 RMU_PERH_PIS = (1U << 5),
125 RMU_PERH_USB = (1U << 10),
126 RMU_PERH_ECC = (1U << 11),
127 RMU_PERH_CHIP = (1U << 0) | (1U << 27),
128 RMU_PERH_CPU = (1U << 1) | (1U << 27),
129 RMU_PERH_EBI = (1U << 8) | (1U << 27),
130 RMU_PERH_TIMER0 = (1U << 0) | (1U << 28),
131 RMU_PERH_TIMER1 = (1U << 1) | (1U << 28),
132 RMU_PERH_TIMER2 = (1U << 2) | (1U << 28),
133 RMU_PERH_TIMER3 = (1U << 3) | (1U << 28),
134 RMU_PERH_TIMER4 = (1U << 4) | (1U << 28),
135 RMU_PERH_TIMER5 = (1U << 5) | (1U << 28),
136 RMU_PERH_TIMER6 = (1U << 6) | (1U << 28),
137 RMU_PERH_TIMER7 = (1U << 7) | (1U << 28),
138 RMU_PERH_UART0 = (1U << 8) | (1U << 28),
139 RMU_PERH_UART1 = (1U << 9) | (1U << 28),
140 RMU_PERH_UART2 = (1U << 10) | (1U << 28),
141 RMU_PERH_UART3 = (1U << 11) | (1U << 28),
142 RMU_PERH_UART4 = (1U << 12) | (1U << 28),
143 RMU_PERH_UART5 = (1U << 13) | (1U << 28),
144 RMU_PERH_SPI0 = (1U << 16) | (1U << 28),
145 RMU_PERH_SPI1 = (1U << 17) | (1U << 28),
146 RMU_PERH_SPI2 = (1U << 18) | (1U << 28),
147 RMU_PERH_I2C0 = (1U << 20) | (1U << 28),
148 RMU_PERH_I2C1 = (1U << 21) | (1U << 28),
149 RMU_PERH_CAN0 = (1U << 24) | (1U << 28),
150 RMU_PERH_QSPI = (1U << 25) | (1U << 28),
151 RMU_PERH_LPTIM0 = (1U << 0) | (1U << 29),
152 RMU_PERH_LPUART0 = (1U << 2) | (1U << 29),
153 RMU_PERH_ADC0 = (1U << 4) | (1U << 29),
154 RMU_PERH_ADC1 = (1U << 5) | (1U << 29),
155 RMU_PERH_ACMP0 = (1U << 6) | (1U << 29),
156 RMU_PERH_ACMP1 = (1U << 7) | (1U << 29),
157 RMU_PERH_OPAMP = (1U << 8) | (1U << 29),
158 RMU_PERH_DAC0 = (1U << 9) | (1U << 29),
159 RMU_PERH_ACMP2 = (1U << 11) | (1U << 29),
160 RMU_PERH_WWDT = (1U << 12) | (1U << 29),
161 RMU_PERH_LCD = (1U << 13) | (1U << 29),
162 RMU_PERH_IWDT = (1U << 14) | (1U << 29),
163 RMU_PERH_RTC = (1U << 15) | (1U << 29),
164 RMU_PERH_TSENSE = (1U << 16) | (1U << 29),
165 RMU_PERH_BKPC = (1U << 17) | (1U << 29),
166 RMU_PERH_BKPRAM = (1U << 18) | (1U << 29),
167 } rmu_peripheral_t;
176 #define IS_RMU_BORFLT(x) (((x) == RMU_BORFLT_1) || \
177 ((x) == RMU_BORFLT_2) || \
178 ((x) == RMU_BORFLT_3) || \
179 ((x) == RMU_BORFLT_4) || \
180 ((x) == RMU_BORFLT_5) || \
181 ((x) == RMU_BORFLT_6) || \
182 ((x) == RMU_BORFLT_7))
183 #define IS_RMU_BORVOL(x) (((x) == RMU_VOL_NONE) || \
184 ((x) == RMU_VOL_2_0) || \
185 ((x) == RMU_VOL_2_2) || \
186 ((x) == RMU_VOL_2_4) || \
187 ((x) == RMU_VOL_2_6) || \
188 ((x) == RMU_VOL_2_8) || \
189 ((x) == RMU_VOL_3_0) || \
190 ((x) == RMU_VOL_3_2) || \
191 ((x) == RMU_VOL_3_4) || \
192 ((x) == RMU_VOL_3_6) || \
193 ((x) == RMU_VOL_3_8) || \
194 ((x) == RMU_VOL_4_0) || \
195 ((x) == RMU_VOL_4_2) || \
196 ((x) == RMU_VOL_4_4) || \
197 ((x) == RMU_VOL_4_6) || \
198 ((x) == RMU_VOL_4_8))
199 #define IS_RMU_STATE(x) (((x) == RMU_RST_POR) || \
200 ((x) == RMU_RST_WAKEUP) || \
201 ((x) == RMU_RST_BOR) || \
202 ((x) == RMU_RST_NMRST) || \
203 ((x) == RMU_RST_IWDT) || \
204 ((x) == RMU_RST_WWDT) || \
205 ((x) == RMU_RST_LOCKUP) || \
206 ((x) == RMU_RST_CHIP) || \
207 ((x) == RMU_RST_MCU) || \
208 ((x) == RMU_RST_CPU) || \
209 ((x) == RMU_RST_CFG) || \
210 ((x) == RMU_RST_CFGERR) || \
211 ((x) == RMU_RST_ALL))
212 #define IS_RMU_STATE_CLEAR(x) (((x) == RMU_RST_POR) || \
213 ((x) == RMU_RST_WAKEUP) || \
214 ((x) == RMU_RST_BOR) || \
215 ((x) == RMU_RST_NMRST) || \
216 ((x) == RMU_RST_IWDT) || \
217 ((x) == RMU_RST_WWDT) || \
218 ((x) == RMU_RST_LOCKUP) || \
219 ((x) == RMU_RST_CHIP) || \
220 ((x) == RMU_RST_MCU) || \
221 ((x) == RMU_RST_CPU) || \
222 ((x) == RMU_RST_CFG) || \
223 ((x) == RMU_RST_ALL))
224 #define IS_RMU_PERH(x) (((x) == RMU_PERH_GPIO) || \
225 ((x) == RMU_PERH_CRC) || \
226 ((x) == RMU_PERH_CALC) || \
227 ((x) == RMU_PERH_CRYPT) || \
228 ((x) == RMU_PERH_TRNG) || \
229 ((x) == RMU_PERH_PIS) || \
230 ((x) == RMU_PERH_USB) || \
231 ((x) == RMU_PERH_ECC) || \
232 ((x) == RMU_PERH_CHIP) || \
233 ((x) == RMU_PERH_CPU) || \
234 ((x) == RMU_PERH_EBI) || \
235 ((x) == RMU_PERH_TIMER0) || \
236 ((x) == RMU_PERH_TIMER1) || \
237 ((x) == RMU_PERH_TIMER2) || \
238 ((x) == RMU_PERH_TIMER3) || \
239 ((x) == RMU_PERH_TIMER4) || \
240 ((x) == RMU_PERH_TIMER5) || \
241 ((x) == RMU_PERH_TIMER6) || \
242 ((x) == RMU_PERH_TIMER7) || \
243 ((x) == RMU_PERH_UART0) || \
244 ((x) == RMU_PERH_UART1) || \
245 ((x) == RMU_PERH_UART2) || \
246 ((x) == RMU_PERH_UART3) || \
247 ((x) == RMU_PERH_UART4) || \
248 ((x) == RMU_PERH_UART5) || \
249 ((x) == RMU_PERH_SPI0) || \
250 ((x) == RMU_PERH_SPI1) || \
251 ((x) == RMU_PERH_SPI2) || \
252 ((x) == RMU_PERH_I2C0) || \
253 ((x) == RMU_PERH_I2C1) || \
254 ((x) == RMU_PERH_CAN0) || \
255 ((x) == RMU_PERH_QSPI) || \
256 ((x) == RMU_PERH_LPTIM0) || \
257 ((x) == RMU_PERH_LPUART0) || \
258 ((x) == RMU_PERH_ADC0) || \
259 ((x) == RMU_PERH_ADC1) || \
260 ((x) == RMU_PERH_ACMP0) || \
261 ((x) == RMU_PERH_ACMP1) || \
262 ((x) == RMU_PERH_OPAMP) || \
263 ((x) == RMU_PERH_DAC0) || \
264 ((x) == RMU_PERH_ACMP2) || \
265 ((x) == RMU_PERH_WWDT) || \
266 ((x) == RMU_PERH_LCD) || \
267 ((x) == RMU_PERH_IWDT) || \
268 ((x) == RMU_PERH_RTC) || \
269 ((x) == RMU_PERH_TSENSE) || \
270 ((x) == RMU_PERH_BKPC) || \
271 ((x) == RMU_PERH_BKPRAM))
272
279 void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state);
280 uint32_t ald_rmu_get_reset_status(rmu_state_t state);
281 void ald_rmu_clear_reset_status(rmu_state_t state);
282 void ald_rmu_reset_periperal(rmu_peripheral_t perh);
294 #ifdef __cplusplus
295 }
296 #endif
297
298 #endif /* __ALD_RMU_H__ */
RMU_PERH_LPTIM0
Definition: ald_rmu.h:151
RMU_RST_BOR
Definition: ald_rmu.h:78
RMU_PERH_CAN0
Definition: ald_rmu.h:149
RMU_PERH_ECC
Definition: ald_rmu.h:126
RMU_RST_CPU
Definition: ald_rmu.h:85
RMU_RST_NMRST
Definition: ald_rmu.h:79
RMU_PERH_CRYPT
Definition: ald_rmu.h:122
RMU_VOL_4_0
Definition: ald_rmu.h:65
RMU_PERH_I2C1
Definition: ald_rmu.h:148
RMU_PERH_SPI1
Definition: ald_rmu.h:145
RMU_PERH_ACMP2
Definition: ald_rmu.h:159
RMU_PERH_TIMER4
Definition: ald_rmu.h:134
ald_rmu_bor_config
void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state)
Configure BOR parameters.
Definition: ald_rmu.c:41
rmu_bor_vol_t
rmu_bor_vol_t
RMU BOR voltage.
Definition: ald_rmu.h:53
type_func_t
type_func_t
Definition: type.h:47
RMU_BORFLT_1
Definition: ald_rmu.h:41
RMU_PERH_TRNG
Definition: ald_rmu.h:123
RMU_PERH_EBI
Definition: ald_rmu.h:129
RMU_VOL_4_4
Definition: ald_rmu.h:67
RMU_PERH_CPU
Definition: ald_rmu.h:128
RMU_VOL_4_8
Definition: ald_rmu.h:69
RMU_PERH_ADC1
Definition: ald_rmu.h:154
RMU_RST_CFG
Definition: ald_rmu.h:86
RMU_VOL_2_4
Definition: ald_rmu.h:57
RMU_RST_WAKEUP
Definition: ald_rmu.h:77
RMU_BORFLT_6
Definition: ald_rmu.h:46
RMU_PERH_LCD
Definition: ald_rmu.h:161
RMU_PERH_DAC0
Definition: ald_rmu.h:158
utils.h
This file contains the Utilities functions/types for the driver.
RMU_PERH_ACMP1
Definition: ald_rmu.h:156
rmu_peripheral_t
rmu_peripheral_t
RMU periperal select bit.
Definition: ald_rmu.h:118
RMU_PERH_UART3
Definition: ald_rmu.h:141
RMU_PERH_UART2
Definition: ald_rmu.h:140
RMU_PERH_OPAMP
Definition: ald_rmu.h:157
RMU_PERH_BKPRAM
Definition: ald_rmu.h:166
RMU_VOL_NONE
Definition: ald_rmu.h:54
RMU_PERH_UART5
Definition: ald_rmu.h:143
RMU_PERH_GPIO
Definition: ald_rmu.h:119
rmu_state_t
rmu_state_t
RMU reset status.
Definition: ald_rmu.h:75
RMU_PERH_TIMER1
Definition: ald_rmu.h:131
RMU_PERH_CALC
Definition: ald_rmu.h:121
RMU_PERH_SPI2
Definition: ald_rmu.h:146
RMU_PERH_TIMER6
Definition: ald_rmu.h:136
RMU_VOL_2_6
Definition: ald_rmu.h:58
RMU_PERH_IWDT
Definition: ald_rmu.h:162
ald_rmu_reset_periperal
void ald_rmu_reset_periperal(rmu_peripheral_t perh)
Reset peripheral device.
Definition: ald_rmu.c:101
RMU_PERH_UART0
Definition: ald_rmu.h:138
RMU_PERH_ACMP0
Definition: ald_rmu.h:155
RMU_PERH_UART1
Definition: ald_rmu.h:139
RMU_VOL_4_2
Definition: ald_rmu.h:66
ald_rmu_clear_reset_status
void ald_rmu_clear_reset_status(rmu_state_t state)
Clear the specified reset status.
Definition: ald_rmu.c:86
RMU_PERH_TIMER5
Definition: ald_rmu.h:135
RMU_PERH_RTC
Definition: ald_rmu.h:163
RMU_BORFLT_2
Definition: ald_rmu.h:42
RMU_RST_IWDT
Definition: ald_rmu.h:80
RMU_RST_CHIP
Definition: ald_rmu.h:83
RMU_PERH_I2C0
Definition: ald_rmu.h:147
RMU_PERH_TIMER2
Definition: ald_rmu.h:132
RMU_PERH_PIS
Definition: ald_rmu.h:124
RMU_PERH_TIMER7
Definition: ald_rmu.h:137
RMU_BORFLT_7
Definition: ald_rmu.h:47
RMU_PERH_TSENSE
Definition: ald_rmu.h:164
RMU_PERH_BKPC
Definition: ald_rmu.h:165
RMU_PERH_UART4
Definition: ald_rmu.h:142
RMU_VOL_2_8
Definition: ald_rmu.h:59
RMU_PERH_TIMER0
Definition: ald_rmu.h:130
RMU_RST_MCU
Definition: ald_rmu.h:84
RMU_PERH_USB
Definition: ald_rmu.h:125
RMU_BORFLT_5
Definition: ald_rmu.h:45
RMU_PERH_WWDT
Definition: ald_rmu.h:160
RMU_VOL_3_6
Definition: ald_rmu.h:63
RMU_PERH_ADC0
Definition: ald_rmu.h:153
ald_rmu_get_reset_status
uint32_t ald_rmu_get_reset_status(rmu_state_t state)
Get specified reset status.
Definition: ald_rmu.c:68
RMU_RST_POR
Definition: ald_rmu.h:76
RMU_RST_CFGERR
Definition: ald_rmu.h:87
RMU_PERH_CRC
Definition: ald_rmu.h:120
RMU_VOL_3_8
Definition: ald_rmu.h:64
RMU_PERH_TIMER3
Definition: ald_rmu.h:133
RMU_VOL_3_0
Definition: ald_rmu.h:60
RMU_BORFLT_4
Definition: ald_rmu.h:44
rmu_bor_filter_t
rmu_bor_filter_t
RMU BOR fliter.
Definition: ald_rmu.h:40
RMU_VOL_2_2
Definition: ald_rmu.h:56
RMU_VOL_4_6
Definition: ald_rmu.h:68
RMU_PERH_QSPI
Definition: ald_rmu.h:150
RMU_PERH_CHIP
Definition: ald_rmu.h:127
RMU_RST_LOCKUP
Definition: ald_rmu.h:82
RMU_VOL_2_0
Definition: ald_rmu.h:55
RMU_PERH_SPI0
Definition: ald_rmu.h:144
RMU_BORFLT_3
Definition: ald_rmu.h:43
RMU_PERH_LPUART0
Definition: ald_rmu.h:152
RMU_VOL_3_4
Definition: ald_rmu.h:62
RMU_RST_WWDT
Definition: ald_rmu.h:81
RMU_RST_ALL
Definition: ald_rmu.h:88
RMU_VOL_3_2
Definition: ald_rmu.h:61


ALD User Manual: D:/svn/src/ald_rtc.c Source File

  • D:
  • svn
  • src
ald_rtc.c
Go to the documentation of this file.
1
119 #include "ald_rtc.h"
120 #include "ald_bkpc.h"
121 #include "ald_tsense.h"
122 #include "ald_syscfg.h"
123
124
133 #ifdef ALD_RTC
134
143 static uint32_t bcd_to_dec(uint32_t bcd)
144 {
145 return ((bcd & 0xF) + ((bcd >> 4) & 0xF) * 10);
146 }
147
153 static uint32_t dec_to_bcd(uint32_t dec)
154 {
155 return (((dec / 10) << 4) | (dec % 10));
156 }
157
168 static int32_t rtc_consistency_check(rtc_time_t *t_last,
169 rtc_date_t *d_last, rtc_time_t *time, rtc_date_t *date)
170 {
171 if (t_last->second != time->second)
172 return 0;
173 if (t_last->minute != time->minute)
174 return 0;
175 if (t_last->hour != time->hour)
176 return 0;
177 if (d_last->day != date->day)
178 return 0;
179 if (d_last->month != date->month)
180 return 0;
181 if (d_last->year != date->year)
182 return 0;
183
184 return 1;
185 }
220 void ald_rtc_reset(void)
221 {
222 RTC_UNLOCK();
223
224 WRITE_REG(RTC->CON, 0x0);
225 WRITE_REG(RTC->TAMPCON, 0x0);
226 WRITE_REG(RTC->WUMAT, 0x0);
227 WRITE_REG(RTC->IER, 0x0);
228 WRITE_REG(RTC->IFCR, ~0x0);
229
230 RTC_LOCK();
231 return;
232 }
233
240 void ald_rtc_init(rtc_init_t *init)
241 {
242 assert_param(IS_RTC_HOUR_FORMAT(init->hour_format));
243 assert_param(IS_RTC_OUTPUT_SEL(init->output));
244 assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity));
245
246 ald_rtc_reset();
247 RTC_UNLOCK();
248
249 MODIFY_REG(RTC->CON, RTC_CON_HFM_MSK, init->hour_format << RTC_CON_HFM_POS);
250 MODIFY_REG(RTC->CON, RTC_CON_EOS_MSK, init->output << RTC_CON_EOS_POSS);
251 MODIFY_REG(RTC->CON, RTC_CON_POL_MSK, init->output_polarity << RTC_CON_POL_POS);
252 MODIFY_REG(RTC->PSR, RTC_PSR_SPRS_MSK, init->synch_pre_div << RTC_PSR_SPRS_POSS);
253 MODIFY_REG(RTC->PSR, RTC_PSR_APRS_MSK, init->asynch_pre_div << RTC_PSR_APRS_POSS);
254 SET_BIT(RTC->CON, RTC_CON_GO_MSK);
255
256 RTC_LOCK();
257 return;
258 }
259
265 void ald_rtc_source_select(rtc_source_sel_t sel)
266 {
267 assert_param(IS_RTC_SOURCE_SEL(sel));
268
269 BKPC_UNLOCK();
270 MODIFY_REG(BKPC->PCCR, BKPC_PCCR_RTCCS_MSK, sel << BKPC_PCCR_RTCCS_POSS);
271
272 if (sel == RTC_SOURCE_LOSC) {
273 SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);
274 }
275 else if (sel == RTC_SOURCE_LRC) {
276 SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);
277 }
278 else {
279 ; /* do nothing */
280 }
281
282 BKPC_LOCK();
283 return;
284 }
314 ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format)
315 {
316 uint32_t tmp;
317
318 assert_param(IS_RTC_FORMAT(format));
319
320 if (format == RTC_FORMAT_DEC) {
321 assert_param(IS_RTC_SECOND(time->second));
322 assert_param(IS_RTC_MINUTE(time->minute));
323 assert_param(IS_RTC_HOUR(time->hour));
324
325 tmp = (dec_to_bcd(time->second)) |
326 (dec_to_bcd(time->minute) << 8) |
327 (dec_to_bcd(time->hour) << 16);
328 }
329 else {
330 assert_param(IS_RTC_SECOND(bcd_to_dec(time->second)));
331 assert_param(IS_RTC_MINUTE(bcd_to_dec(time->minute)));
332 assert_param(IS_RTC_HOUR(bcd_to_dec(time->hour)));
333
334 tmp = time->second | (time->minute << 8) | (time->hour << 16);
335 }
336
337 RTC_UNLOCK();
338 WRITE_REG(RTC->TIME, tmp);
339 RTC_LOCK();
340
341 tmp = ald_get_tick();
342
343 while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) {
344 if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE)
345 return TIMEOUT;
346 }
347
348 return OK;
349 }
350
357 ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format)
358 {
359 uint32_t tmp;
360
361 assert_param(IS_RTC_FORMAT(format));
362
363 if (format == RTC_FORMAT_DEC) {
364 assert_param(IS_RTC_DAY(date->day));
365 assert_param(IS_RTC_MONTH(date->month));
366 assert_param(IS_RTC_YEAR(date->year));
367
368 tmp = (dec_to_bcd(date->day)) |
369 (dec_to_bcd(date->month) << 8) |
370 (dec_to_bcd(date->year) << 16) |
371 (dec_to_bcd(date->week) << 24);
372 }
373 else {
374 assert_param(IS_RTC_DAY(bcd_to_dec(date->day)));
375 assert_param(IS_RTC_MONTH(bcd_to_dec(date->month)));
376 assert_param(IS_RTC_YEAR(bcd_to_dec(date->year)));
377
378 tmp = date->day | (date->month << 8) |
379 (date->year << 16) | (date->week << 24);
380 }
381
382 RTC_UNLOCK();
383 WRITE_REG(RTC->DATE, tmp);
384 RTC_LOCK();
385
386 tmp = ald_get_tick();
387
388 while (READ_BIT(RTC->CON, RTC_CON_BUSY_MSK)) {
389 if ((ald_get_tick() - tmp) > RTC_TIMEOUT_VALUE)
390 return TIMEOUT;
391 }
392
393 return OK;
394 }
395
402 void ald_rtc_get_time(rtc_time_t *time, rtc_format_t format)
403 {
404 uint32_t tmp;
405
406 assert_param(time != NULL);
407 assert_param(IS_RTC_FORMAT(format));
408
409 time->sub_sec = RTC->SSEC & 0xFFFF;
410 tmp = RTC->TIME;
411
412 if (format == RTC_FORMAT_DEC) {
413 time->second = bcd_to_dec(tmp & 0x7F);
414 time->minute = bcd_to_dec((tmp >> 8) & 0x7F);
415 time->hour = bcd_to_dec((tmp >> 16) & 0x7F);
416 }
417 else {
418 time->second = tmp & 0x7F;
419 time->minute = (tmp >> 8) & 0x7F;
420 time->hour = (tmp >> 16) & 0x7F;
421 }
422
423 return;
424 }
425
432 void ald_rtc_get_date(rtc_date_t *date, rtc_format_t format)
433 {
434 uint32_t tmp = RTC->DATE;
435
436 assert_param(date != NULL);
437 assert_param(IS_RTC_FORMAT(format));
438
439 if (format == RTC_FORMAT_DEC) {
440 date->day = bcd_to_dec(tmp & 0x3F);
441 date->month = bcd_to_dec((tmp >> 8) & 0x1F);
442 date->year = bcd_to_dec((tmp >> 16) & 0xFF);
443 date->week = bcd_to_dec((tmp >> 24) & 0x7);
444 }
445 else {
446 date->day = tmp & 0x3F;
447 date->month = (tmp >> 8) & 0x1F;
448 date->year = (tmp >> 16) & 0xFF;
449 date->week = (tmp >> 24) & 0x7;
450 }
451
452 return;
453 }
454
464 int32_t ald_rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format)
465 {
466 int32_t nr = 3;
467 rtc_date_t d_last;
468 rtc_time_t t_last;
469
470 while (nr--) {
471 ald_rtc_get_time(&t_last, format);
472 ald_rtc_get_date(&d_last, format);
473 ald_rtc_get_time(time, format);
474 ald_rtc_get_date(date, format);
475
476 if (rtc_consistency_check(&t_last, &d_last, time, date))
477 return 0;
478 }
479
480 return -1;
481 }
509 void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format)
510 {
511 unsigned int tmp, ss_tmp;
512
513 assert_param(IS_RTC_ALARM(alarm->idx));
514 assert_param(IS_RTC_ALARM_SEL(alarm->sel));
515 assert_param(IS_RTC_ALARM_SS_MASK(alarm->ss_mask));
516 assert_param(IS_RTC_FORMAT(format));
517
518 if (format == RTC_FORMAT_DEC) {
519 assert_param(IS_RTC_SECOND(alarm->time.second));
520 assert_param(IS_RTC_MINUTE(alarm->time.minute));
521 assert_param(IS_RTC_HOUR(alarm->time.hour));
522
523 tmp = (dec_to_bcd(alarm->time.second)) |
524 (dec_to_bcd(alarm->time.minute) << 8) |
525 (dec_to_bcd(alarm->time.hour) << 16) |
526 alarm->mask;
527
528 if (alarm->sel == RTC_SELECT_DAY) {
529 assert_param(IS_RTC_DAY(alarm->day));
530
531 tmp |= (dec_to_bcd(alarm->day) << 24);
532 tmp &= 0x7FFFFFFF; /* Reset bit31 */
533 }
534 else {
535 tmp |= (1 << (alarm->week + 24));
536 tmp |= 0x80000000; /* Set bit31 */
537 }
538 }
539 else {
540 assert_param(IS_RTC_SECOND(bcd_to_dec(alarm->time.second)));
541 assert_param(IS_RTC_MINUTE(bcd_to_dec(alarm->time.minute)));
542 assert_param(IS_RTC_HOUR(bcd_to_dec(alarm->time.hour)));
543
544 tmp = alarm->time.second |
545 (alarm->time.minute << 8) |
546 (alarm->time.hour << 16) |
547 alarm->mask;
548
549 if (alarm->sel == RTC_SELECT_DAY) {
550 assert_param(IS_RTC_DAY(bcd_to_dec(alarm->day)));
551
552 tmp |= (alarm->day << 24);
553 tmp &= 0x7FFFFFFF; /* Reset bit31 */
554 }
555 else {
556 tmp |= (1 << (alarm->week + 24));
557 tmp |= 0x80000000; /* Set bit31 */
558 }
559 }
560
561 ss_tmp = (alarm->time.sub_sec & 0x7F) |
562 (alarm->ss_mask << 24);
563
564 RTC_UNLOCK();
565
566 if (alarm->idx == RTC_ALARM_A) {
567 WRITE_REG(RTC->ALMA, tmp);
568 WRITE_REG(RTC->ALMASSEC, ss_tmp);
569 SET_BIT(RTC->CON, RTC_CON_ALMAEN_MSK);
570 }
571 else {
572 WRITE_REG(RTC->ALMB, tmp);
573 WRITE_REG(RTC->ALMBSSEC, ss_tmp);
574 SET_BIT(RTC->CON, RTC_CON_ALMBEN_MSK);
575 }
576
577 RTC_LOCK();
578 return;
579 }
580
587 void ald_rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format)
588 {
589 uint8_t week;
590 uint32_t tmp, ss_tmp;
591
592 assert_param(alarm != NULL);
593 assert_param(IS_RTC_FORMAT(format));
594
595 if (alarm->idx == RTC_ALARM_A) {
596 tmp = RTC->ALMA;
597 ss_tmp = RTC->ALMASSEC;
598 }
599 else {
600 tmp = RTC->ALMB;
601 ss_tmp = RTC->ALMBSSEC;
602 }
603
604 if ((tmp >> 31) & 0x1) {
605 alarm->sel = RTC_SELECT_WEEK;
606 week = ((tmp >> 24) & 0x7F);
607
608 switch (week) {
609 case 1:
610 alarm->week = 0;
611 break;
612 case 2:
613 alarm->week = 1;
614 break;
615 case 4:
616 alarm->week = 2;
617 break;
618 case 8:
619 alarm->week = 3;
620 break;
621 case 16:
622 alarm->week = 4;
623 break;
624 case 32:
625 alarm->week = 5;
626 break;
627 case 64:
628 alarm->week = 6;
629 break;
630 default:
631 break;
632 }
633 }
634 else {
635 alarm->sel = RTC_SELECT_DAY;
636
637 if (format == RTC_FORMAT_DEC)
638 alarm->day = bcd_to_dec((tmp >> 24) & 0x3F);
639 else
640 alarm->day = (tmp >> 24) & 0x3F;
641 }
642
643 if (format == RTC_FORMAT_DEC) {
644 alarm->time.second = bcd_to_dec(tmp & 0x7F);
645 alarm->time.minute = bcd_to_dec((tmp >> 8) & 0x7F);
646 alarm->time.hour = bcd_to_dec((tmp >> 16) & 0x3F);
647 }
648 else {
649 alarm->time.second = tmp & 0x7F;
650 alarm->time.minute = (tmp >> 8) & 0x7F;
651 alarm->time.hour = (tmp >> 16) & 0x3F;
652 }
653
654 alarm->time.sub_sec = ss_tmp & 0x7FFF;
655 alarm->ss_mask = (rtc_sub_second_mask_t)((ss_tmp >> 24) & 0xF);
656 alarm->mask = tmp & ALARM_MASK_ALL;
657
658 return;
659 }
692 void ald_rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style)
693 {
694 assert_param(IS_RTC_TS_SIGNAL(sel));
695 assert_param(IS_RTC_TS_STYLE(style));
696
697 RTC_UNLOCK();
698
699 CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK);
700 MODIFY_REG(RTC->CON, RTC_CON_TSSEL_MSK, style << RTC_CON_TSSEL_POS);
701 MODIFY_REG(RTC->CON, RTC_CON_TSPIN_MSK, sel << RTC_CON_TSPIN_POS);
702 SET_BIT(RTC->CON, RTC_CON_TSEN_MSK);
703
704 RTC_LOCK();
705 return;
706 }
707
712 void ald_rtc_cancel_time_stamp(void)
713 {
714 RTC_UNLOCK();
715 CLEAR_BIT(RTC->CON, RTC_CON_TSEN_MSK);
716 RTC_LOCK();
717
718 return;
719 }
720
728 void ald_rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format)
729 {
730 uint32_t tmp0, tmp1;
731
732 assert_param(ts_time != NULL);
733 assert_param(ts_date != NULL);
734 assert_param(IS_RTC_FORMAT(format));
735
736 ts_time->sub_sec = RTC->TSSSEC & 0xFFFF;
737 tmp0 = RTC->TSTIME;
738 tmp1 = RTC->TSDATE;
739
740 if (format == RTC_FORMAT_DEC) {
741 ts_time->second = bcd_to_dec(tmp0 & 0x7F);
742 ts_time->minute = bcd_to_dec((tmp0 >> 8) & 0x7F);
743 ts_time->hour = bcd_to_dec((tmp0 >> 16) & 0x3F);
744 ts_date->day = bcd_to_dec(tmp1 & 0x3F);
745 ts_date->month = bcd_to_dec((tmp1 >> 8) & 0x1F);
746 ts_date->year = bcd_to_dec((tmp1 >> 16) & 0xFF);
747 ts_date->week = bcd_to_dec((tmp1 >> 24) & 0x7);
748 }
749 else {
750 ts_time->second = tmp0 & 0x7F;
751 ts_time->minute = (tmp0 >> 8) & 0x7F;
752 ts_time->hour = (tmp0 >> 16) & 0x3F;
753 ts_date->day = tmp1 & 0x3F;
754 ts_date->month = (tmp1 >> 8) & 0x1F;
755 ts_date->year = (tmp1 >> 16) & 0xFF;
756 ts_date->week = (tmp1 >> 24) & 0x7;
757 }
758
759 return;
760 }
786 void ald_rtc_set_tamper(rtc_tamper_t *tamper)
787 {
788 assert_param(IS_RTC_TAMPER(tamper->idx));
789 assert_param(IS_RTC_TAMPER_TRIGGER(tamper->trig));
790 assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(tamper->freq));
791 assert_param(IS_RTC_TAMPER_DURATION(tamper->dur));
792 assert_param(IS_FUNC_STATE(tamper->ts));
793
794 RTC_UNLOCK();
795 MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPTS_MSK, tamper->ts << RTC_TAMPCON_TAMPTS_POS);
796 MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPCKS_MSK, tamper->freq << RTC_TAMPCON_TAMPCKS_POSS);
797 MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMPFLT_MSK, tamper->dur << RTC_TAMPCON_TAMPFLT_POSS);
798
799 if (tamper->idx == RTC_TAMPER_0) {
800 MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP1LV_MSK, tamper->trig << RTC_TAMPCON_TAMP1LV_POS);
801 SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK);
802 }
803 else {
804 MODIFY_REG(RTC->TAMPCON, RTC_TAMPCON_TAMP2LV_MSK, tamper->trig << RTC_TAMPCON_TAMP2LV_POS);
805 SET_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP2EN_MSK);
806 }
807
808 RTC_LOCK();
809 return;
810 }
811
819 void ald_rtc_cancel_tamper(rtc_tamper_idx_t idx)
820 {
821 assert_param(IS_RTC_TAMPER(idx));
822
823 RTC_UNLOCK();
824
825 if (idx == RTC_TAMPER_0)
826 CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP1EN_MSK);
827 else
828 CLEAR_BIT(RTC->TAMPCON, RTC_TAMPCON_TAMP2EN_MSK);
829
830 RTC_LOCK();
831 return;
832 }
860 void ald_rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value)
861 {
862 assert_param(IS_RTC_WAKEUP_CLOCK(clock));
863
864 RTC_UNLOCK();
865 MODIFY_REG(RTC->CON, RTC_CON_WUCKS_MSK, clock << RTC_CON_WUCKS_POSS);
866 WRITE_REG(RTC->WUMAT, value & 0xFFFF);
867 SET_BIT(RTC->CON, RTC_CON_WUTE_MSK);
868 RTC_LOCK();
869
870 return;
871 }
872
877 void ald_rtc_cancel_wakeup(void)
878 {
879 RTC_UNLOCK();
880 CLEAR_BIT(RTC->CON, RTC_CON_WUTE_MSK);
881 RTC_LOCK();
882
883 return;
884 }
885
890 uint16_t ald_rtc_get_wakeup_timer_value(void)
891 {
892 return RTC->WUMAT & 0xFFFF;
893 }
919 ald_status_t ald_rtc_set_clock_output(rtc_clock_output_t clock)
920 {
921 uint32_t cnt = 4000;
922 assert_param(IS_RTC_CLOCK_OUTPUT(clock));
923
924 SYSCFG_UNLOCK();
925
926 if (clock == RTC_CLOCK_OUTPUT_EXA_1) {
927 SET_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK);
928 while ((READ_BIT(CMU->PLLCFG, CMU_PLLCFG_PLL2LCKN_MSK)) && (--cnt));
929 cnt = 4000;
930 while ((!(READ_BIT(CMU->CLKSR, CMU_CLKSR_PLL2RDY_MSK))) && (--cnt));
931 }
932 else {
933 CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLL2EN_MSK);
934 }
935
936 SYSCFG_LOCK();
937 RTC_UNLOCK();
938 MODIFY_REG(RTC->CON, RTC_CON_CKOS_MSK, clock << RTC_CON_CKOS_POSS);
939 SET_BIT(RTC->CON, RTC_CON_CKOE_MSK);
940 RTC_LOCK();
941
942 return OK;
943 }
944
949 void ald_rtc_cancel_clock_output(void)
950 {
951 RTC_UNLOCK();
952 CLEAR_BIT(RTC->CON, RTC_CON_CKOE_MSK);
953 RTC_LOCK();
954
955 return;
956 }
992 void ald_rtc_interrupt_config(rtc_it_t it, type_func_t state)
993 {
994 assert_param(IS_RTC_IT(it));
995 assert_param(IS_FUNC_STATE(state));
996
997 RTC_UNLOCK();
998
999 if (state == ENABLE)
1000 SET_BIT(RTC->IER, it);
1001 else
1002 CLEAR_BIT(RTC->IER, it);
1003
1004 RTC_LOCK();
1005 return;
1006 }
1007
1018 void ald_rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state)
1019 {
1020 assert_param(IS_RTC_ALARM(idx));
1021 assert_param(IS_FUNC_STATE(state));
1022
1023 RTC_UNLOCK();
1024
1025 if (idx == RTC_ALARM_A)
1026 MODIFY_REG(RTC->CON, RTC_CON_ALMAEN_MSK, state << RTC_CON_ALMAEN_POS);
1027 else
1028 MODIFY_REG(RTC->CON, RTC_CON_ALMBEN_MSK, state << RTC_CON_ALMBEN_POS);
1029
1030 RTC_LOCK();
1031 return;
1032 }
1033
1040 ald_status_t ald_rtc_set_shift(type_func_t add_1s, uint16_t sub_ss)
1041 {
1042 uint32_t tick;
1043
1044 assert_param(IS_FUNC_STATE(add_1s));
1045 assert_param(IS_SHIFT_SUB_SS(sub_ss));
1046
1047 RTC_UNLOCK();
1048 MODIFY_REG(RTC->SSECTR, RTC_SSECTR_TRIM_MSK, sub_ss << RTC_SSECTR_TRIM_POSS);
1049 MODIFY_REG(RTC->SSECTR, RTC_SSECTR_INC_MSK, add_1s << RTC_SSECTR_INC_POS);
1050 RTC_LOCK();
1051
1052 tick = ald_get_tick();
1053
1054 while (READ_BIT(RTC->CON, RTC_CON_SSEC_MSK)) {
1055 if ((ald_get_tick() - tick) > RTC_TIMEOUT_VALUE)
1056 return TIMEOUT;
1057 }
1058
1059 return OK;
1060 }
1061
1067 void ald_rtc_set_cali(rtc_cali_t *config)
1068 {
1069 assert_param(IS_RTC_CALI_FREQ(config->cali_freq));
1070 assert_param(IS_RTC_CALI_TC(config->tc));
1071 assert_param(IS_RTC_CALC_FREQ(config->calc_freq));
1072 assert_param(IS_RTC_CALI_CALC(config->calc));
1073 assert_param(IS_FUNC_STATE(config->acc));
1074
1075 RTC_UNLOCK();
1076 RTC_CALI_UNLOCK();
1077
1078 MODIFY_REG(RTC->CALCON, RTC_CALCON_CALP_MSK, config->cali_freq << RTC_CALCON_CALP_POSS);
1079 MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, config->tc << RTC_CALCON_TCM_POSS);
1080 MODIFY_REG(RTC->CALCON, RTC_CALCON_TCP_MSK, config->calc_freq << RTC_CALCON_TCP_POSS);
1081 MODIFY_REG(RTC->CALCON, RTC_CALCON_ALG_MSK, config->calc << RTC_CALCON_ALG_POS);
1082 MODIFY_REG(RTC->CALCON, RTC_CALCON_DCMACC_MSK, config->acc << RTC_CALCON_DCMACC_POS);
1083 SET_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK);
1084
1085 RTC_CALI_LOCK();
1086 RTC_LOCK();
1087
1088 return;
1089 }
1090
1095 void ald_rtc_cancel_cali(void)
1096 {
1097 RTC_CALI_UNLOCK();
1098 CLEAR_BIT(RTC->CALCON, RTC_CALCON_CALEN_MSK);
1099 RTC_CALI_LOCK();
1100
1101 return;
1102 }
1103
1108 ald_status_t ald_rtc_get_cali_status(void)
1109 {
1110 if (READ_BIT(RTC->CALCON, RTC_CALCON_ERR_MSK))
1111 return ERROR;
1112 else
1113 return OK;
1114 }
1115
1121 void ald_rtc_write_temp(uint16_t temp)
1122 {
1123 RTC_CALI_UNLOCK();
1124 MODIFY_REG(RTC->TEMPR, RTC_TEMPR_VAL_MSK, temp << RTC_TEMPR_VAL_POSS);
1125 RTC_CALI_LOCK();
1126
1127 return;
1128 }
1129
1138 it_status_t ald_rtc_get_it_status(rtc_it_t it)
1139 {
1140 assert_param(IS_RTC_IT(it));
1141
1142 if (READ_BIT(RTC->IER, it))
1143 return SET;
1144
1145 return RESET;
1146 }
1147
1156 flag_status_t ald_rtc_get_flag_status(rtc_flag_t flag)
1157 {
1158 assert_param(IS_RTC_IF(flag));
1159
1160 if (READ_BIT(RTC->IFR, flag))
1161 return SET;
1162
1163 return RESET;
1164 }
1165
1170 void ald_rtc_clear_flag_status(rtc_flag_t flag)
1171 {
1172 assert_param(IS_RTC_IF(flag));
1173
1174 RTC_UNLOCK();
1175 WRITE_REG(RTC->IFCR, flag);
1176 RTC_LOCK();
1177
1178 return;
1179 }
1186 #endif /* ALD_RTC */
1187
rtc_consistency_check
static int32_t rtc_consistency_check(rtc_time_t *t_last, rtc_date_t *d_last, rtc_time_t *time, rtc_date_t *date)
Time and Date consistency check.
Definition: ald_rtc.c:168
IS_RTC_TAMPER
#define IS_RTC_TAMPER(x)
Definition: ald_rtc.h:473
rtc_format_t
rtc_format_t
Data format.
Definition: ald_rtc.h:108
IS_RTC_OUTPUT_POLARITY
#define IS_RTC_OUTPUT_POLARITY(x)
Definition: ald_rtc.h:435
ald_rtc_cancel_wakeup
void ald_rtc_cancel_wakeup(void)
Cancel wake-up.
Definition: ald_rtc.c:877
ald_rtc_set_shift
ald_status_t ald_rtc_set_shift(type_func_t add_1s, uint16_t sub_ss)
Set shift parameters.
Definition: ald_rtc.c:1040
IS_RTC_CALC_FREQ
#define IS_RTC_CALC_FREQ(x)
Definition: ald_rtc.h:513
rtc_date_t::day
uint8_t day
Definition: ald_rtc.h:100
IS_RTC_WAKEUP_CLOCK
#define IS_RTC_WAKEUP_CLOCK(x)
Definition: ald_rtc.h:489
ald_rtc_set_wakeup
void ald_rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value)
Set wake-up parameters.
Definition: ald_rtc.c:860
ALARM_MASK_ALL
#define ALARM_MASK_ALL
Definition: ald_rtc.h:425
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
rtc_tamper_t::ts
type_func_t ts
Definition: ald_rtc.h:242
IS_RTC_TS_SIGNAL
#define IS_RTC_TS_SIGNAL(x)
Definition: ald_rtc.h:467
rtc_cali_t::cali_freq
rtc_cali_freq_t cali_freq
Definition: ald_rtc.h:319
rtc_alarm_t::time
rtc_time_t time
Definition: ald_rtc.h:167
rtc_source_sel_t
rtc_source_sel_t
Source select.
Definition: ald_rtc.h:78
RTC_SELECT_WEEK
Definition: ald_rtc.h:159
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
IS_RTC_HOUR_FORMAT
#define IS_RTC_HOUR_FORMAT(x)
Definition: ald_rtc.h:429
assert_param
#define assert_param(x)
Definition: type.h:88
IS_RTC_CALI_CALC
#define IS_RTC_CALI_CALC(x)
Definition: ald_rtc.h:521
SET
Definition: type.h:39
ald_rtc_cancel_tamper
void ald_rtc_cancel_tamper(rtc_tamper_idx_t idx)
Cancel tamper.
Definition: ald_rtc.c:819
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
ald_rtc_interrupt_config
void ald_rtc_interrupt_config(rtc_it_t it, type_func_t state)
Enable/disable the specified RTC interrupts.
Definition: ald_rtc.c:992
type_func_t
type_func_t
Definition: type.h:47
rtc_cali_t
Calibration structure.
Definition: ald_rtc.h:318
ald_rtc_set_time_stamp
void ald_rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style)
Set time stamp.
Definition: ald_rtc.c:692
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
IS_RTC_MONTH
#define IS_RTC_MONTH(x)
Definition: ald_rtc.h:561
rtc_init_t::hour_format
rtc_hour_format_t hour_format
Definition: ald_rtc.h:68
rtc_tamper_t
Tamper structure.
Definition: ald_rtc.h:237
IS_RTC_CALI_TC
#define IS_RTC_CALI_TC(x)
Definition: ald_rtc.h:509
rtc_alarm_t::week
uint8_t week
Definition: ald_rtc.h:173
RTC_TAMPER_0
Definition: ald_rtc.h:198
IS_RTC_TS_STYLE
#define IS_RTC_TS_STYLE(x)
Definition: ald_rtc.h:469
ald_rtc_get_flag_status
flag_status_t ald_rtc_get_flag_status(rtc_flag_t flag)
Get the status of RTC interrupt flag.
Definition: ald_rtc.c:1156
rtc_date_t::month
uint8_t month
Definition: ald_rtc.h:101
ald_rtc.h
Header file of RTC Module driver.
RESET
Definition: type.h:38
rtc_cali_t::calc
rtc_cali_calc_t calc
Definition: ald_rtc.h:322
rtc_date_t::week
uint8_t week
Definition: ald_rtc.h:99
IS_RTC_DAY
#define IS_RTC_DAY(x)
Definition: ald_rtc.h:560
ald_rtc_set_clock_output
ald_status_t ald_rtc_set_clock_output(rtc_clock_output_t clock)
Set clock output parameters.
Definition: ald_rtc.c:919
ald_rtc_set_date
ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format)
Set specified date.
Definition: ald_rtc.c:357
ald_rtc_reset
void ald_rtc_reset(void)
Reset RTC register.
Definition: ald_rtc.c:220
ald_bkpc.h
Header file of BKPC module driver.
ald_rtc_get_cali_status
ald_status_t ald_rtc_get_cali_status(void)
Get calibration status.
Definition: ald_rtc.c:1108
RTC_FORMAT_DEC
Definition: ald_rtc.h:109
rtc_cali_t::tc
rtc_cali_tc_t tc
Definition: ald_rtc.h:320
rtc_init_t::output_polarity
rtc_output_polarity_t output_polarity
Definition: ald_rtc.h:72
IS_RTC_ALARM_SEL
#define IS_RTC_ALARM_SEL(x)
Definition: ald_rtc.h:443
RTC_CLOCK_OUTPUT_EXA_1
Definition: ald_rtc.h:266
it_status_t
enum flag_status_t it_status_t
ald_rtc_get_time
void ald_rtc_get_time(rtc_time_t *time, rtc_format_t format)
Get current time.
Definition: ald_rtc.c:402
IS_RTC_IF
#define IS_RTC_IF(x)
Definition: ald_rtc.h:540
ald_tsense.h
Header file of TSENSE module driver.
rtc_init_t::synch_pre_div
uint32_t synch_pre_div
Definition: ald_rtc.h:70
ald_rtc_write_temp
void ald_rtc_write_temp(uint16_t temp)
Write temperature value.
Definition: ald_rtc.c:1121
IS_RTC_CALI_FREQ
#define IS_RTC_CALI_FREQ(x)
Definition: ald_rtc.h:501
ald_rtc_cancel_time_stamp
void ald_rtc_cancel_time_stamp(void)
Cancel time stamp.
Definition: ald_rtc.c:712
RTC_SELECT_DAY
Definition: ald_rtc.h:158
IS_RTC_ALARM
#define IS_RTC_ALARM(x)
Definition: ald_rtc.h:441
ald_rtc_set_tamper
void ald_rtc_set_tamper(rtc_tamper_t *tamper)
Set tamper parameters.
Definition: ald_rtc.c:786
ald_rtc_init
void ald_rtc_init(rtc_init_t *init)
Initialize the RTC module.
Definition: ald_rtc.c:240
rtc_cali_t::calc_freq
rtc_cali_calc_freq_t calc_freq
Definition: ald_rtc.h:321
IS_RTC_TAMPER_TRIGGER
#define IS_RTC_TAMPER_TRIGGER(x)
Definition: ald_rtc.h:475
rtc_sub_second_mask_t
rtc_sub_second_mask_t
Alarm sub-second mask.
Definition: ald_rtc.h:136
rtc_ts_signal_sel_t
rtc_ts_signal_sel_t
Time stamp signel select.
Definition: ald_rtc.h:181
ald_rtc_cancel_clock_output
void ald_rtc_cancel_clock_output(void)
Cancel clock output.
Definition: ald_rtc.c:949
rtc_init_t::asynch_pre_div
uint32_t asynch_pre_div
Definition: ald_rtc.h:69
ald_rtc_set_time
ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format)
Set specified time.
Definition: ald_rtc.c:314
IS_RTC_HOUR
#define IS_RTC_HOUR(x)
Definition: ald_rtc.h:559
rtc_init_t::output
rtc_output_select_t output
Definition: ald_rtc.h:71
ald_rtc_alarm_cmd
void ald_rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state)
Enable/Disable alarm.
Definition: ald_rtc.c:1018
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
IS_RTC_FORMAT
#define IS_RTC_FORMAT(x)
Definition: ald_rtc.h:471
RTC_SOURCE_LRC
Definition: ald_rtc.h:80
rtc_time_t::minute
uint8_t minute
Definition: ald_rtc.h:90
ald_syscfg.h
SYSCFG module driver.
IS_RTC_SOURCE_SEL
#define IS_RTC_SOURCE_SEL(x)
Definition: ald_rtc.h:437
BKPC_LOCK
#define BKPC_LOCK()
Definition: ald_bkpc.h:38
rtc_ts_trigger_style_t
rtc_ts_trigger_style_t
Time stamp trigger style.
Definition: ald_rtc.h:189
IS_SHIFT_SUB_SS
#define IS_SHIFT_SUB_SS(x)
Definition: ald_rtc.h:428
rtc_alarm_t::day
uint8_t day
Definition: ald_rtc.h:174
dec_to_bcd
static uint32_t dec_to_bcd(uint32_t dec)
Converts a 2 digit decimal to BCD format.
Definition: ald_rtc.c:153
rtc_alarm_t
Alarm structure.
Definition: ald_rtc.h:165
rtc_it_t
rtc_it_t
Interrupt type.
Definition: ald_rtc.h:329
ald_rtc_get_alarm
void ald_rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format)
Get alarm parameters.
Definition: ald_rtc.c:587
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
rtc_time_t::hour
uint8_t hour
Definition: ald_rtc.h:89
TIMEOUT
Definition: utils.h:58
IS_RTC_SECOND
#define IS_RTC_SECOND(x)
Definition: ald_rtc.h:557
rtc_tamper_t::dur
rtc_tamper_duration_t dur
Definition: ald_rtc.h:241
rtc_time_t::second
uint8_t second
Definition: ald_rtc.h:91
rtc_tamper_idx_t
rtc_tamper_idx_t
Index of tamper.
Definition: ald_rtc.h:197
rtc_alarm_t::mask
uint32_t mask
Definition: ald_rtc.h:168
rtc_tamper_t::freq
rtc_tamper_sampling_freq_t freq
Definition: ald_rtc.h:240
RTC_CALI_LOCK
#define RTC_CALI_LOCK()
Definition: ald_rtc.h:424
RTC_CALI_UNLOCK
#define RTC_CALI_UNLOCK()
Definition: ald_rtc.h:423
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378
rtc_flag_t
rtc_flag_t
Interrupt flag.
Definition: ald_rtc.h:352
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_RTC_YEAR
#define IS_RTC_YEAR(x)
Definition: ald_rtc.h:562
RTC_SOURCE_LOSC
Definition: ald_rtc.h:79
rtc_alarm_t::idx
rtc_alarm_idx_t idx
Definition: ald_rtc.h:166
bcd_to_dec
static uint32_t bcd_to_dec(uint32_t bcd)
Converts form 2 digit BCD to Binary.
Definition: ald_rtc.c:143
ald_rtc_get_date
void ald_rtc_get_date(rtc_date_t *date, rtc_format_t format)
Get current date.
Definition: ald_rtc.c:432
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
rtc_clock_output_t
rtc_clock_output_t
RTC clock output type.
Definition: ald_rtc.h:260
ald_rtc_set_cali
void ald_rtc_set_cali(rtc_cali_t *config)
Set calibation.
Definition: ald_rtc.c:1067
rtc_time_t
Time structure.
Definition: ald_rtc.h:88
rtc_alarm_idx_t
rtc_alarm_idx_t
Index of alarm.
Definition: ald_rtc.h:116
IS_RTC_TAMPER_DURATION
#define IS_RTC_TAMPER_DURATION(x)
Definition: ald_rtc.h:485
IS_RTC_CLOCK_OUTPUT
#define IS_RTC_CLOCK_OUTPUT(x)
Definition: ald_rtc.h:495
ald_rtc_cancel_cali
void ald_rtc_cancel_cali(void)
Cancel calibration.
Definition: ald_rtc.c:1095
ald_rtc_set_alarm
void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format)
Set alarm.
Definition: ald_rtc.c:509
BKPC_UNLOCK
#define BKPC_UNLOCK()
Definition: ald_bkpc.h:39
ald_rtc_get_time_stamp
void ald_rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format)
Get time stamp value.
Definition: ald_rtc.c:728
flag_status_t
flag_status_t
Definition: type.h:37
IS_RTC_IT
#define IS_RTC_IT(x)
Definition: ald_rtc.h:523
rtc_alarm_t::ss_mask
rtc_sub_second_mask_t ss_mask
Definition: ald_rtc.h:169
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
rtc_date_t
Date structure.
Definition: ald_rtc.h:98
rtc_init_t
Initialization structure.
Definition: ald_rtc.h:67
rtc_tamper_t::idx
rtc_tamper_idx_t idx
Definition: ald_rtc.h:238
ald_rtc_source_select
void ald_rtc_source_select(rtc_source_sel_t sel)
Configure the RTC source.
Definition: ald_rtc.c:265
rtc_time_t::sub_sec
uint16_t sub_sec
Definition: ald_rtc.h:92
rtc_wakeup_clock_t
rtc_wakeup_clock_t
Wake-up clock.
Definition: ald_rtc.h:248
ald_rtc_clear_flag_status
void ald_rtc_clear_flag_status(rtc_flag_t flag)
Clear the specified RTC pending flag.
Definition: ald_rtc.c:1170
ald_rtc_get_it_status
it_status_t ald_rtc_get_it_status(rtc_it_t it)
Get the status of RTC interrupt source.
Definition: ald_rtc.c:1138
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
SYSCFG_LOCK
#define SYSCFG_LOCK()
Definition: ald_syscfg.h:39
rtc_date_t::year
uint8_t year
Definition: ald_rtc.h:102
ald_rtc_get_wakeup_timer_value
uint16_t ald_rtc_get_wakeup_timer_value(void)
Get wake-up re-load register value.
Definition: ald_rtc.c:890
RTC_TIMEOUT_VALUE
#define RTC_TIMEOUT_VALUE
Definition: ald_rtc.h:426
IS_RTC_MINUTE
#define IS_RTC_MINUTE(x)
Definition: ald_rtc.h:558
rtc_tamper_t::trig
rtc_tamper_trigger_t trig
Definition: ald_rtc.h:239
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
IS_RTC_ALARM_SS_MASK
#define IS_RTC_ALARM_SS_MASK(x)
Definition: ald_rtc.h:451
ERROR
Definition: utils.h:56
rtc_alarm_t::sel
rtc_week_day_sel_t sel
Definition: ald_rtc.h:170
ald_rtc_get_date_time
int32_t ald_rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format)
Get time and date consistency.
Definition: ald_rtc.c:464
IS_RTC_TAMPER_SAMPLING_FREQ
#define IS_RTC_TAMPER_SAMPLING_FREQ(x)
Definition: ald_rtc.h:477
rtc_cali_t::acc
type_func_t acc
Definition: ald_rtc.h:323
RTC_ALARM_A
Definition: ald_rtc.h:117
IS_RTC_OUTPUT_SEL
#define IS_RTC_OUTPUT_SEL(x)
Definition: ald_rtc.h:431


ALD User Manual: D:/svn/src/ald_rtc.h Source File

  • D:
  • svn
  • src
ald_rtc.h
Go to the documentation of this file.
1
16 #ifndef __ALD_RTC_H__
17 #define __ALD_RTC_H__
18
19 #ifdef __cplusplus
20 extern "C" {
21 #endif
22
23 #include "utils.h"
24
25
41 typedef enum {
42 RTC_HOUR_FORMAT_24 = 0x0U,
43 RTC_HOUR_FORMAT_12 = 0x1U,
44 } rtc_hour_format_t;
45
49 typedef enum {
50 RTC_OUTPUT_DISABLE = 0x0U,
51 RTC_OUTPUT_ALARM_A = 0x1U,
52 RTC_OUTPUT_ALARM_B = 0x2U,
53 RTC_OUTPUT_WAKEUP = 0x3U,
54 } rtc_output_select_t;
55
59 typedef enum {
60 RTC_OUTPUT_POLARITY_HIGH = 0x0U,
61 RTC_OUTPUT_POLARITY_LOW = 0x1U,
62 } rtc_output_polarity_t;
63
67 typedef struct {
68 rtc_hour_format_t hour_format;
69 uint32_t asynch_pre_div;
70 uint32_t synch_pre_div;
71 rtc_output_select_t output;
72 rtc_output_polarity_t output_polarity;
73 } rtc_init_t;
74
78 typedef enum {
79 RTC_SOURCE_LOSC = 0x0U,
80 RTC_SOURCE_LRC = 0x1U,
81 RTC_SOURCE_HRC_DIV_1M = 0x2U,
82 RTC_SOURCE_HOSC_DIV_1M = 0x3U,
83 } rtc_source_sel_t;
84
88 typedef struct {
89 uint8_t hour;
90 uint8_t minute;
91 uint8_t second;
92 uint16_t sub_sec;
93 } rtc_time_t;
94
98 typedef struct {
99 uint8_t week;
100 uint8_t day;
101 uint8_t month;
102 uint8_t year;
103 } rtc_date_t;
104
108 typedef enum {
109 RTC_FORMAT_DEC = 0U,
110 RTC_FORMAT_BCD = 1U,
111 } rtc_format_t;
112
116 typedef enum {
117 RTC_ALARM_A = 0x0U,
118 RTC_ALARM_B = 0x1U,
119 } rtc_alarm_idx_t;
120
124 typedef enum {
125 RTC_ALARM_MASK_NONE = 0x0U,
126 RTC_ALARM_MASK_WEEK_DAY = (1U << 30),
127 RTC_ALARM_MASK_HOUR = (1U << 23),
128 RTC_ALARM_MASK_MINUTE = (1U << 15),
129 RTC_ALARM_MASK_SECOND = (1U << 7),
130 RTC_ALARM_MASK_ALL = 0x40808080U,
131 } rtc_alarm_mask_t;
132
136 typedef enum {
137 RTC_ALARM_SS_MASK_NONE = 0xFU,
138 RTC_ALARM_SS_MASK_14_1 = 0x1U,
139 RTC_ALARM_SS_MASK_14_2 = 0x2U,
140 RTC_ALARM_SS_MASK_14_3 = 0x3U,
141 RTC_ALARM_SS_MASK_14_4 = 0x4U,
142 RTC_ALARM_SS_MASK_14_5 = 0x5U,
143 RTC_ALARM_SS_MASK_14_6 = 0x6U,
144 RTC_ALARM_SS_MASK_14_7 = 0x7U,
145 RTC_ALARM_SS_MASK_14_8 = 0x8U,
146 RTC_ALARM_SS_MASK_14_9 = 0x9U,
147 RTC_ALARM_SS_MASK_14_10 = 0xAU,
148 RTC_ALARM_SS_MASK_14_11 = 0xBU,
149 RTC_ALARM_SS_MASK_14_12 = 0xCU,
150 RTC_ALARM_SS_MASK_14_13 = 0xDU,
151 RTC_ALARM_SS_MASK_14 = 0xEU,
152 RTC_ALARM_SS_MASK_ALL = 0x0U,
153 } rtc_sub_second_mask_t;
154
157 typedef enum {
158 RTC_SELECT_DAY = 0x0U,
159 RTC_SELECT_WEEK = 0x1U,
160 } rtc_week_day_sel_t;
161
165 typedef struct {
166 rtc_alarm_idx_t idx;
167 rtc_time_t time;
168 uint32_t mask;
169 rtc_sub_second_mask_t ss_mask;
170 rtc_week_day_sel_t sel;
172 union {
173 uint8_t week;
174 uint8_t day;
175 };
176 } rtc_alarm_t;
177
181 typedef enum {
182 RTC_TS_SIGNAL_SEL_TAMPER0 = 0U,
183 RTC_TS_SIGNAL_SEL_TAMPER1 = 1U,
184 } rtc_ts_signal_sel_t;
185
189 typedef enum {
190 RTC_TS_RISING_EDGE = 0U,
191 RTC_TS_FALLING_EDGE = 1U,
192 } rtc_ts_trigger_style_t;
193
197 typedef enum {
198 RTC_TAMPER_0 = 0U,
199 RTC_TAMPER_1 = 1U,
200 } rtc_tamper_idx_t;
201
205 typedef enum {
206 RTC_TAMPER_TRIGGER_LOW = 0U,
207 RTC_TAMPER_TRIGGER_HIGH = 1U,
208 } rtc_tamper_trigger_t;
209
213 typedef enum {
214 RTC_TAMPER_SAMPLING_FREQ_32768 = 0U,
215 RTC_TAMPER_SAMPLING_FREQ_16384 = 1U,
216 RTC_TAMPER_SAMPLING_FREQ_8192 = 2U,
217 RTC_TAMPER_SAMPLING_FREQ_4096 = 3U,
218 RTC_TAMPER_SAMPLING_FREQ_2048 = 4U,
219 RTC_TAMPER_SAMPLING_FREQ_1024 = 5U,
220 RTC_TAMPER_SAMPLING_FREQ_512 = 6U,
221 RTC_TAMPER_SAMPLING_FREQ_256 = 7U,
222 } rtc_tamper_sampling_freq_t;
223
227 typedef enum {
228 RTC_TAMPER_DURATION_1 = 0U,
229 RTC_TAMPER_DURATION_2 = 1U,
230 RTC_TAMPER_DURATION_4 = 2U,
231 RTC_TAMPER_DURATION_8 = 3U,
232 } rtc_tamper_duration_t;
233
237 typedef struct {
238 rtc_tamper_idx_t idx;
239 rtc_tamper_trigger_t trig;
240 rtc_tamper_sampling_freq_t freq;
241 rtc_tamper_duration_t dur;
242 type_func_t ts;
243 } rtc_tamper_t;
244
248 typedef enum {
249 RTC_WAKEUP_CLOCK_DIV_16 = 0U,
250 RTC_WAKEUP_CLOCK_DIV_8 = 1U,
251 RTC_WAKEUP_CLOCK_DIV_4 = 2U,
252 RTC_WAKEUP_CLOCK_DIV_2 = 3U,
253 RTC_WAKEUP_CLOCK_1HZ = 4U,
254 RTC_WAKEUP_CLOCK_1HZ_PULS = 6U,
255 } rtc_wakeup_clock_t;
256
260 typedef enum {
261 RTC_CLOCK_OUTPUT_32768 = 0U,
262 RTC_CLOCK_OUTPUT_1024 = 1U,
263 RTC_CLOCK_OUTPUT_32 = 2U,
264 RTC_CLOCK_OUTPUT_1 = 3U,
265 RTC_CLOCK_OUTPUT_CAL_1 = 4U,
266 RTC_CLOCK_OUTPUT_EXA_1 = 5U,
267 } rtc_clock_output_t;
268
272 typedef enum {
273 RTC_CALI_FREQ_10_SEC = 0U,
274 RTC_CALI_FREQ_20_SEC = 1U,
275 RTC_CALI_FREQ_1_MIN = 2U,
276 RTC_CALI_FREQ_2_MIN = 3U,
277 RTC_CALI_FREQ_5_MIN = 4U,
278 RTC_CALI_FREQ_10_MIN = 5U,
279 RTC_CALI_FREQ_20_MIN = 6U,
280 RTC_CALI_FREQ_1_SEC = 7U,
281 } rtc_cali_freq_t;
282
286 typedef enum {
287 RTC_CALI_TC_NONE = 0U,
288 RTC_CALI_TC_AUTO_BY_HW = 1U,
289 RTC_CALI_TC_AUTO_BY_SF = 2U,
290 RTC_CALI_TC_AUTO_BY_HW_SF = 3U,
291 } rtc_cali_tc_t;
292
296 typedef enum {
297 RTC_CALI_CALC_FREQ_10_SEC = 0U,
298 RTC_CALI_CALC_FREQ_20_SEC = 1U,
299 RTC_CALI_CALC_FREQ_1_MIN = 2U,
300 RTC_CALI_CALC_FREQ_2_MIN = 3U,
301 RTC_CALI_CALC_FREQ_5_MIN = 4U,
302 RTC_CALI_CALC_FREQ_10_MIN = 5U,
303 RTC_CALI_CALC_FREQ_20_MIN = 6U,
304 RTC_CALI_CALC_FREQ_1_HOUR = 7U,
305 } rtc_cali_calc_freq_t;
306
310 typedef enum {
311 RTC_CALI_CALC_4 = 0U,
312 RTC_CALI_CALC_2 = 1U,
313 } rtc_cali_calc_t;
314
318 typedef struct {
319 rtc_cali_freq_t cali_freq;
320 rtc_cali_tc_t tc;
321 rtc_cali_calc_freq_t calc_freq;
322 rtc_cali_calc_t calc;
323 type_func_t acc;
324 } rtc_cali_t;
325
329 typedef enum {
330 RTC_IT_SEC = (1U << 0),
331 RTC_IT_MIN = (1U << 1),
332 RTC_IT_HR = (1U << 2),
333 RTC_IT_DAY = (1U << 3),
334 RTC_IT_MON = (1U << 4),
335 RTC_IT_YR = (1U << 5),
336 RTC_IT_ALMA = (1U << 8),
337 RTC_IT_ALMB = (1U << 9),
338 RTC_IT_TS = (1U << 10),
339 RTC_IT_TSOV = (1U << 11),
340 RTC_IT_TP0 = (1U << 12),
341 RTC_IT_TP1 = (1U << 13),
342 RTC_IT_RSC = (1U << 16),
343 RTC_IT_SFC = (1U << 17),
344 RTC_IT_WU = (1U << 18),
345 RTC_IT_TCC = (1U << 24),
346 RTC_IT_TCE = (1U << 25),
347 } rtc_it_t;
348
352 typedef enum {
353 RTC_IF_SEC = (1U << 0),
354 RTC_IF_MIN = (1U << 1),
355 RTC_IF_HR = (1U << 2),
356 RTC_IF_DAY = (1U << 3),
357 RTC_IF_MON = (1U << 4),
358 RTC_IF_YR = (1U << 5),
359 RTC_IF_ALMA = (1U << 8),
360 RTC_IF_ALMB = (1U << 9),
361 RTC_IF_TS = (1U << 10),
362 RTC_IF_TSOV = (1U << 11),
363 RTC_IF_TP0 = (1U << 12),
364 RTC_IF_TP1 = (1U << 13),
365 RTC_IF_RSC = (1U << 16),
366 RTC_IF_SFC = (1U << 17),
367 RTC_IF_WU = (1U << 18),
368 RTC_IF_TCC = (1U << 24),
369 RTC_IF_TCE = (1U << 25),
370 } rtc_flag_t;
378 #define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55U))
379 #define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0U))
380 #define RTC_BY_PASS_ENABLE() \
381 do { \
382 RTC_UNLOCK(); \
383 SET_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \
384 RTC_LOCK(); \
385 } while (0)
386 #define RTC_BY_PASS_DISABLE() \
387 do { \
388 RTC_UNLOCK(); \
389 CLEAR_BIT(RTC->CON, RTC_CON_SHDBP_MSK); \
390 RTC_LOCK(); \
391 } while (0)
392 #define RTC_SUMMER_TIME_ENABLE() \
393 do { \
394 RTC_UNLOCK(); \
395 SET_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \
396 RTC_LOCK(); \
397 } while (0)
398 #define RTC_SUMMER_TIME_DISABLE() \
399 do { \
400 RTC_UNLOCK(); \
401 CLEAR_BIT(RTC->CON, RTC_CON_ADD1H_MSK); \
402 RTC_LOCK(); \
403 } while (0)
404 #define RTC_WINTER_TIME_ENABLE() \
405 do { \
406 RTC_UNLOCK(); \
407 SET_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \
408 RTC_LOCK(); \
409 } while (0)
410 #define RTC_WINTER_TIME_DISABLE() \
411 do { \
412 RTC_UNLOCK(); \
413 CLEAR_BIT(RTC->CON, RTC_CON_SUB1H_MSK); \
414 RTC_LOCK(); \
415 } while (0)
416
423 #define RTC_CALI_UNLOCK() (WRITE_REG(RTC->CALWPR, 0x699655AAU))
424 #define RTC_CALI_LOCK() (WRITE_REG(RTC->CALWPR, 0x0U))
425 #define ALARM_MASK_ALL 0x40808080
426 #define RTC_TIMEOUT_VALUE 100
427
428 #define IS_SHIFT_SUB_SS(x) ((x) < (1U << 15))
429 #define IS_RTC_HOUR_FORMAT(x) (((x) == RTC_HOUR_FORMAT_24) || \
430 ((x) == RTC_HOUR_FORMAT_12))
431 #define IS_RTC_OUTPUT_SEL(x) (((x) == RTC_OUTPUT_DISABLE) || \
432 ((x) == RTC_OUTPUT_ALARM_A) || \
433 ((x) == RTC_OUTPUT_ALARM_B) || \
434 ((x) == RTC_OUTPUT_WAKEUP))
435 #define IS_RTC_OUTPUT_POLARITY(x) (((x) == RTC_OUTPUT_POLARITY_HIGH) || \
436 ((x) == RTC_OUTPUT_POLARITY_LOW))
437 #define IS_RTC_SOURCE_SEL(x) (((x) == RTC_SOURCE_LOSC) || \
438 ((x) == RTC_SOURCE_LRC) || \
439 ((x) == RTC_SOURCE_HRC_DIV_1M ) || \
440 ((x) == RTC_SOURCE_HOSC_DIV_1M))
441 #define IS_RTC_ALARM(x) (((x) == RTC_ALARM_A) || \
442 ((x) == RTC_ALARM_B))
443 #define IS_RTC_ALARM_SEL(x) (((x) == RTC_SELECT_DAY) || \
444 ((x) == RTC_SELECT_WEEK))
445 #define IS_RTC_ALARM_MASK(x) (((x) == RTC_ALARM_MASK_NONE) || \
446 ((x) == RTC_ALARM_MASK_WEEK_DAY) || \
447 ((x) == RTC_ALARM_MASK_HOUR) || \
448 ((x) == RTC_ALARM_MASK_MINUTE) || \
449 ((x) == RTC_ALARM_MASK_SECOND) || \
450 ((x) == RTC_ALARM_MASK_ALL))
451 #define IS_RTC_ALARM_SS_MASK(x) (((x) == RTC_ALARM_SS_MASK_NONE) || \
452 ((x) == RTC_ALARM_SS_MASK_14_1) || \
453 ((x) == RTC_ALARM_SS_MASK_14_2) || \
454 ((x) == RTC_ALARM_SS_MASK_14_3) || \
455 ((x) == RTC_ALARM_SS_MASK_14_4) || \
456 ((x) == RTC_ALARM_SS_MASK_14_5) || \
457 ((x) == RTC_ALARM_SS_MASK_14_6) || \
458 ((x) == RTC_ALARM_SS_MASK_14_7) || \
459 ((x) == RTC_ALARM_SS_MASK_14_8) || \
460 ((x) == RTC_ALARM_SS_MASK_14_9) || \
461 ((x) == RTC_ALARM_SS_MASK_14_10) || \
462 ((x) == RTC_ALARM_SS_MASK_14_11) || \
463 ((x) == RTC_ALARM_SS_MASK_14_12) || \
464 ((x) == RTC_ALARM_SS_MASK_14_13) || \
465 ((x) == RTC_ALARM_SS_MASK_14) || \
466 ((x) == RTC_ALARM_SS_MASK_ALL))
467 #define IS_RTC_TS_SIGNAL(x) (((x) == RTC_TS_SIGNAL_SEL_TAMPER0) || \
468 ((x) == RTC_TS_SIGNAL_SEL_TAMPER1))
469 #define IS_RTC_TS_STYLE(x) (((x) == RTC_TS_RISING_EDGE) || \
470 ((x) == RTC_TS_FALLING_EDGE))
471 #define IS_RTC_FORMAT(x) (((x) == RTC_FORMAT_DEC) || \
472 ((x) == RTC_FORMAT_BCD))
473 #define IS_RTC_TAMPER(x) (((x) == RTC_TAMPER_0) || \
474 ((x) == RTC_TAMPER_1))
475 #define IS_RTC_TAMPER_TRIGGER(x) (((x) == RTC_TAMPER_TRIGGER_LOW) || \
476 ((x) == RTC_TAMPER_TRIGGER_HIGH))
477 #define IS_RTC_TAMPER_SAMPLING_FREQ(x) (((x) == RTC_TAMPER_SAMPLING_FREQ_32768) || \
478 ((x) == RTC_TAMPER_SAMPLING_FREQ_16384) || \
479 ((x) == RTC_TAMPER_SAMPLING_FREQ_8192) || \
480 ((x) == RTC_TAMPER_SAMPLING_FREQ_4096) || \
481 ((x) == RTC_TAMPER_SAMPLING_FREQ_2048) || \
482 ((x) == RTC_TAMPER_SAMPLING_FREQ_1024) || \
483 ((x) == RTC_TAMPER_SAMPLING_FREQ_512) || \
484 ((x) == RTC_TAMPER_SAMPLING_FREQ_256))
485 #define IS_RTC_TAMPER_DURATION(x) (((x) == RTC_TAMPER_DURATION_1) || \
486 ((x) == RTC_TAMPER_DURATION_2) || \
487 ((x) == RTC_TAMPER_DURATION_4) || \
488 ((x) == RTC_TAMPER_DURATION_8))
489 #define IS_RTC_WAKEUP_CLOCK(x) (((x) == RTC_WAKEUP_CLOCK_DIV_16) || \
490 ((x) == RTC_WAKEUP_CLOCK_DIV_8) || \
491 ((x) == RTC_WAKEUP_CLOCK_DIV_4) || \
492 ((x) == RTC_WAKEUP_CLOCK_DIV_2) || \
493 ((x) == RTC_WAKEUP_CLOCK_1HZ) || \
494 ((x) == RTC_WAKEUP_CLOCK_1HZ_PULS))
495 #define IS_RTC_CLOCK_OUTPUT(x) (((x) == RTC_CLOCK_OUTPUT_32768) || \
496 ((x) == RTC_CLOCK_OUTPUT_1024) || \
497 ((x) == RTC_CLOCK_OUTPUT_32) || \
498 ((x) == RTC_CLOCK_OUTPUT_1) || \
499 ((x) == RTC_CLOCK_OUTPUT_CAL_1) || \
500 ((x) == RTC_CLOCK_OUTPUT_EXA_1))
501 #define IS_RTC_CALI_FREQ(x) (((x) == RTC_CALI_FREQ_10_SEC) || \
502 ((x) == RTC_CALI_FREQ_20_SEC) || \
503 ((x) == RTC_CALI_FREQ_1_MIN) || \
504 ((x) == RTC_CALI_FREQ_2_MIN) || \
505 ((x) == RTC_CALI_FREQ_5_MIN) || \
506 ((x) == RTC_CALI_FREQ_10_MIN) || \
507 ((x) == RTC_CALI_FREQ_20_MIN) || \
508 ((x) == RTC_CALI_FREQ_1_SEC))
509 #define IS_RTC_CALI_TC(x) (((x) == RTC_CALI_TC_NONE) || \
510 ((x) == RTC_CALI_TC_AUTO_BY_HW) || \
511 ((x) == RTC_CALI_TC_AUTO_BY_SF) || \
512 ((x) == RTC_CALI_TC_AUTO_BY_HW_SF))
513 #define IS_RTC_CALC_FREQ(x) (((x) == RTC_CALI_CALC_FREQ_10_SEC) || \
514 ((x) == RTC_CALI_CALC_FREQ_20_SEC) || \
515 ((x) == RTC_CALI_CALC_FREQ_1_MIN) || \
516 ((x) == RTC_CALI_CALC_FREQ_2_MIN) || \
517 ((x) == RTC_CALI_CALC_FREQ_5_MIN) || \
518 ((x) == RTC_CALI_CALC_FREQ_10_MIN) || \
519 ((x) == RTC_CALI_CALC_FREQ_20_MIN) || \
520 ((x) == RTC_CALI_CALC_FREQ_1_HOUR))
521 #define IS_RTC_CALI_CALC(x) (((x) == RTC_CALI_CALC_4) || \
522 ((x) == RTC_CALI_CALC_2))
523 #define IS_RTC_IT(x) (((x) == RTC_IT_SEC) || \
524 ((x) == RTC_IT_MIN) || \
525 ((x) == RTC_IT_HR) || \
526 ((x) == RTC_IT_DAY) || \
527 ((x) == RTC_IT_MON) || \
528 ((x) == RTC_IT_YR) || \
529 ((x) == RTC_IT_ALMA) || \
530 ((x) == RTC_IT_ALMB) || \
531 ((x) == RTC_IT_TS) || \
532 ((x) == RTC_IT_TSOV) || \
533 ((x) == RTC_IT_TP0) || \
534 ((x) == RTC_IT_TP1) || \
535 ((x) == RTC_IT_RSC) || \
536 ((x) == RTC_IT_SFC) || \
537 ((x) == RTC_IT_WU) || \
538 ((x) == RTC_IT_TCC) || \
539 ((x) == RTC_IT_TCE))
540 #define IS_RTC_IF(x) (((x) == RTC_IF_SEC) || \
541 ((x) == RTC_IF_MIN) || \
542 ((x) == RTC_IF_HR) || \
543 ((x) == RTC_IF_DAY) || \
544 ((x) == RTC_IF_MON) || \
545 ((x) == RTC_IF_YR) || \
546 ((x) == RTC_IF_ALMA) || \
547 ((x) == RTC_IF_ALMB) || \
548 ((x) == RTC_IF_TS) || \
549 ((x) == RTC_IF_TSOV) || \
550 ((x) == RTC_IF_TP0) || \
551 ((x) == RTC_IF_TP1) || \
552 ((x) == RTC_IF_RSC) || \
553 ((x) == RTC_IF_SFC) || \
554 ((x) == RTC_IF_WU) || \
555 ((x) == RTC_IF_TCC) || \
556 ((x) == RTC_IF_TCE))
557 #define IS_RTC_SECOND(x) ((x) < 60)
558 #define IS_RTC_MINUTE(x) ((x) < 60)
559 #define IS_RTC_HOUR(x) ((x) < 24)
560 #define IS_RTC_DAY(x) (((x) > 0) && ((x) < 32))
561 #define IS_RTC_MONTH(x) (((x) > 0) && ((x) < 13))
562 #define IS_RTC_YEAR(x) ((x) < 100)
563
574 /* Initialization functions */
575 void ald_rtc_reset(void);
576 void ald_rtc_init(rtc_init_t *init);
577 void ald_rtc_source_select(rtc_source_sel_t sel);
584 /* Time and date operation functions */
585 ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format);
586 ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format);
587 void ald_rtc_get_time(rtc_time_t *time, rtc_format_t format);
588 void ald_rtc_get_date(rtc_date_t *date, rtc_format_t format);
589 int32_t ald_rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format);
596 /* Alarm functions */
597 void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format);
598 void ald_rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format);
605 /* Time stamp functions */
606 void ald_rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style);
607 void ald_rtc_cancel_time_stamp(void);
608 void ald_rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format);
615 /* Tamper functions */
616 void ald_rtc_set_tamper(rtc_tamper_t *tamper);
617 void ald_rtc_cancel_tamper(rtc_tamper_idx_t idx);
624 /* Wakeup functions */
625 void ald_rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value);
626 void ald_rtc_cancel_wakeup(void);
627 uint16_t ald_rtc_get_wakeup_timer_value(void);
634 /* Clock output functions */
635 ald_status_t ald_rtc_set_clock_output(rtc_clock_output_t clock);
636 void ald_rtc_cancel_clock_output(void);
643 /* Control functions */
644 void ald_rtc_interrupt_config(rtc_it_t it, type_func_t state);
645 void ald_rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state);
646 ald_status_t ald_rtc_set_shift(type_func_t add_1s, uint16_t sub_ss);
647 void ald_rtc_set_cali(rtc_cali_t *config);
648 void ald_rtc_cancel_cali(void);
649 ald_status_t ald_rtc_get_cali_status(void);
650 void ald_rtc_write_temp(uint16_t temp);
651 it_status_t ald_rtc_get_it_status(rtc_it_t it);
652 flag_status_t ald_rtc_get_flag_status(rtc_flag_t flag);
653 void ald_rtc_clear_flag_status(rtc_flag_t flag);
666 #ifdef __cplusplus
667 }
668 #endif
669 #endif
RTC_TAMPER_SAMPLING_FREQ_512
Definition: ald_rtc.h:220
rtc_format_t
rtc_format_t
Data format.
Definition: ald_rtc.h:108
ald_rtc_cancel_wakeup
void ald_rtc_cancel_wakeup(void)
Cancel wake-up.
Definition: ald_rtc.c:877
ald_rtc_set_shift
ald_status_t ald_rtc_set_shift(type_func_t add_1s, uint16_t sub_ss)
Set shift parameters.
Definition: ald_rtc.c:1040
rtc_date_t::day
uint8_t day
Definition: ald_rtc.h:100
RTC_ALARM_SS_MASK_14_1
Definition: ald_rtc.h:138
ald_rtc_set_wakeup
void ald_rtc_set_wakeup(rtc_wakeup_clock_t clock, uint16_t value)
Set wake-up parameters.
Definition: ald_rtc.c:860
RTC_CALI_CALC_FREQ_1_MIN
Definition: ald_rtc.h:299
rtc_tamper_t::ts
type_func_t ts
Definition: ald_rtc.h:242
RTC_TAMPER_SAMPLING_FREQ_256
Definition: ald_rtc.h:221
rtc_cali_tc_t
rtc_cali_tc_t
Temperature compensate type.
Definition: ald_rtc.h:286
rtc_cali_t::cali_freq
rtc_cali_freq_t cali_freq
Definition: ald_rtc.h:319
RTC_CALI_TC_AUTO_BY_SF
Definition: ald_rtc.h:289
rtc_alarm_t::time
rtc_time_t time
Definition: ald_rtc.h:167
rtc_source_sel_t
rtc_source_sel_t
Source select.
Definition: ald_rtc.h:78
RTC_SELECT_WEEK
Definition: ald_rtc.h:159
RTC_ALARM_SS_MASK_14_11
Definition: ald_rtc.h:148
rtc_alarm_mask_t
rtc_alarm_mask_t
Alarm mask.
Definition: ald_rtc.h:124
rtc_tamper_trigger_t
rtc_tamper_trigger_t
Tamper trigger type.
Definition: ald_rtc.h:205
RTC_TS_SIGNAL_SEL_TAMPER0
Definition: ald_rtc.h:182
ald_rtc_cancel_tamper
void ald_rtc_cancel_tamper(rtc_tamper_idx_t idx)
Cancel tamper.
Definition: ald_rtc.c:819
RTC_WAKEUP_CLOCK_DIV_16
Definition: ald_rtc.h:249
ald_rtc_interrupt_config
void ald_rtc_interrupt_config(rtc_it_t it, type_func_t state)
Enable/disable the specified RTC interrupts.
Definition: ald_rtc.c:992
type_func_t
type_func_t
Definition: type.h:47
rtc_cali_t
Calibration structure.
Definition: ald_rtc.h:318
RTC_CALI_FREQ_20_MIN
Definition: ald_rtc.h:279
RTC_CALI_CALC_FREQ_20_MIN
Definition: ald_rtc.h:303
RTC_IF_ALMA
Definition: ald_rtc.h:359
RTC_TAMPER_DURATION_4
Definition: ald_rtc.h:230
ald_rtc_set_time_stamp
void ald_rtc_set_time_stamp(rtc_ts_signal_sel_t sel, rtc_ts_trigger_style_t style)
Set time stamp.
Definition: ald_rtc.c:692
RTC_CALI_CALC_FREQ_20_SEC
Definition: ald_rtc.h:298
RTC_TAMPER_SAMPLING_FREQ_4096
Definition: ald_rtc.h:217
rtc_init_t::hour_format
rtc_hour_format_t hour_format
Definition: ald_rtc.h:68
RTC_CALI_TC_NONE
Definition: ald_rtc.h:287
RTC_OUTPUT_DISABLE
Definition: ald_rtc.h:50
RTC_ALARM_SS_MASK_14_8
Definition: ald_rtc.h:145
RTC_TAMPER_TRIGGER_LOW
Definition: ald_rtc.h:206
rtc_tamper_t
Tamper structure.
Definition: ald_rtc.h:237
rtc_hour_format_t
rtc_hour_format_t
Hours format.
Definition: ald_rtc.h:41
RTC_ALARM_MASK_ALL
Definition: ald_rtc.h:130
RTC_OUTPUT_POLARITY_LOW
Definition: ald_rtc.h:61
RTC_CALI_FREQ_1_SEC
Definition: ald_rtc.h:280
rtc_alarm_t::week
uint8_t week
Definition: ald_rtc.h:173
RTC_IT_WU
Definition: ald_rtc.h:344
RTC_IT_TCC
Definition: ald_rtc.h:345
RTC_SOURCE_HRC_DIV_1M
Definition: ald_rtc.h:81
RTC_CALI_TC_AUTO_BY_HW_SF
Definition: ald_rtc.h:290
RTC_HOUR_FORMAT_12
Definition: ald_rtc.h:43
RTC_IT_TP1
Definition: ald_rtc.h:341
RTC_TAMPER_0
Definition: ald_rtc.h:198
RTC_ALARM_SS_MASK_14_13
Definition: ald_rtc.h:150
RTC_IF_TSOV
Definition: ald_rtc.h:362
RTC_IF_YR
Definition: ald_rtc.h:358
ald_rtc_get_flag_status
flag_status_t ald_rtc_get_flag_status(rtc_flag_t flag)
Get the status of RTC interrupt flag.
Definition: ald_rtc.c:1156
RTC_ALARM_SS_MASK_14_9
Definition: ald_rtc.h:146
rtc_tamper_duration_t
rtc_tamper_duration_t
Tamper filter time.
Definition: ald_rtc.h:227
rtc_date_t::month
uint8_t month
Definition: ald_rtc.h:101
rtc_cali_t::calc
rtc_cali_calc_t calc
Definition: ald_rtc.h:322
RTC_WAKEUP_CLOCK_DIV_8
Definition: ald_rtc.h:250
RTC_TS_RISING_EDGE
Definition: ald_rtc.h:190
RTC_IF_SEC
Definition: ald_rtc.h:353
RTC_IF_TP0
Definition: ald_rtc.h:363
RTC_ALARM_MASK_WEEK_DAY
Definition: ald_rtc.h:126
rtc_date_t::week
uint8_t week
Definition: ald_rtc.h:99
utils.h
This file contains the Utilities functions/types for the driver.
ald_rtc_set_clock_output
ald_status_t ald_rtc_set_clock_output(rtc_clock_output_t clock)
Set clock output parameters.
Definition: ald_rtc.c:919
ald_rtc_set_date
ald_status_t ald_rtc_set_date(rtc_date_t *date, rtc_format_t format)
Set specified date.
Definition: ald_rtc.c:357
RTC_ALARM_SS_MASK_14_3
Definition: ald_rtc.h:140
RTC_WAKEUP_CLOCK_DIV_2
Definition: ald_rtc.h:252
RTC_IT_TCE
Definition: ald_rtc.h:346
ald_rtc_reset
void ald_rtc_reset(void)
Reset RTC register.
Definition: ald_rtc.c:220
RTC_WAKEUP_CLOCK_1HZ
Definition: ald_rtc.h:253
rtc_cali_freq_t
rtc_cali_freq_t
Definition: ald_rtc.h:272
RTC_IT_TSOV
Definition: ald_rtc.h:339
ald_rtc_get_cali_status
ald_status_t ald_rtc_get_cali_status(void)
Get calibration status.
Definition: ald_rtc.c:1108
RTC_ALARM_MASK_MINUTE
Definition: ald_rtc.h:128
RTC_IF_HR
Definition: ald_rtc.h:355
RTC_FORMAT_DEC
Definition: ald_rtc.h:109
RTC_ALARM_SS_MASK_14_2
Definition: ald_rtc.h:139
rtc_cali_t::tc
rtc_cali_tc_t tc
Definition: ald_rtc.h:320
rtc_init_t::output_polarity
rtc_output_polarity_t output_polarity
Definition: ald_rtc.h:72
RTC_IT_MON
Definition: ald_rtc.h:334
RTC_CLOCK_OUTPUT_EXA_1
Definition: ald_rtc.h:266
it_status_t
enum flag_status_t it_status_t
RTC_IT_MIN
Definition: ald_rtc.h:331
RTC_TS_SIGNAL_SEL_TAMPER1
Definition: ald_rtc.h:183
ald_rtc_get_time
void ald_rtc_get_time(rtc_time_t *time, rtc_format_t format)
Get current time.
Definition: ald_rtc.c:402
RTC_IF_TS
Definition: ald_rtc.h:361
rtc_init_t::synch_pre_div
uint32_t synch_pre_div
Definition: ald_rtc.h:70
RTC_IF_DAY
Definition: ald_rtc.h:356
ald_rtc_write_temp
void ald_rtc_write_temp(uint16_t temp)
Write temperature value.
Definition: ald_rtc.c:1121
RTC_FORMAT_BCD
Definition: ald_rtc.h:110
RTC_CALI_FREQ_2_MIN
Definition: ald_rtc.h:276
ald_rtc_cancel_time_stamp
void ald_rtc_cancel_time_stamp(void)
Cancel time stamp.
Definition: ald_rtc.c:712
RTC_SELECT_DAY
Definition: ald_rtc.h:158
rtc_output_select_t
rtc_output_select_t
Output mode.
Definition: ald_rtc.h:49
RTC_TS_FALLING_EDGE
Definition: ald_rtc.h:191
ald_rtc_set_tamper
void ald_rtc_set_tamper(rtc_tamper_t *tamper)
Set tamper parameters.
Definition: ald_rtc.c:786
ald_rtc_init
void ald_rtc_init(rtc_init_t *init)
Initialize the RTC module.
Definition: ald_rtc.c:240
rtc_cali_t::calc_freq
rtc_cali_calc_freq_t calc_freq
Definition: ald_rtc.h:321
rtc_sub_second_mask_t
rtc_sub_second_mask_t
Alarm sub-second mask.
Definition: ald_rtc.h:136
rtc_cali_calc_t
rtc_cali_calc_t
Calibration algorithm.
Definition: ald_rtc.h:310
rtc_ts_signal_sel_t
rtc_ts_signal_sel_t
Time stamp signel select.
Definition: ald_rtc.h:181
RTC_IF_TCE
Definition: ald_rtc.h:369
RTC_ALARM_SS_MASK_14
Definition: ald_rtc.h:151
RTC_ALARM_SS_MASK_14_10
Definition: ald_rtc.h:147
ald_rtc_cancel_clock_output
void ald_rtc_cancel_clock_output(void)
Cancel clock output.
Definition: ald_rtc.c:949
RTC_IF_MON
Definition: ald_rtc.h:357
rtc_init_t::asynch_pre_div
uint32_t asynch_pre_div
Definition: ald_rtc.h:69
RTC_TAMPER_DURATION_2
Definition: ald_rtc.h:229
rtc_week_day_sel_t
rtc_week_day_sel_t
Alarm select week or day.
Definition: ald_rtc.h:157
ald_rtc_set_time
ald_status_t ald_rtc_set_time(rtc_time_t *time, rtc_format_t format)
Set specified time.
Definition: ald_rtc.c:314
RTC_IT_TP0
Definition: ald_rtc.h:340
rtc_init_t::output
rtc_output_select_t output
Definition: ald_rtc.h:71
RTC_ALARM_B
Definition: ald_rtc.h:118
ald_rtc_alarm_cmd
void ald_rtc_alarm_cmd(rtc_alarm_idx_t idx, type_func_t state)
Enable/Disable alarm.
Definition: ald_rtc.c:1018
RTC_CALI_CALC_FREQ_10_MIN
Definition: ald_rtc.h:302
RTC_ALARM_MASK_HOUR
Definition: ald_rtc.h:127
rtc_output_polarity_t
rtc_output_polarity_t
Output polarity.
Definition: ald_rtc.h:59
RTC_SOURCE_LRC
Definition: ald_rtc.h:80
RTC_ALARM_MASK_NONE
Definition: ald_rtc.h:125
rtc_time_t::minute
uint8_t minute
Definition: ald_rtc.h:90
rtc_ts_trigger_style_t
rtc_ts_trigger_style_t
Time stamp trigger style.
Definition: ald_rtc.h:189
rtc_alarm_t::day
uint8_t day
Definition: ald_rtc.h:174
RTC_CALI_FREQ_5_MIN
Definition: ald_rtc.h:277
RTC_CALI_FREQ_10_SEC
Definition: ald_rtc.h:273
rtc_alarm_t
Alarm structure.
Definition: ald_rtc.h:165
rtc_tamper_sampling_freq_t
rtc_tamper_sampling_freq_t
Tamper sampling frequency.
Definition: ald_rtc.h:213
RTC_IT_YR
Definition: ald_rtc.h:335
RTC_IT_DAY
Definition: ald_rtc.h:333
RTC_IF_RSC
Definition: ald_rtc.h:365
RTC_ALARM_SS_MASK_14_6
Definition: ald_rtc.h:143
rtc_it_t
rtc_it_t
Interrupt type.
Definition: ald_rtc.h:329
ald_rtc_get_alarm
void ald_rtc_get_alarm(rtc_alarm_t *alarm, rtc_format_t format)
Get alarm parameters.
Definition: ald_rtc.c:587
rtc_time_t::hour
uint8_t hour
Definition: ald_rtc.h:89
RTC_CALI_CALC_4
Definition: ald_rtc.h:311
RTC_CALI_CALC_FREQ_5_MIN
Definition: ald_rtc.h:301
rtc_tamper_t::dur
rtc_tamper_duration_t dur
Definition: ald_rtc.h:241
RTC_CLOCK_OUTPUT_1
Definition: ald_rtc.h:264
RTC_CLOCK_OUTPUT_CAL_1
Definition: ald_rtc.h:265
rtc_time_t::second
uint8_t second
Definition: ald_rtc.h:91
rtc_tamper_idx_t
rtc_tamper_idx_t
Index of tamper.
Definition: ald_rtc.h:197
RTC_CLOCK_OUTPUT_1024
Definition: ald_rtc.h:262
RTC_IT_SFC
Definition: ald_rtc.h:343
RTC_ALARM_SS_MASK_14_7
Definition: ald_rtc.h:144
rtc_alarm_t::mask
uint32_t mask
Definition: ald_rtc.h:168
rtc_tamper_t::freq
rtc_tamper_sampling_freq_t freq
Definition: ald_rtc.h:240
RTC_TAMPER_1
Definition: ald_rtc.h:199
RTC_IT_HR
Definition: ald_rtc.h:332
RTC_TAMPER_SAMPLING_FREQ_32768
Definition: ald_rtc.h:214
RTC_ALARM_MASK_SECOND
Definition: ald_rtc.h:129
rtc_flag_t
rtc_flag_t
Interrupt flag.
Definition: ald_rtc.h:352
RTC_ALARM_SS_MASK_14_4
Definition: ald_rtc.h:141
RTC_SOURCE_LOSC
Definition: ald_rtc.h:79
RTC_OUTPUT_POLARITY_HIGH
Definition: ald_rtc.h:60
RTC_TAMPER_TRIGGER_HIGH
Definition: ald_rtc.h:207
RTC_OUTPUT_WAKEUP
Definition: ald_rtc.h:53
rtc_alarm_t::idx
rtc_alarm_idx_t idx
Definition: ald_rtc.h:166
ald_rtc_get_date
void ald_rtc_get_date(rtc_date_t *date, rtc_format_t format)
Get current date.
Definition: ald_rtc.c:432
RTC_IT_TS
Definition: ald_rtc.h:338
RTC_IF_MIN
Definition: ald_rtc.h:354
rtc_clock_output_t
rtc_clock_output_t
RTC clock output type.
Definition: ald_rtc.h:260
RTC_CALI_CALC_FREQ_10_SEC
Definition: ald_rtc.h:297
ald_rtc_set_cali
void ald_rtc_set_cali(rtc_cali_t *config)
Set calibation.
Definition: ald_rtc.c:1067
rtc_time_t
Time structure.
Definition: ald_rtc.h:88
RTC_IF_WU
Definition: ald_rtc.h:367
rtc_alarm_idx_t
rtc_alarm_idx_t
Index of alarm.
Definition: ald_rtc.h:116
RTC_CALI_CALC_2
Definition: ald_rtc.h:312
rtc_cali_calc_freq_t
rtc_cali_calc_freq_t
Definition: ald_rtc.h:296
ald_rtc_cancel_cali
void ald_rtc_cancel_cali(void)
Cancel calibration.
Definition: ald_rtc.c:1095
ald_rtc_set_alarm
void ald_rtc_set_alarm(rtc_alarm_t *alarm, rtc_format_t format)
Set alarm.
Definition: ald_rtc.c:509
ald_rtc_get_time_stamp
void ald_rtc_get_time_stamp(rtc_time_t *ts_time, rtc_date_t *ts_date, rtc_format_t format)
Get time stamp value.
Definition: ald_rtc.c:728
flag_status_t
flag_status_t
Definition: type.h:37
RTC_WAKEUP_CLOCK_DIV_4
Definition: ald_rtc.h:251
RTC_WAKEUP_CLOCK_1HZ_PULS
Definition: ald_rtc.h:254
RTC_IF_ALMB
Definition: ald_rtc.h:360
rtc_alarm_t::ss_mask
rtc_sub_second_mask_t ss_mask
Definition: ald_rtc.h:169
RTC_TAMPER_SAMPLING_FREQ_8192
Definition: ald_rtc.h:216
RTC_CLOCK_OUTPUT_32
Definition: ald_rtc.h:263
rtc_date_t
Date structure.
Definition: ald_rtc.h:98
rtc_init_t
Initialization structure.
Definition: ald_rtc.h:67
RTC_OUTPUT_ALARM_B
Definition: ald_rtc.h:52
RTC_ALARM_SS_MASK_ALL
Definition: ald_rtc.h:152
RTC_TAMPER_DURATION_1
Definition: ald_rtc.h:228
rtc_tamper_t::idx
rtc_tamper_idx_t idx
Definition: ald_rtc.h:238
ald_rtc_source_select
void ald_rtc_source_select(rtc_source_sel_t sel)
Configure the RTC source.
Definition: ald_rtc.c:265
RTC_TAMPER_SAMPLING_FREQ_16384
Definition: ald_rtc.h:215
rtc_time_t::sub_sec
uint16_t sub_sec
Definition: ald_rtc.h:92
rtc_wakeup_clock_t
rtc_wakeup_clock_t
Wake-up clock.
Definition: ald_rtc.h:248
ald_rtc_clear_flag_status
void ald_rtc_clear_flag_status(rtc_flag_t flag)
Clear the specified RTC pending flag.
Definition: ald_rtc.c:1170
ald_rtc_get_it_status
it_status_t ald_rtc_get_it_status(rtc_it_t it)
Get the status of RTC interrupt source.
Definition: ald_rtc.c:1138
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
RTC_CLOCK_OUTPUT_32768
Definition: ald_rtc.h:261
RTC_ALARM_SS_MASK_14_5
Definition: ald_rtc.h:142
rtc_date_t::year
uint8_t year
Definition: ald_rtc.h:102
RTC_IT_SEC
Definition: ald_rtc.h:330
ald_rtc_get_wakeup_timer_value
uint16_t ald_rtc_get_wakeup_timer_value(void)
Get wake-up re-load register value.
Definition: ald_rtc.c:890
RTC_TAMPER_SAMPLING_FREQ_2048
Definition: ald_rtc.h:218
rtc_tamper_t::trig
rtc_tamper_trigger_t trig
Definition: ald_rtc.h:239
RTC_TAMPER_DURATION_8
Definition: ald_rtc.h:231
RTC_CALI_FREQ_1_MIN
Definition: ald_rtc.h:275
RTC_OUTPUT_ALARM_A
Definition: ald_rtc.h:51
RTC_IF_TCC
Definition: ald_rtc.h:368
RTC_CALI_CALC_FREQ_1_HOUR
Definition: ald_rtc.h:304
RTC_CALI_FREQ_20_SEC
Definition: ald_rtc.h:274
RTC_ALARM_SS_MASK_14_12
Definition: ald_rtc.h:149
rtc_alarm_t::sel
rtc_week_day_sel_t sel
Definition: ald_rtc.h:170
ald_rtc_get_date_time
int32_t ald_rtc_get_date_time(rtc_date_t *date, rtc_time_t *time, rtc_format_t format)
Get time and date consistency.
Definition: ald_rtc.c:464
RTC_TAMPER_SAMPLING_FREQ_1024
Definition: ald_rtc.h:219
RTC_IT_RSC
Definition: ald_rtc.h:342
RTC_CALI_CALC_FREQ_2_MIN
Definition: ald_rtc.h:300
RTC_ALARM_SS_MASK_NONE
Definition: ald_rtc.h:137
rtc_cali_t::acc
type_func_t acc
Definition: ald_rtc.h:323
RTC_IF_SFC
Definition: ald_rtc.h:366
RTC_IT_ALMA
Definition: ald_rtc.h:336
RTC_IT_ALMB
Definition: ald_rtc.h:337
RTC_CALI_FREQ_10_MIN
Definition: ald_rtc.h:278
RTC_CALI_TC_AUTO_BY_HW
Definition: ald_rtc.h:288
RTC_IF_TP1
Definition: ald_rtc.h:364
RTC_ALARM_A
Definition: ald_rtc.h:117
RTC_HOUR_FORMAT_24
Definition: ald_rtc.h:42
RTC_SOURCE_HOSC_DIV_1M
Definition: ald_rtc.h:82


ALD User Manual: D:/svn/src/ald_rtchw.c Source File

  • D:
  • svn
  • src
ald_rtchw.c
Go to the documentation of this file.
1
17 #include "ald_rtchw.h"
18
27 #ifdef ALD_RTC
28
37 static void delay_losc_clk(uint16_t u)
38 {
39 uint16_t i, j;
40
41 for (i = 0; i < u; i++) {
42 for (j = 0; j < 60; j++) {
43 __ASM volatile ("nop");
44 }
45 }
46 }
47
54 static uint8_t rtc_hw_auto_check(rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode)
55 {
56 uint8_t tom = READ_BITS(TSENSE->CR, TSENSE_CR_TOM_MSK, TSENSE_CR_TOM_POSS);
57 uint8_t shift[8] = {0, 2, 4, 6, 8, 8, 8, 8};
58
59 if (mode == RTC_CALI_MODE_NORMAL) {
60 if ((RTC->CALCON & 0x1F3000F) != (RTCINFO->RTC_CALCR & 0x1F3000F))
61 return 1;
62 }
63 else {
64 if ((RTC->CALCON & 0x183000F) != (RTCINFO->RTC_CALCR & 0x183000F))
65 return 1;
66
67 if (READ_BITS(RTC->CALCON, RTC_CALCON_TCP_MSK, RTC_CALCON_TCP_POSS) != 7) /* when sleep mode */
68 return 1;
69 }
70
71 if ((TSENSE->CR & 0x7702) != (RTCINFO->TEMP_CR & 0x7702))
72 return 1;
73 if (RTC->TEMPBDR != RTCINFO->RTC_TEMPBDR + config->offset_rtc_bdr)
74 return 1;
75 if (RTC->LTAXR != RTCINFO->RTC_LTAXR + config->offset_ltaxr)
76 return 1;
77 if (RTC->HTAXR != RTCINFO->RTC_HTAXR + config->offset_htaxr)
78 return 1;
79 if (RTC->HTAXR != RTCINFO->RTC_HTCAR + config->offset_htcar)
80 return 1;
81 if (RTC->HTCBR != RTCINFO->RTC_HTCBR + config->offset_htcbr)
82 return 1;
83 if (RTC->HTCCR != RTCINFO->RTC_HTCCR + config->offset_htccr)
84 return 1;
85 if (RTC->HTCDR != RTCINFO->RTC_HTCDR + config->offset_htcdr)
86 return 1;
87 if (RTC->HTCER != RTCINFO->RTC_HTCER + config->offset_htcer)
88 return 1;
89 if (RTC->LTAXR != RTCINFO->RTC_LTCAR + config->offset_ltcar)
90 return 1;
91 if (RTC->LTCBR != RTCINFO->RTC_LTCBR + config->offset_ltcbr)
92 return 1;
93 if (RTC->LTCCR != RTCINFO->RTC_LTCCR + config->offset_ltccr)
94 return 1;
95 if (RTC->LTCDR != RTCINFO->RTC_LTCDR + config->offset_ltcdr)
96 return 1;
97 if (RTC->LTCER != RTCINFO->RTC_LTCER + config->offset_ltcer)
98 return 1;
99 if (TSENSE->TBDR != (RTCINFO->TEMP_TBDR & 0xFFFF) + config->offset_temp_bdr)
100 return 1;
101 if (TSENSE->LTGR != RTCINFO->TEMP_LTGR + config->offset_ltgr)
102 return 1;
103 if (TSENSE->HTGR != RTCINFO->TEMP_HTGR + config->offset_htgr)
104 return 1;
105 if (TSENSE->TCALBDR != (((RTCINFO->TEMP_TCALBDR & 0x1FFFFFF) >> shift[tom]) & 0x1FFFF)
106 + config->offset_tcalbdr)
107 return 1;
108
109 return 0;
110 }
124 void ald_rtc_hw_auto_cali(rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode)
125 {
126 uint8_t shift[8] = {0, 2, 4, 6, 8, 8, 8, 8};
127 uint8_t tmp;
128 uint32_t v = 0;
129 uint16_t temp_calf;
130
131 if (!(rtc_hw_auto_check(config, mode)))
132 return;
133
134 RTC_UNLOCK();
135 RTC_CALI_UNLOCK();
136 TSENSE_UNLOCK();
137
138 temp_calf = (uint16_t)RTC->CALDR;
139 while ((READ_BITS(RTC->IFR, RTC_IFR_TCCF_MSK, RTC_IFR_TCCF_POS) == 1) && (v < 0x20000)) /* no usr trig */
140 v++;
141
142 MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, 0 << RTC_CALCON_TCM_POSS); /* disable auto compensation */
143 MODIFY_REG(TSENSE->CR, TSENSE_CR_REQEN_MSK, 0 << TSENSE_CR_REQEN_POS); /* disable temp */
144
145 RTC->CALDR = temp_calf;
146 delay_losc_clk(3);
147
148 if (mode == RTC_CALI_MODE_NORMAL) {
149 v = RTC->CALCON & ~0x01F0000F;
150 RTC->CALCON = v | (RTCINFO->RTC_CALCR & 0x01F0000F);
151 }
152 else {
153 v = RTC->CALCON & ~0x0180000F;
154 RTC->CALCON = v | (RTCINFO->RTC_CALCR & 0x0180000F);
155 MODIFY_REG(RTC->CALCON, RTC_CALCON_TCP_MSK, 7 << RTC_CALCON_TCP_POSS); // when sleep mode, caluate once in 1h
156 }
157
158 RTC->TEMPBDR = RTCINFO->RTC_TEMPBDR + config->offset_rtc_bdr;
159 RTC->LTAXR = RTCINFO->RTC_LTAXR + config->offset_ltaxr;
160 RTC->HTAXR = RTCINFO->RTC_HTAXR + config->offset_htaxr;
161 RTC->LTCAR = RTCINFO->RTC_LTCAR + config->offset_ltcar;
162 RTC->LTCBR = RTCINFO->RTC_LTCBR + config->offset_ltcbr;
163 RTC->LTCCR = RTCINFO->RTC_LTCCR + config->offset_ltccr;
164 RTC->LTCDR = RTCINFO->RTC_LTCDR + config->offset_ltcdr;
165 RTC->LTCER = RTCINFO->RTC_LTCER + config->offset_ltcer;
166 RTC->HTCAR = RTCINFO->RTC_HTCAR + config->offset_htcar;
167 RTC->HTCBR = RTCINFO->RTC_HTCBR + config->offset_htcbr;
168 RTC->HTCCR = RTCINFO->RTC_HTCCR + config->offset_htccr;
169 RTC->HTCDR = RTCINFO->RTC_HTCDR + config->offset_htcdr;
170 RTC->HTCER = RTCINFO->RTC_HTCER + config->offset_htcer;
171 MODIFY_REG(RTC->CON, RTC_CON_CKOS_MSK, 5 << RTC_CON_CKOS_POSS); /* output accuracy 1Hz */
172
173 v = TSENSE->CR & ~0x00007700;
174 TSENSE->CR = v | (RTCINFO->TEMP_CR & 0x00007700);
175 TSENSE->HTGR = RTCINFO->TEMP_HTGR + config->offset_htgr;
176 TSENSE->LTGR = RTCINFO->TEMP_LTGR + config->offset_ltgr;
177 tmp = READ_BITS(RTCINFO->TEMP_CR, TSENSE_CR_TOM_MSK, TSENSE_CR_TOM_POSS);
178 TSENSE->TCALBDR = ((RTCINFO->TEMP_TCALBDR & 0x1FFFFFF) >> shift[tmp]) + config->offset_tcalbdr;
179 TSENSE->TBDR = RTCINFO->TEMP_TBDR + config->offset_temp_bdr;
180
181 delay_losc_clk(3);
182 tmp = READ_BITS(RTCINFO->TEMP_CR, TSENSE_CR_REQEN_MSK, TSENSE_CR_REQEN_POS);
183 MODIFY_REG(TSENSE->CR, TSENSE_CR_REQEN_MSK, tmp << TSENSE_CR_REQEN_POS);
184 MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, 3 << RTC_CALCON_TCM_POSS); /* usr trig */
185
186 delay_losc_clk(3);
187 MODIFY_REG(RTC->TEMPR, RTC_TEMPR_VAL_MSK, 1 << RTC_TEMPR_VAL_POSS); /* trig immediate*/
188
189 delay_losc_clk(3);
190 tmp = READ_BITS(RTCINFO->RTC_CALCR, RTC_CALCON_TCM_MSK, RTC_CALCON_TCM_POSS);
191 MODIFY_REG(RTC->CALCON, RTC_CALCON_TCM_MSK, tmp << RTC_CALCON_TCM_POSS);
192
193 RTC_CALI_LOCK();
194 RTC_LOCK();
195 TSENSE_LOCK();
196 return;
197 }
201 #endif /* ALD_RTC */
202
rtc_hw_cali_offset_t::offset_ltccr
int16_t offset_ltccr
Definition: ald_rtchw.h:91
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
rtc_hw_cali_offset_t::offset_ltcer
int16_t offset_ltcer
Definition: ald_rtchw.h:99
rtc_hw_cali_offset_t::offset_rtc_bdr
int16_t offset_rtc_bdr
Definition: ald_rtchw.h:85
RTC_LOCK
#define RTC_LOCK()
Definition: ald_rtc.h:379
TSENSE_UNLOCK
#define TSENSE_UNLOCK()
Definition: ald_rtchw.h:120
rtc_hw_cali_offset_t::offset_htgr
int16_t offset_htgr
Definition: ald_rtchw.h:98
rtc_hw_cali_offset_t::offset_ltaxr
int16_t offset_ltaxr
Definition: ald_rtchw.h:87
rtc_hw_cali_offset_t::offset_temp_bdr
int16_t offset_temp_bdr
Definition: ald_rtchw.h:86
rtc_hw_cali_offset_t::offset_ltcar
int16_t offset_ltcar
Definition: ald_rtchw.h:89
delay_losc_clk
static void delay_losc_clk(uint16_t u)
delay losc clock
Definition: ald_rtchw.c:37
RTCINFO
#define RTCINFO
Definition: ald_rtchw.h:123
rtc_hw_cali_offset_t::offset_htcar
int16_t offset_htcar
Definition: ald_rtchw.h:93
rtc_hw_cali_offset_t::offset_htccr
int16_t offset_htccr
Definition: ald_rtchw.h:95
rtc_hw_cali_offset_t::offset_htcer
int16_t offset_htcer
Definition: ald_rtchw.h:100
rtc_hw_cali_offset_t::offset_htcdr
int16_t offset_htcdr
Definition: ald_rtchw.h:96
rtc_hw_cali_offset_t::offset_htcbr
int16_t offset_htcbr
Definition: ald_rtchw.h:94
rtc_hw_cali_offset_t::offset_htaxr
int16_t offset_htaxr
Definition: ald_rtchw.h:88
RTC_CALI_LOCK
#define RTC_CALI_LOCK()
Definition: ald_rtc.h:424
RTC_CALI_UNLOCK
#define RTC_CALI_UNLOCK()
Definition: ald_rtc.h:423
TSENSE_LOCK
#define TSENSE_LOCK()
Definition: ald_rtchw.h:119
RTC_UNLOCK
#define RTC_UNLOCK()
Definition: ald_rtc.h:378
rtc_hw_cali_offset_t::offset_ltcbr
int16_t offset_ltcbr
Definition: ald_rtchw.h:90
rtc_hw_auto_check
static uint8_t rtc_hw_auto_check(rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode)
Check parameter for calibation.
Definition: ald_rtchw.c:54
RTC_CALI_MODE_NORMAL
Definition: ald_rtchw.h:42
rtc_hw_cali_offset_t
Hardware calibration structure.
Definition: ald_rtchw.h:84
rtc_hw_cali_offset_t::offset_tcalbdr
int16_t offset_tcalbdr
Definition: ald_rtchw.h:103
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
rtc_hw_cali_offset_t::offset_ltcdr
int16_t offset_ltcdr
Definition: ald_rtchw.h:92
ald_rtchw.h
Header file of RTCHW Module driver.
rtc_hw_cali_offset_t::offset_ltgr
int16_t offset_ltgr
Definition: ald_rtchw.h:97
ald_rtc_hw_auto_cali
void ald_rtc_hw_auto_cali(rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode)
Hardware automatic calibate.
Definition: ald_rtchw.c:124
rtc_hw_cali_mode_t
rtc_hw_cali_mode_t
Hardware calibration algorithm.
Definition: ald_rtchw.h:41


ALD User Manual: D:/svn/src/ald_rtchw.h Source File

  • D:
  • svn
  • src
ald_rtchw.h
Go to the documentation of this file.
1
16 #ifndef __ALD_RTCHW_H__
17 #define __ALD_RTCHW_H__
18
19 #ifdef __cplusplus
20 extern "C" {
21 #endif
22
23 #include "utils.h"
24 #include "ald_rtc.h"
25
26
41 typedef enum {
42 RTC_CALI_MODE_NORMAL = 0U,
43 RTC_CALI_MODE_SLEEP = 1U,
44 } rtc_hw_cali_mode_t;
45
49 typedef struct {
50 uint32_t MODE_CALI;
51 uint32_t RTC_CALCR;
52 uint32_t RTC_TEMPBDR;
53 uint32_t TEMP_TBDR;
54 uint32_t RTC_LTAXR;
55 uint32_t RTC_HTAXR;
56 uint32_t RTC_LTCAR;
57 uint32_t RTC_LTCBR;
58 uint32_t RTC_LTCCR;
59 uint32_t RTC_LTCDR;
60 uint32_t RTC_HTCAR;
61 uint32_t RTC_HTCBR;
62 uint32_t RTC_HTCCR;
63 uint32_t RTC_HTCDR;
64 uint32_t TEMP_LTGR;
65 uint32_t TEMP_HTGR;
66 uint32_t TEMP_CR;
67 uint32_t rsv0;
68 uint32_t RTC_LTCER;
69 uint32_t RTC_HTCER;
70 uint32_t TEMP_PEAK;
71 uint32_t FREQ_PEAK;
72 uint32_t TEMP_CALI;
73 uint32_t TEMP_CALI_AFTER;
74 uint32_t TEMP_TCALBDR;
75 uint32_t TEMP_TCALBDR_MINUS;
76 uint32_t rsv1[4];
77 uint32_t SUM;
78 uint32_t SUM_MINUS;
79 } RTCINFO_TypeDef;
80
84 typedef struct {
85 int16_t offset_rtc_bdr;
86 int16_t offset_temp_bdr;
87 int16_t offset_ltaxr;
88 int16_t offset_htaxr;
89 int16_t offset_ltcar;
90 int16_t offset_ltcbr;
91 int16_t offset_ltccr;
92 int16_t offset_ltcdr;
93 int16_t offset_htcar;
94 int16_t offset_htcbr;
95 int16_t offset_htccr;
96 int16_t offset_htcdr;
97 int16_t offset_ltgr;
98 int16_t offset_htgr;
99 int16_t offset_ltcer;
100 int16_t offset_htcer;
101 int16_t offset_temp_peak;
102 int16_t offset_freq_peak;
103 int16_t offset_tcalbdr;
104 int16_t crc;
105 int16_t rsv[8];
106 } rtc_hw_cali_offset_t;
113 #ifndef RTC_LOCK
114 #define RTC_LOCK() (WRITE_REG(RTC->WPR, 0x0U))
115 #define RTC_UNLOCK() (WRITE_REG(RTC->WPR, 0x55AAAA55U))
116 #endif
117
118 #ifndef TSENSE_LOCK
119 #define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0U))
120 #define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669U))
121 #endif
122
123 #define RTCINFO ((RTCINFO_TypeDef *)0x81000U)
124
131 /* Calibration functions */
132 void ald_rtc_hw_auto_cali(rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode);
142 #ifdef __cplusplus
143 }
144 #endif
145 #endif
RTCINFO_TypeDef::RTC_HTCER
uint32_t RTC_HTCER
Definition: ald_rtchw.h:69
RTCINFO_TypeDef::TEMP_HTGR
uint32_t TEMP_HTGR
Definition: ald_rtchw.h:65
RTCINFO_TypeDef::RTC_CALCR
uint32_t RTC_CALCR
Definition: ald_rtchw.h:51
RTCINFO_TypeDef::RTC_HTCDR
uint32_t RTC_HTCDR
Definition: ald_rtchw.h:63
rtc_hw_cali_offset_t::offset_ltccr
int16_t offset_ltccr
Definition: ald_rtchw.h:91
rtc_hw_cali_offset_t::offset_temp_peak
int16_t offset_temp_peak
Definition: ald_rtchw.h:101
rtc_hw_cali_offset_t::offset_ltcer
int16_t offset_ltcer
Definition: ald_rtchw.h:99
RTCINFO_TypeDef::rsv0
uint32_t rsv0
Definition: ald_rtchw.h:67
rtc_hw_cali_offset_t::offset_rtc_bdr
int16_t offset_rtc_bdr
Definition: ald_rtchw.h:85
RTCINFO_TypeDef::SUM
uint32_t SUM
Definition: ald_rtchw.h:77
RTCINFO_TypeDef::TEMP_TCALBDR_MINUS
uint32_t TEMP_TCALBDR_MINUS
Definition: ald_rtchw.h:75
RTCINFO_TypeDef::RTC_LTCER
uint32_t RTC_LTCER
Definition: ald_rtchw.h:68
rtc_hw_cali_offset_t::offset_htgr
int16_t offset_htgr
Definition: ald_rtchw.h:98
ald_rtc.h
Header file of RTC Module driver.
rtc_hw_cali_offset_t::offset_ltaxr
int16_t offset_ltaxr
Definition: ald_rtchw.h:87
rtc_hw_cali_offset_t::offset_temp_bdr
int16_t offset_temp_bdr
Definition: ald_rtchw.h:86
utils.h
This file contains the Utilities functions/types for the driver.
RTCINFO_TypeDef::RTC_HTCCR
uint32_t RTC_HTCCR
Definition: ald_rtchw.h:62
rtc_hw_cali_offset_t::offset_freq_peak
int16_t offset_freq_peak
Definition: ald_rtchw.h:102
RTCINFO_TypeDef::RTC_LTCDR
uint32_t RTC_LTCDR
Definition: ald_rtchw.h:59
rtc_hw_cali_offset_t::offset_ltcar
int16_t offset_ltcar
Definition: ald_rtchw.h:89
RTCINFO_TypeDef::RTC_LTCCR
uint32_t RTC_LTCCR
Definition: ald_rtchw.h:58
RTCINFO_TypeDef::TEMP_TBDR
uint32_t TEMP_TBDR
Definition: ald_rtchw.h:53
RTCINFO_TypeDef::RTC_HTCBR
uint32_t RTC_HTCBR
Definition: ald_rtchw.h:61
RTCINFO_TypeDef::TEMP_PEAK
uint32_t TEMP_PEAK
Definition: ald_rtchw.h:70
rtc_hw_cali_offset_t::offset_htcar
int16_t offset_htcar
Definition: ald_rtchw.h:93
RTCINFO_TypeDef::TEMP_CALI
uint32_t TEMP_CALI
Definition: ald_rtchw.h:72
RTCINFO_TypeDef::TEMP_CALI_AFTER
uint32_t TEMP_CALI_AFTER
Definition: ald_rtchw.h:73
RTCINFO_TypeDef::RTC_LTCBR
uint32_t RTC_LTCBR
Definition: ald_rtchw.h:57
rtc_hw_cali_offset_t::offset_htccr
int16_t offset_htccr
Definition: ald_rtchw.h:95
rtc_hw_cali_offset_t::offset_htcer
int16_t offset_htcer
Definition: ald_rtchw.h:100
RTCINFO_TypeDef::SUM_MINUS
uint32_t SUM_MINUS
Definition: ald_rtchw.h:78
RTCINFO_TypeDef::MODE_CALI
uint32_t MODE_CALI
Definition: ald_rtchw.h:50
rtc_hw_cali_offset_t::offset_htcdr
int16_t offset_htcdr
Definition: ald_rtchw.h:96
rtc_hw_cali_offset_t::offset_htcbr
int16_t offset_htcbr
Definition: ald_rtchw.h:94
rtc_hw_cali_offset_t::offset_htaxr
int16_t offset_htaxr
Definition: ald_rtchw.h:88
RTCINFO_TypeDef::TEMP_LTGR
uint32_t TEMP_LTGR
Definition: ald_rtchw.h:64
RTCINFO_TypeDef::RTC_LTAXR
uint32_t RTC_LTAXR
Definition: ald_rtchw.h:54
rtc_hw_cali_offset_t::offset_ltcbr
int16_t offset_ltcbr
Definition: ald_rtchw.h:90
RTCINFO_TypeDef::TEMP_TCALBDR
uint32_t TEMP_TCALBDR
Definition: ald_rtchw.h:74
RTC_CALI_MODE_NORMAL
Definition: ald_rtchw.h:42
RTCINFO_TypeDef::RTC_HTAXR
uint32_t RTC_HTAXR
Definition: ald_rtchw.h:55
rtc_hw_cali_offset_t
Hardware calibration structure.
Definition: ald_rtchw.h:84
RTCINFO_TypeDef::FREQ_PEAK
uint32_t FREQ_PEAK
Definition: ald_rtchw.h:71
rtc_hw_cali_offset_t::offset_tcalbdr
int16_t offset_tcalbdr
Definition: ald_rtchw.h:103
rtc_hw_cali_offset_t::crc
int16_t crc
Definition: ald_rtchw.h:104
RTCINFO_TypeDef::RTC_LTCAR
uint32_t RTC_LTCAR
Definition: ald_rtchw.h:56
rtc_hw_cali_offset_t::offset_ltcdr
int16_t offset_ltcdr
Definition: ald_rtchw.h:92
RTC_CALI_MODE_SLEEP
Definition: ald_rtchw.h:43
rtc_hw_cali_offset_t::offset_ltgr
int16_t offset_ltgr
Definition: ald_rtchw.h:97
ald_rtc_hw_auto_cali
void ald_rtc_hw_auto_cali(rtc_hw_cali_offset_t *config, rtc_hw_cali_mode_t mode)
Hardware automatic calibate.
Definition: ald_rtchw.c:124
RTCINFO_TypeDef::TEMP_CR
uint32_t TEMP_CR
Definition: ald_rtchw.h:66
RTCINFO_TypeDef::RTC_TEMPBDR
uint32_t RTC_TEMPBDR
Definition: ald_rtchw.h:52
RTCINFO_TypeDef
the parameters table of rtc calibration
Definition: ald_rtchw.h:49
RTCINFO_TypeDef::RTC_HTCAR
uint32_t RTC_HTCAR
Definition: ald_rtchw.h:60
rtc_hw_cali_mode_t
rtc_hw_cali_mode_t
Hardware calibration algorithm.
Definition: ald_rtchw.h:41


ALD User Manual: D:/svn/src/ald_spi.c Source File

  • D:
  • svn
  • src
ald_spi.c
Go to the documentation of this file.
1
59 #include "ald_spi.h"
60
61
70 #ifdef ALD_SPI
71
76 static void __spi_send_by_it(spi_handle_t *hperh);
77 static void __spi_recv_by_it(spi_handle_t *hperh);
78 static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status);
79 #ifdef ALD_DMA
80 static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout);
81 static void spi_dma_send_cplt(void *arg);
82 static void spi_dma_recv_cplt(void *arg);
83 static void spi_dma_send_recv_cplt(void *arg);
84 #endif
85
131 void ald_spi_reset(spi_handle_t *hperh)
132 {
133 hperh->perh->CON1 = 0x0;
134 hperh->perh->CON2 = 0x0;
135 hperh->perh->CRCPOLY = 0x00000007;
136
137 SPI_RESET_HANDLE_STATE(hperh);
138 __UNLOCK(hperh);
139
140 return;
141 }
142
150 ald_status_t ald_spi_init(spi_handle_t *hperh)
151 {
152 uint32_t tmp = 0;
153
154 if (hperh == NULL)
155 return ERROR;
156
157 assert_param(IS_SPI(hperh->perh));
158 assert_param(IS_SPI_MODE(hperh->init.mode));
159 assert_param(IS_SPI_DIRECTION(hperh->init.dir));
160 assert_param(IS_SPI_BAUD(hperh->init.baud));
161 assert_param(IS_SPI_FIRBIT(hperh->init.first_bit));
162 assert_param(IS_FUNC_STATE(hperh->init.ss_en));
163 assert_param(IS_FUNC_STATE(hperh->init.crc_calc));
164 assert_param(IS_SPI_DATASIZE(hperh->init.data_size));
165 assert_param(IS_SPI_CPHA(hperh->init.phase));
166 assert_param(IS_SPI_CPOL(hperh->init.polarity));
167 assert_param(IS_SPI_FRAME(hperh->init.frame));
168
169 ald_spi_reset(hperh);
170 tmp = hperh->perh->CON1;
171
172 if (hperh->init.mode == SPI_MODE_MASTER)
173 tmp |= 1 << SPI_CON1_SSOUT_POS;
174
175 tmp |= ((hperh->init.phase << SPI_CON1_CPHA_POS) | (hperh->init.polarity << SPI_CON1_CPOL_POS) |
176 (hperh->init.baud << SPI_CON1_BAUD_POSS) | (hperh->init.data_size << SPI_CON1_FLEN_POS) |
177 (hperh->init.mode << SPI_CON1_MSTREN_POS) | (hperh->init.ss_en << SPI_CON1_SSEN_POS) |
178 (hperh->init.first_bit << SPI_CON1_LSBFST_POS));
179
180 hperh->perh->CON1 = tmp;
181
182 MODIFY_REG(hperh->perh->CON2, SPI_CON2_FRF_MSK, hperh->init.frame << SPI_CON2_FRF_POS);
183
184 if (hperh->init.dir == SPI_DIRECTION_2LINES) {
185 CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK);
186 CLEAR_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK);
187 }
188 else if (hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) {
189 CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK);
190 SET_BIT(hperh->perh->CON1, SPI_CON1_RXO_MSK);
191 }
192 else if (hperh->init.dir == SPI_DIRECTION_1LINE_RX) {
193 SET_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK);
194 CLEAR_BIT(hperh->perh->CON1, SPI_CON1_BIDOEN_MSK);
195 }
196 else {
197 SET_BIT(hperh->perh->CON1, SPI_CON1_BIDEN_MSK);
198 SET_BIT(hperh->perh->CON1, SPI_CON1_BIDOEN_MSK);
199 }
200
201 /* configure CRC */
202 hperh->perh->CON1 |= (hperh->init.crc_calc << SPI_CON1_CRCEN_POS);
203 hperh->perh->CRCPOLY = hperh->init.crc_poly;
204
205 hperh->err_code = SPI_ERROR_NONE;
206 hperh->state = SPI_STATE_READY;
207
208 SPI_ENABLE(hperh);
209 return OK;
210 }
211
219 ald_status_t spi_fifo_threshold_config(spi_handle_t *hperh, uint8_t threshold)
220 {
221 assert_param(IS_SPI(hperh->perh));
222
223 MODIFY_REG(hperh->perh->CON2, SPI_CON2_RXFTH_MSK, threshold << SPI_CON2_RXFTH_POSS);
224 MODIFY_REG(hperh->perh->CON2, SPI_CON2_TXFTH_MSK, threshold << SPI_CON2_TXFTH_POSS);
225
226 return OK;
227 }
254 int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data)
255 {
256 uint16_t cnt = 5000, temp;
257
258 hperh->perh->DATA = data;
259 while (((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt));
260
261 cnt = 5000;
262 while (((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) && (--cnt));
263 temp = hperh->perh->DATA;
264 UNUSED(temp);
265
266 return cnt == 0 ? -1 : 0;
267 }
268
277 int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data)
278 {
279 uint16_t cnt = 5000;
280
281 hperh->perh->DATA = data;
282 while (((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt));
283
284 return cnt == 0 ? -1 : 0;
285 }
286
293 uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh, int *status)
294 {
295 uint16_t cnt = 5000;
296
297 if (hperh->init.mode == SPI_MODE_MASTER) {
298 hperh->perh->DATA = 0xFF;
299 while (((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) && (--cnt));
300 }
301
302 cnt = 5000;
303 while (((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) && (--cnt));
304 *status = cnt == 0 ? - 1 : 0;
305
306 return (uint8_t)hperh->perh->DATA;
307 }
308
318 ald_status_t ald_spi_send_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
319 {
320 uint32_t tick;
321 uint16_t i, tmp = 0;
322
323 while (size--) {
324 hperh->perh->DATA = *buf++;
325 tick = ald_get_tick();
326
327 while ((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) {
328 if (((ald_get_tick()) - tick) > timeout)
329 return TIMEOUT;
330 }
331 }
332
333 for (i = 0; i < 16; ++i) {
334 if ((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK)
335 tmp = hperh->perh->DATA;
336 else
337 break;
338 }
339
340 UNUSED(tmp);
341 return OK;
342 }
343
352 ald_status_t ald_spi_master_recv_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size)
353 {
354 uint16_t cnt = 8000;
355
356 while (size--) {
357 hperh->perh->DATA = 0xFF;
358 cnt = 8000;
359 while (((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) && (--cnt));
360
361 if (cnt)
362 *buf++ = (uint8_t)hperh->perh->DATA;
363 else
364 return TIMEOUT;
365 }
366
367 return OK;
368 }
369
379 ald_status_t ald_spi_slave_recv_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
380 {
381 uint32_t tick;
382
383 while (size--) {
384 tick = ald_get_tick();
385
386 while ((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) {
387 if (((ald_get_tick()) - tick) > timeout)
388 return TIMEOUT;
389 }
390
391 *buf++ = (uint8_t)hperh->perh->DATA;
392 }
393
394 return OK;
395 }
396
406 ald_status_t ald_spi_send_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
407 {
408 uint32_t tick;
409 uint16_t i, tmp = 0;
410
411 while (size--) {
412 hperh->perh->DATA = (*(uint16_t *)buf);
413 buf += 2;
414 tick = ald_get_tick();
415
416 while ((hperh->perh->STAT & SPI_STAT_TXE_MSK) == 0) {
417 if (((ald_get_tick()) - tick) > timeout)
418 return TIMEOUT;
419 }
420 }
421
422 for (i = 0; i < 16; ++i) {
423 if ((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK)
424 tmp = hperh->perh->DATA;
425 else
426 break;
427 }
428
429 UNUSED(tmp);
430 return OK;
431 }
432
441 ald_status_t ald_spi_master_recv_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size)
442 {
443 uint16_t cnt = 8000;
444
445 while (size--) {
446 hperh->perh->DATA = 0xFFFF;
447 cnt = 8000;
448 while (((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) && (--cnt));
449
450 if (cnt) {
451 *(uint16_t *)buf = (uint16_t)hperh->perh->DATA;
452 buf += 2;
453 }
454 else {
455 return TIMEOUT;
456 }
457 }
458
459 return OK;
460 }
461
471 ald_status_t ald_spi_slave_recv_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
472 {
473 uint32_t tick;
474
475 while (size--) {
476 tick = ald_get_tick();
477
478 while ((hperh->perh->STAT & SPI_STAT_RXE_MSK) == SPI_STAT_RXE_MSK) {
479 if (((ald_get_tick()) - tick) > timeout)
480 return TIMEOUT;
481 }
482
483 *(uint16_t *)buf = (uint16_t)hperh->perh->DATA;
484 buf += 2;
485 }
486
487 return OK;
488 }
532 ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
533 {
534 uint32_t tick;
535 uint16_t temp;
536
537 assert_param(IS_SPI(hperh->perh));
538
539 if (hperh->state != SPI_STATE_READY)
540 return BUSY;
541 if (buf == NULL || size == 0)
542 return ERROR;
543
544 hperh->state = SPI_STATE_BUSY_TX;
545
546 if (hperh->init.crc_calc)
547 SPI_CRC_RESET(hperh);
548
549 while (size > 1) {
550 tick = ald_get_tick();
551
552 while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) {
553 if (((ald_get_tick()) - tick) > timeout)
554 goto timeout;
555 }
556
557 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
558 hperh->perh->DATA = *buf;
559 ++buf;
560 }
561 else {
562 hperh->perh->DATA = (*(uint16_t *)buf);
563 buf += 2;
564 }
565
566 --size;
567 }
568
569 tick = ald_get_tick();
570
571 while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) {
572 if (((ald_get_tick()) - tick) > timeout)
573 goto timeout;
574 }
575
576 if (hperh->init.crc_calc) {
577 if (hperh->init.data_size == SPI_DATA_SIZE_8)
578 hperh->perh->DATA = *buf;
579 else
580 hperh->perh->DATA = (*(uint16_t *)buf);
581
582 SPI_CRCNEXT_ENABLE(hperh);
583 }
584 else {
585 if (hperh->init.data_size == SPI_DATA_SIZE_8)
586 hperh->perh->DATA = *buf;
587 else
588 hperh->perh->DATA = (*(uint16_t *)buf);
589 }
590
591 while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) {
592 if (((ald_get_tick()) - tick) > timeout)
593 goto timeout;
594 }
595
596 while ((hperh->perh->STAT & SPI_STATUS_BUSY) != RESET) {
597 if (((ald_get_tick()) - tick) > timeout)
598 goto timeout;
599 }
600
601 while ((spi_get_status(hperh, SPI_STATUS_RXE)) == RESET) {
602 temp = hperh->perh->DATA;
603 UNUSED(temp);
604 }
605
606 hperh->state = SPI_STATE_READY;
607 return OK;
608 timeout:
609 if (hperh->init.crc_calc)
610 SPI_CRC_RESET(hperh);
611
612 hperh->state = SPI_STATE_READY;
613 return TIMEOUT;
614 }
615
624 ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
625 {
626 uint32_t tick;
627 uint16_t temp;
628
629 assert_param(IS_SPI(hperh->perh));
630
631 if (hperh->state != SPI_STATE_READY)
632 return BUSY;
633 if (buf == NULL || size == 0)
634 return ERROR;
635
636 if (hperh->init.mode == SPI_MODE_MASTER)
637 return ald_spi_send_recv(hperh, buf, buf, size, timeout);
638
639 hperh->state = SPI_STATE_BUSY_RX;
640 hperh->err_code = SPI_ERROR_NONE;
641
642 if (hperh->init.crc_calc)
643 SPI_CRC_RESET(hperh);
644
645 while (size > 0) {
646 tick = ald_get_tick();
647
648 while ((hperh->perh->STAT & SPI_STATUS_RXE) != RESET) {
649 if (((ald_get_tick()) - tick) > timeout)
650 goto timeout;
651 }
652
653 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
654 *buf = hperh->perh->DATA;
655 ++buf;
656 }
657 else {
658 *(uint16_t *)buf = hperh->perh->DATA;
659 buf += 2;
660 }
661
662 --size;
663 }
664
665 if (hperh->init.crc_calc) {
666 tick = ald_get_tick();
667
668 while ((hperh->perh->STAT & SPI_STATUS_RXTH) != RESET) {
669 if (((ald_get_tick()) - tick) > timeout)
670 goto timeout;
671 }
672
673 temp = hperh->perh->DATA;
674 UNUSED(temp);
675
676 if ((hperh->perh->RIF & SPI_IF_CRCERR) != RESET) {
677 hperh->err_code |= SPI_ERROR_CRC;
678 SPI_CRC_RESET(hperh);
679 ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR);
680 hperh->state = SPI_STATE_READY;
681
682 return ERROR;
683 }
684 }
685
686 hperh->state = SPI_STATE_READY;
687 return OK;
688
689 timeout:
690 if (hperh->init.crc_calc)
691 SPI_CRC_RESET(hperh);
692
693 hperh->state = SPI_STATE_READY;
694 return TIMEOUT;
695 }
696
706 ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout)
707 {
708 uint32_t tick;
709 uint16_t temp;
710
711 assert_param(IS_SPI(hperh->perh));
712
713 if (hperh->state != SPI_STATE_READY)
714 return BUSY;
715 if (hperh->init.dir != SPI_DIRECTION_2LINES)
716 return ERROR;
717 if (tx_buf == NULL || rx_buf == NULL || size == 0)
718 return ERROR;
719
720 hperh->state = SPI_STATE_BUSY_TX_RX;
721 hperh->err_code = SPI_ERROR_NONE;
722
723 if (hperh->init.crc_calc)
724 SPI_CRC_RESET(hperh);
725
726 while (size > 1) {
727 tick = ald_get_tick();
728
729 while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) {
730 if (((ald_get_tick()) - tick) > timeout)
731 goto timeout;
732 }
733
734 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
735 hperh->perh->DATA = *tx_buf;
736 ++tx_buf;
737 }
738 else {
739 hperh->perh->DATA = (*(uint16_t *)tx_buf);
740 tx_buf += 2;
741 }
742
743 tick = ald_get_tick();
744
745 while ((hperh->perh->STAT & SPI_STATUS_RXE) != RESET) {
746 if (((ald_get_tick()) - tick) > timeout)
747 goto timeout;
748 }
749
750 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
751 *rx_buf = (uint8_t)hperh->perh->DATA;
752 ++rx_buf;
753 }
754 else {
755 (*(uint16_t *)rx_buf) = hperh->perh->DATA;
756 rx_buf += 2;
757 }
758
759 --size;
760 }
761
762 tick = ald_get_tick();
763
764 while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) {
765 if (((ald_get_tick()) - tick) > timeout)
766 goto timeout;
767 }
768
769 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
770 if (hperh->init.crc_calc) {
771 hperh->perh->DATA = *tx_buf;
772 SPI_CRCNEXT_ENABLE(hperh);
773 }
774 else {
775 hperh->perh->DATA = *tx_buf;
776 }
777 }
778 else {
779 if (hperh->init.crc_calc) {
780 hperh->perh->DATA = (*(uint16_t *)tx_buf);
781 SPI_CRCNEXT_ENABLE(hperh);
782 }
783 else {
784 hperh->perh->DATA = (*(uint16_t *)tx_buf);
785 }
786 }
787
788 tick = ald_get_tick();
789
790 while ((hperh->perh->STAT & SPI_STATUS_RXE) != RESET) {
791 if (((ald_get_tick()) - tick) > timeout)
792 goto timeout;
793 }
794
795 if (hperh->init.data_size == SPI_DATA_SIZE_8)
796 *rx_buf = (uint8_t)hperh->perh->DATA;
797 else
798 (*(uint16_t *)rx_buf) = hperh->perh->DATA;
799
800 if (hperh->init.crc_calc) {
801 tick = ald_get_tick();
802
803 while ((hperh->perh->STAT & SPI_STATUS_TXE) == RESET) {
804 if (((ald_get_tick()) - tick) > timeout)
805 goto timeout;
806 }
807
808 tick = ald_get_tick();
809
810 while ((hperh->perh->STAT & SPI_STATUS_RXE) != RESET) {
811 if (((ald_get_tick()) - tick) > timeout)
812 goto timeout;
813 }
814
815 temp = hperh->perh->DATA;
816 UNUSED(temp);
817
818 if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET) {
819 hperh->err_code |= SPI_ERROR_CRC;
820 SPI_CRC_RESET(hperh);
821 ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR);
822 hperh->state = SPI_STATE_READY;
823
824 return ERROR;
825 }
826 }
827
828 while ((hperh->perh->STAT & SPI_STATUS_BUSY) != RESET) {
829 if (((ald_get_tick()) - tick) > timeout)
830 goto timeout;
831 }
832
833 hperh->state = SPI_STATE_READY;
834 return OK;
835 timeout:
836 if (hperh->init.crc_calc)
837 SPI_CRC_RESET(hperh);
838
839 hperh->state = SPI_STATE_READY;
840 return TIMEOUT;
841 }
842
850 ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size)
851 {
852 assert_param(IS_SPI(hperh->perh));
853
854 if (hperh->state != SPI_STATE_READY)
855 return BUSY;
856 if (buf == NULL || size == 0)
857 return ERROR;
858
859 __LOCK(hperh);
860 hperh->state = SPI_STATE_BUSY_TX;
861 hperh->err_code = SPI_ERROR_NONE;
862
863 hperh->tx_buf = buf;
864 hperh->tx_size = size;
865 hperh->tx_count = size;
866 hperh->rx_buf = NULL;
867 hperh->rx_size = 0;
868 hperh->rx_count = 0;
869 __UNLOCK(hperh);
870
871 if (hperh->init.crc_calc)
872 SPI_CRC_RESET(hperh);
873
874 ald_spi_interrupt_config(hperh, SPI_IT_TXE, ENABLE);
875
876 return OK;
877 }
878
886 ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size)
887 {
888 assert_param(IS_SPI(hperh->perh));
889
890 if (hperh->state != SPI_STATE_READY)
891 return BUSY;
892 if (buf == NULL || size == 0)
893 return ERROR;
894 if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER))
895 return ERROR;
896
897 __LOCK(hperh);
898 hperh->state = SPI_STATE_BUSY_RX;
899 hperh->err_code = SPI_ERROR_NONE;
900
901 hperh->rx_buf = buf;
902 hperh->rx_size = size;
903 hperh->rx_count = size;
904 hperh->tx_buf = NULL;
905 hperh->tx_size = 0;
906 hperh->tx_count = 0;
907 __UNLOCK(hperh);
908
909 if (hperh->init.dir == SPI_DIRECTION_1LINE_RX)
910 SPI_1LINE_RX(hperh);
911
912 if (hperh->init.crc_calc == ENABLE) {
913 SPI_CRC_RESET(hperh);
914 ald_spi_interrupt_config(hperh, SPI_IT_CRCERR, ENABLE);
915 }
916
917 ald_spi_interrupt_config(hperh, SPI_IT_RXTH, ENABLE);
918 ald_spi_interrupt_config(hperh, SPI_IT_MODF, ENABLE);
919
920 if (hperh->init.data_size <= SPI_DATA_SIZE_8) {
921 *((uint8_t *)&(hperh->perh->DATA)) = 0xFF;
922 }
923 else {
924 *((uint16_t *)&(hperh->perh->DATA)) = 0xFFFF;
925 }
926
927 return OK;
928 }
929
939 ald_status_t ald_spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size)
940 {
941 assert_param(IS_SPI(hperh->perh));
942
943 if (hperh->state != SPI_STATE_READY)
944 return BUSY;
945 if (tx_buf == NULL || rx_buf == NULL || size == 0)
946 return ERROR;
947
948 __LOCK(hperh);
949 hperh->state = SPI_STATE_BUSY_TX_RX;
950 hperh->err_code = SPI_ERROR_NONE;
951
952 hperh->tx_buf = tx_buf;
953 hperh->tx_size = size;
954 hperh->tx_count = size;
955 hperh->rx_buf = rx_buf;
956 hperh->rx_size = size;
957 hperh->rx_count = size;
958 __UNLOCK(hperh);
959
960 if (hperh->init.crc_calc) {
961 SPI_CRC_RESET(hperh);
962 ald_spi_interrupt_config(hperh, SPI_IT_CRCERR, ENABLE);
963 }
964
965 if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX))
966 SPI_ENABLE(hperh);
967
968 ald_spi_interrupt_config(hperh, SPI_IT_RXTH, ENABLE);
969 ald_spi_interrupt_config(hperh, SPI_IT_TXE, ENABLE);
970 ald_spi_interrupt_config(hperh, SPI_IT_MODF, ENABLE);
971
972 return OK;
973 }
974
975 #ifdef ALD_DMA
976
984 ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
985 {
986 assert_param(IS_SPI(hperh->perh));
987
988 if (hperh->state != SPI_STATE_READY)
989 return BUSY;
990 if (buf == NULL || size == 0)
991 return ERROR;
992
993 __LOCK(hperh);
994 hperh->state = SPI_STATE_BUSY_TX;
995 hperh->err_code = SPI_ERROR_NONE;
996
997 hperh->tx_buf = buf;
998 hperh->tx_size = size;
999 hperh->tx_count = size;
1000 hperh->rx_buf = NULL;
1001 hperh->rx_size = 0;
1002 hperh->rx_count = 0;
1003
1004 if (hperh->init.dir == SPI_DIRECTION_1LINE)
1005 SPI_1LINE_TX(hperh);
1006 if (hperh->init.crc_calc)
1007 SPI_CRC_RESET(hperh);
1008
1009 if (hperh->hdmatx.perh == NULL)
1010 hperh->hdmatx.perh = DMA0;
1011
1012 hperh->hdmatx.cplt_arg = (void *)hperh;
1013 hperh->hdmatx.cplt_cbk = spi_dma_send_cplt;
1014
1015 /* Configure SPI DMA transmit */
1016 ald_dma_config_struct(&(hperh->hdmatx.config));
1017 hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD;
1018 hperh->hdmatx.config.src = (void *)buf;
1019 hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA;
1020 hperh->hdmatx.config.size = size;
1021 hperh->hdmatx.config.src_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;
1022 hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
1023 hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2);
1024 hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY;
1025 hperh->hdmatx.config.channel = channel;
1026 hperh->hdmatx.config.burst = ENABLE;
1027 ald_dma_config_basic(&(hperh->hdmatx));
1028
1029 __UNLOCK(hperh);
1030
1031 if (READ_BIT(hperh->perh->CON1, SPI_CON1_SPIEN_MSK) == 0)
1032 SPI_ENABLE(hperh);
1033
1034 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE);
1035
1036 return OK;
1037 }
1038
1047 ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
1048 {
1049 uint16_t tmp_rx = 0xB1B2;
1050 assert_param(IS_SPI(hperh->perh));
1051
1052 if (hperh->state != SPI_STATE_READY)
1053 return BUSY;
1054 if (buf == NULL || size == 0)
1055 return ERROR;
1056
1057 __LOCK(hperh);
1058 hperh->state = SPI_STATE_BUSY_RX;
1059 hperh->err_code = SPI_ERROR_NONE;
1060
1061 hperh->rx_buf = buf;
1062 hperh->rx_size = size;
1063 hperh->rx_count = size;
1064 hperh->tx_buf = NULL;
1065 hperh->tx_size = 0;
1066 hperh->tx_count = 0;
1067
1068 if (hperh->init.dir == SPI_DIRECTION_1LINE_RX)
1069 SPI_1LINE_RX(hperh);
1070 if ((hperh->init.dir == SPI_DIRECTION_2LINES) && (hperh->init.mode == SPI_MODE_MASTER)) {
1071 __UNLOCK(hperh);
1072 return ERROR;
1073 }
1074 if (hperh->init.crc_calc)
1075 SPI_CRC_RESET(hperh);
1076
1077 if (hperh->hdmatx.perh == NULL)
1078 hperh->hdmatx.perh = DMA0;
1079 if (hperh->hdmarx.perh == NULL)
1080 hperh->hdmarx.perh = DMA0;
1081
1082 hperh->hdmarx.cplt_arg = (void *)hperh;
1083 hperh->hdmarx.cplt_cbk = spi_dma_recv_cplt;
1084
1085 /* Configure SPI DMA transmit */
1086 ald_dma_config_struct(&(hperh->hdmatx.config));
1087 hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD;
1088 hperh->hdmatx.config.src = (void *)&tmp_rx;
1089 hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA;
1090 hperh->hdmatx.config.size = size;
1091 hperh->hdmatx.config.src_inc = DMA_DATA_INC_NONE;
1092 hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
1093 hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2);
1094 hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY;
1095 hperh->hdmatx.config.burst = ENABLE;
1096 hperh->hdmatx.config.channel = 11;
1097 ald_dma_config_basic(&(hperh->hdmatx));
1098
1099 /* Configure DMA Receive */
1100 ald_dma_config_struct(&(hperh->hdmarx.config));
1101 hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD;
1102 hperh->hdmarx.config.src = (void *)&hperh->perh->DATA;
1103 hperh->hdmarx.config.dst = (void *)buf;
1104 hperh->hdmarx.config.size = size;
1105 hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE;
1106 hperh->hdmarx.config.dst_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;;
1107 hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2);
1108 hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR;
1109 hperh->hdmatx.config.burst = ENABLE;
1110 hperh->hdmarx.config.channel = channel;
1111 ald_dma_config_basic(&(hperh->hdmarx));
1112
1113 __UNLOCK(hperh);
1114
1115 if ((hperh->init.dir == SPI_DIRECTION_2LINES_RXONLY) || (hperh->init.dir == SPI_DIRECTION_1LINE_RX))
1116 SPI_ENABLE(hperh);
1117
1118 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE);
1119 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE);
1120
1121 return OK;
1122 }
1123
1134 ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel)
1135 {
1136 assert_param(IS_SPI(hperh->perh));
1137
1138 if (hperh->state != SPI_STATE_READY && hperh->state != SPI_STATE_BUSY_RX)
1139 return BUSY;
1140 if (tx_buf == NULL || rx_buf == NULL || size == 0)
1141 return ERROR;
1142
1143 __LOCK(hperh);
1144 hperh->state = SPI_STATE_BUSY_RX;
1145 hperh->err_code = SPI_ERROR_NONE;
1146
1147 hperh->tx_buf = tx_buf;
1148 hperh->tx_size = size;
1149 hperh->tx_count = size;
1150 hperh->rx_buf = rx_buf;
1151 hperh->rx_size = size;
1152 hperh->rx_count = size;
1153
1154 if (hperh->hdmatx.perh == NULL)
1155 hperh->hdmatx.perh = DMA0;
1156 if (hperh->hdmarx.perh == NULL)
1157 hperh->hdmarx.perh = DMA0;
1158
1159 hperh->hdmatx.cplt_arg = NULL;
1160 hperh->hdmatx.cplt_cbk = NULL;
1161 hperh->hdmarx.cplt_arg = (void *)hperh;
1162 hperh->hdmarx.cplt_cbk = spi_dma_send_recv_cplt;
1163
1164 if (hperh->init.crc_calc)
1165 SPI_CRC_RESET(hperh);
1166
1167 /* Configure SPI DMA transmit */
1168 ald_dma_config_struct(&(hperh->hdmatx.config));
1169 hperh->hdmatx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD;
1170 hperh->hdmatx.config.src = (void *)tx_buf;
1171 hperh->hdmatx.config.dst = (void *)&hperh->perh->DATA;
1172 hperh->hdmatx.config.size = size;
1173 hperh->hdmatx.config.src_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;
1174 hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
1175 hperh->hdmatx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2);
1176 hperh->hdmatx.config.msigsel = DMA_MSIGSEL_SPI_TXEMPTY;
1177 hperh->hdmatx.config.burst = ENABLE;
1178 hperh->hdmatx.config.channel = tx_channel;
1179 ald_dma_config_basic(&(hperh->hdmatx));
1180
1181 /* Configure DMA Receive */
1182 ald_dma_config_struct(&(hperh->hdmarx.config));
1183 hperh->hdmarx.config.data_width = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_SIZE_BYTE : DMA_DATA_SIZE_HALFWORD;
1184 hperh->hdmarx.config.src = (void *)&hperh->perh->DATA;
1185 hperh->hdmarx.config.dst = (void *)rx_buf;
1186 hperh->hdmarx.config.size = size;
1187 hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE;
1188 hperh->hdmarx.config.dst_inc = hperh->init.data_size == SPI_DATA_SIZE_8 ? DMA_DATA_INC_BYTE : DMA_DATA_INC_HALFWORD;;
1189 hperh->hdmarx.config.msel = hperh->perh == SPI0 ? DMA_MSEL_SPI0 : (hperh->perh == SPI1 ? DMA_MSEL_SPI1 : DMA_MSEL_SPI2);
1190 hperh->hdmarx.config.msigsel = DMA_MSIGSEL_SPI_RNR;
1191 hperh->hdmarx.config.burst = ENABLE;
1192 hperh->hdmarx.config.channel = rx_channel;
1193 ald_dma_config_basic(&(hperh->hdmarx));
1194
1195 __UNLOCK(hperh);
1196 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE);
1197 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE);
1198
1199 return OK;
1200 }
1201
1207 ald_status_t ald_spi_dma_pause(spi_handle_t *hperh)
1208 {
1209 assert_param(IS_SPI(hperh->perh));
1210
1211 __LOCK(hperh);
1212 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE);
1213 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE);
1214 __UNLOCK(hperh);
1215
1216 return OK;
1217 }
1218
1224 ald_status_t ald_spi_dma_resume(spi_handle_t *hperh)
1225 {
1226 assert_param(IS_SPI(hperh->perh));
1227
1228 __LOCK(hperh);
1229 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, ENABLE);
1230 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, ENABLE);
1231 __UNLOCK(hperh);
1232
1233 return OK;
1234 }
1235
1241 ald_status_t ald_spi_dma_stop(spi_handle_t *hperh)
1242 {
1243 assert_param(IS_SPI(hperh->perh));
1244
1245 __LOCK(hperh);
1246 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE);
1247 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE);
1248 __UNLOCK(hperh);
1249
1250 hperh->state = SPI_STATE_READY;
1251 return OK;
1252 }
1253 #endif
1254
1284 void ald_spi_irq_handler(spi_handle_t *hperh)
1285 {
1286 if ((hperh->state == SPI_STATE_BUSY_RX) || (hperh->state == SPI_STATE_BUSY_TX)) {
1287 if ((ald_spi_get_it_status(hperh, SPI_IT_RXTH) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXTH) != RESET))
1288 __spi_recv_by_it(hperh);
1289
1290 if ((ald_spi_get_it_status(hperh, SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXE) != RESET))
1291 __spi_send_by_it(hperh);
1292 }
1293
1294 else if (hperh->state == SPI_STATE_BUSY_TX_RX) {
1295 if (hperh->init.mode == SPI_MODE_SLAVER) {
1296 if ((ald_spi_get_it_status(hperh, SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXE) != RESET))
1297 __spi_send_recv_by_it(hperh, SPI_SR_TXE);
1298 if ((ald_spi_get_it_status(hperh, SPI_IT_RXTH) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXTH) != RESET))
1299 __spi_send_recv_by_it(hperh, SPI_SR_RXNE);
1300 }
1301 else {
1302 if (hperh->rx_size == hperh->tx_count) {
1303 if ((ald_spi_get_it_status(hperh, SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXE) != RESET))
1304 __spi_send_recv_by_it(hperh, SPI_SR_TXE);
1305 }
1306 else {
1307 if ((ald_spi_get_it_status(hperh, SPI_IT_TXE) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_TXE) != RESET)
1308 && (ald_spi_get_it_status(hperh, SPI_IT_RXTH) != RESET) && (ald_spi_get_flag_status(hperh, SPI_IF_RXTH) != RESET))
1309 __spi_send_recv_by_it(hperh, SPI_SR_TXE_RXNE);
1310 }
1311 }
1312
1313 }
1314
1315 if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET) {
1316 hperh->err_code |= SPI_ERROR_CRC;
1317 ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR);
1318 }
1319 if (ald_spi_get_flag_status(hperh, SPI_IF_MODF) != RESET) {
1320 hperh->err_code |= SPI_ERROR_MODF;
1321 ald_spi_clear_flag_status(hperh, SPI_IF_MODF);
1322 }
1323 if (ald_spi_get_flag_status(hperh, SPI_IF_FRE) != RESET) {
1324 hperh->err_code |= SPI_ERROR_FRE;
1325 ald_spi_clear_flag_status(hperh, SPI_IF_FRE);
1326
1327 }
1328 if (ald_spi_get_flag_status(hperh, SPI_IF_TXOV) != RESET) {
1329 if (hperh->state != SPI_STATE_BUSY_TX) {
1330 hperh->err_code |= SPI_ERROR_TXOV;
1331 ald_spi_clear_flag_status(hperh, SPI_IF_TXOV);
1332 }
1333 }
1334 if (ald_spi_get_flag_status(hperh, SPI_IF_RXOV) != RESET) {
1335 if (hperh->state != SPI_STATE_BUSY_RX) {
1336 hperh->err_code |= SPI_ERROR_RXOV;
1337 ald_spi_clear_flag_status(hperh, SPI_IF_RXOV);
1338 }
1339 }
1340
1341 return;
1342 }
1343
1354 void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state)
1355 {
1356 assert_param(IS_SPI(hperh->perh));
1357 assert_param(IS_SPI_IT(it));
1358 assert_param(IS_FUNC_STATE(state));
1359
1360 if (state == ENABLE)
1361 hperh->perh->IER |= (uint32_t)it;
1362 else
1363 hperh->perh->IDR |= (uint32_t)it;
1364
1365 return;
1366 }
1367
1375 void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed)
1376 {
1377 uint32_t tmp = 0;
1378 assert_param(IS_SPI(hperh->perh));
1379 assert_param(IS_SPI_BAUD(speed));
1380
1381 tmp = hperh->perh->CON1;
1382 tmp &= ~(0x7U << SPI_CON1_BAUD_POSS);
1383 tmp |= (speed << SPI_CON1_BAUD_POSS);
1384 hperh->perh->CON1 = tmp;
1385 return;
1386 }
1387
1398 void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state)
1399 {
1400 assert_param(IS_SPI(hperh->perh));
1401 assert_param(IS_SPI_DMA_REQ(req));
1402 assert_param(IS_FUNC_STATE(state));
1403
1404 if (state == ENABLE) {
1405 if (req == SPI_DMA_REQ_TX)
1406 SET_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK);
1407 else
1408 SET_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK);
1409 }
1410 else {
1411 if (req == SPI_DMA_REQ_TX)
1412 CLEAR_BIT(hperh->perh->CON2, SPI_CON2_TXDMA_MSK);
1413 else
1414 CLEAR_BIT(hperh->perh->CON2, SPI_CON2_RXDMA_MSK);
1415 }
1416
1417 return;
1418 }
1419
1428 flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status)
1429 {
1430 assert_param(IS_SPI(hperh->perh));
1431 assert_param(IS_SPI_STATUS(status));
1432
1433 if (hperh->perh->STAT & status)
1434 return SET;
1435
1436 return RESET;
1437 }
1438
1448 it_status_t ald_spi_get_it_status(spi_handle_t *hperh, spi_it_t it)
1449 {
1450 assert_param(IS_SPI(hperh->perh));
1451 assert_param(IS_SPI_IT(it));
1452
1453 if (hperh->perh->IVS & it)
1454 return SET;
1455
1456 return RESET;
1457 }
1458
1467 flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag)
1468 {
1469 assert_param(IS_SPI(hperh->perh));
1470 assert_param(IS_SPI_IF(flag));
1471
1472 if (hperh->perh->RIF & flag)
1473 return SET;
1474
1475 return RESET;
1476 }
1477
1484 void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag)
1485 {
1486 assert_param(IS_SPI(hperh->perh));
1487 assert_param(IS_SPI_IF(flag));
1488
1489
1490 hperh->perh->ICR |= flag;
1491 return;
1492 }
1493
1494 #ifdef ALD_DMA
1495
1503 static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout)
1504 {
1505 assert_param(timeout > 0);
1506
1507 while (((ald_spi_get_flag_status(hperh, flag)) != status) && (--timeout));
1508
1509 if (timeout)
1510 return OK;
1511
1512 ald_spi_interrupt_config(hperh, SPI_IT_TXE, DISABLE);
1513 ald_spi_interrupt_config(hperh, SPI_IT_RXTH, DISABLE);
1514 ald_spi_interrupt_config(hperh, SPI_IT_CRCERR, DISABLE);
1515 ald_spi_interrupt_config(hperh, SPI_IT_MODF, DISABLE);
1516
1517 return TIMEOUT;
1518 }
1519 #endif
1520
1521 static ald_status_t spi_wait_bsy_flag(spi_handle_t *hperh, flag_status_t status, uint32_t timeout)
1522 {
1523 assert_param(timeout > 0);
1524
1525 while ((READ_BIT(hperh->perh->STAT, SPI_STAT_BUSY_MSK)) && (--timeout));
1526
1527 if (timeout)
1528 return OK;
1529
1530 ald_spi_interrupt_config(hperh, SPI_IT_TXE, DISABLE);
1531 ald_spi_interrupt_config(hperh, SPI_IT_RXTH, DISABLE);
1532 ald_spi_interrupt_config(hperh, SPI_IT_CRCERR, DISABLE);
1533 ald_spi_interrupt_config(hperh, SPI_IT_MODF, DISABLE);
1534
1535 return TIMEOUT;
1536 }
1537
1563 spi_state_t ald_spi_get_state(spi_handle_t *hperh)
1564 {
1565 assert_param(IS_SPI(hperh->perh));
1566 return hperh->state;
1567 }
1568
1574 uint32_t ald_spi_get_error(spi_handle_t *hperh)
1575 {
1576 assert_param(IS_SPI(hperh->perh));
1577 return hperh->err_code;
1578 }
1597 static void __spi_send_by_it(spi_handle_t *hperh)
1598 {
1599 uint16_t temp;
1600
1601 if (hperh->tx_count == 0) {
1602 ald_spi_interrupt_config(hperh, SPI_IT_TXE, DISABLE);
1603 hperh->state = SPI_STATE_READY;
1604
1605 if (hperh->init.dir == SPI_DIRECTION_2LINES) {
1606 ald_spi_clear_flag_status(hperh, SPI_IF_TXOV);
1607 }
1608
1609 if ((spi_wait_bsy_flag(hperh, RESET, 5000)) != OK) {
1610 if (hperh->err_cbk)
1611 hperh->err_cbk(hperh);
1612
1613 return;
1614 }
1615
1616 while ((spi_get_status(hperh, SPI_STATUS_RXE)) == RESET) {
1617 temp = hperh->perh->DATA;
1618 UNUSED(temp);
1619 }
1620
1621 if (hperh->tx_cplt_cbk)
1622 hperh->tx_cplt_cbk(hperh);
1623
1624 return;
1625 }
1626
1627 ald_spi_clear_flag_status(hperh, SPI_IF_TXE);
1628
1629 if (hperh->tx_count == 1) {
1630 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
1631 if (hperh->init.crc_calc) {
1632 hperh->perh->DATA = *hperh->tx_buf;
1633 SPI_CRCNEXT_ENABLE(hperh);
1634 }
1635 else {
1636 hperh->perh->DATA = *hperh->tx_buf;
1637 }
1638
1639 ++hperh->tx_buf;
1640 }
1641 else {
1642 if (hperh->init.crc_calc) {
1643 hperh->perh->DATA = *(uint16_t *)hperh->tx_buf;
1644 SPI_CRCNEXT_ENABLE(hperh);
1645 }
1646 else
1647 hperh->perh->DATA = *(uint16_t *)hperh->tx_buf;
1648
1649 hperh->tx_buf += 2;
1650 }
1651 }
1652 else {
1653 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
1654 hperh->perh->DATA = *hperh->tx_buf;
1655 ++hperh->tx_buf;
1656 }
1657 else {
1658 hperh->perh->DATA = *(uint16_t *)hperh->tx_buf;
1659 hperh->tx_buf += 2;
1660 }
1661 }
1662
1663 --hperh->tx_count;
1664 return;
1665 }
1666
1672 static void __spi_recv_by_it(spi_handle_t *hperh)
1673 {
1674 uint16_t temp;
1675
1676 while (READ_BITS(hperh->perh->STAT, SPI_STAT_RXFLV_MSK, SPI_STAT_RXFLV_POSS)) {
1677 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
1678 *hperh->rx_buf = hperh->perh->DATA;
1679 ++hperh->rx_buf;
1680 }
1681 else {
1682 *(uint16_t *)hperh->rx_buf = hperh->perh->DATA;
1683 hperh->rx_buf += 2;
1684 }
1685
1686 --hperh->rx_count;
1687 }
1688
1689 ald_spi_clear_flag_status(hperh, SPI_IF_RXTH);
1690
1691 if (hperh->rx_count == 0) {
1692 ald_spi_interrupt_config(hperh, SPI_IT_RXTH, DISABLE);
1693 hperh->state = SPI_STATE_READY;
1694
1695 if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) {
1696 hperh->err_code |= SPI_ERROR_CRC;
1697 ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR);
1698
1699 if (hperh->err_cbk)
1700 hperh->err_cbk(hperh);
1701
1702 return;
1703 }
1704
1705 if (hperh->init.crc_calc) {
1706 temp = hperh->perh->DATA;
1707 UNUSED(temp);
1708 }
1709
1710 if (hperh->rx_cplt_cbk)
1711 hperh->rx_cplt_cbk(hperh);
1712 }
1713
1714 if (hperh->init.data_size <= SPI_DATA_SIZE_8) {
1715 hperh->perh->DATA = 0xff;
1716 }
1717 else {
1718 hperh->perh->DATA = 0xffff;
1719 }
1720
1721 return;
1722 }
1723
1730 static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status)
1731 {
1732 if (hperh->rx_count != 0) {
1733 if ((status == SPI_SR_RXNE) || (status == SPI_SR_TXE_RXNE)) {
1734 ald_spi_clear_flag_status(hperh, SPI_IF_RXTH);
1735 while (spi_get_status(hperh, SPI_STATUS_RXTH) != RESET) {
1736 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
1737 *hperh->rx_buf = hperh->perh->DATA;
1738 ++hperh->rx_buf;
1739 }
1740 else {
1741 *(uint16_t *)hperh->rx_buf = hperh->perh->DATA;
1742 hperh->rx_buf += 2;
1743 }
1744 --hperh->rx_count;
1745 }
1746 }
1747 }
1748
1749 if (hperh->tx_count != 0) {
1750 if ((status == SPI_SR_TXE) || (status == SPI_SR_TXE_RXNE)) {
1751 ald_spi_clear_flag_status(hperh, SPI_IF_TXE);
1752 if (hperh->tx_count == 1) {
1753 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
1754 if (hperh->init.crc_calc) {
1755 hperh->perh->DATA = *hperh->tx_buf;
1756 SPI_CRCNEXT_ENABLE(hperh);
1757 }
1758 else {
1759 hperh->perh->DATA = *hperh->tx_buf;
1760 }
1761
1762 ++hperh->tx_buf;
1763 }
1764 else {
1765 if (hperh->init.crc_calc) {
1766 hperh->perh->DATA = *(uint16_t *)hperh->tx_buf;
1767 SPI_CRCNEXT_ENABLE(hperh);
1768 }
1769 else {
1770 hperh->perh->DATA = *(uint16_t *)hperh->tx_buf;
1771 }
1772
1773 hperh->tx_buf += 2;
1774 }
1775
1776 --hperh->tx_count;
1777 }
1778 else {
1779 if (hperh->init.data_size == SPI_DATA_SIZE_8) {
1780 hperh->perh->DATA = *hperh->tx_buf;
1781 ++hperh->tx_buf;
1782 }
1783 else {
1784 hperh->perh->DATA = *(uint16_t *)hperh->tx_buf;
1785 hperh->tx_buf += 2;
1786 }
1787
1788 --hperh->tx_count;
1789 }
1790 }
1791 }
1792
1793 if (hperh->rx_count == 0) {
1794 ald_spi_interrupt_config(hperh, SPI_IT_TXE, DISABLE);
1795 ald_spi_interrupt_config(hperh, SPI_IT_RXTH, DISABLE);
1796 ald_spi_interrupt_config(hperh, SPI_IT_MODF, DISABLE);
1797 hperh->state = SPI_STATE_READY;
1798
1799 if ((hperh->init.crc_calc) && (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) != RESET)) {
1800 hperh->err_code |= SPI_ERROR_CRC;
1801 ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR);
1802
1803 if (hperh->err_cbk)
1804 hperh->err_cbk(hperh);
1805
1806 return;
1807 }
1808
1809 if (hperh->tx_rx_cplt_cbk)
1810 hperh->tx_rx_cplt_cbk(hperh);
1811 }
1812
1813 return;
1814 }
1815
1816 #ifdef ALD_DMA
1817
1822 static void spi_dma_send_cplt(void *arg)
1823 {
1824 uint16_t delay, temp;
1825 spi_handle_t *hperh = (spi_handle_t *)arg;
1826
1827 hperh->tx_count = 0;
1828 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE);
1829 hperh->state = SPI_STATE_READY;
1830
1831 while ((spi_get_status(hperh, SPI_STATUS_RXE)) == RESET) {
1832 temp = hperh->perh->DATA;
1833 UNUSED(temp);
1834 }
1835
1836 if (hperh->init.dir == SPI_DIRECTION_2LINES)
1837 ald_spi_clear_flag_status(hperh, SPI_IF_TXOV);
1838
1839 if ((spi_wait_bsy_flag(hperh, RESET, 5000)) != OK)
1840 hperh->err_code |= SPI_ERROR_FLAG;
1841
1842 for (delay = 0; delay < 3000; delay++);
1843
1844 if (hperh->err_code == SPI_ERROR_NONE) {
1845 if (hperh->tx_cplt_cbk)
1846 hperh->tx_cplt_cbk(hperh);
1847 }
1848 else {
1849 if (hperh->err_cbk)
1850 hperh->err_cbk(hperh);
1851 }
1852
1853 return;
1854 }
1855
1861 static void spi_dma_recv_cplt(void *arg)
1862 {
1863 uint32_t tmp;
1864 spi_handle_t *hperh = (spi_handle_t *)arg;
1865
1866 hperh->rx_count = 0;
1867 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE);
1868 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE);
1869 hperh->state = SPI_STATE_READY;
1870
1871 if (hperh->init.crc_calc) {
1872 if ((spi_wait_flag_irq(hperh, SPI_IF_RXTH, SET, 5000)) != OK)
1873 hperh->err_code |= SPI_ERROR_FLAG;
1874
1875 tmp = hperh->perh->DATA;
1876 UNUSED(tmp);
1877
1878 if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) {
1879 SET_BIT(hperh->err_code, SPI_ERROR_CRC);
1880 SPI_CRC_RESET(hperh);
1881 ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR);
1882 }
1883 }
1884
1885 if (hperh->err_code == SPI_ERROR_NONE) {
1886 if (hperh->rx_cplt_cbk)
1887 hperh->rx_cplt_cbk(hperh);
1888 }
1889 else {
1890 if (hperh->err_cbk)
1891 hperh->err_cbk(hperh);
1892 }
1893
1894 return;
1895 }
1896
1902 static void spi_dma_send_recv_cplt(void *arg)
1903 {
1904 uint32_t tmp;
1905 uint16_t delay;
1906 spi_handle_t *hperh = (spi_handle_t *)arg;
1907
1908 if (hperh->init.crc_calc) {
1909 if ((spi_wait_flag_irq(hperh, SPI_IF_RXTH, SET, 5000)) != OK)
1910 hperh->err_code |= SPI_ERROR_FLAG;
1911
1912 tmp = hperh->perh->DATA;
1913 UNUSED(tmp);
1914
1915 if (ald_spi_get_flag_status(hperh, SPI_IF_CRCERR) == SET) {
1916 SET_BIT(hperh->err_code, SPI_ERROR_CRC);
1917 ald_spi_clear_flag_status(hperh, SPI_IF_CRCERR);
1918 }
1919 }
1920
1921 if ((spi_wait_bsy_flag(hperh, RESET, 5000)) != OK)
1922 hperh->err_code |= SPI_ERROR_FLAG;
1923
1924 for (delay = 0; delay < 3000; delay++);
1925
1926 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_TX, DISABLE);
1927 ald_spi_dma_req_config(hperh, SPI_DMA_REQ_RX, DISABLE);
1928 hperh->tx_count = 0;
1929 hperh->rx_count = 0;
1930 hperh->state = SPI_STATE_READY;
1931
1932 if (hperh->err_code == SPI_ERROR_NONE) {
1933 if (hperh->tx_rx_cplt_cbk)
1934 hperh->tx_rx_cplt_cbk(hperh);
1935 }
1936 else {
1937 if (hperh->err_cbk)
1938 hperh->err_cbk(hperh);
1939 }
1940
1941 return;
1942 }
1943
1944 #endif /* ALD_DMA */
1945
1948 #endif /* ALD_SPI */
1949
DMA_MSEL_SPI1
Definition: ald_dma.h:91
ald_spi.h
ald_spi_dma_resume
ald_status_t ald_spi_dma_resume(spi_handle_t *hperh)
Resumes the DMA Transfer.
Definition: ald_spi.c:1224
SPI_ERROR_FLAG
Definition: ald_spi.h:103
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
SPI_STATUS_TXE
Definition: ald_spi.h:185
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
ald_spi_get_it_status
it_status_t ald_spi_get_it_status(spi_handle_t *hperh, spi_it_t it)
Checks whether the specified SPI interrupt has occurred or not.
Definition: ald_spi.c:1448
spi_handle_s::rx_buf
uint8_t * rx_buf
Definition: ald_spi.h:234
IS_SPI_CPHA
#define IS_SPI_CPHA(x)
Definition: ald_spi.h:285
spi_state_t
spi_state_t
SPI state structures definition.
Definition: ald_spi.h:143
SPI_MODE_MASTER
Definition: ald_spi.h:60
spi_init_t::first_bit
spi_firstbit_t first_bit
Definition: ald_spi.h:218
IS_SPI_DATASIZE
#define IS_SPI_DATASIZE(x)
Definition: ald_spi.h:301
ald_spi_send_recv_by_it
ald_status_t ald_spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size)
Transmit and Receives an amount of data in non blocking mode.
Definition: ald_spi.c:939
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
SPI_ENABLE
#define SPI_ENABLE(x)
Definition: ald_spi.h:258
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
SPI_STATE_BUSY_TX_RX
Definition: ald_spi.h:149
SPI_ERROR_CRC
Definition: ald_spi.h:99
BUSY
Definition: utils.h:57
SPI_ERROR_RXOV
Definition: ald_spi.h:101
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
spi_init_t::crc_poly
uint16_t crc_poly
Definition: ald_spi.h:222
SPI_IT_CRCERR
Definition: ald_spi.h:118
SET
Definition: type.h:39
__spi_send_recv_by_it
static void __spi_send_recv_by_it(spi_handle_t *hperh, spi_sr_status_t status)
handle program when an rx no empty interrupt flag arrived in non block mode(2 lines) ...
Definition: ald_spi.c:1730
spi_dma_recv_cplt
static void spi_dma_recv_cplt(void *arg)
DMA SPI receive process complete callback.
Definition: ald_spi.c:1861
ald_spi_interrupt_config
void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state)
Enables or disables the specified SPI interrupts.
Definition: ald_spi.c:1354
spi_dma_send_recv_cplt
static void spi_dma_send_recv_cplt(void *arg)
DMA SPI transmit and receive process complete callback.
Definition: ald_spi.c:1902
spi_handle_s::tx_buf
uint8_t * tx_buf
Definition: ald_spi.h:231
IS_SPI_IF
#define IS_SPI_IF(x)
Definition: ald_spi.h:335
ald_spi_send_byte_fast
int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data)
Transmit one byte fast in blocking mode.
Definition: ald_spi.c:254
type_func_t
type_func_t
Definition: type.h:47
SPI_DMA_REQ_RX
Definition: ald_spi.h:170
DMA_MSEL_SPI2
Definition: ald_dma.h:99
DISABLE
Definition: type.h:48
spi_handle_s::tx_count
uint16_t tx_count
Definition: ald_spi.h:233
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
spi_init_t::ss_en
type_func_t ss_en
Definition: ald_spi.h:219
ald_spi_recv_byte_fast
uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh, int *status)
Receive one byte fast in blocking mode.
Definition: ald_spi.c:293
spi_init_t::crc_calc
type_func_t crc_calc
Definition: ald_spi.h:220
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
spi_handle_s::tx_rx_cplt_cbk
void(* tx_rx_cplt_cbk)(struct spi_handle_s *arg)
Definition: ald_spi.h:247
SPI_ERROR_MODF
Definition: ald_spi.h:98
spi_fifo_threshold_config
ald_status_t spi_fifo_threshold_config(spi_handle_t *hperh, uint8_t threshold)
Config the fifo threshold.
Definition: ald_spi.c:219
ald_spi_master_recv_dbytes_fast
ald_status_t ald_spi_master_recv_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size)
Receive some double-bytes fast in blocking mode.
Definition: ald_spi.c:441
SPI_1LINE_RX
#define SPI_1LINE_RX(x)
Definition: ald_spi.h:270
dma_config_t::src
void * src
Definition: ald_dma.h:278
SPI_IF_TXOV
Definition: ald_spi.h:128
ald_spi_get_flag_status
flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag)
Check whether the specified SPI flag is set or not.
Definition: ald_spi.c:1467
SPI_ERROR_TXOV
Definition: ald_spi.h:102
IS_SPI_FRAME
#define IS_SPI_FRAME(x)
Definition: ald_spi.h:346
IS_SPI_MODE
#define IS_SPI_MODE(x)
Definition: ald_spi.h:289
spi_handle_s::err_cbk
void(* err_cbk)(struct spi_handle_s *arg)
Definition: ald_spi.h:248
SPI_IT_TXE
Definition: ald_spi.h:110
spi_flag_t
spi_flag_t
interrupt flag
Definition: ald_spi.h:126
SPI_DIRECTION_2LINES_RXONLY
Definition: ald_spi.h:160
IS_SPI_FIRBIT
#define IS_SPI_FIRBIT(x)
Definition: ald_spi.h:291
spi_init_t::phase
spi_cpha_t phase
Definition: ald_spi.h:216
SPI_STATE_BUSY_RX
Definition: ald_spi.h:148
spi_dma_send_cplt
static void spi_dma_send_cplt(void *arg)
DMA SPI transmit process complete callback.
Definition: ald_spi.c:1822
DMA_DATA_SIZE_BYTE
Definition: ald_dma.h:227
SPI_DIRECTION_2LINES
Definition: ald_spi.h:159
RESET
Definition: type.h:38
IS_SPI_IT
#define IS_SPI_IT(x)
Definition: ald_spi.h:324
ald_spi_clear_flag_status
void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag)
Clear the specified SPI pending flags.
Definition: ald_spi.c:1484
IS_SPI_DIRECTION
#define IS_SPI_DIRECTION(x)
Definition: ald_spi.h:307
UNUSED
#define UNUSED(x)
Definition: type.h:76
ald_spi_send_dbytes_fast
ald_status_t ald_spi_send_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Transmit some double-bytes fast in blocking mode.
Definition: ald_spi.c:406
spi_baud_t
spi_baud_t
baud rate control
Definition: ald_spi.h:66
ald_spi_dma_pause
ald_status_t ald_spi_dma_pause(spi_handle_t *hperh)
Pauses the DMA Transfer.
Definition: ald_spi.c:1207
ald_spi_get_error
uint32_t ald_spi_get_error(spi_handle_t *hperh)
Return the SPI error code.
Definition: ald_spi.c:1574
spi_it_t
spi_it_t
interrupt control
Definition: ald_spi.h:109
it_status_t
enum flag_status_t it_status_t
spi_wait_flag_irq
static ald_status_t spi_wait_flag_irq(spi_handle_t *hperh, spi_flag_t flag, flag_status_t status, uint32_t timeout)
This function handles SPI communication timeout in interrupt function.
Definition: ald_spi.c:1503
ald_spi_send_recv_by_dma
ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel)
Transmit and Receive an amount of data used dma channel.
Definition: ald_spi.c:1134
SPI_DIRECTION_1LINE_RX
Definition: ald_spi.h:162
SPI_MODE_SLAVER
Definition: ald_spi.h:59
SPI_STATUS_RXTH
Definition: ald_spi.h:194
IS_SPI_DMA_REQ
#define IS_SPI_DMA_REQ(x)
Definition: ald_spi.h:311
spi_handle_s
SPI handle structure definition.
Definition: ald_spi.h:228
spi_handle_s::init
spi_init_t init
Definition: ald_spi.h:230
SPI_IF_RXOV
Definition: ald_spi.h:132
SPI_STATE_BUSY_TX
Definition: ald_spi.h:147
ald_spi_dma_req_config
void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state)
Enables or disables the dma request.
Definition: ald_spi.c:1398
ald_spi_send_recv
ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout)
Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
Definition: ald_spi.c:706
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
SPI_1LINE_TX
#define SPI_1LINE_TX(x)
Definition: ald_spi.h:269
spi_init_t::polarity
spi_cpol_t polarity
Definition: ald_spi.h:217
SPI_DMA_REQ_TX
Definition: ald_spi.h:169
IS_SPI
#define IS_SPI(x)
Definition: ald_spi.h:282
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_status_t
spi_status_t
SPI status definition.
Definition: ald_spi.h:184
spi_get_status
flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status)
Check whether the specified SPI state flag is set or not.
Definition: ald_spi.c:1428
spi_handle_s::state
spi_state_t state
Definition: ald_spi.h:242
SPI_IF_CRCERR
Definition: ald_spi.h:135
spi_init_t::baud
spi_baud_t baud
Definition: ald_spi.h:215
ald_spi_slave_recv_bytes_fast
ald_status_t ald_spi_slave_recv_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Receive some bytes fast in blocking mode.
Definition: ald_spi.c:379
SPI_DIRECTION_1LINE
Definition: ald_spi.h:161
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
ald_spi_irq_handler
void ald_spi_irq_handler(spi_handle_t *hperh)
This function handles SPI interrupt request.
Definition: ald_spi.c:1284
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
ald_spi_send_bytes_fast
ald_status_t ald_spi_send_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Transmit some bytes fast in blocking mode.
Definition: ald_spi.c:318
spi_wait_bsy_flag
static ald_status_t spi_wait_bsy_flag(spi_handle_t *hperh, flag_status_t status, uint32_t timeout)
Definition: ald_spi.c:1521
DMA_MSIGSEL_SPI_RNR
Definition: ald_dma.h:141
ald_spi_send
ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Transmit an amount of data in blocking mode.
Definition: ald_spi.c:532
DMA_DATA_INC_BYTE
Definition: ald_dma.h:217
ald_spi_send_by_dma
ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
Transmit an amount of data used dma channel.
Definition: ald_spi.c:984
__spi_send_by_it
static void __spi_send_by_it(spi_handle_t *hperh)
handle program when an tx empty interrupt flag arrived in non block mode
Definition: ald_spi.c:1597
spi_handle_s::rx_cplt_cbk
void(* rx_cplt_cbk)(struct spi_handle_s *arg)
Definition: ald_spi.h:246
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
spi_dma_req_t
spi_dma_req_t
SPI dma request definition.
Definition: ald_spi.h:168
SPI_IF_TXE
Definition: ald_spi.h:127
ald_spi_reset
void ald_spi_reset(spi_handle_t *hperh)
Reset the SPI peripheral.
Definition: ald_spi.c:131
IS_SPI_CPOL
#define IS_SPI_CPOL(x)
Definition: ald_spi.h:287
spi_handle_s::tx_size
uint16_t tx_size
Definition: ald_spi.h:232
spi_init_t::mode
spi_mode_t mode
Definition: ald_spi.h:212
spi_handle_s::hdmarx
dma_handle_t hdmarx
Definition: ald_spi.h:239
SPI_SR_TXE_RXNE
Definition: ald_spi.h:204
SPI_RESET_HANDLE_STATE
#define SPI_RESET_HANDLE_STATE(x)
Definition: ald_spi.h:257
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
ald_spi_recv_by_it
ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size)
Receives an amount of data in non blocking mode.
Definition: ald_spi.c:886
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
__spi_recv_by_it
static void __spi_recv_by_it(spi_handle_t *hperh)
handle program when an rx no empty interrupt flag arrived in non block mode
Definition: ald_spi.c:1672
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
ald_spi_dma_stop
ald_status_t ald_spi_dma_stop(spi_handle_t *hperh)
Stops the DMA Transfer.
Definition: ald_spi.c:1241
SPI_STATUS_RXE
Definition: ald_spi.h:190
spi_handle_s::hdmatx
dma_handle_t hdmatx
Definition: ald_spi.h:238
spi_init_t::dir
spi_direction_t dir
Definition: ald_spi.h:213
ald_spi_master_recv_bytes_fast
ald_status_t ald_spi_master_recv_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size)
Receive some bytes fast in blocking mode.
Definition: ald_spi.c:352
SPI_STATE_READY
Definition: ald_spi.h:145
spi_init_t::data_size
spi_datasize_t data_size
Definition: ald_spi.h:214
spi_init_t::frame
spi_frame_t frame
Definition: ald_spi.h:221
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
flag_status_t
flag_status_t
Definition: type.h:37
IS_SPI_STATUS
#define IS_SPI_STATUS(x)
Definition: ald_spi.h:313
ald_spi_init
ald_status_t ald_spi_init(spi_handle_t *hperh)
Initializes the SPI mode according to the specified parameters in the SPI_init_t and create the assoc...
Definition: ald_spi.c:150
DMA_MSIGSEL_SPI_TXEMPTY
Definition: ald_dma.h:142
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
SPI_CRC_RESET
#define SPI_CRC_RESET(x)
Definition: ald_spi.h:260
SPI_CRCNEXT_ENABLE
#define SPI_CRCNEXT_ENABLE(x)
Definition: ald_spi.h:265
spi_handle_s::err_code
uint32_t err_code
Definition: ald_spi.h:243
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
SPI_SR_RXNE
Definition: ald_spi.h:203
SPI_IF_RXTH
Definition: ald_spi.h:134
spi_handle_s::rx_size
uint16_t rx_size
Definition: ald_spi.h:235
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
spi_sr_status_t
spi_sr_status_t
SPI TXE/RXNE status definition.
Definition: ald_spi.h:201
SPI_IT_MODF
Definition: ald_spi.h:119
DMA_MSEL_SPI0
Definition: ald_dma.h:90
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ald_spi_recv_by_dma
ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
Receive an amount of data used dma channel.
Definition: ald_spi.c:1047
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
ERROR
Definition: utils.h:56
ald_spi_recv
ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Receive an amount of data in blocking mode.
Definition: ald_spi.c:624
ald_spi_get_state
spi_state_t ald_spi_get_state(spi_handle_t *hperh)
Returns the SPI state.
Definition: ald_spi.c:1563
SPI_DATA_SIZE_8
Definition: ald_spi.h:89
spi_handle_s::rx_count
uint16_t rx_count
Definition: ald_spi.h:236
SPI_ERROR_NONE
Definition: ald_spi.h:97
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
SPI_IT_RXTH
Definition: ald_spi.h:117
SPI_IF_MODF
Definition: ald_spi.h:136
IS_SPI_BAUD
#define IS_SPI_BAUD(x)
Definition: ald_spi.h:293
ald_spi_speed_config
void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed)
Configure the specified SPI speed.
Definition: ald_spi.c:1375
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
SPI_STATUS_BUSY
Definition: ald_spi.h:195
ald_spi_send_byte_fast_1line
int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data)
Transmit one byte fast in blocking mode(1line).
Definition: ald_spi.c:277
ald_spi_slave_recv_dbytes_fast
ald_status_t ald_spi_slave_recv_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Receive some double-bytes fast in blocking mode.
Definition: ald_spi.c:471
ald_spi_send_by_it
ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size)
Wraps up transmission in non blocking mode.
Definition: ald_spi.c:850
SPI_ERROR_FRE
Definition: ald_spi.h:100
SPI_IF_FRE
Definition: ald_spi.h:137
spi_handle_s::tx_cplt_cbk
void(* tx_cplt_cbk)(struct spi_handle_s *arg)
Definition: ald_spi.h:245
SPI_SR_TXE
Definition: ald_spi.h:202


ALD User Manual: D:/svn/src/ald_spi.h Source File

  • D:
  • svn
  • src
ald_spi.h
Go to the documentation of this file.
1
17 #ifndef __ALD_SPI_H__
18 #define __ALD_SPI_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25 #include "ald_dma.h"
26
42 typedef enum {
43 SPI_CPHA_FIRST = 0U,
44 SPI_CPHA_SECOND = 1U,
45 } spi_cpha_t;
46
50 typedef enum {
51 SPI_CPOL_LOW = 0U,
52 SPI_CPOL_HIGH = 1U,
53 } spi_cpol_t;
54
58 typedef enum {
59 SPI_MODE_SLAVER = 0U,
60 SPI_MODE_MASTER = 1U,
61 } spi_mode_t;
62
66 typedef enum {
67 SPI_BAUD_2 = 0U,
68 SPI_BAUD_4 = 1U,
69 SPI_BAUD_8 = 2U,
70 SPI_BAUD_16 = 3U,
71 SPI_BAUD_32 = 4U,
72 SPI_BAUD_64 = 5U,
73 SPI_BAUD_128 = 6U,
74 SPI_BAUD_256 = 7U,
75 } spi_baud_t;
76
80 typedef enum {
81 SPI_FIRSTBIT_MSB = 0U,
82 SPI_FIRSTBIT_LSB = 1U,
83 } spi_firstbit_t;
84
88 typedef enum {
89 SPI_DATA_SIZE_8 = 0U,
90 SPI_DATA_SIZE_16 = 1U,
91 } spi_datasize_t;
92
96 typedef enum {
97 SPI_ERROR_NONE = 0U,
98 SPI_ERROR_MODF = 1U,
99 SPI_ERROR_CRC = 2U,
100 SPI_ERROR_FRE = 4U,
101 SPI_ERROR_RXOV = 8U,
102 SPI_ERROR_TXOV = 0x10U,
103 SPI_ERROR_FLAG = 0x20U,
104 } spi_error_t;
105
109 typedef enum {
110 SPI_IT_TXE = (1U << 0),
111 SPI_IT_TXOV = (1U << 2),
112 SPI_IT_TXUD = (1U << 3),
113 SPI_IT_TXTH = (1U << 4),
114 SPI_IT_RXF = (1U << 9),
115 SPI_IT_RXOV = (1U << 10),
116 SPI_IT_RXUD = (1U << 11),
117 SPI_IT_RXTH = (1U << 12),
118 SPI_IT_CRCERR = (1U << 16),
119 SPI_IT_MODF = (1U << 17),
120 SPI_IT_FRE = (1U << 18),
121 } spi_it_t;
122
126 typedef enum {
127 SPI_IF_TXE = (1U << 0),
128 SPI_IF_TXOV = (1U << 2),
129 SPI_IF_TXUD = (1U << 3),
130 SPI_IF_TXTH = (1U << 4),
131 SPI_IF_RXF = (1U << 9),
132 SPI_IF_RXOV = (1U << 10),
133 SPI_IF_RXUD = (1U << 11),
134 SPI_IF_RXTH = (1U << 12),
135 SPI_IF_CRCERR = (1U << 16),
136 SPI_IF_MODF = (1U << 17),
137 SPI_IF_FRE = (1U << 18),
138 } spi_flag_t;
139
143 typedef enum {
144 SPI_STATE_RESET = 0x00U,
145 SPI_STATE_READY = 0x01U,
146 SPI_STATE_BUSY = 0x02U,
147 SPI_STATE_BUSY_TX = 0x11U,
148 SPI_STATE_BUSY_RX = 0x21U,
149 SPI_STATE_BUSY_TX_RX = 0x31U,
150 SPI_STATE_TIMEOUT = 0x03U,
151 SPI_STATE_ERROR = 0x04U,
152 } spi_state_t;
153
154
158 typedef enum {
159 SPI_DIRECTION_2LINES = 0U,
160 SPI_DIRECTION_2LINES_RXONLY = 1U,
161 SPI_DIRECTION_1LINE = 2U,
162 SPI_DIRECTION_1LINE_RX = 3U,
163 } spi_direction_t;
164
168 typedef enum {
169 SPI_DMA_REQ_TX = 0U,
170 SPI_DMA_REQ_RX = 1U,
171 } spi_dma_req_t;
172
176 typedef enum {
177 SPI_FRAME_MOTOROLA = 0U,
178 SPI_FRAME_TI = 1U,
179 } spi_frame_t;
180
184 typedef enum {
185 SPI_STATUS_TXE = (1U << 0),
186 SPI_STATUS_TXF = (1U << 1),
187 SPI_STATUS_TXOV = (1U << 2),
188 SPI_STATUS_TXUD = (1U << 3),
189 SPI_STATUS_TXTH = (1U << 4),
190 SPI_STATUS_RXE = (1U << 8),
191 SPI_STATUS_RXF = (1U << 9),
192 SPI_STATUS_RXOV = (1U << 10),
193 SPI_STATUS_RXUD = (1U << 11),
194 SPI_STATUS_RXTH = (1U << 12),
195 SPI_STATUS_BUSY = (1U << 15),
196 } spi_status_t;
197
201 typedef enum {
202 SPI_SR_TXE = 0U,
203 SPI_SR_RXNE = 1U,
204 SPI_SR_TXE_RXNE = 2U,
205 } spi_sr_status_t;
206
207
211 typedef struct {
212 spi_mode_t mode;
213 spi_direction_t dir;
214 spi_datasize_t data_size;
215 spi_baud_t baud;
216 spi_cpha_t phase;
217 spi_cpol_t polarity;
218 spi_firstbit_t first_bit;
219 type_func_t ss_en;
220 type_func_t crc_calc;
221 spi_frame_t frame;
222 uint16_t crc_poly;
223 } spi_init_t;
224
228 typedef struct spi_handle_s {
229 SPI_I2S_TypeDef *perh;
230 spi_init_t init;
231 uint8_t *tx_buf;
232 uint16_t tx_size;
233 uint16_t tx_count;
234 uint8_t *rx_buf;
235 uint16_t rx_size;
236 uint16_t rx_count;
237 #ifdef ALD_DMA
238 dma_handle_t hdmatx;
239 dma_handle_t hdmarx;
240 #endif
241 lock_state_t lock;
242 spi_state_t state;
243 uint32_t err_code;
245 void (*tx_cplt_cbk)(struct spi_handle_s *arg);
246 void (*rx_cplt_cbk)(struct spi_handle_s *arg);
247 void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg);
248 void (*err_cbk)(struct spi_handle_s *arg);
249 } spi_handle_t;
257 #define SPI_RESET_HANDLE_STATE(x) ((x)->state = SPI_STATE_RESET)
258 #define SPI_ENABLE(x) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS))
259 #define SPI_DISABLE(x) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS))
260 #define SPI_CRC_RESET(x) \
261 do { \
262 CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \
263 SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \
264 } while (0)
265 #define SPI_CRCNEXT_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
266 #define SPI_CRCNEXT_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
267 #define SPI_RXONLY_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))
268 #define SPI_RXONLY_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))
269 #define SPI_1LINE_TX(x) (SET_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK))
270 #define SPI_1LINE_RX(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK))
271 #define SPI_SSI_HIGH(x) (SET_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK))
272 #define SPI_SSI_LOW(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK))
273 #define SPI_SSOE_ENABLE(x) (SET_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK))
274 #define SPI_SSOE_DISABLE(x) (CLEAR_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK))
275
282 #define IS_SPI(x) (((x) == SPI0) || \
283 ((x) == SPI1) || \
284 ((x) == SPI2))
285 #define IS_SPI_CPHA(x) (((x) == SPI_CPHA_FIRST) || \
286 ((x) == SPI_CPHA_SECOND))
287 #define IS_SPI_CPOL(x) (((x) == SPI_CPOL_LOW) || \
288 ((x) == SPI_CPOL_HIGH))
289 #define IS_SPI_MODE(x) (((x) == SPI_MODE_SLAVER) || \
290 ((x) == SPI_MODE_MASTER))
291 #define IS_SPI_FIRBIT(x) (((x) == SPI_FIRSTBIT_MSB) || \
292 ((x) == SPI_FIRSTBIT_LSB))
293 #define IS_SPI_BAUD(x) (((x) == SPI_BAUD_2) || \
294 ((x) == SPI_BAUD_4) || \
295 ((x) == SPI_BAUD_8) || \
296 ((x) == SPI_BAUD_16) || \
297 ((x) == SPI_BAUD_32) || \
298 ((x) == SPI_BAUD_64) || \
299 ((x) == SPI_BAUD_128) || \
300 ((x) == SPI_BAUD_256))
301 #define IS_SPI_DATASIZE(x) (((x) == SPI_DATA_SIZE_8) || \
302 ((x) == SPI_DATA_SIZE_16))
303 #define IS_SPI_BIDOE(x) (((x) == SPI_BID_RX) || \
304 ((x) == SPI_BID_TX))
305 #define IS_SPI_BIDMODE(x) (((x) == SPI_BIDMODE_DUAL) || \
306 ((x) == SPI_BIDMODE_SOLE))
307 #define IS_SPI_DIRECTION(x) (((x) == SPI_DIRECTION_2LINES) || \
308 ((x) == SPI_DIRECTION_2LINES_RXONLY) || \
309 ((x) == SPI_DIRECTION_1LINE) || \
310 ((x) == SPI_DIRECTION_1LINE_RX))
311 #define IS_SPI_DMA_REQ(x) (((x) == SPI_DMA_REQ_TX) || \
312 ((x) == SPI_DMA_REQ_RX))
313 #define IS_SPI_STATUS(x) (((x) == SPI_STATUS_TXE) || \
314 ((x) == SPI_STATUS_TXF) || \
315 ((x) == SPI_STATUS_TXOV) || \
316 ((x) == SPI_STATUS_TXUD) || \
317 ((x) == SPI_STATUS_TXTH) || \
318 ((x) == SPI_STATUS_RXE) || \
319 ((x) == SPI_STATUS_RXF) || \
320 ((x) == SPI_STATUS_RXOV) || \
321 ((x) == SPI_STATUS_RXUD) || \
322 ((x) == SPI_STATUS_RXTH) || \
323 ((x) == SPI_STATUS_BUSY))
324 #define IS_SPI_IT(x) (((x) == SPI_IT_TXE) || \
325 ((x) == SPI_IT_TXOV) || \
326 ((x) == SPI_IT_TXUD) || \
327 ((x) == SPI_IT_TXTH) || \
328 ((x) == SPI_IT_RXF) || \
329 ((x) == SPI_IT_RXOV) || \
330 ((x) == SPI_IT_RXUD) || \
331 ((x) == SPI_IT_RXTH) || \
332 ((x) == SPI_IT_CRCERR) || \
333 ((x) == SPI_IT_MODF) || \
334 ((x) == SPI_IT_FRE))
335 #define IS_SPI_IF(x) (((x) == SPI_IF_TXE) || \
336 ((x) == SPI_IF_TXOV) || \
337 ((x) == SPI_IF_TXUD) || \
338 ((x) == SPI_IF_TXTH) || \
339 ((x) == SPI_IF_RXF) || \
340 ((x) == SPI_IF_RXOV) || \
341 ((x) == SPI_IF_RXUD) || \
342 ((x) == SPI_IF_RXTH) || \
343 ((x) == SPI_IF_CRCERR) || \
344 ((x) == SPI_IF_MODF) || \
345 ((x) == SPI_IF_FRE))
346 #define IS_SPI_FRAME(x) (((x) == SPI_FRAME_MOTOROLA) || \
347 ((x) == SPI_FRAME_TI) )
348
360 ald_status_t ald_spi_init(spi_handle_t *hperh);
361 void ald_spi_reset(spi_handle_t *hperh);
368 int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data);
369 int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data);
370 uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh, int *status);
371 ald_status_t ald_spi_send_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout);
372 ald_status_t ald_spi_master_recv_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size);
373 ald_status_t ald_spi_slave_recv_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout);
374 ald_status_t ald_spi_send_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout);
375 ald_status_t ald_spi_master_recv_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size);
376 ald_status_t ald_spi_slave_recv_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout);
383 ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
384 ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
385 ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout);
386 ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size);
387 ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size);
388 ald_status_t ald_spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size);
389 #ifdef ALD_DMA
390 ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
391 ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
392 ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel);
393 ald_status_t ald_spi_dma_pause(spi_handle_t *hperh);
394 ald_status_t ald_spi_dma_resume(spi_handle_t *hperh);
395 ald_status_t ald_spi_dma_stop(spi_handle_t *hperh);
396 #endif
397
403 void ald_spi_irq_handler(spi_handle_t *hperh);
404 void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state);
405 void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed);
406 void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state);
407 it_status_t ald_spi_get_it_status(spi_handle_t *hperh, spi_it_t it);
408 flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status);
409 flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag);
410 void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag);
417 spi_state_t ald_spi_get_state(spi_handle_t *hperh);
418 uint32_t ald_spi_get_error(spi_handle_t *hperh);
431 #ifdef __cplusplus
432 }
433 #endif
434 #endif
SPI_STATE_BUSY
Definition: ald_spi.h:146
ald_spi_dma_resume
ald_status_t ald_spi_dma_resume(spi_handle_t *hperh)
Resumes the DMA Transfer.
Definition: ald_spi.c:1224
SPI_ERROR_FLAG
Definition: ald_spi.h:103
spi_firstbit_t
spi_firstbit_t
frame format
Definition: ald_spi.h:80
SPI_IT_TXTH
Definition: ald_spi.h:113
SPI_STATE_TIMEOUT
Definition: ald_spi.h:150
SPI_STATUS_TXE
Definition: ald_spi.h:185
SPI_STATUS_TXOV
Definition: ald_spi.h:187
spi_init_t
SPI init structure definition.
Definition: ald_spi.h:211
ald_spi_get_it_status
it_status_t ald_spi_get_it_status(spi_handle_t *hperh, spi_it_t it)
Checks whether the specified SPI interrupt has occurred or not.
Definition: ald_spi.c:1448
SPI_FRAME_TI
Definition: ald_spi.h:178
spi_handle_s::rx_buf
uint8_t * rx_buf
Definition: ald_spi.h:234
spi_state_t
spi_state_t
SPI state structures definition.
Definition: ald_spi.h:143
SPI_MODE_MASTER
Definition: ald_spi.h:60
spi_init_t::first_bit
spi_firstbit_t first_bit
Definition: ald_spi.h:218
dma_handle_t
DMA handle structure definition.
Definition: ald_dma.h:297
ald_spi_send_recv_by_it
ald_status_t ald_spi_send_recv_by_it(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size)
Transmit and Receives an amount of data in non blocking mode.
Definition: ald_spi.c:939
SPI_STATE_BUSY_TX_RX
Definition: ald_spi.h:149
SPI_ERROR_CRC
Definition: ald_spi.h:99
SPI_ERROR_RXOV
Definition: ald_spi.h:101
SPI_CPOL_HIGH
Definition: ald_spi.h:52
SPI_CPHA_FIRST
Definition: ald_spi.h:43
spi_init_t::crc_poly
uint16_t crc_poly
Definition: ald_spi.h:222
SPI_IT_CRCERR
Definition: ald_spi.h:118
SPI_STATUS_RXF
Definition: ald_spi.h:191
ald_spi_interrupt_config
void ald_spi_interrupt_config(spi_handle_t *hperh, spi_it_t it, type_func_t state)
Enables or disables the specified SPI interrupts.
Definition: ald_spi.c:1354
spi_handle_s::tx_buf
uint8_t * tx_buf
Definition: ald_spi.h:231
ald_spi_send_byte_fast
int32_t ald_spi_send_byte_fast(spi_handle_t *hperh, uint8_t data)
Transmit one byte fast in blocking mode.
Definition: ald_spi.c:254
type_func_t
type_func_t
Definition: type.h:47
SPI_DMA_REQ_RX
Definition: ald_spi.h:170
spi_handle_s::tx_count
uint16_t tx_count
Definition: ald_spi.h:233
spi_init_t::ss_en
type_func_t ss_en
Definition: ald_spi.h:219
ald_spi_recv_byte_fast
uint8_t ald_spi_recv_byte_fast(spi_handle_t *hperh, int *status)
Receive one byte fast in blocking mode.
Definition: ald_spi.c:293
SPI_BAUD_256
Definition: ald_spi.h:74
spi_init_t::crc_calc
type_func_t crc_calc
Definition: ald_spi.h:220
SPI_BAUD_128
Definition: ald_spi.h:73
spi_handle_s::tx_rx_cplt_cbk
void(* tx_rx_cplt_cbk)(struct spi_handle_s *arg)
Definition: ald_spi.h:247
SPI_ERROR_MODF
Definition: ald_spi.h:98
SPI_IF_RXF
Definition: ald_spi.h:131
ald_spi_master_recv_dbytes_fast
ald_status_t ald_spi_master_recv_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size)
Receive some double-bytes fast in blocking mode.
Definition: ald_spi.c:441
SPI_IF_TXOV
Definition: ald_spi.h:128
ald_spi_get_flag_status
flag_status_t ald_spi_get_flag_status(spi_handle_t *hperh, spi_flag_t flag)
Check whether the specified SPI flag is set or not.
Definition: ald_spi.c:1467
SPI_ERROR_TXOV
Definition: ald_spi.h:102
spi_error_t
spi_error_t
SPI error status.
Definition: ald_spi.h:96
SPI_FIRSTBIT_MSB
Definition: ald_spi.h:81
spi_handle_s::err_cbk
void(* err_cbk)(struct spi_handle_s *arg)
Definition: ald_spi.h:248
SPI_STATE_RESET
Definition: ald_spi.h:144
SPI_IT_TXE
Definition: ald_spi.h:110
spi_flag_t
spi_flag_t
interrupt flag
Definition: ald_spi.h:126
SPI_DIRECTION_2LINES_RXONLY
Definition: ald_spi.h:160
spi_init_t::phase
spi_cpha_t phase
Definition: ald_spi.h:216
SPI_STATE_BUSY_RX
Definition: ald_spi.h:148
SPI_DIRECTION_2LINES
Definition: ald_spi.h:159
ald_spi_clear_flag_status
void ald_spi_clear_flag_status(spi_handle_t *hperh, spi_flag_t flag)
Clear the specified SPI pending flags.
Definition: ald_spi.c:1484
ald_spi_send_dbytes_fast
ald_status_t ald_spi_send_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Transmit some double-bytes fast in blocking mode.
Definition: ald_spi.c:406
utils.h
This file contains the Utilities functions/types for the driver.
SPI_STATUS_TXUD
Definition: ald_spi.h:188
spi_baud_t
spi_baud_t
baud rate control
Definition: ald_spi.h:66
ald_spi_dma_pause
ald_status_t ald_spi_dma_pause(spi_handle_t *hperh)
Pauses the DMA Transfer.
Definition: ald_spi.c:1207
SPI_CPOL_LOW
Definition: ald_spi.h:51
ald_spi_get_error
uint32_t ald_spi_get_error(spi_handle_t *hperh)
Return the SPI error code.
Definition: ald_spi.c:1574
spi_it_t
spi_it_t
interrupt control
Definition: ald_spi.h:109
it_status_t
enum flag_status_t it_status_t
SPI_FRAME_MOTOROLA
Definition: ald_spi.h:177
SPI_IT_RXUD
Definition: ald_spi.h:116
SPI_STATUS_RXOV
Definition: ald_spi.h:192
spi_datasize_t
spi_datasize_t
data frame format
Definition: ald_spi.h:88
ald_spi_send_recv_by_dma
ald_status_t ald_spi_send_recv_by_dma(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel)
Transmit and Receive an amount of data used dma channel.
Definition: ald_spi.c:1134
SPI_DIRECTION_1LINE_RX
Definition: ald_spi.h:162
SPI_BAUD_16
Definition: ald_spi.h:70
SPI_MODE_SLAVER
Definition: ald_spi.h:59
SPI_STATUS_RXTH
Definition: ald_spi.h:194
SPI_CPHA_SECOND
Definition: ald_spi.h:44
spi_handle_s
SPI handle structure definition.
Definition: ald_spi.h:228
spi_handle_s::init
spi_init_t init
Definition: ald_spi.h:230
SPI_IF_RXOV
Definition: ald_spi.h:132
SPI_STATE_BUSY_TX
Definition: ald_spi.h:147
ald_spi_dma_req_config
void ald_spi_dma_req_config(spi_handle_t *hperh, spi_dma_req_t req, type_func_t state)
Enables or disables the dma request.
Definition: ald_spi.c:1398
spi_frame_t
spi_frame_t
SPI crc length definition.
Definition: ald_spi.h:176
ald_spi_send_recv
ald_status_t ald_spi_send_recv(spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout)
Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
Definition: ald_spi.c:706
SPI_IT_FRE
Definition: ald_spi.h:120
spi_init_t::polarity
spi_cpol_t polarity
Definition: ald_spi.h:217
SPI_DMA_REQ_TX
Definition: ald_spi.h:169
spi_handle_s::perh
SPI_I2S_TypeDef * perh
Definition: ald_spi.h:229
spi_status_t
spi_status_t
SPI status definition.
Definition: ald_spi.h:184
spi_get_status
flag_status_t spi_get_status(spi_handle_t *hperh, spi_status_t status)
Check whether the specified SPI state flag is set or not.
Definition: ald_spi.c:1428
spi_handle_s::state
spi_state_t state
Definition: ald_spi.h:242
SPI_STATUS_RXUD
Definition: ald_spi.h:193
lock_state_t
lock_state_t
Definition: type.h:58
spi_cpol_t
spi_cpol_t
clock polarity
Definition: ald_spi.h:50
SPI_IF_CRCERR
Definition: ald_spi.h:135
spi_cpha_t
spi_cpha_t
clock phase
Definition: ald_spi.h:42
spi_init_t::baud
spi_baud_t baud
Definition: ald_spi.h:215
ald_dma.h
DMA module Library.
SPI_IT_RXF
Definition: ald_spi.h:114
ald_spi_slave_recv_bytes_fast
ald_status_t ald_spi_slave_recv_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Receive some bytes fast in blocking mode.
Definition: ald_spi.c:379
SPI_BAUD_64
Definition: ald_spi.h:72
spi_direction_t
spi_direction_t
SPI direction definition.
Definition: ald_spi.h:158
SPI_DIRECTION_1LINE
Definition: ald_spi.h:161
SPI_IF_RXUD
Definition: ald_spi.h:133
SPI_STATE_ERROR
Definition: ald_spi.h:151
ald_spi_irq_handler
void ald_spi_irq_handler(spi_handle_t *hperh)
This function handles SPI interrupt request.
Definition: ald_spi.c:1284
spi_mode_t
spi_mode_t
master selection
Definition: ald_spi.h:58
ald_spi_send_bytes_fast
ald_status_t ald_spi_send_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Transmit some bytes fast in blocking mode.
Definition: ald_spi.c:318
SPI_STATUS_TXF
Definition: ald_spi.h:186
ald_spi_send
ald_status_t ald_spi_send(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Transmit an amount of data in blocking mode.
Definition: ald_spi.c:532
ald_spi_send_by_dma
ald_status_t ald_spi_send_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
Transmit an amount of data used dma channel.
Definition: ald_spi.c:984
SPI_BAUD_2
Definition: ald_spi.h:67
SPI_BAUD_8
Definition: ald_spi.h:69
spi_handle_s::rx_cplt_cbk
void(* rx_cplt_cbk)(struct spi_handle_s *arg)
Definition: ald_spi.h:246
spi_dma_req_t
spi_dma_req_t
SPI dma request definition.
Definition: ald_spi.h:168
SPI_IF_TXE
Definition: ald_spi.h:127
ald_spi_reset
void ald_spi_reset(spi_handle_t *hperh)
Reset the SPI peripheral.
Definition: ald_spi.c:131
spi_handle_s::tx_size
uint16_t tx_size
Definition: ald_spi.h:232
spi_init_t::mode
spi_mode_t mode
Definition: ald_spi.h:212
spi_handle_s::hdmarx
dma_handle_t hdmarx
Definition: ald_spi.h:239
SPI_SR_TXE_RXNE
Definition: ald_spi.h:204
ald_spi_recv_by_it
ald_status_t ald_spi_recv_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size)
Receives an amount of data in non blocking mode.
Definition: ald_spi.c:886
SPI_IT_TXOV
Definition: ald_spi.h:111
SPI_BAUD_4
Definition: ald_spi.h:68
ald_spi_dma_stop
ald_status_t ald_spi_dma_stop(spi_handle_t *hperh)
Stops the DMA Transfer.
Definition: ald_spi.c:1241
SPI_IF_TXUD
Definition: ald_spi.h:129
SPI_STATUS_RXE
Definition: ald_spi.h:190
spi_handle_s::hdmatx
dma_handle_t hdmatx
Definition: ald_spi.h:238
spi_init_t::dir
spi_direction_t dir
Definition: ald_spi.h:213
SPI_BAUD_32
Definition: ald_spi.h:71
ald_spi_master_recv_bytes_fast
ald_status_t ald_spi_master_recv_bytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size)
Receive some bytes fast in blocking mode.
Definition: ald_spi.c:352
SPI_STATE_READY
Definition: ald_spi.h:145
spi_init_t::data_size
spi_datasize_t data_size
Definition: ald_spi.h:214
spi_init_t::frame
spi_frame_t frame
Definition: ald_spi.h:221
flag_status_t
flag_status_t
Definition: type.h:37
spi_handle_t
struct spi_handle_s spi_handle_t
SPI handle structure definition.
ald_spi_init
ald_status_t ald_spi_init(spi_handle_t *hperh)
Initializes the SPI mode according to the specified parameters in the SPI_init_t and create the assoc...
Definition: ald_spi.c:150
SPI_IF_TXTH
Definition: ald_spi.h:130
spi_handle_s::err_code
uint32_t err_code
Definition: ald_spi.h:243
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
SPI_SR_RXNE
Definition: ald_spi.h:203
SPI_IF_RXTH
Definition: ald_spi.h:134
spi_handle_s::rx_size
uint16_t rx_size
Definition: ald_spi.h:235
SPI_FIRSTBIT_LSB
Definition: ald_spi.h:82
spi_sr_status_t
spi_sr_status_t
SPI TXE/RXNE status definition.
Definition: ald_spi.h:201
SPI_IT_MODF
Definition: ald_spi.h:119
ald_spi_recv_by_dma
ald_status_t ald_spi_recv_by_dma(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
Receive an amount of data used dma channel.
Definition: ald_spi.c:1047
ald_spi_recv
ald_status_t ald_spi_recv(spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Receive an amount of data in blocking mode.
Definition: ald_spi.c:624
ald_spi_get_state
spi_state_t ald_spi_get_state(spi_handle_t *hperh)
Returns the SPI state.
Definition: ald_spi.c:1563
SPI_DATA_SIZE_16
Definition: ald_spi.h:90
SPI_IT_TXUD
Definition: ald_spi.h:112
SPI_DATA_SIZE_8
Definition: ald_spi.h:89
spi_handle_s::rx_count
uint16_t rx_count
Definition: ald_spi.h:236
SPI_ERROR_NONE
Definition: ald_spi.h:97
SPI_IT_RXTH
Definition: ald_spi.h:117
SPI_IT_RXOV
Definition: ald_spi.h:115
SPI_IF_MODF
Definition: ald_spi.h:136
spi_handle_s::lock
lock_state_t lock
Definition: ald_spi.h:241
ald_spi_speed_config
void ald_spi_speed_config(spi_handle_t *hperh, spi_baud_t speed)
Configure the specified SPI speed.
Definition: ald_spi.c:1375
SPI_STATUS_BUSY
Definition: ald_spi.h:195
SPI_STATUS_TXTH
Definition: ald_spi.h:189
ald_spi_send_byte_fast_1line
int32_t ald_spi_send_byte_fast_1line(spi_handle_t *hperh, uint8_t data)
Transmit one byte fast in blocking mode(1line).
Definition: ald_spi.c:277
ald_spi_slave_recv_dbytes_fast
ald_status_t ald_spi_slave_recv_dbytes_fast(spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout)
Receive some double-bytes fast in blocking mode.
Definition: ald_spi.c:471
ald_spi_send_by_it
ald_status_t ald_spi_send_by_it(spi_handle_t *hperh, uint8_t *buf, uint16_t size)
Wraps up transmission in non blocking mode.
Definition: ald_spi.c:850
SPI_ERROR_FRE
Definition: ald_spi.h:100
SPI_IF_FRE
Definition: ald_spi.h:137
spi_handle_s::tx_cplt_cbk
void(* tx_cplt_cbk)(struct spi_handle_s *arg)
Definition: ald_spi.h:245
SPI_SR_TXE
Definition: ald_spi.h:202


ALD User Manual: D:/svn/src/ald_sram.c Source File

  • D:
  • svn
  • src
ald_sram.c
Go to the documentation of this file.
1
16 #include "ald_sram.h"
17
27 #ifdef ALD_SRAM
28
43 ald_status_t ald_sram_init(sram_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing)
44 {
45 if (hperh == NULL)
46 return ERROR;
47
48 if (hperh->state == ALD_SRAM_STATE_RESET)
49 hperh->lock = UNLOCK;
50
51 /* Initialize SRAM control Interface */
52 ald_ebi_nor_sram_init(hperh->instance, &(hperh->init));
53 /* Initialize SRAM timing Interface */
54 ald_ebi_nor_sram_timing_init(hperh->instance, timing, hperh->init.bank);
55 /* Initialize SRAM extended mode timing Interface */
56 ald_ebi_nor_sram_ext_timing_init(hperh->ext, ext_timing, hperh->init.bank, hperh->init.ext_mode);
57 /* Enable the NORSRAM device */
58 ald_ebi_nor_sram_enable(hperh->instance, hperh->init.bank);
59
60 return OK;
61 }
62
68 ald_status_t ald_sram_deinit(sram_handle_t *hperh)
69 {
70 ald_ebi_nor_sram_deinit(hperh->instance, hperh->ext, hperh->init.bank);
71 hperh->state = ALD_SRAM_STATE_RESET;
72 __UNLOCK(hperh);
73
74 return OK;
75 }
92 ald_status_t ald_sram_read_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size)
93 {
94 __IO uint8_t * psramaddr = (uint8_t *)addr;
95
96 __LOCK(hperh);
97 hperh->state = ALD_SRAM_STATE_BUSY;
98
99 /* Read data from memory */
100 for (; size != 0U; size--)
101 *buf++ = *(__IO uint8_t *)psramaddr++;
102
103 hperh->state = ALD_SRAM_STATE_READY;
104 __UNLOCK(hperh);
105
106 return OK;
107 }
108
117 ald_status_t ald_sram_write_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size)
118 {
119 __IO uint8_t * psramaddr = (uint8_t *)addr;
120
121 if (hperh->state == ALD_SRAM_STATE_PROTECTED)
122 return ERROR;
123
124 __LOCK(hperh);
125 hperh->state = ALD_SRAM_STATE_BUSY;
126
127 /* Write data to memory */
128 for (; size != 0U; size--)
129 *(__IO uint8_t *)psramaddr++ = *buf++;
130
131 hperh->state = ALD_SRAM_STATE_READY;
132 __UNLOCK(hperh);
133
134 return OK;
135 }
136
146 ald_status_t ald_sram_read_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size)
147 {
148 __IO uint16_t * psramaddr = (uint16_t *)addr;
149
150 __LOCK(hperh);
151 hperh->state = ALD_SRAM_STATE_BUSY;
152
153 /* Read data from memory */
154 for (; size != 0U; size--)
155 *buf++ = *(__IO uint16_t *)psramaddr++;
156
157 hperh->state = ALD_SRAM_STATE_READY;
158 __UNLOCK(hperh);
159
160 return OK;
161 }
162
172 ald_status_t ald_sram_write_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size)
173 {
174 __IO uint16_t * psramaddr = (uint16_t *)addr;
175
176 if (hperh->state == ALD_SRAM_STATE_PROTECTED)
177 return ERROR;
178
179 __LOCK(hperh);
180 hperh->state = ALD_SRAM_STATE_BUSY;
181
182 /* Write data to memory */
183 for (; size != 0U; size--)
184 *(__IO uint16_t *)psramaddr++ = *buf++;
185
186 hperh->state = ALD_SRAM_STATE_READY;
187 __UNLOCK(hperh);
188
189 return OK;
190 }
191
200 ald_status_t ald_sram_read_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size)
201 {
202 __LOCK(hperh);
203 hperh->state = ALD_SRAM_STATE_BUSY;
204
205 /* Read data from memory */
206 for (; size != 0U; size--)
207 *buf++ = *(__IO uint32_t *)addr++;
208
209 hperh->state = ALD_SRAM_STATE_READY;
210 __UNLOCK(hperh);
211
212 return OK;
213 }
214
224 ald_status_t ald_sram_write_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size)
225 {
226 if (hperh->state == ALD_SRAM_STATE_PROTECTED)
227 return ERROR;
228
229 __LOCK(hperh);
230 hperh->state = ALD_SRAM_STATE_BUSY;
231
232 /* Write data to memory */
233 for (; size != 0U; size--)
234 *(__IO uint32_t *)addr++ = *buf++;
235
236 hperh->state = ALD_SRAM_STATE_READY;
237 __UNLOCK(hperh);
238
239 return OK;
240 }
241
242 #ifdef ALD_DMA
243
253 ald_status_t ald_sram_read_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch)
254 {
255 if (buf == NULL)
256 return ERROR;
257
258 hperh->hdma.perh = DMA0;
259 hperh->hdma.cplt_cbk = hperh->cplt_cbk;
260 ald_dma_config_struct(&hperh->hdma.config);
261
262 hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD;
263 hperh->hdma.config.src = (void *)addr;
264 hperh->hdma.config.dst = (void *)buf;
265 hperh->hdma.config.size = size;
266 hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD;
267 hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD;
268 hperh->hdma.config.msel = DMA_MSEL_NONE;
269 hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE;
270 hperh->hdma.config.channel = ch;
271 hperh->hdma.config.R_power = DMA_R_POWER_4;
272 hperh->hdma.config.burst = ENABLE;
273
274 ald_dma_config_auto(&hperh->hdma);
275 return OK;
276 }
277
288 ald_status_t ald_sram_write_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch)
289 {
290 if (buf == NULL)
291 return ERROR;
292 ;
293 hperh->hdma.perh = DMA0;
294 hperh->hdma.cplt_cbk = hperh->cplt_cbk;
295 ald_dma_config_struct(&hperh->hdma.config);
296
297 hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD;
298 hperh->hdma.config.src = (void *)buf;
299 hperh->hdma.config.dst = (void *)addr;
300 hperh->hdma.config.size = size;
301 hperh->hdma.config.src_inc = DMA_DATA_INC_HALFWORD;
302 hperh->hdma.config.dst_inc = DMA_DATA_INC_HALFWORD;
303 hperh->hdma.config.msel = DMA_MSEL_NONE;
304 hperh->hdma.config.msigsel = DMA_MSIGSEL_NONE;
305 hperh->hdma.config.channel = ch;
306 hperh->hdma.config.R_power = DMA_R_POWER_4;
307 hperh->hdma.config.burst = ENABLE;
308
309 ald_dma_config_auto(&hperh->hdma);
310 return OK;
311 }
312 #endif
313
326 ald_status_t ald_sram_write_enable(sram_handle_t *hperh)
327 {
328 __LOCK(hperh);
329 ald_ebi_nor_sram_write_enable(hperh->instance, hperh->init.bank);
330 hperh->state = ALD_SRAM_STATE_READY;
331 __UNLOCK(hperh);
332
333 return OK;
334 }
335
341 ald_status_t ald_sram_write_disable(sram_handle_t *hperh)
342 {
343 __LOCK(hperh);
344 hperh->state = ALD_SRAM_STATE_BUSY;
345 ald_ebi_nor_sram_write_disable(hperh->instance, hperh->init.bank);
346 hperh->state = ALD_SRAM_STATE_PROTECTED;
347 __UNLOCK(hperh);
348
349 return OK;
350 }
364 ald_sram_state_t ald_sram_get_state(sram_handle_t *hperh)
365 {
366 return hperh->state;
367 }
374 #endif /* ALD_SRAM */
375
DMA_R_POWER_4
Definition: ald_dma.h:253
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ENABLE
Definition: type.h:49
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
DMA_MSEL_NONE
Definition: ald_dma.h:78
dma_config_t::R_power
dma_arbiter_config_t R_power
Definition: ald_dma.h:284
sram_handle_t::lock
lock_state_t lock
Definition: ald_sram.h:57
ald_sram_read_8b
ald_status_t ald_sram_read_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size)
Reads 8-bit buffer from SRAM memory.
Definition: ald_sram.c:92
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
ALD_SRAM_STATE_PROTECTED
Definition: ald_sram.h:47
sram_handle_t::instance
EBI_NOR_SRAM_TypeDef * instance
Definition: ald_sram.h:54
ald_sram_write_disable
ald_status_t ald_sram_write_disable(sram_handle_t *hperh)
Disables dynamically SRAM write operation.
Definition: ald_sram.c:341
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
ald_ebi_nor_sram_deinit
ald_status_t ald_ebi_nor_sram_deinit(EBI_NOR_SRAM_TypeDef *dev, EBI_NOR_SRAM_EXTENDED_TypeDef *e_dev, uint32_t bank)
DeInitialize the EBI_NOR_SRAM peripheral.
Definition: ald_ebi.c:172
ald_sram_get_state
ald_sram_state_t ald_sram_get_state(sram_handle_t *hperh)
Returns the SRAM controller state.
Definition: ald_sram.c:364
dma_config_t::src
void * src
Definition: ald_dma.h:278
sram_handle_t::hdma
dma_handle_t hdma
Definition: ald_sram.h:60
ald_sram_write_by_dma
ald_status_t ald_sram_write_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch)
Write a halfwords data to the SRAM memory using DMA transfer.
Definition: ald_sram.c:288
UNLOCK
Definition: type.h:59
sram_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_sram.h:56
ald_sram_read_by_dma
ald_status_t ald_sram_read_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch)
Reads a halfwords data from the SRAM memory using DMA transfer.
Definition: ald_sram.c:253
ald_ebi_nor_sram_init_t::ext_mode
ebi_extended_mode_t ext_mode
Definition: ald_ebi.h:409
ald_ebi_nor_sram_write_enable
void ald_ebi_nor_sram_write_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Enables dynamically NOR-FLASH/SRAM write operation.
Definition: ald_ebi.c:234
ALD_SRAM_STATE_READY
Definition: ald_sram.h:44
ALD_SRAM_STATE_BUSY
Definition: ald_sram.h:45
ald_ebi_nor_sram_timing_init
void ald_ebi_nor_sram_timing_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank)
Initialize the EBI_NOR_SRAM Timing according to the specified parameters in the EBI_NOR_SRAM_TimingTy...
Definition: ald_ebi.c:104
sram_handle_t
SRAM handle Structure definition.
Definition: ald_sram.h:53
ald_sram_write_32b
ald_status_t ald_sram_write_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size)
Writes 32-bit buffer to SRAM memory.
Definition: ald_sram.c:224
ALD_SRAM_STATE_RESET
Definition: ald_sram.h:43
ald_sram.h
Header file of EBI_SRAM driver.
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
ald_ebi_nor_sram_write_disable
void ald_ebi_nor_sram_write_disable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Disables dynamically EBI_NORSRAM write operation.
Definition: ald_ebi.c:249
ald_sram_write_16b
ald_status_t ald_sram_write_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size)
Writes 16-bit buffer to SRAM memory.
Definition: ald_sram.c:172
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
ald_sram_read_16b
ald_status_t ald_sram_read_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size)
Reads 16-bit buffer from SRAM memory.
Definition: ald_sram.c:146
ald_sram_write_enable
ald_status_t ald_sram_write_enable(sram_handle_t *hperh)
Enables dynamically SRAM write operation.
Definition: ald_sram.c:326
ald_sram_write_8b
ald_status_t ald_sram_write_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size)
Writes 8-bit buffer to SRAM memory.
Definition: ald_sram.c:117
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
ald_sram_read_32b
ald_status_t ald_sram_read_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size)
Reads 32-bit buffer from SRAM memory.
Definition: ald_sram.c:200
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
ald_ebi_nor_sram_init
void ald_ebi_nor_sram_init(EBI_NOR_SRAM_TypeDef *dev, ald_ebi_nor_sram_init_t *init)
Initialize the EBI_NOR_SRAM device according to the specified control parameters in the EBI_NOR_SRAM_...
Definition: ald_ebi.c:43
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
sram_handle_t::state
__IO ald_sram_state_t state
Definition: ald_sram.h:58
DMA_MSIGSEL_NONE
Definition: ald_dma.h:115
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
ald_sram_init
ald_status_t ald_sram_init(sram_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing)
Performs the SRAM device initialization sequence.
Definition: ald_sram.c:43
ald_sram_deinit
ald_status_t ald_sram_deinit(sram_handle_t *hperh)
Performs the SRAM device De-initialization sequence.
Definition: ald_sram.c:68
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
ald_sram_state_t
ald_sram_state_t
ALD SRAM State structures definition.
Definition: ald_sram.h:42
ald_dma_config_auto
void ald_dma_config_auto(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is automatic. This mode is used to carry data from memory to memory.
Definition: ald_dma.c:392
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
__LOCK
#define __LOCK(x)
Definition: utils.h:92
ald_ebi_nor_sram_timing_t
EBI NORSRAM Timing parameters structure definition.
Definition: ald_ebi.h:109
ERROR
Definition: utils.h:56
sram_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_sram.h:61
sram_handle_t::ext
EBI_NOR_SRAM_EXTENDED_TypeDef * ext
Definition: ald_sram.h:55
ald_ebi_nor_sram_init_t::bank
uint32_t bank
Definition: ald_ebi.h:399
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_ebi_nor_sram_enable
void ald_ebi_nor_sram_enable(EBI_NOR_SRAM_TypeDef *dev, uint32_t bank)
Enable the NOR/SRAM device access.
Definition: ald_ebi.c:206
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
ald_ebi_nor_sram_ext_timing_init
void ald_ebi_nor_sram_ext_timing_init(EBI_NOR_SRAM_EXTENDED_TypeDef *dev, ald_ebi_nor_sram_timing_t *timing, uint32_t bank, uint32_t mode)
Initialize the EBI_NOR_SRAM Extended mode Timing according to the specified parameters in the EBI_NOR...
Definition: ald_ebi.c:138


ALD User Manual: D:/svn/src/ald_sram.h Source File

  • D:
  • svn
  • src
ald_sram.h
Go to the documentation of this file.
1
17 #ifndef __ALD_SRAM_H__
18 #define __ALD_SRAM_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "ald_ebi.h"
25 #include "ald_dma.h"
26
42 typedef enum {
43 ALD_SRAM_STATE_RESET = 0x00U,
44 ALD_SRAM_STATE_READY = 0x01U,
45 ALD_SRAM_STATE_BUSY = 0x02U,
46 ALD_SRAM_STATE_ERROR = 0x03U,
47 ALD_SRAM_STATE_PROTECTED = 0x04U
48 } ald_sram_state_t;
49
53 typedef struct {
54 EBI_NOR_SRAM_TypeDef *instance;
55 EBI_NOR_SRAM_EXTENDED_TypeDef *ext;
56 ald_ebi_nor_sram_init_t init;
57 lock_state_t lock;
58 __IO ald_sram_state_t state;
59 #ifdef ALD_DMA
60 dma_handle_t hdma;
61 void(*cplt_cbk)(void *arg);
62 #endif
63 } sram_handle_t;
74 /* Initialization functions */
75 ald_status_t ald_sram_init(sram_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing);
76 ald_status_t ald_sram_deinit(sram_handle_t *hperh);
83 /* I/O operation functions */
84 ald_status_t ald_sram_read_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size);
85 ald_status_t ald_sram_write_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size);
86 ald_status_t ald_sram_read_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size);
87 ald_status_t ald_sram_write_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size);
88 ald_status_t ald_sram_read_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size);
89 ald_status_t ald_sram_write_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size);
90 #ifdef ALD_DMA
91 ald_status_t ald_sram_read_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch);
92 ald_status_t ald_sram_write_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch);
93 #endif
94
100 /* Control functions */
101 ald_status_t ald_sram_write_enable(sram_handle_t *hperh);
102 ald_status_t ald_sram_write_disable(sram_handle_t *hperh);
109 /* State functions */
110 ald_sram_state_t ald_sram_get_state(sram_handle_t *hperh);
123 #ifdef __cplusplus
124 }
125 #endif
126 #endif /* __ALD_SRAM_H__ */
dma_handle_t
DMA handle structure definition.
Definition: ald_dma.h:297
EBI_NOR_SRAM_TypeDef
#define EBI_NOR_SRAM_TypeDef
Definition: ald_ebi.h:40
sram_handle_t::lock
lock_state_t lock
Definition: ald_sram.h:57
EBI_NOR_SRAM_EXTENDED_TypeDef
#define EBI_NOR_SRAM_EXTENDED_TypeDef
Definition: ald_ebi.h:41
ald_sram_read_8b
ald_status_t ald_sram_read_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size)
Reads 8-bit buffer from SRAM memory.
Definition: ald_sram.c:92
ALD_SRAM_STATE_ERROR
Definition: ald_sram.h:46
ALD_SRAM_STATE_PROTECTED
Definition: ald_sram.h:47
sram_handle_t::instance
EBI_NOR_SRAM_TypeDef * instance
Definition: ald_sram.h:54
ald_sram_write_disable
ald_status_t ald_sram_write_disable(sram_handle_t *hperh)
Disables dynamically SRAM write operation.
Definition: ald_sram.c:341
ald_sram_get_state
ald_sram_state_t ald_sram_get_state(sram_handle_t *hperh)
Returns the SRAM controller state.
Definition: ald_sram.c:364
ald_ebi_nor_sram_init_t
EBI NORSRAM Configuration Structure definition.
Definition: ald_ebi.h:398
sram_handle_t::hdma
dma_handle_t hdma
Definition: ald_sram.h:60
ald_sram_write_by_dma
ald_status_t ald_sram_write_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch)
Write a halfwords data to the SRAM memory using DMA transfer.
Definition: ald_sram.c:288
sram_handle_t::init
ald_ebi_nor_sram_init_t init
Definition: ald_sram.h:56
ald_sram_read_by_dma
ald_status_t ald_sram_read_by_dma(sram_handle_t *hperh, uint16_t *addr, uint16_t *buf, uint16_t size, uint8_t ch)
Reads a halfwords data from the SRAM memory using DMA transfer.
Definition: ald_sram.c:253
ALD_SRAM_STATE_READY
Definition: ald_sram.h:44
ALD_SRAM_STATE_BUSY
Definition: ald_sram.h:45
sram_handle_t
SRAM handle Structure definition.
Definition: ald_sram.h:53
ald_sram_write_32b
ald_status_t ald_sram_write_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size)
Writes 32-bit buffer to SRAM memory.
Definition: ald_sram.c:224
ALD_SRAM_STATE_RESET
Definition: ald_sram.h:43
lock_state_t
lock_state_t
Definition: type.h:58
ald_dma.h
DMA module Library.
ald_sram_write_16b
ald_status_t ald_sram_write_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size)
Writes 16-bit buffer to SRAM memory.
Definition: ald_sram.c:172
ald_sram_read_16b
ald_status_t ald_sram_read_16b(sram_handle_t *hperh, uint32_t *addr, uint16_t *buf, uint32_t size)
Reads 16-bit buffer from SRAM memory.
Definition: ald_sram.c:146
ald_sram_write_enable
ald_status_t ald_sram_write_enable(sram_handle_t *hperh)
Enables dynamically SRAM write operation.
Definition: ald_sram.c:326
ald_sram_write_8b
ald_status_t ald_sram_write_8b(sram_handle_t *hperh, uint32_t *addr, uint8_t *buf, uint32_t size)
Writes 8-bit buffer to SRAM memory.
Definition: ald_sram.c:117
ald_sram_read_32b
ald_status_t ald_sram_read_32b(sram_handle_t *hperh, uint32_t *addr, uint32_t *buf, uint32_t size)
Reads 32-bit buffer from SRAM memory.
Definition: ald_sram.c:200
sram_handle_t::state
__IO ald_sram_state_t state
Definition: ald_sram.h:58
ald_ebi.h
Header file of EBI module driver.
ald_sram_init
ald_status_t ald_sram_init(sram_handle_t *hperh, ald_ebi_nor_sram_timing_t *timing, ald_ebi_nor_sram_timing_t *ext_timing)
Performs the SRAM device initialization sequence.
Definition: ald_sram.c:43
ald_sram_deinit
ald_status_t ald_sram_deinit(sram_handle_t *hperh)
Performs the SRAM device De-initialization sequence.
Definition: ald_sram.c:68
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
ald_sram_state_t
ald_sram_state_t
ALD SRAM State structures definition.
Definition: ald_sram.h:42
ald_ebi_nor_sram_timing_t
EBI NORSRAM Timing parameters structure definition.
Definition: ald_ebi.h:109
sram_handle_t::ext
EBI_NOR_SRAM_EXTENDED_TypeDef * ext
Definition: ald_sram.h:55


ALD User Manual: D:/svn/src/ald_syscfg.h Source File

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  • svn
  • src
ald_syscfg.h
Go to the documentation of this file.
1
17 #ifndef __ALD_SYSCFG_H__
18 #define __ALD_SYSCFG_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25
26
39 #define SYSCFG_LOCK() WRITE_REG(SYSCFG->PROT, 0x0U)
40 #define SYSCFG_UNLOCK() WRITE_REG(SYSCFG->PROT, 0x55AA6996U)
41 #define GET_SYSCFG_LOCK() READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK)
42
43 #define SYSCFG_BOOTFLASH_MAPPING_ENABLE() SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK)
44 #define SYSCFG_BOOTFLASH_MAPPING_DISABLE() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK)
45
58 __STATIC_INLINE__ void ald_vtor_config(uint32_t offset, type_func_t status)
59 {
60 SCB->VTOR = status ? (offset & ~0x3FU) : 0;
61 return;
62 }
73 #ifdef __cplusplus
74 }
75 #endif
76
77 #endif
type_func_t
type_func_t
Definition: type.h:47
utils.h
This file contains the Utilities functions/types for the driver.
__STATIC_INLINE__
#define __STATIC_INLINE__
Definition: type.h:32
ald_vtor_config
__STATIC_INLINE__ void ald_vtor_config(uint32_t offset, type_func_t status)
Set the offset of the interrup vector map.
Definition: ald_syscfg.h:58


ALD User Manual: D:/svn/src/ald_timer.c Source File

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  • svn
  • src
ald_timer.c
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1
18 #include <string.h>
19 #include "ald_timer.h"
20 #include "ald_cmu.h"
21
22
31 #ifdef ALD_TIMER
32
36 static void timer_base_set_config(TIMER_TypeDef *TIMERx, timer_base_init_t *init);
37 static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config);
38 static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config);
39 static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config);
40 static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config);
41 static void timer_ccx_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state);
42 static void timer_ccxn_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state);
43 static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity,
44 timer_ic_select_t sel, uint32_t filter);
45 static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter);
46 static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity,
47 timer_ic_select_t sel, uint32_t filter);
48 static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter);
49 static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity,
50 timer_ic_select_t sel, uint32_t filter);
51 static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity,
52 timer_ic_select_t sel, uint32_t filter);
53 static void timer_etr_set_config(TIMER_TypeDef* TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter);
54 static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t *config);
55 #ifdef ALD_DMA
56 static void timer_dma_oc_cplt(void *arg);
57 static void timer_dma_capture_cplt(void *arg);
58 static void timer_dma_period_elapse_cplt(void *arg);
59 static void timer_dma_error(void *arg);
60 static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config);
61 #endif
62
97 ald_status_t ald_timer_base_init(timer_handle_t *hperh)
98 {
99 if (hperh == NULL)
100 return ERROR;
101
102 assert_param(IS_TIMER_INSTANCE(hperh->perh));
103 assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode));
104 assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div));
105
106 if (hperh->state == TIMER_STATE_RESET)
107 hperh->lock = UNLOCK;
108
109 hperh->state = TIMER_STATE_BUSY;
110 timer_base_set_config(hperh->perh, &hperh->init);
111 hperh->state = TIMER_STATE_READY;
112
113 return OK;
114 }
115
121 void ald_timer_base_reset(timer_handle_t *hperh)
122 {
123 assert_param(IS_TIMER_INSTANCE(hperh->perh));
124
125 hperh->state = TIMER_STATE_BUSY;
126 TIMER_DISABLE(hperh);
127 hperh->state = TIMER_STATE_RESET;
128 __UNLOCK(hperh);
129
130 return;
131 }
132
138 void ald_timer_base_start(timer_handle_t *hperh)
139 {
140 assert_param(IS_TIMER_INSTANCE(hperh->perh));
141
142 hperh->state = TIMER_STATE_BUSY;
143 TIMER_ENABLE(hperh);
144 hperh->state = TIMER_STATE_READY;
145
146 return;
147 }
148
154 void ald_timer_base_stop(timer_handle_t *hperh)
155 {
156 assert_param(IS_TIMER_INSTANCE(hperh->perh));
157
158 hperh->state = TIMER_STATE_BUSY;
159 TIMER_DISABLE(hperh);
160 hperh->state = TIMER_STATE_READY;
161
162 return;
163 }
164
170 void ald_timer_base_start_by_it(timer_handle_t *hperh)
171 {
172 assert_param(IS_TIMER_INSTANCE(hperh->perh));
173
174 ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, ENABLE);
175 TIMER_ENABLE(hperh);
176
177 return;
178 }
179
185 void ald_timer_base_stop_by_it(timer_handle_t *hperh)
186 {
187 assert_param(IS_TIMER_INSTANCE(hperh->perh));
188
189 ald_timer_interrupt_config(hperh, TIMER_IT_UPDATE, DISABLE);
190 TIMER_DISABLE(hperh);
191
192 return;
193 }
194
195 #ifdef ALD_DMA
196
204 ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh,
205 uint16_t *buf, uint32_t len, uint8_t dma_ch)
206 {
207 assert_param(IS_TIMER_INSTANCE(hperh->perh));
208
209 if ((hperh->state == TIMER_STATE_BUSY))
210 return BUSY;
211 if ((hperh->state == TIMER_STATE_READY)) {
212 if (((uint32_t)buf == 0 ) || (len == 0))
213 return ERROR;
214 }
215
216 hperh->state = TIMER_STATE_BUSY;
217
218 if (hperh->hdma1.perh == NULL)
219 hperh->hdma1.perh = DMA0;
220
221 hperh->hdma1.cplt_cbk = timer_dma_period_elapse_cplt;
222 hperh->hdma1.cplt_arg = (void *)hperh;
223 hperh->hdma1.err_cbk = timer_dma_error;
224 hperh->hdma1.err_arg = (void *)hperh;
225
226 ald_dma_config_struct(&hperh->hdma1.config);
227 hperh->hdma1.config.src = (void *)buf;
228 hperh->hdma1.config.dst = (void *)&hperh->perh->AR;
229 hperh->hdma1.config.size = len;
230 hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD;
231 hperh->hdma1.config.src_inc = DMA_DATA_INC_HALFWORD;
232 hperh->hdma1.config.dst_inc = DMA_DATA_INC_NONE;
233 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_UPDATE;
234 hperh->hdma1.config.channel = dma_ch;
235
236 timer_dma_msel(hperh->perh, &hperh->hdma1.config);
237 ald_dma_config_basic(&hperh->hdma1);
238 ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, ENABLE);
239 TIMER_ENABLE(hperh);
240
241 return OK;
242 }
243
249 void ald_timer_base_stop_by_dma(timer_handle_t *hperh)
250 {
251 assert_param(IS_TIMER_INSTANCE(hperh->perh));
252
253 ald_timer_dma_req_config(hperh, TIMER_DMA_UPDATE, DISABLE);
254 TIMER_DISABLE(hperh);
255 hperh->state = TIMER_STATE_READY;
256
257 return;
258 }
259 #endif
260
290 ald_status_t ald_timer_oc_init(timer_handle_t *hperh)
291 {
292 return ald_timer_base_init(hperh);
293 }
294
306 void ald_timer_oc_start(timer_handle_t *hperh, timer_channel_t ch)
307 {
308 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
309
310 timer_ccx_channel_cmd(hperh->perh, ch, ENABLE);
311
312 if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
313 TIMER_MOE_ENABLE(hperh);
314
315 TIMER_ENABLE(hperh);
316 return;
317 }
318
330 void ald_timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch)
331 {
332 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
333
334 timer_ccx_channel_cmd(hperh->perh, ch, DISABLE);
335
336 if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
337 TIMER_MOE_DISABLE(hperh);
338
339 TIMER_DISABLE(hperh);
340 hperh->state = TIMER_STATE_READY;
341 return;
342 }
343
355 void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
356 {
357 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
358
359 switch (ch) {
360 case TIMER_CHANNEL_1:
361 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE);
362 break;
363
364 case TIMER_CHANNEL_2:
365 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE);
366 break;
367
368 case TIMER_CHANNEL_3:
369 ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE);
370 break;
371
372 case TIMER_CHANNEL_4:
373 ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE);
374 break;
375
376 default:
377 break;
378 }
379
380 timer_ccx_channel_cmd(hperh->perh, ch, ENABLE);
381
382 if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
383 TIMER_MOE_ENABLE(hperh);
384
385 TIMER_ENABLE(hperh);
386 return;
387 }
388
400 void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
401 {
402 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
403
404 switch (ch) {
405 case TIMER_CHANNEL_1:
406 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE);
407 break;
408
409 case TIMER_CHANNEL_2:
410 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE);
411 break;
412
413 case TIMER_CHANNEL_3:
414 ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE);
415 break;
416
417 case TIMER_CHANNEL_4:
418 ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE);
419 break;
420
421 default:
422 break;
423 }
424
425 timer_ccx_channel_cmd(hperh->perh, ch, DISABLE);
426
427 if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
428 TIMER_MOE_DISABLE(hperh);
429
430 TIMER_DISABLE(hperh);
431 hperh->state = TIMER_STATE_READY;
432 return;
433 }
434
435
436
437
438
439 #ifdef ALD_DMA
440
454 ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch,
455 uint16_t *buf, uint32_t len, uint8_t dma_ch)
456 {
457 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
458
459 if ((hperh->state == TIMER_STATE_BUSY))
460 return BUSY;
461 if ((hperh->state == TIMER_STATE_READY)) {
462 if (((uint32_t)buf == 0 ) || (len == 0))
463 return ERROR;
464 }
465
466 hperh->state = TIMER_STATE_BUSY;
467
468 if (hperh->hdma1.perh == NULL)
469 hperh->hdma1.perh = DMA0;
470
471 hperh->hdma1.cplt_cbk = timer_dma_oc_cplt;
472 hperh->hdma1.cplt_arg = (void *)hperh;
473 hperh->hdma1.err_cbk = timer_dma_error;
474 hperh->hdma1.err_arg = (void *)hperh;
475
476 ald_dma_config_struct(&hperh->hdma1.config);
477 hperh->hdma1.config.src = (void *)buf;
478 hperh->hdma1.config.size = len;
479 hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD;
480 hperh->hdma1.config.src_inc = DMA_DATA_INC_HALFWORD;
481 hperh->hdma1.config.dst_inc = DMA_DATA_INC_NONE;
482 hperh->hdma1.config.channel = dma_ch;
483
484
485 timer_dma_msel(hperh->perh, &hperh->hdma1.config);
486
487 switch (ch) {
488 case TIMER_CHANNEL_1:
489 hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL1;
490 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1;
491 ald_dma_config_basic(&hperh->hdma1);
492 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE);
493 hperh->ch = TIMER_ACTIVE_CHANNEL_1;
494 break;
495
496 case TIMER_CHANNEL_2:
497 hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL2;
498 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2;
499 ald_dma_config_basic(&hperh->hdma1);
500 ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE);
501 hperh->ch = TIMER_ACTIVE_CHANNEL_2;
502 break;
503
504 case TIMER_CHANNEL_3:
505 hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL3;
506 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH3;
507 ald_dma_config_basic(&hperh->hdma1);
508 ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE);
509 hperh->ch = TIMER_ACTIVE_CHANNEL_3;
510 break;
511
512 case TIMER_CHANNEL_4:
513 hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL4;
514 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH4;
515 ald_dma_config_basic(&hperh->hdma1);
516 ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE);
517 hperh->ch = TIMER_ACTIVE_CHANNEL_4;
518 break;
519
520 default:
521 break;
522 }
523
524 timer_ccx_channel_cmd(hperh->perh, ch, ENABLE);
525
526 if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
527 TIMER_MOE_ENABLE(hperh);
528
529 TIMER_ENABLE(hperh);
530 return OK;
531 }
532
544 void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
545 {
546 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
547
548 switch (ch) {
549 case TIMER_CHANNEL_1:
550 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE);
551 break;
552
553 case TIMER_CHANNEL_2:
554 ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE);
555 break;
556
557 case TIMER_CHANNEL_3:
558 ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE);
559 break;
560
561 case TIMER_CHANNEL_4:
562 ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE);
563 break;
564
565 default:
566 break;
567 }
568
569 timer_ccx_channel_cmd(hperh->perh, ch, DISABLE);
570
571 if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
572 TIMER_MOE_DISABLE(hperh);
573
574 TIMER_DISABLE(hperh);
575 hperh->state = TIMER_STATE_READY;
576 return;
577 }
578 #endif
579
609 ald_status_t ald_timer_pwm_init(timer_handle_t *hperh)
610 {
611 return ald_timer_base_init(hperh);
612 }
613
625 void ald_timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch)
626 {
627 ald_timer_oc_start(hperh, ch);
628 return;
629 }
630
642 void ald_timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch)
643 {
644 ald_timer_oc_stop(hperh, ch);
645 return;
646 }
647
659 void ald_timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
660 {
661 ald_timer_oc_start_by_it(hperh, ch);
662 return;
663 }
664
676 void ald_timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
677 {
678 ald_timer_oc_stop_by_it(hperh, ch);
679 return;
680 }
681
682 #ifdef ALD_DMA
683
697 ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch,
698 uint16_t *buf, uint32_t len, uint8_t dma_ch)
699 {
700 return ald_timer_oc_start_by_dma(hperh, ch, buf, len, dma_ch);
701 }
702
714 void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
715 {
716 ald_timer_oc_stop_by_dma(hperh, ch);
717 return;
718 }
719 #endif
720
726 void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq)
727 {
728 uint32_t _arr;
729
730 if (freq == 0)
731 return;
732
733 _arr = ald_cmu_get_pclk1_clock() / (hperh->init.prescaler + 1) / freq - 1;
734 WRITE_REG(hperh->perh->AR, _arr);
735 hperh->init.period = _arr;
736 }
737
750 void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty)
751 {
752 uint32_t tmp = (hperh->init.period + 1) * duty / 100 - 1;
753
754 if (ch == TIMER_CHANNEL_1)
755 WRITE_REG(hperh->perh->CCVAL1, tmp);
756 else if (ch == TIMER_CHANNEL_2)
757 WRITE_REG(hperh->perh->CCVAL2, tmp);
758 else if (ch == TIMER_CHANNEL_3)
759 WRITE_REG(hperh->perh->CCVAL3, tmp);
760 else if (ch == TIMER_CHANNEL_4)
761 WRITE_REG(hperh->perh->CCVAL4, tmp);
762 else {
763 ;/* do nothing */
764 }
765 }
766
776 void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch)
777 {
778 assert_param(IS_TIMER_PWM_INPUT_INSTANCE(hperh->perh, ch));
779
780 CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK);
781 switch (ch) {
782 case TIMER_CHANNEL_1:
783 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC1SSEL_POSS);
784 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC2SSEL_POSS);
785 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS);
786 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1NPOL_POS);
787 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS);
788 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2NPOL_POS);
789 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS);
790 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS);
791 break;
792 case TIMER_CHANNEL_2:
793 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, TIMER_IC_SEL_INDIRECT << TIMER_CHMR1_CC1SSEL_POSS);
794 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, TIMER_IC_SEL_DIRECT << TIMER_CHMR1_CC2SSEL_POSS);
795 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC1POL_POS);
796 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC1NPOL_POS);
797 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, TIMER_IC_POLARITY_FALL << TIMER_CCEP_CC2POL_POS);
798 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, TIMER_IC_POLARITY_RISE << TIMER_CCEP_CC2NPOL_POS);
799 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS);
800 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS);
801 break;
802 default:
803 break;
804 }
805
806 SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK);
807 SET_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2EN_MSK);
808
809 return;
810 }
841 ald_status_t ald_timer_ic_init(timer_handle_t *hperh)
842 {
843 return ald_timer_base_init(hperh);
844 }
845
857 void ald_timer_ic_start(timer_handle_t *hperh, timer_channel_t ch)
858 {
859 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
860
861 timer_ccx_channel_cmd(hperh->perh, ch, ENABLE);
862 TIMER_ENABLE(hperh);
863 return;
864 }
865
877 void ald_timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch)
878 {
879 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
880
881 timer_ccx_channel_cmd(hperh->perh, ch, DISABLE);
882 TIMER_DISABLE(hperh);
883 return;
884 }
885
897 void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
898 {
899 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
900
901 switch (ch) {
902 case TIMER_CHANNEL_1:
903 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE);
904 break;
905 case TIMER_CHANNEL_2:
906 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE);
907 break;
908 case TIMER_CHANNEL_3:
909 ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE);
910 break;
911 case TIMER_CHANNEL_4:
912 ald_timer_interrupt_config(hperh, TIMER_IT_CC4, ENABLE);
913 break;
914 default:
915 break;
916 }
917
918 timer_ccx_channel_cmd(hperh->perh, ch, ENABLE);
919 TIMER_ENABLE(hperh);
920 return;
921 }
922
934 void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
935 {
936 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
937
938 switch (ch) {
939 case TIMER_CHANNEL_1:
940 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE);
941 break;
942 case TIMER_CHANNEL_2:
943 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE);
944 break;
945 case TIMER_CHANNEL_3:
946 ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE);
947 break;
948 case TIMER_CHANNEL_4:
949 ald_timer_interrupt_config(hperh, TIMER_IT_CC4, DISABLE);
950 break;
951 default:
952 break;
953 }
954
955 timer_ccx_channel_cmd(hperh->perh, ch, DISABLE);
956 TIMER_DISABLE(hperh);
957 return;
958 }
959
960 #ifdef ALD_DMA
961
975 ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch,
976 uint16_t *buf, uint32_t len, uint8_t dma_ch)
977 {
978 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
979
980 if ((hperh->state == TIMER_STATE_BUSY))
981 return BUSY;
982 if ((hperh->state == TIMER_STATE_READY)) {
983 if (((uint32_t)buf == 0 ) || (len == 0))
984 return ERROR;
985 }
986
987 hperh->state = TIMER_STATE_BUSY;
988
989 if (hperh->perh == NULL)
990 hperh->hdma1.perh = DMA0;
991
992 hperh->hdma1.cplt_cbk = timer_dma_capture_cplt;
993 hperh->hdma1.cplt_arg = (void *)hperh;
994 hperh->hdma1.err_cbk = timer_dma_error;
995 hperh->hdma1.err_arg = (void *)hperh;
996
997 ald_dma_config_struct(&hperh->hdma1.config);
998 hperh->hdma1.config.dst = (void *)buf;
999 hperh->hdma1.config.size = len;
1000 hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD;
1001 hperh->hdma1.config.src_inc = DMA_DATA_INC_NONE;
1002 hperh->hdma1.config.dst_inc = DMA_DATA_INC_HALFWORD;
1003 hperh->hdma1.config.channel = dma_ch;
1004
1005 timer_dma_msel(hperh->perh, &hperh->hdma1.config);
1006
1007 switch (ch) {
1008 case TIMER_CHANNEL_1:
1009 hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1;
1010 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1;
1011 ald_dma_config_basic(&hperh->hdma1);
1012 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE);
1013 hperh->ch = TIMER_ACTIVE_CHANNEL_1;
1014 break;
1015
1016 case TIMER_CHANNEL_2:
1017 hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL2;
1018 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2;
1019 ald_dma_config_basic(&hperh->hdma1);
1020 ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE);
1021 hperh->ch = TIMER_ACTIVE_CHANNEL_2;
1022 break;
1023
1024 case TIMER_CHANNEL_3:
1025 hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL3;
1026 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH3;
1027 ald_dma_config_basic(&hperh->hdma1);
1028 ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE);
1029 hperh->ch = TIMER_ACTIVE_CHANNEL_3;
1030 break;
1031
1032 case TIMER_CHANNEL_4:
1033 hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL4;
1034 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH4;
1035 ald_dma_config_basic(&hperh->hdma1);
1036 ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, ENABLE);
1037 hperh->ch = TIMER_ACTIVE_CHANNEL_4;
1038 break;
1039
1040 default:
1041 break;
1042 }
1043
1044 timer_ccx_channel_cmd(hperh->perh, ch, ENABLE);
1045 TIMER_ENABLE(hperh);
1046 return OK;
1047 }
1048
1060 void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
1061 {
1062 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
1063
1064 switch (ch) {
1065 case TIMER_CHANNEL_1:
1066 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE);
1067 break;
1068 case TIMER_CHANNEL_2:
1069 ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE);
1070 break;
1071 case TIMER_CHANNEL_3:
1072 ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE);
1073 break;
1074 case TIMER_CHANNEL_4:
1075 ald_timer_dma_req_config(hperh, TIMER_DMA_CC4, DISABLE);
1076 break;
1077 default:
1078 break;
1079 }
1080
1081 timer_ccx_channel_cmd(hperh->perh, ch, DISABLE);
1082 TIMER_DISABLE(hperh);
1083 hperh->state = TIMER_STATE_READY;
1084 return;
1085 }
1086 #endif
1087
1121 ald_status_t ald_timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode)
1122 {
1123 if (hperh == NULL)
1124 return ERROR;
1125
1126 assert_param(IS_TIMER_INSTANCE(hperh->perh));
1127 assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode));
1128 assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div));
1129 assert_param(IS_TIMER_OP_MODE(mode));
1130
1131 if (hperh->state == TIMER_STATE_RESET)
1132 hperh->lock = UNLOCK;
1133
1134 hperh->state = TIMER_STATE_BUSY;
1135 timer_base_set_config(hperh->perh, &hperh->init);
1136 MODIFY_REG(hperh->perh->CON1, TIMER_CON1_SPMEN_MSK, mode << TIMER_CON1_SPMEN_POS);
1137 hperh->state = TIMER_STATE_READY;
1138
1139 return OK;
1140 }
1141
1151 void ald_timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch)
1152 {
1153 /* Enable the Capture compare and the Input Capture channels
1154 * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2)
1155 * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and
1156 * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output
1157 * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together
1158 */
1159 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1160 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
1161
1162 if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
1163 TIMER_MOE_ENABLE(hperh);
1164
1165 return;
1166 }
1167
1177 void ald_timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch)
1178 {
1179 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1180 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
1181
1182 if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
1183 TIMER_MOE_DISABLE(hperh);
1184
1185 TIMER_DISABLE(hperh);
1186 return;
1187 }
1188
1198 void ald_timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch)
1199 {
1200 /* Enable the Capture compare and the Input Capture channels
1201 * (in the OPM Mode the two possible channels that can be used are TIMER_CHANNEL_1 and TIMER_CHANNEL_2)
1202 * if TIMER_CHANNEL_1 is used as output, the TIMER_CHANNEL_2 will be used as input and
1203 * if TIMER_CHANNEL_1 is used as input, the TIMER_CHANNEL_2 will be used as output
1204 * in all combinations, the TIMER_CHANNEL_1 and TIMER_CHANNEL_2 should be enabled together
1205 */
1206 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE);
1207 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE);
1208 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1209 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
1210
1211 if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
1212 TIMER_MOE_ENABLE(hperh);
1213
1214 return;
1215 }
1216
1226 void ald_timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch)
1227 {
1228 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE);
1229 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE);
1230 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1231 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
1232
1233 if (IS_TIMER_BREAK_INSTANCE(hperh->perh) != RESET)
1234 TIMER_MOE_DISABLE(hperh);
1235
1236 TIMER_DISABLE(hperh);
1237 return;
1238 }
1269 ald_status_t ald_timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config)
1270 {
1271 if (hperh == NULL)
1272 return ERROR;
1273
1274 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
1275 assert_param(IS_TIMER_ENCODER_MODE(config->mode));
1276 assert_param(IS_TIMER_IC_POLARITY(config->ic1_polarity));
1277 assert_param(IS_TIMER_IC_POLARITY(config->ic2_polarity));
1278 assert_param(IS_TIMER_IC_SELECT(config->ic1_sel));
1279 assert_param(IS_TIMER_IC_SELECT(config->ic2_sel));
1280 assert_param(IS_TIMER_IC_PSC(config->ic1_psc));
1281 assert_param(IS_TIMER_IC_PSC(config->ic2_psc));
1282 assert_param(IS_TIMER_IC_FILTER(config->ic1_filter));
1283 assert_param(IS_TIMER_IC_FILTER(config->ic2_filter));
1284
1285 if (hperh->state == TIMER_STATE_RESET)
1286 hperh->lock = UNLOCK;
1287
1288 hperh->state = TIMER_STATE_BUSY;
1289 CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK);
1290 timer_base_set_config(hperh->perh, &hperh->init);
1291
1292 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS);
1293 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, config->ic1_sel << TIMER_CHMR1_CC1SSEL_POSS);
1294 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, config->ic2_sel << TIMER_CHMR1_CC2SSEL_POSS);
1295 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->ic1_psc << TIMER_CHMR1_IC1PRES_POSS);
1296 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->ic2_psc << TIMER_CHMR1_IC2PRES_POSS);
1297 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->ic1_filter << TIMER_CHMR1_I1FLT_POSS);
1298 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I2FLT_MSK, config->ic2_filter << TIMER_CHMR1_I2FLT_POSS);
1299 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1POL_MSK, (config->ic1_polarity & 0x1) << TIMER_CCEP_CC1POL_POS);
1300 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC1NPOL_MSK, ((config->ic1_polarity >> 1) & 0x1) << TIMER_CCEP_CC1NPOL_POS);
1301 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2POL_MSK, (config->ic2_polarity & 0x1) << TIMER_CCEP_CC2POL_POS);
1302 MODIFY_REG(hperh->perh->CCEP, TIMER_CCEP_CC2NPOL_MSK, ((config->ic2_polarity >> 1) & 0x1) << TIMER_CCEP_CC2NPOL_POS);
1303
1304 hperh->state = TIMER_STATE_READY;
1305 return OK;
1306 }
1307
1318 void ald_timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch)
1319 {
1320 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
1321
1322 switch (ch) {
1323 case TIMER_CHANNEL_1:
1324 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1325 break;
1326 case TIMER_CHANNEL_2:
1327 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
1328 break;
1329 default:
1330 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1331 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
1332 break;
1333 }
1334
1335 TIMER_ENABLE(hperh);
1336 return;
1337 }
1338
1349 void ald_timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch)
1350 {
1351 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
1352
1353 switch (ch) {
1354 case TIMER_CHANNEL_1:
1355 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1356 break;
1357 case TIMER_CHANNEL_2:
1358 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
1359 break;
1360 default:
1361 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1362 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
1363 break;
1364 }
1365
1366 TIMER_DISABLE(hperh);
1367 return;
1368 }
1369
1380 void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
1381 {
1382 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
1383
1384 switch (ch) {
1385 case TIMER_CHANNEL_1:
1386 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1387 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE);
1388 break;
1389 case TIMER_CHANNEL_2:
1390 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
1391 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE);
1392 break;
1393 default:
1394 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1395 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
1396 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE);
1397 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE);
1398 break;
1399 }
1400
1401 TIMER_ENABLE(hperh);
1402 return;
1403 }
1404
1415 void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
1416 {
1417 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
1418
1419 switch (ch) {
1420 case TIMER_CHANNEL_1:
1421 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1422 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE);
1423 break;
1424 case TIMER_CHANNEL_2:
1425 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
1426 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE);
1427 break;
1428 default:
1429 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1430 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
1431 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE);
1432 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE);
1433 break;
1434 }
1435
1436 TIMER_DISABLE(hperh);
1437 hperh->state = TIMER_STATE_READY;
1438 return;
1439 }
1440
1441 #ifdef ALD_DMA
1442
1457 ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch,
1458 uint16_t *buf1, uint16_t *buf2, uint32_t len,
1459 uint8_t dma_ch1, uint8_t dma_ch2)
1460 {
1461 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
1462
1463 if ((hperh->state == TIMER_STATE_BUSY))
1464 return BUSY;
1465 if ((hperh->state == TIMER_STATE_READY)) {
1466 if (((uint32_t)buf1 == 0) || ((uint32_t)buf2 == 0) || (len == 0))
1467 return ERROR;
1468 }
1469
1470 if (hperh->hdma1.perh == NULL)
1471 hperh->hdma1.perh = DMA0;
1472 if (hperh->hdma2.perh == NULL)
1473 hperh->hdma2.perh = DMA0;
1474
1475 hperh->state = TIMER_STATE_BUSY;
1476 hperh->hdma1.cplt_cbk = timer_dma_capture_cplt;
1477 hperh->hdma1.cplt_arg = (void *)hperh;
1478 hperh->hdma1.err_cbk = timer_dma_error;
1479 hperh->hdma1.err_arg = (void *)hperh;
1480
1481 ald_dma_config_struct(&hperh->hdma1.config);
1482 hperh->hdma1.config.size = len;
1483 hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD;
1484 hperh->hdma1.config.src_inc = DMA_DATA_INC_NONE;
1485 hperh->hdma1.config.dst_inc = DMA_DATA_INC_HALFWORD;
1486
1487 timer_dma_msel(hperh->perh, &hperh->hdma1.config);
1488
1489 switch (ch) {
1490 case TIMER_CHANNEL_1:
1491 hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1;
1492 hperh->hdma1.config.dst = (void *)buf1;
1493 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1;
1494 hperh->hdma1.config.channel = dma_ch1;
1495 ald_dma_config_basic(&hperh->hdma1);
1496 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE);
1497 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1498 TIMER_ENABLE(hperh);
1499 break;
1500
1501 case TIMER_CHANNEL_2:
1502 hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL2;
1503 hperh->hdma1.config.dst = (void *)buf2;
1504 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2;
1505 hperh->hdma1.config.channel = dma_ch2;
1506 ald_dma_config_basic(&hperh->hdma1);
1507 ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE);
1508 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
1509 TIMER_ENABLE(hperh);
1510 break;
1511
1512 default:
1513 hperh->hdma2.cplt_cbk = timer_dma_capture_cplt;
1514 hperh->hdma2.cplt_arg = (void *)hperh;
1515 hperh->hdma2.err_cbk = timer_dma_error;
1516 hperh->hdma2.err_arg = (void *)hperh;
1517 memcpy(&hperh->hdma2.config, &hperh->hdma1.config, sizeof(dma_config_t));
1518
1519 hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1;
1520 hperh->hdma1.config.dst = (void *)buf1;
1521 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1;
1522 hperh->hdma1.config.channel = dma_ch1;
1523 ald_dma_config_basic(&hperh->hdma1);
1524 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE);
1525
1526 hperh->hdma2.config.src = (void *)&hperh->perh->CCVAL2;
1527 hperh->hdma2.config.dst = (void *)buf2;
1528 hperh->hdma2.config.msigsel = DMA_MSIGSEL_TIMER_CH2;
1529 hperh->hdma2.config.channel = dma_ch2;
1530 ald_dma_config_basic(&hperh->hdma2);
1531 ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE);
1532
1533 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1534 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, ENABLE);
1535 TIMER_ENABLE(hperh);
1536 break;
1537 }
1538
1539 return OK;
1540 }
1541
1552 void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
1553 {
1554 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
1555
1556 switch (ch) {
1557 case TIMER_CHANNEL_1:
1558 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1559 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE);
1560 break;
1561 case TIMER_CHANNEL_2:
1562 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
1563 ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE);
1564 break;
1565 default:
1566 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1567 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_2, DISABLE);
1568 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE);
1569 ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE);
1570 break;
1571 }
1572
1573 TIMER_DISABLE(hperh);
1574 hperh->state = TIMER_STATE_READY;
1575 return;
1576 }
1577 #endif
1578
1608 ald_status_t ald_timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config)
1609 {
1610 timer_oc_init_t oc;
1611
1612 assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh));
1613 assert_param(IS_TIMER_COUNTER_MODE(hperh->init.mode));
1614 assert_param(IS_TIMER_CLOCK_DIVISION(hperh->init.clk_div));
1615 assert_param(IS_TIMER_IC_POLARITY(config->polarity));
1616 assert_param(IS_TIMER_IC_PSC(config->psc));
1617 assert_param(IS_TIMER_IC_FILTER(config->filter));
1618
1619 if (hperh->state == TIMER_STATE_RESET)
1620 hperh->lock = UNLOCK;
1621
1622 hperh->state = TIMER_STATE_READY;
1623 timer_base_set_config(hperh->perh, &hperh->init);
1624 timer_ti1_set_config(hperh->perh, config->polarity, TIMER_IC_SEL_TRC, config->filter);
1625
1626 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS);
1627 SET_BIT(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK);
1628 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS);
1629 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_RESET << TIMER_SMCON_SMODS_POSS);
1630
1631 oc.oc_mode = TIMER_OC_MODE_PWM2;
1632 oc.pulse = config->delay;
1633 oc.oc_polarity = TIMER_OC_POLARITY_HIGH;
1634 oc.ocn_polarity = TIMER_OCN_POLARITY_HIGH;
1635 oc.oc_fast_en = DISABLE;
1636 oc.oc_idle = TIMER_OC_IDLE_RESET;
1637 oc.ocn_idle = TIMER_OCN_IDLE_RESET;
1638 timer_oc2_set_config(hperh->perh, &oc);
1639
1640 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_TRGO_OC2REF << TIMER_SMCON_SMODS_POSS);
1641 return OK;
1642 }
1648 void ald_timer_hall_sensor_start(timer_handle_t *hperh)
1649 {
1650 assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh));
1651
1652 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1653 TIMER_ENABLE(hperh);
1654
1655 return;
1656 }
1657
1663 void ald_timer_hall_sensor_stop(timer_handle_t *hperh)
1664 {
1665 assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh));
1666
1667 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1668 TIMER_DISABLE(hperh);
1669
1670 return;
1671 }
1672
1678 void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh)
1679 {
1680 assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh));
1681
1682 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE);
1683 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1684 TIMER_ENABLE(hperh);
1685
1686 return;
1687 }
1688
1694 void ald_timer_hall_sensor_stop_by_it(timer_handle_t *hperh)
1695 {
1696 assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh));
1697
1698 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1699 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE);
1700 TIMER_DISABLE(hperh);
1701
1702 return;
1703 }
1704
1705 #ifdef ALD_DMA
1706
1714 ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh,
1715 uint16_t *buf, uint32_t len, uint8_t dma_ch)
1716 {
1717 assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh));
1718
1719 if ((hperh->state == TIMER_STATE_BUSY))
1720 return BUSY;
1721 if ((hperh->state == TIMER_STATE_READY)) {
1722 if (((uint32_t)buf == 0) || (len == 0))
1723 return ERROR;
1724 }
1725
1726 if (hperh->hdma1.perh == NULL)
1727 hperh->hdma1.perh = DMA0;
1728
1729 hperh->state = TIMER_STATE_BUSY;
1730 hperh->hdma1.cplt_cbk = timer_dma_capture_cplt;
1731 hperh->hdma1.cplt_arg = (void *)hperh;
1732 hperh->hdma1.err_cbk = timer_dma_error;
1733 hperh->hdma1.err_arg = (void *)hperh;
1734
1735 ald_dma_config_struct(&hperh->hdma1.config);
1736 hperh->hdma1.config.size = len;
1737 hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD;
1738 hperh->hdma1.config.src_inc = DMA_DATA_INC_NONE;
1739 hperh->hdma1.config.dst_inc = DMA_DATA_INC_HALFWORD;
1740
1741 timer_dma_msel(hperh->perh, &hperh->hdma1.config);
1742
1743 hperh->hdma1.config.src = (void *)&hperh->perh->CCVAL1;
1744 hperh->hdma1.config.dst = (void *)buf;
1745 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1;
1746 hperh->hdma1.config.channel = dma_ch;
1747 ald_dma_config_basic(&hperh->hdma1);
1748 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE);
1749 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, ENABLE);
1750 TIMER_ENABLE(hperh);
1751
1752 return OK;
1753 }
1759 void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh)
1760 {
1761 assert_param(IS_TIMER_XOR_INSTANCE(hperh->perh));
1762
1763 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE);
1764 timer_ccx_channel_cmd(hperh->perh, TIMER_CHANNEL_1, DISABLE);
1765 TIMER_DISABLE(hperh);
1766
1767 return;
1768 }
1769 #endif
1770
1804 void ald_timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch)
1805 {
1806 assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch));
1807
1808 timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE);
1809 TIMER_MOE_ENABLE(hperh);
1810 TIMER_ENABLE(hperh);
1811
1812 return;
1813 }
1814
1825 void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch)
1826 {
1827 assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch));
1828
1829 timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE);
1830 TIMER_MOE_DISABLE(hperh);
1831 TIMER_DISABLE(hperh);
1832
1833 return;
1834 }
1835
1847 void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
1848 {
1849 assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch));
1850
1851 switch (ch) {
1852 case TIMER_CHANNEL_1:
1853 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, ENABLE);
1854 break;
1855
1856 case TIMER_CHANNEL_2:
1857 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, ENABLE);
1858 break;
1859
1860 case TIMER_CHANNEL_3:
1861 ald_timer_interrupt_config(hperh, TIMER_IT_CC3, ENABLE);
1862 break;
1863 default:
1864 break;
1865 }
1866
1867 ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, ENABLE);
1868 timer_ccxn_channel_cmd(hperh->perh, ch, ENABLE);
1869 TIMER_MOE_ENABLE(hperh);
1870 TIMER_ENABLE(hperh);
1871
1872 return;
1873 }
1874
1886 void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
1887 {
1888 assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch));
1889
1890 switch (ch) {
1891 case TIMER_CHANNEL_1:
1892 ald_timer_interrupt_config(hperh, TIMER_IT_CC1, DISABLE);
1893 break;
1894
1895 case TIMER_CHANNEL_2:
1896 ald_timer_interrupt_config(hperh, TIMER_IT_CC2, DISABLE);
1897 break;
1898
1899 case TIMER_CHANNEL_3:
1900 ald_timer_interrupt_config(hperh, TIMER_IT_CC3, DISABLE);
1901 break;
1902 default:
1903 break;
1904 }
1905
1906 if ((!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1NEN_MSK)))
1907 && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC2NEN_MSK)))
1908 && (!(READ_BIT(hperh->perh->CCEP, TIMER_CCEP_CC3NEN_MSK)))) {
1909 ald_timer_interrupt_config(hperh, TIMER_IT_BREAK, DISABLE);
1910 }
1911
1912 timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE);
1913 TIMER_MOE_DISABLE(hperh);
1914 TIMER_DISABLE(hperh);
1915
1916 return;
1917 }
1918
1919 #ifdef ALD_DMA
1920
1934 ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh,
1935 timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
1936 {
1937 assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch));
1938
1939 if ((hperh->state == TIMER_STATE_BUSY))
1940 return BUSY;
1941 if ((hperh->state == TIMER_STATE_READY)) {
1942 if (((uint32_t)buf == 0 ) || (len == 0))
1943 return ERROR;
1944 }
1945
1946 hperh->state = TIMER_STATE_BUSY;
1947
1948 if (hperh->hdma1.perh == NULL)
1949 hperh->hdma1.perh = DMA0;
1950
1951 hperh->hdma1.cplt_cbk = timer_dma_oc_cplt;
1952 hperh->hdma1.cplt_arg = (void *)hperh;
1953 hperh->hdma1.err_cbk = timer_dma_error;
1954 hperh->hdma1.err_arg = (void *)hperh;
1955
1956 ald_dma_config_struct(&hperh->hdma1.config);
1957 hperh->hdma1.config.src = (void *)buf;
1958 hperh->hdma1.config.size = len;
1959 hperh->hdma1.config.data_width = DMA_DATA_SIZE_HALFWORD;
1960 hperh->hdma1.config.src_inc = DMA_DATA_INC_HALFWORD;
1961 hperh->hdma1.config.dst_inc = DMA_DATA_INC_NONE;
1962 hperh->hdma1.config.channel = dma_ch;
1963 hperh->hdma1.config.msel = DMA_MSEL_TIMER0;
1964
1965 switch (ch) {
1966 case TIMER_CHANNEL_1:
1967 hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL1;
1968 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH1;
1969 ald_dma_config_basic(&hperh->hdma1);
1970 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, ENABLE);
1971 hperh->ch = TIMER_ACTIVE_CHANNEL_1;
1972 break;
1973
1974 case TIMER_CHANNEL_2:
1975 hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL2;
1976 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH2;
1977 ald_dma_config_basic(&hperh->hdma1);
1978 ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, ENABLE);
1979 hperh->ch = TIMER_ACTIVE_CHANNEL_2;
1980 break;
1981
1982 case TIMER_CHANNEL_3:
1983 hperh->hdma1.config.dst = (void *)&hperh->perh->CCVAL3;
1984 hperh->hdma1.config.msigsel = DMA_MSIGSEL_TIMER_CH3;
1985 ald_dma_config_basic(&hperh->hdma1);
1986 ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, ENABLE);
1987 hperh->ch = TIMER_ACTIVE_CHANNEL_3;
1988 break;
1989
1990 default:
1991 break;
1992 }
1993
1994 timer_ccx_channel_cmd(hperh->perh, ch, ENABLE);
1995 TIMER_MOE_ENABLE(hperh);
1996 TIMER_ENABLE(hperh);
1997
1998 return OK;
1999 }
2000
2012 void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
2013 {
2014 assert_param(IS_TIMER_CCXN_INSTANCE(hperh->perh, ch));
2015
2016 switch (ch) {
2017 case TIMER_CHANNEL_1:
2018 ald_timer_dma_req_config(hperh, TIMER_DMA_CC1, DISABLE);
2019 break;
2020
2021 case TIMER_CHANNEL_2:
2022 ald_timer_dma_req_config(hperh, TIMER_DMA_CC2, DISABLE);
2023 break;
2024
2025 case TIMER_CHANNEL_3:
2026 ald_timer_dma_req_config(hperh, TIMER_DMA_CC3, DISABLE);
2027 break;
2028 default:
2029 break;
2030 }
2031
2032 timer_ccxn_channel_cmd(hperh->perh, ch, DISABLE);
2033 TIMER_MOE_DISABLE(hperh);
2034 TIMER_DISABLE(hperh);
2035
2036 return;
2037 }
2038 #endif
2039
2073 void ald_timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch)
2074 {
2075 ald_timer_ocn_start(hperh, ch);
2076 }
2077
2088 void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch)
2089 {
2090 ald_timer_ocn_stop(hperh, ch);
2091 }
2092
2104 void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
2105 {
2106 ald_timer_ocn_start_by_it(hperh, ch);
2107 }
2108
2120 void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
2121 {
2122 ald_timer_ocn_stop_by_it(hperh, ch);
2123 }
2124
2125 #ifdef ALD_DMA
2126
2140 ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh,
2141 timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
2142 {
2143 return ald_timer_ocn_start_by_dma(hperh, ch, buf, len, dma_ch);
2144 }
2145
2157 void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
2158 {
2159 ald_timer_ocn_stop_by_dma(hperh, ch);
2160 }
2161 #endif
2162
2193 void ald_timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch)
2194 {
2195 ald_timer_ocn_start(hperh, ch);
2196 }
2197
2207 void ald_timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch)
2208 {
2209 ald_timer_ocn_stop(hperh, ch);
2210 }
2211
2222 void ald_timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
2223 {
2224 ald_timer_ocn_start_by_it(hperh, ch);
2225 }
2226
2237 void ald_timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
2238 {
2239 ald_timer_ocn_stop_by_it(hperh, ch);
2240 }
2281 ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t* config, timer_channel_t ch)
2282 {
2283 assert_param(IS_TIMER_CCX_INSTANCE(hperh->perh, ch));
2284 assert_param(IS_TIMER_OC_MODE(config->oc_mode));
2285 assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity));
2286
2287 __LOCK(hperh);
2288 hperh->state = TIMER_STATE_BUSY;
2289
2290 switch (ch) {
2291 case TIMER_CHANNEL_1:
2292 timer_oc1_set_config(hperh->perh, config);
2293 break;
2294
2295 case TIMER_CHANNEL_2:
2296 timer_oc2_set_config(hperh->perh, config);
2297 break;
2298
2299 case TIMER_CHANNEL_3:
2300 timer_oc3_set_config(hperh->perh, config);
2301 break;
2302
2303 case TIMER_CHANNEL_4:
2304 timer_oc4_set_config(hperh->perh, config);
2305 break;
2306
2307 default:
2308 break;
2309 }
2310
2311 hperh->state = TIMER_STATE_READY;
2312 __UNLOCK(hperh);
2313 return OK;
2314 }
2315
2329 ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t* config, timer_channel_t ch)
2330 {
2331 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
2332 assert_param(IS_TIMER_IC_POLARITY(config->polarity));
2333 assert_param(IS_TIMER_IC_SELECT(config->sel));
2334 assert_param(IS_TIMER_IC_PSC(config->psc));
2335 assert_param(IS_TIMER_IC_FILTER(config->filter));
2336
2337 __LOCK(hperh);
2338 hperh->state = TIMER_STATE_BUSY;
2339
2340 switch (ch) {
2341 case TIMER_CHANNEL_1:
2342 timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter);
2343 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK, config->psc << TIMER_CHMR1_IC1PRES_POSS);
2344 break;
2345
2346 case TIMER_CHANNEL_2:
2347 timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter);
2348 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK, config->psc << TIMER_CHMR1_IC2PRES_POSS);
2349 break;
2350
2351 case TIMER_CHANNEL_3:
2352 timer_ti3_set_config(hperh->perh, config->polarity, config->sel, config->filter);
2353 MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC3PRES_MSK, config->psc << TIMER_CHMR2_IC3PRES_POSS);
2354 break;
2355
2356 case TIMER_CHANNEL_4:
2357 timer_ti4_set_config(hperh->perh, config->polarity, config->sel, config->filter);
2358 MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_IC4PRES_MSK, config->psc << TIMER_CHMR2_IC4PRES_POSS);
2359 break;
2360
2361 default:
2362 break;
2363 }
2364
2365 hperh->state = TIMER_STATE_READY;
2366 __UNLOCK(hperh);
2367 return OK;
2368 }
2369
2385 ald_status_t ald_timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config,
2386 timer_channel_t ch_out, timer_channel_t ch_in)
2387 {
2388 timer_oc_init_t tmp;
2389
2390 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
2391 assert_param(IS_TIMER_OC_MODE(config->mode));
2392 assert_param(IS_TIMER_OC_POLARITY(config->oc_polarity));
2393 assert_param(IS_TIMER_OCN_POLARITY(config->ocn_polarity));
2394 assert_param(IS_TIMER_OCIDLE_STATE(config->oc_idle));
2395 assert_param(IS_TIMER_OCNIDLE_STATE(config->ocn_idle));
2396 assert_param(IS_TIMER_IC_POLARITY(config->polarity));
2397 assert_param(IS_TIMER_IC_SELECT(config->sel));
2398 assert_param(IS_TIMER_IC_FILTER(config->filter));
2399
2400 if (ch_out == ch_in)
2401 return ERROR;
2402
2403 __LOCK(hperh);
2404 hperh->state = TIMER_STATE_BUSY;
2405
2406 tmp.oc_mode = config->mode;
2407 tmp.pulse = config->pulse;
2408 tmp.oc_polarity = config->oc_polarity;
2409 tmp.ocn_polarity = config->ocn_polarity;
2410 tmp.oc_idle = config->oc_idle;
2411 tmp.ocn_idle = config->ocn_idle;
2412
2413 switch (ch_out) {
2414 case TIMER_CHANNEL_1:
2415 timer_oc1_set_config(hperh->perh, &tmp);
2416 break;
2417 case TIMER_CHANNEL_2:
2418 timer_oc2_set_config(hperh->perh, &tmp);
2419 break;
2420 default:
2421 break;
2422 }
2423
2424 switch (ch_in) {
2425 case TIMER_CHANNEL_1:
2426 timer_ti1_set_config(hperh->perh, config->polarity, config->sel, config->filter);
2427 CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC1PRES_MSK);
2428 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS);
2429 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS);
2430 break;
2431
2432 case TIMER_CHANNEL_2:
2433 timer_ti2_set_config(hperh->perh, config->polarity, config->sel, config->filter);
2434 CLEAR_BIT(hperh->perh->CHMR1, TIMER_CHMR1_IC2PRES_MSK);
2435 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS);
2436 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_TRIG << TIMER_SMCON_SMODS_POSS);
2437 break;
2438 default:
2439 break;
2440 }
2441
2442 hperh->state = TIMER_STATE_READY;
2443 __UNLOCK(hperh);
2444 return OK;
2445 }
2446
2460 ald_status_t ald_timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch)
2461 {
2462 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
2463 assert_param(IS_FUNC_STATE(config->state));
2464 assert_param(IS_TIMER_CLEAR_INPUT_SOURCE(config->source));
2465 assert_param(IS_TIMER_CLEAR_INPUT_POLARITY(config->polarity));
2466 assert_param(IS_TIMER_ETR_PSC(config->psc));
2467 assert_param(IS_TIMER_CHNREF_CLEAR(config->clrsel));
2468 assert_param(IS_TIMER_IC_FILTER(config->filter));
2469
2470 if (config->source == TIMER_INPUT_NONE) {
2471 timer_etr_set_config(hperh->perh, TIMER_ETR_PSC_DIV1, TIMER_CLK_POLARITY_NO_INV, 0);
2472 }
2473 else {
2474 timer_etr_set_config(hperh->perh, config->psc,
2475 (timer_clock_polarity_t)config->polarity, config->filter);
2476 }
2477
2478 if (config->clrsel == TIMER_CHNREF_CLR_CMP_IN) {
2479 CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_CHCSEL_MASK);
2480 }
2481 else {
2482 SET_BIT(hperh->perh->SMCON, TIMER_SMCON_CHCSEL_MASK);
2483 }
2484
2485 switch (ch) {
2486 case TIMER_CHANNEL_1:
2487 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OCLREN_MSK, config->state << TIMER_CHMR1_CH1OCLREN_POS);
2488 break;
2489
2490 case TIMER_CHANNEL_2:
2491 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OCLREN_MSK, config->state << TIMER_CHMR1_CH2OCLREN_POS);
2492 break;
2493
2494 case TIMER_CHANNEL_3:
2495 assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh));
2496 MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OCLREN_MSK, config->state << TIMER_CHMR2_CH3OCLREN_POS);
2497 break;
2498
2499 case TIMER_CHANNEL_4:
2500 assert_param(IS_TIMER_CC4_INSTANCE(hperh->perh));
2501 MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OCLREN_MSK, config->state << TIMER_CHMR2_CH4OCLREN_POS);
2502 break;
2503
2504 default:
2505 break;
2506 }
2507
2508 return OK;
2509 }
2510
2518 ald_status_t ald_timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config)
2519 {
2520 assert_param(IS_TIMER_INSTANCE(hperh->perh));
2521 assert_param(IS_TIMER_CLOCK_SOURCE(config->source));
2522 assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity));
2523 assert_param(IS_TIMER_ETR_PSC(config->psc));
2524 assert_param(IS_TIMER_IC_FILTER(config->filter));
2525
2526 __LOCK(hperh);
2527 hperh->state = TIMER_STATE_BUSY;
2528 WRITE_REG(hperh->perh->SMCON, 0x0);
2529
2530 switch (config->source) {
2531 case TIMER_SRC_INTER:
2532 CLEAR_BIT(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK);
2533 break;
2534
2535 case TIMER_SRC_ETRMODE1:
2536 timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter);
2537 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ETRF << TIMER_SMCON_TSSEL_POSS);
2538 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
2539 break;
2540
2541 case TIMER_SRC_ETRMODE2:
2542 timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter);
2543 SET_BIT(hperh->perh->SMCON, TIMER_SMCON_ECM2EN_MSK);
2544 break;
2545
2546 case TIMER_SRC_TI1:
2547 timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter);
2548 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1FP1 << TIMER_SMCON_TSSEL_POSS);
2549 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
2550 break;
2551
2552 case TIMER_SRC_TI2:
2553 timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter);
2554 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI2FP2 << TIMER_SMCON_TSSEL_POSS);
2555 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
2556 break;
2557
2558 case TIMER_SRC_TI1ED:
2559 timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter);
2560 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_TI1F_ED << TIMER_SMCON_TSSEL_POSS);
2561 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
2562 break;
2563
2564 case TIMER_SRC_ITR0:
2565 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR0 << TIMER_SMCON_TSSEL_POSS);
2566 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
2567 break;
2568
2569 case TIMER_SRC_ITR1:
2570 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR1 << TIMER_SMCON_TSSEL_POSS);
2571 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
2572 break;
2573
2574 case TIMER_SRC_ITR2:
2575 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR2 << TIMER_SMCON_TSSEL_POSS);
2576 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
2577 break;
2578
2579 case TIMER_SRC_ITR3:
2580 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, TIMER_TS_ITR3 << TIMER_SMCON_TSSEL_POSS);
2581 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, TIMER_MODE_EXTERNAL1 << TIMER_SMCON_SMODS_POSS);
2582 break;
2583 default:
2584 break;
2585 }
2586
2587 hperh->state = TIMER_STATE_READY;
2588 __UNLOCK(hperh);
2589 return OK;
2590 }
2591
2604 ald_status_t ald_timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select)
2605 {
2606 assert_param(IS_TIMER_INSTANCE(hperh->perh));
2607
2608 MODIFY_REG(hperh->perh->CON2, TIMER_CON2_I1FSEL_MSK, ti1_select << TIMER_CON2_I1FSEL_POS);
2609 return OK;
2610 }
2611
2621 ald_status_t ald_timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config)
2622 {
2623 assert_param(IS_TIMER_INSTANCE(hperh->perh));
2624 assert_param(IS_TIMER_SLAVE_MODE(config->mode));
2625 assert_param(IS_TIMER_TS(config->input));
2626 assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity));
2627 assert_param(IS_TIMER_ETR_PSC(config->psc));
2628 assert_param(IS_TIMER_IC_FILTER(config->filter));
2629
2630 __LOCK(hperh);
2631 hperh->state = TIMER_STATE_BUSY;
2632
2633 timer_slave_set_config(hperh, config);
2634 ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, DISABLE);
2635 ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE);
2636
2637 hperh->state = TIMER_STATE_READY;
2638 __UNLOCK(hperh);
2639 return OK;
2640 }
2641
2651 ald_status_t ald_timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config)
2652 {
2653 assert_param(IS_TIMER_INSTANCE(hperh->perh));
2654 assert_param(IS_TIMER_SLAVE_MODE(config->mode));
2655 assert_param(IS_TIMER_TS(config->input));
2656 assert_param(IS_TIMER_CLOCK_POLARITY(config->polarity));
2657 assert_param(IS_TIMER_ETR_PSC(config->psc));
2658 assert_param(IS_TIMER_IC_FILTER(config->filter));
2659
2660 __LOCK(hperh);
2661 hperh->state = TIMER_STATE_BUSY;
2662
2663 timer_slave_set_config(hperh, config);
2664 ald_timer_interrupt_config(hperh, TIMER_IT_TRIGGER, ENABLE);
2665 ald_timer_dma_req_config(hperh, TIMER_DMA_TRIGGER, DISABLE);
2666
2667 hperh->state = TIMER_STATE_READY;
2668 __UNLOCK(hperh);
2669 return OK;
2670 }
2671
2678 ald_status_t ald_timer_generate_event(timer_handle_t *hperh, timer_event_source_t event)
2679 {
2680 assert_param(IS_TIMER_INSTANCE(hperh->perh));
2681 assert_param(IS_TIMER_EVENT_SOURCE(event));
2682
2683 __LOCK(hperh);
2684 hperh->state = TIMER_STATE_BUSY;
2685 WRITE_REG(hperh->perh->SGE, event);
2686 hperh->state = TIMER_STATE_READY;
2687 __UNLOCK(hperh);
2688
2689 return OK;
2690 }
2691
2703 uint32_t ald_timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch)
2704 {
2705 uint32_t tmp;
2706
2707 __LOCK(hperh);
2708 hperh->state = TIMER_STATE_BUSY;
2709
2710 switch (ch) {
2711 case TIMER_CHANNEL_1:
2712 tmp = hperh->perh->CCVAL1;
2713 break;
2714 case TIMER_CHANNEL_2:
2715 tmp = hperh->perh->CCVAL2;
2716 break;
2717 case TIMER_CHANNEL_3:
2718 tmp = hperh->perh->CCVAL3;
2719 break;
2720 case TIMER_CHANNEL_4:
2721 tmp = hperh->perh->CCVAL4;
2722 break;
2723 default:
2724 tmp = hperh->perh->CCVAL1;
2725 break;
2726 }
2727
2728 hperh->state = TIMER_STATE_READY;
2729 __UNLOCK(hperh);
2730 return tmp;
2731 }
2732
2745 void ald_timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch)
2746 {
2747 assert_param(IS_TIMER_CC2_INSTANCE(hperh->perh));
2748 assert_param(IS_TIMER_OC_MODE(mode));
2749 assert_param(IS_TIMER_CHANNELS(ch));
2750
2751 switch (ch) {
2752 case TIMER_CHANNEL_1:
2753 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, mode << TIMER_CHMR1_CH1OMOD_POSS);
2754 break;
2755 case TIMER_CHANNEL_2:
2756 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, mode << TIMER_CHMR1_CH2OMOD_POSS);
2757 break;
2758 case TIMER_CHANNEL_3:
2759 MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, mode << TIMER_CHMR2_CH3OMOD_POSS);
2760 break;
2761 case TIMER_CHANNEL_4:
2762 MODIFY_REG(hperh->perh->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, mode << TIMER_CHMR2_CH4OMOD_POSS);
2763 break;
2764 default:
2765 break;
2766 }
2767
2768 return;
2769 }
2770
2777 void ald_timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config)
2778 {
2779 uint32_t cm1, cm2, cce;
2780
2781 assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh));
2782 assert_param(IS_FUNC_STATE(config->ch[0].en));
2783 assert_param(IS_FUNC_STATE(config->ch[0].n_en));
2784 assert_param(IS_TIMER_OC_MODE(config->ch[0].mode));
2785 assert_param(IS_FUNC_STATE(config->ch[1].en));
2786 assert_param(IS_FUNC_STATE(config->ch[1].n_en));
2787 assert_param(IS_TIMER_OC_MODE(config->ch[1].mode));
2788 assert_param(IS_FUNC_STATE(config->ch[2].en));
2789 assert_param(IS_FUNC_STATE(config->ch[2].n_en));
2790 assert_param(IS_TIMER_OC_MODE(config->ch[2].mode));
2791
2792 TIMER_MOE_DISABLE(hperh);
2793 TIMER_DISABLE(hperh);
2794
2795 cm1 = hperh->perh->CHMR1;
2796 cm2 = hperh->perh->CHMR2;
2797 cce = hperh->perh->CCEP;
2798
2799 MODIFY_REG(cm1, (0x7 << 4), (config->ch[0].mode << 4));
2800 MODIFY_REG(cm1, (0x7 << 12), (config->ch[1].mode << 12));
2801 MODIFY_REG(cm2, (0x7 << 4), (config->ch[2].mode << 4));
2802 MODIFY_REG(cce, (0x1 << 0), (config->ch[0].en << 0));
2803 MODIFY_REG(cce, (0x1 << 2), (config->ch[0].n_en << 2));
2804 MODIFY_REG(cce, (0x1 << 4), (config->ch[1].en << 4));
2805 MODIFY_REG(cce, (0x1 << 6), (config->ch[1].n_en << 6));
2806 MODIFY_REG(cce, (0x1 << 8), (config->ch[2].en << 8));
2807 MODIFY_REG(cce, (0x1 << 10), (config->ch[2].n_en << 10));
2808
2809 WRITE_REG(hperh->perh->CHMR1, cm1);
2810 WRITE_REG(hperh->perh->CHMR2, cm2);
2811 WRITE_REG(hperh->perh->CCEP, cce);
2812
2813 TIMER_MOE_ENABLE(hperh);
2814 TIMER_ENABLE(hperh);
2815 return;
2816 }
2817
2834 void ald_timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi)
2835 {
2836 assert_param(IS_TIMER_COM_EVENT_INSTANCE(hperh->perh));
2837 assert_param(IS_TIMER_TS(ts));
2838 assert_param(IS_FUNC_STATE(trgi));
2839
2840 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, ts << TIMER_SMCON_TSSEL_POSS);
2841 SET_BIT(hperh->perh->CON2, TIMER_CON2_CCPCEN_MSK);
2842 MODIFY_REG(hperh->perh->CON2, TIMER_CON2_CCUSEL_MSK, trgi << TIMER_CON2_CCUSEL_POS);
2843
2844 return;
2845 }
2846
2863 void ald_timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi)
2864 {
2865 ald_timer_com_event_config(hperh, ts, trgi);
2866 ald_timer_interrupt_config(hperh, TIMER_IT_COM, ENABLE);
2867 }
2868
2875 void ald_timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config)
2876 {
2877 uint32_t tmp;
2878
2879 assert_param(IS_TIMER_BREAK_INSTANCE(hperh->perh));
2880 assert_param(IS_FUNC_STATE(config->off_run));
2881 assert_param(IS_FUNC_STATE(config->off_idle));
2882 assert_param(IS_TIMER_CLOCK_LEVEL(config->lock_level));
2883 assert_param(IS_TIMER_DEAD_TIMERE(config->dead_time));
2884 assert_param(IS_FUNC_STATE(config->break_state));
2885 assert_param(IS_TIMER_BREAK_POLARITY(config->polarity));
2886 assert_param(IS_FUNC_STATE(config->auto_out));
2887
2888 tmp = READ_REG(hperh->perh->BDCFG);
2889 MODIFY_REG(tmp, TIMER_BDCFG_OFFSSR_MSK, config->off_run << TIMER_BDCFG_OFFSSR_POS);
2890 MODIFY_REG(tmp, TIMER_BDCFG_OFFSSI_MSK, config->off_idle << TIMER_BDCFG_OFFSSI_POS);
2891 MODIFY_REG(tmp, TIMER_BDCFG_LOCKLVL_MSK, config->lock_level << TIMER_BDCFG_LOCKLVL_POSS);
2892 MODIFY_REG(tmp, TIMER_BDCFG_DT_MSK, config->dead_time << TIMER_BDCFG_DT_POSS);
2893 MODIFY_REG(tmp, TIMER_BDCFG_BRKEN_MSK, config->break_state << TIMER_BDCFG_BRKEN_POS);
2894 MODIFY_REG(tmp, TIMER_BDCFG_BRKP_MSK, config->polarity << TIMER_BDCFG_BRKP_POS);
2895 MODIFY_REG(tmp, TIMER_BDCFG_AOEN_MSK, config->auto_out << TIMER_BDCFG_AOEN_POS);
2896 WRITE_REG(hperh->perh->BDCFG, tmp);
2897
2898 hperh->state = TIMER_STATE_READY;
2899 return;
2900 }
2901
2908 void ald_timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config)
2909 {
2910 assert_param(IS_TIMER_INSTANCE(hperh->perh));
2911 assert_param(IS_TIMER_MASTER_MODE_SEL(config->sel));
2912 assert_param(IS_FUNC_STATE(config->master_en));
2913
2914 hperh->state = TIMER_STATE_BUSY;
2915 MODIFY_REG(hperh->perh->CON2, TIMER_CON2_TRGOSEL_MSK, config->sel << TIMER_CON2_TRGOSEL_POSS);
2916 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_MSCFG_MSK, config->master_en << TIMER_SMCON_MSCFG_POS);
2917 hperh->state = TIMER_STATE_READY;
2918
2919 return;
2920 }
2921
2927 void ald_timer_irq_handler(timer_handle_t *hperh)
2928 {
2929 uint32_t reg = hperh->perh->IFM;
2930
2931 /* Capture or compare 1 event */
2932 if (READ_BIT(reg, TIMER_FLAG_CC1)) {
2933 ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC1);
2934 hperh->ch = TIMER_ACTIVE_CHANNEL_1;
2935
2936 /* Input capture event */
2937 if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC1SSEL_MSK)) {
2938 if (hperh->capture_cbk)
2939 hperh->capture_cbk(hperh);
2940 }
2941 else { /* Output compare event */
2942 if (hperh->delay_elapse_cbk)
2943 hperh->delay_elapse_cbk(hperh);
2944 if (hperh->pwm_pulse_finish_cbk)
2945 hperh->pwm_pulse_finish_cbk(hperh);
2946 }
2947
2948 hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED;
2949 }
2950 /* Capture or compare 2 event */
2951 if (READ_BIT(reg, TIMER_FLAG_CC2)) {
2952 ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC2);
2953 hperh->ch = TIMER_ACTIVE_CHANNEL_2;
2954
2955 /* Input capture event */
2956 if (READ_BIT(hperh->perh->CHMR1, TIMER_CHMR1_CC2SSEL_MSK)) {
2957 if (hperh->capture_cbk)
2958 hperh->capture_cbk(hperh);
2959 }
2960 else { /* Output compare event */
2961 if (hperh->delay_elapse_cbk)
2962 hperh->delay_elapse_cbk(hperh);
2963 if (hperh->pwm_pulse_finish_cbk)
2964 hperh->pwm_pulse_finish_cbk(hperh);
2965 }
2966
2967 hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED;
2968 }
2969 /* Capture or compare 3 event */
2970 if (READ_BIT(reg, TIMER_FLAG_CC3)) {
2971 ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC3);
2972 hperh->ch = TIMER_ACTIVE_CHANNEL_3;
2973
2974 /* Input capture event */
2975 if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC3SSEL_MSK)) {
2976 if (hperh->capture_cbk)
2977 hperh->capture_cbk(hperh);
2978 }
2979 else { /* Output compare event */
2980 if (hperh->delay_elapse_cbk)
2981 hperh->delay_elapse_cbk(hperh);
2982 if (hperh->pwm_pulse_finish_cbk)
2983 hperh->pwm_pulse_finish_cbk(hperh);
2984 }
2985
2986 hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED;
2987 }
2988 /* Capture or compare 4 event */
2989 if (READ_BIT(reg, TIMER_FLAG_CC4)) {
2990 ald_timer_clear_flag_status(hperh, TIMER_FLAG_CC4);
2991 hperh->ch = TIMER_ACTIVE_CHANNEL_4;
2992
2993 /* Input capture event */
2994 if (READ_BIT(hperh->perh->CHMR2, TIMER_CHMR2_CC4SSEL_MSK)) {
2995 if (hperh->capture_cbk)
2996 hperh->capture_cbk(hperh);
2997 }
2998 else { /* Output compare event */
2999 if (hperh->delay_elapse_cbk)
3000 hperh->delay_elapse_cbk(hperh);
3001 if (hperh->pwm_pulse_finish_cbk)
3002 hperh->pwm_pulse_finish_cbk(hperh);
3003 }
3004
3005 hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED;
3006 }
3007
3008 /* TIMER Update event */
3009 if (READ_BIT(reg, TIMER_FLAG_UPDATE)) {
3010 ald_timer_clear_flag_status(hperh, TIMER_FLAG_UPDATE);
3011
3012 if (hperh->period_elapse_cbk)
3013 hperh->period_elapse_cbk(hperh);
3014 }
3015
3016 /* TIMER Break input event */
3017 if (READ_BIT(reg, TIMER_FLAG_BREAK)) {
3018 ald_timer_clear_flag_status(hperh, TIMER_FLAG_BREAK);
3019
3020 if (hperh->break_cbk)
3021 hperh->break_cbk(hperh);
3022 }
3023
3024 /* TIMER Trigger detection event */
3025 if (READ_BIT(reg, TIMER_FLAG_TRIGGER)) {
3026 ald_timer_clear_flag_status(hperh, TIMER_FLAG_TRIGGER);
3027
3028 if (hperh->trigger_cbk)
3029 hperh->trigger_cbk(hperh);
3030 }
3031
3032 /* TIMER commutation event */
3033 if (READ_BIT(reg, TIMER_FLAG_COM)) {
3034 ald_timer_clear_flag_status(hperh, TIMER_FLAG_COM);
3035
3036 if (hperh->com_cbk)
3037 hperh->com_cbk(hperh);
3038 }
3039
3040 return;
3041 }
3042
3050 void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state)
3051 {
3052 assert_param(IS_TIMER_INSTANCE(hperh->perh));
3053 assert_param(IS_TIMER_DMA_REQ(req));
3054 assert_param(IS_FUNC_STATE(state));
3055
3056 if (state == ENABLE)
3057 SET_BIT(hperh->perh->DMAEN, req);
3058 else
3059 CLEAR_BIT(hperh->perh->DMAEN, req);
3060
3061 return;
3062 }
3063
3075 void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state)
3076 {
3077 assert_param(IS_TIMER_INSTANCE(hperh->perh));
3078 assert_param(IS_TIMER_IT(it));
3079 assert_param(IS_FUNC_STATE(state));
3080
3081 if (state == ENABLE)
3082 SET_BIT(hperh->perh->IER, it);
3083 else
3084 SET_BIT(hperh->perh->IDR, it);
3085
3086 return;
3087 }
3088
3098 it_status_t ald_timer_get_it_status(timer_handle_t *hperh, timer_it_t it)
3099 {
3100 assert_param(IS_TIMER_INSTANCE(hperh->perh));
3101 assert_param(IS_TIMER_IT(it));
3102
3103 if (hperh->perh->IVS & it)
3104 return SET;
3105
3106 return RESET;
3107 }
3108
3118 flag_status_t ald_timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag)
3119 {
3120 assert_param(IS_TIMER_INSTANCE(hperh->perh));
3121 assert_param(IS_TIMER_FLAG(flag));
3122
3123 if (hperh->perh->RIF & flag)
3124 return SET;
3125
3126 return RESET;
3127 }
3128
3136 void ald_timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag)
3137 {
3138 assert_param(IS_TIMER_INSTANCE(hperh->perh));
3139 assert_param(IS_TIMER_FLAG(flag));
3140
3141 hperh->perh->ICR = flag;
3142 return;
3143 }
3168 timer_state_t ald_timer_get_state(timer_handle_t *hperh)
3169 {
3170 return hperh->state;
3171 }
3183 #ifdef ALD_DMA
3184
3189 void timer_dma_oc_cplt(void *arg)
3190 {
3191 timer_handle_t *hperh = (timer_handle_t *)arg;
3192
3193 if (hperh->delay_elapse_cbk)
3194 hperh->delay_elapse_cbk(hperh);
3195
3196 if (hperh->pwm_pulse_finish_cbk)
3197 hperh->pwm_pulse_finish_cbk(hperh);
3198
3199 hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED;
3200 return;
3201 }
3202
3208 void timer_dma_capture_cplt(void *arg)
3209 {
3210 timer_handle_t *hperh = (timer_handle_t *)arg;
3211
3212 if (hperh->capture_cbk)
3213 hperh->capture_cbk(hperh);
3214
3215 hperh->ch = TIMER_ACTIVE_CHANNEL_CLEARED;
3216 return;
3217 }
3218
3224 void timer_dma_period_elapse_cplt(void *arg)
3225 {
3226 timer_handle_t *hperh = (timer_handle_t *)arg;
3227
3228 if (hperh->period_elapse_cbk)
3229 hperh->period_elapse_cbk(hperh);
3230
3231 hperh->state = TIMER_STATE_READY;
3232 return;
3233 }
3234
3240 void timer_dma_error(void *arg)
3241 {
3242 timer_handle_t *hperh = (timer_handle_t *)arg;
3243
3244 hperh->state = TIMER_STATE_READY;
3245 if (hperh->error_cbk)
3246 hperh->error_cbk(hperh);
3247
3248 return;
3249 }
3250 #endif
3251
3258 static void timer_base_set_config(TIMER_TypeDef *TIMERx, timer_base_init_t *init)
3259 {
3260 assert_param(IS_TIMER_COUNTER_MODE(init->mode));
3261 assert_param(IS_TIMER_CLOCK_DIVISION(init->clk_div));
3262
3263 if (init->mode == TIMER_CNT_MODE_UP || init->mode == TIMER_CNT_MODE_DOWN) {
3264 CLEAR_BIT(TIMERx->CON1, TIMER_CON1_CMSEL_MSK);
3265 MODIFY_REG(TIMERx->CON1, TIMER_CON1_DIRSEL_MSK, init->mode << TIMER_CON1_DIRSEL_POS);
3266 }
3267 else {
3268 MODIFY_REG(TIMERx->CON1, TIMER_CON1_CMSEL_MSK, (init->mode - 1) << TIMER_CON1_CMSEL_POSS);
3269 }
3270
3271 if (IS_TIMER_CLOCK_DIVISION_INSTANCE(TIMERx))
3272 MODIFY_REG(TIMERx->CON1, TIMER_CON1_DFCKSEL_MSK, init->clk_div << TIMER_CON1_DFCKSEL_POSS);
3273
3274 WRITE_REG(TIMERx->AR, init->period);
3275 WRITE_REG(TIMERx->PRES, init->prescaler);
3276
3277 if (IS_TIMER_REPETITION_COUNTER_INSTANCE(TIMERx))
3278 WRITE_REG(TIMERx->REPAR, init->re_cnt);
3279
3280 return;
3281 }
3282
3289 static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
3290 {
3291 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK);
3292 CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK);
3293 CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK);
3294 MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH1OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH1OMOD_POSS);
3295 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC1POL_POS);
3296
3297 if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_1)) {
3298 assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity));
3299 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC1NPOL_POS);
3300 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK);
3301 }
3302
3303 if (IS_TIMER_BREAK_INSTANCE(TIMERx)) {
3304 assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle));
3305 assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle));
3306
3307 MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1_MSK, oc_config->oc_idle << TIMER_CON2_OISS1_POS);
3308 MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS1N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS1N_POS);
3309 }
3310
3311 WRITE_REG(TIMERx->CCVAL1, oc_config->pulse);
3312 }
3313
3320 static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
3321 {
3322 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK);
3323 CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK);
3324 CLEAR_BIT(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK);
3325 MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CH2OMOD_MSK, oc_config->oc_mode << TIMER_CHMR1_CH2OMOD_POSS);
3326 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC2POL_POS);
3327
3328 if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_2)) {
3329 assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity));
3330 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC2NPOL_POS);
3331 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK);
3332 }
3333
3334 if (IS_TIMER_BREAK_INSTANCE(TIMERx)) {
3335 assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle));
3336 assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle));
3337
3338 MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2_MSK, oc_config->oc_idle << TIMER_CON2_OISS2_POS);
3339 MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS2N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS2N_POS);
3340 }
3341
3342 WRITE_REG(TIMERx->CCVAL2, oc_config->pulse);
3343 }
3344
3351 static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
3352 {
3353 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK);
3354 CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK);
3355 CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK);
3356 MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH3OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH3OMOD_POSS);
3357 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC3POL_POS);
3358
3359 if (IS_TIMER_CCXN_INSTANCE(TIMERx, TIMER_CHANNEL_3)) {
3360 assert_param(IS_TIMER_OCN_POLARITY(oc_config->ocn_polarity));
3361 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NPOL_MSK, oc_config->ocn_polarity << TIMER_CCEP_CC3NPOL_POS);
3362 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK);
3363 }
3364
3365 if (IS_TIMER_BREAK_INSTANCE(TIMERx)) {
3366 assert_param(IS_TIMER_OCNIDLE_STATE(oc_config->ocn_idle));
3367 assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle));
3368
3369 MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3_MSK, oc_config->oc_idle << TIMER_CON2_OISS3_POS);
3370 MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS3N_MSK, oc_config->ocn_idle << TIMER_CON2_OISS3N_POS);
3371 }
3372
3373 WRITE_REG(TIMERx->CCVAL3, oc_config->pulse);
3374 }
3375
3382 static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
3383 {
3384 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK);
3385 CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK);
3386 CLEAR_BIT(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK);
3387 MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CH4OMOD_MSK, oc_config->oc_mode << TIMER_CHMR2_CH4OMOD_POSS);
3388 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, oc_config->oc_polarity << TIMER_CCEP_CC4POL_POS);
3389
3390 if (IS_TIMER_BREAK_INSTANCE(TIMERx)) {
3391 assert_param(IS_TIMER_OCIDLE_STATE(oc_config->oc_idle));
3392 MODIFY_REG(TIMERx->CON2, TIMER_CON2_OISS4_MSK, oc_config->oc_idle << TIMER_CON2_OISS4_POS);
3393 }
3394
3395 WRITE_REG(TIMERx->CCVAL4, oc_config->pulse);
3396 }
3397
3410 static void timer_ccx_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state)
3411 {
3412 assert_param(IS_TIMER_CC2_INSTANCE(TIMERx));
3413 assert_param(IS_TIMER_CHANNELS(ch));
3414
3415 switch (ch) {
3416 case TIMER_CHANNEL_1:
3417 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK, state << TIMER_CCEP_CC1EN_POS);
3418 break;
3419
3420 case TIMER_CHANNEL_2:
3421 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK, state << TIMER_CCEP_CC2EN_POS);
3422 break;
3423
3424 case TIMER_CHANNEL_3:
3425 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK, state << TIMER_CCEP_CC3EN_POS);
3426 break;
3427
3428 case TIMER_CHANNEL_4:
3429 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK, state << TIMER_CCEP_CC4EN_POS);
3430 break;
3431
3432 default:
3433 break;
3434 }
3435 }
3447 static void timer_ccxn_channel_cmd(TIMER_TypeDef* TIMERx, timer_channel_t ch, type_func_t state)
3448 {
3449 switch (ch) {
3450 case TIMER_CHANNEL_1:
3451 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1NEN_MSK, state << TIMER_CCEP_CC1NEN_POS);
3452 break;
3453
3454 case TIMER_CHANNEL_2:
3455 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2NEN_MSK, state << TIMER_CCEP_CC2NEN_POS);
3456 break;
3457
3458 case TIMER_CHANNEL_3:
3459 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3NEN_MSK, state << TIMER_CCEP_CC3NEN_POS);
3460 break;
3461
3462 default:
3463 break;
3464 }
3465
3466 }
3467
3477 static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity,
3478 timer_ic_select_t sel, uint32_t filter)
3479 {
3480 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC1EN_MSK);
3481 MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC1SSEL_MSK, sel << TIMER_CHMR1_CC1SSEL_POSS);
3482 MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS);
3483 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS);
3484
3485 return;
3486 }
3487
3496 static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter)
3497 {
3498 MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I1FLT_MSK, filter << TIMER_CHMR1_I1FLT_POSS);
3499 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC1POL_MSK, polarity << TIMER_CCEP_CC1POL_POS);
3500
3501 return;
3502 }
3503
3513 static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity,
3514 timer_ic_select_t sel, uint32_t filter)
3515 {
3516 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC2EN_MSK);
3517 MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_CC2SSEL_MSK, sel << TIMER_CHMR1_CC2SSEL_POSS);
3518 MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS);
3519 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS);
3520
3521 return;
3522 }
3523
3532 static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter)
3533 {
3534 MODIFY_REG(TIMERx->CHMR1, TIMER_CHMR1_I2FLT_MSK, filter << TIMER_CHMR1_I2FLT_POSS);
3535 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC2POL_MSK, polarity << TIMER_CCEP_CC2POL_POS);
3536 return;
3537 }
3538
3548 static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity,
3549 timer_ic_select_t sel, uint32_t filter)
3550 {
3551 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC3EN_MSK);
3552 MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC3SSEL_MSK, sel << TIMER_CHMR2_CC3SSEL_POSS);
3553 MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I3FLT_MSK, filter << TIMER_CHMR2_I3FLT_POSS);
3554 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC3POL_MSK, polarity << TIMER_CCEP_CC3POL_POS);
3555
3556 return;
3557 }
3558
3568 static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity,
3569 timer_ic_select_t sel, uint32_t filter)
3570 {
3571 CLEAR_BIT(TIMERx->CCEP, TIMER_CCEP_CC4EN_MSK);
3572 MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_CC4SSEL_MSK, sel << TIMER_CHMR2_CC4SSEL_POSS);
3573 MODIFY_REG(TIMERx->CHMR2, TIMER_CHMR2_I4FLT_MSK, filter << TIMER_CHMR2_I4FLT_POSS);
3574 MODIFY_REG(TIMERx->CCEP, TIMER_CCEP_CC4POL_MSK, polarity << TIMER_CCEP_CC4POL_POS);
3575 return;
3576 }
3577
3587 static void timer_etr_set_config(TIMER_TypeDef* TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter)
3588 {
3589 MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETFLT_MSK, filter << TIMER_SMCON_ETFLT_POSS);
3590 MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPSEL_MSK, psc << TIMER_SMCON_ETPSEL_POSS);
3591 CLEAR_BIT(TIMERx->SMCON, TIMER_SMCON_ECM2EN_MSK);
3592 MODIFY_REG(TIMERx->SMCON, TIMER_SMCON_ETPOL_MSK, polarity << TIMER_SMCON_ETPOL_POS);
3593 return;
3594 }
3595
3603 static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t *config)
3604 {
3605 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_TSSEL_MSK, config->input << TIMER_SMCON_TSSEL_POSS);
3606 MODIFY_REG(hperh->perh->SMCON, TIMER_SMCON_SMODS_MSK, config->mode << TIMER_SMCON_SMODS_POSS);
3607
3608 switch (config->input) {
3609 case TIMER_TS_ETRF:
3610 timer_etr_set_config(hperh->perh, config->psc, config->polarity, config->filter);
3611 break;
3612
3613 case TIMER_TS_TI1F_ED:
3614 CLEAR_BIT(hperh->perh->CCEP, TIMER_CCEP_CC1EN_MSK);
3615 MODIFY_REG(hperh->perh->CHMR1, TIMER_CHMR1_I1FLT_MSK, config->filter << TIMER_CHMR1_I1FLT_POSS);
3616 break;
3617
3618 case TIMER_TS_TI1FP1:
3619 timer_ti1_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter);
3620 break;
3621
3622 case TIMER_TS_TI2FP2:
3623 timer_ti2_set_config_stage(hperh->perh, (timer_ic_polarity_t)config->polarity, config->filter);
3624 break;
3625
3626 default:
3627 break;
3628 }
3629 }
3630
3631 #ifdef ALD_DMA
3632
3640 static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config)
3641 {
3642 #if defined (ES32F36xx)
3643 if (hperh == AD16C4T0)
3644 config->msel = DMA_MSEL_TIMER0;
3645 if (hperh == AD16C4T1)
3646 config->msel = DMA_MSEL_TIMER1;
3647 if (hperh == GP32C4T0)
3648 config->msel = DMA_MSEL_TIMER2;
3649 if (hperh == GP32C4T1)
3650 config->msel = DMA_MSEL_TIMER3;
3651 if (hperh == BS16T0)
3652 config->msel = DMA_MSEL_TIMER4;
3653 if (hperh == BS16T1)
3654 config->msel = DMA_MSEL_TIMER5;
3655 if (hperh == GP32C4T0)
3656 config->msel = DMA_MSEL_TIMER6;
3657 if (hperh == GP32C4T1)
3658 config->msel = DMA_MSEL_TIMER7;
3659 #elif defined(ES32F39xx) || defined(ES32F336x)
3660 if (hperh == GP16C4T0)
3661 config->msel = DMA_MSEL_TIMER0;
3662 if (hperh == GP16C4T1)
3663 config->msel = DMA_MSEL_TIMER1;
3664 if (hperh == GP32C4T0)
3665 config->msel = DMA_MSEL_TIMER2;
3666 if (hperh == GP32C4T1)
3667 config->msel = DMA_MSEL_TIMER3;
3668 if (hperh == BS16T0)
3669 config->msel = DMA_MSEL_TIMER4;
3670 if (hperh == BS16T1)
3671 config->msel = DMA_MSEL_TIMER5;
3672 if (hperh == GP16C4T2)
3673 config->msel = DMA_MSEL_TIMER6;
3674 if (hperh == GP16C4T3)
3675 config->msel = DMA_MSEL_TIMER7;
3676 #endif
3677 }
3678
3679 #endif
3680
3684 #endif /* ALD_TIMER */
3685
timer_clock_config_t::source
timer_clock_source_t source
Definition: ald_timer.h:350
TIMER_OC_MODE_PWM2
Definition: ald_timer.h:71
DMA_MSIGSEL_TIMER_CH1
Definition: ald_dma.h:145
ald_timer_com_event_config
void ald_timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi)
Configure the TIMER commutation event sequence.
Definition: ald_timer.c:2834
TIMER_IT_CC1
Definition: ald_timer.h:493
timer_handle_s::capture_cbk
void(* capture_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:196
ald_timer_base_start_by_it
void ald_timer_base_start_by_it(timer_handle_t *hperh)
Starts the TIMER Base generation in interrupt mode.
Definition: ald_timer.c:170
timer_one_pulse_init_t::oc_polarity
timer_oc_polarity_t oc_polarity
Definition: ald_timer.h:272
timer_oc3_set_config
static void timer_oc3_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
Time Ouput Compare 3 configuration.
Definition: ald_timer.c:3351
DMA_MSEL_TIMER2
Definition: ald_dma.h:96
timer_break_dead_time_t::off_run
type_func_t off_run
Definition: ald_timer.h:427
timer_oc_init_t::oc_idle
timer_oc_idle_t oc_idle
Definition: ald_timer.h:153
timer_ts_t
timer_ts_t
TIMER ts definition.
Definition: ald_timer.h:373
TIMER_TRGO_OC2REF
Definition: ald_timer.h:461
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ENABLE
Definition: type.h:49
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
ald_timer_slave_config_sync
ald_status_t ald_timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config)
Configures the TIMER in Slave mode.
Definition: ald_timer.c:2621
ald_timer_set_output_mode
void ald_timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch)
Sets TIMER output mode.
Definition: ald_timer.c:2745
ald_timer_hall_sensor_stop_by_dma
void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh)
Stops the TIMER hall sensor interface in DMA mode.
Definition: ald_timer.c:1759
timer_ic_init_t::psc
timer_ic_prescaler_t psc
Definition: ald_timer.h:262
TIMER_ACTIVE_CHANNEL_3
Definition: ald_timer.h:174
ald_timer_pwmn_start
void ald_timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER PWM signal generation on the complementary output.
Definition: ald_timer.c:2073
ald_timer_one_pulse_n_start_by_it
void ald_timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER one pulse signal generation on the complementary output. in interrupt mode...
Definition: ald_timer.c:2222
timer_handle_s::trigger_cbk
void(* trigger_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:198
timer_base_init_t::re_cnt
uint32_t re_cnt
Definition: ald_timer.h:141
TIMER_IC_SEL_DIRECT
Definition: ald_timer.h:226
timer_handle_s::hdma2
dma_handle_t hdma2
Definition: ald_timer.h:191
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
IS_TIMER_IT
#define IS_TIMER_IT(x)
Definition: ald_timer.h:959
assert_param
#define assert_param(x)
Definition: type.h:88
TIMER_CHANNEL_3
Definition: ald_timer.h:112
BUSY
Definition: utils.h:57
ald_timer_base_start_by_dma
ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER Base generation in DMA mode.
Definition: ald_timer.c:204
DMA_MSEL_TIMER4
Definition: ald_dma.h:100
ald_timer_ic_stop_by_it
void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Input Capture measurement in interrupt mode.
Definition: ald_timer.c:934
TIMER_IT_CC4
Definition: ald_timer.h:496
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
IS_TIMER_EVENT_SOURCE
#define IS_TIMER_EVENT_SOURCE(x)
Definition: ald_timer.h:929
READ_REG
#define READ_REG(reg)
Definition: type.h:73
ald_timer_one_pulse_n_start
void ald_timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER one pulse signal generation on the complementary output.
Definition: ald_timer.c:2193
DMA_MSIGSEL_TIMER_UPDATE
Definition: ald_dma.h:151
SET
Definition: type.h:39
TIMER_ACTIVE_CHANNEL_2
Definition: ald_timer.h:173
timer_master_config_t::sel
timer_master_mode_sel_t sel
Definition: ald_timer.h:470
TIMER_STATE_RESET
Definition: ald_timer.h:161
timer_base_init_t::clk_div
timer_clock_division_t clk_div
Definition: ald_timer.h:140
ald_timer_pwm_set_input
void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch)
Set capture the PWM.
Definition: ald_timer.c:776
timer_handle_s::break_cbk
void(* break_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:199
timer_clock_polarity_t
timer_clock_polarity_t
TIMER clock polarity.
Definition: ald_timer.h:338
IS_TIMER_COUNTER_MODE
#define IS_TIMER_COUNTER_MODE(x)
Definition: ald_timer.h:847
type_func_t
type_func_t
Definition: type.h:47
timer_ic_init_t::polarity
timer_ic_polarity_t polarity
Definition: ald_timer.h:260
TIMER_STATE_READY
Definition: ald_timer.h:162
DISABLE
Definition: type.h:48
timer_encoder_init_t::ic1_polarity
timer_ic_polarity_t ic1_polarity
Definition: ald_timer.h:246
ald_timer_config_clock_source
ald_status_t ald_timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config)
Configures the clock source to be used.
Definition: ald_timer.c:2518
TIMER_DMA_TRIGGER
Definition: ald_timer.h:512
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
TIMER_TS_TI1FP1
Definition: ald_timer.h:379
TIMER_SRC_ITR1
Definition: ald_timer.h:327
ald_timer_get_state
timer_state_t ald_timer_get_state(timer_handle_t *hperh)
Return the TIMER Base state.
Definition: ald_timer.c:3168
ald_timer_pwm_start_by_it
void ald_timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
Starts the PWM signal generation in interrupt mode.
Definition: ald_timer.c:659
ald_timer_base_init
ald_status_t ald_timer_base_init(timer_handle_t *hperh)
Initializes the TIMER Time base Unit according to the specified parameters in the timer_handle_t and ...
Definition: ald_timer.c:97
timer_channel_config_t::n_en
type_func_t n_en
Definition: ald_timer.h:441
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
ald_timer_hall_sensor_start_by_it
void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh)
Starts the TIMER hall sensor interface in interrupt mode.
Definition: ald_timer.c:1678
timer_ti1_set_config_stage
static void timer_ti1_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter)
Configure the Polarity and Filter for TI1.
Definition: ald_timer.c:3496
timer_ccxn_channel_cmd
static void timer_ccxn_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel xN.
Definition: ald_timer.c:3447
timer_oc_init_t::oc_fast_en
type_func_t oc_fast_en
Definition: ald_timer.h:152
ald_timer_interrupt_config
void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts.
Definition: ald_timer.c:3075
dma_config_t::src
void * src
Definition: ald_dma.h:278
timer_dma_oc_cplt
static void timer_dma_oc_cplt(void *arg)
TIMER DMA out compare complete callback.
Definition: ald_timer.c:3189
timer_clear_input_config_t::state
type_func_t state
Definition: ald_timer.h:313
ald_timer_com_change_config
void ald_timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config)
Configure the channel in commutation event.
Definition: ald_timer.c:2777
timer_clock_config_t::psc
timer_etr_psc_t psc
Definition: ald_timer.h:352
timer_dma_msel
static void timer_dma_msel(TIMER_TypeDef *hperh, dma_config_t *config)
Timer DMA msel signal configuration.
Definition: ald_timer.c:3640
ald_timer_oc_stop_by_it
void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Output Compare signal generation in interrupt mode.
Definition: ald_timer.c:400
TIMER_SRC_INTER
Definition: ald_timer.h:325
TIMER_TS_TI1F_ED
Definition: ald_timer.h:378
ald_timer_pwm_stop
void ald_timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch)
Stops the PWM signal generation.
Definition: ald_timer.c:642
TIMER_IC_SEL_TRC
Definition: ald_timer.h:228
timer_op_output_channel_t
timer_op_output_channel_t
TIMER one pulse output channel.
Definition: ald_timer.h:128
TIMER_FLAG_CC1
Definition: ald_timer.h:520
timer_dma_period_elapse_cplt
static void timer_dma_period_elapse_cplt(void *arg)
TIMER DMA Period Elapse complete callback.
Definition: ald_timer.c:3224
timer_hall_sensor_init_t::psc
timer_ic_prescaler_t psc
Definition: ald_timer.h:400
IS_TIMER_ETR_PSC
#define IS_TIMER_ETR_PSC(x)
Definition: ald_timer.h:900
IS_TIMER_OCNIDLE_STATE
#define IS_TIMER_OCNIDLE_STATE(x)
Definition: ald_timer.h:871
timer_clock_config_t
TIMER clock config structure definition.
Definition: ald_timer.h:349
ald_timer_break_dead_time_config
void ald_timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config)
Configure the break, dead timere, lock level state.
Definition: ald_timer.c:2875
TIMER_CHANNEL_1
Definition: ald_timer.h:110
ald_timer_pwmn_start_by_dma
ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER PWM signal generation on the complementary output. in DMA mode.
Definition: ald_timer.c:2140
timer_base_init_t::period
uint32_t period
Definition: ald_timer.h:139
ald_timer_clear_flag_status
void ald_timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag)
Clear the TIMER interrupt flag.
Definition: ald_timer.c:3136
ald_timer_oc_init
ald_status_t ald_timer_oc_init(timer_handle_t *hperh)
Initializes the TIMER Output Compare according to the specified parameters in the timer_handle_t and ...
Definition: ald_timer.c:290
timer_handle_s::init
timer_base_init_t init
Definition: ald_timer.h:184
timer_slave_config_t::mode
timer_slave_mode_t mode
Definition: ald_timer.h:388
timer_oc_init_t::ocn_polarity
timer_ocn_polarity_t ocn_polarity
Definition: ald_timer.h:151
timer_clear_input_config_t::psc
timer_etr_psc_t psc
Definition: ald_timer.h:316
TIMER_IT_CC2
Definition: ald_timer.h:494
timer_one_pulse_init_t::polarity
timer_ic_polarity_t polarity
Definition: ald_timer.h:276
ald_timer_slave_config_sync_by_it
ald_status_t ald_timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config)
Configures the TIMER in Slave mode in interrupt mode.
Definition: ald_timer.c:2651
UNLOCK
Definition: type.h:59
timer_clock_config_t::polarity
timer_clock_polarity_t polarity
Definition: ald_timer.h:351
ald_timer_pwmn_stop
void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER PWM signal generation on the complementary output.
Definition: ald_timer.c:2088
ald_timer_read_capture_value
uint32_t ald_timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch)
Read the captured value from Capture Compare unit.
Definition: ald_timer.c:2703
TIMER_ENABLE
#define TIMER_ENABLE(hperh)
Enable the TIMER peripheral.
Definition: ald_timer.h:550
TIMER_STATE_BUSY
Definition: ald_timer.h:163
timer_break_dead_time_t::off_idle
type_func_t off_idle
Definition: ald_timer.h:428
IS_TIMER_OP_MODE
#define IS_TIMER_OP_MODE(x)
Definition: ald_timer.h:878
timer_slave_config_t::psc
timer_etr_psc_t psc
Definition: ald_timer.h:391
TIMER_SRC_ETRMODE1
Definition: ald_timer.h:333
ald_timer_ocn_start
void ald_timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER output compare signal generation on the complementary output.
Definition: ald_timer.c:1804
RESET
Definition: type.h:38
IS_TIMER_OC_MODE
#define IS_TIMER_OC_MODE(x)
Definition: ald_timer.h:857
ald_timer_ocn_stop_by_dma
void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER output compare signal generation on the complementary output. in DMA mode...
Definition: ald_timer.c:2012
timer_handle_s::hdma1
dma_handle_t hdma1
Definition: ald_timer.h:190
timer_dma_error
static void timer_dma_error(void *arg)
TIMER DMA error callback.
Definition: ald_timer.c:3240
DMA_MSEL_TIMER6
Definition: ald_dma.h:102
ald_timer_pwm_stop_by_it
void ald_timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
Stops the PWM signal generation in interrupt mode.
Definition: ald_timer.c:676
ald_timer_base_reset
void ald_timer_base_reset(timer_handle_t *hperh)
Reset the TIMER base peripheral.
Definition: ald_timer.c:121
timer_handle_s::com_cbk
void(* com_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:200
DMA_MSIGSEL_TIMER_CH4
Definition: ald_dma.h:148
timer_handle_s
TIMER time base handle structure definition.
Definition: ald_timer.h:182
ald_timer_get_flag_status
flag_status_t ald_timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag)
Get the status of TIMER interrupt flag.
Definition: ald_timer.c:3118
timer_clear_input_config_t::source
timer_clear_input_source_t source
Definition: ald_timer.h:314
timer_one_pulse_init_t::pulse
uint16_t pulse
Definition: ald_timer.h:271
ald_timer_oc_stop_by_dma
void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Output Compare signal generation in DMA mode.
Definition: ald_timer.c:544
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
TIMER_ETR_PSC_DIV1
Definition: ald_timer.h:298
dma_config_t
DMA channal configure structure.
Definition: ald_dma.h:277
ald_timer_oc_config_channel
ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t *config, timer_channel_t ch)
Initializes the TIMER Output Compare Channels according to the specified parameters in the timer_oc_i...
Definition: ald_timer.c:2281
ald_timer_ic_stop_by_dma
void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Input Capture measurement in DMA mode.
Definition: ald_timer.c:1060
DMA_MSEL_TIMER7
Definition: ald_dma.h:103
ald_timer_pwm_set_freq
void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq)
Set the PWM freq.
Definition: ald_timer.c:726
timer_it_t
timer_it_t
TIMER interrupt definition.
Definition: ald_timer.h:491
timer_op_mode_t
timer_op_mode_t
TIMER one pulse mode.
Definition: ald_timer.h:120
timer_encoder_init_t::ic2_filter
uint32_t ic2_filter
Definition: ald_timer.h:253
ald_timer_base_start
void ald_timer_base_start(timer_handle_t *hperh)
Starts the TIMER Base generation.
Definition: ald_timer.c:138
TIMER_TS_ETRF
Definition: ald_timer.h:381
timer_encoder_init_t::ic1_filter
uint32_t ic1_filter
Definition: ald_timer.h:249
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_etr_psc_t
timer_etr_psc_t
TIMER clear input polarity.
Definition: ald_timer.h:297
timer_encoder_init_t::mode
timer_encoder_mode_t mode
Definition: ald_timer.h:245
ald_timer_base_stop_by_it
void ald_timer_base_stop_by_it(timer_handle_t *hperh)
Stops the TIMER Base generation in interrupt mode.
Definition: ald_timer.c:185
timer_one_pulse_init_t::ocn_polarity
timer_ocn_polarity_t ocn_polarity
Definition: ald_timer.h:273
timer_oc_init_t
TIMER output compare configuration structure definition.
Definition: ald_timer.h:147
timer_break_dead_time_t::break_state
type_func_t break_state
Definition: ald_timer.h:431
TIMER_FLAG_CC3
Definition: ald_timer.h:522
TIMER_DISABLE
#define TIMER_DISABLE(hperh)
Disable the TIMER peripheral.
Definition: ald_timer.h:560
timer_oc_init_t::ocn_idle
timer_ocn_idle_t ocn_idle
Definition: ald_timer.h:154
timer_ti2_set_config
static void timer_ti2_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, timer_ic_select_t sel, uint32_t filter)
Configure the TI2 as Input.
Definition: ald_timer.c:3513
TIMER_TS_TI2FP2
Definition: ald_timer.h:380
timer_encoder_init_t::ic2_sel
timer_ic_select_t ic2_sel
Definition: ald_timer.h:251
TIMER_DMA_CC2
Definition: ald_timer.h:508
it_status_t
enum flag_status_t it_status_t
TIMER_MOE_DISABLE
#define TIMER_MOE_DISABLE(hperh)
Disable the TIMER main output.
Definition: ald_timer.h:572
timer_slave_config_t::polarity
timer_clock_polarity_t polarity
Definition: ald_timer.h:390
timer_oc_init_t::oc_polarity
timer_oc_polarity_t oc_polarity
Definition: ald_timer.h:150
IS_TIMER_FLAG
#define IS_TIMER_FLAG(x)
Definition: ald_timer.h:974
TIMER_CLK_POLARITY_NO_INV
Definition: ald_timer.h:340
ald_timer_ocn_stop
void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER output compare signal generation on the complementary output.
Definition: ald_timer.c:1825
timer_one_pulse_init_t::sel
timer_ic_select_t sel
Definition: ald_timer.h:277
ald_timer_one_pulse_start
void ald_timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch)
Starts the TIMER One Pulse signal generation.
Definition: ald_timer.c:1151
ald_timer_ic_start
void ald_timer_ic_start(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Input Capture measurement.
Definition: ald_timer.c:857
TIMER_DMA_UPDATE
Definition: ald_timer.h:506
ald_timer_encoder_start
void ald_timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Encoder Interface.
Definition: ald_timer.c:1318
ald_timer_pwm_stop_by_dma
void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER PWM signal generation in DMA mode.
Definition: ald_timer.c:714
timer_base_set_config
static void timer_base_set_config(TIMER_TypeDef *TIMERx, timer_base_init_t *init)
Time Base configuration.
Definition: ald_timer.c:3258
ald_timer_pwm_set_duty
void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty)
Set the PWM duty.
Definition: ald_timer.c:750
TIMER_OCN_POLARITY_HIGH
Definition: ald_timer.h:86
ald_timer_hall_sensor_stop_by_it
void ald_timer_hall_sensor_stop_by_it(timer_handle_t *hperh)
Stops the TIMER hall sensor interface in interrupt mode.
Definition: ald_timer.c:1694
IS_TIMER_IC_FILTER
#define IS_TIMER_IC_FILTER(x)
Definition: ald_timer.h:894
timer_slave_config_t
TIMER slave configuration structure definition.
Definition: ald_timer.h:387
timer_one_pulse_init_t::mode
timer_oc_mode_t mode
Definition: ald_timer.h:270
ald_timer_encoder_start_by_dma
ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf1, uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2)
Starts the TIMER Encoder Interface in DMA mode.
Definition: ald_timer.c:1457
ald_timer_oc_start_by_it
void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Output Compare signal generation in interrupt mode.
Definition: ald_timer.c:355
ald_timer_oc_stop
void ald_timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Output Compare signal generation.
Definition: ald_timer.c:330
timer_event_source_t
timer_event_source_t
Specifies the event source.
Definition: ald_timer.h:477
IS_TIMER_IC_SELECT
#define IS_TIMER_IC_SELECT(x)
Definition: ald_timer.h:887
timer_one_pulse_init_t::oc_idle
timer_oc_idle_t oc_idle
Definition: ald_timer.h:274
IS_TIMER_IC_PSC
#define IS_TIMER_IC_PSC(x)
Definition: ald_timer.h:890
timer_channel_config_t::mode
timer_oc_mode_t mode
Definition: ald_timer.h:442
timer_base_init_t::prescaler
uint32_t prescaler
Definition: ald_timer.h:137
timer_oc_mode_t
timer_oc_mode_t
TIMER output compare and PWM modes.
Definition: ald_timer.h:63
TIMER_SRC_ITR3
Definition: ald_timer.h:329
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
TIMER_ACTIVE_CHANNEL_CLEARED
Definition: ald_timer.h:176
TIMER_SRC_TI1
Definition: ald_timer.h:331
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
TIMER_FLAG_CC4
Definition: ald_timer.h:523
TIMER_INPUT_NONE
Definition: ald_timer.h:284
IS_TIMER_CLEAR_INPUT_POLARITY
#define IS_TIMER_CLEAR_INPUT_POLARITY(x)
Definition: ald_timer.h:898
DMA_MSIGSEL_TIMER_CH2
Definition: ald_dma.h:146
ald_timer_ic_start_by_dma
ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER Input Capture measurement in DMA mode.
Definition: ald_timer.c:975
TIMER_IT_BREAK
Definition: ald_timer.h:499
timer_break_dead_time_t
TIMER break and dead time configuretion structure definition.
Definition: ald_timer.h:426
IS_TIMER_CHANNELS
#define IS_TIMER_CHANNELS(x)
Definition: ald_timer.h:873
timer_flag_t
timer_flag_t
TIMER flag definition.
Definition: ald_timer.h:518
ald_timer_get_it_status
it_status_t ald_timer_get_it_status(timer_handle_t *hperh, timer_it_t it)
Get the status of TIMER interrupt source.
Definition: ald_timer.c:3098
IS_TIMER_DMA_REQ
#define IS_TIMER_DMA_REQ(x)
Definition: ald_timer.h:967
timer_ti2_set_config_stage
static void timer_ti2_set_config_stage(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, uint32_t filter)
Configure the Polarity and Filter for TI2.
Definition: ald_timer.c:3532
timer_state_t
timer_state_t
State structures definition.
Definition: ald_timer.h:160
TIMER_CNT_MODE_UP
Definition: ald_timer.h:44
ald_cmu.h
Header file of CMU module driver.
timer_ccx_channel_cmd
static void timer_ccx_channel_cmd(TIMER_TypeDef *TIMERx, timer_channel_t ch, type_func_t state)
Enables or disables the TIMER Capture Compare Channel x.
Definition: ald_timer.c:3410
ald_timer_master_sync_config
void ald_timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config)
Configure the master mode.
Definition: ald_timer.c:2908
timer_channel_config_t::en
type_func_t en
Definition: ald_timer.h:440
ald_timer_one_pulse_start_by_it
void ald_timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch)
Starts the TIMER One Pulse signal generation in interrupt mode.
Definition: ald_timer.c:1198
timer_clear_input_config_t::clrsel
timer_chnref_clr_sel_t clrsel
Definition: ald_timer.h:317
TIMER_TS_ITR2
Definition: ald_timer.h:376
ald_timer_encoder_stop_by_dma
void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Encoder Interface in DMA mode.
Definition: ald_timer.c:1552
timer_dma_req_t
timer_dma_req_t
TIMER DMA request.
Definition: ald_timer.h:505
timer_master_config_t::master_en
type_func_t master_en
Definition: ald_timer.h:471
TIMER_SRC_ITR2
Definition: ald_timer.h:328
ald_timer_oc_start_by_dma
ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER Output Compare signal generation in DMA mode.
Definition: ald_timer.c:454
TIMER_SRC_TI2
Definition: ald_timer.h:332
ald_timer_com_event_config_it
void ald_timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi)
Configure the TIMER commutation event sequence with interrupt.
Definition: ald_timer.c:2863
IS_TIMER_CHNREF_CLEAR
#define IS_TIMER_CHNREF_CLEAR(X)
Definition: ald_timer.h:904
TIMER_MODE_RESET
Definition: ald_timer.h:364
timer_ic_polarity_t
timer_ic_polarity_t
TIMER input capture polarity.
Definition: ald_timer.h:217
timer_encoder_init_t::ic1_psc
timer_ic_prescaler_t ic1_psc
Definition: ald_timer.h:248
TIMER_OC_POLARITY_HIGH
Definition: ald_timer.h:78
TIMER_DMA_CC3
Definition: ald_timer.h:509
timer_hall_sensor_init_t
TIMER hall sensor configuretion structure definition.
Definition: ald_timer.h:398
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
IS_TIMER_MASTER_MODE_SEL
#define IS_TIMER_MASTER_MODE_SEL(x)
Definition: ald_timer.h:951
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
TIMER_IC_SEL_INDIRECT
Definition: ald_timer.h:227
timer_dma_capture_cplt
static void timer_dma_capture_cplt(void *arg)
TIMER DMA Capture complete callback.
Definition: ald_timer.c:3208
timer_encoder_init_t
TIMER encoder configuration structure definition.
Definition: ald_timer.h:244
DMA_MSEL_TIMER0
Definition: ald_dma.h:94
TIMER_FLAG_TRIGGER
Definition: ald_timer.h:525
ald_timer_irq_handler
void ald_timer_irq_handler(timer_handle_t *hperh)
This function handles TIMER interrupts requests.
Definition: ald_timer.c:2927
ald_timer_hall_sensor_init
ald_status_t ald_timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config)
Initializes the TIMER Encoder Interface and create the associated handle.
Definition: ald_timer.c:1608
ald_timer_oc_start
void ald_timer_oc_start(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Output Compare signal generation.
Definition: ald_timer.c:306
ald_timer_ic_start_by_it
void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Input Capture measurement in interrupt mode.
Definition: ald_timer.c:897
TIMER_OC_IDLE_RESET
Definition: ald_timer.h:94
TIMER_FLAG_CC2
Definition: ald_timer.h:521
TIMER_IC_POLARITY_RISE
Definition: ald_timer.h:218
TIMER_CHANNEL_4
Definition: ald_timer.h:113
DMA_MSIGSEL_TIMER_CH3
Definition: ald_dma.h:147
DMA_MSEL_TIMER3
Definition: ald_dma.h:97
timer_base_init_t
TIMER time base configuration structure definition.
Definition: ald_timer.h:136
ald_timer_one_pulse_n_stop
void ald_timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER one pulse signal generation on the complementary output.
Definition: ald_timer.c:2207
timer_oc1_set_config
static void timer_oc1_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
Time Ouput Compare 1 configuration.
Definition: ald_timer.c:3289
timer_clear_input_config_t::filter
uint32_t filter
Definition: ald_timer.h:318
timer_oc_init_t::pulse
uint32_t pulse
Definition: ald_timer.h:149
timer_slave_config_t::input
timer_ts_t input
Definition: ald_timer.h:389
timer_hall_sensor_init_t::polarity
timer_ic_polarity_t polarity
Definition: ald_timer.h:399
ald_timer_hall_sensor_start
void ald_timer_hall_sensor_start(timer_handle_t *hperh)
Starts the TIMER hall sensor interface.
Definition: ald_timer.c:1648
TIMER_IT_CC3
Definition: ald_timer.h:495
ald_cmu_get_pclk1_clock
uint32_t ald_cmu_get_pclk1_clock(void)
Get APB1 clock.
Definition: ald_cmu.c:627
ald_timer_ocn_stop_by_it
void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER output compare signal generation on the complementary output. in interrupt mode...
Definition: ald_timer.c:1886
TIMER_IT_TRIGGER
Definition: ald_timer.h:498
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
ald_timer_pwm_start_by_dma
ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER PWM signal generation in DMA mode.
Definition: ald_timer.c:697
timer_one_pulse_init_t::ocn_idle
timer_ocn_idle_t ocn_idle
Definition: ald_timer.h:275
IS_TIMER_CLOCK_SOURCE
#define IS_TIMER_CLOCK_SOURCE(x)
Definition: ald_timer.h:906
timer_oc_init_t::oc_mode
timer_oc_mode_t oc_mode
Definition: ald_timer.h:148
DMA_MSEL_TIMER1
Definition: ald_dma.h:95
timer_master_config_t
TIMER master configuretion structure definition.
Definition: ald_timer.h:469
IS_TIMER_OCIDLE_STATE
#define IS_TIMER_OCIDLE_STATE(x)
Definition: ald_timer.h:869
timer_handle_s::error_cbk
void(* error_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:201
timer_handle_s::delay_elapse_cbk
void(* delay_elapse_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:195
timer_ti1_set_config
static void timer_ti1_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, timer_ic_select_t sel, uint32_t filter)
Configure the TI1 as Input.
Definition: ald_timer.c:3477
timer_clear_input_config_t
TIMER clear input configuration handle structure definition.
Definition: ald_timer.h:312
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
ald_timer_base_stop_by_dma
void ald_timer_base_stop_by_dma(timer_handle_t *hperh)
Stops the TIMER Base generation in DMA mode.
Definition: ald_timer.c:249
TIMER_ACTIVE_CHANNEL_1
Definition: ald_timer.h:172
ald_timer_pwm_init
ald_status_t ald_timer_pwm_init(timer_handle_t *hperh)
Initializes the TIMER PWM Time Base according to the specified parameters in the timer_handle_t and c...
Definition: ald_timer.c:609
timer_clear_input_config_t::polarity
timer_clear_input_polarity_t polarity
Definition: ald_timer.h:315
timer_com_channel_config_t::ch
timer_channel_config_t ch[3]
Definition: ald_timer.h:449
timer_oc4_set_config
static void timer_oc4_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
Time Ouput Compare 4 configuration.
Definition: ald_timer.c:3382
TIMER_IT_UPDATE
Definition: ald_timer.h:492
ald_timer_hall_sensor_start_by_dma
ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER hall sensor interface in DMA mode.
Definition: ald_timer.c:1714
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
timer_handle_s::ch
timer_active_channel_t ch
Definition: ald_timer.h:185
TIMER_MODE_TRIG
Definition: ald_timer.h:366
ald_timer_pwmn_start_by_it
void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER PWM signal generation on the complementary output. in interrupt mode.
Definition: ald_timer.c:2104
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
ald_timer_ocn_start_by_dma
ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER output compare signal generation on the complementary output. in DMA mode...
Definition: ald_timer.c:1934
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
timer_handle_s::pwm_pulse_finish_cbk
void(* pwm_pulse_finish_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:197
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
ald_timer_base_stop
void ald_timer_base_stop(timer_handle_t *hperh)
Stops the TIMER Base generation.
Definition: ald_timer.c:154
TIMER_MODE_EXTERNAL1
Definition: ald_timer.h:367
TIMER_TS_ITR1
Definition: ald_timer.h:375
IS_TIMER_TS
#define IS_TIMER_TS(x)
Definition: ald_timer.h:937
timer_hall_sensor_init_t::filter
uint32_t filter
Definition: ald_timer.h:401
TIMER_SRC_ETRMODE2
Definition: ald_timer.h:324
TIMER_CHNREF_CLR_CMP_IN
Definition: ald_timer.h:307
ald_timer_pwm_start
void ald_timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch)
Starts the PWM signal generation.
Definition: ald_timer.c:625
timer_slave_config_t::filter
uint32_t filter
Definition: ald_timer.h:392
TIMER_FLAG_BREAK
Definition: ald_timer.h:526
ald_timer_encoder_start_by_it
void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Encoder Interface in interrupt mode.
Definition: ald_timer.c:1380
ald_timer_ocn_start_by_it
void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER output compare signal generation on the complementary output. in interrupt mode...
Definition: ald_timer.c:1847
TIMER_ACTIVE_CHANNEL_4
Definition: ald_timer.h:175
TIMER_FLAG_COM
Definition: ald_timer.h:524
timer_ic_init_t::filter
uint32_t filter
Definition: ald_timer.h:263
TIMER_IC_POLARITY_FALL
Definition: ald_timer.h:219
timer_break_dead_time_t::polarity
timer_break_polarity_t polarity
Definition: ald_timer.h:432
timer_hall_sensor_init_t::delay
uint32_t delay
Definition: ald_timer.h:402
timer_break_dead_time_t::dead_time
uint32_t dead_time
Definition: ald_timer.h:430
ald_timer_generate_event
ald_status_t ald_timer_generate_event(timer_handle_t *hperh, timer_event_source_t event)
Generate a software event.
Definition: ald_timer.c:2678
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
timer_slave_set_config
static void timer_slave_set_config(timer_handle_t *hperh, timer_slave_config_t *config)
Time Slave configuration.
Definition: ald_timer.c:3603
flag_status_t
flag_status_t
Definition: type.h:37
TIMER_FLAG_UPDATE
Definition: ald_timer.h:519
IS_TIMER_DEAD_TIMERE
#define IS_TIMER_DEAD_TIMERE(x)
Definition: ald_timer.h:895
IS_TIMER_ENCODER_MODE
#define IS_TIMER_ENCODER_MODE(x)
Definition: ald_timer.h:882
TIMER_CNT_MODE_DOWN
Definition: ald_timer.h:45
TIMER_TS_ITR0
Definition: ald_timer.h:374
timer_handle_s::period_elapse_cbk
void(* period_elapse_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:194
IS_TIMER_CLEAR_INPUT_SOURCE
#define IS_TIMER_CLEAR_INPUT_SOURCE(x)
Definition: ald_timer.h:896
timer_base_init_t::mode
timer_cnt_mode_t mode
Definition: ald_timer.h:138
ald_timer_ic_config_channel
ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t *config, timer_channel_t ch)
Initializes the TIMER Input Capture Channels according to the specified parameters in the timer_ic_in...
Definition: ald_timer.c:2329
timer_ic_init_t
TIMER input capture configuration structure definition.
Definition: ald_timer.h:259
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
ald_timer_encoder_init
ald_status_t ald_timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config)
Initializes the TIMER Encoder Interface and create the associated handle.
Definition: ald_timer.c:1269
IS_TIMER_CLOCK_POLARITY
#define IS_TIMER_CLOCK_POLARITY(x)
Definition: ald_timer.h:916
timer_encoder_init_t::ic2_psc
timer_ic_prescaler_t ic2_psc
Definition: ald_timer.h:252
IS_TIMER_CLOCK_LEVEL
#define IS_TIMER_CLOCK_LEVEL(x)
Definition: ald_timer.h:945
timer_ti3_set_config
static void timer_ti3_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, timer_ic_select_t sel, uint32_t filter)
Configure the TI3 as Input.
Definition: ald_timer.c:3548
ald_timer_dma_req_config
void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state)
Configure DMA request source.
Definition: ald_timer.c:3050
ald_timer_pwmn_stop_by_dma
void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER PWM signal generation on the complementary output. in DMA mode.
Definition: ald_timer.c:2157
timer_etr_set_config
static void timer_etr_set_config(TIMER_TypeDef *TIMERx, timer_etr_psc_t psc, timer_clock_polarity_t polarity, uint32_t filter)
Configures the TIMERx External Trigger (ETR).
Definition: ald_timer.c:3587
ald_timer_one_pulse_stop_by_it
void ald_timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch)
Stops the TIMER One Pulse signal generation in interrupt mode.
Definition: ald_timer.c:1226
ald_timer_one_pulse_init
ald_status_t ald_timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode)
Initializes the TIMER One Pulse Time Base according to the specified parameters in the timer_handle_t...
Definition: ald_timer.c:1121
TIMER_TS_ITR3
Definition: ald_timer.h:377
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
timer_encoder_init_t::ic2_polarity
timer_ic_polarity_t ic2_polarity
Definition: ald_timer.h:250
timer_break_dead_time_t::lock_level
timer_lock_level_t lock_level
Definition: ald_timer.h:429
IS_TIMER_CLOCK_DIVISION
#define IS_TIMER_CLOCK_DIVISION(x)
Definition: ald_timer.h:852
TIMER_DMA_CC1
Definition: ald_timer.h:507
TIMER_DMA_CC4
Definition: ald_timer.h:510
timer_handle_s::lock
lock_state_t lock
Definition: ald_timer.h:186
DMA_MSEL_TIMER5
Definition: ald_dma.h:101
IS_TIMER_OCN_POLARITY
#define IS_TIMER_OCN_POLARITY(x)
Definition: ald_timer.h:867
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
ald_timer_ic_init
ald_status_t ald_timer_ic_init(timer_handle_t *hperh)
Initializes the TIMER Input Capture Time base according to the specified parameters in the timer_hand...
Definition: ald_timer.c:841
IS_TIMER_BREAK_POLARITY
#define IS_TIMER_BREAK_POLARITY(x)
Definition: ald_timer.h:949
ald_timer_config_oc_ref_clear
ald_status_t ald_timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch)
Configures the OCRef clear feature.
Definition: ald_timer.c:2460
ald_timer_hall_sensor_stop
void ald_timer_hall_sensor_stop(timer_handle_t *hperh)
Stops the TIMER hall sensor interface.
Definition: ald_timer.c:1663
TIMER_MOE_ENABLE
#define TIMER_MOE_ENABLE(hperh)
Enable the TIMER main output.
Definition: ald_timer.h:555
timer_channel_t
timer_channel_t
TIMER channel.
Definition: ald_timer.h:109
IS_TIMER_SLAVE_MODE
#define IS_TIMER_SLAVE_MODE(x)
Definition: ald_timer.h:921
IS_TIMER_IC_POLARITY
#define IS_TIMER_IC_POLARITY(x)
Definition: ald_timer.h:885
ald_timer_config_ti1_input
ald_status_t ald_timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1...
Definition: ald_timer.c:2604
TIMER_IT_COM
Definition: ald_timer.h:497
ald_timer_ic_stop
void ald_timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Input Capture measurement.
Definition: ald_timer.c:877
__LOCK
#define __LOCK(x)
Definition: utils.h:92
timer_ic_init_t::sel
timer_ic_select_t sel
Definition: ald_timer.h:261
TIMER_SRC_ITR0
Definition: ald_timer.h:326
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
ald_timer_encoder_stop
void ald_timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Encoder Interface.
Definition: ald_timer.c:1349
ERROR
Definition: utils.h:56
timer_oc2_set_config
static void timer_oc2_set_config(TIMER_TypeDef *TIMERx, timer_oc_init_t *oc_config)
Time Ouput Compare 2 configuration.
Definition: ald_timer.c:3320
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
TIMER_CHANNEL_2
Definition: ald_timer.h:111
TIMER_SRC_TI1ED
Definition: ald_timer.h:330
IS_TIMER_OC_POLARITY
#define IS_TIMER_OC_POLARITY(x)
Definition: ald_timer.h:865
ald_timer_one_pulse_config_channel
ald_status_t ald_timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, timer_channel_t ch_out, timer_channel_t ch_in)
Initializes the TIMER One Pulse Channels according to the specified parameters in the timer_one_pulse...
Definition: ald_timer.c:2385
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
ald_timer.h
TIMER module driver. This is the common part of the TIMER initialization.
ald_timer_encoder_stop_by_it
void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Encoder Interface in interrupt mode.
Definition: ald_timer.c:1415
timer_ti4_set_config
static void timer_ti4_set_config(TIMER_TypeDef *TIMERx, timer_ic_polarity_t polarity, timer_ic_select_t sel, uint32_t filter)
Configure the TI4 as Input.
Definition: ald_timer.c:3568
timer_ic_select_t
timer_ic_select_t
TIMER input capture selection.
Definition: ald_timer.h:225
timer_clock_config_t::filter
uint32_t filter
Definition: ald_timer.h:353
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
TIMER_OCN_IDLE_RESET
Definition: ald_timer.h:102
ald_timer_pwmn_stop_by_it
void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER PWM signal generation on the complementary output. in interrupt mode.
Definition: ald_timer.c:2120
timer_encoder_init_t::ic1_sel
timer_ic_select_t ic1_sel
Definition: ald_timer.h:247
timer_com_channel_config_t
TIMER commutation event configuretion structure definition.
Definition: ald_timer.h:448
timer_one_pulse_init_t::filter
uint32_t filter
Definition: ald_timer.h:278
ald_timer_one_pulse_n_stop_by_it
void ald_timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER one pulse signal generation on the complementary output. in interrupt mode...
Definition: ald_timer.c:2237
ald_timer_one_pulse_stop
void ald_timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch)
Stops the TIMER One Pulse signal generation.
Definition: ald_timer.c:1177
timer_break_dead_time_t::auto_out
type_func_t auto_out
Definition: ald_timer.h:433
timer_one_pulse_init_t
TIMER one pulse mode configuration structure definition.
Definition: ald_timer.h:269


ALD User Manual: D:/svn/src/ald_timer.h Source File

  • D:
  • svn
  • src
ald_timer.h
Go to the documentation of this file.
1
18 #ifndef __ALD_TIMER_H__
19 #define __ALD_TIMER_H__
20
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24
25 #include "utils.h"
26 #include "ald_dma.h"
27
43 typedef enum {
44 TIMER_CNT_MODE_UP = 0U,
45 TIMER_CNT_MODE_DOWN = 1U,
46 TIMER_CNT_MODE_CENTER1 = 2U,
47 TIMER_CNT_MODE_CENTER2 = 3U,
48 TIMER_CNT_MODE_CENTER3 = 4U,
49 } timer_cnt_mode_t;
50
54 typedef enum {
55 TIMER_CLOCK_DIV1 = 0U,
56 TIMER_CLOCK_DIV2 = 1U,
57 TIMER_CLOCK_DIV4 = 2U,
58 } timer_clock_division_t;
59
63 typedef enum {
64 TIMER_OC_MODE_TIMERING = 0U,
65 TIMER_OC_MODE_ACTIVE = 1U,
66 TIMER_OC_MODE_INACTIVE = 2U,
67 TIMER_OC_MODE_TOGGLE = 3U,
68 TIMER_OC_MODE_FORCE_INACTIVE = 4U,
69 TIMER_OC_MODE_FORCE_ACTIVE = 5U,
70 TIMER_OC_MODE_PWM1 = 6U,
71 TIMER_OC_MODE_PWM2 = 7U,
72 } timer_oc_mode_t;
73
77 typedef enum {
78 TIMER_OC_POLARITY_HIGH = 0U,
79 TIMER_OC_POLARITY_LOW = 1U,
80 } timer_oc_polarity_t;
81
85 typedef enum {
86 TIMER_OCN_POLARITY_HIGH = 0U,
87 TIMER_OCN_POLARITY_LOW = 1U,
88 } timer_ocn_polarity_t;
89
93 typedef enum {
94 TIMER_OC_IDLE_RESET = 0U,
95 TIMER_OC_IDLE_SET = 1U,
96 } timer_oc_idle_t;
97
101 typedef enum {
102 TIMER_OCN_IDLE_RESET = 0U,
103 TIMER_OCN_IDLE_SET = 1U,
104 } timer_ocn_idle_t;
105
109 typedef enum {
110 TIMER_CHANNEL_1 = 0U,
111 TIMER_CHANNEL_2 = 1U,
112 TIMER_CHANNEL_3 = 2U,
113 TIMER_CHANNEL_4 = 3U,
114 TIMER_CHANNEL_ALL = 0xFU,
115 } timer_channel_t;
116
120 typedef enum {
121 TIMER_OP_MODE_REPEAT = 0U,
122 TIMER_OP_MODE_SINGLE = 1U,
123 } timer_op_mode_t;
124
128 typedef enum {
129 TIMER_OP_OUTPUT_CHANNEL_1 = 0U,
130 TIMER_OP_OUTPUT_CHANNEL_2 = 1U,
131 } timer_op_output_channel_t;
132
136 typedef struct {
137 uint32_t prescaler;
138 timer_cnt_mode_t mode;
139 uint32_t period;
140 timer_clock_division_t clk_div;
141 uint32_t re_cnt;
142 } timer_base_init_t;
143
147 typedef struct {
148 timer_oc_mode_t oc_mode;
149 uint32_t pulse;
150 timer_oc_polarity_t oc_polarity;
151 timer_ocn_polarity_t ocn_polarity;
152 type_func_t oc_fast_en;
153 timer_oc_idle_t oc_idle;
154 timer_ocn_idle_t ocn_idle;
155 } timer_oc_init_t;
156
160 typedef enum {
161 TIMER_STATE_RESET = 0x00U,
162 TIMER_STATE_READY = 0x01U,
163 TIMER_STATE_BUSY = 0x02U,
164 TIMER_STATE_TIMEREOUT = 0x03U,
165 TIMER_STATE_ERROR = 0x04U,
166 } timer_state_t;
167
171 typedef enum {
172 TIMER_ACTIVE_CHANNEL_1 = 0x01U,
173 TIMER_ACTIVE_CHANNEL_2 = 0x02U,
174 TIMER_ACTIVE_CHANNEL_3 = 0x04U,
175 TIMER_ACTIVE_CHANNEL_4 = 0x08U,
176 TIMER_ACTIVE_CHANNEL_CLEARED = 0x00U,
177 } timer_active_channel_t;
178
182 typedef struct timer_handle_s {
183 TIMER_TypeDef *perh;
184 timer_base_init_t init;
185 timer_active_channel_t ch;
186 lock_state_t lock;
187 timer_state_t state;
189 #ifdef ALD_DMA
190 dma_handle_t hdma1;
191 dma_handle_t hdma2;
192 #endif
193
194 void (*period_elapse_cbk)(struct timer_handle_s *arg);
195 void (*delay_elapse_cbk)(struct timer_handle_s *arg);
196 void (*capture_cbk)(struct timer_handle_s *arg);
197 void (*pwm_pulse_finish_cbk)(struct timer_handle_s *arg);
198 void (*trigger_cbk)(struct timer_handle_s *arg);
199 void (*break_cbk)(struct timer_handle_s *arg);
200 void (*com_cbk)(struct timer_handle_s *arg);
201 void (*error_cbk)(struct timer_handle_s *arg);
202 } timer_handle_t;
203
204
208 typedef enum {
209 TIMER_ENC_MODE_TI1 = 1U,
210 TIMER_ENC_MODE_TI2 = 2U,
211 TIMER_ENC_MODE_TI12 = 3U,
212 } timer_encoder_mode_t;
213
217 typedef enum {
218 TIMER_IC_POLARITY_RISE = 0U,
219 TIMER_IC_POLARITY_FALL = 1U,
220 } timer_ic_polarity_t;
221
225 typedef enum {
226 TIMER_IC_SEL_DIRECT = 1U,
227 TIMER_IC_SEL_INDIRECT = 2U,
228 TIMER_IC_SEL_TRC = 3U,
229 } timer_ic_select_t;
230
234 typedef enum {
235 TIMER_IC_PSC_DIV1 = 0U,
236 TIMER_IC_PSC_DIV2 = 1U,
237 TIMER_IC_PSC_DIV4 = 2U,
238 TIMER_IC_PSC_DIV8 = 3U,
239 } timer_ic_prescaler_t;
240
244 typedef struct {
245 timer_encoder_mode_t mode;
246 timer_ic_polarity_t ic1_polarity;
247 timer_ic_select_t ic1_sel;
248 timer_ic_prescaler_t ic1_psc;
249 uint32_t ic1_filter;
250 timer_ic_polarity_t ic2_polarity;
251 timer_ic_select_t ic2_sel;
252 timer_ic_prescaler_t ic2_psc;
253 uint32_t ic2_filter;
254 } timer_encoder_init_t;
255
259 typedef struct {
260 timer_ic_polarity_t polarity;
261 timer_ic_select_t sel;
262 timer_ic_prescaler_t psc;
263 uint32_t filter;
264 } timer_ic_init_t;
265
269 typedef struct {
270 timer_oc_mode_t mode;
271 uint16_t pulse;
272 timer_oc_polarity_t oc_polarity;
273 timer_ocn_polarity_t ocn_polarity;
274 timer_oc_idle_t oc_idle;
275 timer_ocn_idle_t ocn_idle;
276 timer_ic_polarity_t polarity;
277 timer_ic_select_t sel;
278 uint32_t filter;
279 } timer_one_pulse_init_t;
280
283 typedef enum {
284 TIMER_INPUT_NONE = 0U,
285 TIMER_INPUT_ETR = 1U,
286 } timer_clear_input_source_t;
287
290 typedef enum {
291 TIMER_POLARITY_NO_INV = 0U,
292 TIMER_POLARITY_INV = 1U,
293 } timer_clear_input_polarity_t;
294
297 typedef enum {
298 TIMER_ETR_PSC_DIV1 = 0U,
299 TIMER_ETR_PSC_DIV2 = 1U,
300 TIMER_ETR_PSC_DIV4 = 2U,
301 TIMER_ETR_PSC_DIV8 = 3U,
302 } timer_etr_psc_t;
303
306 typedef enum {
307 TIMER_CHNREF_CLR_CMP_IN = 0U,
308 TIMER_CHNREF_CLR_ETF = 1U,
309 }timer_chnref_clr_sel_t;
312 typedef struct {
313 type_func_t state;
314 timer_clear_input_source_t source;
315 timer_clear_input_polarity_t polarity;
316 timer_etr_psc_t psc;
317 timer_chnref_clr_sel_t clrsel;
318 uint32_t filter;
319 } timer_clear_input_config_t;
320
323 typedef enum {
324 TIMER_SRC_ETRMODE2 = 0U,
325 TIMER_SRC_INTER = 1U,
326 TIMER_SRC_ITR0 = 2U,
327 TIMER_SRC_ITR1 = 3U,
328 TIMER_SRC_ITR2 = 4U,
329 TIMER_SRC_ITR3 = 5U,
330 TIMER_SRC_TI1ED = 6U,
331 TIMER_SRC_TI1 = 7U,
332 TIMER_SRC_TI2 = 8U,
333 TIMER_SRC_ETRMODE1 = 9U,
334 } timer_clock_source_t;
335
338 typedef enum {
339 TIMER_CLK_POLARITY_INV = 1U,
340 TIMER_CLK_POLARITY_NO_INV = 0U,
341 TIMER_CLK_POLARITY_RISE = 0U,
342 TIMER_CLK_POLARITY_FALL = 1U,
343 TIMER_CLK_POLARITY_BOTH = 3U,
344 } timer_clock_polarity_t;
345
349 typedef struct {
350 timer_clock_source_t source;
351 timer_clock_polarity_t polarity;
352 timer_etr_psc_t psc;
353 uint32_t filter;
354 } timer_clock_config_t;
355
359 typedef enum {
360 TIMER_MODE_DISABLE = 0U,
361 TIMER_MODE_ENC1 = 1U,
362 TIMER_MODE_ENC2 = 2U,
363 TIMER_MODE_ENC3 = 3U,
364 TIMER_MODE_RESET = 4U,
365 TIMER_MODE_GATED = 5U,
366 TIMER_MODE_TRIG = 6U,
367 TIMER_MODE_EXTERNAL1 = 7U,
368 } timer_slave_mode_t;
369
373 typedef enum {
374 TIMER_TS_ITR0 = 0U,
375 TIMER_TS_ITR1 = 1U,
376 TIMER_TS_ITR2 = 2U,
377 TIMER_TS_ITR3 = 3U,
378 TIMER_TS_TI1F_ED = 4U,
379 TIMER_TS_TI1FP1 = 5U,
380 TIMER_TS_TI2FP2 = 6U,
381 TIMER_TS_ETRF = 7U,
382 } timer_ts_t;
383
387 typedef struct {
388 timer_slave_mode_t mode;
389 timer_ts_t input;
390 timer_clock_polarity_t polarity;
391 timer_etr_psc_t psc;
392 uint32_t filter;
393 } timer_slave_config_t;
394
398 typedef struct {
399 timer_ic_polarity_t polarity;
400 timer_ic_prescaler_t psc;
401 uint32_t filter;
402 uint32_t delay;
403 } timer_hall_sensor_init_t;
404
408 typedef enum {
409 TIMER_LOCK_LEVEL_OFF = 0U,
410 TIMER_LOCK_LEVEL_1 = 1U,
411 TIMER_LOCK_LEVEL_2 = 2U,
412 TIMER_LOCK_LEVEL_3 = 3U,
413 } timer_lock_level_t;
414
418 typedef enum {
419 TIMER_BREAK_POLARITY_LOW = 0U,
420 TIMER_BREAK_POLARITY_HIGH = 1U,
421 } timer_break_polarity_t;
422
426 typedef struct {
427 type_func_t off_run;
428 type_func_t off_idle;
429 timer_lock_level_t lock_level;
430 uint32_t dead_time;
431 type_func_t break_state;
432 timer_break_polarity_t polarity;
433 type_func_t auto_out;
434 } timer_break_dead_time_t;
435
439 typedef struct {
440 type_func_t en;
441 type_func_t n_en;
442 timer_oc_mode_t mode;
443 } timer_channel_config_t;
444
448 typedef struct {
449 timer_channel_config_t ch[3];
450 } timer_com_channel_config_t;
451
455 typedef enum {
456 TIMER_TRGO_RESET = 0U,
457 TIMER_TRGO_ENABLE = 1U,
458 TIMER_TRGO_UPDATE = 2U,
459 TIMER_TRGO_OC1 = 3U,
460 TIMER_TRGO_OC1REF = 4U,
461 TIMER_TRGO_OC2REF = 5U,
462 TIMER_TRGO_OC3REF = 6U,
463 TIMER_TRGO_OC4REF = 7U,
464 } timer_master_mode_sel_t;
465
469 typedef struct {
470 timer_master_mode_sel_t sel;
471 type_func_t master_en;
472 } timer_master_config_t;
473
477 typedef enum {
478 TIMER_SRC_UPDATE = (1U << 0),
479 TIMER_SRC_CC1 = (1U << 1),
480 TIMER_SRC_CC2 = (1U << 2),
481 TIMER_SRC_CC3 = (1U << 3),
482 TIMER_SRC_CC4 = (1U << 4),
483 TIMER_SRC_COM = (1U << 5),
484 TIMER_SRC_TRIG = (1U << 6),
485 TIMER_SRC_BREAK = (1U << 7),
486 } timer_event_source_t;
487
491 typedef enum {
492 TIMER_IT_UPDATE = (1U << 0),
493 TIMER_IT_CC1 = (1U << 1),
494 TIMER_IT_CC2 = (1U << 2),
495 TIMER_IT_CC3 = (1U << 3),
496 TIMER_IT_CC4 = (1U << 4),
497 TIMER_IT_COM = (1U << 5),
498 TIMER_IT_TRIGGER = (1U << 6),
499 TIMER_IT_BREAK = (1U << 7),
500 } timer_it_t;
501
505 typedef enum {
506 TIMER_DMA_UPDATE = (1U << 0),
507 TIMER_DMA_CC1 = (1U << 1),
508 TIMER_DMA_CC2 = (1U << 2),
509 TIMER_DMA_CC3 = (1U << 3),
510 TIMER_DMA_CC4 = (1U << 4),
511 TIMER_DMA_COM = (1U << 5),
512 TIMER_DMA_TRIGGER = (1U << 6),
513 } timer_dma_req_t;
514
518 typedef enum {
519 TIMER_FLAG_UPDATE = (1U << 0),
520 TIMER_FLAG_CC1 = (1U << 1),
521 TIMER_FLAG_CC2 = (1U << 2),
522 TIMER_FLAG_CC3 = (1U << 3),
523 TIMER_FLAG_CC4 = (1U << 4),
524 TIMER_FLAG_COM = (1U << 5),
525 TIMER_FLAG_TRIGGER = (1U << 6),
526 TIMER_FLAG_BREAK = (1U << 7),
527 TIMER_FLAG_CC1OF = (1U << 9),
528 TIMER_FLAG_CC2OF = (1U << 10),
529 TIMER_FLAG_CC3OF = (1U << 11),
530 TIMER_FLAG_CC4OF = (1U << 12),
531 } timer_flag_t;
539 #define CCER_CCxE_MASK ((1U << 0) | (1U << 4) | (1U << 8) | (1U << 12))
540 #define CCER_CCxNE_MASK ((1U << 2) | (1U << 6) | (1U << 10))
541
545 #define TIMER_RESET_HANDLE_STATE(hperh) ((hperh)->state = TIMER_STATE_RESET)
546
550 #define TIMER_ENABLE(hperh) (SET_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK))
551
555 #define TIMER_MOE_ENABLE(hperh) (SET_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK))
556
560 #define TIMER_DISABLE(hperh) \
561 do { \
562 if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \
563 && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \
564 CLEAR_BIT((hperh)->perh->CON1, TIMER_CON1_CNTEN_MSK); \
565 } while (0)
566
572 #define TIMER_MOE_DISABLE(hperh) \
573 do { \
574 if ((((hperh)->perh->CCEP & CCER_CCxE_MASK) == 0) \
575 && (((hperh)->perh->CCEP & CCER_CCxNE_MASK) == 0)) \
576 CLEAR_BIT((hperh)->perh->BDCFG, TIMER_BDCFG_GOEN_MSK); \
577 } while (0)
578
583 #define TIMER_SET_AUTORELOAD(handle, AUTORELOAD) \
584 do { \
585 (handle)->perh->AR = (AUTORELOAD); \
586 (handle)->init.period = (AUTORELOAD); \
587 } while (0)
588
592 #define TIMER_GET_AUTORELOAD(handle) ((handle)->perh->AR)
593
597 #define TIMER_GET_CNT(handle) ((handle)->perh->COUNT)
598
602 #define TIMER_GET_DIR(handle) (READ_BITS((handle)->perh->CON1, TIMER_CON1_DIRSEL_MSK, TIMER_CON1_DIRSEL_POS))
603
607 #define TIMER_CCx_DMA_REQ_CCx(handle) (CLEAR_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK))
608
612 #define TIMER_CCx_DMA_REQ_UPDATE(handle) (SET_BIT((handle)->perh->CON2, TIMER_CON2_CCDMASEL_MSK))
613
623 #define TIMER_CCx_ENABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \
624 (SET_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4POL_MSK)) : (WRITE_REG(((handle)->perh->CCEP), (((handle)->perh->CCEP) | (1 << ((ch) << 2))))))
625
635 #define TIMER_CCx_DISABLE(handle, ch) (((ch) == TIMER_CHANNEL_4) ? \
636 (CLEAR_BIT((handle)->perh->CCEP, TIMER_CCEP_CC4EN_MSK)) : ((handle)->perh->CCEP &= ~(1 << ((ch) << 2))))
637
646 #define TIMER_CCxN_ENABLE(handle, ch) ((handle)->perh->CCEP |= (1 << (((ch) << 2) + 2)))
647
656 #define TIMER_CCxN_DISABLE(handle, ch) ((handle)->perh->CCEP &= ~(1 << (((ch) << 2) + 2)))
657
665 #if defined(ES32F36xx)
666 #define IS_TIMER_INSTANCE(x) (((x) == AD16C4T0) || \
667 ((x) == AD16C4T1) || \
668 ((x) == GP32C4T0) || \
669 ((x) == GP32C4T1) || \
670 ((x) == BS16T0) || \
671 ((x) == BS16T1) || \
672 ((x) == GP16C4T0) || \
673 ((x) == GP16C4T1))
674 #define IS_ADTIMER_INSTANCE(x) (((x) == AD16C4T0) || \
675 ((x) == AD16C4T1))
676 #define IS_TIMER_XOR_INSTANCE(x) (((x) == AD16C4T0) || \
677 ((x) == AD16C4T1) || \
678 ((x) == GP16C4T1) || \
679 ((x) == GP16C4T0) || \
680 ((x) == GP32C4T0) || \
681 ((x) == GP32C4T1))
682 #define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == AD16C4T0) || \
683 ((x) == AD16C4T1) || \
684 ((x) == GP16C4T1) || \
685 ((x) == GP16C4T0) || \
686 ((x) == GP32C4T0) || \
687 ((x) == GP32C4T1))
688 #define IS_TIMER_CC2_INSTANCE(x) (((x) == AD16C4T0) || \
689 ((x) == AD16C4T1) || \
690 ((x) == GP16C4T0) || \
691 ((x) == GP16C4T1) || \
692 ((x) == GP32C4T0) || \
693 ((x) == GP32C4T1))
694 #define IS_TIMER_CC4_INSTANCE(x) (((x) == AD16C4T0) || \
695 ((x) == AD16C4T1) || \
696 ((x) == GP16C4T0) || \
697 ((x) == GP16C4T1) || \
698 ((x) == GP32C4T0) || \
699 ((x) == GP32C4T1))
700 #define IS_TIMER_BREAK_INSTANCE(x) (((x) == AD16C4T0) || \
701 ((x) == AD16C4T1))
702 #define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == AD16C4T0) && \
703 (((y) == TIMER_CHANNEL_1) || \
704 ((y) == TIMER_CHANNEL_2))) || \
705 (((x) == GP32C4T0) && \
706 (((y) == TIMER_CHANNEL_1) || \
707 ((y) == TIMER_CHANNEL_2))) || \
708 (((x) == GP32C4T1) && \
709 (((y) == TIMER_CHANNEL_1) || \
710 ((y) == TIMER_CHANNEL_2))) || \
711 (((x) == GP16C4T0) && \
712 (((y) == TIMER_CHANNEL_1) || \
713 ((y) == TIMER_CHANNEL_2))) || \
714 (((x) == AD16C4T1) && \
715 (((y) == TIMER_CHANNEL_1) || \
716 ((y) == TIMER_CHANNEL_2))) || \
717 (((x) == GP16C4T1) && \
718 (((y) == TIMER_CHANNEL_1) || \
719 ((y) == TIMER_CHANNEL_2))))
720 #define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == AD16C4T0) && \
721 (((y) == TIMER_CHANNEL_1) || \
722 ((y) == TIMER_CHANNEL_2) || \
723 ((y) == TIMER_CHANNEL_3) || \
724 ((y) == TIMER_CHANNEL_4))) || \
725 (((x) == AD16C4T1) && \
726 (((y) == TIMER_CHANNEL_1) || \
727 ((y) == TIMER_CHANNEL_2) || \
728 ((y) == TIMER_CHANNEL_3) || \
729 ((y) == TIMER_CHANNEL_4))) || \
730 (((x) == GP32C4T0) && \
731 (((y) == TIMER_CHANNEL_1) || \
732 ((y) == TIMER_CHANNEL_2) || \
733 ((y) == TIMER_CHANNEL_3) || \
734 ((y) == TIMER_CHANNEL_4))) || \
735 (((x) == GP32C4T1) && \
736 (((y) == TIMER_CHANNEL_1) || \
737 ((y) == TIMER_CHANNEL_2) || \
738 ((y) == TIMER_CHANNEL_3) || \
739 ((y) == TIMER_CHANNEL_4))) || \
740 (((x) == GP16C4T0) && \
741 (((y) == TIMER_CHANNEL_1) || \
742 ((y) == TIMER_CHANNEL_2) || \
743 ((y) == TIMER_CHANNEL_3) || \
744 ((y) == TIMER_CHANNEL_4))) || \
745 (((x) == GP16C4T1) && \
746 (((y) == TIMER_CHANNEL_1) || \
747 ((y) == TIMER_CHANNEL_2) || \
748 ((y) == TIMER_CHANNEL_3) || \
749 ((y) == TIMER_CHANNEL_4))))
750 #define IS_TIMER_CCXN_INSTANCE(x, y) ((((x) == AD16C4T0) || \
751 ((x) == AD16C4T1)) && \
752 (((y) == TIMER_CHANNEL_1) || \
753 ((y) == TIMER_CHANNEL_2) || \
754 ((y) == TIMER_CHANNEL_3) || \
755 ((y) == TIMER_CHANNEL_4)))
756 #define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == AD16C4T0) || \
757 ((x) == AD16C4T1))
758 #define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x)
759
760 #endif
761
762 #if defined(ES32F39xx) || defined(ES32F336x)
763 #define IS_TIMER_INSTANCE(x) (((x) == GP16C4T0) || \
764 ((x) == GP16C4T1) || \
765 ((x) == GP32C4T0) || \
766 ((x) == GP32C4T1) || \
767 ((x) == BS16T0) || \
768 ((x) == BS16T1) || \
769 ((x) == GP16C4T2) || \
770 ((x) == GP16C4T3))
771 #define IS_TIMER_XOR_INSTANCE(x) (((x) == GP16C4T0) || \
772 ((x) == GP16C4T1) || \
773 ((x) == GP16C4T2) || \
774 ((x) == GP16C4T3) || \
775 ((x) == GP32C4T0) || \
776 ((x) == GP32C4T1))
777 #define IS_TIMER_COM_EVENT_INSTANCE(x) (((x) == GP16C4T0) || \
778 ((x) == GP32C4T0) || \
779 ((x) == GP16C4T1) || \
780 ((x) == GP16C4T2) || \
781 ((x) == GP16C4T3) || \
782 ((x) == GP32C4T1))
783 #define IS_TIMER_CC2_INSTANCE(x) (((x) == GP16C4T0) || \
784 ((x) == GP32C4T0) || \
785 ((x) == GP32C4T1) || \
786 ((x) == GP16C4T2) || \
787 ((x) == GP16C4T2) || \
788 ((x) == GP16C4T3))
789 #define IS_TIMER_CC4_INSTANCE(x) (((x) == GP16C4T0) || \
790 ((x) == GP16C4T1) || \
791 ((x) == GP16C4T2) || \
792 ((x) == GP16C4T3) || \
793 ((x) == GP32C4T0) || \
794 ((x) == GP32C4T1))
795 #define IS_TIMER_PWM_INPUT_INSTANCE(x, y) ((((x) == GP16C4T0) && \
796 (((y) == TIMER_CHANNEL_1) || \
797 ((y) == TIMER_CHANNEL_2))) || \
798 (((x) == GP32C4T0) && \
799 (((y) == TIMER_CHANNEL_1) || \
800 ((y) == TIMER_CHANNEL_2))) || \
801 (((x) == GP32C4T1) && \
802 (((y) == TIMER_CHANNEL_1) || \
803 ((y) == TIMER_CHANNEL_2))) || \
804 (((x) == GP16C4T1) && \
805 (((y) == TIMER_CHANNEL_1) || \
806 ((y) == TIMER_CHANNEL_2))) || \
807 (((x) == GP16C4T3) && \
808 (((y) == TIMER_CHANNEL_1) || \
809 ((y) == TIMER_CHANNEL_2))) || \
810 (((x) == GP16C4T2) && \
811 (((y) == TIMER_CHANNEL_1) || \
812 ((y) == TIMER_CHANNEL_2))))
813 #define IS_TIMER_CCX_INSTANCE(x, y) ((((x) == GP16C4T0) && \
814 (((y) == TIMER_CHANNEL_1) || \
815 ((y) == TIMER_CHANNEL_2) || \
816 ((y) == TIMER_CHANNEL_3) || \
817 ((y) == TIMER_CHANNEL_4))) || \
818 (((x) == GP32C4T0) && \
819 (((y) == TIMER_CHANNEL_1) || \
820 ((y) == TIMER_CHANNEL_2))) || \
821 (((x) == GP32C4T1) && \
822 (((y) == TIMER_CHANNEL_1) || \
823 ((y) == TIMER_CHANNEL_2))) || \
824 (((x) == GP16C4T2) && \
825 (((y) == TIMER_CHANNEL_1) || \
826 ((y) == TIMER_CHANNEL_2) || \
827 ((y) == TIMER_CHANNEL_3) || \
828 ((y) == TIMER_CHANNEL_4))))
829
830 #define IS_TIMER_CCXN_INSTANCE(x, y) ((((x) == NULL) || \
831 ((x) == NULL)) && \
832 (((y) == TIMER_CHANNEL_1) || \
833 ((y) == TIMER_CHANNEL_2) || \
834 ((y) == TIMER_CHANNEL_3) || \
835 ((y) == TIMER_CHANNEL_4)))
836
837 #define IS_TIMER_REPETITION_COUNTER_INSTANCE(x) (((x) == NULL) || \
838 ((x) == NULL))
839
840 #define IS_TIMER_BREAK_INSTANCE(x) (((x) == NULL) || \
841 ((x) == NULL))
842
843 #define IS_TIMER_CLOCK_DIVISION_INSTANCE(x) IS_TIMER_CC2_INSTANCE(x)
844
845 #endif
846
847 #define IS_TIMER_COUNTER_MODE(x) (((x) == TIMER_CNT_MODE_UP) || \
848 ((x) == TIMER_CNT_MODE_DOWN) || \
849 ((x) == TIMER_CNT_MODE_CENTER1) || \
850 ((x) == TIMER_CNT_MODE_CENTER2) || \
851 ((x) == TIMER_CNT_MODE_CENTER3))
852 #define IS_TIMER_CLOCK_DIVISION(x) (((x) == TIMER_CLOCK_DIV1) || \
853 ((x) == TIMER_CLOCK_DIV2) || \
854 ((x) == TIMER_CLOCK_DIV4))
855 #define IS_TIMER_PWM_MODE(x) (((x) == TIMER_OC_MODE_PWM1) || \
856 ((x) == TIMER_OC_MODE_PWM2))
857 #define IS_TIMER_OC_MODE(x) (((x) == TIMER_OC_MODE_TIMERING) || \
858 ((x) == TIMER_OC_MODE_ACTIVE) || \
859 ((x) == TIMER_OC_MODE_INACTIVE) || \
860 ((x) == TIMER_OC_MODE_TOGGLE) || \
861 ((x) == TIMER_OC_MODE_FORCE_ACTIVE) || \
862 ((x) == TIMER_OC_MODE_FORCE_INACTIVE) || \
863 ((x) == TIMER_OC_MODE_PWM1) || \
864 ((x) == TIMER_OC_MODE_PWM2))
865 #define IS_TIMER_OC_POLARITY(x) (((x) == TIMER_OC_POLARITY_HIGH) || \
866 ((x) == TIMER_OC_POLARITY_LOW))
867 #define IS_TIMER_OCN_POLARITY(x) (((x) == TIMER_OCN_POLARITY_HIGH) || \
868 ((x) == TIMER_OCN_POLARITY_LOW))
869 #define IS_TIMER_OCIDLE_STATE(x) (((x) == TIMER_OC_IDLE_RESET) || \
870 ((x) == TIMER_OC_IDLE_SET))
871 #define IS_TIMER_OCNIDLE_STATE(x) (((x) == TIMER_OCN_IDLE_RESET) || \
872 ((x) == TIMER_OCN_IDLE_SET))
873 #define IS_TIMER_CHANNELS(x) (((x) == TIMER_CHANNEL_1) || \
874 ((x) == TIMER_CHANNEL_2) || \
875 ((x) == TIMER_CHANNEL_3) || \
876 ((x) == TIMER_CHANNEL_4) || \
877 ((x) == TIMER_CHANNEL_ALL))
878 #define IS_TIMER_OP_MODE(x) (((x) == TIMER_OP_MODE_REPEAT) || \
879 ((x) == TIMER_OP_MODE_SINGLE))
880 #define IS_TIMER_OP_OUTPUT_CH(x) (((x) == TIMER_OP_OUTPUT_CHANNEL_1) || \
881 ((x) == TIMER_OP_OUTPUT_CHANNEL_2))
882 #define IS_TIMER_ENCODER_MODE(x) (((x) == TIMER_ENC_MODE_TI1) || \
883 ((x) == TIMER_ENC_MODE_TI2) || \
884 ((x) == TIMER_ENC_MODE_TI12))
885 #define IS_TIMER_IC_POLARITY(x) (((x) == TIMER_IC_POLARITY_RISE) || \
886 ((x) == TIMER_IC_POLARITY_FALL))
887 #define IS_TIMER_IC_SELECT(x) (((x) == TIMER_IC_SEL_DIRECT) || \
888 ((x) == TIMER_IC_SEL_INDIRECT) || \
889 ((x) == TIMER_IC_SEL_TRC))
890 #define IS_TIMER_IC_PSC(x) (((x) == TIMER_IC_PSC_DIV1) || \
891 ((x) == TIMER_IC_PSC_DIV2) || \
892 ((x) == TIMER_IC_PSC_DIV4) || \
893 ((x) == TIMER_IC_PSC_DIV8))
894 #define IS_TIMER_IC_FILTER(x) ((x) <= 0xF)
895 #define IS_TIMER_DEAD_TIMERE(x) ((x) <= 0xFF)
896 #define IS_TIMER_CLEAR_INPUT_SOURCE(x) (((x) == TIMER_INPUT_NONE) || \
897 ((x) == TIMER_INPUT_ETR))
898 #define IS_TIMER_CLEAR_INPUT_POLARITY(x) (((x) == TIMER_POLARITY_NO_INV) || \
899 ((x) == TIMER_POLARITY_INV))
900 #define IS_TIMER_ETR_PSC(x) (((x) == TIMER_ETR_PSC_DIV1) || \
901 ((x) == TIMER_ETR_PSC_DIV2) || \
902 ((x) == TIMER_ETR_PSC_DIV4) || \
903 ((x) == TIMER_ETR_PSC_DIV8))
904 #define IS_TIMER_CHNREF_CLEAR(X) (((X) == TIMER_CHNREF_CLR_CMP_IN) || \
905 ((X) == TIMER_CHNREF_CLR_ETF))
906 #define IS_TIMER_CLOCK_SOURCE(x) (((x) == TIMER_SRC_ETRMODE2) || \
907 ((x) == TIMER_SRC_INTER) || \
908 ((x) == TIMER_SRC_ITR0) || \
909 ((x) == TIMER_SRC_ITR1) || \
910 ((x) == TIMER_SRC_ITR2) || \
911 ((x) == TIMER_SRC_ITR3) || \
912 ((x) == TIMER_SRC_TI1ED) || \
913 ((x) == TIMER_SRC_TI1) || \
914 ((x) == TIMER_SRC_TI2) || \
915 ((x) == TIMER_SRC_ETRMODE1))
916 #define IS_TIMER_CLOCK_POLARITY(x) (((x) == TIMER_CLK_POLARITY_INV) || \
917 ((x) == TIMER_CLK_POLARITY_NO_INV) || \
918 ((x) == TIMER_CLK_POLARITY_RISE) || \
919 ((x) == TIMER_CLK_POLARITY_FALL) || \
920 ((x) == TIMER_CLK_POLARITY_BOTH))
921 #define IS_TIMER_SLAVE_MODE(x) (((x) == TIMER_MODE_DISABLE) || \
922 ((x) == TIMER_MODE_ENC1) || \
923 ((x) == TIMER_MODE_ENC2) || \
924 ((x) == TIMER_MODE_ENC3) || \
925 ((x) == TIMER_MODE_RESET) || \
926 ((x) == TIMER_MODE_GATED) || \
927 ((x) == TIMER_MODE_TRIG) || \
928 ((x) == TIMER_MODE_EXTERNAL1))
929 #define IS_TIMER_EVENT_SOURCE(x) (((x) == TIMER_SRC_UPDATE) || \
930 ((x) == TIMER_SRC_CC1) || \
931 ((x) == TIMER_SRC_CC2) || \
932 ((x) == TIMER_SRC_CC3) || \
933 ((x) == TIMER_SRC_CC4) || \
934 ((x) == TIMER_SRC_COM) || \
935 ((x) == TIMER_SRC_TRIG) || \
936 ((x) == TIMER_SRC_BREAK))
937 #define IS_TIMER_TS(x) (((x) == TIMER_TS_ITR0) || \
938 ((x) == TIMER_TS_ITR1) || \
939 ((x) == TIMER_TS_ITR2) || \
940 ((x) == TIMER_TS_ITR3) || \
941 ((x) == TIMER_TS_TI1F_ED) || \
942 ((x) == TIMER_TS_TI1FP1) || \
943 ((x) == TIMER_TS_TI2FP2) || \
944 ((x) == TIMER_TS_ETRF))
945 #define IS_TIMER_CLOCK_LEVEL(x) (((x) == TIMER_LOCK_LEVEL_OFF) || \
946 ((x) == TIMER_LOCK_LEVEL_1) || \
947 ((x) == TIMER_LOCK_LEVEL_2) || \
948 ((x) == TIMER_LOCK_LEVEL_3))
949 #define IS_TIMER_BREAK_POLARITY(x) (((x) == TIMER_BREAK_POLARITY_LOW) || \
950 ((x) == TIMER_BREAK_POLARITY_HIGH))
951 #define IS_TIMER_MASTER_MODE_SEL(x) (((x) == TIMER_TRGO_RESET) || \
952 ((x) == TIMER_TRGO_ENABLE) || \
953 ((x) == TIMER_TRGO_UPDATE) || \
954 ((x) == TIMER_TRGO_OC1) || \
955 ((x) == TIMER_TRGO_OC1REF) || \
956 ((x) == TIMER_TRGO_OC2REF) || \
957 ((x) == TIMER_TRGO_OC3REF) || \
958 ((x) == TIMER_TRGO_OC4REF))
959 #define IS_TIMER_IT(x) (((x) == TIMER_IT_UPDATE) || \
960 ((x) == TIMER_IT_CC1) || \
961 ((x) == TIMER_IT_CC2) || \
962 ((x) == TIMER_IT_CC3) || \
963 ((x) == TIMER_IT_CC4) || \
964 ((x) == TIMER_IT_COM) || \
965 ((x) == TIMER_IT_TRIGGER) || \
966 ((x) == TIMER_IT_BREAK))
967 #define IS_TIMER_DMA_REQ(x) (((x) == TIMER_DMA_UPDATE) || \
968 ((x) == TIMER_DMA_CC1) || \
969 ((x) == TIMER_DMA_CC2) || \
970 ((x) == TIMER_DMA_CC3) || \
971 ((x) == TIMER_DMA_CC4) || \
972 ((x) == TIMER_DMA_COM) || \
973 ((x) == TIMER_DMA_TRIGGER))
974 #define IS_TIMER_FLAG(x) (((x) == TIMER_FLAG_UPDATE) || \
975 ((x) == TIMER_FLAG_CC1) || \
976 ((x) == TIMER_FLAG_CC2) || \
977 ((x) == TIMER_FLAG_CC3) || \
978 ((x) == TIMER_FLAG_CC4) || \
979 ((x) == TIMER_FLAG_COM) || \
980 ((x) == TIMER_FLAG_TRIGGER) || \
981 ((x) == TIMER_FLAG_BREAK) || \
982 ((x) == TIMER_FLAG_CC1OF) || \
983 ((x) == TIMER_FLAG_CC2OF) || \
984 ((x) == TIMER_FLAG_CC3OF) || \
985 ((x) == TIMER_FLAG_CC4OF))
986
996 /* Time Base functions */
997 ald_status_t ald_timer_base_init(timer_handle_t *hperh);
998 void ald_timer_base_reset(timer_handle_t *hperh);
999 void ald_timer_base_start(timer_handle_t *hperh);
1000 void ald_timer_base_stop(timer_handle_t *hperh);
1001 void ald_timer_base_start_by_it(timer_handle_t *hperh);
1002 void ald_timer_base_stop_by_it(timer_handle_t *hperh);
1003 #ifdef ALD_DMA
1004 ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh,
1005 uint16_t *buf, uint32_t len, uint8_t dma_ch);
1006 void ald_timer_base_stop_by_dma(timer_handle_t *hperh);
1007 #endif
1008
1015 /* Timer Output Compare functions */
1016 ald_status_t ald_timer_oc_init(timer_handle_t *hperh);
1017 void ald_timer_oc_start(timer_handle_t *hperh, timer_channel_t ch);
1018 void ald_timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch);
1019 void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch);
1020 void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch);
1021 #ifdef ALD_DMA
1022 ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch,
1023 uint16_t *buf, uint32_t len, uint8_t dma_ch);
1024 void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch);
1025 #endif
1026
1033 /* Timer PWM functions */
1034 ald_status_t ald_timer_pwm_init(timer_handle_t *hperh);
1035 void ald_timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch);
1036 void ald_timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch);
1037 void ald_timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch);
1038 void ald_timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch);
1039 void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq);
1040 void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty);
1041 void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch);
1042 #ifdef ALD_DMA
1043 ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch,
1044 uint16_t *buf, uint32_t len, uint8_t dma_ch);
1045 void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch);
1046 #endif
1047
1054 /* Timer Input Capture functions */
1055 ald_status_t ald_timer_ic_init(timer_handle_t *hperh);
1056 void ald_timer_ic_start(timer_handle_t *hperh, timer_channel_t ch);
1057 void ald_timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch);
1058 void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch);
1059 void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch);
1060 #ifdef ALD_DMA
1061 ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch,
1062 uint16_t *buf, uint32_t len, uint8_t dma_ch);
1063 void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch);
1064 #endif
1065
1072 /* Timer One Pulse functions */
1073 ald_status_t ald_timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode);
1074 void ald_timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch);
1075 void ald_timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch);
1076 void ald_timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch);
1077 void ald_timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch);
1085 /* Timer encoder functions */
1086 ald_status_t ald_timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config);
1087 void ald_timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch);
1088 void ald_timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch);
1089 void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch);
1090 void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch);
1091 #ifdef ALD_DMA
1092 ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch,
1093 uint16_t *buf1, uint16_t *buf2, uint32_t len,
1094 uint8_t dma_ch1, uint8_t dma_ch2);
1095 void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch);
1096 #endif
1097
1104 /* Timer hall sensor functions */
1105 ald_status_t ald_timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config);
1106 void ald_timer_hall_sensor_start(timer_handle_t *hperh);
1107 void ald_timer_hall_sensor_stop(timer_handle_t *hperh);
1108 void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh);
1109 void ald_timer_hall_sensor_stop_by_it(timer_handle_t *hperh);
1110 #ifdef ALD_DMA
1111 ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh,
1112 uint16_t *buf, uint32_t len, uint8_t dma_ch);
1113 void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh);
1114 #endif
1115
1122 /* Timer complementary output compare functions */
1123 void ald_timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch);
1124 void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch);
1125 void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch);
1126 void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch);
1127 #ifdef ALD_DMA
1128 ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh,
1129 timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch);
1130 void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch);
1131 #endif
1132
1139 /* Timer complementary PWM functions */
1140 void ald_timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch);
1141 void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch);
1142 void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch);
1143 void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch);
1144 #ifdef ALD_DMA
1145 ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh,
1146 timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch);
1147 void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch);
1148 #endif
1149
1156 /* Timer complementary one pulse functions */
1157 void ald_timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch);
1158 void ald_timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch);
1159 void ald_timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch);
1160 void ald_timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch);
1168 /* Control functions */
1169 ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t* config, timer_channel_t ch);
1170 ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t* config, timer_channel_t ch);
1171 ald_status_t ald_timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config,
1172 timer_channel_t ch_out, timer_channel_t ch_in);
1173 ald_status_t ald_timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch);
1174 ald_status_t ald_timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config);
1175 ald_status_t ald_timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select);
1176 ald_status_t ald_timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config);
1177 ald_status_t ald_timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config);
1178 ald_status_t ald_timer_generate_event(timer_handle_t *hperh, timer_event_source_t event);
1179 uint32_t ald_timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch);
1180 void ald_timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch);
1181 void ald_timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config);
1182 void ald_timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi);
1183 void ald_timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi);
1184 void ald_timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config);
1185 void ald_timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config);
1186 void ald_timer_irq_handler(timer_handle_t *hperh);
1187 void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state);
1188 void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state);
1189 it_status_t ald_timer_get_it_status(timer_handle_t *hperh, timer_it_t it);
1190 flag_status_t ald_timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag);
1191 void ald_timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag);
1199 /* State functions */
1200 timer_state_t ald_timer_get_state(timer_handle_t *hperh);
1215 #ifdef __cplusplus
1216 }
1217 #endif
1218
1219 #endif /* __ALD_TIMER_H__ */
timer_clock_config_t::source
timer_clock_source_t source
Definition: ald_timer.h:350
TIMER_OC_MODE_PWM2
Definition: ald_timer.h:71
ald_timer_com_event_config
void ald_timer_com_event_config(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi)
Configure the TIMER commutation event sequence.
Definition: ald_timer.c:2834
TIMER_IT_CC1
Definition: ald_timer.h:493
timer_ic_prescaler_t
timer_ic_prescaler_t
TIMER input capture prescaler.
Definition: ald_timer.h:234
timer_handle_s::capture_cbk
void(* capture_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:196
ald_timer_base_start_by_it
void ald_timer_base_start_by_it(timer_handle_t *hperh)
Starts the TIMER Base generation in interrupt mode.
Definition: ald_timer.c:170
timer_one_pulse_init_t::oc_polarity
timer_oc_polarity_t oc_polarity
Definition: ald_timer.h:272
TIMER_CNT_MODE_CENTER2
Definition: ald_timer.h:47
timer_break_dead_time_t::off_run
type_func_t off_run
Definition: ald_timer.h:427
timer_oc_init_t::oc_idle
timer_oc_idle_t oc_idle
Definition: ald_timer.h:153
timer_ts_t
timer_ts_t
TIMER ts definition.
Definition: ald_timer.h:373
TIMER_SRC_UPDATE
Definition: ald_timer.h:478
TIMER_TRGO_OC4REF
Definition: ald_timer.h:463
TIMER_TRGO_OC2REF
Definition: ald_timer.h:461
TIMER_CNT_MODE_CENTER3
Definition: ald_timer.h:48
ald_timer_slave_config_sync
ald_status_t ald_timer_slave_config_sync(timer_handle_t *hperh, timer_slave_config_t *config)
Configures the TIMER in Slave mode.
Definition: ald_timer.c:2621
ald_timer_set_output_mode
void ald_timer_set_output_mode(timer_handle_t *hperh, timer_oc_mode_t mode, timer_channel_t ch)
Sets TIMER output mode.
Definition: ald_timer.c:2745
TIMER_CLK_POLARITY_INV
Definition: ald_timer.h:339
ald_timer_hall_sensor_stop_by_dma
void ald_timer_hall_sensor_stop_by_dma(timer_handle_t *hperh)
Stops the TIMER hall sensor interface in DMA mode.
Definition: ald_timer.c:1759
timer_ic_init_t::psc
timer_ic_prescaler_t psc
Definition: ald_timer.h:262
TIMER_ACTIVE_CHANNEL_3
Definition: ald_timer.h:174
ald_timer_pwmn_start
void ald_timer_pwmn_start(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER PWM signal generation on the complementary output.
Definition: ald_timer.c:2073
TIMER_OCN_IDLE_SET
Definition: ald_timer.h:103
ald_timer_one_pulse_n_start_by_it
void ald_timer_one_pulse_n_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER one pulse signal generation on the complementary output. in interrupt mode...
Definition: ald_timer.c:2222
dma_handle_t
DMA handle structure definition.
Definition: ald_dma.h:297
timer_handle_s::trigger_cbk
void(* trigger_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:198
timer_base_init_t::re_cnt
uint32_t re_cnt
Definition: ald_timer.h:141
TIMER_IC_SEL_DIRECT
Definition: ald_timer.h:226
TIMER_FLAG_CC1OF
Definition: ald_timer.h:527
timer_handle_s::hdma2
dma_handle_t hdma2
Definition: ald_timer.h:191
TIMER_CHANNEL_3
Definition: ald_timer.h:112
timer_break_polarity_t
timer_break_polarity_t
TIMER break polarity.
Definition: ald_timer.h:418
ald_timer_base_start_by_dma
ald_status_t ald_timer_base_start_by_dma(timer_handle_t *hperh, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER Base generation in DMA mode.
Definition: ald_timer.c:204
ald_timer_ic_stop_by_it
void ald_timer_ic_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Input Capture measurement in interrupt mode.
Definition: ald_timer.c:934
TIMER_IT_CC4
Definition: ald_timer.h:496
ald_timer_one_pulse_n_start
void ald_timer_one_pulse_n_start(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER one pulse signal generation on the complementary output.
Definition: ald_timer.c:2193
TIMER_ACTIVE_CHANNEL_2
Definition: ald_timer.h:173
timer_master_config_t::sel
timer_master_mode_sel_t sel
Definition: ald_timer.h:470
timer_slave_mode_t
timer_slave_mode_t
TIMER slave mode.
Definition: ald_timer.h:359
TIMER_STATE_RESET
Definition: ald_timer.h:161
timer_base_init_t::clk_div
timer_clock_division_t clk_div
Definition: ald_timer.h:140
ald_timer_pwm_set_input
void ald_timer_pwm_set_input(timer_handle_t *hperh, timer_channel_t ch)
Set capture the PWM.
Definition: ald_timer.c:776
timer_cnt_mode_t
timer_cnt_mode_t
TIMER counter mode.
Definition: ald_timer.h:43
timer_handle_s::break_cbk
void(* break_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:199
timer_clock_polarity_t
timer_clock_polarity_t
TIMER clock polarity.
Definition: ald_timer.h:338
TIMER_CHNREF_CLR_ETF
Definition: ald_timer.h:308
type_func_t
type_func_t
Definition: type.h:47
timer_ic_init_t::polarity
timer_ic_polarity_t polarity
Definition: ald_timer.h:260
TIMER_STATE_READY
Definition: ald_timer.h:162
TIMER_SRC_CC4
Definition: ald_timer.h:482
TIMER_CLK_POLARITY_FALL
Definition: ald_timer.h:342
timer_encoder_init_t::ic1_polarity
timer_ic_polarity_t ic1_polarity
Definition: ald_timer.h:246
ald_timer_config_clock_source
ald_status_t ald_timer_config_clock_source(timer_handle_t *hperh, timer_clock_config_t *config)
Configures the clock source to be used.
Definition: ald_timer.c:2518
TIMER_DMA_TRIGGER
Definition: ald_timer.h:512
TIMER_TS_TI1FP1
Definition: ald_timer.h:379
TIMER_SRC_ITR1
Definition: ald_timer.h:327
TIMER_OC_MODE_ACTIVE
Definition: ald_timer.h:65
ald_timer_get_state
timer_state_t ald_timer_get_state(timer_handle_t *hperh)
Return the TIMER Base state.
Definition: ald_timer.c:3168
ald_timer_pwm_start_by_it
void ald_timer_pwm_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
Starts the PWM signal generation in interrupt mode.
Definition: ald_timer.c:659
ald_timer_base_init
ald_status_t ald_timer_base_init(timer_handle_t *hperh)
Initializes the TIMER Time base Unit according to the specified parameters in the timer_handle_t and ...
Definition: ald_timer.c:97
timer_channel_config_t::n_en
type_func_t n_en
Definition: ald_timer.h:441
TIMER_OC_MODE_PWM1
Definition: ald_timer.h:70
TIMER_CLOCK_DIV2
Definition: ald_timer.h:56
ald_timer_hall_sensor_start_by_it
void ald_timer_hall_sensor_start_by_it(timer_handle_t *hperh)
Starts the TIMER hall sensor interface in interrupt mode.
Definition: ald_timer.c:1678
timer_oc_init_t::oc_fast_en
type_func_t oc_fast_en
Definition: ald_timer.h:152
ald_timer_interrupt_config
void ald_timer_interrupt_config(timer_handle_t *hperh, timer_it_t it, type_func_t state)
Enable/disable the specified TIMER interrupts.
Definition: ald_timer.c:3075
TIMER_SRC_CC2
Definition: ald_timer.h:480
timer_clear_input_config_t::state
type_func_t state
Definition: ald_timer.h:313
TIMER_CLOCK_DIV4
Definition: ald_timer.h:57
ald_timer_com_change_config
void ald_timer_com_change_config(timer_handle_t *hperh, timer_com_channel_config_t *config)
Configure the channel in commutation event.
Definition: ald_timer.c:2777
timer_clock_config_t::psc
timer_etr_psc_t psc
Definition: ald_timer.h:352
ald_timer_oc_stop_by_it
void ald_timer_oc_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Output Compare signal generation in interrupt mode.
Definition: ald_timer.c:400
TIMER_SRC_INTER
Definition: ald_timer.h:325
TIMER_TS_TI1F_ED
Definition: ald_timer.h:378
TIMER_OP_OUTPUT_CHANNEL_1
Definition: ald_timer.h:129
ald_timer_pwm_stop
void ald_timer_pwm_stop(timer_handle_t *hperh, timer_channel_t ch)
Stops the PWM signal generation.
Definition: ald_timer.c:642
TIMER_IC_SEL_TRC
Definition: ald_timer.h:228
timer_op_output_channel_t
timer_op_output_channel_t
TIMER one pulse output channel.
Definition: ald_timer.h:128
TIMER_FLAG_CC1
Definition: ald_timer.h:520
TIMER_IC_PSC_DIV4
Definition: ald_timer.h:237
timer_hall_sensor_init_t::psc
timer_ic_prescaler_t psc
Definition: ald_timer.h:400
timer_clock_config_t
TIMER clock config structure definition.
Definition: ald_timer.h:349
ald_timer_break_dead_time_config
void ald_timer_break_dead_time_config(timer_handle_t *hperh, timer_break_dead_time_t *config)
Configure the break, dead timere, lock level state.
Definition: ald_timer.c:2875
TIMER_CHANNEL_1
Definition: ald_timer.h:110
ald_timer_pwmn_start_by_dma
ald_status_t ald_timer_pwmn_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER PWM signal generation on the complementary output. in DMA mode.
Definition: ald_timer.c:2140
timer_base_init_t::period
uint32_t period
Definition: ald_timer.h:139
ald_timer_clear_flag_status
void ald_timer_clear_flag_status(timer_handle_t *hperh, timer_flag_t flag)
Clear the TIMER interrupt flag.
Definition: ald_timer.c:3136
ald_timer_oc_init
ald_status_t ald_timer_oc_init(timer_handle_t *hperh)
Initializes the TIMER Output Compare according to the specified parameters in the timer_handle_t and ...
Definition: ald_timer.c:290
timer_handle_s::init
timer_base_init_t init
Definition: ald_timer.h:184
TIMER_TRGO_UPDATE
Definition: ald_timer.h:458
timer_slave_config_t::mode
timer_slave_mode_t mode
Definition: ald_timer.h:388
TIMER_ENC_MODE_TI1
Definition: ald_timer.h:209
timer_oc_init_t::ocn_polarity
timer_ocn_polarity_t ocn_polarity
Definition: ald_timer.h:151
timer_clear_input_config_t::psc
timer_etr_psc_t psc
Definition: ald_timer.h:316
TIMER_IT_CC2
Definition: ald_timer.h:494
TIMER_BREAK_POLARITY_LOW
Definition: ald_timer.h:419
timer_one_pulse_init_t::polarity
timer_ic_polarity_t polarity
Definition: ald_timer.h:276
ald_timer_slave_config_sync_by_it
ald_status_t ald_timer_slave_config_sync_by_it(timer_handle_t *hperh, timer_slave_config_t *config)
Configures the TIMER in Slave mode in interrupt mode.
Definition: ald_timer.c:2651
timer_clock_config_t::polarity
timer_clock_polarity_t polarity
Definition: ald_timer.h:351
ald_timer_pwmn_stop
void ald_timer_pwmn_stop(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER PWM signal generation on the complementary output.
Definition: ald_timer.c:2088
TIMER_POLARITY_NO_INV
Definition: ald_timer.h:291
ald_timer_read_capture_value
uint32_t ald_timer_read_capture_value(timer_handle_t *hperh, timer_channel_t ch)
Read the captured value from Capture Compare unit.
Definition: ald_timer.c:2703
TIMER_STATE_BUSY
Definition: ald_timer.h:163
timer_break_dead_time_t::off_idle
type_func_t off_idle
Definition: ald_timer.h:428
timer_slave_config_t::psc
timer_etr_psc_t psc
Definition: ald_timer.h:391
TIMER_TRGO_RESET
Definition: ald_timer.h:456
TIMER_SRC_ETRMODE1
Definition: ald_timer.h:333
TIMER_CLK_POLARITY_RISE
Definition: ald_timer.h:341
ald_timer_ocn_start
void ald_timer_ocn_start(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER output compare signal generation on the complementary output.
Definition: ald_timer.c:1804
ald_timer_ocn_stop_by_dma
void ald_timer_ocn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER output compare signal generation on the complementary output. in DMA mode...
Definition: ald_timer.c:2012
timer_handle_s::hdma1
dma_handle_t hdma1
Definition: ald_timer.h:190
ald_timer_pwm_stop_by_it
void ald_timer_pwm_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
Stops the PWM signal generation in interrupt mode.
Definition: ald_timer.c:676
TIMER_BREAK_POLARITY_HIGH
Definition: ald_timer.h:420
ald_timer_base_reset
void ald_timer_base_reset(timer_handle_t *hperh)
Reset the TIMER base peripheral.
Definition: ald_timer.c:121
timer_handle_s::com_cbk
void(* com_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:200
timer_handle_s
TIMER time base handle structure definition.
Definition: ald_timer.h:182
ald_timer_get_flag_status
flag_status_t ald_timer_get_flag_status(timer_handle_t *hperh, timer_flag_t flag)
Get the status of TIMER interrupt flag.
Definition: ald_timer.c:3118
timer_clear_input_config_t::source
timer_clear_input_source_t source
Definition: ald_timer.h:314
timer_one_pulse_init_t::pulse
uint16_t pulse
Definition: ald_timer.h:271
ald_timer_oc_stop_by_dma
void ald_timer_oc_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Output Compare signal generation in DMA mode.
Definition: ald_timer.c:544
TIMER_ETR_PSC_DIV1
Definition: ald_timer.h:298
ald_timer_oc_config_channel
ald_status_t ald_timer_oc_config_channel(timer_handle_t *hperh, timer_oc_init_t *config, timer_channel_t ch)
Initializes the TIMER Output Compare Channels according to the specified parameters in the timer_oc_i...
Definition: ald_timer.c:2281
ald_timer_ic_stop_by_dma
void ald_timer_ic_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Input Capture measurement in DMA mode.
Definition: ald_timer.c:1060
ald_timer_pwm_set_freq
void ald_timer_pwm_set_freq(timer_handle_t *hperh, uint16_t freq)
Set the PWM freq.
Definition: ald_timer.c:726
timer_it_t
timer_it_t
TIMER interrupt definition.
Definition: ald_timer.h:491
TIMER_SRC_CC3
Definition: ald_timer.h:481
timer_op_mode_t
timer_op_mode_t
TIMER one pulse mode.
Definition: ald_timer.h:120
timer_encoder_init_t::ic2_filter
uint32_t ic2_filter
Definition: ald_timer.h:253
ald_timer_base_start
void ald_timer_base_start(timer_handle_t *hperh)
Starts the TIMER Base generation.
Definition: ald_timer.c:138
TIMER_CLOCK_DIV1
Definition: ald_timer.h:55
TIMER_TS_ETRF
Definition: ald_timer.h:381
utils.h
This file contains the Utilities functions/types for the driver.
timer_encoder_mode_t
timer_encoder_mode_t
TIMER encoder mode.
Definition: ald_timer.h:208
timer_active_channel_t
timer_active_channel_t
Active channel structures definition.
Definition: ald_timer.h:171
TIMER_IC_PSC_DIV2
Definition: ald_timer.h:236
timer_encoder_init_t::ic1_filter
uint32_t ic1_filter
Definition: ald_timer.h:249
timer_handle_s::perh
TIMER_TypeDef * perh
Definition: ald_timer.h:183
timer_etr_psc_t
timer_etr_psc_t
TIMER clear input polarity.
Definition: ald_timer.h:297
TIMER_MODE_GATED
Definition: ald_timer.h:365
timer_encoder_init_t::mode
timer_encoder_mode_t mode
Definition: ald_timer.h:245
ald_timer_base_stop_by_it
void ald_timer_base_stop_by_it(timer_handle_t *hperh)
Stops the TIMER Base generation in interrupt mode.
Definition: ald_timer.c:185
timer_one_pulse_init_t::ocn_polarity
timer_ocn_polarity_t ocn_polarity
Definition: ald_timer.h:273
timer_oc_init_t
TIMER output compare configuration structure definition.
Definition: ald_timer.h:147
timer_break_dead_time_t::break_state
type_func_t break_state
Definition: ald_timer.h:431
timer_oc_idle_t
timer_oc_idle_t
TIMER output compare idle state.
Definition: ald_timer.h:93
TIMER_FLAG_CC3
Definition: ald_timer.h:522
TIMER_MODE_DISABLE
Definition: ald_timer.h:360
timer_oc_init_t::ocn_idle
timer_ocn_idle_t ocn_idle
Definition: ald_timer.h:154
TIMER_SRC_CC1
Definition: ald_timer.h:479
TIMER_TS_TI2FP2
Definition: ald_timer.h:380
timer_encoder_init_t::ic2_sel
timer_ic_select_t ic2_sel
Definition: ald_timer.h:251
TIMER_DMA_CC2
Definition: ald_timer.h:508
TIMER_OC_MODE_INACTIVE
Definition: ald_timer.h:66
TIMER_STATE_TIMEREOUT
Definition: ald_timer.h:164
it_status_t
enum flag_status_t it_status_t
timer_slave_config_t::polarity
timer_clock_polarity_t polarity
Definition: ald_timer.h:390
timer_oc_init_t::oc_polarity
timer_oc_polarity_t oc_polarity
Definition: ald_timer.h:150
timer_lock_level_t
timer_lock_level_t
TIMER lock level.
Definition: ald_timer.h:408
TIMER_ENC_MODE_TI2
Definition: ald_timer.h:210
TIMER_CLK_POLARITY_NO_INV
Definition: ald_timer.h:340
ald_timer_ocn_stop
void ald_timer_ocn_stop(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER output compare signal generation on the complementary output.
Definition: ald_timer.c:1825
TIMER_OP_MODE_REPEAT
Definition: ald_timer.h:121
timer_one_pulse_init_t::sel
timer_ic_select_t sel
Definition: ald_timer.h:277
ald_timer_one_pulse_start
void ald_timer_one_pulse_start(timer_handle_t *hperh, timer_op_output_channel_t ch)
Starts the TIMER One Pulse signal generation.
Definition: ald_timer.c:1151
ald_timer_ic_start
void ald_timer_ic_start(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Input Capture measurement.
Definition: ald_timer.c:857
TIMER_DMA_UPDATE
Definition: ald_timer.h:506
ald_timer_encoder_start
void ald_timer_encoder_start(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Encoder Interface.
Definition: ald_timer.c:1318
ald_timer_pwm_stop_by_dma
void ald_timer_pwm_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER PWM signal generation in DMA mode.
Definition: ald_timer.c:714
ald_timer_pwm_set_duty
void ald_timer_pwm_set_duty(timer_handle_t *hperh, timer_channel_t ch, uint16_t duty)
Set the PWM duty.
Definition: ald_timer.c:750
TIMER_OCN_POLARITY_HIGH
Definition: ald_timer.h:86
ald_timer_hall_sensor_stop_by_it
void ald_timer_hall_sensor_stop_by_it(timer_handle_t *hperh)
Stops the TIMER hall sensor interface in interrupt mode.
Definition: ald_timer.c:1694
TIMER_CLK_POLARITY_BOTH
Definition: ald_timer.h:343
timer_slave_config_t
TIMER slave configuration structure definition.
Definition: ald_timer.h:387
timer_one_pulse_init_t::mode
timer_oc_mode_t mode
Definition: ald_timer.h:270
ald_timer_encoder_start_by_dma
ald_status_t ald_timer_encoder_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf1, uint16_t *buf2, uint32_t len, uint8_t dma_ch1, uint8_t dma_ch2)
Starts the TIMER Encoder Interface in DMA mode.
Definition: ald_timer.c:1457
ald_timer_oc_start_by_it
void ald_timer_oc_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Output Compare signal generation in interrupt mode.
Definition: ald_timer.c:355
ald_timer_oc_stop
void ald_timer_oc_stop(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Output Compare signal generation.
Definition: ald_timer.c:330
timer_event_source_t
timer_event_source_t
Specifies the event source.
Definition: ald_timer.h:477
timer_one_pulse_init_t::oc_idle
timer_oc_idle_t oc_idle
Definition: ald_timer.h:274
TIMER_OC_MODE_FORCE_INACTIVE
Definition: ald_timer.h:68
TIMER_CHANNEL_ALL
Definition: ald_timer.h:114
timer_channel_config_t::mode
timer_oc_mode_t mode
Definition: ald_timer.h:442
timer_base_init_t::prescaler
uint32_t prescaler
Definition: ald_timer.h:137
timer_clock_source_t
timer_clock_source_t
TIMER clock source.
Definition: ald_timer.h:323
timer_oc_mode_t
timer_oc_mode_t
TIMER output compare and PWM modes.
Definition: ald_timer.h:63
TIMER_SRC_ITR3
Definition: ald_timer.h:329
timer_handle_s::state
timer_state_t state
Definition: ald_timer.h:187
TIMER_ACTIVE_CHANNEL_CLEARED
Definition: ald_timer.h:176
TIMER_OP_OUTPUT_CHANNEL_2
Definition: ald_timer.h:130
TIMER_SRC_TI1
Definition: ald_timer.h:331
TIMER_FLAG_CC4
Definition: ald_timer.h:523
TIMER_INPUT_NONE
Definition: ald_timer.h:284
TIMER_IC_PSC_DIV8
Definition: ald_timer.h:238
TIMER_CNT_MODE_CENTER1
Definition: ald_timer.h:46
ald_timer_ic_start_by_dma
ald_status_t ald_timer_ic_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER Input Capture measurement in DMA mode.
Definition: ald_timer.c:975
TIMER_IT_BREAK
Definition: ald_timer.h:499
timer_break_dead_time_t
TIMER break and dead time configuretion structure definition.
Definition: ald_timer.h:426
TIMER_INPUT_ETR
Definition: ald_timer.h:285
timer_flag_t
timer_flag_t
TIMER flag definition.
Definition: ald_timer.h:518
ald_timer_get_it_status
it_status_t ald_timer_get_it_status(timer_handle_t *hperh, timer_it_t it)
Get the status of TIMER interrupt source.
Definition: ald_timer.c:3098
timer_state_t
timer_state_t
State structures definition.
Definition: ald_timer.h:160
TIMER_CNT_MODE_UP
Definition: ald_timer.h:44
lock_state_t
lock_state_t
Definition: type.h:58
TIMER_TRGO_ENABLE
Definition: ald_timer.h:457
ald_dma.h
DMA module Library.
ald_timer_master_sync_config
void ald_timer_master_sync_config(timer_handle_t *hperh, timer_master_config_t *config)
Configure the master mode.
Definition: ald_timer.c:2908
TIMER_OC_MODE_TOGGLE
Definition: ald_timer.h:67
timer_channel_config_t::en
type_func_t en
Definition: ald_timer.h:440
ald_timer_one_pulse_start_by_it
void ald_timer_one_pulse_start_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch)
Starts the TIMER One Pulse signal generation in interrupt mode.
Definition: ald_timer.c:1198
timer_clear_input_config_t::clrsel
timer_chnref_clr_sel_t clrsel
Definition: ald_timer.h:317
TIMER_IC_PSC_DIV1
Definition: ald_timer.h:235
TIMER_TS_ITR2
Definition: ald_timer.h:376
ald_timer_encoder_stop_by_dma
void ald_timer_encoder_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Encoder Interface in DMA mode.
Definition: ald_timer.c:1552
timer_dma_req_t
timer_dma_req_t
TIMER DMA request.
Definition: ald_timer.h:505
timer_master_config_t::master_en
type_func_t master_en
Definition: ald_timer.h:471
TIMER_SRC_ITR2
Definition: ald_timer.h:328
ald_timer_oc_start_by_dma
ald_status_t ald_timer_oc_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER Output Compare signal generation in DMA mode.
Definition: ald_timer.c:454
TIMER_SRC_TI2
Definition: ald_timer.h:332
ald_timer_com_event_config_it
void ald_timer_com_event_config_it(timer_handle_t *hperh, timer_ts_t ts, type_func_t trgi)
Configure the TIMER commutation event sequence with interrupt.
Definition: ald_timer.c:2863
TIMER_MODE_RESET
Definition: ald_timer.h:364
timer_ic_polarity_t
timer_ic_polarity_t
TIMER input capture polarity.
Definition: ald_timer.h:217
timer_oc_polarity_t
timer_oc_polarity_t
TIMER output compare polarity.
Definition: ald_timer.h:77
timer_encoder_init_t::ic1_psc
timer_ic_prescaler_t ic1_psc
Definition: ald_timer.h:248
TIMER_OC_POLARITY_HIGH
Definition: ald_timer.h:78
TIMER_DMA_CC3
Definition: ald_timer.h:509
timer_hall_sensor_init_t
TIMER hall sensor configuretion structure definition.
Definition: ald_timer.h:398
TIMER_IC_SEL_INDIRECT
Definition: ald_timer.h:227
timer_encoder_init_t
TIMER encoder configuration structure definition.
Definition: ald_timer.h:244
TIMER_FLAG_TRIGGER
Definition: ald_timer.h:525
timer_ocn_idle_t
timer_ocn_idle_t
TIMER complementary output compare idle state.
Definition: ald_timer.h:101
ald_timer_irq_handler
void ald_timer_irq_handler(timer_handle_t *hperh)
This function handles TIMER interrupts requests.
Definition: ald_timer.c:2927
ald_timer_hall_sensor_init
ald_status_t ald_timer_hall_sensor_init(timer_handle_t *hperh, timer_hall_sensor_init_t *config)
Initializes the TIMER Encoder Interface and create the associated handle.
Definition: ald_timer.c:1608
TIMER_TRGO_OC1
Definition: ald_timer.h:459
ald_timer_oc_start
void ald_timer_oc_start(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Output Compare signal generation.
Definition: ald_timer.c:306
TIMER_FLAG_CC3OF
Definition: ald_timer.h:529
ald_timer_ic_start_by_it
void ald_timer_ic_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Input Capture measurement in interrupt mode.
Definition: ald_timer.c:897
TIMER_OC_IDLE_RESET
Definition: ald_timer.h:94
TIMER_FLAG_CC2
Definition: ald_timer.h:521
TIMER_IC_POLARITY_RISE
Definition: ald_timer.h:218
TIMER_CHANNEL_4
Definition: ald_timer.h:113
timer_base_init_t
TIMER time base configuration structure definition.
Definition: ald_timer.h:136
ald_timer_one_pulse_n_stop
void ald_timer_one_pulse_n_stop(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER one pulse signal generation on the complementary output.
Definition: ald_timer.c:2207
timer_clear_input_config_t::filter
uint32_t filter
Definition: ald_timer.h:318
timer_oc_init_t::pulse
uint32_t pulse
Definition: ald_timer.h:149
timer_slave_config_t::input
timer_ts_t input
Definition: ald_timer.h:389
TIMER_TRGO_OC3REF
Definition: ald_timer.h:462
timer_hall_sensor_init_t::polarity
timer_ic_polarity_t polarity
Definition: ald_timer.h:399
ald_timer_hall_sensor_start
void ald_timer_hall_sensor_start(timer_handle_t *hperh)
Starts the TIMER hall sensor interface.
Definition: ald_timer.c:1648
TIMER_IT_CC3
Definition: ald_timer.h:495
ald_timer_ocn_stop_by_it
void ald_timer_ocn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER output compare signal generation on the complementary output. in interrupt mode...
Definition: ald_timer.c:1886
TIMER_IT_TRIGGER
Definition: ald_timer.h:498
ald_timer_pwm_start_by_dma
ald_status_t ald_timer_pwm_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER PWM signal generation in DMA mode.
Definition: ald_timer.c:697
timer_one_pulse_init_t::ocn_idle
timer_ocn_idle_t ocn_idle
Definition: ald_timer.h:275
timer_oc_init_t::oc_mode
timer_oc_mode_t oc_mode
Definition: ald_timer.h:148
timer_master_config_t
TIMER master configuretion structure definition.
Definition: ald_timer.h:469
timer_handle_s::error_cbk
void(* error_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:201
timer_handle_s::delay_elapse_cbk
void(* delay_elapse_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:195
timer_clear_input_config_t
TIMER clear input configuration handle structure definition.
Definition: ald_timer.h:312
TIMER_ETR_PSC_DIV2
Definition: ald_timer.h:299
ald_timer_base_stop_by_dma
void ald_timer_base_stop_by_dma(timer_handle_t *hperh)
Stops the TIMER Base generation in DMA mode.
Definition: ald_timer.c:249
TIMER_ACTIVE_CHANNEL_1
Definition: ald_timer.h:172
TIMER_LOCK_LEVEL_OFF
Definition: ald_timer.h:409
ald_timer_pwm_init
ald_status_t ald_timer_pwm_init(timer_handle_t *hperh)
Initializes the TIMER PWM Time Base according to the specified parameters in the timer_handle_t and c...
Definition: ald_timer.c:609
timer_clear_input_config_t::polarity
timer_clear_input_polarity_t polarity
Definition: ald_timer.h:315
TIMER_ETR_PSC_DIV4
Definition: ald_timer.h:300
TIMER_IT_UPDATE
Definition: ald_timer.h:492
ald_timer_hall_sensor_start_by_dma
ald_status_t ald_timer_hall_sensor_start_by_dma(timer_handle_t *hperh, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER hall sensor interface in DMA mode.
Definition: ald_timer.c:1714
timer_handle_s::ch
timer_active_channel_t ch
Definition: ald_timer.h:185
TIMER_MODE_TRIG
Definition: ald_timer.h:366
ald_timer_pwmn_start_by_it
void ald_timer_pwmn_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER PWM signal generation on the complementary output. in interrupt mode.
Definition: ald_timer.c:2104
ald_timer_ocn_start_by_dma
ald_status_t ald_timer_ocn_start_by_dma(timer_handle_t *hperh, timer_channel_t ch, uint16_t *buf, uint32_t len, uint8_t dma_ch)
Starts the TIMER output compare signal generation on the complementary output. in DMA mode...
Definition: ald_timer.c:1934
timer_ocn_polarity_t
timer_ocn_polarity_t
TIMER complementary output compare polarity.
Definition: ald_timer.h:85
timer_master_mode_sel_t
timer_master_mode_sel_t
TIMER master mode selection.
Definition: ald_timer.h:455
TIMER_OC_MODE_FORCE_ACTIVE
Definition: ald_timer.h:69
timer_handle_s::pwm_pulse_finish_cbk
void(* pwm_pulse_finish_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:197
ald_timer_base_stop
void ald_timer_base_stop(timer_handle_t *hperh)
Stops the TIMER Base generation.
Definition: ald_timer.c:154
TIMER_MODE_EXTERNAL1
Definition: ald_timer.h:367
TIMER_OC_POLARITY_LOW
Definition: ald_timer.h:79
TIMER_TS_ITR1
Definition: ald_timer.h:375
TIMER_MODE_ENC3
Definition: ald_timer.h:363
timer_hall_sensor_init_t::filter
uint32_t filter
Definition: ald_timer.h:401
TIMER_SRC_ETRMODE2
Definition: ald_timer.h:324
TIMER_CHNREF_CLR_CMP_IN
Definition: ald_timer.h:307
ald_timer_pwm_start
void ald_timer_pwm_start(timer_handle_t *hperh, timer_channel_t ch)
Starts the PWM signal generation.
Definition: ald_timer.c:625
timer_slave_config_t::filter
uint32_t filter
Definition: ald_timer.h:392
TIMER_FLAG_BREAK
Definition: ald_timer.h:526
ald_timer_encoder_start_by_it
void ald_timer_encoder_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER Encoder Interface in interrupt mode.
Definition: ald_timer.c:1380
ald_timer_ocn_start_by_it
void ald_timer_ocn_start_by_it(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER output compare signal generation on the complementary output. in interrupt mode...
Definition: ald_timer.c:1847
TIMER_ACTIVE_CHANNEL_4
Definition: ald_timer.h:175
TIMER_FLAG_COM
Definition: ald_timer.h:524
timer_chnref_clr_sel_t
timer_chnref_clr_sel_t
TIMER CHnREF Clear Select.
Definition: ald_timer.h:306
timer_ic_init_t::filter
uint32_t filter
Definition: ald_timer.h:263
TIMER_IC_POLARITY_FALL
Definition: ald_timer.h:219
timer_break_dead_time_t::polarity
timer_break_polarity_t polarity
Definition: ald_timer.h:432
timer_hall_sensor_init_t::delay
uint32_t delay
Definition: ald_timer.h:402
TIMER_ENC_MODE_TI12
Definition: ald_timer.h:211
TIMER_POLARITY_INV
Definition: ald_timer.h:292
timer_break_dead_time_t::dead_time
uint32_t dead_time
Definition: ald_timer.h:430
ald_timer_generate_event
ald_status_t ald_timer_generate_event(timer_handle_t *hperh, timer_event_source_t event)
Generate a software event.
Definition: ald_timer.c:2678
flag_status_t
flag_status_t
Definition: type.h:37
TIMER_FLAG_UPDATE
Definition: ald_timer.h:519
TIMER_TRGO_OC1REF
Definition: ald_timer.h:460
TIMER_CNT_MODE_DOWN
Definition: ald_timer.h:45
TIMER_TS_ITR0
Definition: ald_timer.h:374
timer_handle_s::period_elapse_cbk
void(* period_elapse_cbk)(struct timer_handle_s *arg)
Definition: ald_timer.h:194
timer_base_init_t::mode
timer_cnt_mode_t mode
Definition: ald_timer.h:138
ald_timer_ic_config_channel
ald_status_t ald_timer_ic_config_channel(timer_handle_t *hperh, timer_ic_init_t *config, timer_channel_t ch)
Initializes the TIMER Input Capture Channels according to the specified parameters in the timer_ic_in...
Definition: ald_timer.c:2329
TIMER_OP_MODE_SINGLE
Definition: ald_timer.h:122
timer_ic_init_t
TIMER input capture configuration structure definition.
Definition: ald_timer.h:259
timer_clock_division_t
timer_clock_division_t
TIMER clock division.
Definition: ald_timer.h:54
ald_timer_encoder_init
ald_status_t ald_timer_encoder_init(timer_handle_t *hperh, timer_encoder_init_t *config)
Initializes the TIMER Encoder Interface and create the associated handle.
Definition: ald_timer.c:1269
timer_encoder_init_t::ic2_psc
timer_ic_prescaler_t ic2_psc
Definition: ald_timer.h:252
timer_handle_t
struct timer_handle_s timer_handle_t
TIMER time base handle structure definition.
ald_timer_dma_req_config
void ald_timer_dma_req_config(timer_handle_t *hperh, timer_dma_req_t req, type_func_t state)
Configure DMA request source.
Definition: ald_timer.c:3050
ald_timer_pwmn_stop_by_dma
void ald_timer_pwmn_stop_by_dma(timer_handle_t *hperh, timer_channel_t ch)
Starts the TIMER PWM signal generation on the complementary output. in DMA mode.
Definition: ald_timer.c:2157
ald_timer_one_pulse_stop_by_it
void ald_timer_one_pulse_stop_by_it(timer_handle_t *hperh, timer_op_output_channel_t ch)
Stops the TIMER One Pulse signal generation in interrupt mode.
Definition: ald_timer.c:1226
ald_timer_one_pulse_init
ald_status_t ald_timer_one_pulse_init(timer_handle_t *hperh, timer_op_mode_t mode)
Initializes the TIMER One Pulse Time Base according to the specified parameters in the timer_handle_t...
Definition: ald_timer.c:1121
TIMER_TS_ITR3
Definition: ald_timer.h:377
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
TIMER_DMA_COM
Definition: ald_timer.h:511
timer_encoder_init_t::ic2_polarity
timer_ic_polarity_t ic2_polarity
Definition: ald_timer.h:250
timer_break_dead_time_t::lock_level
timer_lock_level_t lock_level
Definition: ald_timer.h:429
TIMER_MODE_ENC1
Definition: ald_timer.h:361
TIMER_DMA_CC1
Definition: ald_timer.h:507
TIMER_DMA_CC4
Definition: ald_timer.h:510
timer_handle_s::lock
lock_state_t lock
Definition: ald_timer.h:186
ald_timer_ic_init
ald_status_t ald_timer_ic_init(timer_handle_t *hperh)
Initializes the TIMER Input Capture Time base according to the specified parameters in the timer_hand...
Definition: ald_timer.c:841
TIMER_SRC_TRIG
Definition: ald_timer.h:484
ald_timer_config_oc_ref_clear
ald_status_t ald_timer_config_oc_ref_clear(timer_handle_t *hperh, timer_clear_input_config_t *config, timer_channel_t ch)
Configures the OCRef clear feature.
Definition: ald_timer.c:2460
ald_timer_hall_sensor_stop
void ald_timer_hall_sensor_stop(timer_handle_t *hperh)
Stops the TIMER hall sensor interface.
Definition: ald_timer.c:1663
timer_channel_t
timer_channel_t
TIMER channel.
Definition: ald_timer.h:109
ald_timer_config_ti1_input
ald_status_t ald_timer_config_ti1_input(timer_handle_t *hperh, uint32_t ti1_select)
Selects the signal connected to the TI1 input: direct from CH1_input or a XOR combination between CH1...
Definition: ald_timer.c:2604
TIMER_LOCK_LEVEL_3
Definition: ald_timer.h:412
TIMER_IT_COM
Definition: ald_timer.h:497
ald_timer_ic_stop
void ald_timer_ic_stop(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Input Capture measurement.
Definition: ald_timer.c:877
timer_ic_init_t::sel
timer_ic_select_t sel
Definition: ald_timer.h:261
TIMER_SRC_ITR0
Definition: ald_timer.h:326
ald_timer_encoder_stop
void ald_timer_encoder_stop(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Encoder Interface.
Definition: ald_timer.c:1349
TIMER_MODE_ENC2
Definition: ald_timer.h:362
TIMER_SRC_BREAK
Definition: ald_timer.h:485
TIMER_STATE_ERROR
Definition: ald_timer.h:165
TIMER_OCN_POLARITY_LOW
Definition: ald_timer.h:87
TIMER_CHANNEL_2
Definition: ald_timer.h:111
TIMER_FLAG_CC2OF
Definition: ald_timer.h:528
TIMER_SRC_COM
Definition: ald_timer.h:483
TIMER_SRC_TI1ED
Definition: ald_timer.h:330
TIMER_OC_MODE_TIMERING
Definition: ald_timer.h:64
ald_timer_one_pulse_config_channel
ald_status_t ald_timer_one_pulse_config_channel(timer_handle_t *hperh, timer_one_pulse_init_t *config, timer_channel_t ch_out, timer_channel_t ch_in)
Initializes the TIMER One Pulse Channels according to the specified parameters in the timer_one_pulse...
Definition: ald_timer.c:2385
timer_channel_config_t
TIMER commutation event channel configuretion structure definition.
Definition: ald_timer.h:439
TIMER_LOCK_LEVEL_1
Definition: ald_timer.h:410
TIMER_OC_IDLE_SET
Definition: ald_timer.h:95
ald_timer_encoder_stop_by_it
void ald_timer_encoder_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER Encoder Interface in interrupt mode.
Definition: ald_timer.c:1415
timer_ic_select_t
timer_ic_select_t
TIMER input capture selection.
Definition: ald_timer.h:225
TIMER_ETR_PSC_DIV8
Definition: ald_timer.h:301
timer_clock_config_t::filter
uint32_t filter
Definition: ald_timer.h:353
TIMER_OCN_IDLE_RESET
Definition: ald_timer.h:102
ald_timer_pwmn_stop_by_it
void ald_timer_pwmn_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER PWM signal generation on the complementary output. in interrupt mode.
Definition: ald_timer.c:2120
timer_clear_input_source_t
timer_clear_input_source_t
TIMER clear input source.
Definition: ald_timer.h:283
timer_encoder_init_t::ic1_sel
timer_ic_select_t ic1_sel
Definition: ald_timer.h:247
timer_com_channel_config_t
TIMER commutation event configuretion structure definition.
Definition: ald_timer.h:448
timer_one_pulse_init_t::filter
uint32_t filter
Definition: ald_timer.h:278
ald_timer_one_pulse_n_stop_by_it
void ald_timer_one_pulse_n_stop_by_it(timer_handle_t *hperh, timer_channel_t ch)
Stops the TIMER one pulse signal generation on the complementary output. in interrupt mode...
Definition: ald_timer.c:2237
TIMER_LOCK_LEVEL_2
Definition: ald_timer.h:411
ald_timer_one_pulse_stop
void ald_timer_one_pulse_stop(timer_handle_t *hperh, timer_op_output_channel_t ch)
Stops the TIMER One Pulse signal generation.
Definition: ald_timer.c:1177
timer_clear_input_polarity_t
timer_clear_input_polarity_t
TIMER clear input polarity.
Definition: ald_timer.h:290
timer_break_dead_time_t::auto_out
type_func_t auto_out
Definition: ald_timer.h:433
TIMER_FLAG_CC4OF
Definition: ald_timer.h:530
timer_one_pulse_init_t
TIMER one pulse mode configuration structure definition.
Definition: ald_timer.h:269


ALD User Manual: D:/svn/src/ald_trng.c Source File

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  • svn
  • src
ald_trng.c
Go to the documentation of this file.
1
17 #include "ald_trng.h"
18
19
28 #ifdef ALD_TRNG
29
33 void trng_reset(trng_handle_t *hperh);
69 ald_status_t ald_trng_init(trng_handle_t *hperh)
70 {
71 uint32_t tmp = 0;
72
73 if (hperh == NULL)
74 return ERROR;
75
76 assert_param(IS_TRNG_DATA_WIDTH(hperh->init.data_width));
77 assert_param(IS_TRNG_SEED_TYPE(hperh->init.seed_type));
78 assert_param(IS_TRNG_ADJC(hperh->init.adjc));
79 assert_param(IS_FUNC_STATE(hperh->init.posten));
80 assert_param(IS_TRNG_T_START(hperh->init.t_start));
81
82 __LOCK(hperh);
83 trng_reset(hperh);
84
85 if (hperh->state == TRNG_STATE_RESET)
86 __UNLOCK(hperh);
87
88 tmp = TRNG->CR;
89
90 if (hperh->init.adjc == 0)
91 tmp = (0 << TRNG_CR_ADJM_POS);
92 else
93 tmp = (1 << TRNG_CR_ADJM_POS);
94
95 tmp |= ((1 << TRNG_CR_TRNGSEL_POS) | (hperh->init.data_width << TRNG_CR_DSEL_POSS) |
96 (hperh->init.seed_type << TRNG_CR_SDSEL_POSS) | (hperh->init.adjc << TRNG_CR_ADJC_POSS) |
97 (hperh->init.posten << TRNG_CR_POSTEN_MSK));
98
99 TRNG->CR = tmp;
100
101 WRITE_REG(TRNG->SEED, hperh->init.seed);
102 MODIFY_REG(TRNG->CFGR, TRNG_CFGR_TSTART_MSK, (hperh->init.t_start) << TRNG_CFGR_TSTART_POSS);
103
104 hperh->state = TRNG_STATE_READY;
105 __UNLOCK(hperh);
106 return OK;
107 }
137 uint32_t ald_trng_get_result(trng_handle_t *hperh)
138 {
139 hperh->state = TRNG_STATE_READY;
140 hperh->data = hperh->perh->DR;
141 return (uint32_t)hperh->perh->DR;
142 }
143
156 void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t state)
157 {
158 assert_param(IS_TRNG_IT(it));
159 assert_param(IS_FUNC_STATE(state));
160
161 if (state)
162 SET_BIT(hperh->perh->IER, it);
163 else
164 CLEAR_BIT(hperh->perh->IER, it);
165
166 return;
167 }
168
179 flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status)
180 {
181 assert_param(IS_TRNG_STATUS(status));
182
183 if (READ_BIT(hperh->perh->SR, status))
184 return SET;
185
186 return RESET;
187 }
188
199 it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it)
200 {
201 assert_param(IS_TRNG_IT(it));
202
203 if (READ_BIT(hperh->perh->IER, it))
204 return SET;
205
206 return RESET;
207 }
208
219 flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag)
220 {
221 assert_param(IS_TRNG_FLAG(flag));
222
223 if (READ_BIT(hperh->perh->IFR, flag))
224 return SET;
225
226 return RESET;
227 }
228
237 void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag)
238 {
239 assert_param(IS_TRNG_FLAG(flag));
240 WRITE_REG(hperh->perh->IFCR, flag);
241
242 return;
243 }
244
251 void trng_reset(trng_handle_t *hperh)
252 {
253 TRNG->CR = 0;
254 TRNG->SEED = 0;
255 TRNG->CFGR = 0x1FF0707;
256 TRNG->IER = 0;
257 TRNG->IFCR = 0xFFFFFFFF;
258
259 hperh->state = TRNG_STATE_READY;
260 __UNLOCK(hperh);
261 return;
262 }
263
270 void ald_trng_irq_handler(trng_handle_t *hperh)
271 {
272 if (ald_trng_get_flag_status(hperh, TRNG_IF_SERR) == SET) {
273 hperh->state = TRNG_STATE_ERROR;
274 ald_trng_clear_flag_status(hperh, TRNG_IF_SERR);
275 if (hperh->err_cplt_cbk)
276 hperh->err_cplt_cbk(hperh);
277 return;
278 }
279
280 if (ald_trng_get_flag_status(hperh, TRNG_IF_DAVLD) == SET) {
281 hperh->data = hperh->perh->DR;
282 hperh->state = TRNG_STATE_READY;
283 ald_trng_clear_flag_status(hperh, TRNG_IF_DAVLD);
284 if (hperh->trng_cplt_cbk)
285 hperh->trng_cplt_cbk(hperh);
286 }
287
288 if (ald_trng_get_flag_status(hperh, TRNG_IF_START) == SET) {
289 hperh->state = TRNG_STATE_BUSY;
290 ald_trng_clear_flag_status(hperh, TRNG_IF_START);
291 if (hperh->init_cplt_cbk)
292 hperh->init_cplt_cbk(hperh);
293 }
294 }
301 #endif /* ALD_TRNG */
302
IS_TRNG_IT
#define IS_TRNG_IT(x)
Definition: ald_trng.h:151
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
trng_init_t::adjc
uint8_t adjc
Definition: ald_trng.h:66
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
IS_TRNG_SEED_TYPE
#define IS_TRNG_SEED_TYPE(x)
Definition: ald_trng.h:144
IS_TRNG_DATA_WIDTH
#define IS_TRNG_DATA_WIDTH(x)
Definition: ald_trng.h:140
SET
Definition: type.h:39
ald_trng_get_result
uint32_t ald_trng_get_result(trng_handle_t *hperh)
Get the result.
Definition: ald_trng.c:137
type_func_t
type_func_t
Definition: type.h:47
IS_TRNG_ADJC
#define IS_TRNG_ADJC(x)
Definition: ald_trng.h:157
trng_handle_s
TRNG Handle Structure definition.
Definition: ald_trng.h:110
ald_trng_get_status
flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status)
Get the status of SR register.
Definition: ald_trng.c:179
TRNG_STATE_ERROR
Definition: ald_trng.h:77
TRNG_STATE_READY
Definition: ald_trng.h:75
IS_TRNG_STATUS
#define IS_TRNG_STATUS(x)
Definition: ald_trng.h:148
ald_trng_get_flag_status
flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag)
Get the status of interrupt flag.
Definition: ald_trng.c:219
RESET
Definition: type.h:38
TRNG_IF_START
Definition: ald_trng.h:102
TRNG_IF_DAVLD
Definition: ald_trng.h:103
TRNG_STATE_RESET
Definition: ald_trng.h:74
TRNG_STATE_BUSY
Definition: ald_trng.h:76
trng_it_t
trng_it_t
Interrupt type.
Definition: ald_trng.h:92
ald_trng_interrupt_config
void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t state)
Enable/disable the specified interrupts.
Definition: ald_trng.c:156
it_status_t
enum flag_status_t it_status_t
ald_trng.h
Header file of TRNG module driver.
trng_handle_s::err_cplt_cbk
void(* err_cplt_cbk)(struct trng_handle_s *arg)
Definition: ald_trng.h:118
trng_init_t::posten
type_func_t posten
Definition: ald_trng.h:67
IS_TRNG_T_START
#define IS_TRNG_T_START(x)
Definition: ald_trng.h:158
trng_handle_s::trng_cplt_cbk
void(* trng_cplt_cbk)(struct trng_handle_s *arg)
Definition: ald_trng.h:117
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
trng_status_t
trng_status_t
State type.
Definition: ald_trng.h:83
ald_trng_init
ald_status_t ald_trng_init(trng_handle_t *hperh)
Initializes the TRNG according to the specified parameters in the trng_init_t.
Definition: ald_trng.c:69
IS_TRNG_FLAG
#define IS_TRNG_FLAG(x)
Definition: ald_trng.h:154
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
trng_handle_s::data
uint32_t data
Definition: ald_trng.h:113
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
trng_reset
void trng_reset(trng_handle_t *hperh)
Reset the TRNG peripheral.
Definition: ald_trng.c:251
ald_trng_clear_flag_status
void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag)
Clear the interrupt flag.
Definition: ald_trng.c:237
flag_status_t
flag_status_t
Definition: type.h:37
trng_handle_s::perh
TRNG_TypeDef * perh
Definition: ald_trng.h:111
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
trng_init_t::data_width
trng_data_width_t data_width
Definition: ald_trng.h:62
trng_handle_s::init
trng_init_t init
Definition: ald_trng.h:112
trng_handle_s::init_cplt_cbk
void(* init_cplt_cbk)(struct trng_handle_s *arg)
Definition: ald_trng.h:119
trng_handle_s::state
trng_state_t state
Definition: ald_trng.h:115
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
trng_flag_t
trng_flag_t
Interrupt flag type.
Definition: ald_trng.h:101
trng_init_t::seed
uint32_t seed
Definition: ald_trng.h:64
ald_trng_irq_handler
void ald_trng_irq_handler(trng_handle_t *hperh)
This function handles TRNG interrupt request.
Definition: ald_trng.c:270
__LOCK
#define __LOCK(x)
Definition: utils.h:92
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
ERROR
Definition: utils.h:56
trng_init_t::seed_type
trng_seed_type_t seed_type
Definition: ald_trng.h:63
TRNG_IF_SERR
Definition: ald_trng.h:104
trng_init_t::t_start
uint16_t t_start
Definition: ald_trng.h:65
ald_trng_get_it_status
it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it)
Get the status of interrupt source.
Definition: ald_trng.c:199


ALD User Manual: D:/svn/src/ald_trng.h Source File

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  • svn
  • src
ald_trng.h
Go to the documentation of this file.
1
17 #ifndef __ALD_TRNG_H__
18 #define __ALD_TRNG_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25
26
41 typedef enum {
42 TRNG_DSEL_1B = 0x0U,
43 TRNG_DSEL_8B = 0x1U,
44 TRNG_DSEL_16B = 0x2U,
45 TRNG_DSEL_32B = 0x3U,
46 } trng_data_width_t;
47
51 typedef enum {
52 TRNG_SEED_TYPE_0 = 0x0U,
53 TRNG_SEED_TYPE_1 = 0x1U,
54 TRNG_SEED_TYPE_LAST = 0x2U,
55 TRNG_SEED_TYPE_SEED = 0x3U,
56 } trng_seed_type_t;
57
61 typedef struct {
62 trng_data_width_t data_width;
63 trng_seed_type_t seed_type;
64 uint32_t seed;
65 uint16_t t_start;
66 uint8_t adjc;
67 type_func_t posten;
68 } trng_init_t;
69
73 typedef enum {
74 TRNG_STATE_RESET = 0x0U,
75 TRNG_STATE_READY = 0x1U,
76 TRNG_STATE_BUSY = 0x2U,
77 TRNG_STATE_ERROR = 0x4U,
78 } trng_state_t;
79
83 typedef enum {
84 TRNG_STATUS_START = (1U << 0),
85 TRNG_STATUS_DAVLD = (1U << 1),
86 TRNG_STATUS_SERR = (1U << 2),
87 } trng_status_t;
88
92 typedef enum {
93 TRNG_IT_START = (1U << 0),
94 TRNG_IT_DAVLD = (1U << 1),
95 TRNG_IT_SERR = (1U << 2),
96 } trng_it_t;
97
101 typedef enum {
102 TRNG_IF_START = (1U << 0),
103 TRNG_IF_DAVLD = (1U << 1),
104 TRNG_IF_SERR = (1U << 2),
105 } trng_flag_t;
106
110 typedef struct trng_handle_s {
111 TRNG_TypeDef *perh;
112 trng_init_t init;
113 uint32_t data;
114 lock_state_t lock;
115 trng_state_t state;
117 void (*trng_cplt_cbk)(struct trng_handle_s *arg);
118 void (*err_cplt_cbk)(struct trng_handle_s *arg);
119 void (*init_cplt_cbk)(struct trng_handle_s *arg);
120 } trng_handle_t;
128 #define TRNG_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))
129 #define TRNG_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_TRNGEN_MSK))
130 #define TRNG_ADJM_ENABLE() (SET_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))
131 #define TRNG_ADJM_DISABLE() (CLEAR_BIT(TRNG->CR, TRNG_CR_ADJM_MSK))
132
140 #define IS_TRNG_DATA_WIDTH(x) (((x) == TRNG_DSEL_1B) || \
141 ((x) == TRNG_DSEL_8B) || \
142 ((x) == TRNG_DSEL_16B) || \
143 ((x) == TRNG_DSEL_32B))
144 #define IS_TRNG_SEED_TYPE(x) (((x) == TRNG_SEED_TYPE_0) || \
145 ((x) == TRNG_SEED_TYPE_1) || \
146 ((x) == TRNG_SEED_TYPE_LAST) || \
147 ((x) == TRNG_SEED_TYPE_SEED))
148 #define IS_TRNG_STATUS(x) (((x) == TRNG_STATUS_START) || \
149 ((x) == TRNG_STATUS_DAVLD) || \
150 ((x) == TRNG_STATUS_SERR))
151 #define IS_TRNG_IT(x) (((x) == TRNG_IT_START) || \
152 ((x) == TRNG_IT_DAVLD) || \
153 ((x) == TRNG_IT_SERR))
154 #define IS_TRNG_FLAG(x) (((x) == TRNG_IF_START) || \
155 ((x) == TRNG_IF_DAVLD) || \
156 ((x) == TRNG_IF_SERR))
157 #define IS_TRNG_ADJC(x) ((x) < 4)
158 #define IS_TRNG_T_START(x) ((x) < 8)
159
169 /* Initialization functions */
170 extern ald_status_t ald_trng_init(trng_handle_t *hperh);
177 /* Control functions */
178 extern uint32_t ald_trng_get_result(trng_handle_t *hperh);
179 extern void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t state);
180 extern flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status);
181 extern it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it);
182 extern flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag);
183 extern void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag);
184 extern void ald_trng_irq_handler(trng_handle_t *hperh);
197 #ifdef __cplusplus
198 }
199 #endif
200
201 #endif /* __ALD_TRNG_H__ */
TRNG_SEED_TYPE_SEED
Definition: ald_trng.h:55
trng_seed_type_t
trng_seed_type_t
seed type
Definition: ald_trng.h:51
trng_init_t::adjc
uint8_t adjc
Definition: ald_trng.h:66
ald_trng_get_result
uint32_t ald_trng_get_result(trng_handle_t *hperh)
Get the result.
Definition: ald_trng.c:137
type_func_t
type_func_t
Definition: type.h:47
trng_handle_s
TRNG Handle Structure definition.
Definition: ald_trng.h:110
TRNG_SEED_TYPE_0
Definition: ald_trng.h:52
ald_trng_get_status
flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status)
Get the status of SR register.
Definition: ald_trng.c:179
TRNG_STATE_ERROR
Definition: ald_trng.h:77
TRNG_SEED_TYPE_1
Definition: ald_trng.h:53
TRNG_STATE_READY
Definition: ald_trng.h:75
ald_trng_get_flag_status
flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag)
Get the status of interrupt flag.
Definition: ald_trng.c:219
TRNG_DSEL_8B
Definition: ald_trng.h:43
TRNG_STATUS_START
Definition: ald_trng.h:84
TRNG_IF_START
Definition: ald_trng.h:102
TRNG_IF_DAVLD
Definition: ald_trng.h:103
TRNG_STATUS_SERR
Definition: ald_trng.h:86
utils.h
This file contains the Utilities functions/types for the driver.
TRNG_STATE_RESET
Definition: ald_trng.h:74
TRNG_STATE_BUSY
Definition: ald_trng.h:76
trng_it_t
trng_it_t
Interrupt type.
Definition: ald_trng.h:92
ald_trng_interrupt_config
void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t state)
Enable/disable the specified interrupts.
Definition: ald_trng.c:156
it_status_t
enum flag_status_t it_status_t
trng_handle_s::err_cplt_cbk
void(* err_cplt_cbk)(struct trng_handle_s *arg)
Definition: ald_trng.h:118
trng_handle_s::lock
lock_state_t lock
Definition: ald_trng.h:114
TRNG_DSEL_32B
Definition: ald_trng.h:45
trng_init_t::posten
type_func_t posten
Definition: ald_trng.h:67
TRNG_DSEL_16B
Definition: ald_trng.h:44
TRNG_IT_START
Definition: ald_trng.h:93
trng_handle_t
struct trng_handle_s trng_handle_t
TRNG Handle Structure definition.
lock_state_t
lock_state_t
Definition: type.h:58
trng_handle_s::trng_cplt_cbk
void(* trng_cplt_cbk)(struct trng_handle_s *arg)
Definition: ald_trng.h:117
trng_data_width_t
trng_data_width_t
Data width.
Definition: ald_trng.h:41
TRNG_DSEL_1B
Definition: ald_trng.h:42
trng_status_t
trng_status_t
State type.
Definition: ald_trng.h:83
TRNG_IT_DAVLD
Definition: ald_trng.h:94
trng_state_t
trng_state_t
TRNG state structures definition.
Definition: ald_trng.h:73
ald_trng_init
ald_status_t ald_trng_init(trng_handle_t *hperh)
Initializes the TRNG according to the specified parameters in the trng_init_t.
Definition: ald_trng.c:69
trng_handle_s::data
uint32_t data
Definition: ald_trng.h:113
TRNG_SEED_TYPE_LAST
Definition: ald_trng.h:54
ald_trng_clear_flag_status
void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag)
Clear the interrupt flag.
Definition: ald_trng.c:237
flag_status_t
flag_status_t
Definition: type.h:37
trng_handle_s::perh
TRNG_TypeDef * perh
Definition: ald_trng.h:111
trng_init_t::data_width
trng_data_width_t data_width
Definition: ald_trng.h:62
TRNG_STATUS_DAVLD
Definition: ald_trng.h:85
trng_handle_s::init
trng_init_t init
Definition: ald_trng.h:112
trng_handle_s::init_cplt_cbk
void(* init_cplt_cbk)(struct trng_handle_s *arg)
Definition: ald_trng.h:119
trng_handle_s::state
trng_state_t state
Definition: ald_trng.h:115
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
trng_flag_t
trng_flag_t
Interrupt flag type.
Definition: ald_trng.h:101
trng_init_t::seed
uint32_t seed
Definition: ald_trng.h:64
ald_trng_irq_handler
void ald_trng_irq_handler(trng_handle_t *hperh)
This function handles TRNG interrupt request.
Definition: ald_trng.c:270
trng_init_t::seed_type
trng_seed_type_t seed_type
Definition: ald_trng.h:63
TRNG_IT_SERR
Definition: ald_trng.h:95
TRNG_IF_SERR
Definition: ald_trng.h:104
trng_init_t::t_start
uint16_t t_start
Definition: ald_trng.h:65
trng_init_t
TRNG init structure definition.
Definition: ald_trng.h:61
ald_trng_get_it_status
it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it)
Get the status of interrupt source.
Definition: ald_trng.c:199


ALD User Manual: D:/svn/src/ald_tsense.c Source File

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  • svn
  • src
ald_tsense.c
Go to the documentation of this file.
1
17 #include "ald_tsense.h"
18 #include "ald_bkpc.h"
19
20
29 #ifdef ALD_TSENSE
30
31
35 tsense_cbk __tsense_cbk;
66 void ald_tsense_init(void)
67 {
68 uint16_t tempt, temptinv;
69 uint32_t tscic, tscicinv;
70
71 TSENSE_UNLOCK();
72 TSENSE->CR = 0;
73
74 SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK);
75 SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK);
76 MODIFY_REG(TSENSE->CR, TSENSE_CR_TSU_MSK, 0x4 << TSENSE_CR_TSU_POSS);
77 MODIFY_REG(TSENSE->CR, TSENSE_CR_TOM_MSK, 0x3 << TSENSE_CR_TOM_POSS);
78 MODIFY_REG(TSENSE->PSR, TSENSE_PSR_PRS_MSK, 0x1 << TSENSE_PSR_PRS_POSS);
79
80 TSENSE->HTGR = 0x1FD0C;
81 TSENSE->LTGR = 0x21BC1;
82 tempt = *(volatile uint16_t *)0x80348;
83 temptinv = *(volatile uint16_t *)0x8034A;
84 tscic = *(volatile uint32_t *)0x80350;
85 tscicinv = *(volatile uint32_t *)0x80358;
86
87 if ((tempt == (uint16_t)(~temptinv)) && (tscic == (~tscicinv))) {
88 TSENSE->TBDR = tempt;
89 TSENSE->TCALBDR = (tscic & 0x1FFFFFF) >> 6;
90 }
91 else {
92 TSENSE->TBDR = 0x1E00;
93 TSENSE->TCALBDR = 0x1FE70;
94 }
95
96 TSENSE_LOCK();
97 return;
98 }
99
105 void ald_tsense_source_select(tsense_source_sel_t sel)
106 {
107 assert_param(IS_TSENSE_SOURCE_SEL(sel));
108
109 BKPC_UNLOCK();
110 MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TSENSECS_MSK, sel << BKPC_PCCR_TSENSECS_POSS);
111
112 if (sel == TSENSE_SOURCE_LOSC) {
113 SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);
114 }
115 else if (sel == TSENSE_SOURCE_LRC) {
116 SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);
117 }
118 else {
119 ; /* do nothing */
120 }
121
122 BKPC_LOCK();
123 return;
124 }
152 ald_status_t ald_tsense_get_value(uint16_t *tsense)
153 {
154 uint32_t tmp = 0;
155
156 TSENSE_UNLOCK();
157 SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
158 SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
159 TSENSE_LOCK();
160
161 while ((!(READ_BIT(TSENSE->IF, TSENSE_IF_TSENSE_MSK))) && (tmp++ < 1000000));
162
163 if (tmp >= 1000000) {
164 TSENSE_UNLOCK();
165 CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
166 TSENSE_LOCK();
167 return TIMEOUT;
168 }
169
170 TSENSE_UNLOCK();
171 SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
172 TSENSE_LOCK();
173
174 if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) {
175 TSENSE_UNLOCK();
176 CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
177 TSENSE_LOCK();
178 return ERROR;
179 }
180
181 *tsense = READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS);
182
183 TSENSE_UNLOCK();
184 CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
185 TSENSE_LOCK();
186
187 return OK;
188 }
189
195 void ald_tsense_get_value_by_it(tsense_cbk cbk)
196 {
197 __tsense_cbk = cbk;
198
199 TSENSE_UNLOCK();
200 SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
201 SET_BIT(TSENSE->IE, TSENSE_IE_TSENSE_MSK);
202 SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
203 TSENSE_LOCK();
204
205 return;
206 }
207
212 void ald_tsense_irq_handler(void)
213 {
214 TSENSE_UNLOCK();
215 SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
216 TSENSE_LOCK();
217
218 if (__tsense_cbk == NULL) {
219 TSENSE_UNLOCK();
220 CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
221 TSENSE_LOCK();
222 return;
223 }
224
225 if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) {
226 TSENSE_UNLOCK();
227 CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
228 TSENSE_LOCK();
229 __tsense_cbk(0, ERROR);
230
231 return;
232 }
233
234 __tsense_cbk(READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS), OK);
235
236 TSENSE_UNLOCK();
237 SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
238 CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
239 TSENSE_LOCK();
240
241 return;
242 }
249 #endif /* ALD_TSENSE */
250
OK
Definition: utils.h:55
tsense_source_sel_t
tsense_source_sel_t
Source select.
Definition: ald_tsense.h:138
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
tsense_cbk
void(* tsense_cbk)(uint16_t value, ald_status_t status)
Define callback function type.
Definition: ald_tsense.h:147
TSENSE_UNLOCK
#define TSENSE_UNLOCK()
Definition: ald_rtchw.h:120
ald_tsense_source_select
void ald_tsense_source_select(tsense_source_sel_t sel)
Configure the TSENSE source.
Definition: ald_tsense.c:105
ald_bkpc.h
Header file of BKPC module driver.
TSENSE_SOURCE_LRC
Definition: ald_tsense.h:140
ald_tsense.h
Header file of TSENSE module driver.
__tsense_cbk
tsense_cbk __tsense_cbk
Definition: ald_tsense.c:35
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
BKPC_LOCK
#define BKPC_LOCK()
Definition: ald_bkpc.h:38
TIMEOUT
Definition: utils.h:58
ald_tsense_get_value_by_it
void ald_tsense_get_value_by_it(tsense_cbk cbk)
Get the current temperature by interrupt.
Definition: ald_tsense.c:195
TSENSE_SOURCE_LOSC
Definition: ald_tsense.h:139
ald_tsense_irq_handler
void ald_tsense_irq_handler(void)
This function handles TSENSE interrupt request.
Definition: ald_tsense.c:212
TSENSE_LOCK
#define TSENSE_LOCK()
Definition: ald_rtchw.h:119
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
BKPC_UNLOCK
#define BKPC_UNLOCK()
Definition: ald_bkpc.h:39
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
ald_tsense_get_value
ald_status_t ald_tsense_get_value(uint16_t *tsense)
Get the current temperature.
Definition: ald_tsense.c:152
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
ERROR
Definition: utils.h:56
ald_tsense_init
void ald_tsense_init(void)
Initializes the TSENSE according to the specified.
Definition: ald_tsense.c:66
IS_TSENSE_SOURCE_SEL
#define IS_TSENSE_SOURCE_SEL(x)
Definition: ald_tsense.h:156


ALD User Manual: D:/svn/src/ald_tsense.h Source File

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  • svn
  • src
ald_tsense.h
Go to the documentation of this file.
1
17 #ifndef __ALD_TSENSE_H__
18 #define __ALD_TSENSE_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25
26
38 #define TSENSE_LOCK() (WRITE_REG(TSENSE->WPR, 0x0U))
39 #define TSENSE_UNLOCK() (WRITE_REG(TSENSE->WPR, 0xA55A9669U))
40 #define TSENSE_ENABLE() \
41 do { \
42 TSENSE_UNLOCK(); \
43 SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \
44 TSENSE_LOCK(); \
45 } while (0)
46 #define TSENSE_DISABLE() \
47 do { \
48 TSENSE_UNLOCK(); \
49 CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK); \
50 TSENSE_LOCK(); \
51 } while (0)
52 #define TSENSE_REQ_ENABLE() \
53 do { \
54 TSENSE_UNLOCK(); \
55 SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \
56 TSENSE_LOCK(); \
57 } while (0)
58 #define TSENSE_REQ_DISABLE() \
59 do { \
60 TSENSE_UNLOCK(); \
61 CLEAR_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK); \
62 TSENSE_LOCK(); \
63 } while (0)
64 #define TSENSE_CTN_ENABLE() \
65 do { \
66 TSENSE_UNLOCK(); \
67 SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \
68 TSENSE_LOCK(); \
69 } while (0)
70 #define TSENSE_CTN_DISABLE() \
71 do { \
72 TSENSE_UNLOCK(); \
73 CLEAR_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK); \
74 TSENSE_LOCK(); \
75 } while (0)
76 #define TSENSE_RESET() \
77 do { \
78 TSENSE_UNLOCK(); \
79 SET_BIT(TSENSE->CR, TSENSE_CR_RST_MSK); \
80 TSENSE_LOCK(); \
81 } while (0)
82 #define TSENSE_LTGR_WR(data) \
83 do { \
84 TSENSE_UNLOCK(); \
85 WRITE_REG(TSENSE->LTGR, (data)); \
86 TSENSE_LOCK(); \
87 } while (0)
88 #define TSENSE_HTGR_WR(data) \
89 do { \
90 TSENSE_UNLOCK(); \
91 WRITE_REG(TSENSE->HTGR, (data)); \
92 TSENSE_LOCK(); \
93 } while (0)
94 #define TSENSE_TBDR_WR(data) \
95 do { \
96 TSENSE_UNLOCK(); \
97 WRITE_REG(TSENSE->TBDR, (data)); \
98 TSENSE_LOCK(); \
99 } while (0)
100 #define TSENSE_TCALBDR_WR(data) \
101 do { \
102 TSENSE_UNLOCK(); \
103 WRITE_REG(TSENSE->TCALBDR, (data)); \
104 TSENSE_LOCK(); \
105 } while (0)
106
116 typedef enum {
117 TSENSE_UPDATE_CYCLE_3 = 0x3U,
118 TSENSE_UPDATE_CYCLE_4 = 0x4U,
119 TSENSE_UPDATE_CYCLE_5 = 0x5U,
120 TSENSE_UPDATE_CYCLE_6 = 0x6U,
121 TSENSE_UPDATE_CYCLE_7 = 0x7U,
122 } tsense_update_cycle_t;
123
127 typedef enum {
128 TSENSE_OUTPUT_MODE_200 = 0x0U,
129 TSENSE_OUTPUT_MODE_400 = 0x1U,
130 TSENSE_OUTPUT_MODE_800 = 0x2U,
131 TSENSE_OUTPUT_MODE_1600 = 0x3U,
132 TSENSE_OUTPUT_MODE_3200 = 0x4U,
133 } tsense_output_mode_t;
134
138 typedef enum {
139 TSENSE_SOURCE_LOSC = 0x0U,
140 TSENSE_SOURCE_LRC = 0x1U,
141 } tsense_source_sel_t;
142
143
147 typedef void (*tsense_cbk)(uint16_t value, ald_status_t status);
156 #define IS_TSENSE_SOURCE_SEL(x) (((x) == TSENSE_SOURCE_LOSC) || \
157 ((x) == TSENSE_SOURCE_LRC))
158
168 /* Initialization functions */
169 extern void ald_tsense_init(void);
170 extern void ald_tsense_source_select(tsense_source_sel_t sel);
177 /* Control functions */
178 extern ald_status_t ald_tsense_get_value(uint16_t *tsense);
179 extern void ald_tsense_get_value_by_it(tsense_cbk cbk);
180 extern void ald_tsense_irq_handler(void);
195 #ifdef __cplusplus
196 }
197 #endif
198
199 #endif /* __ALD_TSENSE_H__ */
TSENSE_UPDATE_CYCLE_3
Definition: ald_tsense.h:117
tsense_source_sel_t
tsense_source_sel_t
Source select.
Definition: ald_tsense.h:138
tsense_output_mode_t
tsense_output_mode_t
Temperature output mode.
Definition: ald_tsense.h:127
tsense_update_cycle_t
tsense_update_cycle_t
Temperature update time.
Definition: ald_tsense.h:116
TSENSE_OUTPUT_MODE_200
Definition: ald_tsense.h:128
tsense_cbk
void(* tsense_cbk)(uint16_t value, ald_status_t status)
Define callback function type.
Definition: ald_tsense.h:147
TSENSE_OUTPUT_MODE_3200
Definition: ald_tsense.h:132
TSENSE_OUTPUT_MODE_1600
Definition: ald_tsense.h:131
utils.h
This file contains the Utilities functions/types for the driver.
ald_tsense_source_select
void ald_tsense_source_select(tsense_source_sel_t sel)
Configure the TSENSE source.
Definition: ald_tsense.c:105
TSENSE_UPDATE_CYCLE_5
Definition: ald_tsense.h:119
TSENSE_SOURCE_LRC
Definition: ald_tsense.h:140
TSENSE_UPDATE_CYCLE_6
Definition: ald_tsense.h:120
TSENSE_UPDATE_CYCLE_4
Definition: ald_tsense.h:118
ald_tsense_get_value_by_it
void ald_tsense_get_value_by_it(tsense_cbk cbk)
Get the current temperature by interrupt.
Definition: ald_tsense.c:195
TSENSE_SOURCE_LOSC
Definition: ald_tsense.h:139
ald_tsense_irq_handler
void ald_tsense_irq_handler(void)
This function handles TSENSE interrupt request.
Definition: ald_tsense.c:212
TSENSE_OUTPUT_MODE_400
Definition: ald_tsense.h:129
ald_tsense_get_value
ald_status_t ald_tsense_get_value(uint16_t *tsense)
Get the current temperature.
Definition: ald_tsense.c:152
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
ald_tsense_init
void ald_tsense_init(void)
Initializes the TSENSE according to the specified.
Definition: ald_tsense.c:66
TSENSE_OUTPUT_MODE_800
Definition: ald_tsense.h:130
TSENSE_UPDATE_CYCLE_7
Definition: ald_tsense.h:121


ALD User Manual: D:/svn/src/ald_uart.c Source File

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  • svn
  • src
ald_uart.c
Go to the documentation of this file.
1
89 #include "ald_uart.h"
90 #include "ald_cmu.h"
91
92
101 #ifdef ALD_UART
102
107 #ifdef ALD_DMA
108
113 static void uart_dma_send_cplt(void *arg)
114 {
115 uart_handle_t *hperh = (uart_handle_t *)arg;
116 hperh->tx_count = hperh->tx_size;
117
118 ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, DISABLE);
119 hperh->tx_count = 0;
120 ald_uart_interrupt_config(hperh, UART_IT_TSEMPTY, ENABLE);
121 CLEAR_BIT(hperh->state, UART_STATE_TX_MASK);
122
123 return;
124 }
125
131 static void uart_dma_recv_cplt(void *arg)
132 {
133 uart_handle_t *hperh = (uart_handle_t *)arg;
134 hperh->tx_count = hperh->tx_size;
135
136 ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, DISABLE);
137 hperh->rx_count = 0;
138 CLEAR_BIT(hperh->state, UART_STATE_RX_MASK);
139
140 if (hperh->rx_cplt_cbk)
141 hperh->rx_cplt_cbk(hperh);
142
143 return;
144 }
145
151 static void uart_dma_error(void *arg)
152 {
153 uart_handle_t *hperh = (uart_handle_t *)arg;
154
155 hperh->rx_count = 0;
156 hperh->tx_count = 0;
157 hperh->state = UART_STATE_READY;
158 hperh->err_code |= UART_ERROR_DMA;
159 ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, DISABLE);
160 ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, DISABLE);
161
162 if (hperh->error_cbk)
163 hperh->error_cbk(hperh);
164
165 return;
166 }
167 #endif
168
177 static ald_status_t uart_wait_flag(uart_handle_t *hperh, uart_status_t flag, flag_status_t status, uint32_t timeout)
178 {
179 uint32_t tick;
180
181 if (timeout == 0)
182 return ERROR;
183
184 tick = ald_get_tick();
185
186 /* Waiting for flag */
187 while ((ald_uart_get_status(hperh, flag)) != status) {
188 if (((ald_get_tick()) - tick) > timeout)
189 return TIMEOUT;
190 }
191
192 return OK;
193 }
194
200 static ald_status_t __uart_send_by_it(uart_handle_t *hperh)
201 {
202 if ((hperh->state & UART_STATE_TX_MASK) == 0x0)
203 return BUSY;
204
205 hperh->perh->TXBUF = (uint8_t)(*hperh->tx_buf++ & 0x00FF);
206 hperh->tx_count++;
207
208 if (hperh->tx_count >= hperh->tx_size) {
209 ald_uart_interrupt_config(hperh, UART_IT_TFTH, DISABLE);
210 ald_uart_interrupt_config(hperh, UART_IT_TSEMPTY, ENABLE);
211 }
212
213 return OK;
214 }
215
221 static ald_status_t __uart_end_send_by_it(uart_handle_t *hperh)
222 {
223 uint32_t cnt = 0xFFFFFF;
224
225 ald_uart_interrupt_config(hperh, UART_IT_TSEMPTY, DISABLE);
226 CLEAR_BIT(hperh->state, UART_STATE_TX_MASK);
227
228 while ((hperh->perh->STAT & UART_STATUS_TSBUSY) && (cnt--));
229
230 if (hperh->tx_cplt_cbk)
231 hperh->tx_cplt_cbk(hperh);
232
233 return OK;
234 }
235
241 static ald_status_t __uart_recv_by_it(uart_handle_t *hperh)
242 {
243 if ((hperh->state & UART_STATE_RX_MASK) == 0x0)
244 return BUSY;
245
246 while (READ_BITS(hperh->perh->FCON, UART_FCON_RXFL_MSK, UART_FCON_RXFL_POSS)) {
247 *hperh->rx_buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF);
248 hperh->rx_count++;
249
250 if (hperh->rx_count >= hperh->rx_size)
251 break;
252 }
253
254 if (hperh->rx_count >= hperh->rx_size) {
255 ald_uart_interrupt_config(hperh, UART_IT_RFTH, DISABLE);
256 CLEAR_BIT(hperh->state, UART_STATE_RX_MASK);
257
258 if (hperh->rx_cplt_cbk)
259 hperh->rx_cplt_cbk(hperh);
260 }
261
262 return OK;
263 }
303 void ald_uart_reset(uart_handle_t *hperh)
304 {
305 assert_param(IS_UART_ALL(hperh->perh));
306
307
308 WRITE_REG(hperh->perh->BRR, 0x0);
309 WRITE_REG(hperh->perh->LCON, 0x0);
310 WRITE_REG(hperh->perh->MCON, 0x0);
311 WRITE_REG(hperh->perh->RS485, 0x0);
312 WRITE_REG(hperh->perh->SCARD, 0x0);
313 WRITE_REG(hperh->perh->LIN, 0x0);
314 WRITE_REG(hperh->perh->RTOR, 0x0);
315 WRITE_REG(hperh->perh->FCON, 0x0);
316 WRITE_REG(hperh->perh->IDR, 0xFFF);
317 hperh->err_code = UART_ERROR_NONE;
318 hperh->state = UART_STATE_RESET;
319
320 __UNLOCK(hperh);
321 return;
322 }
323
331 void ald_uart_init(uart_handle_t *hperh)
332 {
333 assert_param(IS_UART_ALL(hperh->perh));
334 assert_param(IS_UART_BAUDRATE(hperh->init.baud));
335 assert_param(IS_UART_WORD_LENGTH(hperh->init.word_length));
336 assert_param(IS_UART_STOPBITS(hperh->init.stop_bits));
337 assert_param(IS_UART_PARITY(hperh->init.parity));
338 assert_param(IS_UART_MODE(hperh->init.mode));
339 assert_param(IS_UART_HARDWARE_FLOW_CONTROL(hperh->init.fctl));
340
341 ald_uart_reset(hperh);
342
343 MODIFY_REG(hperh->perh->LCON, UART_LCON_DLS_MSK, hperh->init.word_length << UART_LCON_DLS_POSS);
344 MODIFY_REG(hperh->perh->LCON, UART_LCON_STOP_MSK, hperh->init.stop_bits << UART_LCON_STOP_POS);
345
346 if ((hperh->init.parity) != UART_PARITY_NONE) {
347 SET_BIT(hperh->perh->LCON, UART_LCON_PE_MSK);
348
349 if ((hperh->init.parity) == UART_PARITY_ODD)
350 CLEAR_BIT(hperh->perh->LCON, UART_LCON_PS_MSK);
351
352 if ((hperh->init.parity) == UART_PARITY_EVEN)
353 SET_BIT(hperh->perh->LCON, UART_LCON_PS_MSK);
354 }
355
356 MODIFY_REG(hperh->perh->MCON, UART_MCON_AFCEN_MSK, hperh->init.fctl << UART_MCON_AFCEN_POS);
357 hperh->perh->BRR = (ald_cmu_get_pclk1_clock() + (hperh->init.baud >> 1)) / hperh->init.baud;
358
359 if (hperh->init.mode == UART_MODE_LIN)
360 SET_BIT(hperh->perh->LIN, UART_LIN_LINEN_MSK);
361 else if (hperh->init.mode == UART_MODE_IrDA)
362 SET_BIT(hperh->perh->MCON, UART_MCON_IREN_MSK);
363 else if (hperh->init.mode == UART_MODE_RS485)
364 SET_BIT(hperh->perh->RS485, UART_RS485_AADEN_MSK);
365 else if (hperh->init.mode == UART_MODE_HDSEL)
366 SET_BIT(hperh->perh->MCON, UART_MCON_HDEN_MSK);
367 else if (hperh->init.mode == UART_MODE_SCARD)
368 SET_BIT(hperh->perh->SCARD, UART_SCARD_SCEN_MSK);
369 else
370 ; /* do nothing */
371
372 SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK);
373 SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK);
374 CLEAR_BIT(hperh->perh->FCON, UART_FCON_TXTH_MSK);
375 CLEAR_BIT(hperh->perh->FCON, UART_FCON_RXTH_MSK);
376 SET_BIT(hperh->perh->LCON, UART_LCON_RXEN_MSK);
377 SET_BIT(hperh->perh->LCON, UART_LCON_TXEN_MSK);
378
379 hperh->state = UART_STATE_READY;
380 hperh->err_code = UART_ERROR_NONE;
381 return;
382 }
383
392 void ald_uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config)
393 {
394 assert_param(IS_UART_ALL(hperh->perh));
395 assert_param(IS_FUNC_STATE(config->normal));
396 assert_param(IS_FUNC_STATE(config->dir));
397 assert_param(IS_FUNC_STATE(config->invert));
398
399 MODIFY_REG(hperh->perh->RS485, UART_RS485_AADNEN_MSK, config->normal << UART_RS485_AADNEN_POS);
400 MODIFY_REG(hperh->perh->RS485, UART_RS485_AADACEN_MSK, config->dir << UART_RS485_AADACEN_POS);
401 MODIFY_REG(hperh->perh->RS485, UART_RS485_AADINV_MSK, config->invert << UART_RS485_AADINV_POS);
402 MODIFY_REG(hperh->perh->RS485, UART_RS485_ADDR_MSK, config->addr << UART_RS485_ADDR_POSS);
403
404 return;
405 }
406
415 void ald_uart_scard_config(uart_handle_t *hperh, uart_scard_config_t *config)
416 {
417 assert_param(IS_UART_SCARD(hperh->perh));
418 assert_param(IS_UART_SCARD_CLK(config->clk_div));
419
420 MODIFY_REG(hperh->perh->SCARD, UART_SCARD_BLEN_MSK, config->block_len << UART_SCARD_BLEN_POSS);
421 MODIFY_REG(hperh->perh->SCARD, UART_SCARD_GT_MSK, config->pt << UART_SCARD_GT_POSS);
422 MODIFY_REG(hperh->perh->SCARD, UART_SCARD_SCCNT_MSK, config->retry << UART_SCARD_SCCNT_POSS);
423 MODIFY_REG(hperh->perh->SCARD, UART_SCARD_PSC_MSK, config->clk_div << UART_SCARD_PSC_POSS);
424 MODIFY_REG(hperh->perh->SCARD, UART_SCARD_SCLKEN_MSK, config->clk_out << UART_SCARD_SCLKEN_POS);
425
426 return;
427 }
488 ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
489 {
490 assert_param(IS_UART_ALL(hperh->perh));
491
492 if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX))
493 return BUSY;
494
495 if ((buf == NULL) || (size == 0))
496 return ERROR;
497
498 __LOCK(hperh);
499 hperh->err_code = UART_ERROR_NONE;
500 SET_BIT(hperh->state, UART_STATE_TX_MASK);
501
502 hperh->tx_size = size;
503 hperh->tx_count = 0;
504 SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK);
505
506 while (size-- > 0) {
507 if (uart_wait_flag(hperh, UART_STATUS_TFTH, SET, timeout) != OK) {
508 __UNLOCK(hperh);
509 hperh->state = UART_STATE_READY;
510 return TIMEOUT;
511 }
512
513 hperh->perh->TXBUF = (*buf++ & 0xFF);
514 hperh->tx_count++;
515 }
516
517 if (uart_wait_flag(hperh, UART_STATUS_TSBUSY, RESET, timeout) != OK) {
518 __UNLOCK(hperh);
519 hperh->state = UART_STATE_READY;
520 return TIMEOUT;
521 }
522
523 CLEAR_BIT(hperh->state, UART_STATE_TX_MASK);
524 __UNLOCK(hperh);
525
526 return OK;
527 }
528
537 ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
538 {
539 assert_param(IS_UART_ALL(hperh->perh));
540
541 if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX))
542 return BUSY;
543
544 if ((buf == NULL) || (size == 0))
545 return ERROR;
546
547 __LOCK(hperh);
548 hperh->err_code = UART_ERROR_NONE;
549 SET_BIT(hperh->state, UART_STATE_RX_MASK);
550
551 hperh->rx_size = size;
552 hperh->rx_count = 0;
553 SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK);
554
555 while (size-- > 0) {
556 if (uart_wait_flag(hperh, UART_STATUS_RFTH, SET, timeout) != OK) {
557 __UNLOCK(hperh);
558 hperh->state = UART_STATE_READY;
559 return TIMEOUT;
560 }
561
562 *buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF);
563 hperh->rx_count++;
564 }
565
566 CLEAR_BIT(hperh->state, UART_STATE_RX_MASK);
567 __UNLOCK(hperh);
568
569 return OK;
570
571 }
572
582 ald_status_t ald_uart_send_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
583 {
584 assert_param(IS_UART_ALL(hperh->perh));
585
586 if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX))
587 return BUSY;
588 if ((buf == NULL) || (size == 0))
589 return ERROR;
590
591 hperh->err_code = UART_ERROR_NONE;
592 SET_BIT(hperh->state, UART_STATE_TX_MASK);
593
594 hperh->tx_size = size;
595 hperh->tx_count = 0;
596 SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK);
597
598 while (size-- > 0) {
599 if (uart_wait_flag(hperh, UART_STATUS_TFTH, SET, timeout) != OK) {
600 hperh->state = UART_STATE_READY;
601 return TIMEOUT;
602 }
603
604 hperh->perh->TXBUF = (*buf++ & 0xFF);
605 hperh->tx_count++;
606 }
607
608 if (uart_wait_flag(hperh, UART_STATUS_TSBUSY, RESET, timeout) != OK) {
609 hperh->state = UART_STATE_READY;
610 return TIMEOUT;
611 }
612
613 CLEAR_BIT(hperh->state, UART_STATE_TX_MASK);
614 return OK;
615 }
616
626 ald_status_t ald_uart_recv_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
627 {
628 assert_param(IS_UART_ALL(hperh->perh));
629
630 if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX))
631 return BUSY;
632 if ((buf == NULL) || (size == 0))
633 return ERROR;
634
635 hperh->err_code = UART_ERROR_NONE;
636 SET_BIT(hperh->state, UART_STATE_RX_MASK);
637
638 hperh->rx_size = size;
639 hperh->rx_count = 0;
640 SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK);
641
642 while (size-- > 0) {
643 if (uart_wait_flag(hperh, UART_STATUS_RFTH, SET, timeout) != OK) {
644 hperh->state = UART_STATE_READY;
645 return TIMEOUT;
646 }
647
648 *buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF);
649 hperh->rx_count++;
650 }
651
652 CLEAR_BIT(hperh->state, UART_STATE_RX_MASK);
653 return OK;
654
655 }
656
664 ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size)
665 {
666 assert_param(IS_UART_ALL(hperh->perh));
667
668 if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX))
669 return BUSY;
670
671 if ((buf == NULL ) || (size == 0))
672 return ERROR;
673
674 __LOCK(hperh);
675
676 hperh->tx_buf = buf;
677 hperh->tx_size = size;
678 hperh->tx_count = 0;
679 hperh->err_code = UART_ERROR_NONE;
680 SET_BIT(hperh->state, UART_STATE_TX_MASK);
681
682 __UNLOCK(hperh);
683 SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK);
684 SET_BIT(hperh->perh->ICR, UART_ICR_TFTH_MSK);
685 ald_uart_interrupt_config(hperh, UART_IT_TFTH, ENABLE);
686
687 return OK;
688 }
689
697 ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size)
698 {
699 assert_param(IS_UART_ALL(hperh->perh));
700
701 if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX))
702 return BUSY;
703
704 if ((buf == NULL ) || (size == 0))
705 return ERROR;
706
707 __LOCK(hperh);
708 hperh->rx_buf = buf;
709 hperh->rx_size = size;
710 hperh->rx_count = 0;
711 hperh->err_code = UART_ERROR_NONE;
712 SET_BIT(hperh->state, UART_STATE_RX_MASK);
713
714 __UNLOCK(hperh);
715 SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK);
716 SET_BIT(hperh->perh->ICR, UART_ICR_RFTH_MSK);
717 ald_uart_interrupt_config(hperh, UART_IT_RFTH, ENABLE);
718 return OK;
719 }
720
721
730 ald_status_t ald_uart_recv_frame_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t t_out)
731 {
732 assert_param(IS_UART_ALL(hperh->perh));
733
734 if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX))
735 return BUSY;
736
737 if ((buf == NULL ) || (t_out == 0) || (t_out > 0xFFFFFF) || (size == 0))
738 return ERROR;
739
740 __LOCK(hperh);
741 hperh->rx_buf = buf;
742 hperh->rx_size = size;
743 hperh->rx_count = 0;
744 hperh->err_code = UART_ERROR_NONE;
745 SET_BIT(hperh->state, UART_STATE_RX_MASK);
746
747 __UNLOCK(hperh);
748 SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK);
749 SET_BIT(hperh->perh->ICR, UART_ICR_RFTH_MSK);
750 SET_BIT(hperh->perh->RTOR, UART_RTOR_RTOEN_MSK);
751 MODIFY_REG(hperh->perh->RTOR, UART_RTOR_RTO_MSK, t_out << UART_RTOR_RTO_POSS);
752 ald_uart_interrupt_config(hperh, UART_IT_RFTH, ENABLE);
753 ald_uart_interrupt_config(hperh, UART_IT_RXTO, ENABLE);
754 return OK;
755 }
756
757 #ifdef ALD_DMA
758
766 ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
767 {
768 assert_param(IS_UART_ALL(hperh->perh));
769
770 if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX))
771 return BUSY;
772
773 if ((buf == NULL ) || (size == 0))
774 return ERROR;
775
776 __LOCK(hperh);
777
778 hperh->tx_buf = buf;
779 hperh->tx_size = size;
780 hperh->tx_count = 0;
781 hperh->err_code = UART_ERROR_NONE;
782 SET_BIT(hperh->state, UART_STATE_TX_MASK);
783
784 if (hperh->hdmatx.perh == NULL)
785 hperh->hdmatx.perh = DMA0;
786
787 /* Set the dma parameters */
788 hperh->hdmatx.cplt_cbk = uart_dma_send_cplt;
789 hperh->hdmatx.cplt_arg = (void *)hperh;
790 hperh->hdmatx.err_cbk = uart_dma_error;
791 hperh->hdmatx.err_arg = (void *)hperh;
792
793 ald_dma_config_struct(&hperh->hdmatx.config);
794 hperh->hdmatx.config.src = (void *)buf;
795 hperh->hdmatx.config.dst = (void *)&hperh->perh->TXBUF;
796 hperh->hdmatx.config.size = size;
797 hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE;
798 hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
799 if ((hperh->perh == UART4) || (hperh->perh == UART5)) {
800 hperh->hdmatx.config.msigsel = DMA_MSIGSEL_UART45_TXEMPTY;
801 } else {
802 hperh->hdmatx.config.msigsel = DMA_MSIGSEL_UART_TXEMPTY;
803 }
804 hperh->hdmatx.config.burst = ENABLE;
805 hperh->hdmatx.config.channel = channel;
806
807 if (hperh->init.mode == UART_MODE_RS485) {
808 hperh->hdmatx.config.src_inc = DMA_DATA_INC_HALFWORD;
809 hperh->hdmatx.config.data_width = DMA_DATA_SIZE_HALFWORD;
810 }
811
812 if (hperh->perh == UART0)
813 hperh->hdmatx.config.msel = DMA_MSEL_UART0;
814 else if (hperh->perh == UART1)
815 hperh->hdmatx.config.msel = DMA_MSEL_UART1;
816 else if (hperh->perh == UART2)
817 hperh->hdmatx.config.msel = DMA_MSEL_UART2;
818 else if (hperh->perh == UART3)
819 hperh->hdmatx.config.msel = DMA_MSEL_UART3;
820 else if (hperh->perh == UART4)
821 hperh->hdmatx.config.msel = DMA_MSEL_UART4;
822 else if (hperh->perh == UART5)
823 hperh->hdmatx.config.msel = DMA_MSEL_UART5;
824 else
825 ; /* do nothing */
826
827 ald_dma_config_basic(&hperh->hdmatx);
828
829 __UNLOCK(hperh);
830 SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK);
831 ald_uart_clear_flag_status(hperh, UART_IF_TBC);
832 ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, ENABLE);
833
834
835 return OK;
836 }
837
846 ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
847 {
848 assert_param(IS_UART_ALL(hperh->perh));
849
850 if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_TX))
851 return BUSY;
852
853 if ((buf == NULL) || (size == 0))
854 return ERROR;
855
856 __LOCK(hperh);
857
858 hperh->rx_buf = buf;
859 hperh->rx_size = size;
860 hperh->err_code = UART_ERROR_NONE;
861 SET_BIT(hperh->state, UART_STATE_RX_MASK);
862
863 if (hperh->hdmarx.perh == NULL)
864 hperh->hdmarx.perh = DMA0;
865
866 /* Set the dma parameters */
867 hperh->hdmarx.cplt_cbk = uart_dma_recv_cplt;
868 hperh->hdmarx.cplt_arg = (void *)hperh;
869 hperh->hdmarx.err_cbk = uart_dma_error;
870 hperh->hdmarx.err_arg = (void *)hperh;
871
872 ald_dma_config_struct(&hperh->hdmarx.config);
873 hperh->hdmarx.config.src = (void *)&hperh->perh->RXBUF;
874 hperh->hdmarx.config.dst = (void *)buf;
875 hperh->hdmarx.config.size = size;
876 hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE;
877 hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE;
878 if ((hperh->perh == UART4) || (hperh->perh == UART5)) {
879 hperh->hdmarx.config.msigsel = DMA_MSIGSEL_UART45_RNR;
880 } else {
881 hperh->hdmarx.config.msigsel = DMA_MSIGSEL_UART_RNR;
882 }
883
884 hperh->hdmatx.config.burst = ENABLE;
885 hperh->hdmarx.config.channel = channel;
886
887 if (hperh->init.mode == UART_MODE_RS485) {
888 hperh->hdmarx.config.dst_inc = DMA_DATA_INC_HALFWORD;
889 hperh->hdmarx.config.data_width = DMA_DATA_SIZE_HALFWORD;
890 }
891
892 if (hperh->perh == UART0)
893 hperh->hdmarx.config.msel = DMA_MSEL_UART0;
894 else if (hperh->perh == UART1)
895 hperh->hdmarx.config.msel = DMA_MSEL_UART1;
896 else if (hperh->perh == UART2)
897 hperh->hdmarx.config.msel = DMA_MSEL_UART2;
898 else if (hperh->perh == UART3)
899 hperh->hdmarx.config.msel = DMA_MSEL_UART3;
900 else if (hperh->perh == UART4)
901 hperh->hdmatx.config.msel = DMA_MSEL_UART4;
902 else if (hperh->perh == UART5)
903 hperh->hdmatx.config.msel = DMA_MSEL_UART5;
904 else
905 ;
906
907 __UNLOCK(hperh);
908 ald_dma_config_basic(&hperh->hdmarx);
909 SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK);
910 ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, ENABLE);
911
912 return OK;
913 }
914
920 ald_status_t ald_uart_dma_pause(uart_handle_t *hperh)
921 {
922 assert_param(IS_UART_ALL(hperh->perh));
923
924 ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, DISABLE);
925 ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, DISABLE);
926 return OK;
927 }
928
934 ald_status_t ald_uart_dma_resume(uart_handle_t *hperh)
935 {
936 assert_param(IS_UART_ALL(hperh->perh));
937
938 ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, ENABLE);
939 ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, ENABLE);
940 return OK;
941 }
942
948 ald_status_t ald_uart_dma_stop(uart_handle_t *hperh)
949 {
950 assert_param(IS_UART_ALL(hperh->perh));
951
952 ald_uart_dma_req_config(hperh, UART_DMA_REQ_TX, DISABLE);
953 ald_uart_dma_req_config(hperh, UART_DMA_REQ_RX, DISABLE);
954 hperh->state = UART_STATE_READY;
955 return OK;
956 }
957 #endif
958
964 void ald_uart_irq_handler(uart_handle_t *hperh)
965 {
966 assert_param(IS_UART_ALL(hperh->perh));
967
968 /* Handle parity error */
969 if (((ald_uart_get_status(hperh, UART_STATUS_PERR)) != RESET) && \
970 (ald_uart_get_state(hperh)) == UART_STATE_RX_MASK)
971 hperh->err_code |= UART_ERROR_PE;
972
973 /* Handle frame error */
974 if (((ald_uart_get_status(hperh, UART_STATUS_FERR)) != RESET) && \
975 (ald_uart_get_state(hperh)) == UART_STATE_RX_MASK)
976 hperh->err_code |= UART_ERROR_FE;
977
978 /* Handle rx overflow error */
979 if (((ald_uart_get_status(hperh, UART_STATUS_RFOERR)) != RESET) && \
980 (ald_uart_get_state(hperh)) == UART_STATE_RX_MASK)
981 hperh->err_code |= UART_ERROR_ORE;
982
983 /* Handle tx overflow error */
984 if (((ald_uart_get_status(hperh, UART_STATUS_TFOERR)) != RESET) && \
985 (ald_uart_get_state(hperh)) == UART_STATE_TX_MASK)
986 hperh->err_code |= UART_ERROR_ORE;
987
988 /* Receive */
989 if ((ald_uart_get_mask_flag_status(hperh, UART_IF_RFTH)) != RESET) {
990 ald_uart_clear_flag_status(hperh, UART_IF_RFTH);
991 __uart_recv_by_it(hperh);
992 }
993
994 /* Transmit */
995 if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TFTH)) != RESET) {
996 ald_uart_clear_flag_status(hperh, UART_IF_TFTH);
997 __uart_send_by_it(hperh);
998 }
999
1000 /* End Transmit */
1001 if ((ald_uart_get_mask_flag_status(hperh, UART_IF_TFEMPTY)) != RESET) {
1002 ald_uart_clear_flag_status(hperh, UART_IF_TFEMPTY);
1003 __uart_end_send_by_it(hperh);
1004 }
1005
1006 /* Receive frame timeout*/
1007 if ((ald_uart_get_mask_flag_status(hperh, UART_IF_RXTO)) != RESET) {
1008 ald_uart_clear_flag_status(hperh, UART_IF_RXTO);
1009
1010 ald_uart_interrupt_config(hperh, UART_IT_RXTO, DISABLE);
1011 CLEAR_BIT(hperh->state, UART_STATE_RX_MASK);
1012
1013 if (hperh->rx_cplt_cbk)
1014 hperh->rx_cplt_cbk(hperh);
1015 }
1016
1017 /* Handle error state */
1018 if (hperh->err_code != UART_ERROR_NONE) {
1019 hperh->state = UART_STATE_READY;
1020
1021 if (hperh->error_cbk)
1022 hperh->error_cbk(hperh);
1023 }
1024 }
1025
1031 void ald_uart_irq_handler_fast(uart_handle_t *hperh)
1032 {
1033 volatile uint32_t tmp = hperh->perh->IFM;
1034
1035 /* Transmit */
1036 if (tmp & 0x8000) {
1037 hperh->perh->ICR = 0x8000;
1038 hperh->perh->TXBUF = *hperh->tx_buf++;
1039 ++hperh->tx_count;
1040
1041 if (hperh->tx_count >= hperh->tx_size) {
1042 hperh->perh->IDR = 0x8000;
1043 CLEAR_BIT(hperh->state, UART_STATE_TX_MASK);
1044
1045 if (hperh->tx_cplt_cbk)
1046 hperh->tx_cplt_cbk(hperh);
1047 }
1048 }
1049 /* End Transmit */
1050 if (tmp & 0x10000) {
1051 hperh->perh->ICR = 0x10000;
1052 hperh->perh->IDR = 0x10000;
1053 CLEAR_BIT(hperh->state, UART_STATE_TX_MASK);
1054
1055 if (hperh->tx_cplt_cbk)
1056 hperh->tx_cplt_cbk(hperh);
1057 }
1058
1059 /* Receive*/
1060 if (tmp & 0x200) {
1061 hperh->perh->ICR = 0x200;
1062 *hperh->rx_buf++ = (uint8_t)(hperh->perh->RXBUF & 0xFF);
1063 ++hperh->rx_count;
1064
1065 if (hperh->rx_count >= hperh->rx_size) {
1066 hperh->perh->IDR = 0x200;
1067 CLEAR_BIT(hperh->state, UART_STATE_RX_MASK);
1068
1069 if (hperh->rx_cplt_cbk)
1070 hperh->rx_cplt_cbk(hperh);
1071 }
1072 }
1073 /* Receive frame */
1074 if (tmp & 0x10) {
1075 hperh->perh->ICR = 0x10;
1076 hperh->perh->IDR = 0x10;
1077 CLEAR_BIT(hperh->state, UART_STATE_RX_MASK);
1078
1079 if (hperh->rx_cplt_cbk)
1080 hperh->rx_cplt_cbk(hperh);
1081 }
1082
1083 return;
1084 }
1126 void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state)
1127 {
1128 assert_param(IS_UART_ALL(hperh->perh));
1129 assert_param(IS_UART_IT(it));
1130 assert_param(IS_FUNC_STATE(state));
1131
1132 if (state == ENABLE)
1133 hperh->perh->IER = it;
1134 else
1135 hperh->perh->IDR = it;
1136
1137 return;
1138 }
1139
1150 void ald_uart_dma_req_config(uart_handle_t *hperh, uart_dma_req_t req, type_func_t state)
1151 {
1152 assert_param(IS_UART_ALL(hperh->perh));
1153 assert_param(IS_UART_DMA_REQ(req));
1154 assert_param(IS_FUNC_STATE(state));
1155
1156 if (req == UART_DMA_REQ_TX) {
1157 if (state == ENABLE)
1158 SET_BIT(hperh->perh->MCON, UART_MCON_TXDMAEN_MSK);
1159 else
1160 CLEAR_BIT(hperh->perh->MCON, UART_MCON_TXDMAEN_MSK);
1161 }
1162 else {
1163 if (state == ENABLE)
1164 SET_BIT(hperh->perh->MCON, UART_MCON_RXDMAEN_MSK);
1165 else
1166 CLEAR_BIT(hperh->perh->MCON, UART_MCON_RXDMAEN_MSK);
1167 }
1168
1169 return;
1170 }
1171
1178 void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config)
1179 {
1180 assert_param(IS_UART_ALL(hperh->perh));
1181 assert_param(IS_UART_TXFIFO_TYPE(config));
1182
1183 SET_BIT(hperh->perh->FCON, UART_FCON_TFRST_MSK);
1184 MODIFY_REG(hperh->perh->FCON, UART_FCON_TXTH_MSK, config << UART_FCON_TXTH_POSS);
1185
1186 return;
1187 }
1188
1195 void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config)
1196 {
1197 assert_param(IS_UART_ALL(hperh->perh));
1198 assert_param(IS_UART_RXFIFO_TYPE(config));
1199
1200 SET_BIT(hperh->perh->FCON, UART_FCON_RFRST_MSK);
1201 MODIFY_REG(hperh->perh->FCON, UART_FCON_RXTH_MSK, config << UART_FCON_RXTH_POSS);
1202
1203 return;
1204 }
1205
1212 void uart_lin_break_detect_irq(uart_handle_t *hperh, type_func_t status)
1213 {
1214 assert_param(IS_UART_ALL(hperh->perh));
1215
1216 if (status == ENABLE) {
1217 SET_BIT(hperh->perh->IER, UART_IER_LINBK_MSK);
1218 }
1219 else {
1220 CLEAR_BIT(hperh->perh->IER, UART_IER_LINBK_MSK);
1221 }
1222
1223 return;
1224 }
1225
1231 void ald_uart_lin_send_break(uart_handle_t *hperh)
1232 {
1233 assert_param(IS_UART_ALL(hperh->perh));
1234
1235 SET_BIT(hperh->perh->LIN, UART_LIN_LINBKREQ_MSK);
1236
1237 hperh->perh->TXBUF = (0x55);
1238
1239 return;
1240 }
1241
1250 void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len)
1251 {
1252 assert_param(IS_UART_ALL(hperh->perh));
1253 assert_param(IS_UART_LIN_BREAK_LEN(len));
1254
1255 MODIFY_REG(hperh->perh->LIN, UART_LIN_LINBDL_MSK, len << UART_LIN_LINBDL_POS);
1256
1257 return;
1258 }
1259
1269 void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode)
1270 {
1271 assert_param(IS_UART_ALL(hperh->perh));
1272 assert_param(IS_UART_AUTO_BAUD_MODE(mode));
1273
1274 MODIFY_REG(hperh->perh->MCON, UART_MCON_ABRMOD_MSK, mode << UART_MCON_ABRMOD_POSS);
1275
1276 return;
1277 }
1278
1287 ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout)
1288 {
1289 assert_param(IS_UART_ALL(hperh->perh));
1290
1291 if ((hperh->state != UART_STATE_READY) && (hperh->state != UART_STATE_BUSY_RX))
1292 return BUSY;
1293
1294 SET_BIT(hperh->state, UART_STATE_TX_MASK);
1295
1296 if (uart_wait_flag(hperh, UART_STATUS_TFEMPTY, SET, timeout) != OK) {
1297 hperh->state = UART_STATE_READY;
1298 return TIMEOUT;
1299 }
1300
1301 WRITE_REG(hperh->perh->TXBUF, (addr | 0x100));
1302
1303 if (uart_wait_flag(hperh, UART_STATUS_TFEMPTY, SET, timeout) != OK) {
1304 hperh->state = UART_STATE_READY;
1305 return TIMEOUT;
1306 }
1307
1308 CLEAR_BIT(hperh->state, UART_STATE_TX_MASK);
1309
1310 return OK;
1311 }
1312
1322 it_status_t ald_uart_get_it_status(uart_handle_t *hperh, uart_it_t it)
1323 {
1324 it_status_t status = RESET;
1325
1326 assert_param(IS_UART_ALL(hperh->perh));
1327 assert_param(IS_UART_IT(it));
1328
1329 if (hperh->perh->IVS & it)
1330 status = SET;
1331
1332 return status;
1333 }
1334
1344 flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status)
1345 {
1346 assert_param(IS_UART_ALL(hperh->perh));
1347 assert_param(IS_UART_STATUS(status));
1348
1349 if (hperh->perh->STAT & status)
1350 return SET;
1351
1352 return RESET;
1353 }
1354
1355
1365 flag_status_t ald_uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag)
1366 {
1367 assert_param(IS_UART_ALL(hperh->perh));
1368 assert_param(IS_UART_IF(flag));
1369
1370 if (hperh->perh->RIF & flag)
1371 return SET;
1372
1373 return RESET;
1374 }
1375
1385 flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag)
1386 {
1387 assert_param(IS_UART_ALL(hperh->perh));
1388 assert_param(IS_UART_IF(flag));
1389
1390 if (hperh->perh->IFM & flag)
1391 return SET;
1392
1393 return RESET;
1394 }
1395
1403 void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag)
1404 {
1405 assert_param(IS_UART_ALL(hperh->perh));
1406 assert_param(IS_UART_IF(flag));
1407
1408 hperh->perh->ICR = flag;
1409 return;
1410 }
1438 uart_state_t ald_uart_get_state(uart_handle_t *hperh)
1439 {
1440 return hperh->state;
1441 }
1442
1448 uint32_t ald_uart_get_error(uart_handle_t *hperh)
1449 {
1450 return hperh->err_code;
1451 }
1452
1459 #endif /* ALD_UART */
1460
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
UART_STATUS_TFOERR
Definition: ald_uart.h:300
DMA_MSEL_UART4
Definition: ald_dma.h:88
DMA_DATA_SIZE_HALFWORD
Definition: ald_dma.h:228
ald_uart_dma_resume
ald_status_t ald_uart_dma_resume(uart_handle_t *hperh)
Resumes the DMA Transfer.
Definition: ald_uart.c:934
ENABLE
Definition: type.h:49
uart_lin_break_len_t
uart_lin_break_len_t
LIN detection break length.
Definition: ald_uart.h:240
dma_config_t::burst
type_func_t burst
Definition: ald_dma.h:286
ald_dma_config_basic
void ald_dma_config_basic(dma_handle_t *hperh)
Configure DMA channel according to the specified parameter in the dma_handle_t structure. The DMA mode is basic. This mode is used to carry data from peripheral to memory or from memory to peripheral.
Definition: ald_dma.c:499
OK
Definition: utils.h:55
__UNLOCK
#define __UNLOCK(x)
Definition: utils.h:101
DMA_MSEL_UART5
Definition: ald_dma.h:89
ald_uart_clear_flag_status
void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag)
Clear the UART interrupt flag.
Definition: ald_uart.c:1403
uart_rs485_config_t
UART RS485 configure structure definition.
Definition: ald_uart.h:195
ald_uart_recv_frame_by_it
ald_status_t ald_uart_recv_frame_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t t_out)
Receives an frame of data in non blocking mode.
Definition: ald_uart.c:730
UART_MODE_LIN
Definition: ald_uart.h:114
IS_UART_IT
#define IS_UART_IT(x)
Definition: ald_uart.h:413
ald_uart_get_it_status
it_status_t ald_uart_get_it_status(uart_handle_t *hperh, uart_it_t it)
Get the status of UART interrupt source.
Definition: ald_uart.c:1322
ald_uart_scard_config
void ald_uart_scard_config(uart_handle_t *hperh, uart_scard_config_t *config)
Configure the smart card mode according to the specified parameters in the uart_scard_config_t.
Definition: ald_uart.c:415
dma_handle_t::cplt_arg
void * cplt_arg
Definition: ald_dma.h:302
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
ald_uart_rx_fifo_config
void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config)
Configure receive fifo parameters.
Definition: ald_uart.c:1195
ald_uart_dma_pause
ald_status_t ald_uart_dma_pause(uart_handle_t *hperh)
Pauses the DMA Transfer.
Definition: ald_uart.c:920
uart_handle_s::err_code
uart_error_t err_code
Definition: ald_uart.h:185
uart_auto_baud_mode_t
uart_auto_baud_mode_t
UART auto-baud mode.
Definition: ald_uart.h:268
BUSY
Definition: utils.h:57
uart_handle_s::tx_cplt_cbk
void(* tx_cplt_cbk)(struct uart_handle_s *arg)
Definition: ald_uart.h:187
dma_config_t::msel
dma_msel_t msel
Definition: ald_dma.h:289
READ_BITS
#define READ_BITS(reg, msk, s)
Definition: type.h:70
UART_IT_TSEMPTY
Definition: ald_uart.h:320
SET
Definition: type.h:39
UART_ERROR_PE
Definition: ald_uart.h:148
uart_init_t::baud
uint32_t baud
Definition: ald_uart.h:159
IS_UART_RXFIFO_TYPE
#define IS_UART_RXFIFO_TYPE(x)
Definition: ald_uart.h:389
uart_dma_req_t
uart_dma_req_t
UART DMA Requests.
Definition: ald_uart.h:277
type_func_t
type_func_t
Definition: type.h:47
uart_it_t
uart_it_t
UART interrupt types.
Definition: ald_uart.h:306
uart_rs485_config_t::invert
type_func_t invert
Definition: ald_uart.h:198
DMA_MSIGSEL_UART45_RNR
Definition: ald_dma.h:139
UART_STATE_BUSY_TX
Definition: ald_uart.h:136
uart_init_t::stop_bits
uart_stop_bits_t stop_bits
Definition: ald_uart.h:161
ald_uart_interrupt_config
void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state)
Enable/disable the specified UART interrupts.
Definition: ald_uart.c:1126
DISABLE
Definition: type.h:48
UART_STATE_RX_MASK
#define UART_STATE_RX_MASK
Definition: ald_uart.h:455
dma_handle_t::config
dma_config_t config
Definition: ald_dma.h:299
uart_txfifo_t
uart_txfifo_t
UART TXFIFO size.
Definition: ald_uart.h:248
UART_STATE_READY
Definition: ald_uart.h:134
DMA_MSEL_UART1
Definition: ald_dma.h:85
dma_config_t::src_inc
dma_data_inc_t src_inc
Definition: ald_dma.h:282
UART_PARITY_EVEN
Definition: ald_uart.h:106
DMA_MSEL_UART0
Definition: ald_dma.h:84
dma_config_t::src
void * src
Definition: ald_dma.h:278
UART_IF_TFTH
Definition: ald_uart.h:344
UART_ERROR_FE
Definition: ald_uart.h:150
UART_MODE_SCARD
Definition: ald_uart.h:118
IS_UART_TXFIFO_TYPE
#define IS_UART_TXFIFO_TYPE(x)
Definition: ald_uart.h:385
ald_uart_irq_handler_fast
void ald_uart_irq_handler_fast(uart_handle_t *hperh)
This function handles UART interrupt request.
Definition: ald_uart.c:1031
UART_STATUS_TFTH
Definition: ald_uart.h:297
IS_UART_DMA_REQ
#define IS_UART_DMA_REQ(x)
Definition: ald_uart.h:396
ald_uart_get_status
flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status)
Get the status of UART_SR register.
Definition: ald_uart.c:1344
ald_uart_auto_baud_config
void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode)
Configure the mode of auto-baud-rate detect.
Definition: ald_uart.c:1269
DMA_MSIGSEL_UART_TXEMPTY
Definition: ald_dma.h:137
UART_IF_RFTH
Definition: ald_uart.h:339
UART_MODE_IrDA
Definition: ald_uart.h:115
uart_handle_s::rx_cplt_cbk
void(* rx_cplt_cbk)(struct uart_handle_s *arg)
Definition: ald_uart.h:188
uart_handle_s
UART handle structure definition.
Definition: ald_uart.h:170
uart_dma_send_cplt
static void uart_dma_send_cplt(void *arg)
DMA uart transmit process complete callback.
Definition: ald_uart.c:113
ald_uart_tx_fifo_config
void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config)
Configure transmit fifo parameters.
Definition: ald_uart.c:1178
RESET
Definition: type.h:38
ald_uart_get_mask_flag_status
flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag)
Get the status of interrupt flag and interupt source.
Definition: ald_uart.c:1385
uart_init_t::fctl
uart_hw_flow_ctl_t fctl
Definition: ald_uart.h:164
ald_uart_get_error
uint32_t ald_uart_get_error(uart_handle_t *hperh)
Return the UART error code.
Definition: ald_uart.c:1448
IS_UART_PARITY
#define IS_UART_PARITY(x)
Definition: ald_uart.h:371
dma_handle_t::err_arg
void * err_arg
Definition: ald_dma.h:303
ald_uart_send_by_it
ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size)
Sends an amount of data in non blocking mode.
Definition: ald_uart.c:664
UART_MODE_HDSEL
Definition: ald_uart.h:117
UART_STATUS_TSBUSY
Definition: ald_uart.h:296
uart_handle_s::tx_buf
uint8_t * tx_buf
Definition: ald_uart.h:173
ald_uart_recv_by_it
ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size)
Receives an amount of data in non blocking mode.
Definition: ald_uart.c:697
UART_IF_TFEMPTY
Definition: ald_uart.h:345
UART_ERROR_NONE
Definition: ald_uart.h:147
uart_handle_s::hdmatx
dma_handle_t hdmatx
Definition: ald_uart.h:180
it_status_t
enum flag_status_t it_status_t
ald_uart_recv_by_dma
ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
Receives an amount of data in non blocking mode.
Definition: ald_uart.c:846
UART_STATE_TX_MASK
#define UART_STATE_TX_MASK
Definition: ald_uart.h:454
ald_uart_send
ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Sends an amount of data in blocking mode.
Definition: ald_uart.c:488
IS_UART_STOPBITS
#define IS_UART_STOPBITS(x)
Definition: ald_uart.h:367
ald_uart_send_by_dma
ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
Sends an amount of data in non blocking mode.
Definition: ald_uart.c:766
uart_handle_s::init
uart_init_t init
Definition: ald_uart.h:172
UART_MODE_RS485
Definition: ald_uart.h:116
uart_init_t::mode
uart_mode_t mode
Definition: ald_uart.h:163
IS_UART_HARDWARE_FLOW_CONTROL
#define IS_UART_HARDWARE_FLOW_CONTROL(x)
Definition: ald_uart.h:380
uart_wait_flag
static ald_status_t uart_wait_flag(uart_handle_t *hperh, uart_status_t flag, flag_status_t status, uint32_t timeout)
This function handles uart Communication Timeout.
Definition: ald_uart.c:177
dma_config_t::size
uint16_t size
Definition: ald_dma.h:280
UART_STATUS_TFEMPTY
Definition: ald_uart.h:298
DMA_MSIGSEL_UART_RNR
Definition: ald_dma.h:138
uart_state_t
uart_state_t
ALD UART state.
Definition: ald_uart.h:132
UART_IT_RXTO
Definition: ald_uart.h:311
ald_uart_reset
void ald_uart_reset(uart_handle_t *hperh)
Reset UART peripheral.
Definition: ald_uart.c:303
IS_UART_IF
#define IS_UART_IF(x)
Definition: ald_uart.h:430
uart_rs485_config_t::addr
uint8_t addr
Definition: ald_uart.h:199
ald_cmu.h
Header file of CMU module driver.
uart_scard_config_t::clk_out
type_func_t clk_out
Definition: ald_uart.h:234
UART_PARITY_ODD
Definition: ald_uart.h:105
uart_scard_config_t::block_len
uint8_t block_len
Definition: ald_uart.h:230
DMA_MSIGSEL_UART45_TXEMPTY
Definition: ald_dma.h:140
UART_STATUS_FERR
Definition: ald_uart.h:287
IS_UART_ALL
#define IS_UART_ALL(x)
Definition: ald_uart.h:357
UART_STATE_RESET
Definition: ald_uart.h:133
ald_uart_rs485_send_addr
ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout)
Send address in RS485 mode.
Definition: ald_uart.c:1287
DMA_DATA_INC_HALFWORD
Definition: ald_dma.h:218
ald_uart_recv_n_lock
ald_status_t ald_uart_recv_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Receives an amount of data in blocking mode. Don&#39;t care about device lock. This is for RTOS...
Definition: ald_uart.c:626
UART_IF_RXTO
Definition: ald_uart.h:334
IS_UART_WORD_LENGTH
#define IS_UART_WORD_LENGTH(x)
Definition: ald_uart.h:363
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
ald_uart_send_n_lock
ald_status_t ald_uart_send_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Sends an amount of data in blocking mode. Don&#39;t care about device lock. This is for RTOS...
Definition: ald_uart.c:582
UART_IT_TFTH
Definition: ald_uart.h:321
uart_handle_s::rx_size
uint16_t rx_size
Definition: ald_uart.h:177
DMA_DATA_INC_BYTE
Definition: ald_dma.h:217
UART_ERROR_ORE
Definition: ald_uart.h:151
uart_dma_error
static void uart_dma_error(void *arg)
DMA uart communication error callback.
Definition: ald_uart.c:151
ald_uart_lin_detect_break_len_config
void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len)
Configure the length of break frame to be detect.
Definition: ald_uart.c:1250
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
UART_DMA_REQ_TX
Definition: ald_uart.h:278
ald_uart_get_flag_status
flag_status_t ald_uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag)
Get the status of UART interrupt flag.
Definition: ald_uart.c:1365
ald_uart_dma_stop
ald_status_t ald_uart_dma_stop(uart_handle_t *hperh)
Stops the DMA Transfer.
Definition: ald_uart.c:948
TIMEOUT
Definition: utils.h:58
ald_uart_init
void ald_uart_init(uart_handle_t *hperh)
Initializes the UARTx according to the specified parameters in the uart_handle_t. ...
Definition: ald_uart.c:331
IS_UART_AUTO_BAUD_MODE
#define IS_UART_AUTO_BAUD_MODE(x)
Definition: ald_uart.h:393
uart_init_t::word_length
uart_word_length_t word_length
Definition: ald_uart.h:160
DMA_MSEL_UART3
Definition: ald_dma.h:87
ald_cmu_get_pclk1_clock
uint32_t ald_cmu_get_pclk1_clock(void)
Get APB1 clock.
Definition: ald_cmu.c:627
UART_STATUS_RFTH
Definition: ald_uart.h:291
dma_config_t::dst
void * dst
Definition: ald_dma.h:279
UART_IT_RFTH
Definition: ald_uart.h:316
uart_status_t
uart_status_t
UART status types.
Definition: ald_uart.h:285
UART_IF_TBC
Definition: ald_uart.h:343
uart_init_t::parity
uart_parity_t parity
Definition: ald_uart.h:162
UART_ERROR_DMA
Definition: ald_uart.h:152
uart_flag_t
uart_flag_t
UART flags types.
Definition: ald_uart.h:329
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
IS_UART_BAUDRATE
#define IS_UART_BAUDRATE(x)
Definition: ald_uart.h:451
IS_UART_MODE
#define IS_UART_MODE(x)
Definition: ald_uart.h:374
uart_scard_config_t::pt
uint8_t pt
Definition: ald_uart.h:231
DMA_DATA_INC_NONE
Definition: ald_dma.h:220
UART_DMA_REQ_RX
Definition: ald_uart.h:279
IS_UART_LIN_BREAK_LEN
#define IS_UART_LIN_BREAK_LEN(x)
Definition: ald_uart.h:383
dma_config_t::msigsel
dma_msigsel_t msigsel
Definition: ald_dma.h:290
dma_config_t::data_width
dma_data_size_t data_width
Definition: ald_dma.h:281
ald_uart_get_state
uart_state_t ald_uart_get_state(uart_handle_t *hperh)
Returns the UART state.
Definition: ald_uart.c:1438
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
IS_UART_SCARD_CLK
#define IS_UART_SCARD_CLK(x)
Definition: ald_uart.h:447
ald_uart_dma_req_config
void ald_uart_dma_req_config(uart_handle_t *hperh, uart_dma_req_t req, type_func_t state)
Configure UART DMA request.
Definition: ald_uart.c:1150
dma_handle_t::perh
DMA_TypeDef * perh
Definition: ald_dma.h:298
flag_status_t
flag_status_t
Definition: type.h:37
uart_rxfifo_t
uart_rxfifo_t
UART RXFIFO size.
Definition: ald_uart.h:258
ald_uart_irq_handler
void ald_uart_irq_handler(uart_handle_t *hperh)
This function handles UART interrupt request.
Definition: ald_uart.c:964
uart_lin_break_detect_irq
void uart_lin_break_detect_irq(uart_handle_t *hperh, type_func_t status)
Enable/Disable break signal detect interrup.
Definition: ald_uart.c:1212
UART_STATUS_RFOERR
Definition: ald_uart.h:294
ald_uart_lin_send_break
void ald_uart_lin_send_break(uart_handle_t *hperh)
request to send a frame of break.
Definition: ald_uart.c:1231
uart_dma_recv_cplt
static void uart_dma_recv_cplt(void *arg)
DMA uart receive process complete callback.
Definition: ald_uart.c:131
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
dma_config_t::dst_inc
dma_data_inc_t dst_inc
Definition: ald_dma.h:283
uart_handle_s::rx_count
uint16_t rx_count
Definition: ald_uart.h:178
trng_handle_s::state
trng_state_t state
Definition: ald_trng.h:115
uart_rs485_config_t::normal
type_func_t normal
Definition: ald_uart.h:196
ald_uart_recv
ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Receives an amount of data in blocking mode.
Definition: ald_uart.c:537
uart_scard_config_t::retry
scard_retry_t retry
Definition: ald_uart.h:232
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
uart_handle_s::rx_buf
uint8_t * rx_buf
Definition: ald_uart.h:176
UART_PARITY_NONE
Definition: ald_uart.h:104
uart_handle_s::tx_size
uint16_t tx_size
Definition: ald_uart.h:174
uart_handle_s::hdmarx
dma_handle_t hdmarx
Definition: ald_uart.h:181
dma_handle_t::cplt_cbk
void(* cplt_cbk)(void *arg)
Definition: ald_dma.h:300
uart_handle_s::error_cbk
void(* error_cbk)(struct uart_handle_s *arg)
Definition: ald_uart.h:189
__LOCK
#define __LOCK(x)
Definition: utils.h:92
IS_UART_STATUS
#define IS_UART_STATUS(x)
Definition: ald_uart.h:398
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
DMA_MSEL_UART2
Definition: ald_dma.h:86
ERROR
Definition: utils.h:56
__uart_recv_by_it
static ald_status_t __uart_recv_by_it(uart_handle_t *hperh)
Receives an amount of data in non blocking mode.
Definition: ald_uart.c:241
dma_handle_t::err_cbk
void(* err_cbk)(void *arg)
Definition: ald_dma.h:301
uart_rs485_config_t::dir
type_func_t dir
Definition: ald_uart.h:197
uart_scard_config_t
UART Smart card configure structure definition.
Definition: ald_uart.h:229
ald_uart_rs485_config
void ald_uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config)
Configure the RS485 mode according to the specified parameters in the uart_rs485_config_t.
Definition: ald_uart.c:392
ald_uart.h
Header file of UART module library.
dma_config_t::channel
uint8_t channel
Definition: ald_dma.h:291
IS_UART_SCARD
#define IS_UART_SCARD(x)
Definition: ald_uart.h:355
ald_dma_config_struct
void ald_dma_config_struct(dma_config_t *p)
Configure dma_config_t structure using default parameter. User can invoked this function, before configure dma_config_t.
Definition: ald_dma.c:294
uart_handle_s::tx_count
uint16_t tx_count
Definition: ald_uart.h:175
__uart_send_by_it
static ald_status_t __uart_send_by_it(uart_handle_t *hperh)
Sends an amount of data in non blocking mode.
Definition: ald_uart.c:200
UART_STATE_BUSY_RX
Definition: ald_uart.h:137
__uart_end_send_by_it
static ald_status_t __uart_end_send_by_it(uart_handle_t *hperh)
Wraps up transmission in non blocking mode.
Definition: ald_uart.c:221
UART_STATUS_PERR
Definition: ald_uart.h:286
uart_scard_config_t::clk_div
scard_clk_div_t clk_div
Definition: ald_uart.h:233


ALD User Manual: D:/svn/src/ald_uart.h Source File

  • D:
  • svn
  • src
ald_uart.h
Go to the documentation of this file.
1
17 #ifndef __ALD_UART_H__
18 #define __ALD_UART_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25 #include "ald_dma.h"
26
27
40 #define UART_RX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_RXEN_MSK))
41 #define UART_RX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RXEN_MSK))
42 #define UART_TX_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK))
43 #define UART_TX_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_TXEN_MSK))
44 #define UART_RX_TIMEOUT_ENABLE(hperh) (SET_BIT((hperh)->perh->RTOR, UART_RTOR_RTOEN_MSK))
45 #define UART_RX_TIMEOUT_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->RTOR, UART_RTOR_RTOEN_MSK))
46 #define UART_MSB_FIRST_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK))
47 #define UART_MSB_FIRST_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_MSB_MSK))
48 #define UART_DATA_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_DATAINV_MSK))
49 #define UART_DATA_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_DATAINV_MSK))
50 #define UART_RX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_RXINV_MSK))
51 #define UART_RX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_RXINV_MSK))
52 #define UART_TX_INV_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_TXINV_MSK))
53 #define UART_TX_INV_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_TXINV_MSK))
54 #define UART_TX_RX_SWAP_ENABLE(hperh) (SET_BIT((hperh)->perh->LCON, UART_LCON_SWAP_MSK))
55 #define UART_TX_RX_SWAP_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->LCON, UART_LCON_SWAP_MSK))
56 #define UART_HDSEL_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_HDEN_MSK))
57 #define UART_HDSEL_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_HDEN_MSK))
58 #define UART_FIFO_TX_RESET(hperh) (SET_BIT((hperh)->perh->FCON, UART_FCON_TFRST_MSK))
59 #define UART_FIFO_RX_RESET(hperh) (SET_BIT((hperh)->perh->FCON, UART_FCON_RFRST_MSK))
60 #define UART_LPBMOD_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_LPBKEN_MSK))
61 #define UART_LPBMOD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_LPBKEN_MSK))
62 #define UART_AUTOBR_ENABLE(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK))
63 #define UART_AUTOBR_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->MCON, UART_MCON_ABREN_MSK))
64 #define UART_AUTOBR_REPT(hperh) (SET_BIT((hperh)->perh->MCON, UART_MCON_ABRREPT_MSK))
65 #define UART_GET_BRR_VALUE(hperh) (READ_REG((hperh)->perh->BRR))
66 #define UART_SET_TIMEOUT_VALUE(x, y) (MODIFY_REG((x)->perh->RTOR, UART_RTOR_RTO_MSK, (y) << UART_RTOR_RTO_POSS))
67 #define UART_ENABLE_SCARD_CLK(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCLKEN_MSK))
68 #define UART_DISABLE_SCARD_CLK(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCLKEN_MSK))
69 #define UART_ENABLE_SCARD_NACK(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCNACK_MSK))
70 #define UART_DISABLE_SCARD_NACK(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCNACK_MSK))
71 #define UART_SCARD_ENABLE(hperh) (SET_BIT((hperh)->perh->SCARD, UART_SCARD_SCEN_MSK))
72 #define UART_SCARD_DISABLE(hperh) (CLEAR_BIT((hperh)->perh->SCARD, UART_SCARD_SCEN_MSK))
73
83 typedef enum {
84 UART_WORD_LENGTH_8B = 0x0U,
85 UART_WORD_LENGTH_7B = 0x1U,
86 UART_WORD_LENGTH_6B = 0x2U,
87 UART_WORD_LENGTH_5B = 0x3U,
88 } uart_word_length_t;
89
93 typedef enum {
94 UART_STOP_BITS_1 = 0x0U,
95 UART_STOP_BITS_2 = 0x1U,
96 UART_STOP_BITS_0_5 = 0x0U,
97 UART_STOP_BITS_1_5 = 0x1U,
98 } uart_stop_bits_t;
99
103 typedef enum {
104 UART_PARITY_NONE = 0x0U,
105 UART_PARITY_ODD = 0x1U,
106 UART_PARITY_EVEN = 0x3U,
107 } uart_parity_t;
108
112 typedef enum {
113 UART_MODE_UART = 0x0U,
114 UART_MODE_LIN = 0x1U,
115 UART_MODE_IrDA = 0x2U,
116 UART_MODE_RS485 = 0x3U,
117 UART_MODE_HDSEL = 0x4U,
118 UART_MODE_SCARD = 0x5U,
119 } uart_mode_t;
120
124 typedef enum {
125 UART_HW_FLOW_CTL_DISABLE = 0x0U,
126 UART_HW_FLOW_CTL_ENABLE = 0x1U,
127 } uart_hw_flow_ctl_t;
128
132 typedef enum {
133 UART_STATE_RESET = 0x00U,
134 UART_STATE_READY = 0x01U,
135 UART_STATE_BUSY = 0x02U,
136 UART_STATE_BUSY_TX = 0x11U,
137 UART_STATE_BUSY_RX = 0x21U,
138 UART_STATE_BUSY_TX_RX = 0x31U,
139 UART_STATE_TIMEOUT = 0x03U,
140 UART_STATE_ERROR = 0x04U,
141 } uart_state_t;
142
146 typedef enum {
147 UART_ERROR_NONE = ((uint32_t)0x00U),
148 UART_ERROR_PE = ((uint32_t)0x01U),
149 UART_ERROR_NE = ((uint32_t)0x02U),
150 UART_ERROR_FE = ((uint32_t)0x04U),
151 UART_ERROR_ORE = ((uint32_t)0x08U),
152 UART_ERROR_DMA = ((uint32_t)0x10U),
153 } uart_error_t;
154
158 typedef struct {
159 uint32_t baud;
160 uart_word_length_t word_length;
161 uart_stop_bits_t stop_bits;
162 uart_parity_t parity;
163 uart_mode_t mode;
164 uart_hw_flow_ctl_t fctl;
165 } uart_init_t;
166
170 typedef struct uart_handle_s {
171 UART_TypeDef *perh;
172 uart_init_t init;
173 uint8_t *tx_buf;
174 uint16_t tx_size;
175 uint16_t tx_count;
176 uint8_t *rx_buf;
177 uint16_t rx_size;
178 uint16_t rx_count;
179 #ifdef ALD_DMA
180 dma_handle_t hdmatx;
181 dma_handle_t hdmarx;
182 #endif
183 lock_state_t lock;
184 uart_state_t state;
185 uart_error_t err_code;
187 void (*tx_cplt_cbk)(struct uart_handle_s *arg);
188 void (*rx_cplt_cbk)(struct uart_handle_s *arg);
189 void (*error_cbk)(struct uart_handle_s *arg);
190 } uart_handle_t;
191
195 typedef struct {
196 type_func_t normal;
197 type_func_t dir;
198 type_func_t invert;
199 uint8_t addr;
200 } uart_rs485_config_t;
201
205 typedef enum {
206 SCARD_CLOCK_DIV1 = 0x0U,
207 SCARD_CLOCK_DIV2 = 0x1U,
208 SCARD_CLOCK_DIV4 = 0x2U,
209 SCARD_CLOCK_DIV6 = 0x3U,
210 } scard_clk_div_t;
211
215 typedef enum {
216 SCARD_RETRY_CNT0 = 0x0U,
217 SCARD_RETRY_CNT1 = 0x1U,
218 SCARD_RETRY_CNT2 = 0x2U,
219 SCARD_RETRY_CNT3 = 0x3U,
220 SCARD_RETRY_CNT4 = 0x4U,
221 SCARD_RETRY_CNT5 = 0x5U,
222 SCARD_RETRY_CNT6 = 0x6U,
223 SCARD_RETRY_CNT7 = 0x7U,
224 } scard_retry_t;
225
229 typedef struct {
230 uint8_t block_len;
231 uint8_t pt;
232 scard_retry_t retry;
233 scard_clk_div_t clk_div;
234 type_func_t clk_out;
235 } uart_scard_config_t;
236
240 typedef enum {
241 LIN_BREAK_LEN_10B = 0x0U,
242 LIN_BREAK_LEN_11B = 0x1U,
243 } uart_lin_break_len_t;
244
248 typedef enum {
249 UART_TXFIFO_EMPTY = 0x0U,
250 UART_TXFIFO_2BYTE = 0x1U,
251 UART_TXFIFO_4BYTE = 0x2U,
252 UART_TXFIFO_8BYTE = 0x3U,
253 } uart_txfifo_t;
254
258 typedef enum {
259 UART_RXFIFO_1BYTE = 0x0U,
260 UART_RXFIFO_4BYTE = 0x1U,
261 UART_RXFIFO_8BYTE = 0x2U,
262 UART_RXFIFO_14BYTE = 0x3U,
263 } uart_rxfifo_t;
264
268 typedef enum {
269 UART_ABRMOD_1_TO_0 = 0x0U,
270 UART_ABRMOD_1 = 0x1U,
271 UART_ABRMOD_0_TO_1 = 0x2U,
272 } uart_auto_baud_mode_t;
273
277 typedef enum {
278 UART_DMA_REQ_TX = 0x0U,
279 UART_DMA_REQ_RX = 0x1U,
280 } uart_dma_req_t;
281
285 typedef enum {
286 UART_STATUS_PERR = (1U << 0),
287 UART_STATUS_FERR = (1U << 1),
288 UART_STATUS_BKERR = (1U << 2),
289 UART_STATUS_CTSSTA = (1U << 3),
290 UART_STATUS_RSBUSY = (1U << 8),
291 UART_STATUS_RFTH = (1U << 9),
292 UART_STATUS_RFEMPTY = (1U << 10),
293 UART_STATUS_RFFULL = (1U << 11),
294 UART_STATUS_RFOERR = (1U << 12),
295 UART_STATUS_RFUERR = (1U << 13),
296 UART_STATUS_TSBUSY = (1U << 14),
297 UART_STATUS_TFTH = (1U << 15),
298 UART_STATUS_TFEMPTY = (1U << 16),
299 UART_STATUS_TFFULL = (1U << 17),
300 UART_STATUS_TFOERR = (1U << 18),
301 } uart_status_t;
302
306 typedef enum {
307 UART_IT_RXBERR = (1U << 0),
308 UART_IT_ABEND = (1U << 1),
309 UART_IT_ABTO = (1U << 2),
310 UART_IT_DCTS = (1U << 3),
311 UART_IT_RXTO = (1U << 4),
312 UART_IT_ADDRM = (1U << 5),
313 UART_IT_LINBK = (1U << 6),
314 UART_IT_EOB = (1U << 7),
315 UART_IT_NOISE = (1U << 8),
316 UART_IT_RFTH = (1U << 9),
317 UART_IT_RFFULL = (1U << 11),
318 UART_IT_RFOERR = (1U << 12),
319 UART_IT_RFUERR = (1U << 13),
320 UART_IT_TSEMPTY = (1U << 14),
321 UART_IT_TFTH = (1U << 15),
322 UART_IT_TFEMPTY = (1U << 16),
323 UART_IT_TFOVER = (1U << 18),
324 } uart_it_t;
325
329 typedef enum {
330 UART_IF_RXBERR = (1U << 0),
331 UART_IF_ABEND = (1U << 1),
332 UART_IF_ABTO = (1U << 2),
333 UART_IF_DCTS = (1U << 3),
334 UART_IF_RXTO = (1U << 4),
335 UART_IF_ADDRM = (1U << 5),
336 UART_IF_LINBK = (1U << 6),
337 UART_IF_EOB = (1U << 7),
338 UART_IF_NOISE = (1U << 8),
339 UART_IF_RFTH = (1U << 9),
340 UART_IF_RFFULL = (1U << 11),
341 UART_IF_RFOERR = (1U << 12),
342 UART_IF_RFUERR = (1U << 13),
343 UART_IF_TBC = (1U << 14),
344 UART_IF_TFTH = (1U << 15),
345 UART_IF_TFEMPTY = (1U << 16),
346 UART_IF_TFOVER = (1U << 18),
347 } uart_flag_t;
355 #define IS_UART_SCARD(x)(((x) == UART4) || \
356 ((x) == UART5))
357 #define IS_UART_ALL(x) (((x) == UART0) || \
358 ((x) == UART1) || \
359 ((x) == UART2) || \
360 ((x) == UART3) || \
361 ((x) == UART4) || \
362 ((x) == UART5))
363 #define IS_UART_WORD_LENGTH(x) (((x) == UART_WORD_LENGTH_5B) || \
364 ((x) == UART_WORD_LENGTH_6B) || \
365 ((x) == UART_WORD_LENGTH_7B) || \
366 ((x) == UART_WORD_LENGTH_8B))
367 #define IS_UART_STOPBITS(x) (((x) == UART_STOP_BITS_1) || \
368 ((x) == UART_STOP_BITS_2) || \
369 ((x) == UART_STOP_BITS_0_5) || \
370 ((x) == UART_STOP_BITS_1_5))
371 #define IS_UART_PARITY(x) (((x) == UART_PARITY_NONE) || \
372 ((x) == UART_PARITY_ODD) || \
373 ((x) == UART_PARITY_EVEN))
374 #define IS_UART_MODE(x) (((x) == UART_MODE_UART) || \
375 ((x) == UART_MODE_LIN) || \
376 ((x) == UART_MODE_IrDA) || \
377 ((x) == UART_MODE_HDSEL) || \
378 ((x) == UART_MODE_SCARD) || \
379 ((x) == UART_MODE_RS485))
380 #define IS_UART_HARDWARE_FLOW_CONTROL(x) \
381 (((x) == UART_HW_FLOW_CTL_DISABLE) || \
382 ((x) == UART_HW_FLOW_CTL_ENABLE))
383 #define IS_UART_LIN_BREAK_LEN(x) (((x) == LIN_BREAK_LEN_10B) || \
384 ((x) == LIN_BREAK_LEN_11B))
385 #define IS_UART_TXFIFO_TYPE(x) (((x) == UART_TXFIFO_EMPTY) || \
386 ((x) == UART_TXFIFO_2BYTE) || \
387 ((x) == UART_TXFIFO_4BYTE) || \
388 ((x) == UART_TXFIFO_8BYTE))
389 #define IS_UART_RXFIFO_TYPE(x) (((x) == UART_RXFIFO_1BYTE) || \
390 ((x) == UART_RXFIFO_4BYTE) || \
391 ((x) == UART_RXFIFO_8BYTE) || \
392 ((x) == UART_RXFIFO_14BYTE))
393 #define IS_UART_AUTO_BAUD_MODE(x) (((x) == UART_ABRMOD_1_TO_0) || \
394 ((x) == UART_ABRMOD_1) || \
395 ((x) == UART_ABRMOD_0_TO_1))
396 #define IS_UART_DMA_REQ(x) (((x) == UART_DMA_REQ_TX) || \
397 ((x) == UART_DMA_REQ_RX))
398 #define IS_UART_STATUS(x) (((x) == UART_STATUS_PERR) || \
399 ((x) == UART_STATUS_FERR) || \
400 ((x) == UART_STATUS_BKERR) || \
401 ((x) == UART_STATUS_CTSSTA) || \
402 ((x) == UART_STATUS_RSBUSY) || \
403 ((x) == UART_STATUS_RFEMPTY) || \
404 ((x) == UART_STATUS_RFFULL) || \
405 ((x) == UART_STATUS_RFOERR) || \
406 ((x) == UART_STATUS_RFUERR) || \
407 ((x) == UART_STATUS_TSBUSY) || \
408 ((x) == UART_STATUS_RFTH) || \
409 ((x) == UART_STATUS_TFTH) || \
410 ((x) == UART_STATUS_TFEMPTY) || \
411 ((x) == UART_STATUS_TFFULL) || \
412 ((x) == UART_STATUS_TFOERR))
413 #define IS_UART_IT(x) (((x) == UART_IT_RXBERR) || \
414 ((x) == UART_IT_ABEND) || \
415 ((x) == UART_IT_ABTO) || \
416 ((x) == UART_IT_DCTS) || \
417 ((x) == UART_IT_RXTO) || \
418 ((x) == UART_IT_ADDRM) || \
419 ((x) == UART_IT_LINBK) || \
420 ((x) == UART_IT_EOB) || \
421 ((x) == UART_IT_NOISE) || \
422 ((x) == UART_IT_RFTH) || \
423 ((x) == UART_IT_RFFULL) || \
424 ((x) == UART_IT_RFOERR) || \
425 ((x) == UART_IT_RFUERR) || \
426 ((x) == UART_IT_TSEMPTY) || \
427 ((x) == UART_IT_TFTH) || \
428 ((x) == UART_IT_TFEMPTY) || \
429 ((x) == UART_IT_TFOVER))
430 #define IS_UART_IF(x) (((x) == UART_IF_RXBERR) || \
431 ((x) == UART_IF_ABEND) || \
432 ((x) == UART_IF_ABTO) || \
433 ((x) == UART_IF_DCTS) || \
434 ((x) == UART_IF_RXTO) || \
435 ((x) == UART_IF_ADDRM) || \
436 ((x) == UART_IF_LINBK) || \
437 ((x) == UART_IF_EOB) || \
438 ((x) == UART_IF_NOISE) || \
439 ((x) == UART_IF_RFTH) || \
440 ((x) == UART_IF_RFFULL) || \
441 ((x) == UART_IF_RFOERR) || \
442 ((x) == UART_IF_RFUERR) || \
443 ((x) == UART_IF_TBC) || \
444 ((x) == UART_IF_TFTH) || \
445 ((x) == UART_IF_TFEMPTY) || \
446 ((x) == UART_IF_TFOVER))
447 #define IS_UART_SCARD_CLK(x) (((x) == SCARD_CLOCK_DIV1) || \
448 ((x) == SCARD_CLOCK_DIV2) || \
449 ((x) == SCARD_CLOCK_DIV4) || \
450 ((x) == SCARD_CLOCK_DIV6))
451 #define IS_UART_BAUDRATE(x) (((x) > 0) && ((x) < 0x44AA21))
452 #define IS_UART_DATA(x) ((x) <= 0x1FF)
453
454 #define UART_STATE_TX_MASK (1U << 4)
455 #define UART_STATE_RX_MASK (1U << 5)
456
467 /* Initialization functions */
468 void ald_uart_init(uart_handle_t *hperh);
469 void ald_uart_reset(uart_handle_t *hperh);
470 void ald_uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config);
471 void ald_uart_scard_config(uart_handle_t *hperh, uart_scard_config_t *config);
479 /* IO operation functions */
480 ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
481 ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
482 ald_status_t ald_uart_send_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
483 ald_status_t ald_uart_recv_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
484 ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size);
485 ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size);
486 ald_status_t ald_uart_recv_frame_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t t_out);
487 #ifdef ALD_DMA
488 ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
489 ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
490 ald_status_t ald_uart_dma_pause(uart_handle_t *hperh);
491 ald_status_t ald_uart_dma_resume(uart_handle_t *hperh);
492 ald_status_t ald_uart_dma_stop(uart_handle_t *hperh);
493 #endif
494 void ald_uart_irq_handler(uart_handle_t *hperh);
495 void ald_uart_irq_handler_fast(uart_handle_t *hperh);
503 /* Peripheral Control functions */
504 void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state);
505 void ald_uart_dma_req_config(uart_handle_t *hperh, uart_dma_req_t req, type_func_t state);
506 void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config);
507 void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config);
508 void uart_lin_break_detect_irq(uart_handle_t *hperh, type_func_t status);
509 void ald_uart_lin_send_break(uart_handle_t *hperh);
510 void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len);
511 void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode);
512 ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout);
513 it_status_t ald_uart_get_it_status(uart_handle_t *hperh, uart_it_t it);
514 flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status);
515 flag_status_t ald_uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag);
516 flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag);
517 void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag);
525 /* Peripheral State and Errors functions */
526 uart_state_t ald_uart_get_state(uart_handle_t *hperh);
527 uint32_t ald_uart_get_error(uart_handle_t *hperh);
544 #ifdef __cplusplus
545 }
546 #endif
547
548 #endif /* __ALD_UART_H__ */
UART_HW_FLOW_CTL_ENABLE
Definition: ald_uart.h:126
UART_IT_DCTS
Definition: ald_uart.h:310
uart_handle_s::state
uart_state_t state
Definition: ald_uart.h:184
UART_RXFIFO_1BYTE
Definition: ald_uart.h:259
UART_STATUS_TFOERR
Definition: ald_uart.h:300
uart_mode_t
uart_mode_t
UART mode.
Definition: ald_uart.h:112
SCARD_RETRY_CNT4
Definition: ald_uart.h:220
ald_uart_dma_resume
ald_status_t ald_uart_dma_resume(uart_handle_t *hperh)
Resumes the DMA Transfer.
Definition: ald_uart.c:934
uart_handle_s::lock
lock_state_t lock
Definition: ald_uart.h:183
uart_lin_break_len_t
uart_lin_break_len_t
LIN detection break length.
Definition: ald_uart.h:240
uart_hw_flow_ctl_t
uart_hw_flow_ctl_t
UART hardware flow control.
Definition: ald_uart.h:124
UART_TXFIFO_4BYTE
Definition: ald_uart.h:251
UART_STATUS_RFEMPTY
Definition: ald_uart.h:292
uart_init_t
UART init structure definition.
Definition: ald_uart.h:158
ald_uart_clear_flag_status
void ald_uart_clear_flag_status(uart_handle_t *hperh, uart_flag_t flag)
Clear the UART interrupt flag.
Definition: ald_uart.c:1403
uart_rs485_config_t
UART RS485 configure structure definition.
Definition: ald_uart.h:195
UART_STOP_BITS_1_5
Definition: ald_uart.h:97
ald_uart_recv_frame_by_it
ald_status_t ald_uart_recv_frame_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t t_out)
Receives an frame of data in non blocking mode.
Definition: ald_uart.c:730
UART_IF_ABTO
Definition: ald_uart.h:332
dma_handle_t
DMA handle structure definition.
Definition: ald_dma.h:297
UART_MODE_LIN
Definition: ald_uart.h:114
ald_uart_get_it_status
it_status_t ald_uart_get_it_status(uart_handle_t *hperh, uart_it_t it)
Get the status of UART interrupt source.
Definition: ald_uart.c:1322
ald_uart_scard_config
void ald_uart_scard_config(uart_handle_t *hperh, uart_scard_config_t *config)
Configure the smart card mode according to the specified parameters in the uart_scard_config_t.
Definition: ald_uart.c:415
UART_IF_RXBERR
Definition: ald_uart.h:330
ald_uart_rx_fifo_config
void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config)
Configure receive fifo parameters.
Definition: ald_uart.c:1195
ald_uart_dma_pause
ald_status_t ald_uart_dma_pause(uart_handle_t *hperh)
Pauses the DMA Transfer.
Definition: ald_uart.c:920
UART_WORD_LENGTH_8B
Definition: ald_uart.h:84
uart_handle_s::err_code
uart_error_t err_code
Definition: ald_uart.h:185
uart_auto_baud_mode_t
uart_auto_baud_mode_t
UART auto-baud mode.
Definition: ald_uart.h:268
uart_handle_t
struct uart_handle_s uart_handle_t
UART handle structure definition.
UART_IT_TFEMPTY
Definition: ald_uart.h:322
UART_IT_TSEMPTY
Definition: ald_uart.h:320
UART_HW_FLOW_CTL_DISABLE
Definition: ald_uart.h:125
UART_IT_RFFULL
Definition: ald_uart.h:317
UART_ERROR_PE
Definition: ald_uart.h:148
uart_init_t::baud
uint32_t baud
Definition: ald_uart.h:159
uart_dma_req_t
uart_dma_req_t
UART DMA Requests.
Definition: ald_uart.h:277
type_func_t
type_func_t
Definition: type.h:47
UART_RXFIFO_4BYTE
Definition: ald_uart.h:260
uart_it_t
uart_it_t
UART interrupt types.
Definition: ald_uart.h:306
uart_rs485_config_t::invert
type_func_t invert
Definition: ald_uart.h:198
UART_STATE_BUSY_TX
Definition: ald_uart.h:136
uart_init_t::stop_bits
uart_stop_bits_t stop_bits
Definition: ald_uart.h:161
ald_uart_interrupt_config
void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state)
Enable/disable the specified UART interrupts.
Definition: ald_uart.c:1126
UART_STATUS_RFFULL
Definition: ald_uart.h:293
uart_txfifo_t
uart_txfifo_t
UART TXFIFO size.
Definition: ald_uart.h:248
UART_STATE_READY
Definition: ald_uart.h:134
UART_IT_LINBK
Definition: ald_uart.h:313
UART_PARITY_EVEN
Definition: ald_uart.h:106
UART_STATE_TIMEOUT
Definition: ald_uart.h:139
SCARD_CLOCK_DIV2
Definition: ald_uart.h:207
uart_error_t
uart_error_t
UART error codes.
Definition: ald_uart.h:146
UART_IF_TFTH
Definition: ald_uart.h:344
UART_ERROR_FE
Definition: ald_uart.h:150
UART_MODE_SCARD
Definition: ald_uart.h:118
ald_uart_irq_handler_fast
void ald_uart_irq_handler_fast(uart_handle_t *hperh)
This function handles UART interrupt request.
Definition: ald_uart.c:1031
UART_STATUS_TFTH
Definition: ald_uart.h:297
ald_uart_get_status
flag_status_t ald_uart_get_status(uart_handle_t *hperh, uart_status_t status)
Get the status of UART_SR register.
Definition: ald_uart.c:1344
ald_uart_auto_baud_config
void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode)
Configure the mode of auto-baud-rate detect.
Definition: ald_uart.c:1269
UART_IT_RXBERR
Definition: ald_uart.h:307
UART_IT_ABTO
Definition: ald_uart.h:309
UART_IF_RFTH
Definition: ald_uart.h:339
UART_WORD_LENGTH_6B
Definition: ald_uart.h:86
UART_MODE_IrDA
Definition: ald_uart.h:115
uart_handle_s::rx_cplt_cbk
void(* rx_cplt_cbk)(struct uart_handle_s *arg)
Definition: ald_uart.h:188
uart_handle_s
UART handle structure definition.
Definition: ald_uart.h:170
SCARD_CLOCK_DIV1
Definition: ald_uart.h:206
ald_uart_tx_fifo_config
void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config)
Configure transmit fifo parameters.
Definition: ald_uart.c:1178
UART_TXFIFO_8BYTE
Definition: ald_uart.h:252
ald_uart_get_mask_flag_status
flag_status_t ald_uart_get_mask_flag_status(uart_handle_t *hperh, uart_flag_t flag)
Get the status of interrupt flag and interupt source.
Definition: ald_uart.c:1385
UART_RXFIFO_8BYTE
Definition: ald_uart.h:261
uart_init_t::fctl
uart_hw_flow_ctl_t fctl
Definition: ald_uart.h:164
UART_IF_RFOERR
Definition: ald_uart.h:341
SCARD_RETRY_CNT5
Definition: ald_uart.h:221
ald_uart_get_error
uint32_t ald_uart_get_error(uart_handle_t *hperh)
Return the UART error code.
Definition: ald_uart.c:1448
scard_clk_div_t
scard_clk_div_t
Smart_card clock division.
Definition: ald_uart.h:205
UART_IF_ADDRM
Definition: ald_uart.h:335
ald_uart_send_by_it
ald_status_t ald_uart_send_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size)
Sends an amount of data in non blocking mode.
Definition: ald_uart.c:664
UART_MODE_HDSEL
Definition: ald_uart.h:117
utils.h
This file contains the Utilities functions/types for the driver.
UART_STATUS_TSBUSY
Definition: ald_uart.h:296
uart_handle_s::tx_buf
uint8_t * tx_buf
Definition: ald_uart.h:173
ald_uart_recv_by_it
ald_status_t ald_uart_recv_by_it(uart_handle_t *hperh, uint8_t *buf, uint16_t size)
Receives an amount of data in non blocking mode.
Definition: ald_uart.c:697
UART_IF_TFEMPTY
Definition: ald_uart.h:345
uart_word_length_t
uart_word_length_t
UART word length.
Definition: ald_uart.h:83
UART_ABRMOD_1_TO_0
Definition: ald_uart.h:269
UART_ERROR_NONE
Definition: ald_uart.h:147
uart_handle_s::hdmatx
dma_handle_t hdmatx
Definition: ald_uart.h:180
it_status_t
enum flag_status_t it_status_t
UART_IF_RFUERR
Definition: ald_uart.h:342
UART_IT_TFOVER
Definition: ald_uart.h:323
ald_uart_recv_by_dma
ald_status_t ald_uart_recv_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
Receives an amount of data in non blocking mode.
Definition: ald_uart.c:846
ald_uart_send
ald_status_t ald_uart_send(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Sends an amount of data in blocking mode.
Definition: ald_uart.c:488
ald_uart_send_by_dma
ald_status_t ald_uart_send_by_dma(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
Sends an amount of data in non blocking mode.
Definition: ald_uart.c:766
SCARD_RETRY_CNT7
Definition: ald_uart.h:223
uart_handle_s::init
uart_init_t init
Definition: ald_uart.h:172
UART_STATUS_RSBUSY
Definition: ald_uart.h:290
UART_IT_EOB
Definition: ald_uart.h:314
UART_MODE_RS485
Definition: ald_uart.h:116
uart_init_t::mode
uart_mode_t mode
Definition: ald_uart.h:163
UART_STOP_BITS_1
Definition: ald_uart.h:94
UART_STATUS_TFEMPTY
Definition: ald_uart.h:298
LIN_BREAK_LEN_11B
Definition: ald_uart.h:242
uart_state_t
uart_state_t
ALD UART state.
Definition: ald_uart.h:132
UART_IT_RXTO
Definition: ald_uart.h:311
ald_uart_reset
void ald_uart_reset(uart_handle_t *hperh)
Reset UART peripheral.
Definition: ald_uart.c:303
SCARD_CLOCK_DIV6
Definition: ald_uart.h:209
uart_rs485_config_t::addr
uint8_t addr
Definition: ald_uart.h:199
lock_state_t
lock_state_t
Definition: type.h:58
uart_scard_config_t::clk_out
type_func_t clk_out
Definition: ald_uart.h:234
UART_ABRMOD_0_TO_1
Definition: ald_uart.h:271
uart_parity_t
uart_parity_t
UART parity.
Definition: ald_uart.h:103
ald_dma.h
DMA module Library.
UART_PARITY_ODD
Definition: ald_uart.h:105
uart_scard_config_t::block_len
uint8_t block_len
Definition: ald_uart.h:230
UART_STATUS_FERR
Definition: ald_uart.h:287
UART_IF_DCTS
Definition: ald_uart.h:333
UART_ERROR_NE
Definition: ald_uart.h:149
UART_STATE_RESET
Definition: ald_uart.h:133
ald_uart_rs485_send_addr
ald_status_t ald_uart_rs485_send_addr(uart_handle_t *hperh, uint16_t addr, uint32_t timeout)
Send address in RS485 mode.
Definition: ald_uart.c:1287
ald_uart_recv_n_lock
ald_status_t ald_uart_recv_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Receives an amount of data in blocking mode. Don&#39;t care about device lock. This is for RTOS...
Definition: ald_uart.c:626
UART_IF_RXTO
Definition: ald_uart.h:334
uart_handle_s::perh
UART_TypeDef * perh
Definition: ald_uart.h:171
ald_uart_send_n_lock
ald_status_t ald_uart_send_n_lock(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Sends an amount of data in blocking mode. Don&#39;t care about device lock. This is for RTOS...
Definition: ald_uart.c:582
UART_IT_TFTH
Definition: ald_uart.h:321
uart_handle_s::rx_size
uint16_t rx_size
Definition: ald_uart.h:177
UART_STATE_BUSY_TX_RX
Definition: ald_uart.h:138
UART_ERROR_ORE
Definition: ald_uart.h:151
ald_uart_lin_detect_break_len_config
void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len)
Configure the length of break frame to be detect.
Definition: ald_uart.c:1250
UART_DMA_REQ_TX
Definition: ald_uart.h:278
ald_uart_get_flag_status
flag_status_t ald_uart_get_flag_status(uart_handle_t *hperh, uart_flag_t flag)
Get the status of UART interrupt flag.
Definition: ald_uart.c:1365
UART_STATE_BUSY
Definition: ald_uart.h:135
ald_uart_dma_stop
ald_status_t ald_uart_dma_stop(uart_handle_t *hperh)
Stops the DMA Transfer.
Definition: ald_uart.c:948
ald_uart_init
void ald_uart_init(uart_handle_t *hperh)
Initializes the UARTx according to the specified parameters in the uart_handle_t. ...
Definition: ald_uart.c:331
uart_init_t::word_length
uart_word_length_t word_length
Definition: ald_uart.h:160
UART_RXFIFO_14BYTE
Definition: ald_uart.h:262
UART_STATUS_RFTH
Definition: ald_uart.h:291
UART_IT_RFTH
Definition: ald_uart.h:316
uart_status_t
uart_status_t
UART status types.
Definition: ald_uart.h:285
SCARD_RETRY_CNT0
Definition: ald_uart.h:216
UART_STATUS_BKERR
Definition: ald_uart.h:288
uart_stop_bits_t
uart_stop_bits_t
UART stop bits.
Definition: ald_uart.h:93
scard_retry_t
scard_retry_t
Smart_card Rx/Tx handle retry time.
Definition: ald_uart.h:215
UART_IF_TBC
Definition: ald_uart.h:343
uart_init_t::parity
uart_parity_t parity
Definition: ald_uart.h:162
UART_ERROR_DMA
Definition: ald_uart.h:152
uart_flag_t
uart_flag_t
UART flags types.
Definition: ald_uart.h:329
SCARD_RETRY_CNT6
Definition: ald_uart.h:222
SCARD_RETRY_CNT2
Definition: ald_uart.h:218
UART_ABRMOD_1
Definition: ald_uart.h:270
UART_IT_RFUERR
Definition: ald_uart.h:319
uart_scard_config_t::pt
uint8_t pt
Definition: ald_uart.h:231
UART_DMA_REQ_RX
Definition: ald_uart.h:279
UART_IT_NOISE
Definition: ald_uart.h:315
UART_STATE_ERROR
Definition: ald_uart.h:140
ald_uart_get_state
uart_state_t ald_uart_get_state(uart_handle_t *hperh)
Returns the UART state.
Definition: ald_uart.c:1438
UART_IF_RFFULL
Definition: ald_uart.h:340
UART_WORD_LENGTH_5B
Definition: ald_uart.h:87
ald_uart_dma_req_config
void ald_uart_dma_req_config(uart_handle_t *hperh, uart_dma_req_t req, type_func_t state)
Configure UART DMA request.
Definition: ald_uart.c:1150
UART_TXFIFO_2BYTE
Definition: ald_uart.h:250
UART_IT_ADDRM
Definition: ald_uart.h:312
flag_status_t
flag_status_t
Definition: type.h:37
uart_rxfifo_t
uart_rxfifo_t
UART RXFIFO size.
Definition: ald_uart.h:258
ald_uart_irq_handler
void ald_uart_irq_handler(uart_handle_t *hperh)
This function handles UART interrupt request.
Definition: ald_uart.c:964
uart_lin_break_detect_irq
void uart_lin_break_detect_irq(uart_handle_t *hperh, type_func_t status)
Enable/Disable break signal detect interrup.
Definition: ald_uart.c:1212
UART_STATUS_RFOERR
Definition: ald_uart.h:294
ald_uart_lin_send_break
void ald_uart_lin_send_break(uart_handle_t *hperh)
request to send a frame of break.
Definition: ald_uart.c:1231
UART_IF_EOB
Definition: ald_uart.h:337
UART_MODE_UART
Definition: ald_uart.h:113
UART_IF_LINBK
Definition: ald_uart.h:336
uart_handle_s::rx_count
uint16_t rx_count
Definition: ald_uart.h:178
trng_handle_s::state
trng_state_t state
Definition: ald_trng.h:115
uart_rs485_config_t::normal
type_func_t normal
Definition: ald_uart.h:196
ald_uart_recv
ald_status_t ald_uart_recv(uart_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
Receives an amount of data in blocking mode.
Definition: ald_uart.c:537
UART_STATUS_CTSSTA
Definition: ald_uart.h:289
uart_scard_config_t::retry
scard_retry_t retry
Definition: ald_uart.h:232
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
LIN_BREAK_LEN_10B
Definition: ald_uart.h:241
uart_handle_s::rx_buf
uint8_t * rx_buf
Definition: ald_uart.h:176
UART_PARITY_NONE
Definition: ald_uart.h:104
uart_handle_s::tx_size
uint16_t tx_size
Definition: ald_uart.h:174
uart_handle_s::hdmarx
dma_handle_t hdmarx
Definition: ald_uart.h:181
UART_IT_RFOERR
Definition: ald_uart.h:318
UART_STOP_BITS_2
Definition: ald_uart.h:95
uart_handle_s::error_cbk
void(* error_cbk)(struct uart_handle_s *arg)
Definition: ald_uart.h:189
SCARD_RETRY_CNT1
Definition: ald_uart.h:217
UART_STOP_BITS_0_5
Definition: ald_uart.h:96
UART_IF_TFOVER
Definition: ald_uart.h:346
UART_WORD_LENGTH_7B
Definition: ald_uart.h:85
uart_rs485_config_t::dir
type_func_t dir
Definition: ald_uart.h:197
SCARD_CLOCK_DIV4
Definition: ald_uart.h:208
uart_scard_config_t
UART Smart card configure structure definition.
Definition: ald_uart.h:229
UART_IF_NOISE
Definition: ald_uart.h:338
ald_uart_rs485_config
void ald_uart_rs485_config(uart_handle_t *hperh, uart_rs485_config_t *config)
Configure the RS485 mode according to the specified parameters in the uart_rs485_config_t.
Definition: ald_uart.c:392
UART_STATUS_RFUERR
Definition: ald_uart.h:295
UART_TXFIFO_EMPTY
Definition: ald_uart.h:249
UART_STATUS_TFFULL
Definition: ald_uart.h:299
SCARD_RETRY_CNT3
Definition: ald_uart.h:219
uart_handle_s::tx_count
uint16_t tx_count
Definition: ald_uart.h:175
UART_IF_ABEND
Definition: ald_uart.h:331
UART_STATE_BUSY_RX
Definition: ald_uart.h:137
UART_STATUS_PERR
Definition: ald_uart.h:286
UART_IT_ABEND
Definition: ald_uart.h:308
uart_scard_config_t::clk_div
scard_clk_div_t clk_div
Definition: ald_uart.h:233


ALD User Manual: D:/svn/src/ald_usb.c Source File

  • D:
  • svn
  • src
ald_usb.c
Go to the documentation of this file.
1
17 #include "ald_usb.h"
18 #include "ald_syscfg.h"
19
28 #ifdef ALD_USB
29
42 uint32_t ald_usb_frame_number_get(void)
43 {
44 return USB0->FRAME;
45 }
46
52 void ald_usb_otg_session_request(bool start)
53 {
54 if (start)
55 USB0->DEVCTL |= USB_DEVCTL_SESSION;
56 else
57 USB0->DEVCTL &= ~(USB_DEVCTL_SESSION);
58 }
59
64 uint32_t ald_usb_mode_get(void)
65 {
66 return USB0->DEVCTL & (USB_DEVCTL_DEV | USB_DEVCTL_HOST
67 | USB_DEVCTL_SESSION | USB_DEVCTL_VBUS_M);
68 }
69
75 void ald_usb_high_speed_enable(bool enable)
76 {
77 if (enable)
78 USB0->POWER |= USB_POWER_HS_EN;
79 else
80 USB0->POWER &= ~(USB_POWER_HS_EN);
81 }
82
87 uint32_t ald_usb_device_speed_get(void)
88 {
89 if (USB0->POWER & USB_POWER_HS_EN)
90 return USB_HIGH_SPEED;
91
92 return USB_FULL_SPEED;
93 }
94
99 uint32_t ald_usb_num_ep_get( void)
100 {
101 return NUM_USB_EP;
102 }
103
108 void ald_usb_control_reset(void)
109 {
110 ald_rmu_reset_periperal(RMU_PERH_USB);
111 }
112
117 void ald_usb_clock_output(void)
118 {
119 SYSCFG_UNLOCK();
120 SYSCFG->TESTKEY = 0x5A962814;
121 SYSCFG->TESTKEY = 0xE7CB69A5;
122 SYSCFG->USBTEST = 0x43;
123
124 return;
125 }
126
133 int ald_usb_eye_diagram_start(uint8_t *buf, uint16_t len)
134 {
135 if (len < 53)
136 return -1;
137
138 ald_usb_ep_data_put(0, buf, 53);
139 USB0->TEST = 0x08 | 0x90;
140 ald_delay_ms(20);
141 USB0->CSR0L = USB_CSRL0_TXRDY;
142
143 return 0;
144 }
158 uint8_t ald_usb_dev_get_addr(void)
159 {
160 return USB0->FADDR;
161 }
162
168 void ald_usb_dev_set_addr(uint8_t addr)
169 {
170 USB0->FADDR = addr;
171 }
172
177 void ald_usb_dev_connect(void)
178 {
179 USB0->POWER |= USB_POWER_SOFTCONN;
180 }
181
186 void ald_usb_dev_disconnect(void)
187 {
188 USB0->POWER &= ~(USB_POWER_SOFTCONN);
189 }
190
198 void ald_usb_dev_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t flags)
199 {
200 uint32_t tmp = 0;
201
202 if (flags & USB_EP_DEV_IN) {
203 USB0->CSR[ep_idx - 1].TXxMAXP = p_max;
204 if (flags & USB_EP_AUTO_SET)
205 tmp |= USB_TXCSRH1_AUTOSET;
206 if ((flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC)
207 tmp |= USB_TXCSRH1_ISO;
208
209 USB0->CSR[ep_idx - 1].TXxCSRH = (uint8_t)tmp;
210 USB0->CSR[ep_idx - 1].TXxCSRL = USB_TXCSRL1_CLRDT;
211 }
212 else {
213 USB0->CSR[ep_idx - 1].RXxMAXP = p_max;
214 if (flags & USB_EP_AUTO_CLEAR)
215 tmp = USB_RXCSRH1_AUTOCL;
216 if (flags & USB_EP_DIS_NYET)
217 tmp |= USB_RXCSRH1_DISNYET;
218
219 if ((flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC)
220 tmp |= USB_RXCSRH1_ISO;
221
222 USB0->CSR[ep_idx - 1].RXxCSRH = (uint8_t)tmp;
223 USB0->CSR[ep_idx - 1].RXxCSRL = USB_RXCSRL1_CLRDT;
224 }
225 }
226
234 void ald_usb_dev_ep_get_config(uint32_t ep_idx, uint32_t *p_max, uint32_t *flags)
235 {
236 uint32_t tmp;
237
238 if (*flags & USB_EP_DEV_IN) {
239 *flags = USB_EP_DEV_IN;
240 *p_max = (uint32_t)USB0->CSR[ep_idx - 1].TXxMAXP;
241 tmp = (uint32_t)USB0->CSR[ep_idx - 1].TXxCSRH;
242
243 if (tmp & USB_TXCSRH1_AUTOSET)
244 *flags |= USB_EP_AUTO_SET;
245 if (tmp & USB_TXCSRH1_ISO)
246 *flags |= USB_EP_MODE_ISOC;
247 else
248 *flags |= USB_EP_MODE_BULK;
249 }
250 else {
251 *flags = USB_EP_DEV_OUT;
252 *p_max = (uint32_t)USB0->CSR[ep_idx - 1].RXxMAXP;
253 tmp = (uint32_t)USB0->CSR[ep_idx - 1].RXxCSRH;
254
255 if (tmp & USB_RXCSRH1_AUTOCL)
256 *flags |= USB_EP_AUTO_CLEAR;
257 if (tmp & USB_RXCSRH1_ISO)
258 *flags |= USB_EP_MODE_ISOC;
259 else
260 *flags |= USB_EP_MODE_BULK;
261 }
262 }
263
270 void ald_usb_dev_ep_data_ack(uint32_t ep_idx, bool last)
271 {
272 if (ep_idx == USB_EP_0)
273 USB0->CSR0L = USB_CSRL0_RXRDYC | (last ? USB_CSRL0_DATAEND : 0);
274 else
275 USB0->CSR[ep_idx - 1].RXxCSRL &= ~(USB_RXCSRL1_RXRDY);
276 }
277
284 void ald_usb_dev_ep_stall(uint32_t ep_idx, uint32_t flags)
285 {
286 if (ep_idx == USB_EP_0)
287 USB0->CSR0L |= (USB_CSRL0_STALL | USB_CSRL0_RXRDYC);
288 else if (flags == USB_EP_DEV_IN)
289 USB0->CSR[ep_idx - 1].TXxCSRL |= USB_TXCSRL1_STALL;
290 else
291 USB0->CSR[ep_idx - 1].RXxCSRL |= USB_RXCSRL1_STALL;
292 }
293
300 void ald_usb_dev_ep_stall_clear(uint32_t ep_idx, uint32_t flags)
301 {
302 if (ep_idx == USB_EP_0)
303 USB0->CSR0L &= ~USB_CSRL0_STALLED;
304 else if (flags == USB_EP_DEV_IN) {
305 USB0->CSR[ep_idx - 1].TXxCSRL &= ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED);
306 USB0->CSR[ep_idx - 1].TXxCSRL |= USB_TXCSRL1_CLRDT;
307 }
308 else {
309 USB0->CSR[ep_idx - 1].RXxCSRL &= ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED);
310 USB0->CSR[ep_idx - 1].RXxCSRL |= USB_RXCSRL1_CLRDT;
311 }
312 }
313
320 void ald_usb_dev_ep_status_clear(uint32_t ep_idx, uint32_t flags)
321 {
322 if (ep_idx == USB_EP_0) {
323 if (flags & USB_DEV_EP0_OUT_PKTRDY)
324 USB0->CSR0L |= USB_CSRL0_RXRDYC;
325 if (flags & USB_DEV_EP0_SETUP_END)
326 USB0->CSR0L |= USB_CSRL0_SETENDC;
327 if (flags & USB_DEV_EP0_SENT_STALL)
328 USB0->CSR0L &= ~(USB_DEV_EP0_SENT_STALL);
329 }
330 else {
331 USB0->CSR[ep_idx - 1].TXxCSRL &= ~(flags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN));
332 USB0->CSR[ep_idx - 1].RXxCSRL &= ~((flags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR
333 | USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT);
334 }
335 }
350 uint32_t ald_usb_host_addr_get(uint32_t ep_idx, uint32_t flags)
351 {
352 if (flags & USB_EP_HOST_OUT)
353 return USB0->ADDR[ep_idx].TXxFUNCADDR;
354 else
355 return USB0->ADDR[ep_idx].RXxFUNCADDR;
356 }
357
365 void ald_usb_host_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags)
366 {
367 if (flags & USB_EP_HOST_OUT)
368 USB0->ADDR[ep_idx].TXxFUNCADDR = addr;
369 else
370 USB0->ADDR[ep_idx].RXxFUNCADDR = addr;
371 }
372
382 void ald_usb_host_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t nak_val, uint32_t t_ep, uint32_t flags)
383 {
384 uint32_t tmp;
385
386 if (ep_idx == USB_EP_0) {
387 USB0->NACK = nak_val;
388
389 if (flags & USB_EP_SPEED_HIGH)
390 USB0->TYPE0 = USB_TYPE0_SPEED_HIGH;
391 else if (flags & USB_EP_SPEED_FULL)
392 USB0->TYPE0 = USB_TYPE0_SPEED_FULL;
393 else
394 USB0->TYPE0 = USB_TYPE0_SPEED_LOW;
395 }
396 else {
397 tmp = t_ep;
398
399 if (flags & USB_EP_SPEED_HIGH)
400 tmp |= USB_TXTYPE1_SPEED_HIGH;
401 else if (flags & USB_EP_SPEED_FULL)
402 tmp |= USB_TXTYPE1_SPEED_FULL;
403 else
404 tmp |= USB_TXTYPE1_SPEED_LOW;
405
406 switch (flags & USB_EP_MODE_MASK) {
407 case USB_EP_MODE_BULK:
408 tmp |= USB_TXTYPE1_PROTO_BULK;
409 break;
410
411 case USB_EP_MODE_ISOC:
412 tmp |= USB_TXTYPE1_PROTO_ISOC;
413 break;
414
415 case USB_EP_MODE_INT:
416 tmp |= USB_TXTYPE1_PROTO_INT;
417 break;
418
419 case USB_EP_MODE_CTRL:
420 tmp |= USB_TXTYPE1_PROTO_CTRL;
421 break;
422 }
423
424 if (flags & USB_EP_HOST_OUT) {
425 USB0->CSR[ep_idx - 1].TXxTYPE = tmp;
426 USB0->CSR[ep_idx - 1].TXxINTERVAL = nak_val;
427 USB0->CSR[ep_idx - 1].TXxMAXP = p_max;
428
429 tmp = 0;
430 if (flags & USB_EP_AUTO_SET)
431 tmp |= USB_TXCSRH1_AUTOSET;
432 USB0->CSR[ep_idx - 1].TXxCSRH = (uint8_t)tmp;
433 }
434 else {
435 USB0->CSR[ep_idx - 1].RXxTYPE = tmp;
436 USB0->CSR[ep_idx - 1].RXxINTERVAL = nak_val;
437 USB0->CSR[ep_idx - 1].RXxMAXP = p_max;
438
439 tmp = 0;
440 if (flags & USB_EP_AUTO_CLEAR)
441 tmp |= USB_RXCSRH1_AUTOCL;
442 if (flags & USB_EP_AUTO_REQUEST)
443 tmp |= USB_RXCSRH1_AUTORQ;
444
445 USB0->CSR[ep_idx - 1].RXxCSRH = (uint8_t)tmp;
446 }
447 }
448 }
449
455 void ald_usb_host_ep_data_ack(uint32_t ep_idx)
456 {
457 if (ep_idx == USB_EP_0)
458 USB0->CSR0L &= ~(USB_CSRL0_RXRDY);
459 else
460 USB0->CSR[ep_idx - 1].RXxCSRL &= ~(USB_RXCSRL1_RXRDY);
461 }
462
470 void ald_usb_host_ep_data_toggle(uint32_t ep_idx, bool toggle, uint32_t flags)
471 {
472 uint32_t tmp = 0;
473
474 if (toggle) {
475 if (ep_idx == USB_EP_0)
476 tmp = USB_CSRH0_DT;
477 else if (flags == USB_EP_HOST_IN)
478 tmp = USB_RXCSRH1_DT;
479 else
480 tmp = USB_TXCSRH1_DT;
481 }
482
483 if (ep_idx == USB_EP_0) {
484 USB0->CSR0H = (uint8_t)((USB0->CSR0H & ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) |
485 (tmp | USB_CSRH0_DTWE));
486 }
487 else if (flags == USB_EP_HOST_IN) {
488 USB0->CSR[ep_idx - 1].RXxCSRH = (uint8_t)((USB0->CSR[ep_idx - 1].RXxCSRH &
489 ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) |
490 (tmp | USB_RXCSRH1_DTWE));
491 }
492 else {
493 USB0->CSR[ep_idx - 1].TXxCSRH = (uint8_t)((USB0->CSR[ep_idx - 1].TXxCSRH &
494 ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) |
495 (tmp | USB_TXCSRH1_DTWE));
496 }
497 }
498
505 void ald_usb_host_ep_status_clear(uint32_t ep_idx, uint32_t flags)
506 {
507 if (ep_idx == USB_EP_0) {
508 USB0->CSR0L &= ~flags;
509 }
510 else {
511 USB0->CSR[ep_idx - 1].TXxCSRL &= ~flags;
512 USB0->CSR[ep_idx - 1].RXxCSRL &= ~flags;
513 }
514 }
515
522 uint32_t ald_usb_host_hub_addr_get(uint32_t ep_idx, uint32_t flags)
523 {
524 if (flags & USB_EP_HOST_OUT)
525 return USB0->ADDR[ep_idx].TXxHUBADDR;
526 else
527 return USB0->ADDR[ep_idx].RXxHUBADDR;
528 }
529
537 void ald_usb_host_hub_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags)
538 {
539 if (flags & USB_EP_HOST_OUT)
540 USB0->ADDR[ep_idx].TXxHUBADDR = addr;
541 else
542 USB0->ADDR[ep_idx].RXxHUBADDR = addr;
543
544 if (ep_idx == USB_EP_0) {
545 if (flags & USB_EP_SPEED_FULL)
546 USB0->TYPE0 |= USB_TYPE0_SPEED_FULL;
547 else if (flags & USB_EP_SPEED_HIGH)
548 USB0->TYPE0 |= USB_TYPE0_SPEED_HIGH;
549 else
550 USB0->TYPE0 |= USB_TYPE0_SPEED_LOW;
551 }
552 }
553
558 void ald_usb_host_pwr_disable(void)
559 {
560 return;
561 }
562
567 void ald_usb_host_pwr_enable(void)
568 {
569 return;
570 }
571
577 void ald_usb_host_pwr_config(uint32_t flags)
578 {
579 return;
580 }
581
586 void ald_usb_host_pwr_fault_disable(void)
587 {
588 return;
589 }
590
595 void ald_usb_host_pwr_fault_enable(void)
596 {
597 return;
598 }
599
605 void ald_usb_host_request_in(uint32_t ep_idx)
606 {
607 if (ep_idx == USB_EP_0)
608 USB0->CSR0L = USB_RXCSRL1_REQPKT;
609 else
610 USB0->CSR[ep_idx - 1].RXxCSRL = USB_RXCSRL1_REQPKT;
611 }
612
618 void ald_usb_host_request_in_clear(uint32_t ep_idx)
619 {
620 if (ep_idx == USB_EP_0)
621 USB0->CSR0L &= ~(USB_RXCSRL1_REQPKT);
622 else
623 USB0->CSR[ep_idx - 1].RXxCSRL &= ~(USB_RXCSRL1_REQPKT);
624 }
625
630 void ald_usb_host_request_status(void)
631 {
632 USB0->CSR0L = USB_CSRL0_REQPKT | USB_CSRL0_STATUS;
633 }
634
640 void ald_usb_host_reset(bool start)
641 {
642 if (start)
643 USB0->POWER |= USB_POWER_RESET;
644 else
645 USB0->POWER &= ~(USB_POWER_RESET);
646 }
647
653 void ald_usb_host_resume(bool start)
654 {
655 if (start)
656 USB0->POWER |= USB_POWER_RESUME;
657 else
658 USB0->POWER &= ~(USB_POWER_RESUME);
659 }
660
665 void ald_usb_host_suspend(void)
666 {
667 USB0->POWER |= USB_POWER_SUSPEND;
668 }
669
674 uint32_t ald_usb_host_speed_get(void)
675 {
676 if (USB0->POWER & USB_POWER_HS_M)
677 return USB_HIGH_SPEED;
678
679 if (USB0->DEVCTL & USB_DEVCTL_FSDEV)
680 return USB_FULL_SPEED;
681
682 if (USB0->DEVCTL & USB_DEVCTL_LSDEV)
683 return USB_LOW_SPEED;
684
685 return USB_UNDEF_SPEED;
686 }
687
694 void ald_usb_host_ep_speed_set(uint32_t ep_idx, uint32_t flags)
695 {
696 uint32_t tmp;
697
698 if (flags & USB_EP_SPEED_HIGH)
699 tmp = USB_TYPE0_SPEED_HIGH;
700 else if (flags & USB_EP_SPEED_FULL)
701 tmp = USB_TYPE0_SPEED_FULL;
702 else
703 tmp = USB_TYPE0_SPEED_LOW;
704
705 if (ep_idx == USB_EP_0)
706 USB0->TYPE0 |= tmp;
707 else if (flags & USB_EP_HOST_OUT)
708 USB0->CSR[ep_idx - 1].TXxTYPE |= tmp;
709 else
710 USB0->CSR[ep_idx - 1].RXxTYPE |= tmp;
711 }
712
719 void ald_usb_host_ep_ping(uint32_t ep_idx, bool enable)
720 {
721 if (enable)
722 USB0->CSR0H &= ~(USB_CSRH0_DISPING);
723 else
724 USB0->CSR0H |= USB_CSRH0_DISPING;
725 }
739 uint32_t ald_usb_ep_data_avail(uint32_t ep_idx)
740 {
741 if (ep_idx == USB_EP_0) {
742 if ((USB0->CSR0L & USB_CSRL0_RXRDY) == 0)
743 return 0;
744
745 return USB0->COUNT0;
746 }
747 else {
748 if ((USB0->CSR[ep_idx - 1].RXxCSRL & USB_CSRL0_RXRDY) == 0)
749 return 0;
750
751 return USB0->CSR[ep_idx - 1].RXxCOUNT;
752 }
753 }
754
762 int32_t ald_usb_ep_data_get(uint32_t ep_idx, uint8_t *data, uint32_t *size)
763 {
764 uint32_t i;
765
766 if (ep_idx == USB_EP_0) {
767 if ((USB0->CSR0L & USB_CSRL0_RXRDY) == 0) {
768 *size = 0;
769 return -1;
770 }
771 i = USB0->COUNT0;
772 }
773 else {
774 if ((USB0->CSR[ep_idx - 1].RXxCSRL & USB_CSRL0_RXRDY) == 0) {
775 *size = 0;
776 return -1;
777 }
778 i = USB0->CSR[ep_idx - 1].RXxCOUNT;
779 }
780
781 i = (i < *size) ? i : *size;
782 *size = i;
783
784 for (; i > 0; i--)
785 *data++ = USB0->FIFO[ep_idx].Byte[0];
786
787 return 0;
788 }
789
797 int32_t ald_usb_ep_data_put(uint32_t ep_idx, uint8_t *data, uint32_t size)
798 {
799 if (ep_idx == USB_EP_0) {
800 if (USB0->CSR0L & USB_CSRL0_TXRDY)
801 return -1;
802 }
803 else {
804 if (USB0->CSR[ep_idx - 1].TXxCSRL & USB_TXCSRL1_TXRDY)
805 return -1;
806 }
807
808 for (; size > 0; size--)
809 USB0->FIFO[ep_idx].Byte[0] = *data++;
810
811 return 0;
812 }
813
820 int32_t ald_usb_ep_data_send(uint32_t ep_idx, uint32_t tx_type)
821 {
822 uint32_t tmp;
823
824 if (ep_idx == USB_EP_0) {
825 if (USB0->CSR0L & USB_CSRL0_TXRDY)
826 return -1;
827
828 tmp = tx_type & 0xff;
829 USB0->CSR0L = tmp;
830 }
831 else {
832 if (USB0->CSR[ep_idx - 1].TXxCSRL & USB_TXCSRL1_TXRDY)
833 return -1;
834
835 tmp = (tx_type >> 8) & 0xff;
836 USB0->CSR[ep_idx - 1].TXxCSRL = tmp;
837 }
838
839 return 0;
840 }
841
848 void ald_usb_ep_data_toggle_clear(uint32_t ep_idx, uint32_t flags)
849 {
850 if (flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN))
851 USB0->CSR[ep_idx - 1].TXxCSRL |= USB_TXCSRL1_CLRDT;
852 else
853 USB0->CSR[ep_idx - 1].RXxCSRL |= USB_RXCSRL1_CLRDT;
854 }
855
862 void ald_usb_ep_req_packet_count(uint32_t ep_idx, uint32_t count)
863 {
864 USB0->EP_RQPKTCOUNT[ep_idx - 1] = count;
865 }
866
872 uint32_t ald_usb_ep_status(uint32_t ep_idx)
873 {
874 uint32_t status;
875
876 if (ep_idx == USB_EP_0) {
877 status = USB0->CSR0L;
878 status |= (USB0->CSR0H) << USB_RX_EPSTATUS_SHIFT;
879 }
880 else {
881 status = USB0->CSR[ep_idx - 1].TXxCSRL;
882 status |= USB0->CSR[ep_idx - 1].TXxCSRH << 8;
883 status |= USB0->CSR[ep_idx - 1].RXxCSRL << 16;
884 status |= USB0->CSR[ep_idx - 1].RXxCSRH << 24;
885 }
886
887 return status;
888 }
889
897 void ald_usb_ep_dma_config(uint32_t ep_idx, uint32_t flag, type_func_t en)
898 {
899 if (ep_idx == USB_EP_0)
900 return;
901
902 if (en) {
903 switch (flag) {
904 case USB_DMA_EP_CFG_TX:
905 USB0->CSR[ep_idx - 1].TXxCSRH |= USB_DMA_EP_TX_MSK;
906 break;
907 case USB_DMA_EP_CFG_RX_DEV:
908 USB0->CSR[ep_idx - 1].RXxCSRH |= USB_DMA_EP_RX_DEV_MSK;
909 break;
910 case USB_DMA_EP_CFG_RX_HOST:
911 USB0->CSR[ep_idx - 1].RXxCSRH |= USB_DMA_EP_RX_HOST_MSK;
912 break;
913 default:
914 break;
915 }
916 }
917 else {
918 switch (flag) {
919 case USB_DMA_EP_CFG_TX:
920 USB0->CSR[ep_idx - 1].TXxCSRH &= ~(USB_DMA_EP_TX_MSK);
921 break;
922 case USB_DMA_EP_CFG_RX_DEV:
923 USB0->CSR[ep_idx - 1].RXxCSRH &= ~(USB_DMA_EP_RX_DEV_MSK);
924 break;
925 case USB_DMA_EP_CFG_RX_HOST:
926 USB0->CSR[ep_idx - 1].RXxCSRH &= ~(USB_DMA_EP_RX_HOST_MSK);
927 break;
928 default:
929 break;
930 }
931 }
932
933 return;
934 }
948 uint32_t ald_usb_fifo_addr_get(uint32_t ep_idx)
949 {
950 return (uint32_t)&USB0->FIFO[ep_idx].Word;
951 }
952
961 void ald_usb_fifo_config_get(uint32_t ep_idx, uint32_t *addr, uint32_t *size, uint32_t flags)
962 {
963 uint32_t tmp = USB0->INDEX;
964
965 USB0->INDEX = ep_idx;
966
967 if (flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) {
968 *addr = (USB0->TXFIFOADD << 3);
969 *size = (USB0->TXFIFOSIZE & 0xF);
970 }
971 else {
972 *addr = (USB0->RXFIFOADD << 3);
973 *size = (USB0->RXFIFOSIZE & 0xF);
974 }
975
976 USB0->INDEX = tmp;
977 return;
978 }
979
988 void ald_usb_fifo_config_set(uint32_t ep_idx, uint32_t addr, uint32_t size, uint32_t flags)
989 {
990 uint32_t tmp = USB0->INDEX;
991
992 USB0->INDEX = ep_idx;
993
994 if (flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) {
995 USB0->TXFIFOADD = (addr >> 3);
996 USB0->TXFIFOSIZE = (size & 0xF);
997 }
998 else {
999 USB0->RXFIFOADD = (addr >> 3);
1000 USB0->RXFIFOSIZE = (size & 0xF);
1001 }
1002
1003 USB0->INDEX = tmp;
1004 return;
1005 }
1006
1013 void ald_usb_fifo_flush(uint32_t ep_idx, uint32_t flags)
1014 {
1015 if (ep_idx == USB_EP_0) {
1016 if ((USB0->CSR0L & (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0)
1017 USB0->CSR0H |= USB_CSRH0_FLUSH;
1018 }
1019 else {
1020 if (flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) {
1021 if (USB0->CSR[ep_idx - 1].TXxCSRL & USB_TXCSRL1_TXRDY)
1022 USB0->CSR[ep_idx - 1].TXxCSRL |= USB_TXCSRL1_FLUSH;
1023 }
1024 else {
1025 if (USB0->CSR[ep_idx - 1].RXxCSRL & USB_RXCSRL1_RXRDY)
1026 USB0->CSR[ep_idx - 1].RXxCSRL |= USB_RXCSRL1_FLUSH;
1027 }
1028 }
1029 }
1043 void ald_usb_int_disable(uint32_t flags)
1044 {
1045 if (flags & USB_INTCTRL_STATUS)
1046 USB0->USBIE &= ~(flags & USB_INTCTRL_STATUS);
1047 }
1048
1054 void ald_usb_int_enable(uint32_t flags)
1055 {
1056 if (flags & USB_INTCTRL_STATUS)
1057 USB0->USBIE |= flags ;
1058 }
1059
1064 uint32_t ald_usb_int_status_get(void)
1065 {
1066 return USB0->USBIS;
1067 }
1068
1074 void ald_usb_int_disable_ep(uint32_t flags)
1075 {
1076 USB0->TXIE &= ~(flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0));
1077 USB0->RXIE &= ~((flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> USB_INTEP_RX_SHIFT);
1078 }
1079
1085 void ald_usb_int_enable_ep(uint32_t flags)
1086 {
1087
1088 USB0->TXIE |= flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0);
1089 USB0->RXIE |= ((flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> USB_INTEP_RX_SHIFT);
1090 }
1091
1096 uint32_t ald_usb_int_status_ep_get(void)
1097 {
1098 uint32_t status;
1099
1100 status = USB0->TXIS;
1101 status |= (USB0->RXIS << USB_INTEP_RX_SHIFT);
1102
1103 return status;
1104 }
1105
1110 void ald_usb_int_register(void)
1111 {
1112 ald_mcu_irq_config(USB_INT_IRQn, 2, 2, ENABLE);
1113
1114 }
1115
1120 void ald_usb_int_unregister(void)
1121 {
1122 ald_mcu_irq_config(USB_INT_IRQn, 2, 2, DISABLE);
1123 }
1124
1129 uint32_t ald_usb_int_num_get(void)
1130 {
1131 return USB_INT_IRQn;
1132 }
1149 void ald_usb_dma_channel_config(uint8_t ch, uint32_t addr, uint32_t count, uint32_t ctrl)
1150 {
1151 USB0->DMA_CH[ch].DMA_ADDR = addr;
1152 USB0->DMA_CH[ch].DMA_COUNT = count;
1153 USB0->DMA_CH[ch].DMA_CNTL = ctrl;
1154 return;
1155 }
1156
1162 void ald_usb_dma_mult_recv_start(uint32_t ep_idx)
1163 {
1164 USB0->CSR[ep_idx - 1].RXxCSRH &= ~(USB_RXCSRH1_DMAMOD);
1165 return;
1166 }
1167
1168
1174 void ald_usb_dma_channel_start(uint8_t ch)
1175 {
1176 USB0->DMA_CH[ch].DMA_CNTL |= 0x1;
1177 return;
1178 }
1179
1185 void ald_usb_dma_channel_stop(uint8_t ch)
1186 {
1187 USB0->DMA_CH[ch].DMA_CNTL &= (uint32_t)(~0x1);
1188 return;
1189 }
1190
1195 uint32_t ald_usb_dma_get_interrupt_flag(void)
1196 {
1197 return USB0->DMA_INTR;
1198 }
1199
1205 uint32_t ald_usb_dma_get_channel_error(uint8_t ch)
1206 {
1207 if (USB0->DMA_CH[ch].DMA_CNTL & USB_DMA_CH_ERR_MSK)
1208 return 1;
1209
1210 return 0;
1211 }
1212
1218 void ald_usb_dma_clear_channel_error(uint8_t ch)
1219 {
1220 USB0->DMA_CH[ch].DMA_CNTL &= ~(USB_DMA_CH_ERR_MSK);
1221 }
1236 void ald_usb_host_lpm_send(uint32_t addr, uint32_t ep_idx)
1237 {
1238 uint32_t tmp;
1239
1240 USB0->LPM_FADDR = addr;
1241
1242 tmp = USB0->LPM_ATTR & ~(USB_LPMATTR_ENDPT_M);
1243 tmp |= ep_idx << USB_LPMATTR_ENDPT_S;
1244
1245 USB0->LPM_ATTR = tmp;
1246 USB0->LPM_CNTRL |= USB_LPMCNTRL_LPMXMT;
1247 }
1248
1255 void ald_usb_host_lpm_config(uint32_t resume_time, uint32_t config)
1256 {
1257 uint32_t tmp;
1258
1259 tmp = USB0->LPM_ATTR;
1260 tmp &= ~(USB_LPMATTR_HIRD_M);
1261 tmp |= ((((resume_time - 50) / 75) & 0xF) << USB_LPMATTR_HIRD_S);
1262 tmp |= config;
1263 USB0->LPM_ATTR = tmp;
1264 }
1265
1270 uint32_t ald_usb_lpm_remote_wake_is_enable(void)
1271 {
1272 if (USB0->LPM_ATTR & USB_LPMATTR_RMTWAK)
1273 return 1;
1274
1275 return 0;
1276 }
1277
1282 void ald_usb_host_lpm_resume(void)
1283 {
1284 USB0->LPM_CNTRL |= USB_LPMCNTRL_LPMRES;
1285 }
1286
1291 void ald_usb_dev_lpm_remote_wake(void)
1292 {
1293 USB0->LPM_CNTRL |= USB_LPMCNTRL_LPMRES;
1294 }
1295
1300 void ald_usb_dev_lpm_config(uint32_t config)
1301 {
1302 USB0->LPM_CNTRL = config;
1303 }
1304
1309 void ald_usb_dev_lpm_enable(void)
1310 {
1311 USB0->LPM_CNTRL |= (USB_LPMCNTRL_LPMXMT | USB_LPMCNTRL_ENABLE);
1312 }
1313
1318 void ald_usb_dev_lpm_disable(void)
1319 {
1320 USB0->LPM_CNTRL &= ~(USB_LPMCNTRL_LPMXMT);
1321 }
1322
1327 uint32_t ald_usb_lpm_link_status_get(void)
1328 {
1329 return (USB0->LPM_ATTR & USB_LPMATTR_LS_M);
1330 }
1331
1336 uint32_t ald_usb_lpm_ep_get(void)
1337 {
1338 uint32_t tmp;
1339
1340 tmp = USB0->LPM_ATTR;
1341 tmp &= USB_LPMATTR_ENDPT_M;
1342 tmp = tmp >> USB_LPMATTR_ENDPT_S;
1343
1344 return tmp;
1345 }
1346
1351 uint32_t ald_usb_lpm_int_status_get(void)
1352 {
1353 return USB0->LPM_INTR;
1354 }
1355
1360 void ald_usb_lpm_int_disable(uint32_t ints)
1361 {
1362 USB0->LPM_INTREN &= ~ints;
1363 }
1364
1369 void ald_usb_lpm_int_enable(uint32_t ints)
1370 {
1371 USB0->LPM_INTREN |= ints;
1372 }
1380 #endif
1381
ald_usb_dev_set_addr
void ald_usb_dev_set_addr(uint8_t addr)
Sets the address.
Definition: ald_usb.c:168
ald_usb_int_status_get
uint32_t ald_usb_int_status_get(void)
Gets the status of the interrupt.
Definition: ald_usb.c:1064
USB_HIGH_SPEED
#define USB_HIGH_SPEED
Definition: ald_usb.h:242
USB_EP_HOST_IN
#define USB_EP_HOST_IN
Definition: ald_usb.h:311
ald_usb_ep_data_send
int32_t ald_usb_ep_data_send(uint32_t ep_idx, uint32_t tx_type)
Send data.
Definition: ald_usb.c:820
ENABLE
Definition: type.h:49
USB_POWER_SOFTCONN
#define USB_POWER_SOFTCONN
Definition: ald_usb.h:42
ald_usb_host_request_in_clear
void ald_usb_host_request_in_clear(uint32_t ep_idx)
Clear the status of request IN.
Definition: ald_usb.c:618
ald_usb_host_pwr_fault_disable
void ald_usb_host_pwr_fault_disable(void)
Disable the fault parameters of the power.
Definition: ald_usb.c:586
USB_RXCSRH1_DMAMOD
#define USB_RXCSRH1_DMAMOD
Definition: ald_usb.h:68
ald_usb_high_speed_enable
void ald_usb_high_speed_enable(bool enable)
Enable/Disable the high mode.
Definition: ald_usb.c:75
ald_usb_host_speed_get
uint32_t ald_usb_host_speed_get(void)
Gets the device&#39;s speed.
Definition: ald_usb.c:674
USB_INTEP_HOST_IN
#define USB_INTEP_HOST_IN
Definition: ald_usb.h:171
USB_EP_MODE_INT
#define USB_EP_MODE_INT
Definition: ald_usb.h:305
USB_EP_MODE_CTRL
#define USB_EP_MODE_CTRL
Definition: ald_usb.h:306
USB_CSRL0_RXRDYC
#define USB_CSRL0_RXRDYC
Definition: ald_usb.h:113
USB_POWER_HS_EN
#define USB_POWER_HS_EN
Definition: ald_usb.h:43
ald_usb_frame_number_get
uint32_t ald_usb_frame_number_get(void)
Gets the number of current frame.
Definition: ald_usb.c:42
ald_usb_host_pwr_fault_enable
void ald_usb_host_pwr_fault_enable(void)
Enable the fault parameters of the power.
Definition: ald_usb.c:595
USB_DEVCTL_DEV
#define USB_DEVCTL_DEV
Definition: ald_usb.h:50
USB_DEVCTL_LSDEV
#define USB_DEVCTL_LSDEV
Definition: ald_usb.h:52
USB_CSRL0_STALLED
#define USB_CSRL0_STALLED
Definition: ald_usb.h:120
ald_usb_host_ep_speed_set
void ald_usb_host_ep_speed_set(uint32_t ep_idx, uint32_t flags)
Sets the endpoint speed.
Definition: ald_usb.c:694
ald_usb_int_status_ep_get
uint32_t ald_usb_int_status_ep_get(void)
Gets the ststus of the endpoint interrupt.
Definition: ald_usb.c:1096
USB_EP_DEV_IN
#define USB_EP_DEV_IN
Definition: ald_usb.h:313
USB_LPMATTR_RMTWAK
#define USB_LPMATTR_RMTWAK
Definition: ald_usb.h:143
USB_TYPE0_SPEED_HIGH
#define USB_TYPE0_SPEED_HIGH
Definition: ald_usb.h:125
USB_RXCSRL1_STALL
#define USB_RXCSRL1_STALL
Definition: ald_usb.h:100
SYSCFG_UNLOCK
#define SYSCFG_UNLOCK()
Definition: ald_syscfg.h:40
ald_usb_device_speed_get
uint32_t ald_usb_device_speed_get(void)
Gets the speed of the device.
Definition: ald_usb.c:87
ald_usb_clock_output
void ald_usb_clock_output(void)
Output USB clock via PA15, 60MHz/256=234.375KHz.
Definition: ald_usb.c:117
USB_TXTYPE1_PROTO_BULK
#define USB_TXTYPE1_PROTO_BULK
Definition: ald_usb.h:137
USB_EP_DEV_OUT
#define USB_EP_DEV_OUT
Definition: ald_usb.h:314
type_func_t
type_func_t
Definition: type.h:47
ald_usb_dev_ep_data_ack
void ald_usb_dev_ep_data_ack(uint32_t ep_idx, bool last)
Acknowledge the data from the host.
Definition: ald_usb.c:270
ald_usb_dma_get_interrupt_flag
uint32_t ald_usb_dma_get_interrupt_flag(void)
Gets flags of the interrupt.
Definition: ald_usb.c:1195
ald_usb_otg_session_request
void ald_usb_otg_session_request(bool start)
Request the session.
Definition: ald_usb.c:52
DISABLE
Definition: type.h:48
USB_TYPE0_SPEED_FULL
#define USB_TYPE0_SPEED_FULL
Definition: ald_usb.h:126
ald_usb_host_ep_data_toggle
void ald_usb_host_ep_data_toggle(uint32_t ep_idx, bool toggle, uint32_t flags)
Toggle the data in host mode.
Definition: ald_usb.c:470
USB_EP_HOST_OUT
#define USB_EP_HOST_OUT
Definition: ald_usb.h:312
ald_usb_mode_get
uint32_t ald_usb_mode_get(void)
Gets the mode.
Definition: ald_usb.c:64
USB_EP_0
#define USB_EP_0
Definition: ald_usb.h:347
USB_DMA_CH_ERR_MSK
#define USB_DMA_CH_ERR_MSK
Definition: ald_usb.h:432
ald_usb_int_num_get
uint32_t ald_usb_int_num_get(void)
Get USB&#39;s interrupt number.
Definition: ald_usb.c:1129
USB_EP_AUTO_SET
#define USB_EP_AUTO_SET
Definition: ald_usb.h:295
ald_usb_ep_req_packet_count
void ald_usb_ep_req_packet_count(uint32_t ep_idx, uint32_t count)
Sets the size of request data IN.
Definition: ald_usb.c:862
ald_usb_dev_ep_stall_clear
void ald_usb_dev_ep_stall_clear(uint32_t ep_idx, uint32_t flags)
Cancel the stall status.
Definition: ald_usb.c:300
USB_TXCSRL1_TXRDY
#define USB_TXCSRL1_TXRDY
Definition: ald_usb.h:96
ald_usb_host_pwr_config
void ald_usb_host_pwr_config(uint32_t flags)
Configure power in host mode.
Definition: ald_usb.c:577
ald_usb_int_enable
void ald_usb_int_enable(uint32_t flags)
Enable interrupt.
Definition: ald_usb.c:1054
NUM_USB_EP
#define NUM_USB_EP
Definition: ald_usb.h:353
ald_usb_dev_ep_status_clear
void ald_usb_dev_ep_status_clear(uint32_t ep_idx, uint32_t flags)
Clear the status of the endpoint.
Definition: ald_usb.c:320
USB_DMA_EP_RX_DEV_MSK
#define USB_DMA_EP_RX_DEV_MSK
Definition: ald_usb.h:399
USB_LPMATTR_HIRD_S
#define USB_LPMATTR_HIRD_S
Definition: ald_usb.h:148
ald_usb_lpm_int_status_get
uint32_t ald_usb_lpm_int_status_get(void)
Gets the status of the interrupt.
Definition: ald_usb.c:1351
USB_EP_SPEED_HIGH
#define USB_EP_SPEED_HIGH
Definition: ald_usb.h:310
USB_TXCSRL1_STALL
#define USB_TXCSRL1_STALL
Definition: ald_usb.h:90
USB_LPMATTR_ENDPT_M
#define USB_LPMATTR_ENDPT_M
Definition: ald_usb.h:142
ald_usb_host_lpm_send
void ald_usb_host_lpm_send(uint32_t addr, uint32_t ep_idx)
Transmit a LPM transaction in host mode.
Definition: ald_usb.c:1236
ald_usb_host_addr_set
void ald_usb_host_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags)
Sets the device&#39;s address.
Definition: ald_usb.c:365
USB_RXCSRH1_AUTOCL
#define USB_RXCSRH1_AUTOCL
Definition: ald_usb.h:62
USB_RXCSRL1_FLUSH
#define USB_RXCSRL1_FLUSH
Definition: ald_usb.h:102
ald_usb_dev_ep_config
void ald_usb_dev_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t flags)
Configure the endpoint in device mode.
Definition: ald_usb.c:198
USB_RX_EPSTATUS_SHIFT
#define USB_RX_EPSTATUS_SHIFT
Definition: ald_usb.h:409
ald_usb_dma_mult_recv_start
void ald_usb_dma_mult_recv_start(uint32_t ep_idx)
Start multiple receive.
Definition: ald_usb.c:1162
USB_RXCSRL1_REQPKT
#define USB_RXCSRL1_REQPKT
Definition: ald_usb.h:101
USB_CSRL0_STALL
#define USB_CSRL0_STALL
Definition: ald_usb.h:115
ald_usb_dev_lpm_remote_wake
void ald_usb_dev_lpm_remote_wake(void)
Enable remote wakeup in device mode.
Definition: ald_usb.c:1291
USB_FULL_SPEED
#define USB_FULL_SPEED
Definition: ald_usb.h:243
ald_usb_host_ep_data_ack
void ald_usb_host_ep_data_ack(uint32_t ep_idx)
Acknowledge the data in host mode.
Definition: ald_usb.c:455
ald_usb_host_request_status
void ald_usb_host_request_status(void)
Request data IN at endpoint 0.
Definition: ald_usb.c:630
ald_usb_dev_lpm_enable
void ald_usb_dev_lpm_enable(void)
Enable LPM in device mode.
Definition: ald_usb.c:1309
USB_INTEP_RX_SHIFT
#define USB_INTEP_RX_SHIFT
Definition: ald_usb.h:410
USB_LPMCNTRL_LPMXMT
#define USB_LPMCNTRL_LPMXMT
Definition: ald_usb.h:151
USB_DEVCTL_VBUS_M
#define USB_DEVCTL_VBUS_M
Definition: ald_usb.h:53
ald_usb_dev_lpm_disable
void ald_usb_dev_lpm_disable(void)
Disable LPM in device mode.
Definition: ald_usb.c:1318
ald_usb_dev_lpm_config
void ald_usb_dev_lpm_config(uint32_t config)
Enable remote wakeup in device mode.
Definition: ald_usb.c:1300
USB_INTEP_0
#define USB_INTEP_0
Definition: ald_usb.h:239
USB_CSRH0_DTWE
#define USB_CSRH0_DTWE
Definition: ald_usb.h:74
USB_LPMCNTRL_ENABLE
#define USB_LPMCNTRL_ENABLE
Definition: ald_usb.h:152
USB_TXTYPE1_SPEED_FULL
#define USB_TXTYPE1_SPEED_FULL
Definition: ald_usb.h:132
USB_TXCSRL1_FLUSH
#define USB_TXCSRL1_FLUSH
Definition: ald_usb.h:92
USB_CSRL0_RXRDY
#define USB_CSRL0_RXRDY
Definition: ald_usb.h:122
USB_LPMCNTRL_LPMRES
#define USB_LPMCNTRL_LPMRES
Definition: ald_usb.h:150
ald_usb_ep_data_put
int32_t ald_usb_ep_data_put(uint32_t ep_idx, uint8_t *data, uint32_t size)
Puts data to the FIFO.
Definition: ald_usb.c:797
USB_DEV_EP0_OUT_PKTRDY
#define USB_DEV_EP0_OUT_PKTRDY
Definition: ald_usb.h:293
USB_POWER_HS_M
#define USB_POWER_HS_M
Definition: ald_usb.h:44
USB_EP_DIS_NYET
#define USB_EP_DIS_NYET
Definition: ald_usb.h:300
USB_DEV_TX_SENT_STALL
#define USB_DEV_TX_SENT_STALL
Definition: ald_usb.h:285
ald_usb_int_disable_ep
void ald_usb_int_disable_ep(uint32_t flags)
Disable interrupt of the endpoint.
Definition: ald_usb.c:1074
ald_usb_host_lpm_resume
void ald_usb_host_lpm_resume(void)
Initiate a RESUME from the L1 state in host mode.
Definition: ald_usb.c:1282
USB_UNDEF_SPEED
#define USB_UNDEF_SPEED
Definition: ald_usb.h:241
ald_usb_ep_data_toggle_clear
void ald_usb_ep_data_toggle_clear(uint32_t ep_idx, uint32_t flags)
Clear the status of the toggle.
Definition: ald_usb.c:848
ald_usb_ep_dma_config
void ald_usb_ep_dma_config(uint32_t ep_idx, uint32_t flag, type_func_t en)
Configure the endpoint in DMA mode.
Definition: ald_usb.c:897
USB_LPMATTR_HIRD_M
#define USB_LPMATTR_HIRD_M
Definition: ald_usb.h:144
USB_INTCTRL_STATUS
#define USB_INTCTRL_STATUS
Definition: ald_usb.h:156
USB_POWER_RESET
#define USB_POWER_RESET
Definition: ald_usb.h:45
ald_usb_dma_channel_start
void ald_usb_dma_channel_start(uint8_t ch)
Start DMA&#39;s machine.
Definition: ald_usb.c:1174
ald_usb_fifo_config_set
void ald_usb_fifo_config_set(uint32_t ep_idx, uint32_t addr, uint32_t size, uint32_t flags)
Sets the parameters of the FIFO.
Definition: ald_usb.c:988
USB_TXCSRH1_AUTOSET
#define USB_TXCSRH1_AUTOSET
Definition: ald_usb.h:78
ald_mcu_irq_config
void ald_mcu_irq_config(IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, type_func_t status)
Configure interrupt.
Definition: utils.c:375
ald_usb_dma_clear_channel_error
void ald_usb_dma_clear_channel_error(uint8_t ch)
Clear the status of the error.
Definition: ald_usb.c:1218
ald_usb_lpm_ep_get
uint32_t ald_usb_lpm_ep_get(void)
Gets the index of the endpoint.
Definition: ald_usb.c:1336
ald_usb_fifo_addr_get
uint32_t ald_usb_fifo_addr_get(uint32_t ep_idx)
Gets the address of the FIFO.
Definition: ald_usb.c:948
ald_rmu_reset_periperal
void ald_rmu_reset_periperal(rmu_peripheral_t perh)
Reset peripheral device.
Definition: ald_rmu.c:101
USB_CSRH0_DT
#define USB_CSRH0_DT
Definition: ald_usb.h:75
ald_usb_host_reset
void ald_usb_host_reset(bool start)
Reset the USB&#39;s bus.
Definition: ald_usb.c:640
USB_RXCSRH1_DT
#define USB_RXCSRH1_DT
Definition: ald_usb.h:70
USB_DEV_EP0_SETUP_END
#define USB_DEV_EP0_SETUP_END
Definition: ald_usb.h:289
ald_usb_host_resume
void ald_usb_host_resume(bool start)
Resume the devices.
Definition: ald_usb.c:653
USB_TXCSRH1_ISO
#define USB_TXCSRH1_ISO
Definition: ald_usb.h:79
USB_POWER_RESUME
#define USB_POWER_RESUME
Definition: ald_usb.h:46
USB_CSRL0_TXRDY
#define USB_CSRL0_TXRDY
Definition: ald_usb.h:121
ald_usb_ep_data_avail
uint32_t ald_usb_ep_data_avail(uint32_t ep_idx)
Gets the size of the available data.
Definition: ald_usb.c:739
USB_DMA_EP_CFG_TX
#define USB_DMA_EP_CFG_TX
Definition: ald_usb.h:395
USB_RXCSRH1_DISNYET
#define USB_RXCSRH1_DISNYET
Definition: ald_usb.h:66
USB_EP_MODE_MASK
#define USB_EP_MODE_MASK
Definition: ald_usb.h:307
ald_syscfg.h
SYSCFG module driver.
USB_TXCSRH1_DT
#define USB_TXCSRH1_DT
Definition: ald_usb.h:85
USB_RXCSRL1_CLRDT
#define USB_RXCSRL1_CLRDT
Definition: ald_usb.h:98
ald_usb_host_lpm_config
void ald_usb_host_lpm_config(uint32_t resume_time, uint32_t config)
Configure the LPM parameters in host mode.
Definition: ald_usb.c:1255
ald_usb_eye_diagram_start
int ald_usb_eye_diagram_start(uint8_t *buf, uint16_t len)
Starts eye diagram for high-speed host.
Definition: ald_usb.c:133
USB_DMA_EP_RX_HOST_MSK
#define USB_DMA_EP_RX_HOST_MSK
Definition: ald_usb.h:400
ald_usb_host_ep_config
void ald_usb_host_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t nak_val, uint32_t t_ep, uint32_t flags)
Configure the endpoint in host mode.
Definition: ald_usb.c:382
USB_INTEP_HOST_OUT
#define USB_INTEP_HOST_OUT
Definition: ald_usb.h:205
USB_INTEP_DEV_IN
#define USB_INTEP_DEV_IN
Definition: ald_usb.h:222
USB_RXCSRL1_RXRDY
#define USB_RXCSRL1_RXRDY
Definition: ald_usb.h:108
USB_RXCSRH1_DTWE
#define USB_RXCSRH1_DTWE
Definition: ald_usb.h:69
USB_INTEP_DEV_OUT
#define USB_INTEP_DEV_OUT
Definition: ald_usb.h:188
ald_usb_lpm_remote_wake_is_enable
uint32_t ald_usb_lpm_remote_wake_is_enable(void)
Gets status of remote wakeup.
Definition: ald_usb.c:1270
USB_CSRH0_DISPING
#define USB_CSRH0_DISPING
Definition: ald_usb.h:73
USB_DMA_EP_CFG_RX_DEV
#define USB_DMA_EP_CFG_RX_DEV
Definition: ald_usb.h:396
USB_EP_AUTO_CLEAR
#define USB_EP_AUTO_CLEAR
Definition: ald_usb.h:297
USB_TXCSRL1_CLRDT
#define USB_TXCSRL1_CLRDT
Definition: ald_usb.h:88
USB_RXCSRH1_AUTORQ
#define USB_RXCSRH1_AUTORQ
Definition: ald_usb.h:63
USB_DEV_RX_OVERRUN
#define USB_DEV_RX_OVERRUN
Definition: ald_usb.h:279
USB_DEV_TX_UNDERRUN
#define USB_DEV_TX_UNDERRUN
Definition: ald_usb.h:286
USB_EP_AUTO_REQUEST
#define USB_EP_AUTO_REQUEST
Definition: ald_usb.h:296
USB_CSRL0_SETENDC
#define USB_CSRL0_SETENDC
Definition: ald_usb.h:111
ald_usb_dev_ep_get_config
void ald_usb_dev_ep_get_config(uint32_t ep_idx, uint32_t *p_max, uint32_t *flags)
Gets the parameters of the endpoint.
Definition: ald_usb.c:234
USB_DEVCTL_SESSION
#define USB_DEVCTL_SESSION
Definition: ald_usb.h:60
USB_DEVCTL_HOST
#define USB_DEVCTL_HOST
Definition: ald_usb.h:58
USB_TXCSRH1_DTWE
#define USB_TXCSRH1_DTWE
Definition: ald_usb.h:84
USB_TXTYPE1_SPEED_HIGH
#define USB_TXTYPE1_SPEED_HIGH
Definition: ald_usb.h:131
ald_usb_host_ep_status_clear
void ald_usb_host_ep_status_clear(uint32_t ep_idx, uint32_t flags)
Clear the status of endpoint in host mode.
Definition: ald_usb.c:505
ald_usb_int_disable
void ald_usb_int_disable(uint32_t flags)
Disable interrupt.
Definition: ald_usb.c:1043
USB_TXTYPE1_PROTO_INT
#define USB_TXTYPE1_PROTO_INT
Definition: ald_usb.h:138
USB_DEV_RX_DATA_ERROR
#define USB_DEV_RX_DATA_ERROR
Definition: ald_usb.h:278
ald_usb_dev_ep_stall
void ald_usb_dev_ep_stall(uint32_t ep_idx, uint32_t flags)
Stall the endpoint.
Definition: ald_usb.c:284
USB_POWER_SUSPEND
#define USB_POWER_SUSPEND
Definition: ald_usb.h:47
ald_usb.h
Header file of USB module driver.
ald_usb_lpm_int_disable
void ald_usb_lpm_int_disable(uint32_t ints)
Disable the LPM interrupt.
Definition: ald_usb.c:1360
USB_CSRL0_DATAEND
#define USB_CSRL0_DATAEND
Definition: ald_usb.h:118
ald_usb_dev_connect
void ald_usb_dev_connect(void)
Enable connection.
Definition: ald_usb.c:177
ald_usb_int_enable_ep
void ald_usb_int_enable_ep(uint32_t flags)
Enable interrupt of the endpoint.
Definition: ald_usb.c:1085
USB_TYPE0_SPEED_LOW
#define USB_TYPE0_SPEED_LOW
Definition: ald_usb.h:127
USB_DEVCTL_FSDEV
#define USB_DEVCTL_FSDEV
Definition: ald_usb.h:51
ald_usb_dma_get_channel_error
uint32_t ald_usb_dma_get_channel_error(uint8_t ch)
Gets the status of the error.
Definition: ald_usb.c:1205
ald_delay_ms
__weak void ald_delay_ms(__IO uint32_t delay)
This function provides accurate delay (in milliseconds) based on variable incremented.
Definition: utils.c:247
RMU_PERH_USB
Definition: ald_rmu.h:125
USB_TXTYPE1_SPEED_LOW
#define USB_TXTYPE1_SPEED_LOW
Definition: ald_usb.h:133
ald_usb_num_ep_get
uint32_t ald_usb_num_ep_get(void)
Gets the number of the endpoint.
Definition: ald_usb.c:99
ald_usb_host_addr_get
uint32_t ald_usb_host_addr_get(uint32_t ep_idx, uint32_t flags)
Gets the device&#39;s address.
Definition: ald_usb.c:350
ald_usb_dma_channel_stop
void ald_usb_dma_channel_stop(uint8_t ch)
Stop DMA&#39;s machine.
Definition: ald_usb.c:1185
ald_usb_host_pwr_enable
void ald_usb_host_pwr_enable(void)
Enable power.
Definition: ald_usb.c:567
USB_CSRL0_STATUS
#define USB_CSRL0_STATUS
Definition: ald_usb.h:112
USB_DEV_EP0_SENT_STALL
#define USB_DEV_EP0_SENT_STALL
Definition: ald_usb.h:291
ald_usb_fifo_flush
void ald_usb_fifo_flush(uint32_t ep_idx, uint32_t flags)
Flush the FIFO.
Definition: ald_usb.c:1013
USB_CSRL0_REQPKT
#define USB_CSRL0_REQPKT
Definition: ald_usb.h:114
USB_LPMATTR_LS_M
#define USB_LPMATTR_LS_M
Definition: ald_usb.h:145
USB_TXTYPE1_PROTO_CTRL
#define USB_TXTYPE1_PROTO_CTRL
Definition: ald_usb.h:135
ald_usb_host_hub_addr_get
uint32_t ald_usb_host_hub_addr_get(uint32_t ep_idx, uint32_t flags)
Gets the HUB&#39;s address.
Definition: ald_usb.c:522
ald_usb_host_suspend
void ald_usb_host_suspend(void)
Suspend the devices.
Definition: ald_usb.c:665
ald_usb_fifo_config_get
void ald_usb_fifo_config_get(uint32_t ep_idx, uint32_t *addr, uint32_t *size, uint32_t flags)
Gets the parameters of the FIFO.
Definition: ald_usb.c:961
USB_LPMATTR_ENDPT_S
#define USB_LPMATTR_ENDPT_S
Definition: ald_usb.h:147
ald_usb_host_pwr_disable
void ald_usb_host_pwr_disable(void)
Disable power.
Definition: ald_usb.c:558
USB_RXCSRH1_ISO
#define USB_RXCSRH1_ISO
Definition: ald_usb.h:64
ald_usb_lpm_int_enable
void ald_usb_lpm_int_enable(uint32_t ints)
Enable the LPM interrupt.
Definition: ald_usb.c:1369
ald_usb_host_ep_ping
void ald_usb_host_ep_ping(uint32_t ep_idx, bool enable)
Ping the endpoint.
Definition: ald_usb.c:719
ald_usb_int_unregister
void ald_usb_int_unregister(void)
Unregister USB&#39;s interrupt.
Definition: ald_usb.c:1120
ald_usb_dev_disconnect
void ald_usb_dev_disconnect(void)
Disable connection.
Definition: ald_usb.c:186
ald_usb_int_register
void ald_usb_int_register(void)
Register USB&#39;s interrupt.
Definition: ald_usb.c:1110
USB_TXCSRL1_STALLED
#define USB_TXCSRL1_STALLED
Definition: ald_usb.h:89
USB_DMA_EP_CFG_RX_HOST
#define USB_DMA_EP_CFG_RX_HOST
Definition: ald_usb.h:397
ald_usb_ep_data_get
int32_t ald_usb_ep_data_get(uint32_t ep_idx, uint8_t *data, uint32_t *size)
Gets the data from FIFO.
Definition: ald_usb.c:762
USB_EP_MODE_ISOC
#define USB_EP_MODE_ISOC
Definition: ald_usb.h:303
ald_usb_lpm_link_status_get
uint32_t ald_usb_lpm_link_status_get(void)
Gets the link status.
Definition: ald_usb.c:1327
ald_usb_host_hub_addr_set
void ald_usb_host_hub_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags)
Sets the HUB&#39;s address.
Definition: ald_usb.c:537
USB_CSRH0_FLUSH
#define USB_CSRH0_FLUSH
Definition: ald_usb.h:76
USB_TXTYPE1_PROTO_ISOC
#define USB_TXTYPE1_PROTO_ISOC
Definition: ald_usb.h:136
ald_usb_host_request_in
void ald_usb_host_request_in(uint32_t ep_idx)
Request data IN(from device to host)
Definition: ald_usb.c:605
ald_usb_dma_channel_config
void ald_usb_dma_channel_config(uint8_t ch, uint32_t addr, uint32_t count, uint32_t ctrl)
Configure DMA&#39;s channel.
Definition: ald_usb.c:1149
USB_DEV_RX_SENT_STALL
#define USB_DEV_RX_SENT_STALL
Definition: ald_usb.h:277
USB_EP_SPEED_FULL
#define USB_EP_SPEED_FULL
Definition: ald_usb.h:309
ald_usb_control_reset
void ald_usb_control_reset(void)
Reset USB Control.
Definition: ald_usb.c:108
USB_RXCSRL1_STALLED
#define USB_RXCSRL1_STALLED
Definition: ald_usb.h:99
ald_usb_ep_status
uint32_t ald_usb_ep_status(uint32_t ep_idx)
Gets the status of the endpoint.
Definition: ald_usb.c:872
USB_LOW_SPEED
#define USB_LOW_SPEED
Definition: ald_usb.h:244
USB_DMA_EP_TX_MSK
#define USB_DMA_EP_TX_MSK
Definition: ald_usb.h:398
USB_EP_MODE_BULK
#define USB_EP_MODE_BULK
Definition: ald_usb.h:304
ald_usb_dev_get_addr
uint8_t ald_usb_dev_get_addr(void)
Gets the address.
Definition: ald_usb.c:158


ALD User Manual: D:/svn/src/ald_usb.h Source File

  • D:
  • svn
  • src
ald_usb.h
Go to the documentation of this file.
1
17 #ifndef __ALD_USB_H__
18 #define __ALD_USB_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include <stdbool.h>
25 #include "utils.h"
26 #include "ald_rmu.h"
27
28
41 #define USB_POWER_ISOUP 0x00000080U
42 #define USB_POWER_SOFTCONN 0x00000040U
43 #define USB_POWER_HS_EN 0x00000020U
44 #define USB_POWER_HS_M 0x00000010U
45 #define USB_POWER_RESET 0x00000008U
46 #define USB_POWER_RESUME 0x00000004U
47 #define USB_POWER_SUSPEND 0x00000002U
48 #define USB_POWER_PWRDNPHY 0x00000001U
49
50 #define USB_DEVCTL_DEV 0x00000080U
51 #define USB_DEVCTL_FSDEV 0x00000040U
52 #define USB_DEVCTL_LSDEV 0x00000020U
53 #define USB_DEVCTL_VBUS_M 0x00000018U
54 #define USB_DEVCTL_VBUS_NONE 0x00000000U
55 #define USB_DEVCTL_VBUS_SEND 0x00000008U
56 #define USB_DEVCTL_VBUS_AVALID 0x00000010U
57 #define USB_DEVCTL_VBUS_VALID 0x00000018U
58 #define USB_DEVCTL_HOST 0x00000004U
59 #define USB_DEVCTL_HOSTREQ 0x00000002U
60 #define USB_DEVCTL_SESSION 0x00000001U
61
62 #define USB_RXCSRH1_AUTOCL 0x00000080U
63 #define USB_RXCSRH1_AUTORQ 0x00000040U
64 #define USB_RXCSRH1_ISO 0x00000040U
65 #define USB_RXCSRH1_DMAEN 0x00000020U
66 #define USB_RXCSRH1_DISNYET 0x00000010U
67 #define USB_RXCSRH1_PIDERR 0x00000010U
68 #define USB_RXCSRH1_DMAMOD 0x00000008U
69 #define USB_RXCSRH1_DTWE 0x00000004U
70 #define USB_RXCSRH1_DT 0x00000002U
71 #define USB_RXCSRH1_INCOMPRX 0x00000001U
72
73 #define USB_CSRH0_DISPING 0x00000008U
74 #define USB_CSRH0_DTWE 0x00000004U
75 #define USB_CSRH0_DT 0x00000002U
76 #define USB_CSRH0_FLUSH 0x00000001U
77
78 #define USB_TXCSRH1_AUTOSET 0x00000080U
79 #define USB_TXCSRH1_ISO 0x00000040U
80 #define USB_TXCSRH1_MODE 0x00000020U
81 #define USB_TXCSRH1_DMAEN 0x00000010U
82 #define USB_TXCSRH1_FDT 0x00000008U
83 #define USB_TXCSRH1_DMAMOD 0x00000004U
84 #define USB_TXCSRH1_DTWE 0x00000002U
85 #define USB_TXCSRH1_DT 0x00000001U
86
87 #define USB_TXCSRL1_NAKTO 0x00000080U
88 #define USB_TXCSRL1_CLRDT 0x00000040U
89 #define USB_TXCSRL1_STALLED 0x00000020U
90 #define USB_TXCSRL1_STALL 0x00000010U
91 #define USB_TXCSRL1_SETUP 0x00000010U
92 #define USB_TXCSRL1_FLUSH 0x00000008U
93 #define USB_TXCSRL1_ERROR 0x00000004U
94 #define USB_TXCSRL1_UNDRN 0x00000004U
95 #define USB_TXCSRL1_FIFONE 0x00000002U
96 #define USB_TXCSRL1_TXRDY 0x00000001U
97
98 #define USB_RXCSRL1_CLRDT 0x00000080U
99 #define USB_RXCSRL1_STALLED 0x00000040U
100 #define USB_RXCSRL1_STALL 0x00000020U
101 #define USB_RXCSRL1_REQPKT 0x00000020U
102 #define USB_RXCSRL1_FLUSH 0x00000010U
103 #define USB_RXCSRL1_DATAERR 0x00000008U
104 #define USB_RXCSRL1_NAKTO 0x00000008U
105 #define USB_RXCSRL1_OVER 0x00000004U
106 #define USB_RXCSRL1_ERROR 0x00000004U
107 #define USB_RXCSRL1_FULL 0x00000002U
108 #define USB_RXCSRL1_RXRDY 0x00000001U
109
110 #define USB_CSRL0_NAKTO 0x00000080U
111 #define USB_CSRL0_SETENDC 0x00000080U
112 #define USB_CSRL0_STATUS 0x00000040U
113 #define USB_CSRL0_RXRDYC 0x00000040U
114 #define USB_CSRL0_REQPKT 0x00000020U
115 #define USB_CSRL0_STALL 0x00000020U
116 #define USB_CSRL0_SETEND 0x00000010U
117 #define USB_CSRL0_ERROR 0x00000010U
118 #define USB_CSRL0_DATAEND 0x00000008U
119 #define USB_CSRL0_SETUP 0x00000008U
120 #define USB_CSRL0_STALLED 0x00000004U
121 #define USB_CSRL0_TXRDY 0x00000002U
122 #define USB_CSRL0_RXRDY 0x00000001U
123
124 #define USB_TYPE0_SPEED_M 0x000000C0U
125 #define USB_TYPE0_SPEED_HIGH 0x00000040U
126 #define USB_TYPE0_SPEED_FULL 0x00000080U
127 #define USB_TYPE0_SPEED_LOW 0x000000C0U
128
129 #define USB_TXTYPE1_SPEED_M 0x000000C0U
130 #define USB_TXTYPE1_SPEED_DFLT 0x00000000U
131 #define USB_TXTYPE1_SPEED_HIGH 0x00000040U
132 #define USB_TXTYPE1_SPEED_FULL 0x00000080U
133 #define USB_TXTYPE1_SPEED_LOW 0x000000C0U
134 #define USB_TXTYPE1_PROTO_M 0x00000030U
135 #define USB_TXTYPE1_PROTO_CTRL 0x00000000U
136 #define USB_TXTYPE1_PROTO_ISOC 0x00000010U
137 #define USB_TXTYPE1_PROTO_BULK 0x00000020U
138 #define USB_TXTYPE1_PROTO_INT 0x00000030U
139 #define USB_TXTYPE1_TEP_M 0x0000000FU
140 #define USB_TXTYPE1_TEP_S 0U
141
142 #define USB_LPMATTR_ENDPT_M 0x0000F000U
143 #define USB_LPMATTR_RMTWAK 0x00000100U
144 #define USB_LPMATTR_HIRD_M 0x000000F0U
145 #define USB_LPMATTR_LS_M 0x0000000FU
146 #define USB_LPMATTR_LS_L1 0x00000001U
147 #define USB_LPMATTR_ENDPT_S 12U
148 #define USB_LPMATTR_HIRD_S 4U
149
150 #define USB_LPMCNTRL_LPMRES 0x00000002U
151 #define USB_LPMCNTRL_LPMXMT 0x00000001U
152 #define USB_LPMCNTRL_ENABLE 0x00000006U
153 #define USB_LPMCNTRL_DISABLE 0x00000000U
154
155 #define USB_INTCTRL_ALL 0x000003FFU
156 #define USB_INTCTRL_STATUS 0x000000FFU
157 #define USB_INTCTRL_VBUS_ERR 0x00000080U
158 #define USB_INTCTRL_SESSION 0x00000040U
159 #define USB_INTCTRL_SESSION_END 0x00000040U
160 #define USB_INTCTRL_DISCONNECT 0x00000020U
161 #define USB_INTCTRL_CONNECT 0x00000010U
162 #define USB_INTCTRL_SOF 0x00000008U
163 #define USB_INTCTRL_BABBLE 0x00000004U
164 #define USB_INTCTRL_RESET 0x00000004U
165 #define USB_INTCTRL_RESUME 0x00000002U
166 #define USB_INTCTRL_SUSPEND 0x00000001U
167 #define USB_INTCTRL_MODE_DETECT 0x00000200U
168 #define USB_INTCTRL_POWER_FAULT 0x00000100U
169
170 #define USB_INTEP_ALL 0xFFFFFFFFU
171 #define USB_INTEP_HOST_IN 0xFFFE0000U
172 #define USB_INTEP_HOST_IN_15 0x80000000U
173 #define USB_INTEP_HOST_IN_14 0x40000000U
174 #define USB_INTEP_HOST_IN_13 0x20000000U
175 #define USB_INTEP_HOST_IN_12 0x10000000U
176 #define USB_INTEP_HOST_IN_11 0x08000000U
177 #define USB_INTEP_HOST_IN_10 0x04000000U
178 #define USB_INTEP_HOST_IN_9 0x02000000U
179 #define USB_INTEP_HOST_IN_8 0x01000000U
180 #define USB_INTEP_HOST_IN_7 0x00800000U
181 #define USB_INTEP_HOST_IN_6 0x00400000U
182 #define USB_INTEP_HOST_IN_5 0x00200000U
183 #define USB_INTEP_HOST_IN_4 0x00100000U
184 #define USB_INTEP_HOST_IN_3 0x00080000U
185 #define USB_INTEP_HOST_IN_2 0x00040000U
186 #define USB_INTEP_HOST_IN_1 0x00020000U
187
188 #define USB_INTEP_DEV_OUT 0xFFFE0000U
189 #define USB_INTEP_DEV_OUT_15 0x80000000U
190 #define USB_INTEP_DEV_OUT_14 0x40000000U
191 #define USB_INTEP_DEV_OUT_13 0x20000000U
192 #define USB_INTEP_DEV_OUT_12 0x10000000U
193 #define USB_INTEP_DEV_OUT_11 0x08000000U
194 #define USB_INTEP_DEV_OUT_10 0x04000000U
195 #define USB_INTEP_DEV_OUT_9 0x02000000U
196 #define USB_INTEP_DEV_OUT_8 0x01000000U
197 #define USB_INTEP_DEV_OUT_7 0x00800000U
198 #define USB_INTEP_DEV_OUT_6 0x00400000U
199 #define USB_INTEP_DEV_OUT_5 0x00200000U
200 #define USB_INTEP_DEV_OUT_4 0x00100000U
201 #define USB_INTEP_DEV_OUT_3 0x00080000U
202 #define USB_INTEP_DEV_OUT_2 0x00040000U
203 #define USB_INTEP_DEV_OUT_1 0x00020000U
204
205 #define USB_INTEP_HOST_OUT 0x0000FFFEU
206 #define USB_INTEP_HOST_OUT_15 0x00008000U
207 #define USB_INTEP_HOST_OUT_14 0x00004000U
208 #define USB_INTEP_HOST_OUT_13 0x00002000U
209 #define USB_INTEP_HOST_OUT_12 0x00001000U
210 #define USB_INTEP_HOST_OUT_11 0x00000800U
211 #define USB_INTEP_HOST_OUT_10 0x00000400U
212 #define USB_INTEP_HOST_OUT_9 0x00000200U
213 #define USB_INTEP_HOST_OUT_8 0x00000100U
214 #define USB_INTEP_HOST_OUT_7 0x00000080U
215 #define USB_INTEP_HOST_OUT_6 0x00000040U
216 #define USB_INTEP_HOST_OUT_5 0x00000020U
217 #define USB_INTEP_HOST_OUT_4 0x00000010U
218 #define USB_INTEP_HOST_OUT_3 0x00000008U
219 #define USB_INTEP_HOST_OUT_2 0x00000004U
220 #define USB_INTEP_HOST_OUT_1 0x00000002U
221
222 #define USB_INTEP_DEV_IN 0x0000FFFEU
223 #define USB_INTEP_DEV_IN_15 0x00008000U
224 #define USB_INTEP_DEV_IN_14 0x00004000U
225 #define USB_INTEP_DEV_IN_13 0x00002000U
226 #define USB_INTEP_DEV_IN_12 0x00001000U
227 #define USB_INTEP_DEV_IN_11 0x00000800U
228 #define USB_INTEP_DEV_IN_10 0x00000400U
229 #define USB_INTEP_DEV_IN_9 0x00000200U
230 #define USB_INTEP_DEV_IN_8 0x00000100U
231 #define USB_INTEP_DEV_IN_7 0x00000080U
232 #define USB_INTEP_DEV_IN_6 0x00000040U
233 #define USB_INTEP_DEV_IN_5 0x00000020U
234 #define USB_INTEP_DEV_IN_4 0x00000010U
235 #define USB_INTEP_DEV_IN_3 0x00000008U
236 #define USB_INTEP_DEV_IN_2 0x00000004U
237 #define USB_INTEP_DEV_IN_1 0x00000002U
238
239 #define USB_INTEP_0 0x00000001U
240
241 #define USB_UNDEF_SPEED 0x80000000U
242 #define USB_HIGH_SPEED 0x00000002U
243 #define USB_FULL_SPEED 0x00000001U
244 #define USB_LOW_SPEED 0x00000000U
245
246 #define USB_HOST_IN_STATUS 0x114F0000U
247 #define USB_HOST_IN_PID_ERROR 0x10000000U
248 #define USB_HOST_IN_NOT_COMP 0x01000000U
249 #define USB_HOST_IN_STALL 0x00400000U
250 #define USB_HOST_IN_DATA_ERROR 0x00080000U
251
252 #define USB_HOST_IN_NAK_TO 0x00080000U
253
254 #define USB_HOST_IN_ERROR 0x00040000U
255
256 #define USB_HOST_IN_FIFO_FULL 0x00020000U
257 #define USB_HOST_IN_PKTRDY 0x00010000U
258 #define USB_HOST_OUT_STATUS 0x000000A7U
259 #define USB_HOST_OUT_NAK_TO 0x00000080U
260
261 #define USB_HOST_OUT_NOT_COMP 0x00000080U
262
263 #define USB_HOST_OUT_STALL 0x00000020U
264 #define USB_HOST_OUT_ERROR 0x00000004U
265
266 #define USB_HOST_OUT_FIFO_NE 0x00000002U
267 #define USB_HOST_OUT_PKTPEND 0x00000001U
268 #define USB_HOST_EP0_NAK_TO 0x00000080U
269
270 #define USB_HOST_EP0_STATUS 0x00000040U
271 #define USB_HOST_EP0_ERROR 0x00000010U
272
273 #define USB_HOST_EP0_RX_STALL 0x00000004U
274 #define USB_HOST_EP0_RXPKTRDY 0x00000001U
275 #define USB_DEV_RX_PID_ERROR 0x01000000U
276
277 #define USB_DEV_RX_SENT_STALL 0x00400000U
278 #define USB_DEV_RX_DATA_ERROR 0x00080000U
279 #define USB_DEV_RX_OVERRUN 0x00040000U
280
281 #define USB_DEV_RX_FIFO_FULL 0x00020000U
282 #define USB_DEV_RX_PKT_RDY 0x00010000U
283 #define USB_DEV_TX_NOT_COMP 0x00000080U
284
285 #define USB_DEV_TX_SENT_STALL 0x00000020U
286 #define USB_DEV_TX_UNDERRUN 0x00000004U
287 #define USB_DEV_TX_FIFO_NE 0x00000002U
288 #define USB_DEV_TX_TXPKTRDY 0x00000001U
289 #define USB_DEV_EP0_SETUP_END 0x00000010U
290
291 #define USB_DEV_EP0_SENT_STALL 0x00000004U
292 #define USB_DEV_EP0_IN_PKTPEND 0x00000002U
293 #define USB_DEV_EP0_OUT_PKTRDY 0x00000001U
294
295 #define USB_EP_AUTO_SET 0x00000001U
296 #define USB_EP_AUTO_REQUEST 0x00000002U
297 #define USB_EP_AUTO_CLEAR 0x00000004U
298 #define USB_EP_DMA_MODE_0 0x00000008U
299 #define USB_EP_DMA_MODE_1 0x00000010U
300 #define USB_EP_DIS_NYET 0x00000020U
301
302
303 #define USB_EP_MODE_ISOC 0x00000000U
304 #define USB_EP_MODE_BULK 0x00000100U
305 #define USB_EP_MODE_INT 0x00000200U
306 #define USB_EP_MODE_CTRL 0x00000300U
307 #define USB_EP_MODE_MASK 0x00000300U
308 #define USB_EP_SPEED_LOW 0x00000000U
309 #define USB_EP_SPEED_FULL 0x00001000U
310 #define USB_EP_SPEED_HIGH 0x00004000U
311 #define USB_EP_HOST_IN 0x00000000U
312 #define USB_EP_HOST_OUT 0x00002000U
313 #define USB_EP_DEV_IN 0x00002000U
314 #define USB_EP_DEV_OUT 0x00000000U
315
316 #define USB_HOST_PWRFLT_LOW 0x00000010U
317 #define USB_HOST_PWRFLT_HIGH 0x00000030U
318 #define USB_HOST_PWRFLT_EP_NONE 0x00000000U
319 #define USB_HOST_PWRFLT_EP_TRI 0x00000140U
320 #define USB_HOST_PWRFLT_EP_LOW 0x00000240U
321 #define USB_HOST_PWRFLT_EP_HIGH 0x00000340U
322 #define USB_HOST_PWREN_MAN_LOW 0x00000000U
323 #define USB_HOST_PWREN_MAN_HIGH 0x00000001U
324 #define USB_HOST_PWREN_AUTOLOW 0x00000002U
325 #define USB_HOST_PWREN_AUTOHIGH 0x00000003U
326 #define USB_HOST_PWREN_FILTER 0x00010000U
327
328 #define USB_HOST_LPM_RMTWAKE 0x00000100U
329 #define USB_HOST_LPM_L1 0x00000001U
330 #define USB_DEV_LPM_NAK 0x00000010U
331 #define USB_DEV_LPM_NONE 0x00000000U
332 #define USB_DEV_LPM_EN 0x0000000cU
333 #define USB_DEV_LPM_EXTONLY 0x00000004U
334 #define USB_DEV_LPM_LS_RMTWAKE 0x00000100U
335 #define USB_DEV_LPM_LS_L1 0x00000001U
336 #define USB_INTLPM_ERROR 0x00000020U
337 #define USB_INTLPM_RESUME 0x00000010U
338 #define USB_INTLPM_INCOMPLETE 0x00000008U
339 #define USB_INTLPM_ACK 0x00000004U
340 #define USB_INTLPM_NYET 0x00000002U
341 #define USB_INTLPM_STALL 0x00000001U
342
343 #define MAX_NAK_LIMIT 31U
344 #define DISABLE_NAK_LIMIT 0U
345
346 #define MAX_PACKET_SIZE_EP0 64U
347 #define USB_EP_0 0U
348 #define USB_EP_1 1U
349 #define USB_EP_2 2U
350 #define USB_EP_3 3U
351 #define USB_EP_4 4U
352 #define USB_EP_5 5U
353 #define NUM_USB_EP 6U
354 #define IndexToUSBEP(x) ((x))
355 #define USBEPToIndex(x) ((x))
356
357 #define USB_FIFO_SZ_8 0x00000000U
358 #define USB_FIFO_SZ_16 0x00000001U
359 #define USB_FIFO_SZ_32 0x00000002U
360 #define USB_FIFO_SZ_64 0x00000003U
361 #define USB_FIFO_SZ_128 0x00000004U
362 #define USB_FIFO_SZ_256 0x00000005U
363 #define USB_FIFO_SZ_512 0x00000006U
364 #define USB_FIFO_SZ_1024 0x00000007U
365 #define USB_FIFO_SZ_2048 0x00000008U
366 #define USBFIFOSizeToBytes(x) (8 << (x))
367
368 #define USB_TRANS_OUT 0x00000102U
369 #define USB_TRANS_IN 0x00000102U
370 #define USB_TRANS_IN_LAST 0x0000010aU
371 #define USB_TRANS_SETUP 0x0000110aU
372 #define USB_TRANS_STATUS 0x00000142U
373
374 #define USB_DUAL_MODE_HOST 0x00000001U
375 #define USB_DUAL_MODE_DEVICE 0x00000081U
376 #define USB_DUAL_MODE_NONE 0x00000080U
377 #define USB_OTG_MODE_ASIDE_HOST 0x0000001dU
378 #define USB_OTG_MODE_ASIDE_NPWR 0x00000001U
379 #define USB_OTG_MODE_ASIDE_SESS 0x00000009U
380 #define USB_OTG_MODE_ASIDE_AVAL 0x00000011U
381 #define USB_OTG_MODE_ASIDE_DEV 0x00000019U
382 #define USB_OTG_MODE_BSIDE_HOST 0x0000009dU
383 #define USB_OTG_MODE_BSIDE_DEV 0x00000099U
384 #define USB_OTG_MODE_BSIDE_NPWR 0x00000081U
385 #define USB_OTG_MODE_NONE 0x00000080U
386
387 #define USB_DMA_INT_CH8 0x00000080U
388 #define USB_DMA_INT_CH7 0x00000040U
389 #define USB_DMA_INT_CH6 0x00000020U
390 #define USB_DMA_INT_CH5 0x00000010U
391 #define USB_DMA_INT_CH4 0x00000008U
392 #define USB_DMA_INT_CH3 0x00000004U
393 #define USB_DMA_INT_CH2 0x00000002U
394 #define USB_DMA_INT_CH1 0x00000001U
395 #define USB_DMA_EP_CFG_TX 0x00000001U
396 #define USB_DMA_EP_CFG_RX_DEV 0x00000002U
397 #define USB_DMA_EP_CFG_RX_HOST 0x00000004U
398 #define USB_DMA_EP_TX_MSK 0x94U
399 #define USB_DMA_EP_RX_DEV_MSK 0xA8U
400 #define USB_DMA_EP_RX_HOST_MSK 0xE8U
401 #define USB_DMA_STATUS_ERROR 0x00000100U
402
403 #define USB_MODE_HOST_VBUS 0x00000004U
404 #define USB_MODE_HOST 0x00000002U
405 #define USB_MODE_DEV_VBUS 0x00000005U
406 #define USB_MODE_DEV 0x00000003U
407 #define USB_MODE_OTG 0x00000000U
408
409 #define USB_RX_EPSTATUS_SHIFT 16U
410 #define USB_INTEP_RX_SHIFT 16U
411
412 #define USB_DMA_CFG_START 0x00000001U
413 #define USB_DMA_CFG_START_NO 0x00000000U
414 #define USB_DMA_CFG_DIR_WR 0x00000000U
415 #define USB_DMA_CFG_DIR_RD 0x00000002U
416 #define USB_DMA_CFG_MODE_0 0x00000000U
417 #define USB_DMA_CFG_MODE_1 0x00000004U
418 #define USB_DMA_CFG_IE_DIS 0x00000000U
419 #define USB_DMA_CFG_IE_EN 0x00000008U
420 #define USB_DMA_CFG_EP_1 0x00000010U
421 #define USB_DMA_CFG_EP_2 0x00000020U
422 #define USB_DMA_CFG_EP_3 0x00000030U
423 #define USB_DMA_CFG_EP_4 0x00000040U
424 #define USB_DMA_CFG_EP_5 0x00000050U
425 #define USB_DMA_CFG_BURST_NONE 0x00000000U
426 #define USB_DMA_CFG_BURST_4 0x00000200U
427 #define USB_DMA_CFG_BURST_8 0x00000400U
428 #define USB_DMA_CFG_BURST_16 0x00000600U
429 #define USB_DMA_CFG_MODE_MSK 0x00000004U
430 #define USB_DMA_CFG_EP_POS 0x00000004U
431 #define USB_DMA_CFG_EP_MSK 0x000000F0U
432 #define USB_DMA_CH_ERR_MSK 0x100U
433
444 /* Base functions */
445 extern uint32_t ald_usb_frame_number_get(void);
446 extern void ald_usb_otg_session_request(bool start);
447 extern uint32_t ald_usb_mode_get(void);
448 extern void ald_usb_high_speed_enable(bool enable);
449 extern uint32_t ald_usb_device_speed_get(void);
450 extern uint32_t ald_usb_num_ep_get( void);
451 extern void ald_usb_control_reset(void);
452 extern void ald_usb_clock_output(void);
453 extern int ald_usb_eye_diagram_start(uint8_t *buf, uint16_t len);
461 /* Device functions */
462 extern uint8_t ald_usb_dev_get_addr(void);
463 extern void ald_usb_dev_set_addr(uint8_t addr);
464 extern void ald_usb_dev_connect(void);
465 extern void ald_usb_dev_disconnect(void);
466 extern void ald_usb_dev_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t flags);
467 extern void ald_usb_dev_ep_get_config(uint32_t ep_idx, uint32_t *p_max, uint32_t *flags);
468 extern void ald_usb_dev_ep_data_ack(uint32_t ep_idx, bool last);
469 extern void ald_usb_dev_ep_stall(uint32_t ep_idx, uint32_t flags);
470 extern void ald_usb_dev_ep_stall_clear(uint32_t ep_idx, uint32_t flags);
471 extern void ald_usb_dev_ep_status_clear(uint32_t ep_idx, uint32_t flags);
479 /* Host functions */
480 extern uint32_t ald_usb_host_addr_get(uint32_t ep_idx, uint32_t flags);
481 extern void ald_usb_host_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags);
482 extern void ald_usb_host_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t nak_val, uint32_t t_ep, uint32_t flags);
483 extern void ald_usb_host_ep_data_ack(uint32_t ep_idx);
484 extern void ald_usb_host_ep_data_toggle(uint32_t ep_idx, bool toggle, uint32_t flags);
485 extern void ald_usb_host_ep_status_clear(uint32_t ep_idx, uint32_t flags);
486 extern uint32_t ald_usb_host_hub_addr_get(uint32_t ep_idx, uint32_t flags);
487 extern void ald_usb_host_hub_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags);
488 extern void ald_usb_host_pwr_disable(void);
489 extern void ald_usb_host_pwr_enable(void);
490 extern void ald_usb_host_pwr_config(uint32_t flags);
491 extern void ald_usb_host_pwr_fault_disable(void);
492 extern void ald_usb_host_pwr_fault_enable(void);
493 extern void ald_usb_host_request_in(uint32_t ep_idx);
494 extern void ald_usb_host_request_in_clear(uint32_t ep_idx);
495 extern void ald_usb_host_request_status(void);
496 extern void ald_usb_host_reset(bool start);
497 extern void ald_usb_host_resume(bool start);
498 extern void ald_usb_host_suspend(void);
499 extern uint32_t ald_usb_host_speed_get(void);
500 extern void ald_usb_host_ep_speed_set(uint32_t ep_idx, uint32_t flags);
501 extern void ald_usb_host_ep_ping(uint32_t ep_idx, bool enable);
509 /* Endpoint functions */
510 extern uint32_t ald_usb_ep_data_avail(uint32_t ep_idx);
511 extern int32_t ald_usb_ep_data_get(uint32_t ep_idx, uint8_t *data, uint32_t *size);
512 extern int32_t ald_usb_ep_data_put(uint32_t ep_idx, uint8_t *data, uint32_t size);
513 extern int32_t ald_usb_ep_data_send(uint32_t ep_idx, uint32_t tx_type);
514 extern void ald_usb_ep_data_toggle_clear(uint32_t ep_idx, uint32_t flags);
515 extern void ald_usb_ep_req_packet_count(uint32_t ep_idx, uint32_t count);
516 extern uint32_t ald_usb_ep_status(uint32_t ep_idx);
517 extern void ald_usb_ep_dma_config(uint32_t ep_idx, uint32_t flag, type_func_t en);
525 /* FIFO functions */
526 extern uint32_t ald_usb_fifo_addr_get(uint32_t ep_idx);
527 extern void ald_usb_fifo_config_get(uint32_t ep_idx, uint32_t *addr, uint32_t *size, uint32_t flags);
528 extern void ald_usb_fifo_config_set(uint32_t ep_idx, uint32_t addr, uint32_t size, uint32_t flags);
529 extern void ald_usb_fifo_flush(uint32_t ep_idx, uint32_t flags);
537 /* Interrupt functions */
538 extern void ald_usb_int_disable(uint32_t flags);
539 extern void ald_usb_int_enable(uint32_t flags);
540 extern uint32_t ald_usb_int_status_get(void);
541 extern void ald_usb_int_disable_ep(uint32_t flags);
542 extern void ald_usb_int_enable_ep(uint32_t flags);
543 extern uint32_t ald_usb_int_status_ep_get(void);
544 extern void ald_usb_int_register(void);
545 extern void ald_usb_int_unregister(void);
546 extern uint32_t ald_usb_int_num_get(void);
554 /* DMA functions */
555 extern void ald_usb_dma_channel_config(uint8_t ch, uint32_t addr, uint32_t count, uint32_t ctrl);
556 extern void ald_usb_dma_mult_recv_start(uint32_t ep_idx);
557 extern void ald_usb_dma_channel_start(uint8_t ch);
558 extern void ald_usb_dma_channel_stop(uint8_t ch);
559 extern uint32_t ald_usb_dma_get_interrupt_flag(void);
560 extern uint32_t ald_usb_dma_get_channel_error(uint8_t ch);
561 extern void ald_usb_dma_clear_channel_error(uint8_t ch);
569 /* LPM functions */
570 extern void ald_usb_host_lpm_send(uint32_t addr, uint32_t ep_idx);
571 extern void ald_usb_host_lpm_config(uint32_t resume_time, uint32_t config);
572 extern uint32_t ald_usb_lpm_remote_wake_is_enable(void);
573 extern void ald_usb_host_lpm_resume(void);
574 extern void ald_usb_dev_lpm_remote_wake(void);
575 extern void ald_usb_dev_lpm_config(uint32_t config);
576 extern void ald_usb_dev_lpm_enable(void);
577 extern void ald_usb_dev_lpm_disable(void);
578 extern uint32_t ald_usb_lpm_link_status_get(void);
579 extern uint32_t ald_usb_lpm_ep_get(void);
580 extern uint32_t ald_usb_lpm_int_status_get(void);
581 extern void ald_usb_lpm_int_disable(uint32_t ints);
582 extern void ald_usb_lpm_int_enable(uint32_t ints);
599 #ifdef __cplusplus
600 }
601 #endif
602 #endif
ald_usb_dev_set_addr
void ald_usb_dev_set_addr(uint8_t addr)
Sets the address.
Definition: ald_usb.c:168
ald_usb_int_status_get
uint32_t ald_usb_int_status_get(void)
Gets the status of the interrupt.
Definition: ald_usb.c:1064
ald_usb_ep_data_send
int32_t ald_usb_ep_data_send(uint32_t ep_idx, uint32_t tx_type)
Send data.
Definition: ald_usb.c:820
ald_usb_host_request_in_clear
void ald_usb_host_request_in_clear(uint32_t ep_idx)
Clear the status of request IN.
Definition: ald_usb.c:618
ald_usb_host_pwr_fault_disable
void ald_usb_host_pwr_fault_disable(void)
Disable the fault parameters of the power.
Definition: ald_usb.c:586
ald_usb_high_speed_enable
void ald_usb_high_speed_enable(bool enable)
Enable/Disable the high mode.
Definition: ald_usb.c:75
ald_usb_host_speed_get
uint32_t ald_usb_host_speed_get(void)
Gets the device&#39;s speed.
Definition: ald_usb.c:674
ald_usb_frame_number_get
uint32_t ald_usb_frame_number_get(void)
Gets the number of current frame.
Definition: ald_usb.c:42
ald_usb_host_pwr_fault_enable
void ald_usb_host_pwr_fault_enable(void)
Enable the fault parameters of the power.
Definition: ald_usb.c:595
ald_usb_host_ep_speed_set
void ald_usb_host_ep_speed_set(uint32_t ep_idx, uint32_t flags)
Sets the endpoint speed.
Definition: ald_usb.c:694
ald_usb_int_status_ep_get
uint32_t ald_usb_int_status_ep_get(void)
Gets the ststus of the endpoint interrupt.
Definition: ald_usb.c:1096
ald_usb_device_speed_get
uint32_t ald_usb_device_speed_get(void)
Gets the speed of the device.
Definition: ald_usb.c:87
ald_usb_clock_output
void ald_usb_clock_output(void)
Output USB clock via PA15, 60MHz/256=234.375KHz.
Definition: ald_usb.c:117
type_func_t
type_func_t
Definition: type.h:47
ald_usb_dev_ep_data_ack
void ald_usb_dev_ep_data_ack(uint32_t ep_idx, bool last)
Acknowledge the data from the host.
Definition: ald_usb.c:270
ald_usb_dma_get_interrupt_flag
uint32_t ald_usb_dma_get_interrupt_flag(void)
Gets flags of the interrupt.
Definition: ald_usb.c:1195
ald_usb_otg_session_request
void ald_usb_otg_session_request(bool start)
Request the session.
Definition: ald_usb.c:52
ald_usb_host_ep_data_toggle
void ald_usb_host_ep_data_toggle(uint32_t ep_idx, bool toggle, uint32_t flags)
Toggle the data in host mode.
Definition: ald_usb.c:470
ald_usb_mode_get
uint32_t ald_usb_mode_get(void)
Gets the mode.
Definition: ald_usb.c:64
ald_usb_int_num_get
uint32_t ald_usb_int_num_get(void)
Get USB&#39;s interrupt number.
Definition: ald_usb.c:1129
ald_usb_ep_req_packet_count
void ald_usb_ep_req_packet_count(uint32_t ep_idx, uint32_t count)
Sets the size of request data IN.
Definition: ald_usb.c:862
ald_usb_dev_ep_stall_clear
void ald_usb_dev_ep_stall_clear(uint32_t ep_idx, uint32_t flags)
Cancel the stall status.
Definition: ald_usb.c:300
ald_usb_host_pwr_config
void ald_usb_host_pwr_config(uint32_t flags)
Configure power in host mode.
Definition: ald_usb.c:577
ald_usb_int_enable
void ald_usb_int_enable(uint32_t flags)
Enable interrupt.
Definition: ald_usb.c:1054
ald_usb_dev_ep_status_clear
void ald_usb_dev_ep_status_clear(uint32_t ep_idx, uint32_t flags)
Clear the status of the endpoint.
Definition: ald_usb.c:320
ald_rmu.h
Header file of RMU module driver.
ald_usb_lpm_int_status_get
uint32_t ald_usb_lpm_int_status_get(void)
Gets the status of the interrupt.
Definition: ald_usb.c:1351
ald_usb_host_lpm_send
void ald_usb_host_lpm_send(uint32_t addr, uint32_t ep_idx)
Transmit a LPM transaction in host mode.
Definition: ald_usb.c:1236
ald_usb_host_addr_set
void ald_usb_host_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags)
Sets the device&#39;s address.
Definition: ald_usb.c:365
ald_usb_dev_ep_config
void ald_usb_dev_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t flags)
Configure the endpoint in device mode.
Definition: ald_usb.c:198
ald_usb_dma_mult_recv_start
void ald_usb_dma_mult_recv_start(uint32_t ep_idx)
Start multiple receive.
Definition: ald_usb.c:1162
ald_usb_dev_lpm_remote_wake
void ald_usb_dev_lpm_remote_wake(void)
Enable remote wakeup in device mode.
Definition: ald_usb.c:1291
ald_usb_host_ep_data_ack
void ald_usb_host_ep_data_ack(uint32_t ep_idx)
Acknowledge the data in host mode.
Definition: ald_usb.c:455
ald_usb_host_request_status
void ald_usb_host_request_status(void)
Request data IN at endpoint 0.
Definition: ald_usb.c:630
utils.h
This file contains the Utilities functions/types for the driver.
ald_usb_dev_lpm_enable
void ald_usb_dev_lpm_enable(void)
Enable LPM in device mode.
Definition: ald_usb.c:1309
ald_usb_dev_lpm_disable
void ald_usb_dev_lpm_disable(void)
Disable LPM in device mode.
Definition: ald_usb.c:1318
ald_usb_dev_lpm_config
void ald_usb_dev_lpm_config(uint32_t config)
Enable remote wakeup in device mode.
Definition: ald_usb.c:1300
ald_usb_ep_data_put
int32_t ald_usb_ep_data_put(uint32_t ep_idx, uint8_t *data, uint32_t size)
Puts data to the FIFO.
Definition: ald_usb.c:797
ald_usb_int_disable_ep
void ald_usb_int_disable_ep(uint32_t flags)
Disable interrupt of the endpoint.
Definition: ald_usb.c:1074
ald_usb_host_lpm_resume
void ald_usb_host_lpm_resume(void)
Initiate a RESUME from the L1 state in host mode.
Definition: ald_usb.c:1282
ald_usb_ep_data_toggle_clear
void ald_usb_ep_data_toggle_clear(uint32_t ep_idx, uint32_t flags)
Clear the status of the toggle.
Definition: ald_usb.c:848
ald_usb_ep_dma_config
void ald_usb_ep_dma_config(uint32_t ep_idx, uint32_t flag, type_func_t en)
Configure the endpoint in DMA mode.
Definition: ald_usb.c:897
ald_usb_dma_channel_start
void ald_usb_dma_channel_start(uint8_t ch)
Start DMA&#39;s machine.
Definition: ald_usb.c:1174
ald_usb_fifo_config_set
void ald_usb_fifo_config_set(uint32_t ep_idx, uint32_t addr, uint32_t size, uint32_t flags)
Sets the parameters of the FIFO.
Definition: ald_usb.c:988
ald_usb_dma_clear_channel_error
void ald_usb_dma_clear_channel_error(uint8_t ch)
Clear the status of the error.
Definition: ald_usb.c:1218
ald_usb_lpm_ep_get
uint32_t ald_usb_lpm_ep_get(void)
Gets the index of the endpoint.
Definition: ald_usb.c:1336
ald_usb_fifo_addr_get
uint32_t ald_usb_fifo_addr_get(uint32_t ep_idx)
Gets the address of the FIFO.
Definition: ald_usb.c:948
ald_usb_host_reset
void ald_usb_host_reset(bool start)
Reset the USB&#39;s bus.
Definition: ald_usb.c:640
ald_usb_host_resume
void ald_usb_host_resume(bool start)
Resume the devices.
Definition: ald_usb.c:653
ald_usb_ep_data_avail
uint32_t ald_usb_ep_data_avail(uint32_t ep_idx)
Gets the size of the available data.
Definition: ald_usb.c:739
ald_usb_host_lpm_config
void ald_usb_host_lpm_config(uint32_t resume_time, uint32_t config)
Configure the LPM parameters in host mode.
Definition: ald_usb.c:1255
ald_usb_eye_diagram_start
int ald_usb_eye_diagram_start(uint8_t *buf, uint16_t len)
Starts eye diagram for high-speed host.
Definition: ald_usb.c:133
ald_usb_host_ep_config
void ald_usb_host_ep_config(uint32_t ep_idx, uint32_t p_max, uint32_t nak_val, uint32_t t_ep, uint32_t flags)
Configure the endpoint in host mode.
Definition: ald_usb.c:382
ald_usb_lpm_remote_wake_is_enable
uint32_t ald_usb_lpm_remote_wake_is_enable(void)
Gets status of remote wakeup.
Definition: ald_usb.c:1270
ald_usb_dev_ep_get_config
void ald_usb_dev_ep_get_config(uint32_t ep_idx, uint32_t *p_max, uint32_t *flags)
Gets the parameters of the endpoint.
Definition: ald_usb.c:234
ald_usb_host_ep_status_clear
void ald_usb_host_ep_status_clear(uint32_t ep_idx, uint32_t flags)
Clear the status of endpoint in host mode.
Definition: ald_usb.c:505
ald_usb_int_disable
void ald_usb_int_disable(uint32_t flags)
Disable interrupt.
Definition: ald_usb.c:1043
ald_usb_dev_ep_stall
void ald_usb_dev_ep_stall(uint32_t ep_idx, uint32_t flags)
Stall the endpoint.
Definition: ald_usb.c:284
ald_usb_lpm_int_disable
void ald_usb_lpm_int_disable(uint32_t ints)
Disable the LPM interrupt.
Definition: ald_usb.c:1360
ald_usb_dev_connect
void ald_usb_dev_connect(void)
Enable connection.
Definition: ald_usb.c:177
ald_usb_int_enable_ep
void ald_usb_int_enable_ep(uint32_t flags)
Enable interrupt of the endpoint.
Definition: ald_usb.c:1085
ald_usb_dma_get_channel_error
uint32_t ald_usb_dma_get_channel_error(uint8_t ch)
Gets the status of the error.
Definition: ald_usb.c:1205
ald_usb_num_ep_get
uint32_t ald_usb_num_ep_get(void)
Gets the number of the endpoint.
Definition: ald_usb.c:99
ald_usb_host_addr_get
uint32_t ald_usb_host_addr_get(uint32_t ep_idx, uint32_t flags)
Gets the device&#39;s address.
Definition: ald_usb.c:350
ald_usb_dma_channel_stop
void ald_usb_dma_channel_stop(uint8_t ch)
Stop DMA&#39;s machine.
Definition: ald_usb.c:1185
ald_usb_host_pwr_enable
void ald_usb_host_pwr_enable(void)
Enable power.
Definition: ald_usb.c:567
ald_usb_fifo_flush
void ald_usb_fifo_flush(uint32_t ep_idx, uint32_t flags)
Flush the FIFO.
Definition: ald_usb.c:1013
ald_usb_host_hub_addr_get
uint32_t ald_usb_host_hub_addr_get(uint32_t ep_idx, uint32_t flags)
Gets the HUB&#39;s address.
Definition: ald_usb.c:522
ald_usb_host_suspend
void ald_usb_host_suspend(void)
Suspend the devices.
Definition: ald_usb.c:665
ald_usb_fifo_config_get
void ald_usb_fifo_config_get(uint32_t ep_idx, uint32_t *addr, uint32_t *size, uint32_t flags)
Gets the parameters of the FIFO.
Definition: ald_usb.c:961
ald_usb_host_pwr_disable
void ald_usb_host_pwr_disable(void)
Disable power.
Definition: ald_usb.c:558
ald_usb_lpm_int_enable
void ald_usb_lpm_int_enable(uint32_t ints)
Enable the LPM interrupt.
Definition: ald_usb.c:1369
ald_usb_host_ep_ping
void ald_usb_host_ep_ping(uint32_t ep_idx, bool enable)
Ping the endpoint.
Definition: ald_usb.c:719
ald_usb_int_unregister
void ald_usb_int_unregister(void)
Unregister USB&#39;s interrupt.
Definition: ald_usb.c:1120
ald_usb_dev_disconnect
void ald_usb_dev_disconnect(void)
Disable connection.
Definition: ald_usb.c:186
ald_usb_int_register
void ald_usb_int_register(void)
Register USB&#39;s interrupt.
Definition: ald_usb.c:1110
ald_usb_ep_data_get
int32_t ald_usb_ep_data_get(uint32_t ep_idx, uint8_t *data, uint32_t *size)
Gets the data from FIFO.
Definition: ald_usb.c:762
ald_usb_lpm_link_status_get
uint32_t ald_usb_lpm_link_status_get(void)
Gets the link status.
Definition: ald_usb.c:1327
ald_usb_host_hub_addr_set
void ald_usb_host_hub_addr_set(uint32_t ep_idx, uint32_t addr, uint32_t flags)
Sets the HUB&#39;s address.
Definition: ald_usb.c:537
ald_usb_host_request_in
void ald_usb_host_request_in(uint32_t ep_idx)
Request data IN(from device to host)
Definition: ald_usb.c:605
ald_usb_dma_channel_config
void ald_usb_dma_channel_config(uint8_t ch, uint32_t addr, uint32_t count, uint32_t ctrl)
Configure DMA&#39;s channel.
Definition: ald_usb.c:1149
ald_usb_control_reset
void ald_usb_control_reset(void)
Reset USB Control.
Definition: ald_usb.c:108
ald_usb_ep_status
uint32_t ald_usb_ep_status(uint32_t ep_idx)
Gets the status of the endpoint.
Definition: ald_usb.c:872
ald_usb_dev_get_addr
uint8_t ald_usb_dev_get_addr(void)
Gets the address.
Definition: ald_usb.c:158


ALD User Manual: D:/svn/src/ald_wdt.c Source File

  • D:
  • svn
  • src
ald_wdt.c
Go to the documentation of this file.
1
16 #include "ald_conf.h"
17 #include "ald_wdt.h"
18
19
28 #ifdef ALD_WDT
29
30
47 void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt)
48 {
49 assert_param(IS_WWDT_WIN_TYPE(win));
50 assert_param(IS_FUNC_STATE(interrupt));
51
52 WWDT_UNLOCK();
53 WRITE_REG(WWDT->LOAD, load);
54 MODIFY_REG(WWDT->CON, WWDT_CON_WWDTWIN_MSK, win << WWDT_CON_WWDTWIN_POSS);
55 SET_BIT(WWDT->CON, WWDT_CON_CLKS_MSK);
56 SET_BIT(WWDT->CON, WWDT_CON_RSTEN_MSK);
57 MODIFY_REG(WWDT->CON, WWDT_CON_IE_MSK, interrupt << WWDT_CON_IE_POS);
58 WWDT_LOCK();
59
60 return;
61 }
62
67 void ald_wwdt_start(void)
68 {
69 WWDT_UNLOCK();
70 SET_BIT(WWDT->CON, WWDT_CON_EN_MSK);
71 WWDT_LOCK();
72
73 return;
74 }
75
80 uint32_t ald_wwdt_get_value(void)
81 {
82 return WWDT->VALUE;
83 }
84
89 it_status_t ald_wwdt_get_flag_status(void)
90 {
91 if (READ_BIT(WWDT->RIS, WWDT_RIS_WWDTIF_MSK))
92 return SET;
93
94 return RESET;
95 }
96
101 void ald_wwdt_clear_flag_status(void)
102 {
103 WRITE_REG(WWDT->INTCLR, 1);
104 return;
105 }
106
111 void ald_wwdt_feed_dog(void)
112 {
113 WWDT_UNLOCK();
114 WRITE_REG(WWDT->INTCLR, 0x1);
115 WWDT_LOCK();
116
117 return;
118 }
133 void ald_iwdt_init(uint32_t load, type_func_t interrupt)
134 {
135 assert_param(IS_FUNC_STATE(interrupt));
136
137 IWDT_UNLOCK();
138 WRITE_REG(IWDT->LOAD, load);
139 SET_BIT(IWDT->CON, IWDT_CON_CLKS_MSK);
140 SET_BIT(IWDT->CON, IWDT_CON_RSTEN_MSK);
141 MODIFY_REG(IWDT->CON, IWDT_CON_IE_MSK, interrupt << IWDT_CON_IE_POS);
142 IWDT_LOCK();
143
144 return;
145 }
146
151 void ald_iwdt_start(void)
152 {
153 IWDT_UNLOCK();
154 SET_BIT(IWDT->CON, IWDT_CON_EN_MSK);
155 IWDT_LOCK();
156
157 return;
158 }
159
164 uint32_t ald_iwdt_get_value(void)
165 {
166 return IWDT->VALUE;
167 }
168
173 it_status_t ald_iwdt_get_flag_status(void)
174 {
175 if (READ_BIT(IWDT->RIS, IWDT_RIS_WDTIF_MSK))
176 return SET;
177
178 return RESET;
179 }
180
185 void ald_iwdt_clear_flag_status(void)
186 {
187 WRITE_REG(IWDT->INTCLR, 1);
188 return;
189 }
190
195 void ald_iwdt_feed_dog(void)
196 {
197 IWDT_UNLOCK();
198 WRITE_REG(IWDT->INTCLR, 1);
199 IWDT_LOCK();
200
201 return;
202 }
207 #endif /* ALD_WDT */
208
wwdt_win_t
wwdt_win_t
Wwdt no dog window.
Definition: ald_wdt.h:41
WWDT_LOCK
#define WWDT_LOCK()
Definition: ald_wdt.h:57
ald_wwdt_feed_dog
void ald_wwdt_feed_dog(void)
Refreshes the WWDT.
Definition: ald_wdt.c:111
assert_param
#define assert_param(x)
Definition: type.h:88
SET
Definition: type.h:39
ald_iwdt_clear_flag_status
void ald_iwdt_clear_flag_status(void)
Clear interrupt state.
Definition: ald_wdt.c:185
type_func_t
type_func_t
Definition: type.h:47
IWDT_UNLOCK
#define IWDT_UNLOCK()
Definition: ald_wdt.h:58
ald_wdt.h
Header file of WDT module driver.
ald_iwdt_get_flag_status
it_status_t ald_iwdt_get_flag_status(void)
Get interrupt state.
Definition: ald_wdt.c:173
ald_wwdt_start
void ald_wwdt_start(void)
Start the WWDT.
Definition: ald_wdt.c:67
IS_WWDT_WIN_TYPE
#define IS_WWDT_WIN_TYPE(x)
Definition: ald_wdt.h:69
RESET
Definition: type.h:38
ald_conf.h
Enable/Disable the peripheral module.
ald_iwdt_init
void ald_iwdt_init(uint32_t load, type_func_t interrupt)
Initializes the IWDG according to the specified parameters.
Definition: ald_wdt.c:133
ald_iwdt_feed_dog
void ald_iwdt_feed_dog(void)
Refreshes the WWDT.
Definition: ald_wdt.c:195
it_status_t
enum flag_status_t it_status_t
IWDT_LOCK
#define IWDT_LOCK()
Definition: ald_wdt.h:59
ald_wwdt_get_flag_status
it_status_t ald_wwdt_get_flag_status(void)
Get interrupt state.
Definition: ald_wdt.c:89
ald_wwdt_clear_flag_status
void ald_wwdt_clear_flag_status(void)
Clear interrupt state.
Definition: ald_wdt.c:101
ald_wwdt_get_value
uint32_t ald_wwdt_get_value(void)
Get the free-running downcounter value.
Definition: ald_wdt.c:80
ald_iwdt_start
void ald_iwdt_start(void)
Start the IWDT.
Definition: ald_wdt.c:151
READ_BIT
#define READ_BIT(reg, bit)
Definition: type.h:69
ald_wwdt_init
void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt)
Initializes the WWDT according to the specified parameters.
Definition: ald_wdt.c:47
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
WWDT_UNLOCK
#define WWDT_UNLOCK()
Definition: ald_wdt.h:56
WRITE_REG
#define WRITE_REG(reg, val)
Definition: type.h:72
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
ald_iwdt_get_value
uint32_t ald_iwdt_get_value(void)
Get the free-running downcounter value.
Definition: ald_wdt.c:164
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73


ALD User Manual: D:/svn/src/ald_wdt.h Source File

  • D:
  • svn
  • src
ald_wdt.h
Go to the documentation of this file.
1
17 #ifndef __ALD_WDT_H__
18 #define __ALD_WDT_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include "utils.h"
25
41 typedef enum {
42 WWDT_WIN_25 = 0x0U,
43 WWDT_WIN_50 = 0x1U,
44 WWDT_WIN_75 = 0x2U,
45 WWDT_WIN_00 = 0x3U,
46 } wwdt_win_t;
47
56 #define WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551U);}
57 #define WWDT_LOCK() {WRITE_REG(WWDT->LOCK, 0xFFFFFFFFU);}
58 #define IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551U);}
59 #define IWDT_LOCK() {WRITE_REG(IWDT->LOCK, 0xFFFFFFFFU);}
60
69 #define IS_WWDT_WIN_TYPE(x) ((x == WWDT_WIN_25) || \
70 (x == WWDT_WIN_50) || \
71 (x == WWDT_WIN_75) || \
72 (x == WWDT_WIN_00))
73 #define IS_FUNC_STATE(x) (((x) == DISABLE) || \
74 ((x) == ENABLE))
75
82 void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt);
83 void ald_wwdt_start(void);
84 uint32_t ald_wwdt_get_value(void);
85 it_status_t ald_wwdt_get_flag_status(void);
86 void ald_wwdt_clear_flag_status(void);
87 void ald_wwdt_feed_dog(void);
95 void ald_iwdt_init(uint32_t load, type_func_t interrupt);
96 void ald_iwdt_start(void);
97 uint32_t ald_iwdt_get_value(void);
98 it_status_t ald_iwdt_get_flag_status(void);
99 void ald_iwdt_clear_flag_status(void);
100 void ald_iwdt_feed_dog(void);
112 #ifdef __cplusplus
113 }
114 #endif
115
116 #endif /* __ALD_WDT_H__ */
wwdt_win_t
wwdt_win_t
Wwdt no dog window.
Definition: ald_wdt.h:41
WWDT_WIN_00
Definition: ald_wdt.h:45
ald_wwdt_feed_dog
void ald_wwdt_feed_dog(void)
Refreshes the WWDT.
Definition: ald_wdt.c:111
ald_iwdt_clear_flag_status
void ald_iwdt_clear_flag_status(void)
Clear interrupt state.
Definition: ald_wdt.c:185
type_func_t
type_func_t
Definition: type.h:47
WWDT_WIN_50
Definition: ald_wdt.h:43
ald_iwdt_get_flag_status
it_status_t ald_iwdt_get_flag_status(void)
Get interrupt state.
Definition: ald_wdt.c:173
ald_wwdt_start
void ald_wwdt_start(void)
Start the WWDT.
Definition: ald_wdt.c:67
utils.h
This file contains the Utilities functions/types for the driver.
WWDT_WIN_75
Definition: ald_wdt.h:44
ald_iwdt_init
void ald_iwdt_init(uint32_t load, type_func_t interrupt)
Initializes the IWDG according to the specified parameters.
Definition: ald_wdt.c:133
ald_iwdt_feed_dog
void ald_iwdt_feed_dog(void)
Refreshes the WWDT.
Definition: ald_wdt.c:195
it_status_t
enum flag_status_t it_status_t
ald_wwdt_get_flag_status
it_status_t ald_wwdt_get_flag_status(void)
Get interrupt state.
Definition: ald_wdt.c:89
ald_wwdt_clear_flag_status
void ald_wwdt_clear_flag_status(void)
Clear interrupt state.
Definition: ald_wdt.c:101
ald_wwdt_get_value
uint32_t ald_wwdt_get_value(void)
Get the free-running downcounter value.
Definition: ald_wdt.c:80
ald_iwdt_start
void ald_iwdt_start(void)
Start the IWDT.
Definition: ald_wdt.c:151
ald_wwdt_init
void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt)
Initializes the WWDT according to the specified parameters.
Definition: ald_wdt.c:47
ald_iwdt_get_value
uint32_t ald_iwdt_get_value(void)
Get the free-running downcounter value.
Definition: ald_wdt.c:164
WWDT_WIN_25
Definition: ald_wdt.h:42


ALD User Manual: Graph Legend

Graph Legend

This page explains how to interpret the graphs that are generated by doxygen.

Consider the following example:

/*! Invisible class because of truncation */
class Invisible { };
/*! Truncated class, inheritance relation is hidden */
class Truncated : public Invisible { };
/* Class not documented with doxygen comments */
class Undocumented { };
/*! Class that is inherited using public inheritance */
class PublicBase : public Truncated { };
/*! A template class */
template<class T> class Templ { };
/*! Class that is inherited using protected inheritance */
class ProtectedBase { };
/*! Class that is inherited using private inheritance */
class PrivateBase { };
/*! Class that is used by the Inherited class */
class Used { };
/*! Super class that inherits a number of other classes */
class Inherited : public PublicBase,
protected ProtectedBase,
private PrivateBase,
public Undocumented,
public Templ<int>
{
private:
Used *m_usedClass;
};

This will result in the following graph:

The boxes in the above graph have the following meaning:

  • A filled gray box represents the struct or class for which the graph is generated.
  • A box with a black border denotes a documented struct or class.
  • A box with a gray border denotes an undocumented struct or class.
  • A box with a red border denotes a documented struct or class forwhich not all inheritance/containment relations are shown. A graph is truncated if it does not fit within the specified boundaries.

The arrows have the following meaning:

  • A dark blue arrow is used to visualize a public inheritance relation between two classes.
  • A dark green arrow is used for protected inheritance.
  • A dark red arrow is used for private inheritance.
  • A purple dashed arrow is used if a class is contained or used by another class. The arrow is labelled with the variable(s) through which the pointed class or struct is accessible.
  • A yellow dashed arrow denotes a relation between a template instance and the template class it was instantiated from. The arrow is labelled with the template parameters of the instance.


ALD User Manual: Main Page

ALD User Manual Documentation


ALD User Manual: D:/svn/src/type.h Source File

  • D:
  • svn
  • src
type.h
Go to the documentation of this file.
1
17 #ifndef __TYPE_H__
18 #define __TYPE_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include <stdint.h>
25
26
27 #if defined (__CC_ARM)
28 #define __INLINE__ __inline
29 #define __STATIC_INLINE__ static __inline
30 #else
31 #define __INLINE__ inline
32 #define __STATIC_INLINE__ static inline
33 #endif
34
35 #define __isr__
36
37 typedef enum {
38 RESET = 0x0U,
39 SET = 0x1U,
40 } flag_status_t, it_status_t;
41
42 typedef enum {
43 BIT_RESET = 0x0U,
44 BIT_SET = 0x1U,
45 } bit_status_t;
46
47 typedef enum {
48 DISABLE = 0x0U,
49 ENABLE = 0x1U,
50 } type_func_t;
51 #define IS_FUNC_STATE(x) (((x) == DISABLE) || ((x) == ENABLE))
52
53 typedef enum {
54 FALSE = 0x0U,
55 TRUE = 0x1U,
56 } type_bool_t;
57
58 typedef enum {
59 UNLOCK = 0x0U,
60 LOCK = 0x1U,
61 } lock_state_t;
62 #define IS_LOCK_STATE(x) (((x) == UNLOCK) || ((x) == LOCK))
63
64
65 #define BIT(x) ((1U << (x)))
66 #define BITS(s, e) ((0xffffffffU << (s)) & (0xffffffffU >> (31 - (e))))
67 #define SET_BIT(reg, bit) ((reg) |= (bit))
68 #define CLEAR_BIT(reg, bit) ((reg) &= ~(bit))
69 #define READ_BIT(reg, bit) ((reg) & (bit))
70 #define READ_BITS(reg, msk, s) (((reg) & (msk)) >> (s))
71 #define CLEAR_REG(reg) ((reg) = (0x0))
72 #define WRITE_REG(reg, val) ((reg) = (val))
73 #define READ_REG(reg) ((reg))
74 #define MODIFY_REG(reg, clearmask, setmask) \
75 WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask)))
76 #define UNUSED(x) ((void)(x))
77
78 #ifdef USE_ASSERT
79 #define assert_param(x) \
80 do { \
81 if (!(x)) { \
82 __disable_irq(); \
83 while (1) \
84 ; \
85 } \
86 } while (0)
87 #else
88 #define assert_param(x)
89 #endif
90
91
92 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /* PER base address */
93 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /* RAM base address */
94 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /* Peripheral Address Space bit-band area */
95 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /* SRAM Address Space bit-band area */
96
97 __STATIC_INLINE__ void BITBAND_PER(volatile uint32_t *addr, uint32_t bit, uint32_t val)
98 {
99 uint32_t tmp = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) << 5) + (bit << 2);
100 *((volatile uint32_t *)tmp) = (uint32_t)val;
101 }
102
103 __STATIC_INLINE__ void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val)
104 {
105 uint32_t tmp = BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) << 5) + (bit << 2);
106 *((volatile uint32_t *)tmp) = (uint32_t)val;
107 }
108
109 #if defined ( __GNUC__ )
110 #ifndef __weak
111 #define __weak __attribute__((weak))
112 #endif /* __weak */
113 #ifndef __packed
114 #define __packed __attribute__((__packed__))
115 #endif /* __packed */
116 #endif /* __GNUC__ */
117
118 #ifdef __cplusplus
119 }
120 #endif /* __cplusplus */
121
122 #endif /* __TYPE_H__ */
ENABLE
Definition: type.h:49
FALSE
Definition: type.h:54
SET
Definition: type.h:39
LOCK
Definition: type.h:60
type_func_t
type_func_t
Definition: type.h:47
type_bool_t
type_bool_t
Definition: type.h:53
DISABLE
Definition: type.h:48
BITBAND_PER
__STATIC_INLINE__ void BITBAND_PER(volatile uint32_t *addr, uint32_t bit, uint32_t val)
Definition: type.h:97
UNLOCK
Definition: type.h:59
RESET
Definition: type.h:38
TRUE
Definition: type.h:55
it_status_t
enum flag_status_t it_status_t
__STATIC_INLINE__
#define __STATIC_INLINE__
Definition: type.h:32
lock_state_t
lock_state_t
Definition: type.h:58
PER_MEM_BASE
#define PER_MEM_BASE
Definition: type.h:92
BITBAND_SRAM
__STATIC_INLINE__ void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val)
Definition: type.h:103
flag_status_t
flag_status_t
Definition: type.h:37
BIT_RESET
Definition: type.h:43
BITBAND_PER_BASE
#define BITBAND_PER_BASE
Definition: type.h:94
BITBAND_RAM_BASE
#define BITBAND_RAM_BASE
Definition: type.h:95
bit_status_t
bit_status_t
Definition: type.h:42
RAM_MEM_BASE
#define RAM_MEM_BASE
Definition: type.h:93
BIT_SET
Definition: type.h:44


ALD User Manual: D:/svn/src/utils.c Source File

  • D:
  • svn
  • src
utils.c
Go to the documentation of this file.
1
17 #include <string.h>
18 #include "utils.h"
19 #include "ald_dma.h"
20 #include "ald_cmu.h"
21
22
41 #define __ALD_VERSION_MAIN (0x01)
42 #define __ALD_VERSION_SUB1 (0x00)
43 #define __ALD_VERSION_SUB2 (0x00)
44 #define __ALD_VERSION_RC (0x00)
45 #define __ALD_VERSION ((__ALD_VERSION_MAIN << 24) | \
46 (__ALD_VERSION_SUB1 << 16) | \
47 (__ALD_VERSION_SUB2 << 8 ) | \
48 (__ALD_VERSION_RC))
49
58 static __IO uint32_t lib_tick;
59 uint32_t __systick_interval = SYSTICK_INTERVAL_1MS;
112 void ald_cmu_init(void)
113 {
114 NVIC_SetPriorityGrouping(NVIC_PRIORITY_GROUP_2);
115 ald_cmu_clock_config_default();
116 ald_tick_init(TICK_INT_PRIORITY);
117 #ifdef ALD_DMA
118 ald_cmu_perh_clock_config(CMU_PERH_DMA, ENABLE);
119 ald_dma_init(DMA0);
120 #endif
121 return;
122 }
123
138 __weak void ald_tick_init(uint32_t prio)
139 {
140 /* Configure the SysTick IRQ */
141 NVIC_SetPriority(SysTick_IRQn, prio);
142 SysTick_Config(ald_cmu_get_sys_clock() / SYSTICK_INTERVAL_1MS);
143
144 return;
145 }
146
156 void ald_systick_interval_select(systick_interval_t value)
157 {
158 assert_param(IS_SYSTICK_INTERVAL(value));
159
160 SysTick_Config(ald_cmu_get_sys_clock() / value);
161 __systick_interval = value;
162
163 if (TICK_INT_PRIORITY != 15)
164 NVIC_SetPriority(SysTick_IRQn, TICK_INT_PRIORITY);
165
166 return;
167 }
204 __weak void ald_systick_irq_cbk(void)
205 {
206 /* do nothing */
207 return;
208 }
209
219 __weak void ald_inc_tick(void)
220 {
221 ++lib_tick;
222 ald_systick_irq_cbk();
223 }
224
231 __weak uint32_t ald_get_tick(void)
232 {
233 return lib_tick;
234 }
235
247 __weak void ald_delay_ms(__IO uint32_t delay)
248 {
249 uint32_t tick, __delay;
250
251 switch (__systick_interval) {
252 case SYSTICK_INTERVAL_1MS:
253 __delay = delay;
254 break;
255
256 case SYSTICK_INTERVAL_10MS:
257 __delay = delay / 10;
258 break;
259
260 case SYSTICK_INTERVAL_100MS:
261 __delay = delay / 100;
262 break;
263
264 case SYSTICK_INTERVAL_1000MS:
265 __delay = delay / 1000;
266 break;
267
268 default:
269 __delay = delay;
270 break;
271 }
272
273 tick = ald_get_tick();
274 __delay = __delay == 0 ? 1 : __delay;
275
276 while ((ald_get_tick() - tick) < __delay)
277 ;
278 }
279
290 __weak void ald_suspend_tick(void)
291 {
292 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
293 }
294
305 __weak void ald_resume_tick(void)
306 {
307 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
308 }
309
314 uint32_t ald_get_ald_version(void)
315 {
316 return __ALD_VERSION;
317 }
318
324 void ald_flash_wait_config(uint8_t cycle)
325 {
326 uint32_t tmp;
327
328 tmp = MSC->MEMWAIT;
329 MODIFY_REG(tmp, MSC_MEMWAIT_FLASH_W_MSK, (0x30U | cycle) << MSC_MEMWAIT_FLASH_W_POSS);
330 MSC->MEMWAIT = tmp;
331
332 return;
333 }
334
343 ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout)
344 {
345 uint32_t tick = ald_get_tick();
346
347 assert_param(timeout > 0);
348
349 if (status == SET) {
350 while (!(IS_BIT_SET(*reg, bit))) {
351 if (((ald_get_tick()) - tick) > timeout)
352 return TIMEOUT;
353 }
354 }
355 else {
356 while ((IS_BIT_SET(*reg, bit))) {
357 if (((ald_get_tick()) - tick) > timeout)
358 return TIMEOUT;
359 }
360 }
361
362 return OK;
363 }
364
375 void ald_mcu_irq_config(IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, type_func_t status)
376 {
377 uint32_t pri;
378 uint8_t sub_bw, pre_bw;
379 uint8_t sub_mask = 0xF;
380
381 assert_param(IS_FUNC_STATE(status));
382 assert_param(IS_PREEMPT_PRIO(preempt_prio));
383 assert_param(IS_SUB_PRIO(sub_prio));
384
385 if (status == ENABLE) {
386 pre_bw = 7 - (((SCB->AIRCR) >> 8) & 7);
387 sub_bw = 4 - pre_bw;
388 sub_mask >>= pre_bw;
389
390 pri = preempt_prio << sub_bw;
391 pri |= sub_prio & sub_mask;
392
393 NVIC_SetPriority(irq, pri);
394 NVIC_EnableIRQ(irq);
395 }
396 else {
397 NVIC_DisableIRQ(irq);
398 }
399
400 return;
401 }
402
407 void ald_mcu_timestamp_init(void)
408 {
409 DEM_CR |= (uint32_t)DEM_CR_TRCENA;
410 DWT_CYCCNT = 0x0;
411 DWT_CR |= (uint32_t)DWT_CR_CYCCNTEA;
412
413 return;
414 }
415
420 uint32_t ald_mcu_get_timestamp(void)
421 {
422 return (uint32_t)DWT_CYCCNT;
423 }
424
429 uint32_t ald_mcu_get_cpu_id(void)
430 {
431 return SCB->CPUID;
432 }
433
439 void ald_mcu_get_uid(uint8_t *buf)
440 {
441 memcpy(&buf[0], (void *)MCU_UID0_ADDR, 4);
442 memcpy(&buf[4], (void *)MCU_UID1_ADDR, 4);
443 memcpy(&buf[8], (void *)MCU_UID2_ADDR, 4);
444
445 return;
446 }
447
452 uint32_t ald_mcu_get_chipid(void)
453 {
454 return (uint32_t)*(uint32_t *)MCU_CHIPID_ADDR;
455 }
ENABLE
Definition: type.h:49
OK
Definition: utils.h:55
ald_cmu_init
void ald_cmu_init(void)
This function Configures time base source, NVIC and DMA.
Definition: utils.c:112
ald_wait_flag
ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout)
Waiting the specified bit in the register change to SET/RESET.
Definition: utils.c:343
CLEAR_BIT
#define CLEAR_BIT(reg, bit)
Definition: type.h:68
assert_param
#define assert_param(x)
Definition: type.h:88
ald_dma_init
void ald_dma_init(DMA_TypeDef *DMAx)
DMA module initialization, this function is invoked by ald_cmu_init().
Definition: ald_dma.c:270
SET
Definition: type.h:39
ald_mcu_get_uid
void ald_mcu_get_uid(uint8_t *buf)
Get the UID.
Definition: utils.c:439
type_func_t
type_func_t
Definition: type.h:47
DWT_CR
#define DWT_CR
Definition: utils.h:121
SYSTICK_INTERVAL_10MS
Definition: utils.h:77
ald_suspend_tick
__weak void ald_suspend_tick(void)
Suspend Tick increment.
Definition: utils.c:290
ald_systick_interval_select
void ald_systick_interval_select(systick_interval_t value)
Selects the interval of systick interrupt.
Definition: utils.c:156
ald_mcu_get_chipid
uint32_t ald_mcu_get_chipid(void)
Get the CHIPID.
Definition: utils.c:452
ald_mcu_get_timestamp
uint32_t ald_mcu_get_timestamp(void)
Get core timestamp.
Definition: utils.c:420
lib_tick
static __IO uint32_t lib_tick
lib_tick: Increase by one millisecond
Definition: utils.c:58
ald_cmu_get_sys_clock
uint32_t ald_cmu_get_sys_clock(void)
Get SYS clock.
Definition: ald_cmu.c:616
ald_cmu_clock_config_default
ald_status_t ald_cmu_clock_config_default(void)
Configure system clock using default. Select CMU_CLOCK_HRC(24MHz) as system clock and enable CMU_CLOC...
Definition: ald_cmu.c:263
IS_BIT_SET
#define IS_BIT_SET(reg, bit)
Definition: utils.h:89
ald_systick_irq_cbk
__weak void ald_systick_irq_cbk(void)
This function invoked by Systick ISR.
Definition: utils.c:204
SYSTICK_INTERVAL_1MS
Definition: utils.h:76
SYSTICK_INTERVAL_100MS
Definition: utils.h:78
MCU_UID2_ADDR
#define MCU_UID2_ADDR
Definition: utils.h:119
utils.h
This file contains the Utilities functions/types for the driver.
systick_interval_t
systick_interval_t
SysTick interval definition.
Definition: utils.h:75
ald_tick_init
__weak void ald_tick_init(uint32_t prio)
This function configures the source of the time base. The time source is configured to have 1ms time ...
Definition: utils.c:138
MCU_CHIPID_ADDR
#define MCU_CHIPID_ADDR
Definition: utils.h:120
__systick_interval
uint32_t __systick_interval
SysTick interval.
Definition: utils.c:59
NVIC_PRIORITY_GROUP_2
Definition: utils.h:67
ald_mcu_irq_config
void ald_mcu_irq_config(IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, type_func_t status)
Configure interrupt.
Definition: utils.c:375
DEM_CR_TRCENA
#define DEM_CR_TRCENA
Definition: utils.h:124
ald_cmu.h
Header file of CMU module driver.
ald_dma.h
DMA module Library.
DWT_CYCCNT
#define DWT_CYCCNT
Definition: utils.h:122
DWT_CR_CYCCNTEA
#define DWT_CR_CYCCNTEA
Definition: utils.h:125
ald_mcu_get_cpu_id
uint32_t ald_mcu_get_cpu_id(void)
Get the CPU ID.
Definition: utils.c:429
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
DEM_CR
#define DEM_CR
Definition: utils.h:123
SET_BIT
#define SET_BIT(reg, bit)
Definition: type.h:67
SYSTICK_INTERVAL_1000MS
Definition: utils.h:79
IS_SYSTICK_INTERVAL
#define IS_SYSTICK_INTERVAL(x)
Definition: utils.h:128
ald_flash_wait_config
void ald_flash_wait_config(uint8_t cycle)
Configure the flash wait period.
Definition: utils.c:324
ald_resume_tick
__weak void ald_resume_tick(void)
Resume Tick increment.
Definition: utils.c:305
IS_SUB_PRIO
#define IS_SUB_PRIO(x)
Definition: utils.h:127
MCU_UID1_ADDR
#define MCU_UID1_ADDR
Definition: utils.h:118
ald_get_ald_version
uint32_t ald_get_ald_version(void)
This method returns the ALD revision.
Definition: utils.c:314
IS_PREEMPT_PRIO
#define IS_PREEMPT_PRIO(x)
Definition: utils.h:126
CMU_PERH_DMA
Definition: ald_cmu.h:417
flag_status_t
flag_status_t
Definition: type.h:37
ald_delay_ms
__weak void ald_delay_ms(__IO uint32_t delay)
This function provides accurate delay (in milliseconds) based on variable incremented.
Definition: utils.c:247
ald_mcu_timestamp_init
void ald_mcu_timestamp_init(void)
Initialize core timestamp.
Definition: utils.c:407
MODIFY_REG
#define MODIFY_REG(reg, clearmask, setmask)
Definition: type.h:74
__ALD_VERSION
#define __ALD_VERSION
Definition: utils.c:45
MCU_UID0_ADDR
#define MCU_UID0_ADDR
Definition: utils.h:117
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
TICK_INT_PRIORITY
#define TICK_INT_PRIORITY
Definition: ald_conf.h:62
IS_FUNC_STATE
#define IS_FUNC_STATE(x)
Definition: ald_wdt.h:73
ald_cmu_perh_clock_config
void ald_cmu_perh_clock_config(cmu_perh_t perh, type_func_t status)
Enable/Disable peripheral clock.
Definition: ald_cmu.c:1071
ald_inc_tick
__weak void ald_inc_tick(void)
This function is called to increment a global variable "lib_tick" used as application time base...
Definition: utils.c:219


ALD User Manual: D:/svn/src/utils.h Source File

  • D:
  • svn
  • src
utils.h
Go to the documentation of this file.
1
17 #ifndef __UTILS_H__
18 #define __UTILS_H__
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 #include <stdlib.h>
25 #include "ald_conf.h"
26 #include "type.h"
27 #ifdef ES32F36xx
28 #include "es32f36xx.h"
29 #elif ES32F39xx
30 #include "es32f39xx.h"
31 #elif ES32F336x
32 #include "es32f336x.h"
33 #endif
34
49 extern uint32_t __systick_interval;
50
54 typedef enum {
55 OK = 0x0U,
56 ERROR = 0x1U,
57 BUSY = 0x2U,
58 TIMEOUT = 0x3U,
59 } ald_status_t;
60
64 typedef enum {
65 NVIC_PRIORITY_GROUP_0 = 0x7U,
66 NVIC_PRIORITY_GROUP_1 = 0x6U,
67 NVIC_PRIORITY_GROUP_2 = 0x5U,
68 NVIC_PRIORITY_GROUP_3 = 0x4U,
69 NVIC_PRIORITY_GROUP_4 = 0x3U,
70 } nvic_priority_group_t;
71
75 typedef enum {
76 SYSTICK_INTERVAL_1MS = 1000U,
77 SYSTICK_INTERVAL_10MS = 100U,
78 SYSTICK_INTERVAL_100MS = 10U,
79 SYSTICK_INTERVAL_1000MS = 1U,
80 } systick_interval_t;
88 #define ALD_MAX_DELAY 0xFFFFFFFFU
89 #define IS_BIT_SET(reg, bit) (((reg) & (bit)) != RESET)
90 #define IS_BIT_CLR(reg, bit) (((reg) & (bit)) == RESET)
91 #define RESET_HANDLE_STATE(x) ((x)->state = 0)
92 #define __LOCK(x) \
93 do { \
94 if ((x)->lock == LOCK) { \
95 return BUSY; \
96 } \
97 else { \
98 (x)->lock = LOCK; \
99 } \
100 } while (0)
101 #define __UNLOCK(x) \
102 do { \
103 (x)->lock = UNLOCK; \
104 } while (0)
105 #define ALD_PANIC() \
106 do { \
107 while (1) \
108 ; \
109 } while (0)
110
117 #define MCU_UID0_ADDR 0x000803E0U
118 #define MCU_UID1_ADDR 0x000803E8U
119 #define MCU_UID2_ADDR 0x000803F0U
120 #define MCU_CHIPID_ADDR 0x000803F8U
121 #define DWT_CR *(uint32_t *)0xE0001000U
122 #define DWT_CYCCNT *(volatile uint32_t *)0xE0001004U
123 #define DEM_CR *(uint32_t *)0xE000EDFCU
124 #define DEM_CR_TRCENA (1U << 24)
125 #define DWT_CR_CYCCNTEA (1U << 0)
126 #define IS_PREEMPT_PRIO(x) ((x) < 16)
127 #define IS_SUB_PRIO(x) ((x) < 16)
128 #define IS_SYSTICK_INTERVAL(x) (((x) == SYSTICK_INTERVAL_1MS) || \
129 ((x) == SYSTICK_INTERVAL_10MS) || \
130 ((x) == SYSTICK_INTERVAL_100MS) || \
131 ((x) == SYSTICK_INTERVAL_1000MS))
132
144 /* Initialization functions */
145 void ald_cmu_init(void);
146 void ald_tick_init(uint32_t prio);
147 void ald_systick_interval_select(systick_interval_t value);
148
156 /* Peripheral Control functions */
157 void ald_inc_tick(void);
158 void ald_systick_irq_cbk(void);
159 void ald_delay_ms(__IO uint32_t delay);
160 uint32_t ald_get_tick(void);
161 void ald_suspend_tick(void);
162 void ald_resume_tick(void);
163 uint32_t ald_get_ald_version(void);
164 void ald_flash_wait_config(uint8_t cycle);
165 ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout);
166 void ald_mcu_irq_config(IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, type_func_t status);
167 void ald_mcu_timestamp_init(void);
168 uint32_t ald_mcu_get_timestamp(void);
169 uint32_t ald_mcu_get_cpu_id(void);
170 void ald_mcu_get_uid(uint8_t *buf);
171 uint32_t ald_mcu_get_chipid(void);
188 #ifdef __cplusplus
189 }
190 #endif
191
192 #endif /* __UTILS_H__ */
nvic_priority_group_t
nvic_priority_group_t
NVIC Preemption Priority Group.
Definition: utils.h:64
OK
Definition: utils.h:55
ald_cmu_init
void ald_cmu_init(void)
This function Configures time base source, NVIC and DMA.
Definition: utils.c:112
NVIC_PRIORITY_GROUP_4
Definition: utils.h:69
ald_wait_flag
ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout)
Waiting the specified bit in the register change to SET/RESET.
Definition: utils.c:343
BUSY
Definition: utils.h:57
NVIC_PRIORITY_GROUP_0
Definition: utils.h:65
ald_mcu_get_uid
void ald_mcu_get_uid(uint8_t *buf)
Get the UID.
Definition: utils.c:439
type_func_t
type_func_t
Definition: type.h:47
SYSTICK_INTERVAL_10MS
Definition: utils.h:77
ald_suspend_tick
__weak void ald_suspend_tick(void)
Suspend Tick increment.
Definition: utils.c:290
ald_systick_interval_select
void ald_systick_interval_select(systick_interval_t value)
Selects the interval of systick interrupt.
Definition: utils.c:156
ald_mcu_get_chipid
uint32_t ald_mcu_get_chipid(void)
Get the CHIPID.
Definition: utils.c:452
__systick_interval
uint32_t __systick_interval
SysTick interval.
Definition: utils.c:59
ald_mcu_get_timestamp
uint32_t ald_mcu_get_timestamp(void)
Get core timestamp.
Definition: utils.c:420
ald_systick_irq_cbk
__weak void ald_systick_irq_cbk(void)
This function invoked by Systick ISR.
Definition: utils.c:204
SYSTICK_INTERVAL_1MS
Definition: utils.h:76
SYSTICK_INTERVAL_100MS
Definition: utils.h:78
ald_conf.h
Enable/Disable the peripheral module.
systick_interval_t
systick_interval_t
SysTick interval definition.
Definition: utils.h:75
ald_tick_init
__weak void ald_tick_init(uint32_t prio)
This function configures the source of the time base. The time source is configured to have 1ms time ...
Definition: utils.c:138
NVIC_PRIORITY_GROUP_2
Definition: utils.h:67
ald_mcu_irq_config
void ald_mcu_irq_config(IRQn_Type irq, uint8_t preempt_prio, uint8_t sub_prio, type_func_t status)
Configure interrupt.
Definition: utils.c:375
NVIC_PRIORITY_GROUP_1
Definition: utils.h:66
ald_mcu_get_cpu_id
uint32_t ald_mcu_get_cpu_id(void)
Get the CPU ID.
Definition: utils.c:429
ald_get_tick
__weak uint32_t ald_get_tick(void)
Provides a tick value in millisecond.
Definition: utils.c:231
TIMEOUT
Definition: utils.h:58
SYSTICK_INTERVAL_1000MS
Definition: utils.h:79
ald_flash_wait_config
void ald_flash_wait_config(uint8_t cycle)
Configure the flash wait period.
Definition: utils.c:324
ald_resume_tick
__weak void ald_resume_tick(void)
Resume Tick increment.
Definition: utils.c:305
ald_get_ald_version
uint32_t ald_get_ald_version(void)
This method returns the ALD revision.
Definition: utils.c:314
NVIC_PRIORITY_GROUP_3
Definition: utils.h:68
flag_status_t
flag_status_t
Definition: type.h:37
ald_delay_ms
__weak void ald_delay_ms(__IO uint32_t delay)
This function provides accurate delay (in milliseconds) based on variable incremented.
Definition: utils.c:247
ald_mcu_timestamp_init
void ald_mcu_timestamp_init(void)
Initialize core timestamp.
Definition: utils.c:407
ald_status_t
ald_status_t
ALD Status structures definition.
Definition: utils.h:54
ERROR
Definition: utils.h:56
type.h
define type
ald_inc_tick
__weak void ald_inc_tick(void)
This function is called to increment a global variable "lib_tick" used as application time base...
Definition: utils.c:219